cortex-m85: Add Task Dedicated PAC Key example

CORTEX_M85_TASK_DEDICATED_PAC_KEY_FVP_ARMCLANG/CMSIS/CMakeLists.txt

@@ -0,0 +1,67 @@
+# Copyright 2023-2024 Arm Limited and/or its affiliates
+# <[email protected]>
+# SPDX-License-Identifier: Apache-2.0
+
+set(arm_corstone_platform_bsp_SOURCE_DIR
+    ${CMAKE_CURRENT_LIST_DIR}/../../Demos_Dependencies/arm_corstone_platform_bsp
+    CACHE INTERNAL
+    "Path to Arm Corstone-3xx Platform CMSIS-Driver Based Board Support Package source code"
+)
+
+set(ARM_CORSTONE_BSP_TARGET_PLATFORM "corstone315" CACHE STRING "")
+
+add_subdirectory(${arm_corstone_platform_bsp_SOURCE_DIR} build)
+
+if(FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG STREQUAL "ARM_V_8_1_M_PACBTI_CONFIG_STANDARD")
+    target_compile_options(arm-corstone-platform-bsp
+        PUBLIC
+            -mbranch-protection=standard
+    )
+elseif(FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG STREQUAL "ARM_V_8_1_M_PACBTI_CONFIG_PACRET_LEAF_BTI")
+    target_compile_options(arm-corstone-platform-bsp
+        PUBLIC
+            -mbranch-protection=bti+pac-ret+leaf
+    )
+elseif(FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG STREQUAL "ARM_V_8_1_M_PACBTI_CONFIG_PACRET")
+    target_compile_options(arm-corstone-platform-bsp
+        PUBLIC
+            -mbranch-protection=pac-ret
+    )
+elseif(FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG STREQUAL "ARM_V_8_1_M_PACBTI_CONFIG_PACRET_LEAF")
+    target_compile_options(arm-corstone-platform-bsp
+        PUBLIC
+            -mbranch-protection=pac-ret+leaf
+    )
+elseif(FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG STREQUAL "ARM_V_8_1_M_PACBTI_CONFIG_BTI")
+    target_compile_options(arm-corstone-platform-bsp
+        PUBLIC
+            -mbranch-protection=bti
+    )
+elseif(FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG STREQUAL "ARM_V_8_1_M_PACBTI_CONFIG_NONE")
+    target_compile_options(arm-corstone-platform-bsp
+        PUBLIC
+            -mbranch-protection=none
+    )
+else()
+	message(FATAL_ERROR "Invalid FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG option chosen, the supported configurations are
+	ARM_V_8_1_M_PACBTI_CONFIG_STANDARD,
+	ARM_V_8_1_M_PACBTI_CONFIG_PACRET_LEAF_BTI,
+	ARM_V_8_1_M_PACBTI_CONFIG_PACRET,
+	ARM_V_8_1_M_PACBTI_CONFIG_PACRET_LEAF,
+	ARM_V_8_1_M_PACBTI_CONFIG_BTI,
+	ARM_V_8_1_M_PACBTI_CONFIG_NONE"
+    )
+endif()
+
+target_compile_definitions(arm-corstone-platform-bsp
+    INTERFACE
+        __DOMAIN_NS=1
+)
+
+set(S_IMAGE_LOAD_ADDRESS  0x11000000 CACHE STRING "Secure firmware loading address")
+set(NS_IMAGE_LOAD_ADDRESS 0x01020000 CACHE STRING "Non-secure user application loading address")
+
+target_include_directories(arm-corstone-platform-bsp
+    PUBLIC
+        ${CMAKE_CURRENT_LIST_DIR}/corstone315/include
+)

CORTEX_M85_TASK_DEDICATED_PAC_KEY_FVP_ARMCLANG/CMSIS/common/bsp_serial.c

@@ -0,0 +1,56 @@
+/* Copyright 2017-2024 Arm Limited and/or its affiliates
+ * <[email protected]>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include "device_cfg.h"
+#include "Driver_USART.h"
+#include "bsp_serial.h"
+
+extern ARM_DRIVER_USART Driver_USART0;
+
+void bsp_serial_init( void )
+{
+    Driver_USART0.Initialize( NULL );
+
+    Driver_USART0.PowerControl( ARM_POWER_FULL );
+
+    Driver_USART0.Control( ARM_USART_MODE_ASYNCHRONOUS, DEFAULT_UART_BAUDRATE );
+
+    Driver_USART0.Control( ARM_USART_CONTROL_TX, 1 );
+
+    Driver_USART0.Control( ARM_USART_CONTROL_RX, 1 );
+}
+
+#if defined( __ARMCOMPILER_VERSION )
+
+    int stdio_output_string(const unsigned char *str, uint32_t len)
+    {
+        int32_t ret;
+
+        /* Add a busy wait before sending. */
+        while (Driver_USART0.GetStatus().tx_busy);
+        ret = Driver_USART0.Send(str, len);
+        if (ret != ARM_DRIVER_OK) {
+            return 0;
+        }
+        /* Add a busy wait after sending. */
+        while (Driver_USART0.GetStatus().tx_busy);
+
+        return Driver_USART0.GetTxCount();
+    }
+
+    int fputc(int ch, FILE *f)
+    {
+        (void)f;
+
+        /* Send byte to USART */
+        (void)stdio_output_string((const unsigned char *)&ch, 1);
+
+        /* Return character written */
+        return ch;
+    }
+
+#endif /* if defined( __ARMCOMPILER_VERSION ) */

CORTEX_M85_TASK_DEDICATED_PAC_KEY_FVP_ARMCLANG/CMSIS/common/bsp_serial.h

@@ -0,0 +1,17 @@
+/* Copyright 2017-2024 Arm Limited and/or its affiliates
+ * <[email protected]>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __SERIAL_H__
+#define __SERIAL_H__
+
+
+#include <stddef.h>
+
+/**
+ * \brief Initializes default UART device
+ */
+void bsp_serial_init( void );
+
+#endif /* __SERIAL_H__ */

CORTEX_M85_TASK_DEDICATED_PAC_KEY_FVP_ARMCLANG/CMSIS/corstone315/include/RTE_Components.h

@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2019-2024, Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- */
+
+#ifndef __RTE_COMPONENTS_H
+#define __RTE_COMPONENTS_H
+
+/* <q> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0] */
+/* <i> Configuration settings for Driver_USART0 in component ::Drivers:USART */
+#define   RTE_USART0     1
+#define   RTE_SRAM_MPC   1
+#define   RTE_ISRAM0_MPC 1
+#define   RTE_PERIPH_EXP2_PPC_CORSTONE315 1
+#endif /* __RTE_COMPONENTS_H */