Upgrade to Quartus 18.0

Feuerwerk · Jul 20, 2018 · a6ce5c4 · a6ce5c4
1 parent facaec6
commit a6ce5c4
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Showing 64 changed files with 151 additions and 151 deletions.
diff --git a/audio_pll.bsf b/audio_pll.bsf
@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
 the Block Editor! File corruption is VERY likely to occur.
 */
 /*
-Copyright (C) 2017  Intel Corporation. All rights reserved.
+Copyright (C) 2018  Intel Corporation. All rights reserved.
 Your use of Intel Corporation's design tools, logic functions 
 and other software and tools, and its AMPP partner logic 
 functions, and any output files from any of the foregoing 

diff --git a/audio_pll.qip b/audio_pll.qip
@@ -1,25 +1,25 @@
 set_global_assignment -entity "audio_pll" -library "audio_pll" -name IP_TOOL_NAME "altera_pll"
-set_global_assignment -entity "audio_pll" -library "audio_pll" -name IP_TOOL_VERSION "17.1"
+set_global_assignment -entity "audio_pll" -library "audio_pll" -name IP_TOOL_VERSION "18.0"
 set_global_assignment -entity "audio_pll" -library "audio_pll" -name IP_TOOL_ENV "mwpim"
 set_global_assignment -library "audio_pll" -name MISC_FILE [file join $::quartus(qip_path) "audio_pll.cmp"]
 set_global_assignment -entity "audio_pll" -library "audio_pll" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
 set_global_assignment -entity "audio_pll" -library "audio_pll" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
 set_global_assignment -entity "audio_pll" -library "audio_pll" -name IP_QSYS_MODE "UNKNOWN"
 set_global_assignment -name SYNTHESIS_ONLY_QIP ON
 set_global_assignment -entity "audio_pll" -library "audio_pll" -name IP_COMPONENT_NAME "YXVkaW9fcGxs"
-set_global_assignment -entity "audio_pll" -library "audio_pll" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
+set_global_assignment -entity "audio_pll" -library "audio_pll" -name IP_COMPONENT_DISPLAY_NAME "UExMIEludGVsIEZQR0EgSVA="
 set_global_assignment -entity "audio_pll" -library "audio_pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
 set_global_assignment -entity "audio_pll" -library "audio_pll" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "audio_pll" -library "audio_pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
-set_global_assignment -entity "audio_pll" -library "audio_pll" -name IP_COMPONENT_VERSION "MTcuMQ=="
-set_global_assignment -entity "audio_pll" -library "audio_pll" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
+set_global_assignment -entity "audio_pll" -library "audio_pll" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "audio_pll" -library "audio_pll" -name IP_COMPONENT_VERSION "MTguMA=="
+set_global_assignment -entity "audio_pll" -library "audio_pll" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A="
 set_global_assignment -entity "audio_pll_0002" -library "audio_pll" -name IP_COMPONENT_NAME "YXVkaW9fcGxsXzAwMDI="
-set_global_assignment -entity "audio_pll_0002" -library "audio_pll" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
+set_global_assignment -entity "audio_pll_0002" -library "audio_pll" -name IP_COMPONENT_DISPLAY_NAME "UExMIEludGVsIEZQR0EgSVA="
 set_global_assignment -entity "audio_pll_0002" -library "audio_pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
 set_global_assignment -entity "audio_pll_0002" -library "audio_pll" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "audio_pll_0002" -library "audio_pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
-set_global_assignment -entity "audio_pll_0002" -library "audio_pll" -name IP_COMPONENT_VERSION "MTcuMQ=="
-set_global_assignment -entity "audio_pll_0002" -library "audio_pll" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
+set_global_assignment -entity "audio_pll_0002" -library "audio_pll" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "audio_pll_0002" -library "audio_pll" -name IP_COMPONENT_VERSION "MTguMA=="
+set_global_assignment -entity "audio_pll_0002" -library "audio_pll" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A="
 set_global_assignment -entity "audio_pll_0002" -library "audio_pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0"
 set_global_assignment -entity "audio_pll_0002" -library "audio_pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k"
 set_global_assignment -entity "audio_pll_0002" -library "audio_pll" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::VW5rbm93bg==::ZGV2aWNl"
@@ -334,5 +334,5 @@ set_global_assignment -library "audio_pll" -name VERILOG_FILE [file join $::quar
 set_global_assignment -library "audio_pll" -name QIP_FILE [file join $::quartus(qip_path) "audio_pll/audio_pll_0002.qip"]
 
 set_global_assignment -entity "audio_pll_0002" -library "audio_pll" -name IP_TOOL_NAME "altera_pll"
-set_global_assignment -entity "audio_pll_0002" -library "audio_pll" -name IP_TOOL_VERSION "17.1"
+set_global_assignment -entity "audio_pll_0002" -library "audio_pll" -name IP_TOOL_VERSION "18.0"
 set_global_assignment -entity "audio_pll_0002" -library "audio_pll" -name IP_TOOL_ENV "mwpim"
diff --git a/audio_pll.sip b/audio_pll.sip
@@ -1,5 +1,5 @@
 set_global_assignment -entity "audio_pll" -library "lib_audio_pll" -name IP_TOOL_NAME "altera_pll"
-set_global_assignment -entity "audio_pll" -library "lib_audio_pll" -name IP_TOOL_VERSION "17.1"
+set_global_assignment -entity "audio_pll" -library "lib_audio_pll" -name IP_TOOL_VERSION "18.0"
 set_global_assignment -entity "audio_pll" -library "lib_audio_pll" -name IP_TOOL_ENV "mwpim"
 set_global_assignment -library "lib_audio_pll" -name SPD_FILE [file join $::quartus(sip_path) "audio_pll.spd"]
 

diff --git a/audio_pll.vhd b/audio_pll.vhd
@@ -1,8 +1,8 @@
--- megafunction wizard: %Altera PLL v17.1%
+-- megafunction wizard: %PLL Intel FPGA IP v18.0%
 -- GENERATION: XML
 -- audio_pll.vhd
 
--- Generated using ACDS version 17.1 590
+-- Generated using ACDS version 18.0 614
 
 library IEEE;
 use IEEE.std_logic_1164.all;
@@ -64,7 +64,7 @@ end architecture rtl; -- of audio_pll
 --	their respective licensors.  No other licenses, including any licenses
 --	needed under any third party's intellectual property, are provided herein.
 ---->
--- Retrieval info: <instance entity-name="altera_pll" version="17.1" >
+-- Retrieval info: <instance entity-name="altera_pll" version="18.0" >
 -- Retrieval info: 	<generic name="debug_print_output" value="false" />
 -- Retrieval info: 	<generic name="debug_use_rbc_taf_method" value="false" />
 -- Retrieval info: 	<generic name="device_family" value="Cyclone V" />

diff --git a/audio_pll_sim/aldec/rivierapro_setup.tcl b/audio_pll_sim/aldec/rivierapro_setup.tcl
@@ -12,7 +12,7 @@
 # or its authorized distributors. Please refer to the applicable 
 # agreement for further details.
 
-# ACDS 17.1 590 win32 2018.01.10.18:39:30
+# ACDS 18.0 614 win32 2018.07.18.19:32:54
 # ----------------------------------------
 # Auto-generated simulation script rivierapro_setup.tcl
 # ----------------------------------------
@@ -113,7 +113,7 @@ if ![info exists QSYS_SIMDIR] {
 }
 
 if ![info exists QUARTUS_INSTALL_DIR] { 
-  set QUARTUS_INSTALL_DIR "C:/intelfpga/17.1/quartus/"
+  set QUARTUS_INSTALL_DIR "C:/intelfpga/18.0/quartus/"
 }
 
 if ![info exists USER_DEFINED_COMPILE_OPTIONS] { 

diff --git a/audio_pll_sim/audio_pll.vho b/audio_pll_sim/audio_pll.vho
@@ -1,8 +1,8 @@
 --IP Functional Simulation Model
---VERSION_BEGIN 17.1 cbx_mgl 2017:10:25:18:08:29:SJ cbx_simgen 2017:10:25:18:06:53:SJ  VERSION_END
+--VERSION_BEGIN 18.0 cbx_mgl 2018:04:24:18:08:49:SJ cbx_simgen 2018:04:24:18:04:18:SJ  VERSION_END
 
 
--- Copyright (C) 2017  Intel Corporation. All rights reserved.
+-- Copyright (C) 2018  Intel Corporation. All rights reserved.
 -- Your use of Intel Corporation's design tools, logic functions 
 -- and other software and tools, and its AMPP partner logic 
 -- functions, and any output files from any of the foregoing 

diff --git a/audio_pll_sim/cadence/ncsim_setup.sh b/audio_pll_sim/cadence/ncsim_setup.sh
@@ -12,7 +12,7 @@
 # or its authorized distributors. Please refer to the applicable 
 # agreement for further details.
 
-# ACDS 17.1 590 win32 2018.01.10.18:39:30
+# ACDS 18.0 614 win32 2018.07.18.19:32:54
 
 # ----------------------------------------
 # ncsim - auto-generated simulation script
@@ -106,12 +106,12 @@
 # within the Quartus project, and generate a unified
 # script which supports all the Altera IP within the design.
 # ----------------------------------------
-# ACDS 17.1 590 win32 2018.01.10.18:39:30
+# ACDS 18.0 614 win32 2018.07.18.19:32:54
 # ----------------------------------------
 # initialize variables
 TOP_LEVEL_NAME="audio_pll"
 QSYS_SIMDIR="./../"
-QUARTUS_INSTALL_DIR="C:/intelfpga/17.1/quartus/"
+QUARTUS_INSTALL_DIR="C:/intelfpga/18.0/quartus/"
 SKIP_FILE_COPY=0
 SKIP_DEV_COM=0
 SKIP_COM=0

diff --git a/audio_pll_sim/mentor/msim_setup.tcl b/audio_pll_sim/mentor/msim_setup.tcl
@@ -94,7 +94,7 @@
 # within the Quartus project, and generate a unified
 # script which supports all the Altera IP within the design.
 # ----------------------------------------
-# ACDS 17.1 590 win32 2018.01.10.18:39:30
+# ACDS 18.0 614 win32 2018.07.18.19:32:54
 
 # ----------------------------------------
 # Initialize variables
@@ -113,7 +113,7 @@ if ![info exists QSYS_SIMDIR] {
 }
 
 if ![info exists QUARTUS_INSTALL_DIR] { 
-  set QUARTUS_INSTALL_DIR "C:/intelfpga/17.1/quartus/"
+  set QUARTUS_INSTALL_DIR "C:/intelfpga/18.0/quartus/"
 }
 
 if ![info exists USER_DEFINED_COMPILE_OPTIONS] { 

diff --git a/audio_pll_sim/synopsys/vcsmx/vcsmx_setup.sh b/audio_pll_sim/synopsys/vcsmx/vcsmx_setup.sh
@@ -12,7 +12,7 @@
 # or its authorized distributors. Please refer to the applicable 
 # agreement for further details.
 
-# ACDS 17.1 590 win32 2018.01.10.18:39:30
+# ACDS 18.0 614 win32 2018.07.18.19:32:54
 
 # ----------------------------------------
 # vcsmx - auto-generated simulation script
@@ -107,12 +107,12 @@
 # within the Quartus project, and generate a unified
 # script which supports all the Altera IP within the design.
 # ----------------------------------------
-# ACDS 17.1 590 win32 2018.01.10.18:39:30
+# ACDS 18.0 614 win32 2018.07.18.19:32:54
 # ----------------------------------------
 # initialize variables
 TOP_LEVEL_NAME="audio_pll"
 QSYS_SIMDIR="./../../"
-QUARTUS_INSTALL_DIR="C:/intelfpga/17.1/quartus/"
+QUARTUS_INSTALL_DIR="C:/intelfpga/18.0/quartus/"
 SKIP_FILE_COPY=0
 SKIP_DEV_COM=0
 SKIP_COM=0

diff --git a/datamem.cmp b/datamem.cmp
@@ -1,4 +1,4 @@
---Copyright (C) 2017  Intel Corporation. All rights reserved.
+--Copyright (C) 2018  Intel Corporation. All rights reserved.
 --Your use of Intel Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 

diff --git a/datamem.qip b/datamem.qip
@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
-set_global_assignment -name IP_TOOL_VERSION "17.1"
+set_global_assignment -name IP_TOOL_VERSION "18.0"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
 set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "datamem.vhd"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "datamem.cmp"]
diff --git a/datamem.vhd b/datamem.vhd
@@ -14,11 +14,11 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 17.1.0 Build 590 10/25/2017 SJ Lite Edition
+-- 18.0.0 Build 614 04/24/2018 SJ Lite Edition
 -- ************************************************************
 
 
---Copyright (C) 2017  Intel Corporation. All rights reserved.
+--Copyright (C) 2018  Intel Corporation. All rights reserved.
 --Your use of Intel Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 

diff --git a/frmmem.cmp b/frmmem.cmp
@@ -1,4 +1,4 @@
---Copyright (C) 2017  Intel Corporation. All rights reserved.
+--Copyright (C) 2018  Intel Corporation. All rights reserved.
 --Your use of Intel Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 

diff --git a/frmmem.qip b/frmmem.qip
@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
-set_global_assignment -name IP_TOOL_VERSION "17.1"
+set_global_assignment -name IP_TOOL_VERSION "18.0"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
 set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "frmmem.vhd"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "frmmem.cmp"]
diff --git a/frmmem.vhd b/frmmem.vhd
@@ -14,11 +14,11 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 17.1.0 Build 590 10/25/2017 SJ Lite Edition
+-- 18.0.0 Build 614 04/24/2018 SJ Lite Edition
 -- ************************************************************
 
 
---Copyright (C) 2017  Intel Corporation. All rights reserved.
+--Copyright (C) 2018  Intel Corporation. All rights reserved.
 --Your use of Intel Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 

diff --git a/master_pll.bsf b/master_pll.bsf
@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
 the Block Editor! File corruption is VERY likely to occur.
 */
 /*
-Copyright (C) 2017  Intel Corporation. All rights reserved.
+Copyright (C) 2018  Intel Corporation. All rights reserved.
 Your use of Intel Corporation's design tools, logic functions 
 and other software and tools, and its AMPP partner logic 
 functions, and any output files from any of the foregoing 

diff --git a/master_pll.qip b/master_pll.qip
@@ -1,25 +1,25 @@
 set_global_assignment -entity "master_pll" -library "master_pll" -name IP_TOOL_NAME "altera_pll"
-set_global_assignment -entity "master_pll" -library "master_pll" -name IP_TOOL_VERSION "17.1"
+set_global_assignment -entity "master_pll" -library "master_pll" -name IP_TOOL_VERSION "18.0"
 set_global_assignment -entity "master_pll" -library "master_pll" -name IP_TOOL_ENV "mwpim"
 set_global_assignment -library "master_pll" -name MISC_FILE [file join $::quartus(qip_path) "master_pll.cmp"]
 set_global_assignment -entity "master_pll" -library "master_pll" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
 set_global_assignment -entity "master_pll" -library "master_pll" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
 set_global_assignment -entity "master_pll" -library "master_pll" -name IP_QSYS_MODE "UNKNOWN"
 set_global_assignment -name SYNTHESIS_ONLY_QIP ON
 set_global_assignment -entity "master_pll" -library "master_pll" -name IP_COMPONENT_NAME "bWFzdGVyX3BsbA=="
-set_global_assignment -entity "master_pll" -library "master_pll" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
+set_global_assignment -entity "master_pll" -library "master_pll" -name IP_COMPONENT_DISPLAY_NAME "UExMIEludGVsIEZQR0EgSVA="
 set_global_assignment -entity "master_pll" -library "master_pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
 set_global_assignment -entity "master_pll" -library "master_pll" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "master_pll" -library "master_pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
-set_global_assignment -entity "master_pll" -library "master_pll" -name IP_COMPONENT_VERSION "MTcuMQ=="
-set_global_assignment -entity "master_pll" -library "master_pll" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
+set_global_assignment -entity "master_pll" -library "master_pll" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "master_pll" -library "master_pll" -name IP_COMPONENT_VERSION "MTguMA=="
+set_global_assignment -entity "master_pll" -library "master_pll" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A="
 set_global_assignment -entity "master_pll_0002" -library "master_pll" -name IP_COMPONENT_NAME "bWFzdGVyX3BsbF8wMDAy"
-set_global_assignment -entity "master_pll_0002" -library "master_pll" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
+set_global_assignment -entity "master_pll_0002" -library "master_pll" -name IP_COMPONENT_DISPLAY_NAME "UExMIEludGVsIEZQR0EgSVA="
 set_global_assignment -entity "master_pll_0002" -library "master_pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
 set_global_assignment -entity "master_pll_0002" -library "master_pll" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "master_pll_0002" -library "master_pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
-set_global_assignment -entity "master_pll_0002" -library "master_pll" -name IP_COMPONENT_VERSION "MTcuMQ=="
-set_global_assignment -entity "master_pll_0002" -library "master_pll" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
+set_global_assignment -entity "master_pll_0002" -library "master_pll" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "master_pll_0002" -library "master_pll" -name IP_COMPONENT_VERSION "MTguMA=="
+set_global_assignment -entity "master_pll_0002" -library "master_pll" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A="
 set_global_assignment -entity "master_pll_0002" -library "master_pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0"
 set_global_assignment -entity "master_pll_0002" -library "master_pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k"
 set_global_assignment -entity "master_pll_0002" -library "master_pll" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::VW5rbm93bg==::ZGV2aWNl"
@@ -480,5 +480,5 @@ set_global_assignment -library "master_pll" -name VERILOG_FILE [file join $::qua
 set_global_assignment -library "master_pll" -name QIP_FILE [file join $::quartus(qip_path) "master_pll/master_pll_0002.qip"]
 
 set_global_assignment -entity "master_pll_0002" -library "master_pll" -name IP_TOOL_NAME "altera_pll"
-set_global_assignment -entity "master_pll_0002" -library "master_pll" -name IP_TOOL_VERSION "17.1"
+set_global_assignment -entity "master_pll_0002" -library "master_pll" -name IP_TOOL_VERSION "18.0"
 set_global_assignment -entity "master_pll_0002" -library "master_pll" -name IP_TOOL_ENV "mwpim"
diff --git a/master_pll.sip b/master_pll.sip
@@ -1,5 +1,5 @@
 set_global_assignment -entity "master_pll" -library "lib_master_pll" -name IP_TOOL_NAME "altera_pll"
-set_global_assignment -entity "master_pll" -library "lib_master_pll" -name IP_TOOL_VERSION "17.1"
+set_global_assignment -entity "master_pll" -library "lib_master_pll" -name IP_TOOL_VERSION "18.0"
 set_global_assignment -entity "master_pll" -library "lib_master_pll" -name IP_TOOL_ENV "mwpim"
 set_global_assignment -library "lib_master_pll" -name SPD_FILE [file join $::quartus(sip_path) "master_pll.spd"]
 

diff --git a/master_pll.vhd b/master_pll.vhd
@@ -1,8 +1,8 @@
--- megafunction wizard: %Altera PLL v17.1%
+-- megafunction wizard: %PLL Intel FPGA IP v18.0%
 -- GENERATION: XML
 -- master_pll.vhd
 
--- Generated using ACDS version 17.1 590
+-- Generated using ACDS version 18.0 614
 
 library IEEE;
 use IEEE.std_logic_1164.all;
@@ -70,7 +70,7 @@ end architecture rtl; -- of master_pll
 --	their respective licensors.  No other licenses, including any licenses
 --	needed under any third party's intellectual property, are provided herein.
 ---->
--- Retrieval info: <instance entity-name="altera_pll" version="17.1" >
+-- Retrieval info: <instance entity-name="altera_pll" version="18.0" >
 -- Retrieval info: 	<generic name="debug_print_output" value="false" />
 -- Retrieval info: 	<generic name="debug_use_rbc_taf_method" value="false" />
 -- Retrieval info: 	<generic name="device_family" value="Cyclone V" />

diff --git a/master_pll_sim/aldec/rivierapro_setup.tcl b/master_pll_sim/aldec/rivierapro_setup.tcl
@@ -12,7 +12,7 @@
 # or its authorized distributors. Please refer to the applicable 
 # agreement for further details.
 
-# ACDS 17.1 590 win32 2018.01.10.18:38:59
+# ACDS 18.0 614 win32 2018.07.18.19:32:25
 # ----------------------------------------
 # Auto-generated simulation script rivierapro_setup.tcl
 # ----------------------------------------
@@ -113,7 +113,7 @@ if ![info exists QSYS_SIMDIR] {
 }
 
 if ![info exists QUARTUS_INSTALL_DIR] { 
-  set QUARTUS_INSTALL_DIR "C:/intelfpga/17.1/quartus/"
+  set QUARTUS_INSTALL_DIR "C:/intelfpga/18.0/quartus/"
 }
 
 if ![info exists USER_DEFINED_COMPILE_OPTIONS] {