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Digital watch with alarm clock and stop watch on a FPGA Artix-7 - VHDL Assignment 23/24

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bitstreams		bitstreams
ctr		ctr
sim		sim
src		src
ESQUEMA.jpg		ESQUEMA.jpg
README.md		README.md

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Trabajo-SED-VHDL

Trabajo-SED-VHDL

Sistemas Electrónicos Digitales
Trabajo VHDL
Curso 23/24
Placa de desarrollo: Nexys 4 DDR Artix-7

Pablo Nuñez Hernández (54773)
Sara de Vargas Muller (53919)
Andrés Fernández Muñoz (55237)

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Digital watch with alarm clock and stop watch on a FPGA Artix-7 - VHDL Assignment 23/24

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