Fixing non power of 2 mux generation

[KelvinChung2000]

Now can correctly generate non power of 2 mux.

 //switch matrix multiplexer E6BEG4 MUX-5
assign E6BEG4_input = {A_O,W6END3,WW4END3,W1END2,W1END0};
cus_mux81_buf inst_cus_mux81_buf_E6BEG4 (
    .A0(E6BEG4_input[0]),
    .A1(E6BEG4_input[1]),
    .A2(E6BEG4_input[2]),
    .A3(E6BEG4_input[3]),
    .A4(E6BEG4_input[4]),
    .A5(GND0),
    .A6(GND0),
    .A7(GND0),
    .S0(ConfigBits[76+0]),
    .S0N(ConfigBits_N[76+0]),
    .S1(ConfigBits[76+1]),
    .S1N(ConfigBits_N[76+1]),
    .S2(ConfigBits[76+2]),
    .S2N(ConfigBits_N[76+2]),
    .X(E6BEG4)
);

I have also updated the name of the my_mux2 to cus_mux21, to make them follow the same naming conversion for the other muxes.

[EverythingElseWasAlreadyTaken]

I've run some tests and the general output looks good.
I compared the default Fabric with the current dev branch, also looks good.

I currently try to run an equivalence check of the outputs with yosys, but this seems to run for a long time. But this is more out of curiosity and for future testing.

But there is one thing, it would be nice if you maybe squash your commits together and provide a meaningful commit message, why this was changed.
For changes like this, it could be good to know on a later point, why this was changed.

[KelvinChung2000]

The repo is default to squash and merge when merging which will use the pull request title as the commit message.

…

________________________________ From: Jonas K. ***@***.***> Sent: 30 October 2024 16:22 To: FPGA-Research-Manchester/FABulous ***@***.***> Cc: King Chung ***@***.***>; Author ***@***.***> Subject: Re: [FPGA-Research-Manchester/FABulous] Fixing non power of 2 mux generation (PR #242) @EverythingElseWasAlreadyTaken requested changes on this pull request. I've run some tests and the general output looks good. I compared the default Fabric with the current dev branch, also looks good. I currently try to run an equivalence check of the outputs with yosys, but this seems to run for a long time. But this is more out of curiosity and for future testing. But there is one thing, it would be nice if you maybe squash your commits together and provide a meaningful commit message, why this was changed. For changes like this, it could be good to know on a later point, why this was changed. — Reply to this email directly, view it on GitHub [github.com]<https://urldefense.com/v3/__https://github.com/FPGA-Research-Manchester/FABulous/pull/242*pullrequestreview-2405535288__;Iw!!PDiH4ENfjr2_Jw!AL5GKABU8rMkV2Dtn6dwXfyKdatHxtkh50mxBsYH1KgL40NpNhUciynSbI9Exa0x7L8RcPP3oaUHkw2cDFsn7qmb3WgQlvGX$>, or unsubscribe [github.com]<https://urldefense.com/v3/__https://github.com/notifications/unsubscribe-auth/AQF2K6P3MWWSTWKEZTKGMZ3Z6EBT7AVCNFSM6AAAAABQK6AGHGVHI2DSMVQWIX3LMV43YUDVNRWFEZLROVSXG5CSMV3GSZLXHMZDIMBVGUZTKMRYHA__;!!PDiH4ENfjr2_Jw!AL5GKABU8rMkV2Dtn6dwXfyKdatHxtkh50mxBsYH1KgL40NpNhUciynSbI9Exa0x7L8RcPP3oaUHkw2cDFsn7qmb3fwwynrf$>. You are receiving this because you authored the thread.Message ID: ***@***.***>

[EverythingElseWasAlreadyTaken]

The repo is default to squash and merge when merging which will use the pull request title as the commit message.

Sorry, I forgot about this feature!