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Refactor file path handling in fabric_gen.py using pathlib #171

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merged 2 commits into from
May 3, 2024
Merged

Refactor file path handling in fabric_gen.py using pathlib #171

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4c65802
Refactor file path handling in fabric_gen.py using pathlib
KelvinChung2000 May 3, 2024
51cbe56
clean up the debug print
KelvinChung2000 May 3, 2024
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60 changes: 27 additions & 33 deletions fabric_generator/fabric_gen.py
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Original file line number Diff line number Diff line change
Expand Up @@ -23,6 +23,7 @@
import csv
from typing import Dict, List, Tuple
import logging
from pathlib import Path


from fasm import * # Remove this line if you do not have the fasm library installed and will not be generating a bitstream
Expand Down Expand Up @@ -768,30 +769,26 @@ def generateTile(self, tile: Tile) -> None:

# insert switch matrix and config_mem component declaration
if isinstance(self.writer, VHDLWriter):
tileName = tile.name
subFolder = "."
if tile.partOfSuperTile:
tileName = tile.name.rsplit("_", 1)[0]
subFolder = tile.name

if os.path.exists(f"Tile/{tileName}/{subFolder}/{tile.name}_switch_matrix.vhdl"):
basePath = Path(self.writer.outFileName).parent

if os.path.exists(f"{basePath}/{tile.name}_switch_matrix.vhdl"):
self.writer.addComponentDeclarationForFile(
f"Tile/{tileName}/{subFolder}/{tile.name}_switch_matrix.vhdl")
f"{basePath}/{tile.name}_switch_matrix.vhdl")
else:
raise ValueError(
f"Could not find {tile.name}_switch_matrix.vhdl in Tile/{tileName}/{subFolder}/ Need to run matrix generation first")
f"Could not find {tile.name}_switch_matrix.vhdl in {basePath} Need to run matrix generation first")

if os.path.exists(f"Tile/{tileName}/{subFolder}/{tile.name}_ConfigMem.vhdl"):
if os.path.exists(f"{basePath}/{tile.name}_ConfigMem.vhdl"):
self.writer.addComponentDeclarationForFile(
f"Tile/{tileName}/{subFolder}/{tile.name}_ConfigMem.vhdl")
f"{basePath}/{tile.name}_ConfigMem.vhdl")
else:
raise ValueError(
f"Could not find {tile.name}_ConfigMem.vhdl in Tile/{tileName}/{subFolder}/ config_mem generation first")
f"Could not find {tile.name}_ConfigMem.vhdl in {basePath} config_mem generation first")

if self.fabric.configBitMode == ConfigBitMode.FRAME_BASED and tile.globalConfigBits > 0:
if os.path.exists(f"{tile.name}_ConfigMem.vhdl"):
self.writer.addComponentDeclarationForFile(
f"{tile.name}_ConfigMem.vhdl")
if self.fabric.configBitMode == ConfigBitMode.FRAME_BASED and tile.globalConfigBits > 0:
if os.path.exists(f"{basePath}/{tile.name}_ConfigMem.vhdl"):
self.writer.addComponentDeclarationForFile(
f"{basePath}/{tile.name}_ConfigMem.vhdl")

# VHDL signal declarations
self.writer.addComment("signal declarations", onNewLine=True)
Expand Down Expand Up @@ -1161,7 +1158,7 @@ def generateSuperTile(self, superTile: SuperTile) -> None:
for t in superTile.tiles:
# This is only relevant to VHDL code generation, will not affect Verilog code generation
self.writer.addComponentDeclarationForFile(
f"Tile/{superTile.name}/{t.name}/{t.name}.vhdl")
f"{Path(self.writer.outFileName).parent}/{t.name}/{t.name}.vhdl")

# find all internal connections
internalConnections = superTile.getInternalConnections()
Expand Down Expand Up @@ -1357,11 +1354,11 @@ def generateFabric(self) -> None:
continue
if name not in self.fabric.superTileDic.keys():
self.writer.addComponentDeclarationForFile(
f"Tile/{t}/{t}.vhdl")
f"{Path(self.writer.outFileName).parent.parent}/Tile/{t}/{t}.vhdl")
added.add(t)
else:
self.writer.addComponentDeclarationForFile(
f"Tile/{name}/{name}.vhdl")
f"{Path(self.writer.outFileName).parent.parent}/Tile/{name}/{name}.vhdl")
added.add(name)

# VHDL signal declarations
Expand Down Expand Up @@ -1809,29 +1806,26 @@ def split_port(p):
self.writer.addConnectionScalar("resten")

if isinstance(self.writer, VHDLWriter):
if not os.path.exists("./Fabric/Frame_Data_Reg.vhdl"):
basePath = Path(self.writer.outFileName).parent
if not os.path.exists(f"{basePath}/Frame_Data_Reg.vhdl"):
raise FileExistsError(
"Frame_Data_Reg.vhdl not found in Fabric folder")
if not os.path.exists("./Fabric/Frame_Select.vhdl"):
if not os.path.exists(f"{basePath}/Frame_Select.vhdl"):
raise FileExistsError(
"Frame_Select.vhdl not found in Fabric folder")
if not os.path.exists("./Fabric/eFPGA_Config.vhdl"):
if not os.path.exists(f"{basePath}/eFPGA_Config.vhdl"):
raise FileExistsError("Config.vhdl not found in Fabric folder")
if not os.path.exists("./Fabric/eFPGA.vhdl"):
if not os.path.exists(f"{basePath}/eFPGA.vhdl"):
raise FileExistsError(
"eFPGA.vhdl not found in Fabric folder, need to generate the eFPGA first")
if not os.path.exists("./Fabric/BlockRAM_1KB.vhdl"):
if not os.path.exists(f"{basePath}/BlockRAM_1KB.vhdl"):
raise FileExistsError(
"BlockRAM_1KB.vhdl not found in Fabric folder")
self.writer.addComponentDeclarationForFile(
"./Fabric/Frame_Data_Reg.vhdl")
self.writer.addComponentDeclarationForFile(
"./Fabric/Frame_Select.vhdl")
self.writer.addComponentDeclarationForFile(
"./Fabric/eFPGA_Config.vhdl")
self.writer.addComponentDeclarationForFile("./Fabric/eFPGA.vhdl")
self.writer.addComponentDeclarationForFile(
"./Fabric/BlockRAM_1KB.vhdl")
self.writer.addComponentDeclarationForFile(f"{basePath}/Frame_Data_Reg.vhdl")
self.writer.addComponentDeclarationForFile(f"{basePath}/Frame_Select.vhdl")
self.writer.addComponentDeclarationForFile(f"{basePath}/eFPGA_Config.vhdl")
self.writer.addComponentDeclarationForFile(f"{basePath}/eFPGA.vhdl")
self.writer.addComponentDeclarationForFile(f"{basePath}/BlockRAM_1KB.vhdl")

self.writer.addLogicStart()

Expand Down
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