Merge pull request #217 from IAmMarcelJung/hotfix/fix_simulation_command

Fix .fst generation in run_simulation and correct signal generation for the demo design in the test bench
FPGA-Research · Jul 30, 2024 · 77ff8e6 · 77ff8e6
2 parents cde60b2 + 058eec8
commit 77ff8e6
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Showing 2 changed files with 6 additions and 3 deletions.
diff --git a/FABulous.py b/FABulous.py
@@ -1079,7 +1079,10 @@ def do_run_simulation(self, args):
         make_hex(f"{self.projectDir}/{path}/{bitstream}", f"{self.projectDir}/{path}/{bitstream_hex}")
 
         try:
-            runCmd = ["vvp", f"{self.projectDir}/{path}/{vvp_file}"]
+            if optional_arg  == "fst":
+                runCmd = ["vvp", f"{self.projectDir}/{path}/{vvp_file}", "-fst"]
+            else:
+                runCmd = ["vvp", f"{self.projectDir}/{path}/{vvp_file}"]
             sp.run(runCmd, check=True)
         except sp.CalledProcessError:
             logger.error("Simulation failed")

diff --git a/fabric_files/FABulous_project_template_verilog/Test/sequential_16bit_en_tb.v b/fabric_files/FABulous_project_template_verilog/Test/sequential_16bit_en_tb.v
@@ -88,9 +88,9 @@ module sequential_16bit_en_tb;
         end
 `endif
         repeat (100) @(posedge CLK);
-        O_top = 28'b1; // reset
+        O_top = 28'b11; // enable and reset
         repeat (5) @(posedge CLK);
-        O_top = 28'b0;
+        O_top = 28'b10;
         for (i = 0; i < 100; i = i + 1) begin
             @(negedge CLK);
             $display("fabric(I_top) = 0x%X gold = 0x%X, fabric(T_top) = 0x%X gold = 0x%X", I_top, I_top_gold, T_top, T_top_gold);