Fix rendering of simulation doc commands (#137)

FPGA-Research · Nov 23, 2023 · 5bd4b93 · 5bd4b93
1 parent 0431674
commit 5bd4b93
Showing 1 changed file with 5 additions and 5 deletions.
diff --git a/docs/source/simulation/simulation.rst b/docs/source/simulation/simulation.rst
@@ -3,11 +3,11 @@ Simulation setup
 
 The following series of commands can be used to easily run a simulation with a test bitstream loaded, using Icarus Verilog:
 
-```
-cd demo/Test
-./build_test_design.sh
-./run_simulation.sh
-```
+.. code-block:: console
+
+        cd demo/Test
+        ./build_test_design.sh
+        ./run_simulation.sh
 
 FABulous comes with 3 different simulation methods _`configuration module`,