The idea is to speed up the Floating Point Multiplier by means of redesigning the Multiply Significand block.
The Modified Booth Encoding technique is implemented, which allow to convert signed numbers into 2's complement, so the multiplication can be performed faster.
This encoding is performed in order to get all the partial products of the multiplication.
Given all the partial products, the way in which they are added toghether is using a Dadda Adder Plane.
This implementation uses full adders and half adders in a Carry Save Adder configuration to add all the partial products together.
To design this particular hardware configuration, a Python script is used to write the VHDL code of the block.
The 2 outputs of DaddaTree are added using a simple Ripple Carry Adder.
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The hardware accelerator is made for the Multiply Significand block.
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Modified Booth Encoder .
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Dadda Adder Plane.
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Simple 2-input Adder.
sudo apt-get install ghdl gtkwave
Walkthrough https://github.com/YosysHQ/yosys
Walkthrough to convert vhdl into verilog files https://github.com/ldoolitt/vhd2vl (needed for synthesys with yosys)
Walkthrough https://github.com/YosysHQ/nextpnr
The 'tb_mul.vhd' is the default testbench for the overall architecture.
The simulation can be seen running gtkwave tb/tb_mul.vcd.
There is also the 'tb_MBE.vhd' testbench, which involves only the Multiply Significand Block.
This other simulation can be seen running gtkwave tb/tb_MBE.vcd
Running tb_script file , files of the overall architecture will be analyzed using ghdl.
By default a vcd file named 'tb_mul.vcd' will be created in the tb/ directory.
You can see the simulation running again gtkwave tb/tb_mul.vcd.
The tb_MBE file compiles the design of the Hardware Accelerator, the Multiply Significand Block.
Also in this case a vcd file is created in the tb/ directory, named 'tb_MBE.vcd'.
You can see the simulation running again gtkwave tb/tb_MBE.vcd.
The vhdl code are converted in verilog files with vhd2vl.
The DaddaTree.vhd file can't be converted in verilog using vhd2vl because of memory exhausted problem.
If you can convert it, all verilog files the synthesys can be done with yosys.
The target FPGA platform can be choosed with yosys with the commmand: synth_<target_name>.
Has to be done.
Using nextpnr.