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Merge pull request #58 from Digilent/feature/zmod-support
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Pull request for merging feature/zmod-support to hierarchies branch
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@artvvb
artvvb authored Nov 12, 2021
2 parents 202e194 + e1d6f41 commit f261272
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Showing 5 changed files with 77 additions and 60 deletions.
46 changes: 38 additions & 8 deletions ip/Zmods/AXI_Zmod_ADC1410/component.xml
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Expand All @@ -590,7 +590,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
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<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>65fdc6e7</spirit:value>
<spirit:value>d34b96a5</spirit:value>
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<spirit:vendorExtensions>
<xilinx:coreExtensions>
<xilinx:supportedFamilies>
<xilinx:family xilinx:lifeCycle="Pre-Production">zynq</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">artix7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">artix7l</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">kintex7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">kintex7l</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">spartan7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">aartix7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">aspartan7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">azynq</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">zynquplus</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">zynq</xilinx:family>
<xilinx:family xilinx:lifeCycle="Pre-Production">azynq</xilinx:family>
</xilinx:supportedFamilies>
<xilinx:taxonomies>
<xilinx:taxonomy>AXI_Peripheral</xilinx:taxonomy>
</xilinx:taxonomies>
<xilinx:displayName>AXI_ZmodADC1410_v1.0</xilinx:displayName>
<xilinx:coreRevision>141</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2020-03-05T20:29:46Z</xilinx:coreCreationDateTime>
<xilinx:coreRevision>143</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2021-11-11T00:37:39Z</xilinx:coreCreationDateTime>
<xilinx:tags>
<xilinx:tag xilinx:name="natinst.com:user:AXI_ZmodADC1410:1.0_ARCHIVE_LOCATION">c:/Vivado_Projects/Deploy/repo/local/ip/AXI_Zmod_ADC1410</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@4f2d92da_ARCHIVE_LOCATION">c:/Vivado_Projects/Git_ZmodADC1410_Demo/repo/local/ip/AXI_Zmod_ADC1410</xilinx:tag>
Expand Down Expand Up @@ -4063,13 +4063,43 @@
<xilinx:tag xilinx:name="ui.data.coregen.dd@55eeeac7_ARCHIVE_LOCATION">d:/Github/USB104A7-ZmodDAC/FPGA/repo/vivado-library/ip/Zmods/AXI_Zmod_ADC1410</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@6301a865_ARCHIVE_LOCATION">d:/Github/USB104A7-ZmodDAC/FPGA/repo/vivado-library/ip/Zmods/AXI_Zmod_ADC1410</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@610218af_ARCHIVE_LOCATION">d:/Github/USB104A7-ZmodDAC/FPGA/repo/vivado-library/ip/Zmods/AXI_Zmod_ADC1410</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@6fd0b789_ARCHIVE_LOCATION">d:/Workspace/Vivado/ecl/Eclypse-Z7/hw/repo/vivado-library/ip/Zmods/AXI_Zmod_ADC1410</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@4630a9_ARCHIVE_LOCATION">d:/Workspace/Vivado/ecl/Eclypse-Z7/hw/repo/vivado-library/ip/Zmods/AXI_Zmod_ADC1410</xilinx:tag>
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</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2019.1</xilinx:xilinxVersion>
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6 changes: 1 addition & 5 deletions ip/Zmods/AXI_Zmod_ADC1410/src/AXI_ZmodADC1410_v1_0_S00_AXI.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -343,11 +343,7 @@ ProcSlvReg0: process (AxiLiteClk) --Control Register
lSlvReg0(4) <= not lSetStop;
elsif (lSlvRegWrEn = '1' and loc_addr = "00000") then
if (lAxiWstrb(0) = '1') then
lSlvReg0(7 downto 5) <= lAxiWdata(7 downto 5);
lSlvReg0(3 downto 0) <= lAxiWdata(3 downto 0);
if (lAxiWdata(4) = '1') then
lSlvReg0(4) <= lAxiWdata(4);
end if;
lSlvReg0(7 downto 0) <= lAxiWdata(7 downto 0);
end if;
if (lAxiWstrb(1) = '1') then
lSlvReg0(15 downto 8) <= lAxiWdata(15 downto 8);
Expand Down
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