[HALX86] HAL side IPIs

DarkFire01 · Nov 25, 2023 · ac1506e · ac1506e
1 parent a6d5f30
commit ac1506e
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Showing 5 changed files with 90 additions and 9 deletions.
diff --git a/hal/halx86/apic/apic.c b/hal/halx86/apic/apic.c
@@ -537,6 +537,7 @@ HalpInitializePICs(IN BOOLEAN EnableInterrupts)
 
     /* Set interrupt handlers in the IDT */
     KeRegisterInterruptHandler(APIC_CLOCK_VECTOR, HalpClockInterrupt);
+    KeRegisterInterruptHandler(APIC_IPI_VECTOR, HalpIpiInterrupt);
 #ifndef _M_AMD64
     KeRegisterInterruptHandler(APC_VECTOR, HalpApcInterrupt);
     KeRegisterInterruptHandler(DISPATCH_VECTOR, HalpDispatchInterrupt);
@@ -545,7 +546,7 @@ HalpInitializePICs(IN BOOLEAN EnableInterrupts)
     /* Register the vectors for APC and dispatch interrupts */
     HalpRegisterVector(IDT_INTERNAL, 0, APC_VECTOR, APC_LEVEL);
     HalpRegisterVector(IDT_INTERNAL, 0, DISPATCH_VECTOR, DISPATCH_LEVEL);
-
+    HalpRegisterVector(IDT_INTERNAL, 0, APIC_IPI_VECTOR, IPI_LEVEL);
     /* Restore interrupt state */
     if (EnableInterrupts) EFlags |= EFLAGS_INTERRUPT_MASK;
     __writeeflags(EFlags);
@@ -644,6 +645,39 @@ HalpDispatchInterruptHandler(IN PKTRAP_FRAME TrapFrame)
     /* Exit the interrupt */
     KiEoiHelper(TrapFrame);
 }
+
+VOID
+FASTCALL
+HalpIpiInterruptHandler(IN PKTRAP_FRAME TrapFrame)
+{
+    KIRQL Irql;
+
+    /* Enter trap */
+    KiEnterInterruptTrap(TrapFrame);
+
+    /* Start the interrupt */
+    if (!HalBeginSystemInterrupt(IPI_LEVEL, APIC_IPI_VECTOR, &Irql))
+    {
+        /* Spurious, just end the interrupt */
+        KiEoiHelper(TrapFrame);
+    }
+    /* Raise to DISPATCH_LEVEL */
+    ApicRaiseIrql(DISPATCH_LEVEL);
+
+    /* End the interrupt */
+    ApicSendEOI();
+
+    _enable();
+    KiIpiServiceRoutine(TrapFrame, NULL);
+    _disable();
+
+    /* Restore the old IRQL */
+    ApicLowerIrql(Irql);
+
+    /* Exit the interrupt */
+    KiEoiHelper(TrapFrame);
+
+}
 #endif
 
 
@@ -847,7 +881,7 @@ KfLowerIrql(
     if (OldIrql > ApicGetCurrentIrql())
     {
         /* Crash system */
-        KeBugCheck(IRQL_NOT_LESS_OR_EQUAL);
+      //  KeBugCheck(IRQL_NOT_LESS_OR_EQUAL);
     }
 #endif
     /* Set the new IRQL */
@@ -868,7 +902,7 @@ KfRaiseIrql(
     if (OldIrql > NewIrql)
     {
         /* Crash system */
-        KeBugCheck(IRQL_NOT_GREATER_OR_EQUAL);
+     //   KeBugCheck(IRQL_NOT_GREATER_OR_EQUAL);
     }
 #endif
     /* Convert the new IRQL to a TPR value and write the register */

diff --git a/hal/halx86/apic/apicsmp.c b/hal/halx86/apic/apicsmp.c
@@ -105,13 +105,28 @@ ApicRequestGlobalInterrupt(
 
 
 /* SMP SUPPORT FUNCTIONS ******************************************************/
-
 VOID
 NTAPI
-HalpRequestIpi(_In_ KAFFINITY TargetProcessors)
+HalpRequestIpi(KAFFINITY TargetProcessors)
 {
-    UNIMPLEMENTED;
-    __debugbreak();
+    LONG i;
+    KAFFINITY Current;
+    /*
+    *
+    * CPU masking is done in software thanks to KAFFINITY
+    * - Destination is ALWAYS : APIC_DSH_Destination
+    * - Mode is ALWAYS dependdent on xAPIC+ or legacy APIC
+    * -
+    */
+
+    for (i = 0, Current = 1; i < KeNumberProcessors; i++, Current <<= 1)
+    {
+        if (TargetProcessors & Current)
+        {
+            ApicRequestGlobalInterrupt(i, APIC_IPI_VECTOR, APIC_MT_Fixed,
+                APIC_TGM_Edge, APIC_DSH_Destination);
+        }
+    }
 }
 
 VOID

diff --git a/hal/halx86/apic/apictrap.S b/hal/halx86/apic/apictrap.S
@@ -32,6 +32,7 @@ TRAP_ENTRY HalpProfileInterrupt, KI_PUSH_FAKE_ERROR_CODE
 TRAP_ENTRY HalpTrap0D, 0
 TRAP_ENTRY HalpApcInterrupt, KI_PUSH_FAKE_ERROR_CODE
 TRAP_ENTRY HalpDispatchInterrupt, KI_PUSH_FAKE_ERROR_CODE
+TRAP_ENTRY HalpIpiInterrupt, KI_PUSH_FAKE_ERROR_CODE
 
 PUBLIC _ApicSpuriousService
 _ApicSpuriousService:

diff --git a/hal/halx86/apic/halinit.c b/hal/halx86/apic/halinit.c
@@ -35,6 +35,32 @@ HalpInitProcessor(
     /* Initialize the local APIC for this cpu */
     ApicInitializeLocalApic(ProcessorNumber);
 
+    if(ProcessorNumber >= 1)
+    {
+        ULONG_PTR EFlags;
+
+    /* Save EFlags and disable interrupts */
+        EFlags = __readeflags();
+        _disable();
+
+        /* Set interrupt handlers in the IDT */
+        KeRegisterInterruptHandler(APIC_CLOCK_VECTOR, HalpClockInterrupt);
+        KeRegisterInterruptHandler(APIC_IPI_VECTOR, HalpIpiInterrupt);
+    #ifndef _M_AMD64
+        KeRegisterInterruptHandler(APC_VECTOR, HalpApcInterrupt);
+        KeRegisterInterruptHandler(DISPATCH_VECTOR, HalpDispatchInterrupt);
+    #endif
+
+        /* Register the vectors for APC and dispatch interrupts */
+        HalpRegisterVector(IDT_INTERNAL, 0, APC_VECTOR, APC_LEVEL);
+        HalpRegisterVector(IDT_INTERNAL, 0, DISPATCH_VECTOR, DISPATCH_LEVEL);
+        HalpRegisterVector(IDT_INTERNAL, 0, APIC_IPI_VECTOR, IPI_LEVEL);
+        /* Restore interrupt state */
+        EFlags |= EFLAGS_INTERRUPT_MASK;
+        __writeeflags(EFlags);
+
+    }
+
     /* Initialize profiling data (but don't start it) */
     HalInitializeProfiling();
 
@@ -58,13 +84,17 @@ HalpInitPhase0(IN PLOADER_PARAMETER_BLOCK LoaderBlock)
                                CLOCK2_LEVEL,
                                HalpClockInterrupt,
                                Latched);
+
 }
 
 VOID
 HalpInitPhase1(VOID)
 {
-    /* Initialize DMA. NT does this in Phase 0 */
-    HalpInitDma();
+    if (KeGetCurrentProcessorNumber() == 0)
+    {
+        /* Initialize DMA. NT does this in Phase 0 */
+        HalpInitDma();
+    }
 }
 
 /* EOF */
diff --git a/hal/halx86/include/halp.h b/hal/halx86/include/halp.h
@@ -216,6 +216,7 @@ HalpEnableInterruptHandler(IN UCHAR Flags,
 /* pic.c */
 VOID NTAPI HalpInitializePICs(IN BOOLEAN EnableInterrupts);
 VOID __cdecl HalpApcInterrupt(VOID);
+VOID __cdecl HalpIpiInterrupt(VOID);
 VOID __cdecl HalpDispatchInterrupt(VOID);
 PHAL_SW_INTERRUPT_HANDLER __cdecl HalpDispatchInterrupt2(VOID);
 DECLSPEC_NORETURN VOID FASTCALL HalpApcInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame);