Refactor build.rs, top.v, and top.rs files

build.rs

@@ -1,4 +1,3 @@
-use std::path::Path;
 use std::path::PathBuf;
 use std::{env, fs};
 use verilator::gen::{Standard, Verilator};
@@ -28,8 +27,6 @@ fn main() {
   verilator
     .with_coverage(true)
     .with_trace(true)
-    .no_warn("fatal")
-    .no_warn("WIDTHTRUNC")
     .file_with_standard("dependencies/rtl/PuaCpu.v", Standard::SystemVerilog2012)
     .file_with_standard("dependencies/rtl/top.v", Standard::SystemVerilog2012)
     .file(out_dir.join("top.cpp"))

dependencies/rtl/top.v

@@ -9,14 +9,14 @@ module top(
     input  [31:0] inst_sram_rdata,
     // data sram interface
     output        data_sram_en,
-    output [ 8:0] data_sram_wen,
+    output [ 7:0] data_sram_wen,
     output [31:0] data_sram_addr,
-    output [64:0] data_sram_wdata,
-    input  [64:0] data_sram_rdata,
+    output [63:0] data_sram_wdata,
+    input  [63:0] data_sram_rdata,
     // trace debug interface
     output        debug_commit,
     output [63:0] debug_pc,
-    output [4:0 ] debug_reg_num,
+    output [4:0 ] debug_reg_wnum,
     output [63:0] debug_wdata
 );
 
@@ -42,7 +42,7 @@ PuaCpu core(
     // debug
     .io_debug_wb_pc           (debug_pc),
     .io_debug_wb_rf_wen       (debug_commit),
-    .io_debug_wb_rf_wnum      (debug_reg_num),
+    .io_debug_wb_rf_wnum      (debug_reg_wnum),
     .io_debug_wb_rf_wdata     (debug_wdata)
 );
 

src/dut/top.rs

@@ -1,4 +1,3 @@
-use std::time::Duration;
 use verilated_module::module;
 
 #[module(top)]
@@ -39,33 +38,3 @@ pub struct Top {
   #[port(output)]
   pub debug_wdata: [bool; 64],
 }
-
-pub fn create_tb() {
-  let mut tb: Top = Top::default();
-  tb.eval();
-  tb.eval();
-
-  tb.open_trace("wave.vcd", 99).unwrap();
-
-  let mut clocks: u64 = 0;
-  while clocks < 100 {
-    if clocks == 2 {
-      tb.reset_toggle();
-    }
-
-    tb.clock_toggle();
-    tb.eval();
-    tb.trace_at(Duration::from_nanos(20 * clocks));
-
-    tb.clock_toggle();
-    tb.eval();
-    tb.trace_at(Duration::from_nanos(20 * clocks + 10));
-
-    clocks += 1;
-  }
-  tb.trace_at(Duration::from_nanos(20 * clocks));
-
-  tb.finish();
-
-  println!("Simulation complete");
-}