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feat: Add inst and data fields to Dut struct
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This commit adds two new fields, `inst` and `data`, to the `Dut` struct in the `dut.rs` file. These fields will store the instruction and data values respectively.
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@Clo91eaf
Clo91eaf committed May 8, 2024
1 parent b2b7f43 commit 275981e
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Showing 4 changed files with 24 additions and 71 deletions.
37 changes: 14 additions & 23 deletions dependencies/rtl/PuaCpu.v
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Original file line number Diff line number Diff line change
Expand Up @@ -63,8 +63,7 @@ module Ctrl( // playground/src/ctrl/Ctrl.scala:9:7
input io_executeUnit_data_is_load, // playground/src/ctrl/Ctrl.scala:10:14
input [4:0] io_executeUnit_data_reg_waddr, // playground/src/ctrl/Ctrl.scala:10:14
input io_executeUnit_flush, // playground/src/ctrl/Ctrl.scala:10:14
input [63:0] io_executeUnit_target, // playground/src/ctrl/Ctrl.scala:10:14
output io_executeUnit_ctrlSignal_do_flush // playground/src/ctrl/Ctrl.scala:10:14
input [63:0] io_executeUnit_target // playground/src/ctrl/Ctrl.scala:10:14
);

wire lw_stall =
Expand All @@ -78,7 +77,6 @@ module Ctrl( // playground/src/ctrl/Ctrl.scala:9:7
assign io_fetchUnit_ctrlSignal_do_flush = io_executeUnit_flush; // playground/src/ctrl/Ctrl.scala:9:7
assign io_decodeUnit_ctrlSignal_allow_to_go = ~lw_stall; // playground/src/ctrl/Ctrl.scala:9:7, :18:85, :22:46
assign io_decodeUnit_ctrlSignal_do_flush = io_executeUnit_flush | lw_stall; // playground/src/ctrl/Ctrl.scala:9:7, :18:85, :29:61
assign io_executeUnit_ctrlSignal_do_flush = io_executeUnit_flush; // playground/src/ctrl/Ctrl.scala:9:7
endmodule

module FetchUnit( // playground/src/pipeline/fetch/FetchUnit.scala:9:7
Expand Down Expand Up @@ -1347,7 +1345,6 @@ endmodule
module MemoryStage( // playground/src/pipeline/memory/MemoryStage.scala:21:7
input clock, // playground/src/pipeline/memory/MemoryStage.scala:21:7
reset, // playground/src/pipeline/memory/MemoryStage.scala:21:7
io_ctrl_do_flush, // playground/src/pipeline/memory/MemoryStage.scala:22:14
input [63:0] io_executeUnit_data_pc, // playground/src/pipeline/memory/MemoryStage.scala:22:14
input io_executeUnit_data_info_valid, // playground/src/pipeline/memory/MemoryStage.scala:22:14
input [2:0] io_executeUnit_data_info_fusel, // playground/src/pipeline/memory/MemoryStage.scala:22:14
Expand Down Expand Up @@ -1379,28 +1376,25 @@ module MemoryStage( // playground/src/pipeline/memory/MemoryStage.scala:21:7
always @(posedge clock) begin // playground/src/pipeline/memory/MemoryStage.scala:21:7
if (reset) begin // playground/src/pipeline/memory/MemoryStage.scala:21:7
data_pc <= 64'h0; // playground/src/pipeline/memory/MemoryStage.scala:22:14, :27:21, :29:26, :30:10, :31:35
data_info_valid <= 1'h0; // playground/src/pipeline/memory/MemoryStage.scala:22:14, :27:21, :29:26, :30:10, :31:35
data_info_valid <= 1'h0; // playground/src/pipeline/memory/MemoryStage.scala:22:14, :27:21
data_info_fusel <= 3'h0; // playground/src/pipeline/memory/MemoryStage.scala:27:{21,34}
data_info_reg_wen <= 1'h0; // playground/src/pipeline/memory/MemoryStage.scala:22:14, :27:21, :29:26, :30:10, :31:35
data_info_reg_wen <= 1'h0; // playground/src/pipeline/memory/MemoryStage.scala:22:14, :27:21
data_info_reg_waddr <= 5'h0; // playground/src/pipeline/memory/MemoryStage.scala:21:7, :27:21
data_rd_info_wdata_0 <= 64'h0; // playground/src/pipeline/memory/MemoryStage.scala:22:14, :27:21, :29:26, :30:10, :31:35
data_rd_info_wdata_2 <= 64'h0; // playground/src/pipeline/memory/MemoryStage.scala:22:14, :27:21, :29:26, :30:10, :31:35
data_rd_info_wdata_5 <= 64'h0; // playground/src/pipeline/memory/MemoryStage.scala:22:14, :27:21, :29:26, :30:10, :31:35
data_has_exception <= 1'h0; // playground/src/pipeline/memory/MemoryStage.scala:22:14, :27:21, :29:26, :30:10, :31:35
data_has_exception <= 1'h0; // playground/src/pipeline/memory/MemoryStage.scala:22:14, :27:21
end
else begin // playground/src/pipeline/memory/MemoryStage.scala:21:7
data_pc <= io_ctrl_do_flush ? 64'h0 : io_executeUnit_data_pc; // playground/src/pipeline/memory/MemoryStage.scala:22:14, :27:21, :29:26, :30:10, :31:35
data_info_valid <= ~io_ctrl_do_flush & io_executeUnit_data_info_valid; // playground/src/pipeline/memory/MemoryStage.scala:27:21, :29:26, :30:10, :31:35
data_info_fusel <= io_ctrl_do_flush ? 3'h0 : io_executeUnit_data_info_fusel; // playground/src/pipeline/memory/MemoryStage.scala:27:{21,34}, :29:26, :30:10, :31:35
data_info_reg_wen <= ~io_ctrl_do_flush & io_executeUnit_data_info_reg_wen; // playground/src/pipeline/memory/MemoryStage.scala:27:21, :29:26, :30:10, :31:35
data_info_reg_waddr <= io_ctrl_do_flush ? 5'h0 : io_executeUnit_data_info_reg_waddr; // playground/src/pipeline/memory/MemoryStage.scala:21:7, :27:21, :29:26, :30:10, :31:35
data_rd_info_wdata_0 <=
io_ctrl_do_flush ? 64'h0 : io_executeUnit_data_rd_info_wdata_0; // playground/src/pipeline/memory/MemoryStage.scala:22:14, :27:21, :29:26, :30:10, :31:35
data_rd_info_wdata_2 <=
io_ctrl_do_flush ? 64'h0 : io_executeUnit_data_rd_info_wdata_2; // playground/src/pipeline/memory/MemoryStage.scala:22:14, :27:21, :29:26, :30:10, :31:35
data_rd_info_wdata_5 <=
io_ctrl_do_flush ? 64'h0 : io_executeUnit_data_rd_info_wdata_5; // playground/src/pipeline/memory/MemoryStage.scala:22:14, :27:21, :29:26, :30:10, :31:35
data_has_exception <= 1'h0; // playground/src/pipeline/memory/MemoryStage.scala:22:14, :27:21, :29:26, :30:10, :31:35
data_pc <= io_executeUnit_data_pc; // playground/src/pipeline/memory/MemoryStage.scala:27:21
data_info_valid <= io_executeUnit_data_info_valid; // playground/src/pipeline/memory/MemoryStage.scala:27:21
data_info_fusel <= io_executeUnit_data_info_fusel; // playground/src/pipeline/memory/MemoryStage.scala:27:21
data_info_reg_wen <= io_executeUnit_data_info_reg_wen; // playground/src/pipeline/memory/MemoryStage.scala:27:21
data_info_reg_waddr <= io_executeUnit_data_info_reg_waddr; // playground/src/pipeline/memory/MemoryStage.scala:27:21
data_rd_info_wdata_0 <= io_executeUnit_data_rd_info_wdata_0; // playground/src/pipeline/memory/MemoryStage.scala:27:21
data_rd_info_wdata_2 <= io_executeUnit_data_rd_info_wdata_2; // playground/src/pipeline/memory/MemoryStage.scala:27:21
data_rd_info_wdata_5 <= io_executeUnit_data_rd_info_wdata_5; // playground/src/pipeline/memory/MemoryStage.scala:27:21
data_has_exception <= 1'h0; // playground/src/pipeline/memory/MemoryStage.scala:22:14, :27:21
end
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_ // playground/src/pipeline/memory/MemoryStage.scala:21:7
Expand Down Expand Up @@ -1759,7 +1753,6 @@ module Core( // playground/src/Core.scala:10:7
wire _Ctrl_io_fetchUnit_ctrlSignal_do_flush; // playground/src/Core.scala:18:30
wire _Ctrl_io_decodeUnit_ctrlSignal_allow_to_go; // playground/src/Core.scala:18:30
wire _Ctrl_io_decodeUnit_ctrlSignal_do_flush; // playground/src/Core.scala:18:30
wire _Ctrl_io_executeUnit_ctrlSignal_do_flush; // playground/src/Core.scala:18:30
Ctrl Ctrl ( // playground/src/Core.scala:18:30
.io_fetchUnit_target (_Ctrl_io_fetchUnit_target),
.io_fetchUnit_ctrlSignal_allow_to_go (_Ctrl_io_fetchUnit_ctrlSignal_allow_to_go),
Expand All @@ -1773,8 +1766,7 @@ module Core( // playground/src/Core.scala:10:7
.io_executeUnit_data_is_load (_ExecuteUnit_io_ctrl_data_is_load), // playground/src/Core.scala:24:30
.io_executeUnit_data_reg_waddr (_ExecuteUnit_io_ctrl_data_reg_waddr), // playground/src/Core.scala:24:30
.io_executeUnit_flush (_ExecuteUnit_io_ctrl_flush), // playground/src/Core.scala:24:30
.io_executeUnit_target (_ExecuteUnit_io_ctrl_target), // playground/src/Core.scala:24:30
.io_executeUnit_ctrlSignal_do_flush (_Ctrl_io_executeUnit_ctrlSignal_do_flush)
.io_executeUnit_target (_ExecuteUnit_io_ctrl_target) // playground/src/Core.scala:24:30
);
FetchUnit FetchUnit ( // playground/src/Core.scala:19:30
.clock (clock),
Expand Down Expand Up @@ -1934,7 +1926,6 @@ module Core( // playground/src/Core.scala:10:7
MemoryStage MemoryStage ( // playground/src/Core.scala:25:30
.clock (clock),
.reset (reset),
.io_ctrl_do_flush (_Ctrl_io_executeUnit_ctrlSignal_do_flush), // playground/src/Core.scala:18:30
.io_executeUnit_data_pc (_ExecuteUnit_io_memoryStage_data_pc), // playground/src/Core.scala:24:30
.io_executeUnit_data_info_valid (_ExecuteUnit_io_memoryStage_data_info_valid), // playground/src/Core.scala:24:30
.io_executeUnit_data_info_fusel (_ExecuteUnit_io_memoryStage_data_info_fusel), // playground/src/Core.scala:24:30
Expand Down
40 changes: 0 additions & 40 deletions format.gtkw
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This file was deleted.

6 changes: 5 additions & 1 deletion src/dut.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -22,6 +22,8 @@ pub struct Dut {
reset: bool,
pub ticks: u64,
pub prepare_for_difftest: bool,
pub inst: u32,
pub data: u64
}

impl Dut {
Expand All @@ -36,6 +38,8 @@ impl Dut {
reset: false,
ticks: 0,
prepare_for_difftest: false,
inst: 0,
data: 0
}
}

Expand Down Expand Up @@ -67,10 +71,10 @@ impl Dut {
_ => {},
}

// a little trick: there must be 2 state transitions after clock posedge
self.clock_toggle();
self.top.eval();
if self.ticks >= 2 {
assert!(self.clock && !self.reset);
self.top.set_inst_sram_rdata(inst);
self.top.set_data_sram_rdata(data);
self.top.eval();
Expand Down
12 changes: 5 additions & 7 deletions src/emulator.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -101,11 +101,9 @@ impl Emulator {
}

fn dut_step(&mut self) -> DebugInfo {
let mut inst: u32 = 0;
let mut data: u64 = 0;
let mut ticks = 20;
loop {
let (inst_sram, data_sram, debug_info) = self.dut.step(inst, data).unwrap();
let (inst_sram, data_sram, debug_info) = self.dut.step(self.dut.inst, self.dut.data).unwrap();

if data_sram.en {
let p_addr = self
Expand All @@ -115,12 +113,12 @@ impl Emulator {

// The result of the read method can be `Exception::LoadAccessFault`. In fetch(), an error
// should be `Exception::InstructionAccessFault`.
data = self.cpu.bus.read(p_addr, crate::cpu::DOUBLEWORD).unwrap();
self.dut.data = self.cpu.bus.read(p_addr, crate::cpu::DOUBLEWORD).unwrap();
trace!(
"[dut] ticks: {}, data_sram: addr: {:#x}, data: {:#018x}",
self.dut.ticks,
data_sram.addr,
data
self.dut.data
);
}

Expand All @@ -132,13 +130,13 @@ impl Emulator {

// The result of the read method can be `Exception::LoadAccessFault`. In fetch(), an error
// should be `Exception::InstructionAccessFault`.
inst = self.cpu.bus.read(p_pc, crate::cpu::WORD).unwrap() as u32;
self.dut.inst = self.cpu.bus.read(p_pc, crate::cpu::WORD).unwrap() as u32;

trace!(
"[dut] ticks: {}, inst_sram: addr: {:#x}, inst: {:#018x}",
self.dut.ticks,
inst_sram.addr,
inst
self.dut.inst
);
}

Expand Down

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