Add rvemu crate and rvemu.dts file

Cargo.toml

@@ -15,3 +15,4 @@ clap = { version = "4.3.11", features = ["derive"] }
 regex = "1.9.0"
 eval = "0.4.3"
 anyhow = "1.0.80"
+rvemu = "0.0.11"

rvemu.dts

@@ -0,0 +1,88 @@
+/dts-v1/;
+
+/ {
+    #address-cells = <0x02>;
+    #size-cells = <0x02>;
+    compatible = "riscv-virtio";
+    model = "riscv-virtio,qemu";
+
+    chosen {
+        bootargs = "root=/dev/vda ro console=ttyS0";
+        stdout-path = "/uart@10000000";
+    };
+
+    uart@10000000 {
+        interrupts = <0xa>;
+        interrupt-parent = <0x03>;
+        clock-frequency = <0x384000>;
+        reg = <0x0 0x10000000 0x0 0x100>;
+        compatible = "ns16550a";
+    };
+
+    virtio_mmio@10001000 {
+        interrupts = <0x01>;
+        interrupt-parent = <0x03>;
+        reg = <0x0 0x10001000 0x0 0x1000>;
+        compatible = "virtio,mmio";
+    };
+
+    cpus {
+        #address-cells = <0x01>;
+        #size-cells = <0x00>;
+        timebase-frequency = <0x989680>;
+
+        cpu-map {
+            cluster0 {
+                core0 {
+                    cpu = <0x01>;
+                };
+            };
+        };
+
+        cpu@0 {
+            phandle = <0x01>;
+            device_type = "cpu";
+            reg = <0x00>;
+            status = "okay";
+            compatible = "riscv";
+            riscv,isa = "rv64imafdcsu";
+            mmu-type = "riscv,sv48";
+
+            interrupt-controller {
+                #interrupt-cells = <0x01>;
+                interrupt-controller;
+                compatible = "riscv,cpu-intc";
+                phandle = <0x02>;
+            };
+        };
+    };
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x0 0x8000000>;
+	};
+
+    soc {
+        #address-cells = <0x02>;
+        #size-cells = <0x02>;
+        compatible = "simple-bus";
+        ranges;
+
+        interrupt-controller@c000000 {
+            phandle = <0x03>;
+            riscv,ndev = <0x35>;
+            reg = <0x00 0xc000000 0x00 0x4000000>;
+            interrupts-extended = <0x02 0x0b 0x02 0x09>;
+            interrupt-controller;
+            compatible = "riscv,plic0";
+            #interrupt-cells = <0x01>;
+            #address-cells = <0x00>;
+        };
+
+        clint@2000000 {
+            interrupts-extended = <0x02 0x03 0x02 0x07>;
+            reg = <0x00 0x2000000 0x00 0x10000>;
+            compatible = "riscv,clint0";
+        };
+    };
+};

src/main.rs

@@ -1,5 +1,87 @@
-use hemu::engine::init::engine_start;
+use std::fs::File;
+use std::io;
+use std::io::prelude::*;
+use std::iter::FromIterator;
 
-fn main() {
-  engine_start();
+use rvemu::bus::DRAM_BASE;
+use rvemu::cpu::Cpu;
+use rvemu::emulator::Emulator;
+
+use clap::Parser;
+
+/// Command line arguments.
+#[derive(Parser, Debug)]
+#[clap(name = "rvemu: RISC-V emulator", version = "0.0.1", author = "Asami Doi <@d0iasm>")]
+struct Args {
+  /// A kernel ELF image without headers
+  #[arg(short = 'k', long = "kernel", required = true)]
+  kernel: String,
+
+  /// A raw disk image
+  #[arg(short = 'f', long = "file")]
+  file: Option<String>,
+
+  /// Enables to output debug messages
+  #[arg(short = 'd', long = "debug")]
+  debug: bool,
+
+  /// Enables to count each instruction executed
+  #[clap(short = 'c', long = "count")]
+  count: bool,
+}
+
+/// Output current registers to the console.
+fn dump_registers(cpu: &Cpu) {
+  println!("-------------------------------------------------------------------------------------------");
+  println!("{}", cpu.xregs);
+  println!("-------------------------------------------------------------------------------------------");
+  println!("{}", cpu.fregs);
+  println!("-------------------------------------------------------------------------------------------");
+  println!("{}", cpu.state);
+  println!("-------------------------------------------------------------------------------------------");
+  println!("pc: {:#x}", cpu.pc);
+}
+
+/// Output the count of each instruction executed.
+fn dump_count(cpu: &Cpu) {
+  if cpu.is_count {
+    println!("===========================================================================================");
+    let mut sorted_counter = Vec::from_iter(&cpu.inst_counter);
+    sorted_counter.sort_by(|&(_, a), &(_, b)| b.cmp(&a));
+    for (inst, count) in sorted_counter.iter() {
+      println!("{}, {}", inst, count);
+    }
+    println!("===========================================================================================");
+  }
+}
+
+/// Main function of RISC-V emulator for the CLI version.
+fn main() -> io::Result<()> {
+  let args = Args::parse();
+
+  let mut kernel_file = File::open(args.kernel)?;
+  let mut kernel_data = Vec::new();
+  kernel_file.read_to_end(&mut kernel_data)?;
+
+  let mut img_data = Vec::new();
+  if let Some(img_file) = args.file {
+    File::open(img_file)?.read_to_end(&mut img_data)?;
+  }
+
+  let mut emu = Emulator::new();
+
+  emu.initialize_dram(kernel_data);
+  emu.initialize_disk(img_data);
+  emu.initialize_pc(DRAM_BASE);
+
+  emu.is_debug = args.debug;
+
+  emu.cpu.is_count = args.count;
+
+  emu.start();
+
+  dump_registers(&emu.cpu);
+  dump_count(&emu.cpu);
+
+  Ok(())
 }