updated documentation

README.md

@@ -1,41 +1,27 @@
 ![](../../workflows/gds/badge.svg) ![](../../workflows/docs/badge.svg) ![](../../workflows/test/badge.svg) ![](../../workflows/fpga/badge.svg)
 
-# Tiny Tapeout Verilog Project Template
+![logo](docs/logo.jpeg)
+# tt08-decisiontree-asic
+This project explores the generation of custom ml hardware from ml software.
 
-- [Read the documentation for project](docs/info.md)
+## Project Overview
 
-## What is Tiny Tapeout?
+The goal is to create a custom ASIC that classifies 5x5 images of digits.
 
-Tiny Tapeout is an educational project that aims to make it easier and cheaper than ever to get your digital and analog designs manufactured on a real chip.
+This is achieved by:
+1. Training a sklearn model on the dataset.
+2. Parsing the decision tree structure.
+3. Generating HDL from amaranth.
 
-To learn more and get started, visit https://tinytapeout.com.
+This project is made viable by the tinytapeout open ASIC initiative.
 
-## Set up your Verilog project
+## Model Overview
 
-1. Add your Verilog files to the `src` folder.
-2. Edit the [info.yaml](info.yaml) and update information about your project, paying special attention to the `source_files` and `top_module` properties. If you are upgrading an existing Tiny Tapeout project, check out our [online info.yaml migration tool](https://tinytapeout.github.io/tt-yaml-upgrade-tool/).
-3. Edit [docs/info.md](docs/info.md) and add a description of your project.
-4. Adapt the testbench to your design. See [test/README.md](test/README.md) for more information.
+The dataset is composed of binary 5x5 images as shown in the following picture:
 
-The GitHub action will automatically build the ASIC files using [OpenLane](https://www.zerotoasiccourse.com/terminology/openlane/).
+![digit](docs/digit_4.png)
 
-## Enable GitHub actions to build the results page
+The model has flattened view of the image and has the following structure:
 
-- [Enabling GitHub Pages](https://tinytapeout.com/faq/#my-github-action-is-failing-on-the-pages-part)
+![model](docs/tree.png)
 
-## Resources
-
-- [FAQ](https://tinytapeout.com/faq/)
-- [Digital design lessons](https://tinytapeout.com/digital_design/)
-- [Learn how semiconductors work](https://tinytapeout.com/siliwiz/)
-- [Join the community](https://tinytapeout.com/discord)
-- [Build your design locally](https://www.tinytapeout.com/guides/local-hardening/)
-
-## What next?
-
-- [Submit your design to the next shuttle](https://app.tinytapeout.com/).
-- Edit [this README](README.md) and explain your design, how it works, and how to test it.
-- Share your project on your social network of choice:
- - LinkedIn [#tinytapeout](https://www.linkedin.com/search/results/content/?keywords=%23tinytapeout) [@TinyTapeout](https://www.linkedin.com/company/100708654/)
- - Mastodon [#tinytapeout](https://chaos.social/tags/tinytapeout) [@matthewvenn](https://chaos.social/@matthewvenn)
- - X (formerly Twitter) [#tinytapeout](https://twitter.com/hashtag/tinytapeout) [@tinytapeout](https://twitter.com/tinytapeout)

docs/info.md

@@ -34,6 +34,8 @@ The output of the device is the predicted digit.
 The ironic part is that to test this project you most likely need an external mcu which would run the model much faster than the asic...
 You can also use a parallel to serial converter to send the data to the device.
 
+take a look at the "src/amaranth/digits.ipynb" for a better understanding.
+
 ## External hardware
 
 The minimum required external hardware is a switch matrix to shape the digits and a parallel to serial converter to send the data to the device.