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modified test cases #4

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merged 1 commit into from
Jul 20, 2024
Merged

modified test cases #4

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2 changes: 1 addition & 1 deletion test/tb.v
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Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,7 @@ module tb ();
wire [7:0] uio_oe;

// Replace tt_um_example with your module name:
tt_um_example user_project (
tt_um_COLVERTYETY_top user_project (

// Include power ports for the Gate Level test:
`ifdef GL_TEST
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9 changes: 8 additions & 1 deletion test/test.py
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Expand Up @@ -44,6 +44,13 @@ def shape_input(x):

@cocotb.test()
async def test_project(dut):
"""Test the project."""

dataset = get_dataset()
print(dataset)


# Initialize the dut
dut._log.info("Start")

# Set the clock period to 10 us (100 KHz)
Expand All @@ -70,7 +77,7 @@ async def test_project(dut):

# The following assersion is just an example of how to check the output values.
# Change it to match the actual expected output of your module:
assert dut.uo_out.value == 50
# assert dut.uo_out.value == 50

# Keep testing the module by changing the input values, waiting for
# one or more clock cycles, and asserting the expected output values.