This is an introductory course to computer engineering, focusing on the hardware/software interface, and presenting a bottom-up view of a computer system. Topics include logic design: binary arithmetic, combinational and sequential logic. Computer organization: assembly language programming, CPU design, and memory systems. Introduction to compilers, operating systems, and computer networks.
Implemented with ANDs, OR and XOR gates. The full adder takes a carry-in and two binary numbers as inputs, and a carry out and sum result as outputs.
The ripple carry adder was implemented by putting 8 full adders in series.
Utilize a 4-bit ripple carry adder to determine the 4 LSBs and then depending on the carry out of this computation, one of the ripple carry adders that accounts for this carry is selected for the 4 MSBs of the sum
The ALU, Arithmetic Logic Unit, take in 3 inputs. One input is the OPCODE, which decides the function the ALU will operate. The other two inputs are the values the ALU is operates on. We made it to operate on 10 functions : and, or, not, xor, left shift, logical right shift, arithmetic right shift, add, and subtract. It will output the result of the operation and flags that describes the result whether if it is negative, zero, has a carry out, or has a overflow.
Implemented an 8-bit counter capable of reversing the direction of its count, and resetting its count within our desired bounds. The counter can also be paused.
The clock divider is intended to take in a more traditional MHz clock frequency and output a human friendly clock. The current configuration is capable of translating the 100MHz clock of the FPGA to 1 second.
It outputs a certain arrangement of LEDs. This machine should be cable of reversing and pausing its direction. It takes inputs from 3 switches, which controls the direction and pausing.