Single-Cycle-RISC-V-Processor

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
Dmem.v		Dmem.v
Imem.v		Imem.v
LICENSE		LICENSE
README.md		README.md
RISC-V Single Drawing.vsdx		RISC-V Single Drawing.vsdx
RISC.pdf		RISC.pdf
alu.v		alu.v
code.s		code.s
con_alu_dec.v		con_alu_dec.v
con_main_dec.v		con_main_dec.v
control.v		control.v
datapath.v		datapath.v
extend.v		extend.v
hexcode.txt		hexcode.txt
mux2x1.v		mux2x1.v
mux4x1.v		mux4x1.v
pc.v		pc.v
pcadd.v		pcadd.v
pcadd4.v		pcadd4.v
reg_file.v		reg_file.v
testbench.v		testbench.v
top_risc.v		top_risc.v

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