Cutting Chips

Si Wafers

We use wafers that are slightly more conductive than typical phosphorous doped silicon, specifically antimony (Sb) doped wafers. The full parameters of our typical chips are:

Diameter: 100 +/-0.5 mm
Type/Orientation: N/Antimony<111>
Resistivity:0.005-0.02 ohm*m
Thickness: 500-550 um
Specifications: SSP, 1 flat

These wafers are: N-type silicon; Antimony doped; <111> crystal orientation; low resistivity; ~0.5 mm thick (high tolerance here is not that important); single side polished (SSP, double side polished or DSP wafers are unnecessary); single flat (a flat is a straight line (chord) on one side of the wafer that helps with alignment).

Wafers can be purchased from WRS Materials (our usual supplier, now PureWafer), Ultrasil, or other suppliers.

Cutting Diagrams

Note that the sizes below are for the cut chips, they are not the spacing of the cuts and don't take saw kerf/width into account.

Chips that cross the edge of the wafer are (obviously) waste.

You can get 8 35x16 mm chips from a 100mm wafer.

Cutting

We have our wafers cut at MIT's Microsystems Technology Laboratories by Dan Adams (dan at mtl.mit.edu) or Ryan O'Keefe (rmokeefe at mit.ed). Most EE departments should have a precision diamond saw, and there are many commercial companies. (just google silicon wafer dicing)