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VHDL keywords in node names #6

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andrewpeck opened this issue Jan 15, 2021 · 0 comments
Open

VHDL keywords in node names #6

andrewpeck opened this issue Jan 15, 2021 · 0 comments

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@andrewpeck
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It is a small thing but I noticed today by accident that if I name a node SELECT the generated VHDL will fail, since SELECT is a vhdl keyword..

Maybe the program could include some check for keywords like this at runtime so you don't have to wait until compiling the VHDL?

select, process, case, etc...

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