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It is a small thing but I noticed today by accident that if I name a node SELECT the generated VHDL will fail, since SELECT is a vhdl keyword..
Maybe the program could include some check for keywords like this at runtime so you don't have to wait until compiling the VHDL?
select, process, case, etc...
The text was updated successfully, but these errors were encountered:
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It is a small thing but I noticed today by accident that if I name a node SELECT the generated VHDL will fail, since SELECT is a vhdl keyword..
Maybe the program could include some check for keywords like this at runtime so you don't have to wait until compiling the VHDL?
select, process, case, etc...
The text was updated successfully, but these errors were encountered: