Skip to content

Commit

Permalink
next round of fixes: JR, JP, RR Flags, decode SRL
Browse files Browse the repository at this point in the history
  • Loading branch information
LaurinZ committed Jun 2, 2024
1 parent 117479e commit faa4b65
Show file tree
Hide file tree
Showing 5 changed files with 23 additions and 8 deletions.
8 changes: 6 additions & 2 deletions src/cpu/decode.rs
Original file line number Diff line number Diff line change
Expand Up @@ -215,7 +215,7 @@ impl CPU {
0x3 => match tail {
0x0 => Instructions::JR(
InstParam::ConditionCodes(InstructionCondition::NotCarry),
InstParam::Number8Bit(self.get_8bit_from_pc()),
InstParam::SignedNumber8Bit(self.get_8bit_from_pc() as i8),
),
0x1 => self.decode_0x0_to_0x3_commons(opcode)?,
0x2 => Instructions::LDHLDA,
Expand Down Expand Up @@ -442,7 +442,11 @@ impl CPU {
0x0 => Instructions::RLC(register),
0x1 => Instructions::RL(register),
0x2 => Instructions::SLA(register),
0x3 => Instructions::SWAP(register),
0x3 => match tail {
0x0..=0x7 => Instructions::SWAP(register),
0x8..=0xF => Instructions::SRL(register),
_ => return self.not_implemented(opcode),
}
0x4 => Instructions::BIT(InstParam::Unsigned3Bit(0 + offset), register),
0x5 => Instructions::BIT(InstParam::Unsigned3Bit(2 + offset), register),
0x6 => Instructions::BIT(InstParam::Unsigned3Bit(4 + offset), register),
Expand Down
6 changes: 3 additions & 3 deletions src/cpu/instructions/bit_shift/rr.rs
Original file line number Diff line number Diff line change
Expand Up @@ -24,10 +24,10 @@ impl CPU {
let result = (value >> 1) | shift_into_result;
(
ConditionCodes {
zero: if result != 0 && set_zero {
FlagState::Unset
} else {
zero: if set_zero && result == 0 {
FlagState::Set
} else {
FlagState::Unset
},
subtract: FlagState::Unset,
half_carry: FlagState::Unset,
Expand Down
10 changes: 10 additions & 0 deletions src/cpu/instructions/jumps_subroutines.rs
Original file line number Diff line number Diff line change
Expand Up @@ -44,6 +44,11 @@ impl CPU {
pub fn jp_cc_n16(&mut self, cc:bool, target: u16) -> InstructionResult {
if cc {
self.set_16bit_register(Register16Bit::PC, target);
} else {
// 3 bytes for the jp instruction
// Even if the condition is false, the instruction is still 3 bytes
// So we need to increment the PC by 3
self.set_16bit_register(Register16Bit::PC, self.get_16bit_register(Register16Bit::PC)+3);
}


Expand Down Expand Up @@ -127,6 +132,11 @@ impl CPU {
pub fn ret_cc(&mut self, cc: bool) -> InstructionResult {
if cc {
self.pop_r16(Register16Bit::PC);
} else {
// 1 bytes for the ret instruction
// Even if the condition is false, the instruction is still 1 bytes
// So we need to increment the PC by 1
self.set_16bit_register(Register16Bit::PC, self.get_16bit_register(Register16Bit::PC)+1);
}

InstructionResult {
Expand Down
2 changes: 1 addition & 1 deletion src/cpu/step.rs
Original file line number Diff line number Diff line change
Expand Up @@ -436,7 +436,7 @@ impl CPU {
InstParam::SignedNumber8Bit(target_addr) => {
self.jr_cc_n16(self.check_condition(cond), *target_addr)
}
_ => return Err(format!("CALL of {:?} not implemented", optional_target)),
_ => return Err(format!("JR of {:?} not implemented", optional_target)),
},
_ => return Err(format!("CALL of {:?} not implemented", target_or_condition)),
},
Expand Down
5 changes: 3 additions & 2 deletions src/main.rs
Original file line number Diff line number Diff line change
Expand Up @@ -31,10 +31,11 @@ const DOTS_PER_LINE: u32 = 456;
const TIME_PER_FRAME: f32 = 1.0 / 60.0 * 1000.0;

const DUMP_GAMEBOY_DOCTOR_LOG: bool = true;
const WINDOWS: bool = true;

#[macroquad::main("GB Emulator")]
async fn main() {
// Set up logging
//Set up logging
let config = LogConfigBuilder::builder()
.size(1 * 100)
.roll_count(10)
Expand Down Expand Up @@ -218,7 +219,7 @@ async fn main() {
frame += 1;

// Dump memory every 3 seconds
if dump_time.elapsed().as_secs() >= 3 {
if !WINDOWS && dump_time.elapsed().as_secs() >= 3 {
dump_time = time::Instant::now();
cpu.dump_memory();
}
Expand Down

0 comments on commit faa4b65

Please sign in to comment.