fix carry flag in add_sp_e8

AnnsAnns · Jun 2, 2024 · bdd6df0 · bdd6df0
1 parent e106b9f
commit bdd6df0
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Showing 2 changed files with 4 additions and 4 deletions.
diff --git a/src/cpu/instructions/arithmetic_and_logic/add.rs b/src/cpu/instructions/arithmetic_and_logic/add.rs
@@ -144,7 +144,7 @@ impl CPU {
     }
 
     /// Add a signed 8-bit value to the SP register
-    /// https://rgbds.gbdev.io/docs/v0.6.1/gbz80.7/#ADD_SP,r8
+    /// https://rgbds.gbdev.io/docs/v0.6.1/gbz80.7/#ADD_SP,e8
     pub fn add_sp_e8(&mut self, value: i8) -> InstructionResult {
         let sp = self.get_16bit_register(Register16Bit::SP);
         let (result, overflow) = sp.overflowing_add(value as u16);
@@ -162,7 +162,7 @@ impl CPU {
                 } else {
                     FlagState::Unset
                 },
-                carry: if overflow {
+                carry: if (sp & 0xFF) + (value as u16 & 0xFF) > 0xFF {
                     FlagState::Set
                 } else {
                     FlagState::Unset

diff --git a/src/cpu/instructions/stack_operations.rs b/src/cpu/instructions/stack_operations.rs
@@ -14,7 +14,7 @@ impl CPU { //maybe move ld, dec and inc to their files?
     /// decrements sp
     pub fn dec_sp(&mut self) -> InstructionResult {
         let sp = self.get_16bit_register(Register16Bit::SP);
-        let value = sp-1;
+        let value = sp.wrapping_sub(1);
 
         self.set_16bit_register(Register16Bit::SP, value);
         InstructionResult {
@@ -31,7 +31,7 @@ impl CPU { //maybe move ld, dec and inc to their files?
     /// increments sp
     pub fn inc_sp(&mut self) -> InstructionResult {
         let sp = self.get_16bit_register(Register16Bit::SP);
-        let value = sp+1;
+        let value = sp.wrapping_add(1);
 
         self.set_16bit_register(Register16Bit::SP, value);
         InstructionResult {