ipbus updated, now all types of SFP connectors worknig

AliceO2Group · Dec 29, 2020 · 0de9bc1 · 0de9bc1
1 parent 4b0da86
commit 0de9bc1
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Showing 18 changed files with 145 additions and 72 deletions.
diff --git a/firmware/FT0/FTM_PM/ipcore_properties/gig_ethernet_pcs_pma_0.txt b/firmware/FT0/FTM_PM/ipcore_properties/gig_ethernet_pcs_pma_0.txt
@@ -65,7 +65,7 @@ CONFIG.SGMII_PHY_Mode                     string  false      false
 CONFIG.S_AXI.INSERT_VIP                   string  false      0
 CONFIG.S_AXI_ACLK.INSERT_VIP              string  false      0
 CONFIG.S_AXI_RESETN.INSERT_VIP            string  false      0
-CONFIG.Standard                           string  false      1000BASEX
+CONFIG.Standard                           string  false      BOTH
 CONFIG.SupportLevel                       string  false      Include_Shared_Logic_in_Example_Design
 CONFIG.TXOUTCLK_PORT.INSERT_VIP           string  false      0
 CONFIG.Timer_Format                       string  false      Time_of_day

diff --git a/firmware/FT0/FTM_PM/ipcore_properties/tri_mode_ethernet_mac_0.txt b/firmware/FT0/FTM_PM/ipcore_properties/tri_mode_ethernet_mac_0.txt
@@ -16,7 +16,7 @@ CONFIG.GTX_CLK_OUT.INSERT_VIP        string  false      0
 CONFIG.Half_Duplex                   string  false      false
 CONFIG.Int_Clk_Src                   string  false      user_clk2
 CONFIG.Int_Mode_Type                 string  false      BASEX
-CONFIG.MAC_Speed                     string  false      1000_Mbps
+CONFIG.MAC_Speed                     string  false      Tri_speed
 CONFIG.MDIO_BOARD_INTERFACE          string  false      Custom
 CONFIG.MII_IO                        string  false      true
 CONFIG.M_AXIS_RX.INSERT_VIP          string  false      0

diff --git a/firmware/FT0/FTM_PM/xdc/FIT_GBT_kc705_io.xdc b/firmware/FT0/FTM_PM/xdc/FIT_GBT_kc705_io.xdc
@@ -34,6 +34,9 @@ set_property PACKAGE_PIN B25 [get_ports FMC_HPC_clk_A_n]
 
 set_property PACKAGE_PIN H24 [get_ports LAS_EN]
 set_property IOSTANDARD LVCMOS25 [get_ports LAS_EN]
+set_property IOSTANDARD LVCMOS25 [get_ports SCOPE]
+set_property PACKAGE_PIN E28 [get_ports SCOPE]
+
 
 #set_property PACKAGE_PIN AG27 [get_ports TCM_TT0_P]
 #set_property PACKAGE_PIN AJ26 [get_ports TCM_TA1_P]
@@ -146,8 +149,8 @@ set_property IOSTANDARD LVCMOS15 [get_ports GPIO_LED_3]
 set_property IOSTANDARD LVCMOS15 [get_ports GPIO_LED_2]
 set_property IOSTANDARD LVCMOS25 [get_ports GPIO_LED_4]
 set_property IOSTANDARD LVCMOS25 [get_ports GPIO_LED_6]
-set_property IOSTANDARD LVCMOS15 [get_ports GPIO_LED_7]
-set_property IOSTANDARD LVCMOS15 [get_ports GPIO_BUTTON_SW_C]
+set_property IOSTANDARD LVCMOS25 [get_ports GPIO_LED_7]
+set_property IOSTANDARD LVCMOS25 [get_ports GPIO_BUTTON_SW_C]
 set_property IOSTANDARD LVCMOS25 [get_ports GPIO_LED_5]
 #set_property IOSTANDARD LVCMOS25 [get_ports GPIO_SMA_J13]
 #set_property IOSTANDARD LVCMOS25 [get_ports GPIO_SMA_J14]
@@ -246,3 +249,26 @@ set_property CFGBVS VCCO [current_design]
 set_property PACKAGE_PIN Y29 [get_ports GPIO_DIP_SW0]
 set_property IOSTANDARD LVCMOS25 [get_ports GPIO_DIP_SW0]
 
+
+set_property OFFCHIP_TERM NONE [get_ports GPIO_SMA_J13]
+set_property OFFCHIP_TERM NONE [get_ports TCM_SPI_MOSI]
+set_property OFFCHIP_TERM NONE [get_ports TCM_SPI_SCK]
+set_property OFFCHIP_TERM NONE [get_ports TCM_SPI_SEL]
+set_property OFFCHIP_TERM NONE [get_ports LA[15]]
+set_property OFFCHIP_TERM NONE [get_ports LA[14]]
+set_property OFFCHIP_TERM NONE [get_ports LA[13]]
+set_property OFFCHIP_TERM NONE [get_ports LA[12]]
+set_property OFFCHIP_TERM NONE [get_ports LA[11]]
+set_property OFFCHIP_TERM NONE [get_ports LA[10]]
+set_property OFFCHIP_TERM NONE [get_ports LA[9]]
+set_property OFFCHIP_TERM NONE [get_ports LA[8]]
+set_property OFFCHIP_TERM NONE [get_ports LA[7]]
+set_property OFFCHIP_TERM NONE [get_ports LA[6]]
+set_property OFFCHIP_TERM NONE [get_ports LA[5]]
+set_property OFFCHIP_TERM NONE [get_ports LA[4]]
+set_property OFFCHIP_TERM NONE [get_ports LA[3]]
+set_property OFFCHIP_TERM NONE [get_ports LA[2]]
+set_property OFFCHIP_TERM NONE [get_ports LA[1]]
+set_property OFFCHIP_TERM NONE [get_ports LA[0]]
+set_property OFFCHIP_TERM NONE [get_ports sfp_rate_sel[1]]
+set_property OFFCHIP_TERM NONE [get_ports sfp_rate_sel[0]]
diff --git a/firmware/FT0/FTM_TCM/ipcore_properties/gig_ethernet_pcs_pma_0.txt b/firmware/FT0/FTM_TCM/ipcore_properties/gig_ethernet_pcs_pma_0.txt
@@ -65,7 +65,7 @@ CONFIG.SGMII_PHY_Mode                     string  false      false
 CONFIG.S_AXI.INSERT_VIP                   string  false      0
 CONFIG.S_AXI_ACLK.INSERT_VIP              string  false      0
 CONFIG.S_AXI_RESETN.INSERT_VIP            string  false      0
-CONFIG.Standard                           string  false      1000BASEX
+CONFIG.Standard                           string  false      BOTH
 CONFIG.SupportLevel                       string  false      Include_Shared_Logic_in_Example_Design
 CONFIG.TXOUTCLK_PORT.INSERT_VIP           string  false      0
 CONFIG.Timer_Format                       string  false      Time_of_day

diff --git a/firmware/FT0/FTM_TCM/ipcore_properties/tri_mode_ethernet_mac_0.txt b/firmware/FT0/FTM_TCM/ipcore_properties/tri_mode_ethernet_mac_0.txt
@@ -16,7 +16,7 @@ CONFIG.GTX_CLK_OUT.INSERT_VIP        string  false      0
 CONFIG.Half_Duplex                   string  false      false
 CONFIG.Int_Clk_Src                   string  false      user_clk2
 CONFIG.Int_Mode_Type                 string  false      BASEX
-CONFIG.MAC_Speed                     string  false      1000_Mbps
+CONFIG.MAC_Speed                     string  false      Tri_speed
 CONFIG.MDIO_BOARD_INTERFACE          string  false      Custom
 CONFIG.MII_IO                        string  false      true
 CONFIG.M_AXIS_RX.INSERT_VIP          string  false      0

diff --git a/firmware/FT0/FTM_TCM/xdc/FIT_GBT_kc705_io.xdc b/firmware/FT0/FTM_TCM/xdc/FIT_GBT_kc705_io.xdc
@@ -34,6 +34,9 @@ set_property PACKAGE_PIN B25 [get_ports FMC_HPC_clk_A_n]
 
 set_property PACKAGE_PIN H24 [get_ports LAS_EN]
 set_property IOSTANDARD LVCMOS25 [get_ports LAS_EN]
+set_property IOSTANDARD LVCMOS25 [get_ports SCOPE]
+set_property PACKAGE_PIN E28 [get_ports SCOPE]
+
 
 #set_property PACKAGE_PIN AG27 [get_ports TCM_TT0_P]
 #set_property PACKAGE_PIN AJ26 [get_ports TCM_TA1_P]
@@ -103,8 +106,6 @@ set_property PACKAGE_PIN AF28 [get_ports {LA[0]}]
 
 # ============================================================
 
-set_property IOSTANDARD LVCMOS25 [get_ports SCOPE]
-set_property PACKAGE_PIN E28 [get_ports SCOPE]
 
 set_property IOSTANDARD LVDS_25 [get_ports LAS_D_N]
 set_property IOSTANDARD LVDS_25 [get_ports LAS_D_P]
@@ -148,8 +149,8 @@ set_property IOSTANDARD LVCMOS15 [get_ports GPIO_LED_3]
 set_property IOSTANDARD LVCMOS15 [get_ports GPIO_LED_2]
 set_property IOSTANDARD LVCMOS25 [get_ports GPIO_LED_4]
 set_property IOSTANDARD LVCMOS25 [get_ports GPIO_LED_6]
-set_property IOSTANDARD LVCMOS15 [get_ports GPIO_LED_7]
-set_property IOSTANDARD LVCMOS15 [get_ports GPIO_BUTTON_SW_C]
+set_property IOSTANDARD LVCMOS25 [get_ports GPIO_LED_7]
+set_property IOSTANDARD LVCMOS25 [get_ports GPIO_BUTTON_SW_C]
 set_property IOSTANDARD LVCMOS25 [get_ports GPIO_LED_5]
 #set_property IOSTANDARD LVCMOS25 [get_ports GPIO_SMA_J13]
 #set_property IOSTANDARD LVCMOS25 [get_ports GPIO_SMA_J14]
@@ -249,36 +250,25 @@ set_property PACKAGE_PIN Y29 [get_ports GPIO_DIP_SW0]
 set_property IOSTANDARD LVCMOS25 [get_ports GPIO_DIP_SW0]
 
 
-set_property MARK_DEBUG true [get_nets IsRxData_rxclk_from_GBT]
-connect_debug_port u_ila_0/probe1 [get_nets [list IsRxData_rxclk_from_GBT]]
-
-create_debug_core u_ila_0 ila
-set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
-set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0]
-set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0]
-set_property C_DATA_DEPTH 4096 [get_debug_cores u_ila_0]
-set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0]
-set_property C_INPUT_PIPE_STAGES 3 [get_debug_cores u_ila_0]
-set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
-set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
-set_property port_width 1 [get_debug_ports u_ila_0/clk]
-connect_debug_port u_ila_0/clk [get_nets [list CDMClkpllcomp/inst/CLK_OUT1_40]]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
-set_property port_width 80 [get_debug_ports u_ila_0/probe0]
-connect_debug_port u_ila_0/probe0 [get_nets [list {Data_from_FITrd[0]} {Data_from_FITrd[1]} {Data_from_FITrd[2]} {Data_from_FITrd[3]} {Data_from_FITrd[4]} {Data_from_FITrd[5]} {Data_from_FITrd[6]} {Data_from_FITrd[7]} {Data_from_FITrd[8]} {Data_from_FITrd[9]} {Data_from_FITrd[10]} {Data_from_FITrd[11]} {Data_from_FITrd[12]} {Data_from_FITrd[13]} {Data_from_FITrd[14]} {Data_from_FITrd[15]} {Data_from_FITrd[16]} {Data_from_FITrd[17]} {Data_from_FITrd[18]} {Data_from_FITrd[19]} {Data_from_FITrd[20]} {Data_from_FITrd[21]} {Data_from_FITrd[22]} {Data_from_FITrd[23]} {Data_from_FITrd[24]} {Data_from_FITrd[25]} {Data_from_FITrd[26]} {Data_from_FITrd[27]} {Data_from_FITrd[28]} {Data_from_FITrd[29]} {Data_from_FITrd[30]} {Data_from_FITrd[31]} {Data_from_FITrd[32]} {Data_from_FITrd[33]} {Data_from_FITrd[34]} {Data_from_FITrd[35]} {Data_from_FITrd[36]} {Data_from_FITrd[37]} {Data_from_FITrd[38]} {Data_from_FITrd[39]} {Data_from_FITrd[40]} {Data_from_FITrd[41]} {Data_from_FITrd[42]} {Data_from_FITrd[43]} {Data_from_FITrd[44]} {Data_from_FITrd[45]} {Data_from_FITrd[46]} {Data_from_FITrd[47]} {Data_from_FITrd[48]} {Data_from_FITrd[49]} {Data_from_FITrd[50]} {Data_from_FITrd[51]} {Data_from_FITrd[52]} {Data_from_FITrd[53]} {Data_from_FITrd[54]} {Data_from_FITrd[55]} {Data_from_FITrd[56]} {Data_from_FITrd[57]} {Data_from_FITrd[58]} {Data_from_FITrd[59]} {Data_from_FITrd[60]} {Data_from_FITrd[61]} {Data_from_FITrd[62]} {Data_from_FITrd[63]} {Data_from_FITrd[64]} {Data_from_FITrd[65]} {Data_from_FITrd[66]} {Data_from_FITrd[67]} {Data_from_FITrd[68]} {Data_from_FITrd[69]} {Data_from_FITrd[70]} {Data_from_FITrd[71]} {Data_from_FITrd[72]} {Data_from_FITrd[73]} {Data_from_FITrd[74]} {Data_from_FITrd[75]} {Data_from_FITrd[76]} {Data_from_FITrd[77]} {Data_from_FITrd[78]} {Data_from_FITrd[79]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
-set_property port_width 80 [get_debug_ports u_ila_0/probe1]
-connect_debug_port u_ila_0/probe1 [get_nets [list {FitGbtPrg/RX_Data_DataClk[0]} {FitGbtPrg/RX_Data_DataClk[1]} {FitGbtPrg/RX_Data_DataClk[2]} {FitGbtPrg/RX_Data_DataClk[3]} {FitGbtPrg/RX_Data_DataClk[4]} {FitGbtPrg/RX_Data_DataClk[5]} {FitGbtPrg/RX_Data_DataClk[6]} {FitGbtPrg/RX_Data_DataClk[7]} {FitGbtPrg/RX_Data_DataClk[8]} {FitGbtPrg/RX_Data_DataClk[9]} {FitGbtPrg/RX_Data_DataClk[10]} {FitGbtPrg/RX_Data_DataClk[11]} {FitGbtPrg/RX_Data_DataClk[12]} {FitGbtPrg/RX_Data_DataClk[13]} {FitGbtPrg/RX_Data_DataClk[14]} {FitGbtPrg/RX_Data_DataClk[15]} {FitGbtPrg/RX_Data_DataClk[16]} {FitGbtPrg/RX_Data_DataClk[17]} {FitGbtPrg/RX_Data_DataClk[18]} {FitGbtPrg/RX_Data_DataClk[19]} {FitGbtPrg/RX_Data_DataClk[20]} {FitGbtPrg/RX_Data_DataClk[21]} {FitGbtPrg/RX_Data_DataClk[22]} {FitGbtPrg/RX_Data_DataClk[23]} {FitGbtPrg/RX_Data_DataClk[24]} {FitGbtPrg/RX_Data_DataClk[25]} {FitGbtPrg/RX_Data_DataClk[26]} {FitGbtPrg/RX_Data_DataClk[27]} {FitGbtPrg/RX_Data_DataClk[28]} {FitGbtPrg/RX_Data_DataClk[29]} {FitGbtPrg/RX_Data_DataClk[30]} {FitGbtPrg/RX_Data_DataClk[31]} {FitGbtPrg/RX_Data_DataClk[32]} {FitGbtPrg/RX_Data_DataClk[33]} {FitGbtPrg/RX_Data_DataClk[34]} {FitGbtPrg/RX_Data_DataClk[35]} {FitGbtPrg/RX_Data_DataClk[36]} {FitGbtPrg/RX_Data_DataClk[37]} {FitGbtPrg/RX_Data_DataClk[38]} {FitGbtPrg/RX_Data_DataClk[39]} {FitGbtPrg/RX_Data_DataClk[40]} {FitGbtPrg/RX_Data_DataClk[41]} {FitGbtPrg/RX_Data_DataClk[42]} {FitGbtPrg/RX_Data_DataClk[43]} {FitGbtPrg/RX_Data_DataClk[44]} {FitGbtPrg/RX_Data_DataClk[45]} {FitGbtPrg/RX_Data_DataClk[46]} {FitGbtPrg/RX_Data_DataClk[47]} {FitGbtPrg/RX_Data_DataClk[48]} {FitGbtPrg/RX_Data_DataClk[49]} {FitGbtPrg/RX_Data_DataClk[50]} {FitGbtPrg/RX_Data_DataClk[51]} {FitGbtPrg/RX_Data_DataClk[52]} {FitGbtPrg/RX_Data_DataClk[53]} {FitGbtPrg/RX_Data_DataClk[54]} {FitGbtPrg/RX_Data_DataClk[55]} {FitGbtPrg/RX_Data_DataClk[56]} {FitGbtPrg/RX_Data_DataClk[57]} {FitGbtPrg/RX_Data_DataClk[58]} {FitGbtPrg/RX_Data_DataClk[59]} {FitGbtPrg/RX_Data_DataClk[60]} {FitGbtPrg/RX_Data_DataClk[61]} {FitGbtPrg/RX_Data_DataClk[62]} {FitGbtPrg/RX_Data_DataClk[63]} {FitGbtPrg/RX_Data_DataClk[64]} {FitGbtPrg/RX_Data_DataClk[65]} {FitGbtPrg/RX_Data_DataClk[66]} {FitGbtPrg/RX_Data_DataClk[67]} {FitGbtPrg/RX_Data_DataClk[68]} {FitGbtPrg/RX_Data_DataClk[69]} {FitGbtPrg/RX_Data_DataClk[70]} {FitGbtPrg/RX_Data_DataClk[71]} {FitGbtPrg/RX_Data_DataClk[72]} {FitGbtPrg/RX_Data_DataClk[73]} {FitGbtPrg/RX_Data_DataClk[74]} {FitGbtPrg/RX_Data_DataClk[75]} {FitGbtPrg/RX_Data_DataClk[76]} {FitGbtPrg/RX_Data_DataClk[77]} {FitGbtPrg/RX_Data_DataClk[78]} {FitGbtPrg/RX_Data_DataClk[79]}]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
-set_property port_width 1 [get_debug_ports u_ila_0/probe2]
-connect_debug_port u_ila_0/probe2 [get_nets [list FitGbtPrg/RX_IsData_DataClk]]
-create_debug_port u_ila_0 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
-set_property port_width 1 [get_debug_ports u_ila_0/probe3]
-connect_debug_port u_ila_0/probe3 [get_nets [list IsData_from_FITrd]]
-set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
-set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
-set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
-connect_debug_port dbg_hub/clk [get_nets GPIO_SMA_J13_OBUF]
+set_property OFFCHIP_TERM NONE [get_ports GPIO_SMA_J13]
+set_property OFFCHIP_TERM NONE [get_ports TCM_SPI_MOSI]
+set_property OFFCHIP_TERM NONE [get_ports TCM_SPI_SCK]
+set_property OFFCHIP_TERM NONE [get_ports TCM_SPI_SEL]
+set_property OFFCHIP_TERM NONE [get_ports LA[15]]
+set_property OFFCHIP_TERM NONE [get_ports LA[14]]
+set_property OFFCHIP_TERM NONE [get_ports LA[13]]
+set_property OFFCHIP_TERM NONE [get_ports LA[12]]
+set_property OFFCHIP_TERM NONE [get_ports LA[11]]
+set_property OFFCHIP_TERM NONE [get_ports LA[10]]
+set_property OFFCHIP_TERM NONE [get_ports LA[9]]
+set_property OFFCHIP_TERM NONE [get_ports LA[8]]
+set_property OFFCHIP_TERM NONE [get_ports LA[7]]
+set_property OFFCHIP_TERM NONE [get_ports LA[6]]
+set_property OFFCHIP_TERM NONE [get_ports LA[5]]
+set_property OFFCHIP_TERM NONE [get_ports LA[4]]
+set_property OFFCHIP_TERM NONE [get_ports LA[3]]
+set_property OFFCHIP_TERM NONE [get_ports LA[2]]
+set_property OFFCHIP_TERM NONE [get_ports LA[1]]
+set_property OFFCHIP_TERM NONE [get_ports LA[0]]
+set_property OFFCHIP_TERM NONE [get_ports sfp_rate_sel[1]]
+set_property OFFCHIP_TERM NONE [get_ports sfp_rate_sel[0]]
diff --git a/firmware/FT0/TCM/ipcore_properties/gig_ethernet_pcs_pma_0.txt b/firmware/FT0/TCM/ipcore_properties/gig_ethernet_pcs_pma_0.txt
@@ -65,7 +65,7 @@ CONFIG.SGMII_PHY_Mode                     string  false      false
 CONFIG.S_AXI.INSERT_VIP                   string  false      0
 CONFIG.S_AXI_ACLK.INSERT_VIP              string  false      0
 CONFIG.S_AXI_RESETN.INSERT_VIP            string  false      0
-CONFIG.Standard                           string  false      1000BASEX
+CONFIG.Standard                           string  false      BOTH
 CONFIG.SupportLevel                       string  false      Include_Shared_Logic_in_Example_Design
 CONFIG.TXOUTCLK_PORT.INSERT_VIP           string  false      0
 CONFIG.Timer_Format                       string  false      Time_of_day

diff --git a/firmware/FT0/TCM/ipcore_properties/tri_mode_ethernet_mac_0.txt b/firmware/FT0/TCM/ipcore_properties/tri_mode_ethernet_mac_0.txt
@@ -16,7 +16,7 @@ CONFIG.GTX_CLK_OUT.INSERT_VIP        string  false      0
 CONFIG.Half_Duplex                   string  false      false
 CONFIG.Int_Clk_Src                   string  false      user_clk2
 CONFIG.Int_Mode_Type                 string  false      BASEX
-CONFIG.MAC_Speed                     string  false      1000_Mbps
+CONFIG.MAC_Speed                     string  false      Tri_speed
 CONFIG.MDIO_BOARD_INTERFACE          string  false      Custom
 CONFIG.MII_IO                        string  false      true
 CONFIG.M_AXIS_RX.INSERT_VIP          string  false      0

diff --git a/firmware/FT0/TCM_v1/ipcore_properties/LCLK_PLL.txt b/firmware/FT0/TCM_v1/ipcore_properties/LCLK_PLL.txt
@@ -98,6 +98,10 @@ CONFIG.CLK_OUT6_USE_FINE_PS_GUI      string  false      false
 CONFIG.CLK_OUT7_PORT                 string  false      clk_out7
 CONFIG.CLK_OUT7_USE_FINE_PS_GUI      string  false      false
 CONFIG.CLK_VALID_PORT                string  false      CLK_VALID
+CONFIG.CLOCK_CLKFB_IN.INSERT_VIP     string  false      0
+CONFIG.CLOCK_CLKFB_OUT.INSERT_VIP    string  false      0
+CONFIG.CLOCK_CLK_IN1.INSERT_VIP      string  false      0
+CONFIG.CLOCK_CLK_OUT1.INSERT_VIP     string  false      0
 CONFIG.CLOCK_MGR_TYPE                string  false      auto
 CONFIG.Component_Name                string  false      LCLK_PLL
 CONFIG.DADDR_PORT                    string  false      daddr

diff --git a/firmware/FT0/TCM_v1/ipcore_properties/MMCM125ETH.txt b/firmware/FT0/TCM_v1/ipcore_properties/MMCM125ETH.txt
@@ -98,6 +98,9 @@ CONFIG.CLK_OUT6_USE_FINE_PS_GUI      string  false      false
 CONFIG.CLK_OUT7_PORT                 string  false      clk_out7
 CONFIG.CLK_OUT7_USE_FINE_PS_GUI      string  false      false
 CONFIG.CLK_VALID_PORT                string  false      CLK_VALID
+CONFIG.CLOCK_CLK_IN1.INSERT_VIP      string  false      0
+CONFIG.CLOCK_CLK_OUT1.INSERT_VIP     string  false      0
+CONFIG.CLOCK_CLK_OUT2.INSERT_VIP     string  false      0
 CONFIG.CLOCK_MGR_TYPE                string  false      auto
 CONFIG.Component_Name                string  false      MMCM125ETH
 CONFIG.DADDR_PORT                    string  false      daddr

diff --git a/firmware/FT0/TCM_v1/ipcore_properties/MMCM320_PH.txt b/firmware/FT0/TCM_v1/ipcore_properties/MMCM320_PH.txt
@@ -98,6 +98,10 @@ CONFIG.CLK_OUT6_USE_FINE_PS_GUI      string  false      false
 CONFIG.CLK_OUT7_PORT                 string  false      clk_out7
 CONFIG.CLK_OUT7_USE_FINE_PS_GUI      string  false      false
 CONFIG.CLK_VALID_PORT                string  false      CLK_VALID
+CONFIG.CLOCK_CLK_IN1.INSERT_VIP      string  false      0
+CONFIG.CLOCK_CLK_OUT1.INSERT_VIP     string  false      0
+CONFIG.CLOCK_CLK_OUT2.INSERT_VIP     string  false      0
+CONFIG.CLOCK_CLK_OUT3.INSERT_VIP     string  false      0
 CONFIG.CLOCK_MGR_TYPE                string  false      auto
 CONFIG.Component_Name                string  false      MMCM320_PH
 CONFIG.DADDR_PORT                    string  false      daddr

diff --git a/firmware/FT0/TCM_v1/ipcore_properties/PLL125.txt b/firmware/FT0/TCM_v1/ipcore_properties/PLL125.txt
@@ -98,6 +98,10 @@ CONFIG.CLK_OUT6_USE_FINE_PS_GUI      string  false      false
 CONFIG.CLK_OUT7_PORT                 string  false      clk_out7
 CONFIG.CLK_OUT7_USE_FINE_PS_GUI      string  false      false
 CONFIG.CLK_VALID_PORT                string  false      CLK_VALID
+CONFIG.CLOCK_CLK_IN1.INSERT_VIP      string  false      0
+CONFIG.CLOCK_CLK_OUT1.INSERT_VIP     string  false      0
+CONFIG.CLOCK_CLK_OUT2.INSERT_VIP     string  false      0
+CONFIG.CLOCK_CLK_OUT3.INSERT_VIP     string  false      0
 CONFIG.CLOCK_MGR_TYPE                string  false      auto
 CONFIG.Component_Name                string  false      PLL125
 CONFIG.DADDR_PORT                    string  false      daddr

diff --git a/firmware/FT0/TCM_v1/ipcore_properties/gig_ethernet_pcs_pma_0.txt b/firmware/FT0/TCM_v1/ipcore_properties/gig_ethernet_pcs_pma_0.txt
@@ -65,7 +65,7 @@ CONFIG.SGMII_PHY_Mode                     string  false      false
 CONFIG.S_AXI.INSERT_VIP                   string  false      0
 CONFIG.S_AXI_ACLK.INSERT_VIP              string  false      0
 CONFIG.S_AXI_RESETN.INSERT_VIP            string  false      0
-CONFIG.Standard                           string  false      1000BASEX
+CONFIG.Standard                           string  false      BOTH
 CONFIG.SupportLevel                       string  false      Include_Shared_Logic_in_Example_Design
 CONFIG.TXOUTCLK_PORT.INSERT_VIP           string  false      0
 CONFIG.Timer_Format                       string  false      Time_of_day

diff --git a/firmware/FT0/TCM_v1/ipcore_properties/tri_mode_ethernet_mac_0.txt b/firmware/FT0/TCM_v1/ipcore_properties/tri_mode_ethernet_mac_0.txt
@@ -16,7 +16,7 @@ CONFIG.GTX_CLK_OUT.INSERT_VIP        string  false      0
 CONFIG.Half_Duplex                   string  false      false
 CONFIG.Int_Clk_Src                   string  false      user_clk2
 CONFIG.Int_Mode_Type                 string  false      BASEX
-CONFIG.MAC_Speed                     string  false      1000_Mbps
+CONFIG.MAC_Speed                     string  false      Tri_speed
 CONFIG.MDIO_BOARD_INTERFACE          string  false      Custom
 CONFIG.MII_IO                        string  false      true
 CONFIG.M_AXIS_RX.INSERT_VIP          string  false      0

diff --git a/firmware/FT0/TCM_v1/ipcore_properties/xlx_k7v7_gbt_rx_frameclk_phalgnr_mmcm.txt b/firmware/FT0/TCM_v1/ipcore_properties/xlx_k7v7_gbt_rx_frameclk_phalgnr_mmcm.txt
@@ -98,6 +98,8 @@ CONFIG.CLK_OUT6_USE_FINE_PS_GUI      string  false      false
 CONFIG.CLK_OUT7_PORT                 string  false      clk_out7
 CONFIG.CLK_OUT7_USE_FINE_PS_GUI      string  false      false
 CONFIG.CLK_VALID_PORT                string  false      CLK_VALID
+CONFIG.CLOCK_CLK_IN1.INSERT_VIP      string  false      0
+CONFIG.CLOCK_CLK_OUT1.INSERT_VIP     string  false      0
 CONFIG.CLOCK_MGR_TYPE                string  false      auto
 CONFIG.Component_Name                string  false      xlx_k7v7_gbt_rx_frameclk_phalgnr_mmcm
 CONFIG.DADDR_PORT                    string  false      daddr

diff --git a/firmware/common/ftm/hdl/FIT_TESTMODULE_IPBUS_sender.vhd b/firmware/common/ftm/hdl/FIT_TESTMODULE_IPBUS_sender.vhd
@@ -114,11 +114,11 @@ architecture Behavioral of FIT_TESTMODULE_IPBUS_sender is
 
 	attribute mark_debug : string;
 
-    attribute MARK_DEBUG of Control_register_reg_dc : signal is "true";
-    attribute MARK_DEBUG of FIT_GBT_status : signal is "true";
+--    attribute MARK_DEBUG of Control_register_reg_dc : signal is "true";
+--    attribute MARK_DEBUG of FIT_GBT_status : signal is "true";
 
-    attribute MARK_DEBUG of data_fifo_datain : signal is "true";
-    attribute MARK_DEBUG of data_fifo_wren : signal is "true";
+--    attribute MARK_DEBUG of data_fifo_datain : signal is "true";
+--    attribute MARK_DEBUG of data_fifo_wren : signal is "true";
 
 
 begin