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upgrate while tests at CERN Apr 21
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- SGMII/BASE-X autodetect improved to work with switch capable of both protocols on optical transceivers.
- HDMI link synchronization algorithm fixes.
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Dmitry Finogeev committed Apr 25, 2021
1 parent 61b4c93 commit 03cb4ae
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Showing 3 changed files with 48 additions and 25 deletions.
9 changes: 5 additions & 4 deletions firmware/FT0/TCM_proto/hdl/HDMIRX.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -58,7 +58,8 @@ entity hdmirx is
bp_stable : out STD_LOGIC;
dl_low : out STD_LOGIC;
dl_high : out STD_LOGIC;
mast_dl_err : out STD_LOGIC;
mast_dl_low : out STD_LOGIC;
mast_dl_high : out STD_LOGIC;
mast_stable : out STD_LOGIC;
dly_ctrl_ena : in STD_LOGIC;
syn_err : out STD_LOGIC;
Expand Down Expand Up @@ -187,7 +188,7 @@ if (dvalue(i)="11111") then dl_high_i(i)<= '1'; else dl_high_i(i)<='0'; end if;
else
if ( mast_stable_i='1') then
if (edge(i)='1') then
if ((ph_cnt(i)="11111") and (el(i)='1') and (dl_high_i(i)='0')) or ((ph_cnt(i)="00000") and (el(i)='0') and (dl_low_i(i)='0')) then dl_ce(i)<='1'; dl_inc(i)<=el(i); ph_cnt(i)<="01111";
if ((ph_cnt(i)="11110") and (el(i)='1') and (dl_high_i(i)='0')) or ((ph_cnt(i)=0) and (el(i)='0') and (dl_low_i(i)='0')) then dl_ce(i)<='1'; dl_inc(i)<=el(i); ph_cnt(i)<="01111";
else
if (el(i)='1') then ph_cnt(i)<=ph_cnt(i)+1; else ph_cnt(i)<=ph_cnt(i)-1; end if;
end if;
Expand All @@ -210,7 +211,7 @@ if (dvalue(i)="11111") then dl_high_i(i)<= '1'; else dl_high_i(i)<='0'; end if;
if (rst='1') or (sig_lost(0)='1') or (ena='0') or ((master='0') and (dly_ctrl_ena='0')) then ph_cnt(0)<="01111";
else
if (edge(0)='1') then
if ((ph_cnt(0)="11111") and (el(0)='1') and (dl_high_i(0)='0')) or ((ph_cnt(0)="00000") and (el(0)='0') and (dl_low_i(0)='0')) then dl_ce0<='1';
if ((ph_cnt(0)="11110") and (el(0)='1') and (dl_high_i(0)='0')) or ((ph_cnt(0)=0) and (el(0)='0') and (dl_low_i(0)='0')) then dl_ce0<='1';
dl_inc0<=el(0); ph_cnt(0)<="01111";
else
if (el(0)='1') then ph_cnt(0)<=ph_cnt(0)+1; else ph_cnt(0)<=ph_cnt(0)-1; end if;
Expand Down Expand Up @@ -283,7 +284,7 @@ end generate;

dl_low0<= ena when (dl_low_i(3 downto 1)/="000") or ((master='0') and (dl_low_i(0)='1')) else '0';
dl_high0<= ena when (dl_high_i(3 downto 1)/="000") or ((master='0') and (dl_high_i(0)='1')) else '0';
mast_dl_err <= dl_low_i(0) or dl_high_i(0);
mast_dl_low <= dl_low_i(0); mast_dl_high <= dl_high_i(0);

TLogic: for i in 0 to 7 generate
TDV(i)<= (TTsr(0)(i) and TTsr(1)(i) and TTsr(2)(i) and TTsr(3)(i));
Expand Down
20 changes: 17 additions & 3 deletions firmware/FT0/TCM_proto/hdl/tcm_proto.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -203,7 +203,8 @@ signal TimeC, TimeC0, TimeC1, TimeC2, TimeA : STD_LOGIC_VECTOR (8 downto 0);
signal TimeA_o, TimeC_o : STD_LOGIC_VECTOR (15 downto 0);
signal AvgA, AvgC : STD_LOGIC_VECTOR (13 downto 0);
signal TresbM, TdiffM : STD_LOGIC_VECTOR (23 downto 0);
signal hdmiac_select, hdmicc_select, hdmias_select, hdmics_select, pll_lock_a, pll_lock_c, hdmis_ack, mul_ena, mul_enc, sideA_OK, sideC_OK, stat_clrA, stat_clrC, as_chg, cs_chg, rst_fl : STD_LOGIC;
signal hdmiac_select, hdmicc_select, hdmias_select, hdmics_select, pll_lock_a, pll_lock_c, hdmis_ack, mul_ena, mul_enc, sideA_OK, sideC_OK, stat_clrA, stat_clrC, as_chg, cs_chg, rst_fl, as_blk, cs_blk, hdmi_to0, hdmi_to : STD_LOGIC;
signal PM_tcou : STD_LOGIC_VECTOR (25 downto 0);
signal dly_rst, cnt_rd, pm_adr_sel, pm_rdy, cnt_ctrl_sel, cnt_ctrl_rdy, ipb_locked, cnt_clr, cnt_lock, Tcnt_sel, Tcnt_0_rd, cnt_lock0, cnt_lock1, cnt_lock2, Tcnt_clr, cnt_clr0, cnt_clr1, cnt_clr2, Tcnt_ack, Tcnt_err : STD_LOGIC;
signal fifo_sel, fifo_csel, f_rd, f_empty, f_wr, f_full, lclk160, lmode_sel, lpatt0_sel, lpatt1_sel, l_on, l_on0, l_on1, l_tg1, l_tg, l_fbin, l_fbout, a_t, a0_t, an_t : STD_LOGIC;
signal l_cnt : STD_LOGIC_VECTOR (1 downto 0);
Expand Down Expand Up @@ -1077,10 +1078,10 @@ end if;
end if;
end process;

tcma: tcm_side port map(CLKA=>CLKA, RST=>reset, SRST=>sreset, TD_P=>TDA_P, TD_N=>TDA_N, Config=>hdmia_config, Status=>Status_a, stat_adr=> ipb_addr(3 downto 0), stat_clr=>stat_clrA, stat_chg=>as_chg, side_OK=>sideA_OK, TDD=>TDA, rd_lock=> rd_lock_a,
tcma: tcm_side port map(CLKA=>CLKA, RST=>reset, SRST=>sreset, TD_P=>TDA_P, TD_N=>TDA_N, Config=>hdmia_config, Status=>Status_a, stat_adr=> ipb_addr(3 downto 0), stat_clr=>stat_clrA, stat_chg=>as_blk, side_OK=>sideA_OK, TDD=>TDA, rd_lock=> rd_lock_a,
Or_o=>OrA_i, CLK320_o=>CLK320A, clksys40_o => clksys40, pll_lock=> pll_lock_a, mt_cou_o=>bitcnt_A, Time_o=>TimeA_o, Avg_o=>AvgA, Ampl_O=>AmplA, Nchan=> Nchan_A, req=> reqA, bkgnd=> bkgndA);

tcmc: tcm_side port map(CLKA=>CLKC, RST=>reset, SRST=>sreset, TD_P=>TDC_P, TD_N=>TDC_N, Config=>hdmic_config, Status=>Status_C, stat_adr=> ipb_addr(3 downto 0), stat_clr=>stat_clrC, stat_chg=>cs_chg, side_OK=>sideC_OK, TDD=>TDC0, rd_lock=> rd_lock_c,
tcmc: tcm_side port map(CLKA=>CLKC, RST=>reset, SRST=>sreset, TD_P=>TDC_P, TD_N=>TDC_N, Config=>hdmic_config, Status=>Status_C, stat_adr=> ipb_addr(3 downto 0), stat_clr=>stat_clrC, stat_chg=>cs_blk, side_OK=>sideC_OK, TDD=>TDC0, rd_lock=> rd_lock_c,
Or_o=>OrC_B, CLK320_o=>CLK320C, clksys40_o=> open, pll_lock=> pll_lock_c, mt_cou_o=>bitcnt_c, Time_o=>TimeC_o, Avg_o=>AvgC, Ampl_o=>AmplC0, Nchan=> Nchan_C0, req=> reqC, bkgnd=> bkgndC0);

TresbM<=TimeC(8) & TimeC & "00000000000000";
Expand Down Expand Up @@ -1173,6 +1174,10 @@ PM_rst <= rst_spi2 and (not rst_spi1);

bccorr_rd<= bccorr_sel or bccorrA_sel or bccorrC_sel; bccorr_ack<=bccorr_ack0 and bccorr_rd;

hdmi_to0<='1' when (PM_tcou/=31250000) else '0';
as_blk<=as_chg or hdmi_to; cs_blk<=cs_chg or hdmi_to;


process(ipb_clk)
begin
if (ipb_clk'event and ipb_clk='1') then
Expand Down Expand Up @@ -1210,8 +1215,17 @@ if (rst_spi1='1') then RST_req<='0'; clk_frs<='0';

end if;

if (ipb_rst='1') then hdmia_config<=(others=>'0'); hdmic_config<=(others=>'0');
else
hdmi_to<=hdmi_to0;
if (PM_rst='1') then PM_tcou<=(others=>'0');
else
if (hdmi_to0='1') then PM_tcou<=PM_tcou+1; end if;
end if;

if (hdmiac_select='1') and (ipb_iswr='1') then hdmia_config<=ipb_data_out; as_chg<='1'; end if;
if (hdmicc_select='1') and (ipb_iswr='1') then hdmic_config<=ipb_data_out; cs_chg<='1'; end if;
end if;

if (as_chg='1') then as_chg<='0'; end if; if (cs_chg='1') then cs_chg<='0'; end if;

Expand Down
44 changes: 26 additions & 18 deletions firmware/FT0/TCM_proto/hdl/tcm_side.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -98,13 +98,14 @@ signal inp_act : STD_LOGIC_VECTOR (9 downto 1);
signal HDMI_status : Trgdat;

signal clk320, clk320_90, trig_ena, done, done0, done_toggle, ena_dly, inc_dly, psen, ph_inc, link_OK, side_on, dly_inc, dly_dec, dly_err,dly_err_s, bitpos_ok, mdl_err, mdl_err_s, dly_ctrl_ena, stat_clr0, stat_clr1, stat_clr2 : STD_LOGIC;
signal rd_lock1, rd_lock0 : STD_LOGIC;
signal rd_lock1, rd_lock0, dly_ctrl_rdy : STD_LOGIC;
signal idle_cou : STD_LOGIC_VECTOR (5 downto 0);
signal mt_cou : STD_LOGIC_VECTOR (2 downto 0);
signal link_ena, link_OK_in, link_OK_act, master_sel, psen_o, ph_inc_o, is_idle, bp_stable, dl_low, dl_high, bitpos_ok_in, bitpos_ok_act, sig_empty, mast_dlerr, mast_stable, sync_err, sync_err_s: STD_LOGIC_VECTOR (9 downto 0);
signal link_ena, link_OK_in, link_OK_act, master_sel, psen_o, ph_inc_o, is_idle, bp_stable, dl_low, dl_high, bitpos_ok_in, bitpos_ok_act, sig_empty, mast_dl_low, mast_dl_high, mast_stable, sync_err, sync_err_s: STD_LOGIC_VECTOR (9 downto 0);
signal bitpos : vect3_arr;
signal master_n, N_empty0 : STD_LOGIC_VECTOR (3 downto 0);
signal adj_count : STD_LOGIC_VECTOR (7 downto 0);
signal mast_delay: STD_LOGIC_VECTOR (17 downto 0);

component hdmirx is
Port ( TD_P : in STD_LOGIC_VECTOR (3 downto 0);
Expand Down Expand Up @@ -132,7 +133,8 @@ component hdmirx is
bp_stable : out STD_LOGIC;
dl_low : out STD_LOGIC;
dl_high : out STD_LOGIC;
mast_dl_err : out STD_LOGIC;
mast_dl_low : out STD_LOGIC;
mast_dl_high : out STD_LOGIC;
mast_stable : out STD_LOGIC;
dly_ctrl_ena : in STD_LOGIC;
syn_err : out STD_LOGIC;
Expand Down Expand Up @@ -178,7 +180,7 @@ HDMIA: for i in 0 to 9 generate

HDMI_RX: hdmirx port map(TD_P=>TD_P(i), TD_N=>TD_N(i), RST=>SRST, ena=>link_ena(i), link_rdy=>link_OK_in(i), trig_ena=>done, clk320=>clk320, clk320_90=>clk320_90, TDO=>HDMI_in(i), rd_lock=>rd_lock1, DATA_OUT=> TDD(i),
status => HDMI_status(i), master=> master_sel(i), mt_cou=>mt_cou, bitpos=>bitpos(i), bitpos_ok=>bitpos_ok_in(i), ena_dly=>ena_dly, inc_dly=>inc_dly, ena_ph=>psen_o(i), inc_ph=>ph_inc_o(i), is_idle=>is_idle(i), bp_stable=>bp_stable(i),
dl_low=> dl_low(i), dl_high=> dl_high(i), mast_dl_err=>mast_dlerr(i), mast_stable=>mast_stable(i), dly_ctrl_ena=>dly_ctrl_ena, syn_err=>sync_err(i), PM_req=>req(i));
dl_low=> dl_low(i), dl_high=> dl_high(i), mast_dl_low=>mast_dl_low(i), mast_dl_high=>mast_dl_high(i), mast_stable=>mast_stable(i), dly_ctrl_ena=>dly_ctrl_ena, syn_err=>sync_err(i), PM_req=>req(i));
end generate;

ROM1 : ROM7x15 PORT MAP (clka => CLK320, addra => Nchan_A, douta => Avg_0);
Expand Down Expand Up @@ -208,21 +210,28 @@ msel: for i in 0 to 9 generate
side_on<='1' when (config(9 downto 0)/=0) else '0';
dly_dec<='1' when dl_high/=0 else '0';
dly_inc<='1' when dl_low/=0 else '0';
dly_err<= (dly_inc and dly_dec) or mdl_err;
dly_err<= (dly_inc and dly_dec) or (mast_dl_low(to_integer(unsigned(master_n))) and dly_dec) or (mast_dl_high(to_integer(unsigned(master_n))) and dly_inc);


link_OK<= '1' when (link_OK_act="1111111111") and (side_on='1') else '0';
bitpos_OK<= '1' when (bitpos_ok_act="1111111111") and (side_on='1') else '0';
dly_ctrl_ena<='1' when (mast_stable="1111111111") else '0';
dly_ctrl_rdy<='1' when (mast_stable="1111111111") else '0';

psen<= psen_o(to_integer(unsigned(master_n))) when (side_on='1') else '0';
ph_inc<= ph_inc_o(to_integer(unsigned(master_n))) when (side_on='1') else '0';
mdl_err<= mast_dlerr(to_integer(unsigned(master_n))) when (side_on='1') else '0';
mdl_err<= (mast_dl_low(to_integer(unsigned(master_n))) or mast_dl_high(to_integer(unsigned(master_n)))) when (side_on='1') and (dly_err='1') else '0';

process (clk320)
begin
if (clk320'event and clk320='1') then


if (dly_ctrl_rdy='0') then dly_ctrl_ena<='0'; mast_delay<=(others=>'0');
else
if (mast_delay/="11" & x"FFFF") then mast_delay<=mast_delay+1;
else dly_ctrl_ena<='1';
end if;
end if;

rd_lock1<=rd_lock0; rd_lock0<=rd_lock;
stat_clr2<=stat_clr1; stat_clr1<=stat_clr0; stat_clr0<=stat_clr;
done0<=done;
Expand Down Expand Up @@ -263,16 +272,15 @@ if (side_on='1') and (srst='0') then
else if (done='0') and (bitpos_OK='1') and (idle_cou>"010000") then done<='1'; end if;
end if;

if (link_OK_in(to_integer(unsigned(master_n)))='1') and (dly_err='0') then
if (adj_count/=x"FF") then adj_count<=adj_count+1;
else
if (dly_inc or dly_dec)='1' then adj_count<=x"00"; ena_dly<=dly_ctrl_ena; inc_dly<=dly_inc; end if;
end if;
else adj_count<=x"00";
end if;

if (ena_dly='1') then ena_dly<='0'; end if;
else done<='0'; idle_cou<="000000"; adj_count<=x"00";
if (link_OK_in(to_integer(unsigned(master_n)))='1') and (dly_err='0') and ((dly_inc or dly_dec)='1') then
adj_count<=adj_count+1;
if (adj_count=x"FF") then ena_dly<='1'; inc_dly<=dly_inc;
else ena_dly<='0';
end if;
else adj_count<=x"00"; ena_dly<='0';
end if;

else ena_dly<='0';
end if;


Expand Down

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