Welcome ! This repository introduces to the concept of a single core RISC-V processor ,For anyone interested in RISC-V based designs, this would be a good starting point. The features include
1)The Processor has been subjected to test environment for the verification of correct implementation of various features like supervisor mode , machine mode , floating-point extension and vector extensions. This is done with the help of macros written in assembly language.
2)A Linker Script for controlling for sections of how program are stored in memory.
3)Header Files written in assmebly for timer module to handle interrupts