Core(M): Correct Cortex-M55/M85 TPIU type and align core header

[ghost]

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Test Results

   152 files     152 suites   0s ⏱️
     56 tests      54 ✔️        2 💤 0 ❌
8 116 runs  6 260 ✔️ 1 856 💤 0 ❌

Results for commit f4e234b.

[JonatanAntoni]

@EdmundPlayer, can you comment on the identification registers?

[ghost]

For consistency reasons we we should either add 'Peripheral Identification Register' and 'Component Identification Register' to all Peripheral Units or remove them. It does not make sense to have them for just some peripheral units.
I decided to remove them.

[EdmundPlayer]

In the Armv7-M Architecture Reference Manual, these fall under "Optional CoreSight management and ID registers." However, in the Armv8-M Architecture Reference Manual, it looks like these registers have dedicated sections in the manual.

Although these registers could in theory be accessed by privileged software, I believe they're really intended to be accessed by a debug tool/driver via the CoreSight protocol.

I don't see any harm in adding these registers, as it could potentially be useful for people writing debug tools in C/C++. See PMU_Type in core_cm55.h, for example.

When there's already an architectural header like pmu_v8.h, it might make more sense to move these data structures into the separate header because then we won't have to keep duplicating the information across different core headers. If there is anything specific to a particular core, e.g., M85-specific PMU events, then we can still use the core header for that information.

For the TPIU, one minor change I'd make it to rename TPI to TPIU for the comments (to make TPIU a more searchable term), e.g.,

  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
  \brief    Type definitions for the Trace Port Interface (TPI)

should become

  \defgroup CMSIS_TPIU     Trace Port Interface (TPIU)
  \brief    Type definitions for the Trace Port Interface (TPIU)

assuming this doesn't break anything.