Fixup for Cortex-A

ARM-software · Oct 12, 2023 · c74aa02 · c74aa02
1 parent 38fd1d4
commit c74aa02
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Showing 7 changed files with 81 additions and 59 deletions.
diff --git a/.devcontainer/ubuntu-22.04/Dockerfile b/.devcontainer/ubuntu-22.04/Dockerfile
@@ -23,11 +23,14 @@ RUN pip install \
         lit \
         python-matrix-runner
 
+RUN bash -c "$(curl -fsSL https://raw.githubusercontent.com/ohmybash/oh-my-bash/master/tools/install.sh)" &&
+    sed -i 's/OSH_THEME="font"/OSH_THEME="powerline"/' ~/.bashrc
+
 ADD vcpkg-configuration.json /root/
 
 RUN pushd /root && \
     . <(curl https://aka.ms/vcpkg-init.sh -L) && \
-    echo ". /root/.vcpkg/vcpkg-init" >> .bashrc && \
+    echo "\n# Initialize vcpkg\n. /root/.vcpkg/vcpkg-init" >> .bashrc && \
     vcpkg x-update-registry --all && \
     vcpkg activate
 

diff --git a/CMSIS/Core/Test/clz_compat.c b/CMSIS/Core/Test/clz_compat.c
@@ -0,0 +1,18 @@
+// UNSUPPORTED: clz
+// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s
+
+#include "cmsis_compiler.h"
+
+static volatile uint32_t a = 10u;
+
+void clz() {
+    // CHECK-LABEL: <clz>:
+    // CHECK: cmp [[REG1:r[0-9]+]], #0x0
+    // CHECK: beq
+    // CHECK: lsrs [[REG2:r[0-9]+]], [[REG1]], #0x1
+    // CHECK: orrs [[REG2]], [[REG1]]
+    // CHECK: lsrs [[REG1]], [[REG2]], #0x2
+    volatile uint32_t c = __CLZ(a);
+    // CHECK: {{(bx lr)|(pop {.*pc})}}
+}
+
diff --git a/CMSIS/Core/Test/lit.cfg.py b/CMSIS/Core/Test/lit.cfg.py
@@ -45,7 +45,7 @@
         'mcpu': 'cortex-m3',
         'mfpu': 'none',
         'mpu': True,
-        'features': ['thumbv6m', 'thumbv7m', 'thumb-2', 'sat', 'ldrex'],
+        'features': ['thumbv6m', 'thumbv7m', 'thumb-2', 'sat', 'ldrex', 'clz'],
         'header': 'core_cm3.h',
         'defines': {
             '__CM3_REV': '0x0000U',
@@ -62,7 +62,7 @@
         'mcpu': 'cortex-m4',
         'mfpu': 'none',
         'mpu': True,
-        'features': ['thumbv6m', 'thumbv7m', 'thumbv7em', 'thumb-2', 'sat', 'ldrex'],
+        'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumb-2', 'sat', 'ldrex', 'clz'],
         'header': 'core_cm4.h',
         'defines': {
             '__CM4_REV': '0x0000U',
@@ -80,7 +80,7 @@
         'mcpu': 'cortex-m4',
         'mfpu': 'fpv4-sp-d16',
         'mpu': True,
-        'features': ['thumbv6m', 'thumbv7m', 'thumbv7em', 'thumb-2', 'sat', 'ldrex'],
+        'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumb-2', 'sat', 'ldrex', 'clz'],
         'header': 'core_cm4.h',
         'defines': {
             '__CM4_REV': '0x0000U',
@@ -98,7 +98,7 @@
         'mcpu': 'cortex-m7',
         'mfpu': 'none',
         'mpu': True,
-        'features': ['thumbv6m', 'thumbv7m', 'thumbv7em', 'thumb-2', 'sat', 'ldrex'],
+        'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumb-2', 'sat', 'ldrex', 'clz'],
         'header': 'core_cm7.h',
         'defines': {
             '__CM7_REV': '0x0000U',
@@ -119,7 +119,7 @@
         'mcpu': 'cortex-m7',
         'mfpu': 'fpv4-sp-d16',
         'mpu': True,
-        'features': ['thumbv6m', 'thumbv7m', 'thumbv7em', 'thumb-2', 'sat', 'ldrex'],
+        'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumb-2', 'sat', 'ldrex', 'clz'],
         'header': 'core_cm7.h',
         'defines': {
             '__CM7_REV': '0x0000U',
@@ -140,7 +140,7 @@
         'mcpu': 'cortex-m7',
         'mfpu': 'fpv5-d16',
         'mpu': True,
-        'features': ['thumbv6m', 'thumbv7m', 'thumbv7em', 'thumb-2', 'sat', 'ldrex'],
+        'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumb-2', 'sat', 'ldrex', 'clz'],
         'header': 'core_cm7.h',
         'defines': {
             '__CM7_REV': '0x0000U',
@@ -218,7 +218,7 @@
         'mcpu': 'cortex-m33',
         'mfpu': 'fpv5-d16',
         'mpu': True,
-        'features': ['thumbv6m', 'thumbv7m', 'thumbv7em', 'thumbv8m.base', 'thumbv8m.main', 'thumb-2', 'sat', 'ldrex'],
+        'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumbv8m.base', 'thumbv8m.main', 'thumb-2', 'sat', 'ldrex', 'clz'],
         'header': 'core_cm33.h',
         'defines': {
             '__CM33_REV': '0x0000U',
@@ -237,7 +237,7 @@
         'mcpu': 'cortex-m33',
         'mfpu': 'fpv5-d16',
         'mpu': True,
-        'features': ['thumbv6m', 'thumbv7m', 'thumbv7em', 'thumbv8m.base', 'thumbv8m.main', 'thumb-2', 'sat', 'ldrex'],
+        'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumbv8m.base', 'thumbv8m.main', 'thumb-2', 'sat', 'ldrex', 'clz'],
         'header': 'core_cm33.h',
         'defines': {
             '__CM33_REV': '0x0000U',
@@ -256,7 +256,7 @@
         'mcpu': 'cortex-m33',
         'mfpu': 'fpv5-d16',
         'mpu': True,
-        'features': ['thumbv6m', 'thumbv7m', 'thumbv7em', 'thumbv8m.base', 'thumbv8m.main', 'thumb-2', 'sat', 'ldrex'],
+        'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumbv8m.base', 'thumbv8m.main', 'thumb-2', 'sat', 'ldrex', 'clz'],
         'header': 'core_cm33.h',
         'defines': {
             '__CM33_REV': '0x0000U',
@@ -275,7 +275,7 @@
         'mcpu': 'cortex-m35p',
         'mfpu': 'fpv5-d16',
         'mpu': True,
-        'features': ['thumbv6m', 'thumbv7m', 'thumbv7em', 'thumbv8m.base', 'thumbv8m.main', 'thumb-2', 'sat', 'ldrex'],
+        'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumbv8m.base', 'thumbv8m.main', 'thumb-2', 'sat', 'ldrex', 'clz'],
         'header': 'core_cm35p.h',
         'defines': {
             '__CM35P_REV': '0x0000U',
@@ -294,7 +294,7 @@
         'mcpu': 'cortex-m35p',
         'mfpu': 'fpv5-d16',
         'mpu': True,
-        'features': ['thumbv6m', 'thumbv7m', 'thumbv7em', 'thumbv8m.base', 'thumbv8m.main', 'thumb-2', 'sat', 'ldrex'],
+        'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumbv8m.base', 'thumbv8m.main', 'thumb-2', 'sat', 'ldrex', 'clz'],
         'header': 'core_cm35p.h',
         'defines': {
             '__CM35P_REV': '0x0000U',
@@ -313,7 +313,7 @@
         'mcpu': 'cortex-m35p',
         'mfpu': 'fpv5-d16',
         'mpu': True,
-        'features': ['thumbv6m', 'thumbv7m', 'thumbv7em', 'thumbv8m.base', 'thumbv8m.main', 'thumb-2', 'sat', 'ldrex'],
+        'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumbv8m.base', 'thumbv8m.main', 'thumb-2', 'sat', 'ldrex', 'clz'],
         'header': 'core_cm35p.h',
         'defines': {
             '__CM35P_REV': '0x0000U',
@@ -332,7 +332,7 @@
         'mcpu': 'cortex-m55',
         'mfpu': 'fpv5-d16',
         'mpu': True,
-        'features': ['thumbv6m', 'thumbv7m', 'thumbv7em', 'thumbv8m.base', 'thumbv8m.main', 'thumbv8.1m.main', 'thumb-2', 'sat', 'ldrex'],
+        'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumbv8m.base', 'thumbv8m.main', 'thumbv8.1m.main', 'thumb-2', 'sat', 'ldrex', 'clz'],
         'header': 'core_cm55.h',
         'defines': {
             '__CM55_REV': '0x0000U',
@@ -358,7 +358,7 @@
         'mcpu': 'cortex-m55',
         'mfpu': 'fpv5-d16',
         'mpu': True,
-        'features': ['thumbv6m', 'thumbv7m', 'thumbv7em', 'thumbv8m.base', 'thumbv8m.main', 'thumbv8.1m.main', 'thumb-2', 'sat', 'ldrex'],
+        'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumbv8m.base', 'thumbv8m.main', 'thumbv8.1m.main', 'thumb-2', 'sat', 'ldrex', 'clz'],
         'header': 'core_cm55.h',
         'defines': {
             '__CM55_REV': '0x0000U',
@@ -384,7 +384,7 @@
         'mcpu': 'cortex-m55',
         'mfpu': 'fpv5-d16',
         'mpu': True,
-        'features': ['thumbv6m', 'thumbv7m', 'thumbv7em', 'thumbv8m.base', 'thumbv8m.main', 'thumbv8.1m.main', 'thumb-2', 'sat', 'ldrex'],
+        'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumbv8m.base', 'thumbv8m.main', 'thumbv8.1m.main', 'thumb-2', 'sat', 'ldrex', 'clz'],
         'header': 'core_cm55.h',
         'defines': {
             '__CM55_REV': '0x0000U',
@@ -410,7 +410,7 @@
         'mcpu': 'cortex-m85',
         'mfpu': 'fpv5-d16',
         'mpu': True,
-        'features': ['thumbv6m', 'thumbv7m', 'thumbv7em', 'thumbv8m.base', 'thumbv8m.main', 'thumbv8.1m.main', 'thumb-2', 'sat', 'ldrex'],
+        'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumbv8m.base', 'thumbv8m.main', 'thumbv8.1m.main', 'thumb-2', 'sat', 'ldrex', 'clz'],
         'header': 'core_cm85.h',
         'defines': {
             '__CM85_REV': '0x0000U',
@@ -436,7 +436,7 @@
         'mcpu': 'cortex-m85',
         'mfpu': 'fpv5-d16',
         'mpu': True,
-        'features': ['thumbv6m', 'thumbv7m', 'thumbv7em', 'thumbv8m.base', 'thumbv8m.main', 'thumbv8.1m.main', 'thumb-2', 'sat', 'ldrex'],
+        'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumbv8m.base', 'thumbv8m.main', 'thumbv8.1m.main', 'thumb-2', 'sat', 'ldrex', 'clz'],
         'header': 'core_cm85.h',
         'defines': {
             '__CM85_REV': '0x0000U',
@@ -462,7 +462,7 @@
         'mcpu': 'cortex-m85',
         'mfpu': 'fpv5-d16',
         'mpu': True,
-        'features': ['thumbv6m', 'thumbv7m', 'thumbv7em', 'thumbv8m.base', 'thumbv8m.main', 'thumbv8.1m.main', 'thumb-2', 'sat', 'ldrex'],
+        'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumbv8m.base', 'thumbv8m.main', 'thumbv8.1m.main', 'thumb-2', 'sat', 'ldrex', 'clz'],
         'header': 'core_cm85.h',
         'defines': {
             '__CM85_REV': '0x0000U',
@@ -488,7 +488,7 @@
         'mcpu': 'cortex-a5',
         'mfpu': 'none',
         'mpu': True,
-        'features': ['armv7a', 'thumb-2'],
+        'features': ['armv7a', 'thumb-2', 'sat', 'clz'],
         'header': 'core_ca.h',
         'defines': {
             '__CA_REV': '0x0000U',
@@ -505,7 +505,7 @@
         'mcpu': 'cortex-a5',
         'mfpu': 'neon-vfpv4',
         'mpu': True,
-        'features': ['armv7a', 'thumb-2'],
+        'features': ['armv7a', 'thumb-2', 'sat', 'dsp', 'clz'],
         'header': 'core_ca.h',
         'defines': {
             '__CA_REV': '0x0000U',
@@ -522,7 +522,7 @@
         'mcpu': 'cortex-a7',
         'mfpu': 'none',
         'mpu': True,
-        'features': ['armv7a', 'thumb-2'],
+        'features': ['armv7a', 'thumb-2', 'sat', 'clz'],
         'header': 'core_ca.h',
         'defines': {
             '__CA_REV': '0x0000U',
@@ -539,7 +539,7 @@
         'mcpu': 'cortex-a7',
         'mfpu': 'neon-vfpv4',
         'mpu': True,
-        'features': ['armv7a', 'thumb-2'],
+        'features': ['armv7a', 'thumb-2', 'sat', 'dsp', 'clz'],
         'header': 'core_ca.h',
         'defines': {
             '__CA_REV': '0x0000U',
@@ -556,7 +556,7 @@
         'mcpu': 'cortex-a9',
         'mfpu': 'none',
         'mpu': True,
-        'features': ['armv7a', 'thumb-2'],
+        'features': ['armv7a', 'thumb-2', 'sat', 'clz'],
         'header': 'core_ca.h',
         'defines': {
             '__CA_REV': '0x0000U',
@@ -573,7 +573,7 @@
         'mcpu': 'cortex-a9',
         'mfpu': 'neon-vfpv3',
         'mpu': True,
-        'features': ['armv7a', 'thumb-2'],
+        'features': ['armv7a', 'thumb-2', 'sat', 'dsp', 'ldrex', 'clz'],
         'header': 'core_ca.h',
         'defines': {
             '__CA_REV': '0x0000U',

diff --git a/CMSIS/Core/Test/sat.c b/CMSIS/Core/Test/sat.c
@@ -0,0 +1,26 @@
+// REQUIRES: sat
+// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s
+
+#include "cmsis_compiler.h"
+
+static volatile uint32_t s32 = 10;
+static volatile uint32_t u32 = 10U;
+
+void ssat() {
+    // CHECK-LABEL: <ssat>:
+    // CHECK: ssat {{r[0-9]+}}, #0x2, {{r[0-9]+}}
+    volatile uint32_t c = __SSAT(s32, 2u);
+    // CHECK: ssat {{r[0-9]+}}, #0x5, {{r[0-9]+}}
+    volatile uint32_t d = __SSAT(s32, 5u);
+    // CHECK: {{(bx lr)|(pop {.*pc})}}
+}
+
+void usat() {
+    // CHECK-LABEL: <usat>:
+    // CHECK: usat {{r[0-9]+}}, #0x2, {{r[0-9]+}}
+    volatile uint32_t c = __USAT(u32, 2u);
+    // CHECK: usat {{r[0-9]+}}, #0x5, {{r[0-9]+}}
+    volatile uint32_t d = __USAT(u32, 5u);
+    // CHECK: {{(bx lr)|(pop {.*pc})}}
+}
+
diff --git a/CMSIS/Core/Test/simd.c b/CMSIS/Core/Test/simd.c
@@ -1,4 +1,4 @@
-// REQUIRES: thumbv7em
+// REQUIRES: dsp
 // RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s
 
 #include "cmsis_compiler.h"
@@ -480,12 +480,14 @@ void sxtb16_ror() {
     // CHECK: sxtb16 {{r[0-9]+}}, {{r[0-9]+}}, ror #24
     result = __SXTB16_RORn(s32_1, 24);
 
-    // CHECK: ror.w [[REG:r[0-9]+]], {{r[0-9]+}}, {{#5|#0x5}}
+    // CHECK-THUMB: ror.w [[REG:r[0-9]+]], {{r[0-9]+}}, {{#5|#0x5}}
+    // CHECK-ARM: ror [[REG:r[0-9]+]], {{r[0-9]+}}, {{#5|#0x5}}
     // CHECK: sxtb16 {{r[0-9]+}}, [[REG]]
     // CHECK-NOT: , ror
     result = __SXTB16_RORn(s32_1, 5);
 
-    // CHECK: ror{{.w|ne|s}} {{r[0-9]+}}, {{r[0-9]+}}
+    // CHECK-THUMB: ror{{.w|ne|s}} {{r[0-9]+}}, {{r[0-9]+}}
+    // CHECK-ARM: ror {{r[0-9]+}}, {{r[0-9]+}}
     // CHECK: sxtb16 {{r[0-9]+}}, {{r[0-9]+}}
     // CHECK-NOT: , ror
     result = __SXTB16_RORn(s32_1, u8);
@@ -505,12 +507,14 @@ void sxtab16_ror() {
     // CHECK: sxtab16 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}}, ror #24
     result = __SXTAB16_RORn(s32_1, s32_2, 24);
 
-    // CHECK: ror.w [[REG:r[0-9]+]], {{r[0-9]+}}, {{#5|#0x5}}
+    // CHECK-THUMB: ror.w [[REG:r[0-9]+]], {{r[0-9]+}}, {{#5|#0x5}}
+    // CHECK-ARM: ror [[REG:r[0-9]+]], {{r[0-9]+}}, {{#5|#0x5}}
     // CHECK: sxtab16 {{r[0-9]+}}, {{r[0-9]+}}, [[REG]]
     // CHECK-NOT: , ror
     result = __SXTAB16_RORn(s32_1, s32_2, 5);
 
-    // CHECK: ror{{.w|ne|s}} {{r[0-9]+}}, {{r[0-9]+}}
+    // CHECK-THUMB: ror{{.w|ne|s}} {{r[0-9]+}}, {{r[0-9]+}}
+    // CHECK-ARM: ror {{r[0-9]+}}, {{r[0-9]+}}
     // CHECK: sxtab16 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}}
     // CHECK-NOT: , ror
     result = __SXTAB16_RORn(s32_1, s32_2, u8);

diff --git a/CMSIS/Core/Test/ssat.c b/CMSIS/Core/Test/ssat.c
diff --git a/CMSIS/Core/Test/usat.c b/CMSIS/Core/Test/usat.c