Add Core validation tests for Cortex-R4-5-7-8 and Cortex-A53

ARM.CMSIS.pdsc

@@ -625,6 +625,20 @@
       <accept Dcore="Cortex-A7"/>
       <accept Dcore="Cortex-A9"/>
     </condition>
+    <condition id="ARMv8-A Device">
+      <description>Armv7-A architecture based device</description>
+      <accept Dcore="Cortex-A35"/>
+      <accept Dcore="Cortex-A53"/>
+      <accept Dcore="Cortex-A55"/>
+      <accept Dcore="Cortex-A57"/>
+    </condition>
+    <condition id="ARMv7-R Device">
+      <description>Armv7-R architecture based device</description>
+      <accept Dcore="Cortex-R4"/>
+      <accept Dcore="Cortex-R5"/>
+      <accept Dcore="Cortex-R7"/>
+      <accept Dcore="Cortex-R8"/>
+    </condition>
 
     <condition id="TrustZone">
       <description>TrustZone</description>
@@ -681,9 +695,34 @@
       </files>
     </component>
 
+    <component Cclass="CMSIS" Cgroup="CORE" Cversion="1.0.0"  condition="ARMv8-A Device" >
+      <description>CMSIS-CORE for Cortex-A</description>
+      <files>
+        <!-- CPU independent -->
+        <file category="doc"     name="CMSIS/Documentation/html/Core_A/index.html"/>
+        <file category="include" name="CMSIS/Core/Include/"/>
+      </files>
+    </component>
+
+    <component Cclass="CMSIS" Cgroup="CORE" Cversion="1.0.0"  condition="ARMv7-R Device" >
+      <description>CMSIS-CORE for Cortex-R</description>
+      <files>
+        <!-- CPU independent -->
+        <file category="doc"     name="CMSIS/Documentation/html/Core_R/index.html"/>
+        <file category="include" name="CMSIS/Core/Include/"/>
+      </files>
+    </component>
+
     <!-- IRQ Controller -->
-    <component Cclass="Device" Cgroup="IRQ Controller" Csub="GIC" Capiversion="1.0.0" Cversion="1.2.0" condition="ARMv7-A Device">
+    <component Cclass="Device" Cgroup="IRQ Controller" Csub="GIC" Capiversion="1.0.0" Cversion="1.2.0">
       <description>IRQ Controller implementation using GIC</description>
+      <accept Dcore="Cortex-A5"/>
+      <accept Dcore="Cortex-A7"/>
+      <accept Dcore="Cortex-A9"/>
+      <accept Dcore="Cortex-R4"/>
+      <accept Dcore="Cortex-R5"/>
+      <accept Dcore="Cortex-R7"/>
+      <accept Dcore="Cortex-R8"/>
       <files>
         <file category="sourceC" name="CMSIS/Core/Source/irq_ctrl_gic.c"/>
       </files>

CMSIS/CoreValidation/Layer/App/Validation_Cortex-R/App.clayer.yml

@@ -0,0 +1,44 @@
+layer:
+  type: App
+  description: Validation of CMSIS-Core implementation
+
+  # packs:
+  #   - pack: ARM::CMSIS
+
+  define:
+    - PRINT_XML_REPORT: 1
+
+  add-path:
+    - ../../../Include
+    - ../../../Source/ConfigA
+
+  misc:
+    - for-compiler: AC6
+      C-CPP:
+      - -Wno-declaration-after-statement
+      - -Wno-covered-switch-default
+    - for-compiler: GCC
+      C-CPP:
+      - -Wno-declaration-after-statement
+
+  groups:
+    - group: Documentation
+      files:
+        - file: ../../../README.md
+
+    - group: Source Files
+      files:
+        - file: ./main.c
+
+    - group: CMSIS-Core_Validation
+      files:
+        - file: ../../../Source/cmsis_cv.c
+        - file: ../../../Source/CV_CoreAFunc.c
+        - file: ../../../Source/CV_CoreInstr.c
+        - file: ../../../Source/CV_CAL1Cache.c
+#        - file: ../../../Source/ConfigA/mmu.c
+
+    - group: Validation Framework
+      files:
+        - file: ../../../Source/CV_Framework.c
+        - file: ../../../Source/CV_Report.c

CMSIS/CoreValidation/Layer/App/Validation_Cortex-R/main.c

@@ -0,0 +1,133 @@
+/*
+ * Copyright (C) 2022 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "RTE_Components.h"
+#include  CMSIS_device_header
+
+#ifdef RTE_Compiler_EventRecorder
+#include "EventRecorder.h"
+#endif
+
+#include "cmsis_cv.h"
+#include "CV_Report.h"
+
+//lint -e970 allow using int for main
+
+int main (void)
+{
+
+  // System Initialization
+  SystemCoreClockUpdate();
+
+#ifdef RTE_Compiler_EventRecorder
+  // Initialize and start Event Recorder
+  (void)EventRecorderInitialize(EventRecordError, 1U);
+  (void)EventRecorderEnable(EventRecordAll, 0xFEU, 0xFEU);
+#endif
+
+  cmsis_cv();
+
+  #ifdef __MICROLIB
+  for(;;) {}
+  #else
+  exit(0);
+  #endif
+}
+
+#if defined(__CORTEX_R)
+#include "irq_ctrl.h"
+
+#if (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || \
+    (defined ( __GNUC__ ))
+  #define __IRQ __attribute__((interrupt("IRQ")))
+#elif defined ( __CC_ARM )
+  #define __IRQ __irq
+#elif defined ( __ICCARM__ )
+  #define __IRQ __irq __arm
+#else
+  #error "Unsupported compiler!"
+#endif
+
+
+__IRQ
+void IRQ_Handler(void);
+__IRQ
+void IRQ_Handler(void) {
+  const IRQn_ID_t irqn = IRQ_GetActiveIRQ();
+  IRQHandler_t const handler = IRQ_GetHandler(irqn);
+  if (handler != NULL) {
+    __enable_irq();
+    handler();
+    __disable_irq();
+  }
+  IRQ_EndOfInterrupt(irqn);
+}
+
+__IRQ __NO_RETURN
+void Undef_Handler (void);
+__IRQ __NO_RETURN
+void Undef_Handler (void) {
+  cmsis_cv_abort(__FILENAME__, __LINE__, "Undefined Instruction!");
+  exit(0);
+}
+
+__IRQ
+void SVC_Handler   (void);
+__IRQ
+void SVC_Handler   (void) {
+}
+
+__IRQ __NO_RETURN
+void PAbt_Handler  (void);
+__IRQ __NO_RETURN
+void PAbt_Handler  (void) {
+  cmsis_cv_abort(__FILENAME__, __LINE__, "Prefetch Abort!");
+  exit(0);
+}
+
+__IRQ __NO_RETURN
+void DAbt_Handler  (void);
+__IRQ __NO_RETURN
+void DAbt_Handler  (void) {
+  cmsis_cv_abort(__FILENAME__, __LINE__, "Data Abort!");
+  exit(0);
+}
+
+__IRQ
+void FIQ_Handler   (void);
+__IRQ
+void FIQ_Handler   (void) {
+}
+#endif
+
+#if defined(__CORTEX_M)
+__NO_RETURN
+void HardFault_Handler(void);
+__NO_RETURN
+void HardFault_Handler(void) {
+  cmsis_cv_abort(__FILENAME__, __LINE__, "HardFault!");
+  #ifdef __MICROLIB
+  for(;;) {}
+  #else
+  exit(0);
+  #endif
+}
+#endif