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- Add initial support for ARMv8A, ARMV7R and ARMV8R
- Added core_cxx.h files for ARMv8A, ARMV7R and ARMV8R based profiles - Moved gic peripheral to separate file - Moved __FPU_Enable function to the architecture specific file
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CMSIS/Core/Include/core_ca.h → CMSIS/Core/Include/a-profile/armv7a.h
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4 changes: 2 additions & 2 deletions
4
CMSIS/Core/Include/a-profile/cmsis_cp15.h → CMSIS/Core/Include/a-profile/armv7a_cp15.h
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| Original file line number | Diff line number | Diff line change |
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| /**************************************************************************//** | ||
| * @file armv8a_cp15.h | ||
| * @brief CMSIS compiler specific macros, functions, instructions | ||
| * @version V6.0.0 | ||
| * @date 4. August 2023 | ||
| ******************************************************************************/ | ||
| /* | ||
| * Copyright (c) 2009-2023 ARM Limited. All rights reserved. | ||
| * | ||
| * SPDX-License-Identifier: Apache-2.0 | ||
| * | ||
| * Licensed under the Apache License, Version 2.0 (the License); you may | ||
| * not use this file except in compliance with the License. | ||
| * You may obtain a copy of the License at | ||
| * | ||
| * www.apache.org/licenses/LICENSE-2.0 | ||
| * | ||
| * Unless required by applicable law or agreed to in writing, software | ||
| * distributed under the License is distributed on an AS IS BASIS, WITHOUT | ||
| * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
| * See the License for the specific language governing permissions and | ||
| * limitations under the License. | ||
| */ | ||
| #include <stdint.h> | ||
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| #if defined ( __ICCARM__ ) | ||
| #pragma system_include /* treat file as system include file for MISRA check */ | ||
| #elif defined (__clang__) | ||
| #pragma clang system_header /* treat file as system include file */ | ||
| #endif | ||
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| #ifndef __CMSIS_SYSTEM_CONTROL_H | ||
| #define __CMSIS_SYSTEM_CONTROL_H | ||
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| /** \brief Get MPIDR EL1 | ||
| \return Multiprocessor Affinity Register value | ||
| */ | ||
| __STATIC_FORCEINLINE uint64_t __get_MPIDR_EL1(void) | ||
| { | ||
| uint64_t result; | ||
| __ASM volatile("MRS %0, MPIDR_EL1" : "=r" (result) : : "memory"); | ||
| return result; | ||
| } | ||
|
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| /** \brief Get MAIR EL3 | ||
| \return MAIR value | ||
| */ | ||
| __STATIC_FORCEINLINE uint64_t __get_MAIR_EL3(void) | ||
| { | ||
| uint64_t result; | ||
| __ASM volatile("MRS %0, mair_el3" : "=r" (result) : : "memory"); | ||
| return result; | ||
| } | ||
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| /** \brief Set MAIR EL3 | ||
| \param [in] mair MAIR value to set | ||
| */ | ||
| __STATIC_FORCEINLINE void __set_MAIR_EL3(uint64_t mair) | ||
| { | ||
| __ASM volatile("MSR mair_el3, %0" : : "r" (mair) : "memory"); | ||
| } | ||
|
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| /** \brief Get TCR EL3 | ||
| \return TCR value | ||
| */ | ||
| __STATIC_FORCEINLINE uint64_t __get_TCR_EL3(void) | ||
| { | ||
| uint64_t result; | ||
| __ASM volatile("MRS %0, tcr_el3" : "=r" (result) : : "memory"); | ||
| return result; | ||
| } | ||
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| /** \brief Set TCR EL3 | ||
| \param [in] tcr TCR value to set | ||
| */ | ||
| __STATIC_FORCEINLINE void __set_TCR_EL3(uint64_t tcr) | ||
| { | ||
| __ASM volatile("MSR tcr_el3, %0" : : "r" (tcr) : "memory"); | ||
| } | ||
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| /** \brief Get TTBR0 EL3 | ||
| \return Translation Table Base Register 0 value | ||
| */ | ||
| __STATIC_FORCEINLINE uint64_t __get_TTBR0_EL3(void) | ||
| { | ||
| uint64_t result; | ||
| __ASM volatile("MRS %0, ttbr0_el3" : "=r" (result) : : "memory"); | ||
| return result; | ||
| } | ||
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| /** \brief Set TTBR0 EL3 | ||
| \param [in] ttbr0 Translation Table Base Register 0 value to set | ||
| */ | ||
| __STATIC_FORCEINLINE void __set_TTBR0_EL3(uint64_t ttbr0) | ||
| { | ||
| __ASM volatile("MSR ttbr0_el3, %0" : : "r" (ttbr0) : "memory"); | ||
| } | ||
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| /** \brief Get SCTLR EL3 | ||
| \return STRLR EL3 value | ||
| */ | ||
| __STATIC_FORCEINLINE uint64_t __get_SCTLR_EL3(void) | ||
| { | ||
| uint64_t result; | ||
| __ASM volatile("MRS %0, sctlr_el3" : "=r" (result) : : "memory"); | ||
| return result; | ||
| } | ||
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| /** \brief Set SCTLR EL3 | ||
| \param [in] vbar SCTLR value to set | ||
| */ | ||
| __STATIC_FORCEINLINE void __set_SCTLR_EL3(uint64_t sctlr) | ||
| { | ||
| __ASM volatile("MSR sctlr_el3, %0" : : "r" (sctlr) : "memory"); | ||
| } | ||
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| /** \brief Set VBAR EL3 | ||
| \param [in] vbar VBAR value to set | ||
| */ | ||
| __STATIC_FORCEINLINE void __set_VBAR_EL3(uint64_t vbar) | ||
| { | ||
| __ASM volatile("MSR vbar_el3, %0" : : "r" (vbar) : "memory"); | ||
| } | ||
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| /** \brief Set VBAR EL2 | ||
| \param [in] vbar VBAR value to set | ||
| */ | ||
| __STATIC_FORCEINLINE void __set_VBAR_EL2(uint64_t vbar) | ||
| { | ||
| __ASM volatile("MSR vbar_el2, %0" : : "r" (vbar) : "memory"); | ||
| } | ||
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| /** \brief Set VBAR EL1 | ||
| \param [in] vbar VBAR value to set | ||
| */ | ||
| __STATIC_FORCEINLINE void __set_VBAR_EL1(uint64_t vbar) | ||
| { | ||
| __ASM volatile("MSR vbar_el1, %0" : : "r" (vbar) : "memory"); | ||
| } | ||
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| #endif /* __CMSIS_SYSTEM_CONTROL_H */ |
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