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zbt_6111_sample.twx
executable file
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zbt_6111_sample.twx
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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE twReport [
<!ELEMENT twReport (twHead?, (twWarn | twDebug | twInfo)*, twBody, twSum?,
twDebug*, twFoot?, twClientInfo?)>
<!ATTLIST twReport version CDATA "10,4">
<!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
<!ELEMENT twExecVer (#PCDATA)>
<!ELEMENT twCopyright (#PCDATA)>
<!ELEMENT twCmdLine (#PCDATA)>
<!ELEMENT twDesign (#PCDATA)>
<!ELEMENT twPCF (#PCDATA)>
<!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
<!ELEMENT twDevName (#PCDATA)>
<!ATTLIST twDevInfo arch CDATA #IMPLIED pkg CDATA #IMPLIED>
<!ELEMENT twSpeedGrade (#PCDATA)>
<!ELEMENT twSpeedVer (#PCDATA)>
<!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
<!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
<!ATTLIST twRptInfo twAdvRpt (TRUE | FALSE) "FALSE">
<!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
<!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
<!ATTLIST twRptInfo twReportMinPaths CDATA #IMPLIED>
<!ELEMENT twItemLimit (#PCDATA)>
<!ELEMENT twUnconst EMPTY>
<!ELEMENT twUnconstLimit (#PCDATA)>
<!ELEMENT twEnvVar EMPTY>
<!ATTLIST twEnvVar name CDATA #REQUIRED>
<!ATTLIST twEnvVar description CDATA #REQUIRED>
<!ELEMENT twWarn (#PCDATA)>
<!ELEMENT twInfo (#PCDATA)>
<!ELEMENT twDebug (#PCDATA)>
<!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
<!ATTLIST twBody twFastPaths CDATA #IMPLIED>
<!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
<!ELEMENT twProc (#PCDATA)>
<!ELEMENT twTemp (#PCDATA)>
<!ELEMENT twVolt (#PCDATA)>
<!ELEMENT twSumRpt (twConstRollupTable*, twConstList?, twConstSummaryTable?, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?)>
<!ELEMENT twErrRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
<!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
<!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
<!ELEMENT twCycles (twSigConn+)>
<!ATTLIST twCycles twNum CDATA #REQUIRED>
<!ELEMENT twSigConn (twSig, twDriver, twLoad)>
<!ELEMENT twSig (#PCDATA)>
<!ELEMENT twDriver (#PCDATA)>
<!ELEMENT twLoad (#PCDATA)>
<!ELEMENT twConst (twConstHead, ((twPathRpt?,twRacePathRpt?, twPathRptBanner?)* | (twPathRpt*, twRacePathRpt?) | twNetRpt* | twClkSkewLimit*))>
<!ATTLIST twConst twConstType (NET |
NETDELAY |
NETSKEW |
PATH |
DEFPERIOD |
UNCONSTPATH |
DEFPATH |
PATH2SETUP |
UNCONSTPATH2SETUP |
PATHCLASS |
PATHDELAY |
PERIOD |
FREQUENCY |
PATHBLOCK |
OFFSET |
OFFSETIN |
OFFSETINCLOCK |
UNCONSTOFFSETINCLOCK |
OFFSETINDELAY |
OFFSETINMOD |
OFFSETOUT |
OFFSETOUTCLOCK |
UNCONSTOFFSETOUTCLOCK |
OFFSETOUTDELAY |
OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED>
<!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntEndPt?, twErrCntHold,
twEndPtCnt?,
twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
<!ELEMENT twConstName (#PCDATA)>
<!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
<!ATTLIST twConstHead uID CDATA #IMPLIED>
<!ELEMENT twItemCnt (#PCDATA)>
<!ELEMENT twErrCnt (#PCDATA)>
<!ELEMENT twErrCntEndPt (#PCDATA)>
<!ELEMENT twErrCntSetup (#PCDATA)>
<!ELEMENT twErrCntHold (#PCDATA)>
<!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
<!ELEMENT twEndPtCnt (#PCDATA)>
<!ELEMENT twPathErrCnt (#PCDATA)>
<!ELEMENT twMinPer (#PCDATA) >
<!ELEMENT twFootnote EMPTY>
<!ATTLIST twFootnote number CDATA #REQUIRED>
<!ELEMENT twMaxDel (#PCDATA)>
<!ELEMENT twMaxFreq (#PCDATA)>
<!ELEMENT twMinOff (#PCDATA)>
<!ELEMENT twMaxOff (#PCDATA)>
<!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
<!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
<!ELEMENT twTIGName (#PCDATA)>
<!ELEMENT twInstantiated (#PCDATA)>
<!ELEMENT twBlocked (#PCDATA)>
<!ELEMENT twRacePathRpt (twRacePath+)>
<!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
<!ELEMENT twUnconstPath (twTotDel, twSrc, twDest, (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
<!ATTLIST twUnconstPath twDataPathType CDATA #IMPLIED
twSimpleMinPath CDATA #IMPLIED>
<!ELEMENT twTotDel (#PCDATA)>
<!ELEMENT twSrc (#PCDATA)>
<!ATTLIST twSrc BELType CDATA #IMPLIED>
<!ELEMENT twDest (#PCDATA)>
<!ATTLIST twDest BELType CDATA #IMPLIED>
<!ELEMENT twDel (#PCDATA)>
<!ELEMENT twSUTime (#PCDATA)>
<!ELEMENT twTotPathDel (#PCDATA)>
<!ELEMENT twClkSkew (#PCDATA)>
<!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
<!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
<!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
<!ELEMENT twSlack (#PCDATA)>
<!ELEMENT twDelConst (#PCDATA)>
<!ELEMENT tw2Phase EMPTY>
<!ELEMENT twClkUncert (#PCDATA)>
<!ATTLIST twClkUncert fSysJit CDATA #IMPLIED fInputJit CDATA #IMPLIED
fDCMJit CDATA #IMPLIED
fPhaseErr CDATA #IMPLIED
sEqu CDATA #IMPLIED>
<!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
<!ELEMENT twPathRptBanner (#PCDATA)>
<!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
<!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
<!ELEMENT twOff (#PCDATA)>
<!ELEMENT twGuaranteed EMPTY>
<!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
<!ELEMENT twClkDel (#PCDATA)>
<!ELEMENT twClkSrc (#PCDATA)>
<!ELEMENT twClkDest (#PCDATA)>
<!ELEMENT twGuarInSetup (#PCDATA)>
<!ELEMENT twOffSrc (#PCDATA)>
<!ELEMENT twOffDest (#PCDATA)>
<!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
<!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
<!ELEMENT twDataDel (#PCDATA)>
<!ELEMENT twDataSrc (#PCDATA)>
<!ELEMENT twDataDest (#PCDATA)>
<!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
<!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twLogLvls (#PCDATA)>
<!ELEMENT twSrcSite (#PCDATA)>
<!ELEMENT twSrcClk (#PCDATA)>
<!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
<!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
<!ELEMENT twDelInfo (#PCDATA)>
<!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twSite (#PCDATA)>
<!ELEMENT twDelType (#PCDATA)>
<!ELEMENT twFanCnt (#PCDATA)>
<!ELEMENT twComp (#PCDATA)>
<!ELEMENT twNet (#PCDATA)>
<!ELEMENT twBEL (#PCDATA)>
<!ELEMENT twLogDel (#PCDATA)>
<!ELEMENT twRouteDel (#PCDATA)>
<!ELEMENT twDestClk (#PCDATA)>
<!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPctLog (#PCDATA)>
<!ELEMENT twPctRoute (#PCDATA)>
<!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
<!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
<!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
<!ELEMENT twTimeConst (#PCDATA)>
<!ELEMENT twAbsSlack (#PCDATA)>
<!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
<!ELEMENT twSkew (#PCDATA)>
<!ELEMENT twDetNet (twNetDel*)>
<!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
<!ELEMENT twNetDelInfo (#PCDATA)>
<!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twDetSkewNet (twNetSkew*)>
<!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
<!ELEMENT twClkSkewLimit EMPTY>
<!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED arrv1 CDATA #IMPLIED
arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
<!ELEMENT twConstRollupTable (twConstRollup*)>
<!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
<!ELEMENT twConstRollup EMPTY>
<!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
<!ATTLIST twConstRollup actualRollup CDATA #IMPLIED errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED itemsRollup CDATA #IMPLIED>
<!ELEMENT twConstList (twConstListItem)*>
<!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)>
<!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
<!ELEMENT twNotMet EMPTY>
<!ELEMENT twReqVal (#PCDATA)>
<!ELEMENT twActVal (#PCDATA)>
<!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
<!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
<!ELEMENT twConstStats (twConstName)>
<!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
<!ATTLIST twConstStats twRequired CDATA #IMPLIED>
<!ATTLIST twConstStats twActual CDATA #IMPLIED>
<!ATTLIST twConstStats twSlack CDATA #IMPLIED>
<!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
<!ATTLIST twConstStats twErrors CDATA #IMPLIED>
<!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twTCType CDATA #IMPLIED>
<!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
<!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED slackIndex CDATA #IMPLIED>
<!ELEMENT twConstData EMPTY>
<!ATTLIST twConstData type CDATA #IMPLIED units (MHz | ns) "ns" slack CDATA #IMPLIED
best CDATA #IMPLIED requested CDATA #IMPLIED
errors CDATA #IMPLIED
score CDATA #IMPLIED>
<!ELEMENT twTimeGrpRpt (twTimeGrp)*>
<!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
<!ELEMENT twTimeGrpName (#PCDATA)>
<!ELEMENT twCompList (twCompName+)>
<!ELEMENT twCompName (#PCDATA)>
<!ELEMENT twSigList (twSigName+)>
<!ELEMENT twSigName (#PCDATA)>
<!ELEMENT twBELList (twBELName+)>
<!ELEMENT twBELName (#PCDATA)>
<!ELEMENT twBlockList (twBlockName+)>
<!ELEMENT twBlockName (#PCDATA)>
<!ELEMENT twMacList (twMacName+)>
<!ELEMENT twMacName (#PCDATA)>
<!ELEMENT twPinList (twPinName+)>
<!ELEMENT twPinName (#PCDATA)>
<!ELEMENT twUnmetConstCnt (#PCDATA)>
<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)>
<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
<!ELEMENT twSU2ClkTime (#PCDATA)>
<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twH2ClkTime (#PCDATA)>
<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
<!ELEMENT twClk2Pad (twDest, twTime)>
<!ELEMENT twTime (#PCDATA)>
<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
<!ELEMENT twClk2Out EMPTY>
<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
<!ELEMENT twRiseRise (#PCDATA)>
<!ELEMENT twFallRise (#PCDATA)>
<!ELEMENT twRiseFall (#PCDATA)>
<!ELEMENT twFallFall (#PCDATA)>
<!ELEMENT twPad2PadList (twPad2Pad+)>
<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
<!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>
<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED twHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffOutTblRow EMPTY>
<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
<!ELEMENT twNonDedClk (#PCDATA)>
<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
<!ELEMENT twScore (#PCDATA)>
<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
<!ELEMENT twPathCnt (#PCDATA)>
<!ELEMENT twNetCnt (#PCDATA)>
<!ELEMENT twConnCnt (#PCDATA)>
<!ELEMENT twPct (#PCDATA)>
<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
<!ELEMENT twMaxCombDel (#PCDATA)>
<!ELEMENT twMaxFromToDel (#PCDATA)>
<!ELEMENT twMaxNetDel (#PCDATA)>
<!ELEMENT twMaxNetSkew (#PCDATA)>
<!ELEMENT twMaxInAfterClk (#PCDATA)>
<!ELEMENT twMinInBeforeClk (#PCDATA)>
<!ELEMENT twMaxOutBeforeClk (#PCDATA)>
<!ELEMENT twMinOutAfterClk (#PCDATA)>
<!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
<!ELEMENT twTimestamp (#PCDATA)>
<!ELEMENT twFootnoteExplanation EMPTY>
<!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
<!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
<!ELEMENT twClientInfo (twClientName, twAttrList?)>
<!ELEMENT twClientName (#PCDATA)>
<!ELEMENT twAttrList (twAttrListItem)*>
<!ELEMENT twAttrListItem (twName, twValue*)>
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twHead><twExecVer>Release 10.1.03 Trace (lin64)</twExecVer><twCopyright>Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.</twCopyright><twCmdLine>/afs/csail.mit.edu/proj/redsocs/Xilinx10.1/ISE/bin/lin64/unwrapped/trce -ise
/afs/athena.mit.edu/user/z/a/zareenc/pc-na-13-dec-1.0/pc-na.ise -intstyle ise
-v 3 -s 4 -xml zbt_6111_sample zbt_6111_sample.ncd -o zbt_6111_sample.twr
zbt_6111_sample.pcf -ucf labkit.ucf
</twCmdLine><twDesign>zbt_6111_sample.ncd</twDesign><twPCF>zbt_6111_sample.pcf</twPCF><twDevInfo arch="virtex2" pkg="bf957"><twDevName>xc2v6000</twDevName><twSpeedGrade>-4</twSpeedGrade><twSpeedVer>PRODUCTION 1.121 2008-07-25, STEPPING level 0</twSpeedVer></twDevInfo><twRptInfo twRptLvl="twVerbose"></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo>INFO:Timing:2698 - No timing constraints found, doing default enumeration.</twInfo><twInfo>INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo>INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twBody><twVerboseRpt><twDataSheet twNameLen="19"><twSUH2ClkList twDestWidth = "13" twPhaseWidth = "20"><twDest>clock_27mhz</twDest><twSUH2Clk ><twSrc>button1</twSrc><twSUHTime twInternalClk ="tv_in_clock_OBUF" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">2.956</twSU2ClkTime><twH2ClkTime twEdge="twRising">-1.215</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>button_enter</twSrc><twSUHTime twInternalClk ="analyzer3_clock_OBUF" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">3.979</twSU2ClkTime><twH2ClkTime twEdge="twRising">-0.943</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ram0_data<0></twSrc><twSUHTime twInternalClk ="analyzer3_clock_OBUF" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">-2.564</twSU2ClkTime><twH2ClkTime twEdge="twRising">2.836</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ram0_data<1></twSrc><twSUHTime twInternalClk ="analyzer3_clock_OBUF" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">-2.891</twSU2ClkTime><twH2ClkTime twEdge="twRising">3.163</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ram0_data<2></twSrc><twSUHTime twInternalClk ="analyzer3_clock_OBUF" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">-3.393</twSU2ClkTime><twH2ClkTime twEdge="twRising">3.665</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ram0_data<3></twSrc><twSUHTime twInternalClk ="analyzer3_clock_OBUF" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">-3.091</twSU2ClkTime><twH2ClkTime twEdge="twRising">3.363</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ram0_data<4></twSrc><twSUHTime twInternalClk ="analyzer3_clock_OBUF" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">-2.313</twSU2ClkTime><twH2ClkTime twEdge="twRising">2.585</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ram0_data<5></twSrc><twSUHTime twInternalClk ="analyzer3_clock_OBUF" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">-2.722</twSU2ClkTime><twH2ClkTime twEdge="twRising">2.994</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ram0_data<6></twSrc><twSUHTime twInternalClk ="analyzer3_clock_OBUF" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">-2.725</twSU2ClkTime><twH2ClkTime twEdge="twRising">2.997</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ram0_data<7></twSrc><twSUHTime twInternalClk ="analyzer3_clock_OBUF" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">-2.394</twSU2ClkTime><twH2ClkTime twEdge="twRising">2.666</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ram0_data<8></twSrc><twSUHTime twInternalClk ="analyzer3_clock_OBUF" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">-2.605</twSU2ClkTime><twH2ClkTime twEdge="twRising">2.877</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ram0_data<9></twSrc><twSUHTime twInternalClk ="analyzer3_clock_OBUF" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">-1.816</twSU2ClkTime><twH2ClkTime twEdge="twRising">2.088</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ram0_data<10></twSrc><twSUHTime twInternalClk ="analyzer3_clock_OBUF" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">-2.603</twSU2ClkTime><twH2ClkTime twEdge="twRising">2.875</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ram0_data<11></twSrc><twSUHTime twInternalClk ="analyzer3_clock_OBUF" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">-2.514</twSU2ClkTime><twH2ClkTime twEdge="twRising">2.786</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ram0_data<12></twSrc><twSUHTime twInternalClk ="analyzer3_clock_OBUF" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">-2.536</twSU2ClkTime><twH2ClkTime twEdge="twRising">2.808</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ram0_data<13></twSrc><twSUHTime twInternalClk ="analyzer3_clock_OBUF" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">-1.720</twSU2ClkTime><twH2ClkTime twEdge="twRising">1.992</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ram0_data<14></twSrc><twSUHTime twInternalClk ="analyzer3_clock_OBUF" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">-2.668</twSU2ClkTime><twH2ClkTime twEdge="twRising">2.940</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ram0_data<15></twSrc><twSUHTime twInternalClk ="analyzer3_clock_OBUF" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">-2.655</twSU2ClkTime><twH2ClkTime twEdge="twRising">2.927</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ram0_data<16></twSrc><twSUHTime twInternalClk ="analyzer3_clock_OBUF" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">-3.039</twSU2ClkTime><twH2ClkTime twEdge="twRising">3.311</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ram0_data<17></twSrc><twSUHTime twInternalClk ="analyzer3_clock_OBUF" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">-2.724</twSU2ClkTime><twH2ClkTime twEdge="twRising">2.996</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ram0_data<18></twSrc><twSUHTime twInternalClk ="analyzer3_clock_OBUF" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">-2.703</twSU2ClkTime><twH2ClkTime twEdge="twRising">2.975</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ram0_data<19></twSrc><twSUHTime twInternalClk ="analyzer3_clock_OBUF" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">-3.290</twSU2ClkTime><twH2ClkTime twEdge="twRising">3.562</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ram0_data<20></twSrc><twSUHTime twInternalClk ="analyzer3_clock_OBUF" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">-2.717</twSU2ClkTime><twH2ClkTime twEdge="twRising">2.989</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ram0_data<21></twSrc><twSUHTime twInternalClk ="analyzer3_clock_OBUF" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">-1.965</twSU2ClkTime><twH2ClkTime twEdge="twRising">2.237</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ram0_data<22></twSrc><twSUHTime twInternalClk ="analyzer3_clock_OBUF" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">-2.264</twSU2ClkTime><twH2ClkTime twEdge="twRising">2.536</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ram0_data<23></twSrc><twSUHTime twInternalClk ="analyzer3_clock_OBUF" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">-3.021</twSU2ClkTime><twH2ClkTime twEdge="twRising">3.293</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ram0_data<24></twSrc><twSUHTime twInternalClk ="analyzer3_clock_OBUF" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">-2.106</twSU2ClkTime><twH2ClkTime twEdge="twRising">2.378</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ram0_data<25></twSrc><twSUHTime twInternalClk ="analyzer3_clock_OBUF" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">-2.522</twSU2ClkTime><twH2ClkTime twEdge="twRising">2.794</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ram0_data<26></twSrc><twSUHTime twInternalClk ="analyzer3_clock_OBUF" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">-2.713</twSU2ClkTime><twH2ClkTime twEdge="twRising">2.985</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ram0_data<27></twSrc><twSUHTime twInternalClk ="analyzer3_clock_OBUF" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">-2.044</twSU2ClkTime><twH2ClkTime twEdge="twRising">2.316</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ram0_data<28></twSrc><twSUHTime twInternalClk ="analyzer3_clock_OBUF" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">-3.011</twSU2ClkTime><twH2ClkTime twEdge="twRising">3.283</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ram0_data<29></twSrc><twSUHTime twInternalClk ="analyzer3_clock_OBUF" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">-2.191</twSU2ClkTime><twH2ClkTime twEdge="twRising">2.463</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ram0_data<30></twSrc><twSUHTime twInternalClk ="analyzer3_clock_OBUF" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">-3.007</twSU2ClkTime><twH2ClkTime twEdge="twRising">3.279</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ram0_data<31></twSrc><twSUHTime twInternalClk ="analyzer3_clock_OBUF" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">-1.930</twSU2ClkTime><twH2ClkTime twEdge="twRising">2.202</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>switch<0></twSrc><twSUHTime twInternalClk ="analyzer3_clock_OBUF" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">0.820</twSU2ClkTime><twH2ClkTime twEdge="twRising">1.227</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>switch<1></twSrc><twSUHTime twInternalClk ="analyzer3_clock_OBUF" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">0.482</twSU2ClkTime><twH2ClkTime twEdge="twRising">1.257</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>switch<4></twSrc><twSUHTime twInternalClk ="analyzer3_clock_OBUF" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">0.433</twSU2ClkTime><twH2ClkTime twEdge="twRising">-0.188</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>switch<5></twSrc><twSUHTime twInternalClk ="analyzer3_clock_OBUF" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">0.252</twSU2ClkTime><twH2ClkTime twEdge="twRising">0.874</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>switch<6></twSrc><twSUHTime twInternalClk ="analyzer3_clock_OBUF" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">0.776</twSU2ClkTime><twH2ClkTime twEdge="twRising">2.302</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>switch<7></twSrc><twSUHTime twInternalClk ="analyzer3_clock_OBUF" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">1.663</twSU2ClkTime><twH2ClkTime twEdge="twRising">2.335</twH2ClkTime></twSUHTime></twSUH2Clk></twSUH2ClkList><twSUH2ClkList twDestWidth = "15" twPhaseWidth = "23"><twDest>tv_in_line_clock1</twDest><twSUH2Clk ><twSrc>tv_in_ycrcb<10></twSrc><twSUHTime twInternalClk ="tv_in_line_clock1_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">4.766</twSU2ClkTime><twH2ClkTime twEdge="twRising">-0.008</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>tv_in_ycrcb<11></twSrc><twSUHTime twInternalClk ="tv_in_line_clock1_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">4.950</twSU2ClkTime><twH2ClkTime twEdge="twRising">-0.168</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>tv_in_ycrcb<12></twSrc><twSUHTime twInternalClk ="tv_in_line_clock1_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">4.100</twSU2ClkTime><twH2ClkTime twEdge="twRising">0.680</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>tv_in_ycrcb<13></twSrc><twSUHTime twInternalClk ="tv_in_line_clock1_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">4.218</twSU2ClkTime><twH2ClkTime twEdge="twRising">-0.647</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>tv_in_ycrcb<14></twSrc><twSUHTime twInternalClk ="tv_in_line_clock1_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">2.980</twSU2ClkTime><twH2ClkTime twEdge="twRising">-0.138</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>tv_in_ycrcb<15></twSrc><twSUHTime twInternalClk ="tv_in_line_clock1_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">3.769</twSU2ClkTime><twH2ClkTime twEdge="twRising">-0.075</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>tv_in_ycrcb<16></twSrc><twSUHTime twInternalClk ="tv_in_line_clock1_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">3.917</twSU2ClkTime><twH2ClkTime twEdge="twRising">-0.587</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>tv_in_ycrcb<17></twSrc><twSUHTime twInternalClk ="tv_in_line_clock1_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">4.093</twSU2ClkTime><twH2ClkTime twEdge="twRising">-0.573</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>tv_in_ycrcb<18></twSrc><twSUHTime twInternalClk ="tv_in_line_clock1_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">4.623</twSU2ClkTime><twH2ClkTime twEdge="twRising">-1.038</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>tv_in_ycrcb<19></twSrc><twSUHTime twInternalClk ="tv_in_line_clock1_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising">4.997</twSU2ClkTime><twH2ClkTime twEdge="twRising">-0.843</twH2ClkTime></twSUHTime></twSUH2Clk></twSUH2ClkList><twClk2OutList twDestWidth = "18" twPhaseWidth = "20"><twSrc>clock_27mhz</twSrc><twClk2Out twOutPad = "Q" twMinTime = "14.030" twMinEdge ="twRising" twMaxTime = "14.030" twMaxEdge ="twRising" twInternalClk="rc/ram_clock" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "Q" twMinTime = "14.030" twMinEdge ="twFalling" twMaxTime = "14.030" twMaxEdge ="twFalling" twInternalClk="rc/ram_clock" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "clock_feedback_out" twMinTime = "12.602" twMinEdge ="twRising" twMaxTime = "12.602" twMaxEdge ="twRising" twInternalClk="rc/ram_clock" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "clock_feedback_out" twMinTime = "12.602" twMinEdge ="twFalling" twMaxTime = "12.602" twMaxEdge ="twFalling" twInternalClk="rc/ram_clock" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "disp_ce_b" twMinTime = "11.457" twMinEdge ="twRising" twMaxTime = "11.457" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "disp_clock" twMinTime = "11.766" twMinEdge ="twRising" twMaxTime = "12.402" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "disp_data_out" twMinTime = "12.353" twMinEdge ="twRising" twMaxTime = "12.353" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "disp_reset_b" twMinTime = "11.454" twMinEdge ="twRising" twMaxTime = "11.454" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "disp_rs" twMinTime = "10.876" twMinEdge ="twRising" twMaxTime = "10.876" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "led<2>" twMinTime = "14.447" twMinEdge ="twRising" twMaxTime = "14.447" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_address<0>" twMinTime = "11.728" twMinEdge ="twRising" twMaxTime = "26.844" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_address<1>" twMinTime = "11.793" twMinEdge ="twRising" twMaxTime = "25.887" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_address<2>" twMinTime = "11.802" twMinEdge ="twRising" twMaxTime = "25.753" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_address<3>" twMinTime = "12.702" twMinEdge ="twRising" twMaxTime = "26.866" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_address<4>" twMinTime = "11.971" twMinEdge ="twRising" twMaxTime = "26.218" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_address<5>" twMinTime = "12.136" twMinEdge ="twRising" twMaxTime = "26.427" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_address<6>" twMinTime = "11.896" twMinEdge ="twRising" twMaxTime = "25.985" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_address<7>" twMinTime = "12.005" twMinEdge ="twRising" twMaxTime = "26.468" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_address<8>" twMinTime = "13.002" twMinEdge ="twRising" twMaxTime = "22.643" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_address<9>" twMinTime = "12.637" twMinEdge ="twRising" twMaxTime = "23.248" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_address<10>" twMinTime = "12.193" twMinEdge ="twRising" twMaxTime = "23.082" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_address<11>" twMinTime = "11.432" twMinEdge ="twRising" twMaxTime = "22.614" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_address<12>" twMinTime = "11.851" twMinEdge ="twRising" twMaxTime = "22.270" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_address<13>" twMinTime = "12.629" twMinEdge ="twRising" twMaxTime = "23.003" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_address<14>" twMinTime = "12.620" twMinEdge ="twRising" twMaxTime = "23.651" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_address<15>" twMinTime = "12.389" twMinEdge ="twRising" twMaxTime = "22.841" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_address<16>" twMinTime = "12.707" twMinEdge ="twRising" twMaxTime = "24.121" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_address<17>" twMinTime = "12.786" twMinEdge ="twRising" twMaxTime = "23.469" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_address<18>" twMinTime = "13.533" twMinEdge ="twRising" twMaxTime = "25.135" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_clk" twMinTime = "12.499" twMinEdge ="twRising" twMaxTime = "12.499" twMaxEdge ="twRising" twInternalClk="rc/ram_clock" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_clk" twMinTime = "12.499" twMinEdge ="twFalling" twMaxTime = "12.499" twMaxEdge ="twFalling" twInternalClk="rc/ram_clock" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_data<0>" twMinTime = "10.457" twMinEdge ="twRising" twMaxTime = "11.399" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_data<1>" twMinTime = "9.764" twMinEdge ="twRising" twMaxTime = "10.745" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_data<2>" twMinTime = "9.786" twMinEdge ="twRising" twMaxTime = "11.034" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_data<3>" twMinTime = "10.412" twMinEdge ="twRising" twMaxTime = "10.751" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_data<4>" twMinTime = "10.154" twMinEdge ="twRising" twMaxTime = "11.036" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_data<5>" twMinTime = "9.778" twMinEdge ="twRising" twMaxTime = "10.239" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_data<6>" twMinTime = "9.130" twMinEdge ="twRising" twMaxTime = "9.745" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_data<7>" twMinTime = "10.206" twMinEdge ="twRising" twMaxTime = "10.245" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_data<8>" twMinTime = "9.747" twMinEdge ="twRising" twMaxTime = "9.836" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_data<9>" twMinTime = "11.270" twMinEdge ="twRising" twMaxTime = "12.246" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_data<10>" twMinTime = "10.008" twMinEdge ="twRising" twMaxTime = "11.671" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_data<11>" twMinTime = "10.313" twMinEdge ="twRising" twMaxTime = "12.258" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_data<12>" twMinTime = "9.848" twMinEdge ="twRising" twMaxTime = "11.077" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_data<13>" twMinTime = "10.608" twMinEdge ="twRising" twMaxTime = "11.673" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_data<14>" twMinTime = "10.558" twMinEdge ="twRising" twMaxTime = "11.080" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_data<15>" twMinTime = "10.883" twMinEdge ="twRising" twMaxTime = "11.378" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_data<16>" twMinTime = "9.403" twMinEdge ="twRising" twMaxTime = "9.425" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_data<17>" twMinTime = "9.899" twMinEdge ="twRising" twMaxTime = "10.030" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_data<18>" twMinTime = "9.513" twMinEdge ="twRising" twMaxTime = "9.753" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_data<19>" twMinTime = "9.140" twMinEdge ="twRising" twMaxTime = "9.791" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_data<20>" twMinTime = "9.757" twMinEdge ="twRising" twMaxTime = "10.582" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_data<21>" twMinTime = "10.114" twMinEdge ="twRising" twMaxTime = "10.785" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_data<22>" twMinTime = "10.881" twMinEdge ="twRising" twMaxTime = "11.681" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_data<23>" twMinTime = "10.105" twMinEdge ="twRising" twMaxTime = "10.793" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_data<24>" twMinTime = "9.850" twMinEdge ="twRising" twMaxTime = "11.685" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_data<25>" twMinTime = "9.891" twMinEdge ="twRising" twMaxTime = "12.270" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_data<26>" twMinTime = "9.991" twMinEdge ="twRising" twMaxTime = "10.768" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_data<27>" twMinTime = "10.225" twMinEdge ="twRising" twMaxTime = "11.035" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_data<28>" twMinTime = "9.809" twMinEdge ="twRising" twMaxTime = "11.062" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_data<29>" twMinTime = "10.836" twMinEdge ="twRising" twMaxTime = "11.934" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_data<30>" twMinTime = "10.092" twMinEdge ="twRising" twMaxTime = "11.075" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_data<31>" twMinTime = "11.196" twMinEdge ="twRising" twMaxTime = "11.926" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_data<32>" twMinTime = "11.660" twMinEdge ="twRising" twMaxTime = "11.660" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_data<33>" twMinTime = "11.647" twMinEdge ="twRising" twMaxTime = "11.647" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_data<34>" twMinTime = "12.266" twMinEdge ="twRising" twMaxTime = "12.266" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_data<35>" twMinTime = "10.430" twMinEdge ="twRising" twMaxTime = "10.430" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "ram0_we_b" twMinTime = "13.951" twMinEdge ="twRising" twMaxTime = "18.367" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "vga_out_blank_b" twMinTime = "11.865" twMinEdge ="twRising" twMaxTime = "11.865" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "vga_out_blue<0>" twMinTime = "16.814" twMinEdge ="twRising" twMaxTime = "91.259" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "vga_out_blue<1>" twMinTime = "17.126" twMinEdge ="twRising" twMaxTime = "91.356" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "vga_out_blue<2>" twMinTime = "17.067" twMinEdge ="twRising" twMaxTime = "91.285" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "vga_out_blue<3>" twMinTime = "17.234" twMinEdge ="twRising" twMaxTime = "91.048" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "vga_out_blue<4>" twMinTime = "14.849" twMinEdge ="twRising" twMaxTime = "92.104" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "vga_out_blue<5>" twMinTime = "15.315" twMinEdge ="twRising" twMaxTime = "92.997" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "vga_out_blue<6>" twMinTime = "15.401" twMinEdge ="twRising" twMaxTime = "92.348" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "vga_out_blue<7>" twMinTime = "15.532" twMinEdge ="twRising" twMaxTime = "92.497" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "vga_out_green<0>" twMinTime = "15.797" twMinEdge ="twRising" twMaxTime = "94.371" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "vga_out_green<1>" twMinTime = "16.516" twMinEdge ="twRising" twMaxTime = "95.940" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "vga_out_green<2>" twMinTime = "17.531" twMinEdge ="twRising" twMaxTime = "98.801" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "vga_out_green<3>" twMinTime = "17.789" twMinEdge ="twRising" twMaxTime = "94.898" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "vga_out_green<4>" twMinTime = "17.078" twMinEdge ="twRising" twMaxTime = "98.150" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "vga_out_green<5>" twMinTime = "16.923" twMinEdge ="twRising" twMaxTime = "100.793" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "vga_out_green<6>" twMinTime = "17.478" twMinEdge ="twRising" twMaxTime = "101.111" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "vga_out_green<7>" twMinTime = "17.487" twMinEdge ="twRising" twMaxTime = "96.872" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "vga_out_hsync" twMinTime = "12.286" twMinEdge ="twRising" twMaxTime = "12.286" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "vga_out_red<0>" twMinTime = "16.557" twMinEdge ="twRising" twMaxTime = "97.073" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "vga_out_red<1>" twMinTime = "15.533" twMinEdge ="twRising" twMaxTime = "96.243" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "vga_out_red<2>" twMinTime = "18.674" twMinEdge ="twRising" twMaxTime = "96.493" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "vga_out_red<3>" twMinTime = "18.541" twMinEdge ="twRising" twMaxTime = "96.990" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "vga_out_red<4>" twMinTime = "19.421" twMinEdge ="twRising" twMaxTime = "100.365" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "vga_out_red<5>" twMinTime = "16.494" twMinEdge ="twRising" twMaxTime = "97.643" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "vga_out_red<6>" twMinTime = "18.038" twMinEdge ="twRising" twMaxTime = "98.100" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "vga_out_red<7>" twMinTime = "17.334" twMinEdge ="twRising" twMaxTime = "97.038" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "vga_out_vsync" twMinTime = "11.967" twMinEdge ="twRising" twMaxTime = "11.967" twMaxEdge ="twRising" twInternalClk="analyzer3_clock_OBUF" twClkPhase="0.000" ></twClk2Out></twClk2OutList><twClk2SUList twDestWidth = "17"><twDest>clock_27mhz</twDest><twClk2SU><twSrc>clock_27mhz</twSrc><twRiseRise>41.309</twRiseRise></twClk2SU><twClk2SU><twSrc>tv_in_line_clock1</twSrc><twRiseRise>3.463</twRiseRise></twClk2SU></twClk2SUList><twClk2SUList twDestWidth = "17"><twDest>tv_in_line_clock1</twDest><twClk2SU><twSrc>clock_27mhz</twSrc><twRiseRise>11.443</twRiseRise></twClk2SU><twClk2SU><twSrc>tv_in_line_clock1</twSrc><twRiseRise>7.597</twRiseRise></twClk2SU></twClk2SUList><twPad2PadList twSrcWidth = "11" twDestWidth = "19"><twPad2Pad><twSrc>clock_27mhz</twSrc><twDest>analyzer3_clock</twDest><twDel>12.071</twDel></twPad2Pad><twPad2Pad><twSrc>clock_27mhz</twSrc><twDest>tv_in_clock</twDest><twDel>11.990</twDel></twPad2Pad><twPad2Pad><twSrc>clock_27mhz</twSrc><twDest>vga_out_pixel_clock</twDest><twDel>11.511</twDel></twPad2Pad><twPad2Pad><twSrc>switch<2></twSrc><twDest>vga_out_blue<0></twDest><twDel>48.788</twDel></twPad2Pad><twPad2Pad><twSrc>switch<2></twSrc><twDest>vga_out_blue<1></twDest><twDel>48.878</twDel></twPad2Pad><twPad2Pad><twSrc>switch<2></twSrc><twDest>vga_out_blue<2></twDest><twDel>48.559</twDel></twPad2Pad><twPad2Pad><twSrc>switch<2></twSrc><twDest>vga_out_blue<3></twDest><twDel>48.026</twDel></twPad2Pad><twPad2Pad><twSrc>switch<2></twSrc><twDest>vga_out_blue<4></twDest><twDel>48.397</twDel></twPad2Pad><twPad2Pad><twSrc>switch<2></twSrc><twDest>vga_out_blue<5></twDest><twDel>48.990</twDel></twPad2Pad><twPad2Pad><twSrc>switch<2></twSrc><twDest>vga_out_blue<6></twDest><twDel>47.775</twDel></twPad2Pad><twPad2Pad><twSrc>switch<2></twSrc><twDest>vga_out_blue<7></twDest><twDel>47.916</twDel></twPad2Pad><twPad2Pad><twSrc>switch<2></twSrc><twDest>vga_out_green<0></twDest><twDel>49.135</twDel></twPad2Pad><twPad2Pad><twSrc>switch<2></twSrc><twDest>vga_out_green<1></twDest><twDel>50.704</twDel></twPad2Pad><twPad2Pad><twSrc>switch<2></twSrc><twDest>vga_out_green<2></twDest><twDel>52.106</twDel></twPad2Pad><twPad2Pad><twSrc>switch<2></twSrc><twDest>vga_out_green<3></twDest><twDel>48.909</twDel></twPad2Pad><twPad2Pad><twSrc>switch<2></twSrc><twDest>vga_out_green<4></twDest><twDel>51.506</twDel></twPad2Pad><twPad2Pad><twSrc>switch<2></twSrc><twDest>vga_out_green<5></twDest><twDel>54.098</twDel></twPad2Pad><twPad2Pad><twSrc>switch<2></twSrc><twDest>vga_out_green<6></twDest><twDel>54.416</twDel></twPad2Pad><twPad2Pad><twSrc>switch<2></twSrc><twDest>vga_out_green<7></twDest><twDel>50.228</twDel></twPad2Pad><twPad2Pad><twSrc>switch<2></twSrc><twDest>vga_out_red<0></twDest><twDel>50.429</twDel></twPad2Pad><twPad2Pad><twSrc>switch<2></twSrc><twDest>vga_out_red<1></twDest><twDel>49.599</twDel></twPad2Pad><twPad2Pad><twSrc>switch<2></twSrc><twDest>vga_out_red<2></twDest><twDel>49.849</twDel></twPad2Pad><twPad2Pad><twSrc>switch<2></twSrc><twDest>vga_out_red<3></twDest><twDel>50.346</twDel></twPad2Pad><twPad2Pad><twSrc>switch<2></twSrc><twDest>vga_out_red<4></twDest><twDel>53.670</twDel></twPad2Pad><twPad2Pad><twSrc>switch<2></twSrc><twDest>vga_out_red<5></twDest><twDel>50.948</twDel></twPad2Pad><twPad2Pad><twSrc>switch<2></twSrc><twDest>vga_out_red<6></twDest><twDel>51.405</twDel></twPad2Pad><twPad2Pad><twSrc>switch<2></twSrc><twDest>vga_out_red<7></twDest><twDel>50.343</twDel></twPad2Pad><twPad2Pad><twSrc>switch<5></twSrc><twDest>vga_out_blue<0></twDest><twDel>15.825</twDel></twPad2Pad><twPad2Pad><twSrc>switch<5></twSrc><twDest>vga_out_blue<1></twDest><twDel>15.466</twDel></twPad2Pad><twPad2Pad><twSrc>switch<5></twSrc><twDest>vga_out_blue<2></twDest><twDel>14.330</twDel></twPad2Pad><twPad2Pad><twSrc>switch<5></twSrc><twDest>vga_out_blue<3></twDest><twDel>14.247</twDel></twPad2Pad><twPad2Pad><twSrc>switch<5></twSrc><twDest>vga_out_blue<4></twDest><twDel>14.178</twDel></twPad2Pad><twPad2Pad><twSrc>switch<5></twSrc><twDest>vga_out_blue<5></twDest><twDel>14.852</twDel></twPad2Pad><twPad2Pad><twSrc>switch<5></twSrc><twDest>vga_out_blue<6></twDest><twDel>13.513</twDel></twPad2Pad><twPad2Pad><twSrc>switch<5></twSrc><twDest>vga_out_blue<7></twDest><twDel>13.788</twDel></twPad2Pad><twPad2Pad><twSrc>switch<5></twSrc><twDest>vga_out_green<0></twDest><twDel>14.563</twDel></twPad2Pad><twPad2Pad><twSrc>switch<5></twSrc><twDest>vga_out_green<1></twDest><twDel>15.714</twDel></twPad2Pad><twPad2Pad><twSrc>switch<5></twSrc><twDest>vga_out_green<2></twDest><twDel>13.592</twDel></twPad2Pad><twPad2Pad><twSrc>switch<5></twSrc><twDest>vga_out_green<3></twDest><twDel>14.174</twDel></twPad2Pad><twPad2Pad><twSrc>switch<5></twSrc><twDest>vga_out_green<4></twDest><twDel>16.631</twDel></twPad2Pad><twPad2Pad><twSrc>switch<5></twSrc><twDest>vga_out_green<5></twDest><twDel>15.859</twDel></twPad2Pad><twPad2Pad><twSrc>switch<5></twSrc><twDest>vga_out_green<6></twDest><twDel>16.190</twDel></twPad2Pad><twPad2Pad><twSrc>switch<5></twSrc><twDest>vga_out_green<7></twDest><twDel>15.448</twDel></twPad2Pad><twPad2Pad><twSrc>switch<5></twSrc><twDest>vga_out_red<0></twDest><twDel>16.029</twDel></twPad2Pad><twPad2Pad><twSrc>switch<5></twSrc><twDest>vga_out_red<1></twDest><twDel>14.459</twDel></twPad2Pad><twPad2Pad><twSrc>switch<5></twSrc><twDest>vga_out_red<2></twDest><twDel>15.493</twDel></twPad2Pad><twPad2Pad><twSrc>switch<5></twSrc><twDest>vga_out_red<3></twDest><twDel>15.216</twDel></twPad2Pad><twPad2Pad><twSrc>switch<5></twSrc><twDest>vga_out_red<4></twDest><twDel>18.974</twDel></twPad2Pad><twPad2Pad><twSrc>switch<5></twSrc><twDest>vga_out_red<5></twDest><twDel>15.710</twDel></twPad2Pad><twPad2Pad><twSrc>switch<5></twSrc><twDest>vga_out_red<6></twDest><twDel>16.519</twDel></twPad2Pad><twPad2Pad><twSrc>switch<5></twSrc><twDest>vga_out_red<7></twDest><twDel>15.583</twDel></twPad2Pad><twPad2Pad><twSrc>switch<7></twSrc><twDest>ram0_address<0></twDest><twDel>9.040</twDel></twPad2Pad><twPad2Pad><twSrc>switch<7></twSrc><twDest>ram0_address<1></twDest><twDel>10.037</twDel></twPad2Pad><twPad2Pad><twSrc>switch<7></twSrc><twDest>ram0_address<2></twDest><twDel>7.783</twDel></twPad2Pad><twPad2Pad><twSrc>switch<7></twSrc><twDest>ram0_address<3></twDest><twDel>10.085</twDel></twPad2Pad><twPad2Pad><twSrc>switch<7></twSrc><twDest>ram0_address<4></twDest><twDel>9.027</twDel></twPad2Pad><twPad2Pad><twSrc>switch<7></twSrc><twDest>ram0_address<5></twDest><twDel>7.785</twDel></twPad2Pad><twPad2Pad><twSrc>switch<7></twSrc><twDest>ram0_address<6></twDest><twDel>9.695</twDel></twPad2Pad><twPad2Pad><twSrc>switch<7></twSrc><twDest>ram0_address<7></twDest><twDel>9.769</twDel></twPad2Pad><twPad2Pad><twSrc>switch<7></twSrc><twDest>ram0_address<8></twDest><twDel>11.303</twDel></twPad2Pad><twPad2Pad><twSrc>switch<7></twSrc><twDest>ram0_address<9></twDest><twDel>11.448</twDel></twPad2Pad><twPad2Pad><twSrc>switch<7></twSrc><twDest>ram0_address<10></twDest><twDel>10.186</twDel></twPad2Pad><twPad2Pad><twSrc>switch<7></twSrc><twDest>ram0_address<11></twDest><twDel>9.638</twDel></twPad2Pad><twPad2Pad><twSrc>switch<7></twSrc><twDest>ram0_address<12></twDest><twDel>9.845</twDel></twPad2Pad><twPad2Pad><twSrc>switch<7></twSrc><twDest>ram0_address<13></twDest><twDel>9.981</twDel></twPad2Pad><twPad2Pad><twSrc>switch<7></twSrc><twDest>ram0_address<14></twDest><twDel>10.324</twDel></twPad2Pad><twPad2Pad><twSrc>switch<7></twSrc><twDest>ram0_address<15></twDest><twDel>9.610</twDel></twPad2Pad><twPad2Pad><twSrc>switch<7></twSrc><twDest>ram0_address<16></twDest><twDel>10.968</twDel></twPad2Pad><twPad2Pad><twSrc>switch<7></twSrc><twDest>ram0_address<17></twDest><twDel>11.103</twDel></twPad2Pad><twPad2Pad><twSrc>switch<7></twSrc><twDest>ram0_address<18></twDest><twDel>11.865</twDel></twPad2Pad><twPad2Pad><twSrc>switch<7></twSrc><twDest>ram0_we_b</twDest><twDel>10.314</twDel></twPad2Pad></twPad2PadList><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twFoot><twTimestamp>Tue Dec 13 19:59:19 2016 </twTimestamp></twFoot><twClientInfo><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>
Peak Memory Usage: 720 MB
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