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zbt_6111_sample.twr
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zbt_6111_sample.twr
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--------------------------------------------------------------------------------
Release 10.1.03 Trace (lin64)
Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
/afs/csail.mit.edu/proj/redsocs/Xilinx10.1/ISE/bin/lin64/unwrapped/trce -ise
/afs/athena.mit.edu/user/z/a/zareenc/pc-na-13-dec-1.0/pc-na.ise -intstyle ise
-v 3 -s 4 -xml zbt_6111_sample zbt_6111_sample.ncd -o zbt_6111_sample.twr
zbt_6111_sample.pcf -ucf labkit.ucf
Design file: zbt_6111_sample.ncd
Physical constraint file: zbt_6111_sample.pcf
Device,package,speed: xc2v6000,bf957,-4 (PRODUCTION 1.121 2008-07-25, STEPPING level 0)
Report level: verbose report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Setup/Hold to clock clock_27mhz
-------------+------------+------------+--------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
-------------+------------+------------+--------------------+--------+
button1 | 2.956(R)| -1.215(R)|tv_in_clock_OBUF | 0.000|
button_enter | 3.979(R)| -0.943(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<0> | -2.564(R)| 2.836(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<1> | -2.891(R)| 3.163(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<2> | -3.393(R)| 3.665(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<3> | -3.091(R)| 3.363(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<4> | -2.313(R)| 2.585(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<5> | -2.722(R)| 2.994(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<6> | -2.725(R)| 2.997(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<7> | -2.394(R)| 2.666(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<8> | -2.605(R)| 2.877(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<9> | -1.816(R)| 2.088(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<10>| -2.603(R)| 2.875(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<11>| -2.514(R)| 2.786(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<12>| -2.536(R)| 2.808(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<13>| -1.720(R)| 1.992(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<14>| -2.668(R)| 2.940(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<15>| -2.655(R)| 2.927(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<16>| -3.039(R)| 3.311(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<17>| -2.724(R)| 2.996(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<18>| -2.703(R)| 2.975(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<19>| -3.290(R)| 3.562(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<20>| -2.717(R)| 2.989(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<21>| -1.965(R)| 2.237(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<22>| -2.264(R)| 2.536(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<23>| -3.021(R)| 3.293(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<24>| -2.106(R)| 2.378(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<25>| -2.522(R)| 2.794(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<26>| -2.713(R)| 2.985(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<27>| -2.044(R)| 2.316(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<28>| -3.011(R)| 3.283(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<29>| -2.191(R)| 2.463(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<30>| -3.007(R)| 3.279(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<31>| -1.930(R)| 2.202(R)|analyzer3_clock_OBUF| 0.000|
switch<0> | 0.820(R)| 1.227(R)|analyzer3_clock_OBUF| 0.000|
switch<1> | 0.482(R)| 1.257(R)|analyzer3_clock_OBUF| 0.000|
switch<4> | 0.433(R)| -0.188(R)|analyzer3_clock_OBUF| 0.000|
switch<5> | 0.252(R)| 0.874(R)|analyzer3_clock_OBUF| 0.000|
switch<6> | 0.776(R)| 2.302(R)|analyzer3_clock_OBUF| 0.000|
switch<7> | 1.663(R)| 2.335(R)|analyzer3_clock_OBUF| 0.000|
-------------+------------+------------+--------------------+--------+
Setup/Hold to clock tv_in_line_clock1
---------------+------------+------------+-----------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
---------------+------------+------------+-----------------------+--------+
tv_in_ycrcb<10>| 4.766(R)| -0.008(R)|tv_in_line_clock1_BUFGP| 0.000|
tv_in_ycrcb<11>| 4.950(R)| -0.168(R)|tv_in_line_clock1_BUFGP| 0.000|
tv_in_ycrcb<12>| 4.100(R)| 0.680(R)|tv_in_line_clock1_BUFGP| 0.000|
tv_in_ycrcb<13>| 4.218(R)| -0.647(R)|tv_in_line_clock1_BUFGP| 0.000|
tv_in_ycrcb<14>| 2.980(R)| -0.138(R)|tv_in_line_clock1_BUFGP| 0.000|
tv_in_ycrcb<15>| 3.769(R)| -0.075(R)|tv_in_line_clock1_BUFGP| 0.000|
tv_in_ycrcb<16>| 3.917(R)| -0.587(R)|tv_in_line_clock1_BUFGP| 0.000|
tv_in_ycrcb<17>| 4.093(R)| -0.573(R)|tv_in_line_clock1_BUFGP| 0.000|
tv_in_ycrcb<18>| 4.623(R)| -1.038(R)|tv_in_line_clock1_BUFGP| 0.000|
tv_in_ycrcb<19>| 4.997(R)| -0.843(R)|tv_in_line_clock1_BUFGP| 0.000|
---------------+------------+------------+-----------------------+--------+
Clock clock_27mhz to Pad
------------------+------------+--------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
------------------+------------+--------------------+--------+
Q | 14.030(R)|rc/ram_clock | 0.000|
| 14.030(F)|rc/ram_clock | 0.000|
clock_feedback_out| 12.602(R)|rc/ram_clock | 0.000|
| 12.602(F)|rc/ram_clock | 0.000|
disp_ce_b | 11.457(R)|analyzer3_clock_OBUF| 0.000|
disp_clock | 12.402(R)|analyzer3_clock_OBUF| 0.000|
disp_data_out | 12.353(R)|analyzer3_clock_OBUF| 0.000|
disp_reset_b | 11.454(R)|analyzer3_clock_OBUF| 0.000|
disp_rs | 10.876(R)|analyzer3_clock_OBUF| 0.000|
led<2> | 14.447(R)|analyzer3_clock_OBUF| 0.000|
ram0_address<0> | 26.844(R)|analyzer3_clock_OBUF| 0.000|
ram0_address<1> | 25.887(R)|analyzer3_clock_OBUF| 0.000|
ram0_address<2> | 25.753(R)|analyzer3_clock_OBUF| 0.000|
ram0_address<3> | 26.866(R)|analyzer3_clock_OBUF| 0.000|
ram0_address<4> | 26.218(R)|analyzer3_clock_OBUF| 0.000|
ram0_address<5> | 26.427(R)|analyzer3_clock_OBUF| 0.000|
ram0_address<6> | 25.985(R)|analyzer3_clock_OBUF| 0.000|
ram0_address<7> | 26.468(R)|analyzer3_clock_OBUF| 0.000|
ram0_address<8> | 22.643(R)|analyzer3_clock_OBUF| 0.000|
ram0_address<9> | 23.248(R)|analyzer3_clock_OBUF| 0.000|
ram0_address<10> | 23.082(R)|analyzer3_clock_OBUF| 0.000|
ram0_address<11> | 22.614(R)|analyzer3_clock_OBUF| 0.000|
ram0_address<12> | 22.270(R)|analyzer3_clock_OBUF| 0.000|
ram0_address<13> | 23.003(R)|analyzer3_clock_OBUF| 0.000|
ram0_address<14> | 23.651(R)|analyzer3_clock_OBUF| 0.000|
ram0_address<15> | 22.841(R)|analyzer3_clock_OBUF| 0.000|
ram0_address<16> | 24.121(R)|analyzer3_clock_OBUF| 0.000|
ram0_address<17> | 23.469(R)|analyzer3_clock_OBUF| 0.000|
ram0_address<18> | 25.135(R)|analyzer3_clock_OBUF| 0.000|
ram0_clk | 12.499(R)|rc/ram_clock | 0.000|
| 12.499(F)|rc/ram_clock | 0.000|
ram0_data<0> | 11.399(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<1> | 10.745(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<2> | 11.034(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<3> | 10.751(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<4> | 11.036(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<5> | 10.239(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<6> | 9.745(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<7> | 10.245(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<8> | 9.836(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<9> | 12.246(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<10> | 11.671(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<11> | 12.258(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<12> | 11.077(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<13> | 11.673(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<14> | 11.080(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<15> | 11.378(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<16> | 9.425(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<17> | 10.030(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<18> | 9.753(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<19> | 9.791(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<20> | 10.582(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<21> | 10.785(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<22> | 11.681(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<23> | 10.793(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<24> | 11.685(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<25> | 12.270(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<26> | 10.768(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<27> | 11.035(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<28> | 11.062(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<29> | 11.934(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<30> | 11.075(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<31> | 11.926(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<32> | 11.660(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<33> | 11.647(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<34> | 12.266(R)|analyzer3_clock_OBUF| 0.000|
ram0_data<35> | 10.430(R)|analyzer3_clock_OBUF| 0.000|
ram0_we_b | 18.367(R)|analyzer3_clock_OBUF| 0.000|
vga_out_blank_b | 11.865(R)|analyzer3_clock_OBUF| 0.000|
vga_out_blue<0> | 91.259(R)|analyzer3_clock_OBUF| 0.000|
vga_out_blue<1> | 91.356(R)|analyzer3_clock_OBUF| 0.000|
vga_out_blue<2> | 91.285(R)|analyzer3_clock_OBUF| 0.000|
vga_out_blue<3> | 91.048(R)|analyzer3_clock_OBUF| 0.000|
vga_out_blue<4> | 92.104(R)|analyzer3_clock_OBUF| 0.000|
vga_out_blue<5> | 92.997(R)|analyzer3_clock_OBUF| 0.000|
vga_out_blue<6> | 92.348(R)|analyzer3_clock_OBUF| 0.000|
vga_out_blue<7> | 92.497(R)|analyzer3_clock_OBUF| 0.000|
vga_out_green<0> | 94.371(R)|analyzer3_clock_OBUF| 0.000|
vga_out_green<1> | 95.940(R)|analyzer3_clock_OBUF| 0.000|
vga_out_green<2> | 98.801(R)|analyzer3_clock_OBUF| 0.000|
vga_out_green<3> | 94.898(R)|analyzer3_clock_OBUF| 0.000|
vga_out_green<4> | 98.150(R)|analyzer3_clock_OBUF| 0.000|
vga_out_green<5> | 100.793(R)|analyzer3_clock_OBUF| 0.000|
vga_out_green<6> | 101.111(R)|analyzer3_clock_OBUF| 0.000|
vga_out_green<7> | 96.872(R)|analyzer3_clock_OBUF| 0.000|
vga_out_hsync | 12.286(R)|analyzer3_clock_OBUF| 0.000|
vga_out_red<0> | 97.073(R)|analyzer3_clock_OBUF| 0.000|
vga_out_red<1> | 96.243(R)|analyzer3_clock_OBUF| 0.000|
vga_out_red<2> | 96.493(R)|analyzer3_clock_OBUF| 0.000|
vga_out_red<3> | 96.990(R)|analyzer3_clock_OBUF| 0.000|
vga_out_red<4> | 100.365(R)|analyzer3_clock_OBUF| 0.000|
vga_out_red<5> | 97.643(R)|analyzer3_clock_OBUF| 0.000|
vga_out_red<6> | 98.100(R)|analyzer3_clock_OBUF| 0.000|
vga_out_red<7> | 97.038(R)|analyzer3_clock_OBUF| 0.000|
vga_out_vsync | 11.967(R)|analyzer3_clock_OBUF| 0.000|
------------------+------------+--------------------+--------+
Clock to Setup on destination clock clock_27mhz
-----------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
-----------------+---------+---------+---------+---------+
clock_27mhz | 41.309| | | |
tv_in_line_clock1| 3.463| | | |
-----------------+---------+---------+---------+---------+
Clock to Setup on destination clock tv_in_line_clock1
-----------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
-----------------+---------+---------+---------+---------+
clock_27mhz | 11.443| | | |
tv_in_line_clock1| 7.597| | | |
-----------------+---------+---------+---------+---------+
Pad to Pad
---------------+-------------------+---------+
Source Pad |Destination Pad | Delay |
---------------+-------------------+---------+
clock_27mhz |analyzer3_clock | 12.071|
clock_27mhz |tv_in_clock | 11.990|
clock_27mhz |vga_out_pixel_clock| 11.511|
switch<2> |vga_out_blue<0> | 48.788|
switch<2> |vga_out_blue<1> | 48.878|
switch<2> |vga_out_blue<2> | 48.559|
switch<2> |vga_out_blue<3> | 48.026|
switch<2> |vga_out_blue<4> | 48.397|
switch<2> |vga_out_blue<5> | 48.990|
switch<2> |vga_out_blue<6> | 47.775|
switch<2> |vga_out_blue<7> | 47.916|
switch<2> |vga_out_green<0> | 49.135|
switch<2> |vga_out_green<1> | 50.704|
switch<2> |vga_out_green<2> | 52.106|
switch<2> |vga_out_green<3> | 48.909|
switch<2> |vga_out_green<4> | 51.506|
switch<2> |vga_out_green<5> | 54.098|
switch<2> |vga_out_green<6> | 54.416|
switch<2> |vga_out_green<7> | 50.228|
switch<2> |vga_out_red<0> | 50.429|
switch<2> |vga_out_red<1> | 49.599|
switch<2> |vga_out_red<2> | 49.849|
switch<2> |vga_out_red<3> | 50.346|
switch<2> |vga_out_red<4> | 53.670|
switch<2> |vga_out_red<5> | 50.948|
switch<2> |vga_out_red<6> | 51.405|
switch<2> |vga_out_red<7> | 50.343|
switch<5> |vga_out_blue<0> | 15.825|
switch<5> |vga_out_blue<1> | 15.466|
switch<5> |vga_out_blue<2> | 14.330|
switch<5> |vga_out_blue<3> | 14.247|
switch<5> |vga_out_blue<4> | 14.178|
switch<5> |vga_out_blue<5> | 14.852|
switch<5> |vga_out_blue<6> | 13.513|
switch<5> |vga_out_blue<7> | 13.788|
switch<5> |vga_out_green<0> | 14.563|
switch<5> |vga_out_green<1> | 15.714|
switch<5> |vga_out_green<2> | 13.592|
switch<5> |vga_out_green<3> | 14.174|
switch<5> |vga_out_green<4> | 16.631|
switch<5> |vga_out_green<5> | 15.859|
switch<5> |vga_out_green<6> | 16.190|
switch<5> |vga_out_green<7> | 15.448|
switch<5> |vga_out_red<0> | 16.029|
switch<5> |vga_out_red<1> | 14.459|
switch<5> |vga_out_red<2> | 15.493|
switch<5> |vga_out_red<3> | 15.216|
switch<5> |vga_out_red<4> | 18.974|
switch<5> |vga_out_red<5> | 15.710|
switch<5> |vga_out_red<6> | 16.519|
switch<5> |vga_out_red<7> | 15.583|
switch<7> |ram0_address<0> | 9.040|
switch<7> |ram0_address<1> | 10.037|
switch<7> |ram0_address<2> | 7.783|
switch<7> |ram0_address<3> | 10.085|
switch<7> |ram0_address<4> | 9.027|
switch<7> |ram0_address<5> | 7.785|
switch<7> |ram0_address<6> | 9.695|
switch<7> |ram0_address<7> | 9.769|
switch<7> |ram0_address<8> | 11.303|
switch<7> |ram0_address<9> | 11.448|
switch<7> |ram0_address<10> | 10.186|
switch<7> |ram0_address<11> | 9.638|
switch<7> |ram0_address<12> | 9.845|
switch<7> |ram0_address<13> | 9.981|
switch<7> |ram0_address<14> | 10.324|
switch<7> |ram0_address<15> | 9.610|
switch<7> |ram0_address<16> | 10.968|
switch<7> |ram0_address<17> | 11.103|
switch<7> |ram0_address<18> | 11.865|
switch<7> |ram0_we_b | 10.314|
---------------+-------------------+---------+
Analysis completed Tue Dec 13 19:59:19 2016
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 720 MB