any example on the project?

[blueardour]

Hi, @xuanyoya

Thanks for the interesting project. I'm reading the related paper 'A Systematic Approach to blocking convolutional neural networks' and found it could be more useful to take this project to get better understand of the paper.

However, i still could not fully understand how an optimal schedule is searched. kentaroy47 provide an example in his/her fork: patch-3.
) It seems that only half of the PEs are used. And also I don't if it is an error for his/her last image. In the ICO and ICI loop, the iteration number should be 6*16 in my thought.

I wonder if you would add any example or tutorial in this project? Very thanks for that

[blueardour]

Hi, @xuanyoya
I notice you add a readme in the arch subfolder. For the
"capacity": "[1st level buffer size, 2nd level buffer size, ...]",

does it mean the 1st level buffer size is the register buffer and the 2nd level buffer size the global SRAM buffer. Assume 64*1 PE in the systems, and capacity is [256, 1024, 256000], does it mean the chip has 64 PE, each own a 256 bytes of private ram and sharing a 1024 bytes global SRAM and 256000 bytes of DDR SRAM?

ps. It is exciting to notice you are stilling updating the project.