From 8fc1f99640b2aad2ff9271826d59782c076e3f80 Mon Sep 17 00:00:00 2001 From: Jeremiah McCarthy Date: Tue, 20 Jun 2023 14:41:38 -0400 Subject: [PATCH 01/36] Initial TDM API for TX 16 Note full featured library skeleton in place but not feature full yet. i2s_tdm_slave_tx_16 currently makes assumptions that may change. --- modules/i2s/api/i2s.h | 20 ++-- modules/i2s/api/i2s_tdm_slave.h | 198 ++++++++++++++++++++++++++++++++ modules/i2s/src/i2s_tdm_slave.c | 183 +++++++++++++++++++++++++++++ 3 files changed, 393 insertions(+), 8 deletions(-) create mode 100644 modules/i2s/api/i2s_tdm_slave.h create mode 100644 modules/i2s/src/i2s_tdm_slave.c diff --git a/modules/i2s/api/i2s.h b/modules/i2s/api/i2s.h index 01a22c5..a7b3073 100644 --- a/modules/i2s/api/i2s.h +++ b/modules/i2s/api/i2s.h @@ -1,4 +1,4 @@ -// Copyright 2021-2022 XMOS LIMITED. +// Copyright 2021-2023 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #ifndef _i2s_h_ #define _i2s_h_ @@ -47,9 +47,9 @@ typedef enum i2s_slave_bclk_polarity { * This structure describes the configuration of an I2S bus. */ typedef struct i2s_config { - unsigned mclk_bclk_ratio; /**< The ratio between the master clock and bit clock signals. */ - i2s_mode_t mode; /**< The mode of the LR clock. */ - i2s_slave_bclk_polarity_t slave_bclk_polarity; /**< Slave bit clock polarity. */ + unsigned mclk_bclk_ratio; /**< The ratio between the master clock and bit clock signals. */ + i2s_mode_t mode; /**< The mode of the LR clock. */ + i2s_slave_bclk_polarity_t slave_bclk_polarity; /**< Slave bit clock polarity. */ } i2s_config_t; /** @@ -58,9 +58,9 @@ typedef struct i2s_config { * Restart commands that can be signalled to the I2S or TDM component. */ typedef enum i2s_restart { - I2S_NO_RESTART = 0, /**< Do not restart. */ - I2S_RESTART, /**< Restart the bus (causes the I2S/TDM to stop and a new init callback to occur allowing reconfiguration of the BUS). */ - I2S_SHUTDOWN /**< Shutdown. This will cause the I2S/TDM component to exit. */ + I2S_NO_RESTART = 0, /**< Do not restart. */ + I2S_RESTART, /**< Restart the bus (causes the I2S/TDM to stop and a new init callback to occur allowing reconfiguration of the BUS). */ + I2S_SHUTDOWN /**< Shutdown. This will cause the I2S/TDM component to exit. */ } i2s_restart_t; /** @@ -73,10 +73,13 @@ typedef enum i2s_restart { * by the application. May be used for context * data specific to each I2S task instance. * + * This will contain the TDM context when in TDM mode. + * * \param i2s_config This structure is provided if the connected * component drives an I2S bus. The members * of the structure should be set to the - * required configuration. + * required configuration. This is ignored when + * used in TDM mode. */ typedef void (*i2s_init_t)(void *app_data, i2s_config_t *i2s_config); @@ -161,6 +164,7 @@ typedef struct { void *app_data; } i2s_callback_group_t; + /**@}*/ // END: addtogroup hil_i2s_core DECLARE_JOB(i2s_master, (const i2s_callback_group_t *, const port_t *, const size_t, const port_t *, const size_t, const port_t, const port_t, const port_t, const xclock_t)); diff --git a/modules/i2s/api/i2s_tdm_slave.h b/modules/i2s/api/i2s_tdm_slave.h new file mode 100644 index 0000000..db21b68 --- /dev/null +++ b/modules/i2s/api/i2s_tdm_slave.h @@ -0,0 +1,198 @@ +// Copyright 2023 XMOS LIMITED. +// This Software is subject to the terms of the XMOS Public Licence: Version 1. +#pragma once + +#include +#include +#include + +#include +#include +#include + +#include "i2s.h" + +/** + * \addtogroup hil_i2s_tdm_core hil_i2s_tdm_core + * + * The public API for using the HIL I2S TDM core. + * @{ + */ + +#define I2S_TDM_MAX_POUT_CNT 4 +#define I2S_TDM_MAX_PIN_CNT 4 + +/* Max channels per frame. This is overrideable to enable + * memory savings in specific applications by allowing + * IO buffers to be optimal size, saving up to + * word length bytes * (default val - app defined value) bytes. + */ +#ifndef I2S_TDM_MAX_CH_PER_FRAME +#define I2S_TDM_MAX_CH_PER_FRAME 16 +#endif /* I2S_TDM_MAX_CH_PER_FRAME */ + +/** + * Struct to hold an I2S TDM context. + * + * The members in this struct should not be accessed directly. + */ +typedef struct { + i2s_callback_group_t *const i2s_cbg; + port_t p_dout[I2S_TDM_MAX_POUT_CNT]; + size_t num_out; + port_t p_din[I2S_TDM_MAX_PIN_CNT]; + size_t num_in; + port_t p_fsync; + port_t p_bclk; + xclock_t bclk; + uint32_t tx_offset; + uint32_t fsync_len; + uint32_t word_len; + uint32_t ch_len; + uint32_t ch_per_frame; + i2s_slave_bclk_polarity_t slave_bclk_polarity; + void *app_data; +} i2s_tdm_ctx_t; + +/**@}*/ // END: addtogroup hil_i2s_tdm_core + +DECLARE_JOB(i2s_tdm_slave_tx_16, (const i2s_tdm_ctx_t *)); +DECLARE_JOB(i2s_slave_tdm, (const i2s_tdm_ctx_t *)); + +/** + * \addtogroup hil_i2s_tdm_slave_tx16 hil_i2s_tdm_slave_tx16 + * + * The public API for using the HIL I2S TDM TX 16 slave. + * @{ + */ + +/** + * I2S TDM slave context initialization for 16 channel TX only with + * 1 output port, 32b word length, 32b channel length, + * and 16 channels per frame. + * + * This prepares a context for I2S TDM slave on the provided pins. + * + * The resulting context can be used with i2s_tdm_slave_tx_16_thread(). + * + * \param ctx A pointer to the I2S TDM context to use. + * \param i2s_cbg The I2S callback group pointing to the application's + * functions to use for initialization and getting and receiving + * frames. For TDM the app_data variable within this + * struct is NOT used. + * \param p_dout The data output port. MUST be a 1b port + * \param p_fsync The fsync input port. MUST be a 1b port + * \param p_bclk The bit clock input port. MUST be a 1b port + * \param bclk A clock that will get configured for use with + * the bit clock + * \param tx_offset The number of bclks from FSYNC transition to the MSB + * of Slot 0 + * \param app_data A pointer to application specific data supplied + * by the application. May be used for context + * data specific to each I2S task instance. + */ +void tdm_slave_tx_16_init( + const i2s_tdm_ctx_t *ctx, + const i2s_callback_group_t *const i2s_cbg, + const port_t p_dout, + const port_t p_fsync, + const port_t p_bclk, + const xclock_t bclk, + const uint32_t tx_offset, + void *app_data); + +/** + * I2S TDM TX 16 ch slave task + * + * This task performs I2S TDM slave on the provided context which was + * initialized with tdm_slave_tx_16_init(). It will perform + * callbacks over the i2s_callback_group_t callback group to get + * data from the application using this component. + * + * This thread outputs assumes 1 output port, 32b word length, + * 32b channel length, and 16 channels per frame. + * + * The component performs I2S TDM slave so will expect the fsync and + * bit clock to be driven externally. + * + * \param ctx A pointer to the I2S TDM context to use. + */ +void i2s_tdm_slave_tx_16_thread( + const i2s_tdm_ctx_t *ctx); + +/**@}*/ // END: addtogroup hil_i2s_tdm_slave_tx16 + +/** + * \addtogroup hil_i2s_tdm_slave hil_i2s_tdm_slave + * + * The public API for using the HIL I2S TDM generic slave. + * @{ + */ + +/** + * I2S generic TDM slave context initialization + * + * This prepares a context for I2S TDM slave on the provided pins. + * + * The resulting context can be used with an I2S thread call. + * + * \param ctx A pointer to the I2S TDM context to use. + * \param i2s_cbg The I2S callback group pointing to the application's + * functions to use for initialization and getting and receiving + * frames. For TDM the app_data variable within this + * struct is NOT used. + * \param p_dout An array of data output ports. MUST be 1b ports + * \param num_out The number of output data ports + * \param p_din An array of data input ports. MUST be 1b ports + * \param num_in The number of input data ports + * \param p_fsync The fsync input port. MUST be a 1b port + * \param p_bclk The bit clock input port. MUST be a 1b port + * \param bclk A clock that will get configured for use with + * the bit clock + * \param tx_offset The number of bclks from FSYNC transition to the MSB + * of Slot 0 + * \param fsync_len The length of the FSYNC in BCLKS + * \param word_len The number of bits in each sample frame slot. + * MUST be 32. + * \param ch_len The number of bits in each channel. MUST be less than + * word_len + * \param ch_per_frame The number of channels per frame + * \param slave_bclk_pol The polarity of bclk + * \param app_data A pointer to application specific data supplied + * by the application. May be used for context + * data specific to each I2S task instance. + */ +void i2s_tdm_slave_init( + const i2s_tdm_ctx_t *ctx, + const i2s_callback_group_t *const i2s_cbg, + const port_t p_dout[], + const size_t num_out, + const port_t p_din[], + const size_t num_in, + const port_t p_fsync, + const port_t p_bclk, + const xclock_t bclk, + const uint32_t tx_offset, + const uint32_t fsync_len, + const uint32_t word_len, + const uint32_t ch_len, + const uint32_t ch_per_frame, + i2s_slave_bclk_polarity_t slave_bclk_pol, + void *app_data); + +/** + * I2S generic TDM slave task + * + * This task performs I2S TDM slave on the provided context. It will perform + * callbacks over the i2s_callback_group_t callback group to get/receive + * data from the application using this component. + * + * The component performs I2S TDM slave so will expect the fsync and + * bit clock to be driven externally. + * + * \param ctx A pointer to the I2S TDM context to use. + */ +void i2s_slave_tdm_thread( + const i2s_tdm_ctx_t *ctx); + +/**@}*/ // END: addtogroup hil_i2s_tdm_slave \ No newline at end of file diff --git a/modules/i2s/src/i2s_tdm_slave.c b/modules/i2s/src/i2s_tdm_slave.c new file mode 100644 index 0000000..e3ef077 --- /dev/null +++ b/modules/i2s/src/i2s_tdm_slave.c @@ -0,0 +1,183 @@ +// Copyright 2023 XMOS LIMITED. +// This Software is subject to the terms of the XMOS Public Licence: Version 1. +#include +#include +#include +#include +#include + +#include "i2s.h" +#include "i2s_tdm.h" + +void i2s_tdm_slave_init( + const i2s_tdm_ctx_t *ctx, + const i2s_callback_group_t *const i2s_cbg, + const port_t p_dout[], + const size_t num_out, + const port_t p_din[], + const size_t num_in, + const port_t p_fsync, + const port_t p_bclk, + const xclock_t bclk, + const uint32_t tx_offset, + const uint32_t fsync_len, + const uint32_t word_len, + const uint32_t ch_len, + const uint32_t ch_per_frame, + i2s_slave_bclk_polarity_t slave_bclk_pol, + void *app_data); +{ + memset(&ctx, 0, sizeof(i2s_tdm_ctx_t)); + ctx->i2s_cbg = i2s_cbg; + + xassert(num_out <= I2S_TDM_MAX_POUT_CNT); + memcpy(ctx->p_dout, p_dout, sizeof(port_t) * num_out); + xassert(num_in <= I2S_TDM_MAX_PIN_CNT); + memcpy(ctx->p_din, p_din, sizeof(port_t) * num_in); + + ctx->p_fsync = p_fsync; + ctx->p_bclk = p_bclk; + ctx->bclk = bclk; + ctx->tx_offset = tx_offset; + ctx->fsync_len = 1; /* Does not matter for slave as we only care about rising or falling edge */ + ctx->word_len = word_len; + ctx->ch_len = ch_len; + ctx->ch_per_frame = ch_per_frame; + ctx->slave_bclk_polarity = I2S_SLAVE_SAMPLE_ON_BCLK_RISING; + ctx->app_data = app_data; +} + +void i2s_tdm_slave_tx_16_init( + const i2s_tdm_ctx_t *ctx, + const i2s_callback_group_t *const i2s_cbg, + const port_t p_fsync, + const port_t p_dout, + const port_t p_bclk, + const xclock_t bclk, + const uint32_t tx_offset, + i2s_slave_bclk_polarity_t slave_bclk_polarity, + void *app_data)) +{ + memset(&ctx, 0, sizeof(i2s_tdm_ctx_t)); + port_t pdout = p_dout; + + i2s_tdm_slave_init( + ctx, + i2s_cbg, + &pdout, + 1, + NULL, + 0, + p_fsync, + p_bclk, + bclk, + tx_offset, + 1, /* fsync_len: Does not matter for slave as we only care about edge */ + 32, /* word len */ + 32, /* ch len */ + 16 /* ch per frame */ + slave_bclk_polarity, + app_data); +} + +static void i2s_tdm_slave_init_resources( + const i2s_tdm_ctx_t *ctx) +{ + port_enable(ctx->p_bclk); + clock_enable(ctx->bclk); + clock_set_source_port(ctx->bclk, ctx->p_blck); + + for(int i=0; inum_out; i++) { + port_start_buffered(ctx->p_dout[i], 32); + port_set_clock(ctx->p_dout[i], ctx->bclk); + } + for(int i=0; inum_in; i++) { + port_start_buffered(ctx->p_din[i], 32); + port_set_clock(ctx->p_din[i], ctx->bclk); + } + port_start_buffered(ctx->p_fsync, 32); + port_set_clock(ctx->p_fsync, ctx->bclk); + + if (ctx->slave_bclk_polarity == I2S_SLAVE_SAMPLE_ON_BCLK_FALLING) { + set_port_inv(ctx->p_bclk); + } else { + set_port_no_inv(ctx->p_bclk); + } +} + +static void i2s_tdm_slave_deinit_resources( + const i2s_tdm_ctx_t *ctx) +{ + clock_disable(ctx->bclk); + port_disable(ctx->p_bclk); + + for(int i=0; inum_out; i++) { + port_disable(ctx->p_dout[i]); + } + for(int i=0; inum_in; i++) { + port_disable(ctx->p_din[i]); + } +} + +void i2s_tdm_slave_tx_16( + const i2s_tdm_ctx_t *ctx) +{ + uint32_t out_samps[I2S_TDM_MAX_CH_PER_FRAME]; + uint32_t fsync_valid; + + if (ctx->i2s_cbg->init != NULL) { + ctx->i2s_cbg->init((void*)ctx, NULL); + } + xassert(ctx->num_out == 1); + + i2s_tdm_slave_init_resources(ctx); + + uint32_t port_frame_time = (ctx->ch_per_frame * ctx->word_len); + + /* Determine bclks for tx offset setting */ + uint32_t tx_offset_word_clks = ctx->tx_offset / 32; + uint32_t tx_offset_rem_clks = ctx->tx_offset % 32; + + /* Wait for first fsync rising edge to occur */ + port_set_trigger_in_equal(ctx->p_fsync, 0); + (void) port_in(ctx->p_fsync); + port_set_trigger_in_equal(ctx->p_fsync, 1); + (void) port_in(ctx->p_fsync); + port_timestamp_t fsync_edge_time = port_get_trigger_time(ctx->p_fsync); + + port_set_trigger_time(ctx->p_dout[0], port_frame_time + fsync_edge_time); + + while(1) { + /* Assume at this point in time we are always at fsync edge */ + /* TODO how would we best check that we have stayed in sync also what if we did get out of sync? do we just implicitly exit or do we add another callback to alert app */ + for (int i=0; ip_dout[0]); + } + if (tx_offset_rem_clks > 0) { + port_set_shift_count(ctx->p_dout[0], tx_offset_rem_clks); + (void) port_in(ctx->p_dout[0]); + port_set_shift_count(ctx->p_dout[0], ctx->word_len); + } + + /* Get frame data and tx */ + ctx->i2s_cbg->send((void*)ctx, ctx->ch_per_frame, out_samps); + + for (int i=0; ich_per_frame; i++) { + port_out(ctx->p_dout[0], bitrev(out_samps[i])); + } + + /* Check for exit condition */ + if (ctx->i2s_cbg->restart_check != NULL) { + if (ctx->i2s_cbg->restart_check(ctx) == I2S_SHUTDOWN) { + i2s_tdm_slave_deinit_resources(ctx); + return; + } + } + } +} + +void i2s_slave_tdm_thread( + const i2s_tdm_ctx_t *ctx) +{ + xassert(0); /* Not yet implemented */ +} \ No newline at end of file From 76e7b74b460209be1978d7f52031e7de3ea44f31 Mon Sep 17 00:00:00 2001 From: Jeremiah McCarthy Date: Thu, 22 Jun 2023 11:37:24 -0400 Subject: [PATCH 02/36] tdm slave updates --- modules/i2s/src/i2s_tdm_slave.c | 91 +++++++++++++++++++-------------- modules/mic_array | 2 +- modules/xud/lib_xud | 2 +- test/lib_i2s/lib_i2s.cmake | 1 + 4 files changed, 55 insertions(+), 41 deletions(-) diff --git a/modules/i2s/src/i2s_tdm_slave.c b/modules/i2s/src/i2s_tdm_slave.c index e3ef077..b1a713d 100644 --- a/modules/i2s/src/i2s_tdm_slave.c +++ b/modules/i2s/src/i2s_tdm_slave.c @@ -50,8 +50,8 @@ void i2s_tdm_slave_init( void i2s_tdm_slave_tx_16_init( const i2s_tdm_ctx_t *ctx, const i2s_callback_group_t *const i2s_cbg, - const port_t p_fsync, const port_t p_dout, + const port_t p_fsync, const port_t p_bclk, const xclock_t bclk, const uint32_t tx_offset, @@ -90,13 +90,16 @@ static void i2s_tdm_slave_init_resources( for(int i=0; inum_out; i++) { port_start_buffered(ctx->p_dout[i], 32); port_set_clock(ctx->p_dout[i], ctx->bclk); + port_clear_buffer(ctx->p_dout[i]); } for(int i=0; inum_in; i++) { port_start_buffered(ctx->p_din[i], 32); port_set_clock(ctx->p_din[i], ctx->bclk); + port_clear_buffer(ctx->p_din[i]); } port_start_buffered(ctx->p_fsync, 32); port_set_clock(ctx->p_fsync, ctx->bclk); + port_clear_buffer(ctx->p_fsync); if (ctx->slave_bclk_polarity == I2S_SLAVE_SAMPLE_ON_BCLK_FALLING) { set_port_inv(ctx->p_bclk); @@ -123,61 +126,71 @@ void i2s_tdm_slave_tx_16( const i2s_tdm_ctx_t *ctx) { uint32_t out_samps[I2S_TDM_MAX_CH_PER_FRAME]; - uint32_t fsync_valid; + uint32_t fsync_val = 0; - if (ctx->i2s_cbg->init != NULL) { - ctx->i2s_cbg->init((void*)ctx, NULL); - } - xassert(ctx->num_out == 1); - - i2s_tdm_slave_init_resources(ctx); + while(1) { + if (ctx->i2s_cbg->init != NULL) { + ctx->i2s_cbg->init((void*)ctx, NULL); + } + xassert(ctx->num_out == 1); - uint32_t port_frame_time = (ctx->ch_per_frame * ctx->word_len); + i2s_tdm_slave_init_resources(ctx); - /* Determine bclks for tx offset setting */ - uint32_t tx_offset_word_clks = ctx->tx_offset / 32; - uint32_t tx_offset_rem_clks = ctx->tx_offset % 32; + /* Get first frame data */ + ctx->i2s_cbg->send((void*)ctx, ctx->ch_per_frame, out_samps); - /* Wait for first fsync rising edge to occur */ - port_set_trigger_in_equal(ctx->p_fsync, 0); - (void) port_in(ctx->p_fsync); - port_set_trigger_in_equal(ctx->p_fsync, 1); - (void) port_in(ctx->p_fsync); - port_timestamp_t fsync_edge_time = port_get_trigger_time(ctx->p_fsync); + uint32_t port_frame_time = (ctx->ch_per_frame * ctx->word_len); - port_set_trigger_time(ctx->p_dout[0], port_frame_time + fsync_edge_time); + /* Wait for first fsync rising edge to occur */ + port_set_trigger_in_equal(ctx->p_fsync, 0); + (void) port_in(ctx->p_fsync); + port_set_trigger_in_equal(ctx->p_fsync, 1); + (void) port_in(ctx->p_fsync); + port_timestamp_t fsync_edge_time = port_get_trigger_time(ctx->p_fsync); - while(1) { - /* Assume at this point in time we are always at fsync edge */ - /* TODO how would we best check that we have stayed in sync also what if we did get out of sync? do we just implicitly exit or do we add another callback to alert app */ - for (int i=0; ip_dout[0]); - } - if (tx_offset_rem_clks > 0) { - port_set_shift_count(ctx->p_dout[0], tx_offset_rem_clks); - (void) port_in(ctx->p_dout[0]); - port_set_shift_count(ctx->p_dout[0], ctx->word_len); - } - - /* Get frame data and tx */ - ctx->i2s_cbg->send((void*)ctx, ctx->ch_per_frame, out_samps); - + /* Setup trigger times */ + uint32_t fsync_trig_time = port_frame_time + ctx->word_len + fsync_edge_time - 1; + port_set_trigger_time(ctx->p_fsync, fsync_trig_time); + port_set_trigger_time(ctx->p_dout[0], port_frame_time + fsync_edge_time + ctx->tx_offset); for (int i=0; ich_per_frame; i++) { port_out(ctx->p_dout[0], bitrev(out_samps[i])); } - /* Check for exit condition */ - if (ctx->i2s_cbg->restart_check != NULL) { - if (ctx->i2s_cbg->restart_check(ctx) == I2S_SHUTDOWN) { - i2s_tdm_slave_deinit_resources(ctx); - return; + while(1) { + fsync_val = port_in(ctx->p_fsync); + /* We only care about seeing the rising edge */ + fsync_val &= 0xc0000000; + if (fsync_val != 0x80000000) { + printf("fsync error, expected 0x%x, was %x0x\n", 0x80000000, fsync_val); + break; + } + + /* Get frame data and tx */ + ctx->i2s_cbg->send((void*)ctx, ctx->ch_per_frame, out_samps); + + for (int i=0; ich_per_frame; i++) { + port_out(ctx->p_dout[0], bitrev(out_samps[i])); + } + + /* Check for exit condition */ + if (ctx->i2s_cbg->restart_check != NULL) { + i2s_restart_t restart = ctx->i2s_cbg->restart_check((void*)ctx); + + if (restart == I2S_RESTART) { + break; + } else if (restart == I2S_SHUTDOWN) { + i2s_tdm_slave_deinit_resources(ctx); + return; + } } } + i2s_tdm_slave_deinit_resources(ctx); } } void i2s_slave_tdm_thread( const i2s_tdm_ctx_t *ctx) { + printf("Not implemented\n"); xassert(0); /* Not yet implemented */ } \ No newline at end of file diff --git a/modules/mic_array b/modules/mic_array index ccfd6d7..c045fc2 160000 --- a/modules/mic_array +++ b/modules/mic_array @@ -1 +1 @@ -Subproject commit ccfd6d72f04c816dd5b2c615e352ce12c6f8edf3 +Subproject commit c045fc228777baccf5defd7710d029312ede4847 diff --git a/modules/xud/lib_xud b/modules/xud/lib_xud index d5a9973..50dfe9f 160000 --- a/modules/xud/lib_xud +++ b/modules/xud/lib_xud @@ -1 +1 @@ -Subproject commit d5a99733f9c23e2cf48cc1bc526a8c0b267b97a9 +Subproject commit 50dfe9f62f20c7dc752f2bdc2be17e4498e60bc3 diff --git a/test/lib_i2s/lib_i2s.cmake b/test/lib_i2s/lib_i2s.cmake index efb52da..ee577c6 100644 --- a/test/lib_i2s/lib_i2s.cmake +++ b/test/lib_i2s/lib_i2s.cmake @@ -2,3 +2,4 @@ include(${CMAKE_CURRENT_LIST_DIR}/backpressure_test/backpressure_test.cmake) include(${CMAKE_CURRENT_LIST_DIR}/i2s_master_external_clock_test/i2s_master_external_clock_test.cmake) include(${CMAKE_CURRENT_LIST_DIR}/i2s_master_test/i2s_master_test.cmake) include(${CMAKE_CURRENT_LIST_DIR}/i2s_slave_test/i2s_slave_test.cmake) +include(${CMAKE_CURRENT_LIST_DIR}/tdm_slave_tx16_cb_test/i2s_tdm_tx16_slave_test.cmake) From 88b4c83de39cc79c29da3e3c72002002a6fed9cd Mon Sep 17 00:00:00 2001 From: Jeremiah McCarthy Date: Thu, 22 Jun 2023 11:42:39 -0400 Subject: [PATCH 03/36] Add initial test --- .../expected/tdm_slave_tx16_cb_test.expect | 1 + .../i2s_tdm_tx16_slave_test.cmake | 46 ++++++++++ .../src/tdm_slave_tx16_test.c | 86 +++++++++++++++++++ test/lib_i2s/test_tdm_slave_tx16_cb.py | 42 +++++++++ 4 files changed, 175 insertions(+) create mode 100644 test/lib_i2s/expected/tdm_slave_tx16_cb_test.expect create mode 100644 test/lib_i2s/tdm_slave_tx16_cb_test/i2s_tdm_tx16_slave_test.cmake create mode 100644 test/lib_i2s/tdm_slave_tx16_cb_test/src/tdm_slave_tx16_test.c create mode 100644 test/lib_i2s/test_tdm_slave_tx16_cb.py diff --git a/test/lib_i2s/expected/tdm_slave_tx16_cb_test.expect b/test/lib_i2s/expected/tdm_slave_tx16_cb_test.expect new file mode 100644 index 0000000..1ab1e70 --- /dev/null +++ b/test/lib_i2s/expected/tdm_slave_tx16_cb_test.expect @@ -0,0 +1 @@ +TDM Slave 16 Checker Started \ No newline at end of file diff --git a/test/lib_i2s/tdm_slave_tx16_cb_test/i2s_tdm_tx16_slave_test.cmake b/test/lib_i2s/tdm_slave_tx16_cb_test/i2s_tdm_tx16_slave_test.cmake new file mode 100644 index 0000000..bdfb89e --- /dev/null +++ b/test/lib_i2s/tdm_slave_tx16_cb_test/i2s_tdm_tx16_slave_test.cmake @@ -0,0 +1,46 @@ +#********************** +# Gather Sources +#********************** +file(GLOB_RECURSE APP_SOURCES ${CMAKE_CURRENT_LIST_DIR}/src/*.c) +set(APP_INCLUDES ${CMAKE_CURRENT_LIST_DIR}/src) + +#********************** +# Flags +#********************** +set(APP_COMPILER_FLAGS + -Os + -target=XCORE-AI-EXPLORER +) +set(APP_LINK_OPTIONS + -report + -target=XCORE-AI-EXPLORER +) + +#********************** +# Tile Targets +#********************** +if(NOT DEFINED ENV{TX_OFFSET}) + set(TX_OFFSET "0" "1" "2") +else() + set(TX_OFFSET $ENV{TX_OFFSET}) +endif() + +#********************** +# Setup targets +#********************** +foreach(tx_offset ${TX_OFFSET}) + set(TARGET_NAME "test_hil_i2s_tdm_tx16_slave_test_${tx_offset}") + add_executable(${TARGET_NAME} EXCLUDE_FROM_ALL) + target_sources(${TARGET_NAME} PUBLIC ${APP_SOURCES}) + target_include_directories(${TARGET_NAME} PUBLIC ${APP_INCLUDES}) + target_compile_definitions(${TARGET_NAME} + PRIVATE + ${APP_COMPILE_DEFINITIONS} + TX_OFFSET=${tx_offset} + ) + target_compile_options(${TARGET_NAME} PRIVATE ${APP_COMPILER_FLAGS}) + target_link_libraries(${TARGET_NAME} PUBLIC lib_i2s framework_core_utils) + target_link_options(${TARGET_NAME} PRIVATE ${APP_LINK_OPTIONS}) + set_target_properties(${TARGET_NAME} PROPERTIES RUNTIME_OUTPUT_DIRECTORY ${CMAKE_CURRENT_LIST_DIR}/bin) + unset(TARGET_NAME) +endforeach() diff --git a/test/lib_i2s/tdm_slave_tx16_cb_test/src/tdm_slave_tx16_test.c b/test/lib_i2s/tdm_slave_tx16_cb_test/src/tdm_slave_tx16_test.c new file mode 100644 index 0000000..d761298 --- /dev/null +++ b/test/lib_i2s/tdm_slave_tx16_cb_test/src/tdm_slave_tx16_test.c @@ -0,0 +1,86 @@ +// Copyright 2023 XMOS LIMITED. +// This Software is subject to the terms of the XMOS Public Licence: Version 1. +#include +#include +#include +#include +#include +#include + +#include "xcore/port.h" +#include "xcore/parallel.h" + +port_t p_bclk = XS1_PORT_1A; +port_t p_fsync = XS1_PORT_1C; +port_t p_dout = XS1_PORT_1D; + +xclock_t bclk = XS1_CLKBLK_1 + +#ifndef TEST_FRAME_COUNT +#define TEST_FRAME_COUNT 100 +#endif + +DECLARE_JOB(burn, (void)); + +void burn(void) { + for(;;); +} + +I2S_CALLBACK_ATTR +void i2s_send(void *app_data, size_t n, int32_t *send_data) +{ + static int32_t cnt = 0; + + for(size_t i=0; i Date: Fri, 23 Jun 2023 14:03:16 -0400 Subject: [PATCH 04/36] Add broken test --- modules/i2s/api/i2s_tdm_slave.h | 60 ++++++------ modules/i2s/src/i2s_tdm_slave.c | 98 +++++++++++-------- test/lib_i2s/tdm_slave_checker.py | 80 +++++++++++++++ .../i2s_tdm_tx16_slave_test.cmake | 2 +- .../src/tdm_slave_tx16_test.c | 21 ++-- 5 files changed, 177 insertions(+), 84 deletions(-) create mode 100644 test/lib_i2s/tdm_slave_checker.py diff --git a/modules/i2s/api/i2s_tdm_slave.h b/modules/i2s/api/i2s_tdm_slave.h index db21b68..84f8ecb 100644 --- a/modules/i2s/api/i2s_tdm_slave.h +++ b/modules/i2s/api/i2s_tdm_slave.h @@ -37,7 +37,7 @@ * The members in this struct should not be accessed directly. */ typedef struct { - i2s_callback_group_t *const i2s_cbg; + i2s_callback_group_t *i2s_cbg; port_t p_dout[I2S_TDM_MAX_POUT_CNT]; size_t num_out; port_t p_din[I2S_TDM_MAX_PIN_CNT]; @@ -56,8 +56,8 @@ typedef struct { /**@}*/ // END: addtogroup hil_i2s_tdm_core -DECLARE_JOB(i2s_tdm_slave_tx_16, (const i2s_tdm_ctx_t *)); -DECLARE_JOB(i2s_slave_tdm, (const i2s_tdm_ctx_t *)); +DECLARE_JOB(i2s_tdm_slave_tx_16_thread, (i2s_tdm_ctx_t *)); +DECLARE_JOB(i2s_slave_tdm_thread, (i2s_tdm_ctx_t *)); /** * \addtogroup hil_i2s_tdm_slave_tx16 hil_i2s_tdm_slave_tx16 @@ -87,25 +87,27 @@ DECLARE_JOB(i2s_slave_tdm, (const i2s_tdm_ctx_t *)); * the bit clock * \param tx_offset The number of bclks from FSYNC transition to the MSB * of Slot 0 + * \param slave_bclk_pol The polarity of bclk * \param app_data A pointer to application specific data supplied * by the application. May be used for context * data specific to each I2S task instance. */ -void tdm_slave_tx_16_init( - const i2s_tdm_ctx_t *ctx, - const i2s_callback_group_t *const i2s_cbg, - const port_t p_dout, - const port_t p_fsync, - const port_t p_bclk, - const xclock_t bclk, - const uint32_t tx_offset, +void i2s_tdm_slave_tx_16_init( + i2s_tdm_ctx_t *ctx, + i2s_callback_group_t *i2s_cbg, + port_t p_dout, + port_t p_fsync, + port_t p_bclk, + xclock_t bclk, + uint32_t tx_offset, + i2s_slave_bclk_polarity_t slave_bclk_polarity, void *app_data); /** * I2S TDM TX 16 ch slave task * * This task performs I2S TDM slave on the provided context which was - * initialized with tdm_slave_tx_16_init(). It will perform + * initialized with i2s_tdm_slave_tx_16_init(). It will perform * callbacks over the i2s_callback_group_t callback group to get * data from the application using this component. * @@ -118,7 +120,7 @@ void tdm_slave_tx_16_init( * \param ctx A pointer to the I2S TDM context to use. */ void i2s_tdm_slave_tx_16_thread( - const i2s_tdm_ctx_t *ctx); + i2s_tdm_ctx_t *ctx); /**@}*/ // END: addtogroup hil_i2s_tdm_slave_tx16 @@ -163,20 +165,20 @@ void i2s_tdm_slave_tx_16_thread( * data specific to each I2S task instance. */ void i2s_tdm_slave_init( - const i2s_tdm_ctx_t *ctx, - const i2s_callback_group_t *const i2s_cbg, - const port_t p_dout[], - const size_t num_out, - const port_t p_din[], - const size_t num_in, - const port_t p_fsync, - const port_t p_bclk, - const xclock_t bclk, - const uint32_t tx_offset, - const uint32_t fsync_len, - const uint32_t word_len, - const uint32_t ch_len, - const uint32_t ch_per_frame, + i2s_tdm_ctx_t *ctx, + i2s_callback_group_t *i2s_cbg, + port_t p_dout[], + size_t num_out, + port_t p_din[], + size_t num_in, + port_t p_fsync, + port_t p_bclk, + xclock_t bclk, + uint32_t tx_offset, + uint32_t fsync_len, + uint32_t word_len, + uint32_t ch_len, + uint32_t ch_per_frame, i2s_slave_bclk_polarity_t slave_bclk_pol, void *app_data); @@ -193,6 +195,6 @@ void i2s_tdm_slave_init( * \param ctx A pointer to the I2S TDM context to use. */ void i2s_slave_tdm_thread( - const i2s_tdm_ctx_t *ctx); + i2s_tdm_ctx_t *ctx); -/**@}*/ // END: addtogroup hil_i2s_tdm_slave \ No newline at end of file +/**@}*/ // END: addtogroup hil_i2s_tdm_slave diff --git a/modules/i2s/src/i2s_tdm_slave.c b/modules/i2s/src/i2s_tdm_slave.c index b1a713d..49afb75 100644 --- a/modules/i2s/src/i2s_tdm_slave.c +++ b/modules/i2s/src/i2s_tdm_slave.c @@ -1,39 +1,43 @@ // Copyright 2023 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include +#include #include + #include #include #include #include "i2s.h" -#include "i2s_tdm.h" +#include "i2s_tdm_slave.h" void i2s_tdm_slave_init( - const i2s_tdm_ctx_t *ctx, - const i2s_callback_group_t *const i2s_cbg, - const port_t p_dout[], - const size_t num_out, - const port_t p_din[], - const size_t num_in, - const port_t p_fsync, - const port_t p_bclk, - const xclock_t bclk, - const uint32_t tx_offset, - const uint32_t fsync_len, - const uint32_t word_len, - const uint32_t ch_len, - const uint32_t ch_per_frame, + i2s_tdm_ctx_t *ctx, + i2s_callback_group_t *i2s_cbg, + port_t p_dout[], + size_t num_out, + port_t p_din[], + size_t num_in, + port_t p_fsync, + port_t p_bclk, + xclock_t bclk, + uint32_t tx_offset, + uint32_t fsync_len, + uint32_t word_len, + uint32_t ch_len, + uint32_t ch_per_frame, i2s_slave_bclk_polarity_t slave_bclk_pol, - void *app_data); + void *app_data) { - memset(&ctx, 0, sizeof(i2s_tdm_ctx_t)); + memset(ctx, 0, sizeof(i2s_tdm_ctx_t)); ctx->i2s_cbg = i2s_cbg; xassert(num_out <= I2S_TDM_MAX_POUT_CNT); - memcpy(ctx->p_dout, p_dout, sizeof(port_t) * num_out); + memcpy((void*)ctx->p_dout, p_dout, sizeof(port_t) * num_out); xassert(num_in <= I2S_TDM_MAX_PIN_CNT); - memcpy(ctx->p_din, p_din, sizeof(port_t) * num_in); + memcpy((void*)ctx->p_din, p_din, sizeof(port_t) * num_in); + ctx->num_out = num_out; + ctx->num_in = num_in; ctx->p_fsync = p_fsync; ctx->p_bclk = p_bclk; @@ -48,23 +52,23 @@ void i2s_tdm_slave_init( } void i2s_tdm_slave_tx_16_init( - const i2s_tdm_ctx_t *ctx, - const i2s_callback_group_t *const i2s_cbg, - const port_t p_dout, - const port_t p_fsync, - const port_t p_bclk, - const xclock_t bclk, - const uint32_t tx_offset, + i2s_tdm_ctx_t *ctx, + i2s_callback_group_t *i2s_cbg, + port_t p_dout, + port_t p_fsync, + port_t p_bclk, + xclock_t bclk, + uint32_t tx_offset, i2s_slave_bclk_polarity_t slave_bclk_polarity, - void *app_data)) + void *app_data) { - memset(&ctx, 0, sizeof(i2s_tdm_ctx_t)); - port_t pdout = p_dout; + port_t pdout[I2S_TDM_MAX_POUT_CNT]; + pdout[0] = p_dout; i2s_tdm_slave_init( ctx, i2s_cbg, - &pdout, + pdout, 1, NULL, 0, @@ -75,17 +79,17 @@ void i2s_tdm_slave_tx_16_init( 1, /* fsync_len: Does not matter for slave as we only care about edge */ 32, /* word len */ 32, /* ch len */ - 16 /* ch per frame */ + 16, /* ch per frame */ slave_bclk_polarity, app_data); } static void i2s_tdm_slave_init_resources( - const i2s_tdm_ctx_t *ctx) + i2s_tdm_ctx_t *ctx) { port_enable(ctx->p_bclk); clock_enable(ctx->bclk); - clock_set_source_port(ctx->bclk, ctx->p_blck); + clock_set_source_port(ctx->bclk, ctx->p_bclk); for(int i=0; inum_out; i++) { port_start_buffered(ctx->p_dout[i], 32); @@ -102,14 +106,14 @@ static void i2s_tdm_slave_init_resources( port_clear_buffer(ctx->p_fsync); if (ctx->slave_bclk_polarity == I2S_SLAVE_SAMPLE_ON_BCLK_FALLING) { - set_port_inv(ctx->p_bclk); + port_set_invert(ctx->p_bclk); } else { - set_port_no_inv(ctx->p_bclk); + port_set_no_invert(ctx->p_bclk); } } static void i2s_tdm_slave_deinit_resources( - const i2s_tdm_ctx_t *ctx) + i2s_tdm_ctx_t *ctx) { clock_disable(ctx->bclk); port_disable(ctx->p_bclk); @@ -122,23 +126,26 @@ static void i2s_tdm_slave_deinit_resources( } } -void i2s_tdm_slave_tx_16( - const i2s_tdm_ctx_t *ctx) +void i2s_tdm_slave_tx_16_thread( + i2s_tdm_ctx_t *ctx) { uint32_t out_samps[I2S_TDM_MAX_CH_PER_FRAME]; uint32_t fsync_val = 0; +printf("%d\n",__LINE__); while(1) { if (ctx->i2s_cbg->init != NULL) { +printf("%d\n",__LINE__); ctx->i2s_cbg->init((void*)ctx, NULL); } xassert(ctx->num_out == 1); - +printf("%d\n",__LINE__); i2s_tdm_slave_init_resources(ctx); /* Get first frame data */ - ctx->i2s_cbg->send((void*)ctx, ctx->ch_per_frame, out_samps); + ctx->i2s_cbg->send((void*)ctx, ctx->ch_per_frame, (int32_t*)out_samps); +printf("%d\n",__LINE__); uint32_t port_frame_time = (ctx->ch_per_frame * ctx->word_len); /* Wait for first fsync rising edge to occur */ @@ -148,6 +155,7 @@ void i2s_tdm_slave_tx_16( (void) port_in(ctx->p_fsync); port_timestamp_t fsync_edge_time = port_get_trigger_time(ctx->p_fsync); +printf("%d\n",__LINE__); /* Setup trigger times */ uint32_t fsync_trig_time = port_frame_time + ctx->word_len + fsync_edge_time - 1; port_set_trigger_time(ctx->p_fsync, fsync_trig_time); @@ -156,17 +164,18 @@ void i2s_tdm_slave_tx_16( port_out(ctx->p_dout[0], bitrev(out_samps[i])); } +printf("%d\n",__LINE__); while(1) { fsync_val = port_in(ctx->p_fsync); /* We only care about seeing the rising edge */ fsync_val &= 0xc0000000; if (fsync_val != 0x80000000) { - printf("fsync error, expected 0x%x, was %x0x\n", 0x80000000, fsync_val); + printf("fsync error, expected 0x%x, was 0x%x\n", 0x80000000, (unsigned int)fsync_val); break; } /* Get frame data and tx */ - ctx->i2s_cbg->send((void*)ctx, ctx->ch_per_frame, out_samps); + ctx->i2s_cbg->send((void*)ctx, ctx->ch_per_frame, (int32_t*)out_samps); for (int i=0; ich_per_frame; i++) { port_out(ctx->p_dout[0], bitrev(out_samps[i])); @@ -189,8 +198,11 @@ void i2s_tdm_slave_tx_16( } void i2s_slave_tdm_thread( - const i2s_tdm_ctx_t *ctx) + i2s_tdm_ctx_t *ctx) { printf("Not implemented\n"); xassert(0); /* Not yet implemented */ + while(1) { + ; + } } \ No newline at end of file diff --git a/test/lib_i2s/tdm_slave_checker.py b/test/lib_i2s/tdm_slave_checker.py new file mode 100644 index 0000000..1d7bcc9 --- /dev/null +++ b/test/lib_i2s/tdm_slave_checker.py @@ -0,0 +1,80 @@ +# Copyright 2023 XMOS LIMITED. +# This Software is subject to the terms of the XMOS Public Licence: Version 1. +import Pyxsim + +class TDMSlaveTX16Checker(Pyxsim.SimThread): + + def __init__(self, sclk, fsync, dout, tx_offset): + self._sclk = sclk + self._fsync = fsync + self._dout = dout + self._tx_offset = tx_offset + + def run(self): + xsi = self.xsi + print("TDM Slave TX 16 Checker Started") + + while True: + time = xsi.get_time() + + frame_count = 0 + bit_count = 0 + word_count = 0 + bits_per_word = 32 + ch_count = 16 + fsync_len = 1 + + sclk_frequency = 49152000 + + xsi.drive_port_pins(self._sclk, 1) + xsi.drive_port_pins(self._fsync, 0) + + print(f"CONFIG: bclk:{sclk_frequency}") + clock_half_period = float(1000000000000) / float(2 * sclk_frequency) + + # Give app time to start, TODO replace with sync signal + time = time + (clock_half_period * 1000) # arbitary delay + self.wait_until(time) + + blcks_per_frame = bits_per_word * ch_count + + # Start test + while 1: + bits_rx = 0 + bclk_val = 0 + for i in range(0, blcks_per_frame): + + # bclk + xsi.drive_port_pins(self._sclk, 0) + + # fsync + if bits_rx % blcks_per_frame == 0: + xsi.drive_port_pins(self._fsync, 1) + if bits_rx % blcks_per_frame == fsync_len: + xsi.drive_port_pins(self._fsync, 0) + + # half clock update + time = xsi.get_time() + time = time + clock_half_period + self.wait_until(time) + + # bclk + xsi.drive_port_pins(self._sclk, 1) + + # fsync (unchanged) + if bits_rx % blcks_per_frame == 0: + xsi.drive_port_pins(self._fsync, 1) + if bits_rx % blcks_per_frame == fsync_len: + xsi.drive_port_pins(self._fsync, 0) + + # full clock update + time = xsi.get_time() + time = time + clock_half_period + self.wait_until(time) + + # sample + bit_val = xsi.sample_port_pins(self._dout) + print(f"bit[{bits_rx}]:{bit_val}") + + bits_rx += 1 + diff --git a/test/lib_i2s/tdm_slave_tx16_cb_test/i2s_tdm_tx16_slave_test.cmake b/test/lib_i2s/tdm_slave_tx16_cb_test/i2s_tdm_tx16_slave_test.cmake index bdfb89e..a02171a 100644 --- a/test/lib_i2s/tdm_slave_tx16_cb_test/i2s_tdm_tx16_slave_test.cmake +++ b/test/lib_i2s/tdm_slave_tx16_cb_test/i2s_tdm_tx16_slave_test.cmake @@ -39,7 +39,7 @@ foreach(tx_offset ${TX_OFFSET}) TX_OFFSET=${tx_offset} ) target_compile_options(${TARGET_NAME} PRIVATE ${APP_COMPILER_FLAGS}) - target_link_libraries(${TARGET_NAME} PUBLIC lib_i2s framework_core_utils) + target_link_libraries(${TARGET_NAME} PUBLIC lib_i2s) target_link_options(${TARGET_NAME} PRIVATE ${APP_LINK_OPTIONS}) set_target_properties(${TARGET_NAME} PROPERTIES RUNTIME_OUTPUT_DIRECTORY ${CMAKE_CURRENT_LIST_DIR}/bin) unset(TARGET_NAME) diff --git a/test/lib_i2s/tdm_slave_tx16_cb_test/src/tdm_slave_tx16_test.c b/test/lib_i2s/tdm_slave_tx16_cb_test/src/tdm_slave_tx16_test.c index d761298..c9cf374 100644 --- a/test/lib_i2s/tdm_slave_tx16_cb_test/src/tdm_slave_tx16_test.c +++ b/test/lib_i2s/tdm_slave_tx16_cb_test/src/tdm_slave_tx16_test.c @@ -1,20 +1,21 @@ // Copyright 2023 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include -#include -#include #include #include -#include #include "xcore/port.h" +#include "xcore/clock.h" #include "xcore/parallel.h" +#include "i2s.h" +#include "i2s_tdm_slave.h" + port_t p_bclk = XS1_PORT_1A; port_t p_fsync = XS1_PORT_1C; port_t p_dout = XS1_PORT_1D; -xclock_t bclk = XS1_CLKBLK_1 +xclock_t bclk = XS1_CLKBLK_1; #ifndef TEST_FRAME_COUNT #define TEST_FRAME_COUNT 100 @@ -57,12 +58,8 @@ int main(void) .send = (i2s_send_t) i2s_send, .app_data = NULL, }; - - port_enable(setup_strobe_port); - port_enable(setup_data_port); - port_enable(setup_resp_port); - - tdm_slave_tx_16_init( +printf("start\n"); + i2s_tdm_slave_tx_16_init( &ctx, &i_i2s, p_dout, @@ -70,10 +67,12 @@ int main(void) p_bclk, bclk, TX_OFFSET, + I2S_SLAVE_SAMPLE_ON_BCLK_RISING, NULL); +printf("init done\n"); PAR_JOBS( - PJOB((i2s_tdm_slave_tx_16_thread), (&ctx)), + PJOB(i2s_tdm_slave_tx_16_thread, (&ctx)), PJOB(burn, ()), PJOB(burn, ()), PJOB(burn, ()), From 9cc56001b70098c4b7c35c2aadafb24dea218933 Mon Sep 17 00:00:00 2001 From: Jeremiah McCarthy Date: Wed, 28 Jun 2023 17:15:11 -0400 Subject: [PATCH 05/36] Add tests, nonfunctional fsync --- modules/i2s/src/i2s_tdm_slave.c | 43 +++++---- .../expected/tdm_slave_tx16_cb_test.expect | 3 +- test/lib_i2s/tdm_slave_checker.py | 96 ++++++++++++++++--- .../src/tdm_slave_tx16_test.c | 78 +++++++++++++-- test/lib_i2s/test_tdm_slave_tx16_cb.py | 70 +++++++++----- 5 files changed, 226 insertions(+), 64 deletions(-) diff --git a/modules/i2s/src/i2s_tdm_slave.c b/modules/i2s/src/i2s_tdm_slave.c index 49afb75..5dff26e 100644 --- a/modules/i2s/src/i2s_tdm_slave.c +++ b/modules/i2s/src/i2s_tdm_slave.c @@ -90,6 +90,7 @@ static void i2s_tdm_slave_init_resources( port_enable(ctx->p_bclk); clock_enable(ctx->bclk); clock_set_source_port(ctx->bclk, ctx->p_bclk); + clock_set_divide(ctx->bclk, 0); for(int i=0; inum_out; i++) { port_start_buffered(ctx->p_dout[i], 32); @@ -101,7 +102,7 @@ static void i2s_tdm_slave_init_resources( port_set_clock(ctx->p_din[i], ctx->bclk); port_clear_buffer(ctx->p_din[i]); } - port_start_buffered(ctx->p_fsync, 32); + port_enable(ctx->p_fsync); port_set_clock(ctx->p_fsync, ctx->bclk); port_clear_buffer(ctx->p_fsync); @@ -110,6 +111,7 @@ static void i2s_tdm_slave_init_resources( } else { port_set_no_invert(ctx->p_bclk); } + clock_start(ctx->bclk); } static void i2s_tdm_slave_deinit_resources( @@ -132,20 +134,16 @@ void i2s_tdm_slave_tx_16_thread( uint32_t out_samps[I2S_TDM_MAX_CH_PER_FRAME]; uint32_t fsync_val = 0; -printf("%d\n",__LINE__); while(1) { if (ctx->i2s_cbg->init != NULL) { -printf("%d\n",__LINE__); ctx->i2s_cbg->init((void*)ctx, NULL); } xassert(ctx->num_out == 1); -printf("%d\n",__LINE__); i2s_tdm_slave_init_resources(ctx); /* Get first frame data */ ctx->i2s_cbg->send((void*)ctx, ctx->ch_per_frame, (int32_t*)out_samps); -printf("%d\n",__LINE__); uint32_t port_frame_time = (ctx->ch_per_frame * ctx->word_len); /* Wait for first fsync rising edge to occur */ @@ -154,31 +152,44 @@ printf("%d\n",__LINE__); port_set_trigger_in_equal(ctx->p_fsync, 1); (void) port_in(ctx->p_fsync); port_timestamp_t fsync_edge_time = port_get_trigger_time(ctx->p_fsync); + port_start_buffered(ctx->p_fsync, 32); -printf("%d\n",__LINE__); /* Setup trigger times */ - uint32_t fsync_trig_time = port_frame_time + ctx->word_len + fsync_edge_time - 1; + uint32_t fsync_trig_time = port_frame_time + fsync_edge_time - ctx->word_len - 2; port_set_trigger_time(ctx->p_fsync, fsync_trig_time); port_set_trigger_time(ctx->p_dout[0], port_frame_time + fsync_edge_time + ctx->tx_offset); + + // (void) port_in(ctx->p_fsync); for (int i=0; ich_per_frame; i++) { port_out(ctx->p_dout[0], bitrev(out_samps[i])); + // (void) port_in(ctx->p_fsync); } -printf("%d\n",__LINE__); while(1) { - fsync_val = port_in(ctx->p_fsync); /* We only care about seeing the rising edge */ - fsync_val &= 0xc0000000; - if (fsync_val != 0x80000000) { - printf("fsync error, expected 0x%x, was 0x%x\n", 0x80000000, (unsigned int)fsync_val); - break; - } + // fsync_val &= 0x8000000; + // if (fsync_val != 0x8000000) { + // printf("fsync error, expected 0x%x, was 0x%x\n", 0x00000001, (unsigned int)fsync_val); + // break; + // } /* Get frame data and tx */ ctx->i2s_cbg->send((void*)ctx, ctx->ch_per_frame, (int32_t*)out_samps); - + for (int i=0; ich_per_frame; i++) { port_out(ctx->p_dout[0], bitrev(out_samps[i])); + // fsync_val = port_in(ctx->p_fsync); + + // if (i == 1) { + // fsync_val &= 0x00000003; + // if (fsync_val != 0x00000002) { + // printf("fsync error, expected 0x%x, was 0x%x\n", 0x00000001, (unsigned int)fsync_val); + // break; + // } + // } + + + // printf("fsync_val[%d] 0x%x\n", i, fsync_val); } /* Check for exit condition */ @@ -205,4 +216,4 @@ void i2s_slave_tdm_thread( while(1) { ; } -} \ No newline at end of file +} diff --git a/test/lib_i2s/expected/tdm_slave_tx16_cb_test.expect b/test/lib_i2s/expected/tdm_slave_tx16_cb_test.expect index 1ab1e70..567e14b 100644 --- a/test/lib_i2s/expected/tdm_slave_tx16_cb_test.expect +++ b/test/lib_i2s/expected/tdm_slave_tx16_cb_test.expect @@ -1 +1,2 @@ -TDM Slave 16 Checker Started \ No newline at end of file +TDM Slave TX 16 Checker Started +Got Settings:tx_offset \d+ diff --git a/test/lib_i2s/tdm_slave_checker.py b/test/lib_i2s/tdm_slave_checker.py index 1d7bcc9..270b131 100644 --- a/test/lib_i2s/tdm_slave_checker.py +++ b/test/lib_i2s/tdm_slave_checker.py @@ -4,19 +4,37 @@ class TDMSlaveTX16Checker(Pyxsim.SimThread): - def __init__(self, sclk, fsync, dout, tx_offset): + def __init__( + self, + sclk, + fsync, + dout, + tx_offset, + setup_strobe_port, + setup_data_port, + setup_resp_port + ): self._sclk = sclk self._fsync = fsync self._dout = dout self._tx_offset = tx_offset + self._setup_strobe_port = setup_strobe_port + self._setup_data_port = setup_data_port + self._setup_resp_port = setup_resp_port + + def get_setup_data(self, + xsi: Pyxsim.pyxsim.Xsi, + setup_strobe_port: str, + setup_data_port: str) -> int: + self.wait_for_port_pins_change([setup_strobe_port]) + self.wait_for_port_pins_change([setup_strobe_port]) + return xsi.sample_port_pins(setup_data_port) def run(self): xsi = self.xsi print("TDM Slave TX 16 Checker Started") - while True: - time = xsi.get_time() - + while True: frame_count = 0 bit_count = 0 word_count = 0 @@ -25,23 +43,35 @@ def run(self): fsync_len = 1 sclk_frequency = 49152000 - - xsi.drive_port_pins(self._sclk, 1) - xsi.drive_port_pins(self._fsync, 0) + blcks_per_frame = bits_per_word * ch_count print(f"CONFIG: bclk:{sclk_frequency}") - clock_half_period = float(1000000000000) / float(2 * sclk_frequency) + clock_half_period = float(1000000000000) / float(2 * (sclk_frequency/1000)) ## Want freq in khz + clock_quarter_period = clock_half_period / 2 - # Give app time to start, TODO replace with sync signal - time = time + (clock_half_period * 1000) # arbitary delay - self.wait_until(time) + #first do the setup rx + strobe_val = xsi.sample_port_pins(self._setup_strobe_port) + if strobe_val == 1: + xsi.drive_port_pins(self._sclk, 1) + xsi.drive_port_pins(self._fsync, 0) + self.wait_for_port_pins_change([self._setup_strobe_port]) - blcks_per_frame = bits_per_word * ch_count + tx_offset = self.get_setup_data(xsi, self._setup_strobe_port, self._setup_data_port) + + print(f"Got Settings:tx_offset {tx_offset}") + + # drive initial values while slave starts up for the first time + xsi.drive_port_pins(self._sclk, 1) + xsi.drive_port_pins(self._fsync, 0) + self.wait_until(xsi.get_time() + 10000000) + frame_cnt = 0 # Start test while 1: bits_rx = 0 bclk_val = 0 + + # print(f"frame:{frame_cnt}") for i in range(0, blcks_per_frame): # bclk @@ -69,12 +99,48 @@ def run(self): # full clock update time = xsi.get_time() - time = time + clock_half_period + time = time + clock_quarter_period self.wait_until(time) # sample bit_val = xsi.sample_port_pins(self._dout) - print(f"bit[{bits_rx}]:{bit_val}") - + + if frame_cnt >= 2: + if tx_offset == 0: + frame_arg = frame_cnt-1 + bit_arg = bits_rx + else: + frame_arg = (frame_cnt-1) if bits_rx <= tx_offset else (frame_cnt-2) + bit_arg = bits_rx + tx_offset if bits_rx >= tx_offset else blcks_per_frame - (tx_offset - bits_rx) + + expect_rx = self.calc_expected_bit(frame_arg, bit_arg) + + if bit_val != expect_rx: + print(f"bit[{bits_rx}]:{bit_val}:{expect_rx}") + bits_rx += 1 + time = xsi.get_time() + time = time + clock_quarter_period + self.wait_until(time) + + frame_cnt += 1 + + def calc_expected_bit(self, frame, bit): + # Each sample in the tdm_slave_tx16_test output is in the format + # bin AAAABBBB BBBBBBBB BBBBBBBB BBBBBBBB + # Where: + # AAAA is the channel id, [0,15] + # BBBB BBBBBBBB BBBBBBBB BBBBBBBB is frame num starting at 1 + # Additionally, the output data is bitrev, so that it shows up + # in a more easily recognizable format on the wire in vcd traces + ret = 0 + + ch = bit // 32 + ch_index = bit % 32 + + if ch_index >= 28: + ret = (ch >> (ch_index - 28)) & 0b1 + else: + ret = (frame >> ch_index) & 0b1 + return ret diff --git a/test/lib_i2s/tdm_slave_tx16_cb_test/src/tdm_slave_tx16_test.c b/test/lib_i2s/tdm_slave_tx16_cb_test/src/tdm_slave_tx16_test.c index c9cf374..ae0e502 100644 --- a/test/lib_i2s/tdm_slave_tx16_cb_test/src/tdm_slave_tx16_test.c +++ b/test/lib_i2s/tdm_slave_tx16_cb_test/src/tdm_slave_tx16_test.c @@ -1,6 +1,7 @@ // Copyright 2023 XMOS LIMITED. // This Software is subject to the terms of the XMOS Public Licence: Version 1. #include +#include #include #include @@ -17,9 +18,19 @@ port_t p_dout = XS1_PORT_1D; xclock_t bclk = XS1_CLKBLK_1; +port_t setup_strobe_port = XS1_PORT_1E; +port_t setup_data_port = XS1_PORT_16B; +port_t setup_resp_port = XS1_PORT_1F; + #ifndef TEST_FRAME_COUNT #define TEST_FRAME_COUNT 100 #endif +#ifndef TEST_NUM_CH +#define TEST_NUM_CH 16 +#endif + +int32_t test_data[TEST_FRAME_COUNT][TEST_NUM_CH] = {0}; + DECLARE_JOB(burn, (void)); @@ -27,19 +38,67 @@ void burn(void) { for(;;); } +static void send_data_to_tester( + port_t setup_strobe_port, + port_t setup_data_port, + unsigned data){ + port_out(setup_data_port, data); + asm volatile("syncr res[%0]" : : "r" (setup_data_port)); + port_out(setup_strobe_port, 1); + port_out(setup_strobe_port, 0); + asm volatile("syncr res[%0]" : : "r" (setup_data_port)); +} + +static void broadcast_settings( + port_t setup_strobe_port, + port_t setup_data_port) +{ + port_out(setup_strobe_port, 0); + + send_data_to_tester(setup_strobe_port, setup_data_port, TX_OFFSET); +} + +static uint32_t request_response( + port_t setup_strobe_port, + port_t setup_resp_port) +{ + port_enable(setup_resp_port); + port_out(setup_strobe_port, 1); + port_out(setup_strobe_port, 0); + uint32_t tmp = port_in(setup_resp_port); + return tmp; +} + + +I2S_CALLBACK_ATTR +void i2s_init(void *app_data, i2s_config_t *i2s_config) +{ + (void) app_data; + (void) i2s_config; + + /* Initialize test data */ + for (int i=1; i<=TEST_FRAME_COUNT; i++) { + for (int j=0; j Date: Wed, 28 Jun 2023 18:16:09 -0400 Subject: [PATCH 06/36] Add tested tdm 16 --- modules/i2s/src/i2s_tdm_slave.c | 46 +++--- test/build_lib_i2s_tests.sh | 147 +++++++++--------- test/lib_i2s/tdm_slave_checker.py | 24 ++- .../src/tdm_slave_tx16_test.c | 1 + test/lib_i2s/test_tdm_slave_tx16_cb.py | 11 +- 5 files changed, 116 insertions(+), 113 deletions(-) diff --git a/modules/i2s/src/i2s_tdm_slave.c b/modules/i2s/src/i2s_tdm_slave.c index 5dff26e..f9c7117 100644 --- a/modules/i2s/src/i2s_tdm_slave.c +++ b/modules/i2s/src/i2s_tdm_slave.c @@ -152,44 +152,37 @@ void i2s_tdm_slave_tx_16_thread( port_set_trigger_in_equal(ctx->p_fsync, 1); (void) port_in(ctx->p_fsync); port_timestamp_t fsync_edge_time = port_get_trigger_time(ctx->p_fsync); - port_start_buffered(ctx->p_fsync, 32); - + /* Setup trigger times */ - uint32_t fsync_trig_time = port_frame_time + fsync_edge_time - ctx->word_len - 2; - port_set_trigger_time(ctx->p_fsync, fsync_trig_time); + port_set_trigger_time(ctx->p_fsync, port_frame_time + fsync_edge_time); port_set_trigger_time(ctx->p_dout[0], port_frame_time + fsync_edge_time + ctx->tx_offset); - // (void) port_in(ctx->p_fsync); - for (int i=0; ich_per_frame; i++) { + port_out(ctx->p_dout[0], bitrev(out_samps[0])); + fsync_val = port_in(ctx->p_fsync); + fsync_edge_time = port_get_trigger_time(ctx->p_fsync); + port_set_trigger_time(ctx->p_fsync, port_frame_time + fsync_edge_time); + + for (int i=1; ich_per_frame; i++) { port_out(ctx->p_dout[0], bitrev(out_samps[i])); - // (void) port_in(ctx->p_fsync); } while(1) { - /* We only care about seeing the rising edge */ - // fsync_val &= 0x8000000; - // if (fsync_val != 0x8000000) { - // printf("fsync error, expected 0x%x, was 0x%x\n", 0x00000001, (unsigned int)fsync_val); - // break; - // } - /* Get frame data and tx */ ctx->i2s_cbg->send((void*)ctx, ctx->ch_per_frame, (int32_t*)out_samps); - for (int i=0; ich_per_frame; i++) { - port_out(ctx->p_dout[0], bitrev(out_samps[i])); - // fsync_val = port_in(ctx->p_fsync); - - // if (i == 1) { - // fsync_val &= 0x00000003; - // if (fsync_val != 0x00000002) { - // printf("fsync error, expected 0x%x, was 0x%x\n", 0x00000001, (unsigned int)fsync_val); - // break; - // } - // } + port_out(ctx->p_dout[0], bitrev(out_samps[0])); + fsync_val = port_in(ctx->p_fsync); + fsync_edge_time = port_get_trigger_time(ctx->p_fsync); + port_set_trigger_time(ctx->p_fsync, port_frame_time + fsync_edge_time); + /* Note: Still possible for us to alias, but this will catch nonperiod drifting */ + if (fsync_val != 1) { + // printf("fsync_error\n"); + break; + } - // printf("fsync_val[%d] 0x%x\n", i, fsync_val); + for (int i=1; ich_per_frame; i++) { + port_out(ctx->p_dout[0], bitrev(out_samps[i])); } /* Check for exit condition */ @@ -211,7 +204,6 @@ void i2s_tdm_slave_tx_16_thread( void i2s_slave_tdm_thread( i2s_tdm_ctx_t *ctx) { - printf("Not implemented\n"); xassert(0); /* Not yet implemented */ while(1) { ; diff --git a/test/build_lib_i2s_tests.sh b/test/build_lib_i2s_tests.sh index 1e8bc39..f02edc4 100755 --- a/test/build_lib_i2s_tests.sh +++ b/test/build_lib_i2s_tests.sh @@ -7,78 +7,81 @@ source ${FRAMEWORK_IO_ROOT}/tools/ci/helper_functions.sh # row format is: "make_target BOARD toolchain" applications=( - "test_hil_backpressure_test_768000_4_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_backpressure_test_768000_4_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_backpressure_test_768000_4_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_backpressure_test_768000_3_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_backpressure_test_768000_3_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_backpressure_test_768000_3_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_backpressure_test_768000_2_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_backpressure_test_768000_2_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_backpressure_test_768000_2_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_backpressure_test_768000_1_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_backpressure_test_768000_1_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_backpressure_test_768000_1_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_backpressure_test_384000_4_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_backpressure_test_384000_4_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_backpressure_test_384000_4_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_backpressure_test_384000_3_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_backpressure_test_384000_3_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_backpressure_test_384000_3_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_backpressure_test_384000_2_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_backpressure_test_384000_2_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_backpressure_test_384000_2_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_backpressure_test_384000_1_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_backpressure_test_384000_1_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_backpressure_test_384000_1_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_backpressure_test_192000_4_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_backpressure_test_192000_4_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_backpressure_test_192000_4_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_backpressure_test_192000_3_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_backpressure_test_192000_3_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_backpressure_test_192000_3_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_backpressure_test_192000_2_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_backpressure_test_192000_2_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_backpressure_test_192000_2_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_backpressure_test_192000_1_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_backpressure_test_192000_1_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_backpressure_test_192000_1_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_i2s_master_external_clock_test_0_4_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_i2s_master_external_clock_test_0_1_1 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_i2s_master_external_clock_test_0_4_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_i2s_master_external_clock_test_0_0_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_i2s_master_external_clock_test_1_4_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_i2s_master_external_clock_test_1_1_1 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_i2s_master_external_clock_test_1_4_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_i2s_master_external_clock_test_1_0_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_i2s_master_test_0_4_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_i2s_master_test_0_1_1 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_i2s_master_test_0_4_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_i2s_master_test_0_0_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_i2s_master_test_1_4_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_i2s_master_test_1_1_1 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_i2s_master_test_1_4_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_i2s_master_test_1_0_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_i2s_slave_test_0_4_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_i2s_slave_test_0_1_1 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_i2s_slave_test_0_4_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_i2s_slave_test_0_0_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_i2s_slave_test_0_2_2 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_i2s_slave_test_1_4_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_i2s_slave_test_1_1_1 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_i2s_slave_test_1_4_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_i2s_slave_test_1_0_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_i2s_slave_test_1_2_2 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_i2s_slave_test_0_4_4_inv XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_i2s_slave_test_0_1_1_inv XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_i2s_slave_test_0_4_0_inv XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_i2s_slave_test_0_0_4_inv XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_i2s_slave_test_0_2_2_inv XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_i2s_slave_test_1_4_4_inv XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_i2s_slave_test_1_1_1_inv XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_i2s_slave_test_1_4_0_inv XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_i2s_slave_test_1_0_4_inv XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - "test_hil_i2s_slave_test_1_2_2_inv XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_backpressure_test_768000_4_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_backpressure_test_768000_4_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_backpressure_test_768000_4_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_backpressure_test_768000_3_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_backpressure_test_768000_3_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_backpressure_test_768000_3_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_backpressure_test_768000_2_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_backpressure_test_768000_2_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_backpressure_test_768000_2_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_backpressure_test_768000_1_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_backpressure_test_768000_1_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_backpressure_test_768000_1_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_backpressure_test_384000_4_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_backpressure_test_384000_4_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_backpressure_test_384000_4_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_backpressure_test_384000_3_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_backpressure_test_384000_3_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_backpressure_test_384000_3_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_backpressure_test_384000_2_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_backpressure_test_384000_2_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_backpressure_test_384000_2_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_backpressure_test_384000_1_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_backpressure_test_384000_1_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_backpressure_test_384000_1_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_backpressure_test_192000_4_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_backpressure_test_192000_4_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_backpressure_test_192000_4_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_backpressure_test_192000_3_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_backpressure_test_192000_3_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_backpressure_test_192000_3_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_backpressure_test_192000_2_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_backpressure_test_192000_2_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_backpressure_test_192000_2_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_backpressure_test_192000_1_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_backpressure_test_192000_1_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_backpressure_test_192000_1_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_i2s_master_external_clock_test_0_4_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_i2s_master_external_clock_test_0_1_1 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_i2s_master_external_clock_test_0_4_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_i2s_master_external_clock_test_0_0_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_i2s_master_external_clock_test_1_4_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_i2s_master_external_clock_test_1_1_1 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_i2s_master_external_clock_test_1_4_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_i2s_master_external_clock_test_1_0_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_i2s_master_test_0_4_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_i2s_master_test_0_1_1 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_i2s_master_test_0_4_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_i2s_master_test_0_0_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_i2s_master_test_1_4_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_i2s_master_test_1_1_1 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_i2s_master_test_1_4_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_i2s_master_test_1_0_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_i2s_slave_test_0_4_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_i2s_slave_test_0_1_1 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_i2s_slave_test_0_4_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_i2s_slave_test_0_0_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_i2s_slave_test_0_2_2 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_i2s_slave_test_1_4_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_i2s_slave_test_1_1_1 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_i2s_slave_test_1_4_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_i2s_slave_test_1_0_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_i2s_slave_test_1_2_2 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_i2s_slave_test_0_4_4_inv XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_i2s_slave_test_0_1_1_inv XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_i2s_slave_test_0_4_0_inv XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_i2s_slave_test_0_0_4_inv XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_i2s_slave_test_0_2_2_inv XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_i2s_slave_test_1_4_4_inv XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_i2s_slave_test_1_1_1_inv XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_i2s_slave_test_1_4_0_inv XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_i2s_slave_test_1_0_4_inv XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + # "test_hil_i2s_slave_test_1_2_2_inv XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_i2s_tdm_tx16_slave_test_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_i2s_tdm_tx16_slave_test_1 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_i2s_tdm_tx16_slave_test_2 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" ) # perform builds diff --git a/test/lib_i2s/tdm_slave_checker.py b/test/lib_i2s/tdm_slave_checker.py index 270b131..d376b93 100644 --- a/test/lib_i2s/tdm_slave_checker.py +++ b/test/lib_i2s/tdm_slave_checker.py @@ -9,7 +9,6 @@ def __init__( sclk, fsync, dout, - tx_offset, setup_strobe_port, setup_data_port, setup_resp_port @@ -17,7 +16,6 @@ def __init__( self._sclk = sclk self._fsync = fsync self._dout = dout - self._tx_offset = tx_offset self._setup_strobe_port = setup_strobe_port self._setup_data_port = setup_data_port self._setup_resp_port = setup_resp_port @@ -105,18 +103,30 @@ def run(self): # sample bit_val = xsi.sample_port_pins(self._dout) - if frame_cnt >= 2: + if frame_cnt >= 2: # Ignore init frame as data is 0's while slave syncs up + frame_arg = 0 + bit_arg = 0 if tx_offset == 0: frame_arg = frame_cnt-1 bit_arg = bits_rx else: - frame_arg = (frame_cnt-1) if bits_rx <= tx_offset else (frame_cnt-2) - bit_arg = bits_rx + tx_offset if bits_rx >= tx_offset else blcks_per_frame - (tx_offset - bits_rx) + if bits_rx < tx_offset: + frame_arg = (frame_cnt-2) + else: + frame_arg = (frame_cnt-1) + + if frame_arg == (frame_cnt-1): + bit_arg = bits_rx - tx_offset + else: + bit_arg = (blcks_per_frame - 1) + (bits_rx - tx_offset) expect_rx = self.calc_expected_bit(frame_arg, bit_arg) + # print(f"asked for {frame_arg}:{bit_arg} check bit[{bits_rx}]:{bit_val}:{expect_rx}") - if bit_val != expect_rx: - print(f"bit[{bits_rx}]:{bit_val}:{expect_rx}") + # For the first frame, if tx_offset > 0, the first tx_offset bits are don't cares + if frame_cnt == 2 and bits_rx > tx_offset: + if bit_val != expect_rx: + print(f"bit[{bits_rx}]:{bit_val}:{expect_rx}") bits_rx += 1 time = xsi.get_time() diff --git a/test/lib_i2s/tdm_slave_tx16_cb_test/src/tdm_slave_tx16_test.c b/test/lib_i2s/tdm_slave_tx16_cb_test/src/tdm_slave_tx16_test.c index ae0e502..70ba118 100644 --- a/test/lib_i2s/tdm_slave_tx16_cb_test/src/tdm_slave_tx16_test.c +++ b/test/lib_i2s/tdm_slave_tx16_cb_test/src/tdm_slave_tx16_test.c @@ -140,6 +140,7 @@ int main(void) PJOB(burn, ()), PJOB(burn, ()), PJOB(burn, ()), + PJOB(burn, ()), PJOB(burn, ()) ); diff --git a/test/lib_i2s/test_tdm_slave_tx16_cb.py b/test/lib_i2s/test_tdm_slave_tx16_cb.py index 42c206a..64d3fc1 100644 --- a/test/lib_i2s/test_tdm_slave_tx16_cb.py +++ b/test/lib_i2s/test_tdm_slave_tx16_cb.py @@ -8,11 +8,9 @@ DEBUG = True # DEBUG = False -tx_offset_args = {"0": (0)} -# tx_offset_args = {"1": (1)} -# tx_offset_args = {"0": (0), -# "1": (1), -# "2": (2)} +tx_offset_args = {"0": (0), + "1": (1), + "2": (2)} @pytest.mark.parametrize(("tx_offset"), tx_offset_args.values(), ids=tx_offset_args.keys()) def test_tdm_slavetx16_cb(capfd, request, nightly, tx_offset): @@ -25,7 +23,6 @@ def test_tdm_slavetx16_cb(capfd, request, nightly, tx_offset): "tile[0]:XS1_PORT_1A", "tile[0]:XS1_PORT_1C", "tile[0]:XS1_PORT_1D", - tx_offset, "tile[0]:XS1_PORT_1E", "tile[0]:XS1_PORT_16B", "tile[0]:XS1_PORT_1F") @@ -44,7 +41,7 @@ def test_tdm_slavetx16_cb(capfd, request, nightly, tx_offset): simthreads = [checker], simargs = [], vcdTracing = True, - timeout = 50) + timeout = 100) tester.run(capfd.readouterr().out) else: From c1ee551b2ff6b3c21c841dda8dd8bd4729c64948 Mon Sep 17 00:00:00 2001 From: Jeremiah McCarthy Date: Thu, 29 Jun 2023 08:36:10 -0400 Subject: [PATCH 07/36] Fix CI running --- .github/workflows/ci.yml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index dbe7664..a9c3906 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -83,7 +83,7 @@ jobs: - name: Run tests run: | - docker run --rm -u $(id -u):$(id -g) -w /fwk_io/test -v ${{github.workspace}}:/fwk_io ${FWK_IO_TESTER_IMAGE} bash -l run_tests.sh lib_i2c + docker run --rm -w /fwk_io/test -v ${{github.workspace}}:/fwk_io ${FWK_IO_TESTER_IMAGE} bash -l run_tests.sh lib_i2c i2stests: name: I2S tests @@ -102,7 +102,7 @@ jobs: - name: Run tests run: | - docker run --rm -u $(id -u):$(id -g) -w /fwk_io/test -v ${{github.workspace}}:/fwk_io ${FWK_IO_TESTER_IMAGE} bash -l run_tests.sh lib_i2s + docker run --rm -w /fwk_io/test -v ${{github.workspace}}:/fwk_io ${FWK_IO_TESTER_IMAGE} bash -l run_tests.sh lib_i2s spitests: name: SPI tests @@ -121,7 +121,7 @@ jobs: - name: Run tests run: | - docker run --rm -u $(id -u):$(id -g) -w /fwk_io/test -v ${{github.workspace}}:/fwk_io ${FWK_IO_TESTER_IMAGE} bash -l run_tests.sh lib_spi + docker run --rm -w /fwk_io/test -v ${{github.workspace}}:/fwk_io ${FWK_IO_TESTER_IMAGE} bash -l run_tests.sh lib_spi uarttests: @@ -141,4 +141,4 @@ jobs: - name: Run tests run: | - docker run --rm -u $(id -u):$(id -g) -w /fwk_io/test -v ${{github.workspace}}:/fwk_io ${FWK_IO_TESTER_IMAGE} bash -l run_tests.sh lib_uart + docker run --rm -w /fwk_io/test -v ${{github.workspace}}:/fwk_io ${FWK_IO_TESTER_IMAGE} bash -l run_tests.sh lib_uart From 21be68f3d5dda2989943b334c4ce64bc308e6c7a Mon Sep 17 00:00:00 2001 From: Jeremiah McCarthy Date: Thu, 29 Jun 2023 09:12:59 -0400 Subject: [PATCH 08/36] Update tdm test expect --- test/lib_i2s/expected/tdm_slave_tx16_cb_test.expect | 1 + 1 file changed, 1 insertion(+) diff --git a/test/lib_i2s/expected/tdm_slave_tx16_cb_test.expect b/test/lib_i2s/expected/tdm_slave_tx16_cb_test.expect index 567e14b..83b9957 100644 --- a/test/lib_i2s/expected/tdm_slave_tx16_cb_test.expect +++ b/test/lib_i2s/expected/tdm_slave_tx16_cb_test.expect @@ -1,2 +1,3 @@ TDM Slave TX 16 Checker Started +CONFIG: bclk:\d+ Got Settings:tx_offset \d+ From 693f8af3279a670afcd1b5f350abdc54800d222e Mon Sep 17 00:00:00 2001 From: Jeremiah McCarthy Date: Thu, 29 Jun 2023 09:14:54 -0400 Subject: [PATCH 09/36] Re-add lib_i2s tests --- test/build_lib_i2s_tests.sh | 144 ++++++++++++------------- test/lib_i2s/test_tdm_slave_tx16_cb.py | 10 +- 2 files changed, 76 insertions(+), 78 deletions(-) diff --git a/test/build_lib_i2s_tests.sh b/test/build_lib_i2s_tests.sh index f02edc4..7443962 100755 --- a/test/build_lib_i2s_tests.sh +++ b/test/build_lib_i2s_tests.sh @@ -7,78 +7,78 @@ source ${FRAMEWORK_IO_ROOT}/tools/ci/helper_functions.sh # row format is: "make_target BOARD toolchain" applications=( - # "test_hil_backpressure_test_768000_4_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_backpressure_test_768000_4_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_backpressure_test_768000_4_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_backpressure_test_768000_3_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_backpressure_test_768000_3_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_backpressure_test_768000_3_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_backpressure_test_768000_2_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_backpressure_test_768000_2_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_backpressure_test_768000_2_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_backpressure_test_768000_1_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_backpressure_test_768000_1_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_backpressure_test_768000_1_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_backpressure_test_384000_4_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_backpressure_test_384000_4_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_backpressure_test_384000_4_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_backpressure_test_384000_3_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_backpressure_test_384000_3_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_backpressure_test_384000_3_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_backpressure_test_384000_2_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_backpressure_test_384000_2_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_backpressure_test_384000_2_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_backpressure_test_384000_1_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_backpressure_test_384000_1_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_backpressure_test_384000_1_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_backpressure_test_192000_4_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_backpressure_test_192000_4_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_backpressure_test_192000_4_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_backpressure_test_192000_3_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_backpressure_test_192000_3_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_backpressure_test_192000_3_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_backpressure_test_192000_2_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_backpressure_test_192000_2_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_backpressure_test_192000_2_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_backpressure_test_192000_1_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_backpressure_test_192000_1_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_backpressure_test_192000_1_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_i2s_master_external_clock_test_0_4_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_i2s_master_external_clock_test_0_1_1 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_i2s_master_external_clock_test_0_4_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_i2s_master_external_clock_test_0_0_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_i2s_master_external_clock_test_1_4_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_i2s_master_external_clock_test_1_1_1 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_i2s_master_external_clock_test_1_4_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_i2s_master_external_clock_test_1_0_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_i2s_master_test_0_4_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_i2s_master_test_0_1_1 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_i2s_master_test_0_4_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_i2s_master_test_0_0_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_i2s_master_test_1_4_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_i2s_master_test_1_1_1 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_i2s_master_test_1_4_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_i2s_master_test_1_0_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_i2s_slave_test_0_4_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_i2s_slave_test_0_1_1 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_i2s_slave_test_0_4_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_i2s_slave_test_0_0_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_i2s_slave_test_0_2_2 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_i2s_slave_test_1_4_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_i2s_slave_test_1_1_1 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_i2s_slave_test_1_4_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_i2s_slave_test_1_0_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_i2s_slave_test_1_2_2 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_i2s_slave_test_0_4_4_inv XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_i2s_slave_test_0_1_1_inv XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_i2s_slave_test_0_4_0_inv XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_i2s_slave_test_0_0_4_inv XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_i2s_slave_test_0_2_2_inv XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_i2s_slave_test_1_4_4_inv XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_i2s_slave_test_1_1_1_inv XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_i2s_slave_test_1_4_0_inv XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_i2s_slave_test_1_0_4_inv XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" - # "test_hil_i2s_slave_test_1_2_2_inv XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_backpressure_test_768000_4_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_backpressure_test_768000_4_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_backpressure_test_768000_4_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_backpressure_test_768000_3_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_backpressure_test_768000_3_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_backpressure_test_768000_3_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_backpressure_test_768000_2_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_backpressure_test_768000_2_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_backpressure_test_768000_2_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_backpressure_test_768000_1_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_backpressure_test_768000_1_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_backpressure_test_768000_1_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_backpressure_test_384000_4_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_backpressure_test_384000_4_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_backpressure_test_384000_4_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_backpressure_test_384000_3_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_backpressure_test_384000_3_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_backpressure_test_384000_3_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_backpressure_test_384000_2_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_backpressure_test_384000_2_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_backpressure_test_384000_2_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_backpressure_test_384000_1_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_backpressure_test_384000_1_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_backpressure_test_384000_1_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_backpressure_test_192000_4_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_backpressure_test_192000_4_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_backpressure_test_192000_4_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_backpressure_test_192000_3_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_backpressure_test_192000_3_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_backpressure_test_192000_3_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_backpressure_test_192000_2_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_backpressure_test_192000_2_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_backpressure_test_192000_2_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_backpressure_test_192000_1_5_5 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_backpressure_test_192000_1_0_10 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_backpressure_test_192000_1_10_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_i2s_master_external_clock_test_0_4_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_i2s_master_external_clock_test_0_1_1 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_i2s_master_external_clock_test_0_4_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_i2s_master_external_clock_test_0_0_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_i2s_master_external_clock_test_1_4_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_i2s_master_external_clock_test_1_1_1 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_i2s_master_external_clock_test_1_4_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_i2s_master_external_clock_test_1_0_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_i2s_master_test_0_4_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_i2s_master_test_0_1_1 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_i2s_master_test_0_4_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_i2s_master_test_0_0_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_i2s_master_test_1_4_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_i2s_master_test_1_1_1 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_i2s_master_test_1_4_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_i2s_master_test_1_0_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_i2s_slave_test_0_4_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_i2s_slave_test_0_1_1 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_i2s_slave_test_0_4_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_i2s_slave_test_0_0_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_i2s_slave_test_0_2_2 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_i2s_slave_test_1_4_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_i2s_slave_test_1_1_1 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_i2s_slave_test_1_4_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_i2s_slave_test_1_0_4 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_i2s_slave_test_1_2_2 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_i2s_slave_test_0_4_4_inv XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_i2s_slave_test_0_1_1_inv XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_i2s_slave_test_0_4_0_inv XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_i2s_slave_test_0_0_4_inv XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_i2s_slave_test_0_2_2_inv XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_i2s_slave_test_1_4_4_inv XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_i2s_slave_test_1_1_1_inv XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_i2s_slave_test_1_4_0_inv XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_i2s_slave_test_1_0_4_inv XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" + "test_hil_i2s_slave_test_1_2_2_inv XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" "test_hil_i2s_tdm_tx16_slave_test_0 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" "test_hil_i2s_tdm_tx16_slave_test_1 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" "test_hil_i2s_tdm_tx16_slave_test_2 XCORE-AI-EXPLORER xmos_cmake_toolchain/xs3a.cmake" diff --git a/test/lib_i2s/test_tdm_slave_tx16_cb.py b/test/lib_i2s/test_tdm_slave_tx16_cb.py index 64d3fc1..c23c306 100644 --- a/test/lib_i2s/test_tdm_slave_tx16_cb.py +++ b/test/lib_i2s/test_tdm_slave_tx16_cb.py @@ -5,8 +5,8 @@ import Pyxsim import pytest -DEBUG = True -# DEBUG = False +# DEBUG = True +DEBUG = False tx_offset_args = {"0": (0), "1": (1), @@ -30,7 +30,7 @@ def test_tdm_slavetx16_cb(capfd, request, nightly, tx_offset): ## Temporarily building externally, see hil/build_lib_i2s_tests.sh if DEBUG: - tester = Pyxsim.testers.AssertiveComparisonTester( + tester = Pyxsim.testers.PytestComparisonTester( f'{cwd}/expected/tdm_slave_tx16_cb_test.expect', regexp = True, ordered = True @@ -45,12 +45,10 @@ def test_tdm_slavetx16_cb(capfd, request, nightly, tx_offset): tester.run(capfd.readouterr().out) else: - tester = Pyxsim.testers.AssertiveComparisonTester( + tester = Pyxsim.testers.PytestComparisonTester( f'{cwd}/expected/tdm_slave_tx16_cb_test.expect', regexp = True, ordered = True, - suppress_multidrive_messages=True, - ignore=["CONFIG:.*"] ) Pyxsim.run_with_pyxsim(binary, From 7bfbbdcef3617b46f551fdf391c4e046cf564301 Mon Sep 17 00:00:00 2001 From: Ed Date: Wed, 19 Jul 2023 11:00:31 +0100 Subject: [PATCH 10/36] Fix use of app_data for callbacks --- modules/i2s/api/i2s_tdm_slave.h | 12 ++---------- modules/i2s/src/i2s_tdm_slave.c | 18 +++++++----------- 2 files changed, 9 insertions(+), 21 deletions(-) diff --git a/modules/i2s/api/i2s_tdm_slave.h b/modules/i2s/api/i2s_tdm_slave.h index 84f8ecb..2c2996a 100644 --- a/modules/i2s/api/i2s_tdm_slave.h +++ b/modules/i2s/api/i2s_tdm_slave.h @@ -88,9 +88,6 @@ DECLARE_JOB(i2s_slave_tdm_thread, (i2s_tdm_ctx_t *)); * \param tx_offset The number of bclks from FSYNC transition to the MSB * of Slot 0 * \param slave_bclk_pol The polarity of bclk - * \param app_data A pointer to application specific data supplied - * by the application. May be used for context - * data specific to each I2S task instance. */ void i2s_tdm_slave_tx_16_init( i2s_tdm_ctx_t *ctx, @@ -100,8 +97,7 @@ void i2s_tdm_slave_tx_16_init( port_t p_bclk, xclock_t bclk, uint32_t tx_offset, - i2s_slave_bclk_polarity_t slave_bclk_polarity, - void *app_data); + i2s_slave_bclk_polarity_t slave_bclk_polarity); /** * I2S TDM TX 16 ch slave task @@ -160,9 +156,6 @@ void i2s_tdm_slave_tx_16_thread( * word_len * \param ch_per_frame The number of channels per frame * \param slave_bclk_pol The polarity of bclk - * \param app_data A pointer to application specific data supplied - * by the application. May be used for context - * data specific to each I2S task instance. */ void i2s_tdm_slave_init( i2s_tdm_ctx_t *ctx, @@ -179,8 +172,7 @@ void i2s_tdm_slave_init( uint32_t word_len, uint32_t ch_len, uint32_t ch_per_frame, - i2s_slave_bclk_polarity_t slave_bclk_pol, - void *app_data); + i2s_slave_bclk_polarity_t slave_bclk_pol); /** * I2S generic TDM slave task diff --git a/modules/i2s/src/i2s_tdm_slave.c b/modules/i2s/src/i2s_tdm_slave.c index f9c7117..7d64293 100644 --- a/modules/i2s/src/i2s_tdm_slave.c +++ b/modules/i2s/src/i2s_tdm_slave.c @@ -26,8 +26,7 @@ void i2s_tdm_slave_init( uint32_t word_len, uint32_t ch_len, uint32_t ch_per_frame, - i2s_slave_bclk_polarity_t slave_bclk_pol, - void *app_data) + i2s_slave_bclk_polarity_t slave_bclk_pol) { memset(ctx, 0, sizeof(i2s_tdm_ctx_t)); ctx->i2s_cbg = i2s_cbg; @@ -48,7 +47,6 @@ void i2s_tdm_slave_init( ctx->ch_len = ch_len; ctx->ch_per_frame = ch_per_frame; ctx->slave_bclk_polarity = I2S_SLAVE_SAMPLE_ON_BCLK_RISING; - ctx->app_data = app_data; } void i2s_tdm_slave_tx_16_init( @@ -59,8 +57,7 @@ void i2s_tdm_slave_tx_16_init( port_t p_bclk, xclock_t bclk, uint32_t tx_offset, - i2s_slave_bclk_polarity_t slave_bclk_polarity, - void *app_data) + i2s_slave_bclk_polarity_t slave_bclk_polarity) { port_t pdout[I2S_TDM_MAX_POUT_CNT]; pdout[0] = p_dout; @@ -80,8 +77,7 @@ void i2s_tdm_slave_tx_16_init( 32, /* word len */ 32, /* ch len */ 16, /* ch per frame */ - slave_bclk_polarity, - app_data); + slave_bclk_polarity); } static void i2s_tdm_slave_init_resources( @@ -136,13 +132,13 @@ void i2s_tdm_slave_tx_16_thread( while(1) { if (ctx->i2s_cbg->init != NULL) { - ctx->i2s_cbg->init((void*)ctx, NULL); + ctx->i2s_cbg->init(ctx->i2s_cbg->app_data, NULL); } xassert(ctx->num_out == 1); i2s_tdm_slave_init_resources(ctx); /* Get first frame data */ - ctx->i2s_cbg->send((void*)ctx, ctx->ch_per_frame, (int32_t*)out_samps); + ctx->i2s_cbg->send(ctx->i2s_cbg->app_data, ctx->ch_per_frame, (int32_t*)out_samps); uint32_t port_frame_time = (ctx->ch_per_frame * ctx->word_len); @@ -168,7 +164,7 @@ void i2s_tdm_slave_tx_16_thread( while(1) { /* Get frame data and tx */ - ctx->i2s_cbg->send((void*)ctx, ctx->ch_per_frame, (int32_t*)out_samps); + ctx->i2s_cbg->send(ctx->i2s_cbg->app_data, ctx->ch_per_frame, (int32_t*)out_samps); port_out(ctx->p_dout[0], bitrev(out_samps[0])); fsync_val = port_in(ctx->p_fsync); @@ -187,7 +183,7 @@ void i2s_tdm_slave_tx_16_thread( /* Check for exit condition */ if (ctx->i2s_cbg->restart_check != NULL) { - i2s_restart_t restart = ctx->i2s_cbg->restart_check((void*)ctx); + i2s_restart_t restart = ctx->i2s_cbg->restart_check(ctx->app_data); if (restart == I2S_RESTART) { break; From a8cb51e57c56c3bd0fbb071c9045391a318665fb Mon Sep 17 00:00:00 2001 From: Ed Date: Wed, 19 Jul 2023 14:31:31 +0100 Subject: [PATCH 11/36] mic_array on 16 mic branch --- modules/mic_array | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/modules/mic_array b/modules/mic_array index c045fc2..3e3afc1 160000 --- a/modules/mic_array +++ b/modules/mic_array @@ -1 +1 @@ -Subproject commit c045fc228777baccf5defd7710d029312ede4847 +Subproject commit 3e3afc1b6603c99691a12d025b19fd2198f276c8 From a5c762ecc553a9f287b641449fdb643782d6a787 Mon Sep 17 00:00:00 2001 From: Ed Date: Fri, 21 Jul 2023 07:38:29 +0100 Subject: [PATCH 12/36] Add post resource init callback to allow pad control for timing --- modules/i2s/api/i2s_tdm_slave.h | 104 ++++++++++++++++++++------------ modules/i2s/src/i2s_tdm_slave.c | 22 +++++-- 2 files changed, 84 insertions(+), 42 deletions(-) diff --git a/modules/i2s/api/i2s_tdm_slave.h b/modules/i2s/api/i2s_tdm_slave.h index 2c2996a..82b024b 100644 --- a/modules/i2s/api/i2s_tdm_slave.h +++ b/modules/i2s/api/i2s_tdm_slave.h @@ -31,6 +31,26 @@ #define I2S_TDM_MAX_CH_PER_FRAME 16 #endif /* I2S_TDM_MAX_CH_PER_FRAME */ +/** + * TDM post resource initialization event callback. + * + * The TDM component will call this after it first initializes the ports. + * This gives the app write the chance to make adjustments to port timing which + * are often needed when clocking above 15MHz. + * + * \param i2s_tdm_ctx Points to i2s_tdm_ctx_t struct allowing the resources to be + * modified after they have been enabled and initialised. + * + */ +typedef void (*tdm_post_port_init_t)(void *i2s_tdm_ctx); + +/** + * This attribute must be specified on the TDM callback function + * provided by the application. + */ +#define TDM_CALLBACK_ATTR __attribute__((fptrgroup("i2s_callback"))) + + /** * Struct to hold an I2S TDM context. * @@ -38,6 +58,7 @@ */ typedef struct { i2s_callback_group_t *i2s_cbg; + TDM_CALLBACK_ATTR tdm_post_port_init_t tdm_post_port_init; port_t p_dout[I2S_TDM_MAX_POUT_CNT]; size_t num_out; port_t p_din[I2S_TDM_MAX_PIN_CNT]; @@ -75,19 +96,22 @@ DECLARE_JOB(i2s_slave_tdm_thread, (i2s_tdm_ctx_t *)); * * The resulting context can be used with i2s_tdm_slave_tx_16_thread(). * - * \param ctx A pointer to the I2S TDM context to use. - * \param i2s_cbg The I2S callback group pointing to the application's - * functions to use for initialization and getting and receiving - * frames. For TDM the app_data variable within this - * struct is NOT used. - * \param p_dout The data output port. MUST be a 1b port - * \param p_fsync The fsync input port. MUST be a 1b port - * \param p_bclk The bit clock input port. MUST be a 1b port - * \param bclk A clock that will get configured for use with - * the bit clock - * \param tx_offset The number of bclks from FSYNC transition to the MSB - * of Slot 0 - * \param slave_bclk_pol The polarity of bclk + * \param ctx A pointer to the I2S TDM context to use. + * \param i2s_cbg The I2S callback group pointing to the application's + * functions to use for initialization and getting and receiving + * frames. For TDM the app_data variable within this + * struct is NOT used. + * \param p_dout The data output port. MUST be a 1b port + * \param p_fsync The fsync input port. MUST be a 1b port + * \param p_bclk The bit clock input port. MUST be a 1b port + * \param bclk A clock that will get configured for use with + * the bit clock + * \param tx_offset The number of bclks from FSYNC transition to the MSB + * of Slot 0 + * \param slave_bclk_pol The polarity of bclk + * \param tdm_post_port_init Callback to be called just after resource init. + * Allows for modification of port timing for >15MHz clocks. + * Set to NULL if not needed. */ void i2s_tdm_slave_tx_16_init( i2s_tdm_ctx_t *ctx, @@ -97,7 +121,8 @@ void i2s_tdm_slave_tx_16_init( port_t p_bclk, xclock_t bclk, uint32_t tx_offset, - i2s_slave_bclk_polarity_t slave_bclk_polarity); + i2s_slave_bclk_polarity_t slave_bclk_polarity, + tdm_post_port_init_t tdm_post_port_init); /** * I2S TDM TX 16 ch slave task @@ -134,28 +159,31 @@ void i2s_tdm_slave_tx_16_thread( * * The resulting context can be used with an I2S thread call. * - * \param ctx A pointer to the I2S TDM context to use. - * \param i2s_cbg The I2S callback group pointing to the application's - * functions to use for initialization and getting and receiving - * frames. For TDM the app_data variable within this - * struct is NOT used. - * \param p_dout An array of data output ports. MUST be 1b ports - * \param num_out The number of output data ports - * \param p_din An array of data input ports. MUST be 1b ports - * \param num_in The number of input data ports - * \param p_fsync The fsync input port. MUST be a 1b port - * \param p_bclk The bit clock input port. MUST be a 1b port - * \param bclk A clock that will get configured for use with - * the bit clock - * \param tx_offset The number of bclks from FSYNC transition to the MSB - * of Slot 0 - * \param fsync_len The length of the FSYNC in BCLKS - * \param word_len The number of bits in each sample frame slot. - * MUST be 32. - * \param ch_len The number of bits in each channel. MUST be less than - * word_len - * \param ch_per_frame The number of channels per frame - * \param slave_bclk_pol The polarity of bclk + * \param ctx A pointer to the I2S TDM context to use. + * \param i2s_cbg The I2S callback group pointing to the application's + * functions to use for initialization and getting and receiving + * frames. For TDM the app_data variable within this + * struct is NOT used. + * \param p_dout An array of data output ports. MUST be 1b ports + * \param num_out The number of output data ports + * \param p_din An array of data input ports. MUST be 1b ports + * \param num_in The number of input data ports + * \param p_fsync The fsync input port. MUST be a 1b port + * \param p_bclk The bit clock input port. MUST be a 1b port + * \param bclk A clock that will get configured for use with + * the bit clock + * \param tx_offset The number of bclks from FSYNC transition to the MSB + * of Slot 0 + * \param fsync_len The length of the FSYNC in BCLKS + * \param word_len The number of bits in each sample frame slot. + * MUST be 32. + * \param ch_len The number of bits in each channel. MUST be less than + * word_len + * \param ch_per_frame The number of channels per frame + * \param slave_bclk_pol The polarity of bclk + * \param tdm_post_port_init Callback to be called just after resource init. + * Allows for modification of port timing for >15MHz clocks. + * Set to NULL if not needed. */ void i2s_tdm_slave_init( i2s_tdm_ctx_t *ctx, @@ -172,7 +200,9 @@ void i2s_tdm_slave_init( uint32_t word_len, uint32_t ch_len, uint32_t ch_per_frame, - i2s_slave_bclk_polarity_t slave_bclk_pol); + i2s_slave_bclk_polarity_t slave_bclk_pol, + tdm_post_port_init_t tdm_post_port_init +); /** * I2S generic TDM slave task diff --git a/modules/i2s/src/i2s_tdm_slave.c b/modules/i2s/src/i2s_tdm_slave.c index 7d64293..62c46af 100644 --- a/modules/i2s/src/i2s_tdm_slave.c +++ b/modules/i2s/src/i2s_tdm_slave.c @@ -26,7 +26,8 @@ void i2s_tdm_slave_init( uint32_t word_len, uint32_t ch_len, uint32_t ch_per_frame, - i2s_slave_bclk_polarity_t slave_bclk_pol) + i2s_slave_bclk_polarity_t slave_bclk_pol, + tdm_post_port_init_t tdm_post_port_init) { memset(ctx, 0, sizeof(i2s_tdm_ctx_t)); ctx->i2s_cbg = i2s_cbg; @@ -47,6 +48,7 @@ void i2s_tdm_slave_init( ctx->ch_len = ch_len; ctx->ch_per_frame = ch_per_frame; ctx->slave_bclk_polarity = I2S_SLAVE_SAMPLE_ON_BCLK_RISING; + ctx->tdm_post_port_init = tdm_post_port_init; } void i2s_tdm_slave_tx_16_init( @@ -57,7 +59,8 @@ void i2s_tdm_slave_tx_16_init( port_t p_bclk, xclock_t bclk, uint32_t tx_offset, - i2s_slave_bclk_polarity_t slave_bclk_polarity) + i2s_slave_bclk_polarity_t slave_bclk_polarity, + tdm_post_port_init_t tdm_post_port_init) { port_t pdout[I2S_TDM_MAX_POUT_CNT]; pdout[0] = p_dout; @@ -77,7 +80,8 @@ void i2s_tdm_slave_tx_16_init( 32, /* word len */ 32, /* ch len */ 16, /* ch per frame */ - slave_bclk_polarity); + slave_bclk_polarity, + tdm_post_port_init); } static void i2s_tdm_slave_init_resources( @@ -131,12 +135,20 @@ void i2s_tdm_slave_tx_16_thread( uint32_t fsync_val = 0; while(1) { + xassert(ctx->num_out == 1); + if (ctx->i2s_cbg->init != NULL) { ctx->i2s_cbg->init(ctx->i2s_cbg->app_data, NULL); } - xassert(ctx->num_out == 1); + i2s_tdm_slave_init_resources(ctx); + /* Note we init the resources first to allow port delays etc. to be modified + after ports and clocks have been initialised */ + if (ctx->tdm_post_port_init != NULL) { + ctx->tdm_post_port_init(ctx); + } + /* Get first frame data */ ctx->i2s_cbg->send(ctx->i2s_cbg->app_data, ctx->ch_per_frame, (int32_t*)out_samps); @@ -183,7 +195,7 @@ void i2s_tdm_slave_tx_16_thread( /* Check for exit condition */ if (ctx->i2s_cbg->restart_check != NULL) { - i2s_restart_t restart = ctx->i2s_cbg->restart_check(ctx->app_data); + i2s_restart_t restart = ctx->i2s_cbg->restart_check(ctx->i2s_cbg->app_data); if (restart == I2S_RESTART) { break; From 75337f0956f33ae87e8136fc22cc60d1dc1493d7 Mon Sep 17 00:00:00 2001 From: Ed Date: Fri, 21 Jul 2023 07:39:34 +0100 Subject: [PATCH 13/36] Add post resource init callback for timing adjustments --- modules/i2s/api/i2s_tdm_slave.h | 104 ++++++++++++++++++++------------ modules/i2s/src/i2s_tdm_slave.c | 22 +++++-- 2 files changed, 84 insertions(+), 42 deletions(-) diff --git a/modules/i2s/api/i2s_tdm_slave.h b/modules/i2s/api/i2s_tdm_slave.h index 2c2996a..82b024b 100644 --- a/modules/i2s/api/i2s_tdm_slave.h +++ b/modules/i2s/api/i2s_tdm_slave.h @@ -31,6 +31,26 @@ #define I2S_TDM_MAX_CH_PER_FRAME 16 #endif /* I2S_TDM_MAX_CH_PER_FRAME */ +/** + * TDM post resource initialization event callback. + * + * The TDM component will call this after it first initializes the ports. + * This gives the app write the chance to make adjustments to port timing which + * are often needed when clocking above 15MHz. + * + * \param i2s_tdm_ctx Points to i2s_tdm_ctx_t struct allowing the resources to be + * modified after they have been enabled and initialised. + * + */ +typedef void (*tdm_post_port_init_t)(void *i2s_tdm_ctx); + +/** + * This attribute must be specified on the TDM callback function + * provided by the application. + */ +#define TDM_CALLBACK_ATTR __attribute__((fptrgroup("i2s_callback"))) + + /** * Struct to hold an I2S TDM context. * @@ -38,6 +58,7 @@ */ typedef struct { i2s_callback_group_t *i2s_cbg; + TDM_CALLBACK_ATTR tdm_post_port_init_t tdm_post_port_init; port_t p_dout[I2S_TDM_MAX_POUT_CNT]; size_t num_out; port_t p_din[I2S_TDM_MAX_PIN_CNT]; @@ -75,19 +96,22 @@ DECLARE_JOB(i2s_slave_tdm_thread, (i2s_tdm_ctx_t *)); * * The resulting context can be used with i2s_tdm_slave_tx_16_thread(). * - * \param ctx A pointer to the I2S TDM context to use. - * \param i2s_cbg The I2S callback group pointing to the application's - * functions to use for initialization and getting and receiving - * frames. For TDM the app_data variable within this - * struct is NOT used. - * \param p_dout The data output port. MUST be a 1b port - * \param p_fsync The fsync input port. MUST be a 1b port - * \param p_bclk The bit clock input port. MUST be a 1b port - * \param bclk A clock that will get configured for use with - * the bit clock - * \param tx_offset The number of bclks from FSYNC transition to the MSB - * of Slot 0 - * \param slave_bclk_pol The polarity of bclk + * \param ctx A pointer to the I2S TDM context to use. + * \param i2s_cbg The I2S callback group pointing to the application's + * functions to use for initialization and getting and receiving + * frames. For TDM the app_data variable within this + * struct is NOT used. + * \param p_dout The data output port. MUST be a 1b port + * \param p_fsync The fsync input port. MUST be a 1b port + * \param p_bclk The bit clock input port. MUST be a 1b port + * \param bclk A clock that will get configured for use with + * the bit clock + * \param tx_offset The number of bclks from FSYNC transition to the MSB + * of Slot 0 + * \param slave_bclk_pol The polarity of bclk + * \param tdm_post_port_init Callback to be called just after resource init. + * Allows for modification of port timing for >15MHz clocks. + * Set to NULL if not needed. */ void i2s_tdm_slave_tx_16_init( i2s_tdm_ctx_t *ctx, @@ -97,7 +121,8 @@ void i2s_tdm_slave_tx_16_init( port_t p_bclk, xclock_t bclk, uint32_t tx_offset, - i2s_slave_bclk_polarity_t slave_bclk_polarity); + i2s_slave_bclk_polarity_t slave_bclk_polarity, + tdm_post_port_init_t tdm_post_port_init); /** * I2S TDM TX 16 ch slave task @@ -134,28 +159,31 @@ void i2s_tdm_slave_tx_16_thread( * * The resulting context can be used with an I2S thread call. * - * \param ctx A pointer to the I2S TDM context to use. - * \param i2s_cbg The I2S callback group pointing to the application's - * functions to use for initialization and getting and receiving - * frames. For TDM the app_data variable within this - * struct is NOT used. - * \param p_dout An array of data output ports. MUST be 1b ports - * \param num_out The number of output data ports - * \param p_din An array of data input ports. MUST be 1b ports - * \param num_in The number of input data ports - * \param p_fsync The fsync input port. MUST be a 1b port - * \param p_bclk The bit clock input port. MUST be a 1b port - * \param bclk A clock that will get configured for use with - * the bit clock - * \param tx_offset The number of bclks from FSYNC transition to the MSB - * of Slot 0 - * \param fsync_len The length of the FSYNC in BCLKS - * \param word_len The number of bits in each sample frame slot. - * MUST be 32. - * \param ch_len The number of bits in each channel. MUST be less than - * word_len - * \param ch_per_frame The number of channels per frame - * \param slave_bclk_pol The polarity of bclk + * \param ctx A pointer to the I2S TDM context to use. + * \param i2s_cbg The I2S callback group pointing to the application's + * functions to use for initialization and getting and receiving + * frames. For TDM the app_data variable within this + * struct is NOT used. + * \param p_dout An array of data output ports. MUST be 1b ports + * \param num_out The number of output data ports + * \param p_din An array of data input ports. MUST be 1b ports + * \param num_in The number of input data ports + * \param p_fsync The fsync input port. MUST be a 1b port + * \param p_bclk The bit clock input port. MUST be a 1b port + * \param bclk A clock that will get configured for use with + * the bit clock + * \param tx_offset The number of bclks from FSYNC transition to the MSB + * of Slot 0 + * \param fsync_len The length of the FSYNC in BCLKS + * \param word_len The number of bits in each sample frame slot. + * MUST be 32. + * \param ch_len The number of bits in each channel. MUST be less than + * word_len + * \param ch_per_frame The number of channels per frame + * \param slave_bclk_pol The polarity of bclk + * \param tdm_post_port_init Callback to be called just after resource init. + * Allows for modification of port timing for >15MHz clocks. + * Set to NULL if not needed. */ void i2s_tdm_slave_init( i2s_tdm_ctx_t *ctx, @@ -172,7 +200,9 @@ void i2s_tdm_slave_init( uint32_t word_len, uint32_t ch_len, uint32_t ch_per_frame, - i2s_slave_bclk_polarity_t slave_bclk_pol); + i2s_slave_bclk_polarity_t slave_bclk_pol, + tdm_post_port_init_t tdm_post_port_init +); /** * I2S generic TDM slave task diff --git a/modules/i2s/src/i2s_tdm_slave.c b/modules/i2s/src/i2s_tdm_slave.c index 7d64293..62c46af 100644 --- a/modules/i2s/src/i2s_tdm_slave.c +++ b/modules/i2s/src/i2s_tdm_slave.c @@ -26,7 +26,8 @@ void i2s_tdm_slave_init( uint32_t word_len, uint32_t ch_len, uint32_t ch_per_frame, - i2s_slave_bclk_polarity_t slave_bclk_pol) + i2s_slave_bclk_polarity_t slave_bclk_pol, + tdm_post_port_init_t tdm_post_port_init) { memset(ctx, 0, sizeof(i2s_tdm_ctx_t)); ctx->i2s_cbg = i2s_cbg; @@ -47,6 +48,7 @@ void i2s_tdm_slave_init( ctx->ch_len = ch_len; ctx->ch_per_frame = ch_per_frame; ctx->slave_bclk_polarity = I2S_SLAVE_SAMPLE_ON_BCLK_RISING; + ctx->tdm_post_port_init = tdm_post_port_init; } void i2s_tdm_slave_tx_16_init( @@ -57,7 +59,8 @@ void i2s_tdm_slave_tx_16_init( port_t p_bclk, xclock_t bclk, uint32_t tx_offset, - i2s_slave_bclk_polarity_t slave_bclk_polarity) + i2s_slave_bclk_polarity_t slave_bclk_polarity, + tdm_post_port_init_t tdm_post_port_init) { port_t pdout[I2S_TDM_MAX_POUT_CNT]; pdout[0] = p_dout; @@ -77,7 +80,8 @@ void i2s_tdm_slave_tx_16_init( 32, /* word len */ 32, /* ch len */ 16, /* ch per frame */ - slave_bclk_polarity); + slave_bclk_polarity, + tdm_post_port_init); } static void i2s_tdm_slave_init_resources( @@ -131,12 +135,20 @@ void i2s_tdm_slave_tx_16_thread( uint32_t fsync_val = 0; while(1) { + xassert(ctx->num_out == 1); + if (ctx->i2s_cbg->init != NULL) { ctx->i2s_cbg->init(ctx->i2s_cbg->app_data, NULL); } - xassert(ctx->num_out == 1); + i2s_tdm_slave_init_resources(ctx); + /* Note we init the resources first to allow port delays etc. to be modified + after ports and clocks have been initialised */ + if (ctx->tdm_post_port_init != NULL) { + ctx->tdm_post_port_init(ctx); + } + /* Get first frame data */ ctx->i2s_cbg->send(ctx->i2s_cbg->app_data, ctx->ch_per_frame, (int32_t*)out_samps); @@ -183,7 +195,7 @@ void i2s_tdm_slave_tx_16_thread( /* Check for exit condition */ if (ctx->i2s_cbg->restart_check != NULL) { - i2s_restart_t restart = ctx->i2s_cbg->restart_check(ctx->app_data); + i2s_restart_t restart = ctx->i2s_cbg->restart_check(ctx->i2s_cbg->app_data); if (restart == I2S_RESTART) { break; From f0399492ed703d2763cbcd2a0fb78ba5632a7cf0 Mon Sep 17 00:00:00 2001 From: Ed Date: Tue, 25 Jul 2023 14:03:53 +0100 Subject: [PATCH 14/36] Enable debug compiler --- modules/i2s/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/modules/i2s/CMakeLists.txt b/modules/i2s/CMakeLists.txt index 3bc04e3..59bf2ea 100644 --- a/modules/i2s/CMakeLists.txt +++ b/modules/i2s/CMakeLists.txt @@ -13,7 +13,7 @@ if((${CMAKE_SYSTEM_NAME} STREQUAL XCORE_XS3A) OR (${CMAKE_SYSTEM_NAME} STREQUAL set(XCORE_XS3A_SOURCES ${LIB_ASM_SOURCES}) ## Set any local library compile options - set(LIB_COMPILE_FLAGS "-Os") + set(LIB_COMPILE_FLAGS -Os -g) ## Includes files set(LIB_PUBLIC_INCLUDES api) From ce27d9a15c3e53577914ae38a8a7fad7f7922afb Mon Sep 17 00:00:00 2001 From: Ed Date: Tue, 25 Jul 2023 14:10:28 +0100 Subject: [PATCH 15/36] Fix lockup bug by clearing the port value condition --- modules/i2s/src/i2s_tdm_slave.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/modules/i2s/src/i2s_tdm_slave.c b/modules/i2s/src/i2s_tdm_slave.c index 62c46af..b62c5dc 100644 --- a/modules/i2s/src/i2s_tdm_slave.c +++ b/modules/i2s/src/i2s_tdm_slave.c @@ -160,7 +160,8 @@ void i2s_tdm_slave_tx_16_thread( port_set_trigger_in_equal(ctx->p_fsync, 1); (void) port_in(ctx->p_fsync); port_timestamp_t fsync_edge_time = port_get_trigger_time(ctx->p_fsync); - + port_clear_trigger_in(ctx->p_fsync); + /* Setup trigger times */ port_set_trigger_time(ctx->p_fsync, port_frame_time + fsync_edge_time); port_set_trigger_time(ctx->p_dout[0], port_frame_time + fsync_edge_time + ctx->tx_offset); @@ -181,7 +182,7 @@ void i2s_tdm_slave_tx_16_thread( port_out(ctx->p_dout[0], bitrev(out_samps[0])); fsync_val = port_in(ctx->p_fsync); fsync_edge_time = port_get_trigger_time(ctx->p_fsync); - port_set_trigger_time(ctx->p_fsync, port_frame_time + fsync_edge_time); + port_set_trigger_time(ctx->p_fsync, fsync_edge_time + port_frame_time); /* Note: Still possible for us to alias, but this will catch nonperiod drifting */ if (fsync_val != 1) { From 77baeae7085ae88314df2e5fba3f818c20bbc406 Mon Sep 17 00:00:00 2001 From: Ed Date: Tue, 25 Jul 2023 14:42:25 +0100 Subject: [PATCH 16/36] Add fsynch_error field in struct --- modules/i2s/api/i2s_tdm_slave.h | 2 ++ modules/i2s/src/i2s_tdm_slave.c | 4 +++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/modules/i2s/api/i2s_tdm_slave.h b/modules/i2s/api/i2s_tdm_slave.h index 82b024b..1117f7f 100644 --- a/modules/i2s/api/i2s_tdm_slave.h +++ b/modules/i2s/api/i2s_tdm_slave.h @@ -5,6 +5,7 @@ #include #include #include +#include #include #include @@ -72,6 +73,7 @@ typedef struct { uint32_t ch_len; uint32_t ch_per_frame; i2s_slave_bclk_polarity_t slave_bclk_polarity; + bool fysnch_error; void *app_data; } i2s_tdm_ctx_t; diff --git a/modules/i2s/src/i2s_tdm_slave.c b/modules/i2s/src/i2s_tdm_slave.c index b62c5dc..f2f9249 100644 --- a/modules/i2s/src/i2s_tdm_slave.c +++ b/modules/i2s/src/i2s_tdm_slave.c @@ -49,6 +49,7 @@ void i2s_tdm_slave_init( ctx->ch_per_frame = ch_per_frame; ctx->slave_bclk_polarity = I2S_SLAVE_SAMPLE_ON_BCLK_RISING; ctx->tdm_post_port_init = tdm_post_port_init; + ctx->fysnch_error = false; } void i2s_tdm_slave_tx_16_init( @@ -155,6 +156,7 @@ void i2s_tdm_slave_tx_16_thread( uint32_t port_frame_time = (ctx->ch_per_frame * ctx->word_len); /* Wait for first fsync rising edge to occur */ + ctx->fysnch_error = false; port_set_trigger_in_equal(ctx->p_fsync, 0); (void) port_in(ctx->p_fsync); port_set_trigger_in_equal(ctx->p_fsync, 1); @@ -186,7 +188,7 @@ void i2s_tdm_slave_tx_16_thread( /* Note: Still possible for us to alias, but this will catch nonperiod drifting */ if (fsync_val != 1) { - // printf("fsync_error\n"); + ctx->fysnch_error = true; break; } From bc29e2c8b8fe3837b98a01f72d0712309ef7a77b Mon Sep 17 00:00:00 2001 From: Ed Date: Wed, 26 Jul 2023 07:18:28 +0100 Subject: [PATCH 17/36] Add support for falling/rising edge in test --- test/lib_i2s/tdm_slave_checker.py | 32 ++++++++++++++++++++++--------- 1 file changed, 23 insertions(+), 9 deletions(-) diff --git a/test/lib_i2s/tdm_slave_checker.py b/test/lib_i2s/tdm_slave_checker.py index d376b93..194de99 100644 --- a/test/lib_i2s/tdm_slave_checker.py +++ b/test/lib_i2s/tdm_slave_checker.py @@ -4,6 +4,9 @@ class TDMSlaveTX16Checker(Pyxsim.SimThread): + sample_on_falling = 0 + sample_on_rising = 1 + def __init__( self, sclk, @@ -11,7 +14,8 @@ def __init__( dout, setup_strobe_port, setup_data_port, - setup_resp_port + setup_resp_port, + sample_edge ): self._sclk = sclk self._fsync = fsync @@ -19,6 +23,7 @@ def __init__( self._setup_strobe_port = setup_strobe_port self._setup_data_port = setup_data_port self._setup_resp_port = setup_resp_port + self._sample_edge = sample_edge def get_setup_data(self, xsi: Pyxsim.pyxsim.Xsi, @@ -45,6 +50,8 @@ def run(self): print(f"CONFIG: bclk:{sclk_frequency}") clock_half_period = float(1000000000000) / float(2 * (sclk_frequency/1000)) ## Want freq in khz + edge_str = "FALLING" if self._sample_edge==self.sample_on_falling else "RISING" + print(f"CONFIG: bclk:{sclk_frequency} sample_edge: {edge_str} fsynch_len: {fsync_len}") clock_quarter_period = clock_half_period / 2 #first do the setup rx @@ -59,9 +66,9 @@ def run(self): print(f"Got Settings:tx_offset {tx_offset}") # drive initial values while slave starts up for the first time - xsi.drive_port_pins(self._sclk, 1) + xsi.drive_port_pins(self._sclk, 1 if self._sample_edge == self.sample_on_rising else 0) xsi.drive_port_pins(self._fsync, 0) - self.wait_until(xsi.get_time() + 10000000) + self.wait_until(xsi.get_time() + 1000000) frame_cnt = 0 # Start test @@ -69,11 +76,14 @@ def run(self): bits_rx = 0 bclk_val = 0 + # print(f"frame:{frame_cnt}") for i in range(0, blcks_per_frame): + if i % bits_per_word == 0: + word_rx = 0 # bclk - xsi.drive_port_pins(self._sclk, 0) + xsi.drive_port_pins(self._sclk, 0 if self._sample_edge == self.sample_on_rising else 1) # fsync if bits_rx % blcks_per_frame == 0: @@ -87,7 +97,7 @@ def run(self): self.wait_until(time) # bclk - xsi.drive_port_pins(self._sclk, 1) + xsi.drive_port_pins(self._sclk, 1 if self._sample_edge == self.sample_on_rising else 0) # fsync (unchanged) if bits_rx % blcks_per_frame == 0: @@ -102,6 +112,7 @@ def run(self): # sample bit_val = xsi.sample_port_pins(self._dout) + word_rx |= bit_val << ((i - tx_offset) % bits_per_word) if frame_cnt >= 2: # Ignore init frame as data is 0's while slave syncs up frame_arg = 0 @@ -126,21 +137,24 @@ def run(self): # For the first frame, if tx_offset > 0, the first tx_offset bits are don't cares if frame_cnt == 2 and bits_rx > tx_offset: if bit_val != expect_rx: - print(f"bit[{bits_rx}]:{bit_val}:{expect_rx}") + print(f"ERROR: bit[{bits_rx}]:{bit_val}:{expect_rx}") bits_rx += 1 time = xsi.get_time() time = time + clock_quarter_period self.wait_until(time) + if i % bits_per_word == bits_per_word - 1: + print(f"Received word: {frame_cnt} {i // bits_per_word} {hex(word_rx)}") + frame_cnt += 1 def calc_expected_bit(self, frame, bit): # Each sample in the tdm_slave_tx16_test output is in the format - # bin AAAABBBB BBBBBBBB BBBBBBBB BBBBBBBB + # bin AAAAAAAA BBBBBBBB BBBBBBBB BBBBBBBB # Where: - # AAAA is the channel id, [0,15] - # BBBB BBBBBBBB BBBBBBBB BBBBBBBB is frame num starting at 1 + # AAAAAAAA is the channel id, [0,255] + # BBBBBBBB BBBBBBBB BBBBBBBB is frame num starting at 1 # Additionally, the output data is bitrev, so that it shows up # in a more easily recognizable format on the wire in vcd traces ret = 0 From b5765abbf346d00cffff3ae3e936e3cb3ad3e253 Mon Sep 17 00:00:00 2001 From: Ed Date: Wed, 26 Jul 2023 07:19:18 +0100 Subject: [PATCH 18/36] tidy test fw --- test/lib_i2s/tdm_slave_tx16_cb_test/src/tdm_slave_tx16_test.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/test/lib_i2s/tdm_slave_tx16_cb_test/src/tdm_slave_tx16_test.c b/test/lib_i2s/tdm_slave_tx16_cb_test/src/tdm_slave_tx16_test.c index 70ba118..81bdb69 100644 --- a/test/lib_i2s/tdm_slave_tx16_cb_test/src/tdm_slave_tx16_test.c +++ b/test/lib_i2s/tdm_slave_tx16_cb_test/src/tdm_slave_tx16_test.c @@ -4,6 +4,7 @@ #include #include #include +#include #include "xcore/port.h" #include "xcore/clock.h" @@ -29,7 +30,7 @@ port_t setup_resp_port = XS1_PORT_1F; #define TEST_NUM_CH 16 #endif -int32_t test_data[TEST_FRAME_COUNT][TEST_NUM_CH] = {0}; +int32_t test_data[TEST_FRAME_COUNT][TEST_NUM_CH] = {{0}}; DECLARE_JOB(burn, (void)); @@ -73,6 +74,7 @@ static uint32_t request_response( I2S_CALLBACK_ATTR void i2s_init(void *app_data, i2s_config_t *i2s_config) { + printf("i2s_init\n"); (void) app_data; (void) i2s_config; From 14f443e6847f82d0f517848545661a4510c6590f Mon Sep 17 00:00:00 2001 From: Ed Date: Wed, 26 Jul 2023 07:19:55 +0100 Subject: [PATCH 19/36] Fix timebase in checker --- test/lib_i2s/tdm_slave_checker.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/test/lib_i2s/tdm_slave_checker.py b/test/lib_i2s/tdm_slave_checker.py index 194de99..c0d8183 100644 --- a/test/lib_i2s/tdm_slave_checker.py +++ b/test/lib_i2s/tdm_slave_checker.py @@ -48,10 +48,9 @@ def run(self): sclk_frequency = 49152000 blcks_per_frame = bits_per_word * ch_count - print(f"CONFIG: bclk:{sclk_frequency}") - clock_half_period = float(1000000000000) / float(2 * (sclk_frequency/1000)) ## Want freq in khz edge_str = "FALLING" if self._sample_edge==self.sample_on_falling else "RISING" print(f"CONFIG: bclk:{sclk_frequency} sample_edge: {edge_str} fsynch_len: {fsync_len}") + clock_half_period = float(1000000000) / float(2 * (sclk_frequency/1000)) ## Want freq in khz clock_quarter_period = clock_half_period / 2 #first do the setup rx From b62071639e8848c64add310af262e040de6e4cc0 Mon Sep 17 00:00:00 2001 From: Ed Date: Wed, 26 Jul 2023 07:20:30 +0100 Subject: [PATCH 20/36] Support up to 256 slots in tdm test --- test/lib_i2s/tdm_slave_checker.py | 4 ++-- test/lib_i2s/tdm_slave_tx16_cb_test/src/tdm_slave_tx16_test.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/test/lib_i2s/tdm_slave_checker.py b/test/lib_i2s/tdm_slave_checker.py index c0d8183..e940a04 100644 --- a/test/lib_i2s/tdm_slave_checker.py +++ b/test/lib_i2s/tdm_slave_checker.py @@ -161,8 +161,8 @@ def calc_expected_bit(self, frame, bit): ch = bit // 32 ch_index = bit % 32 - if ch_index >= 28: - ret = (ch >> (ch_index - 28)) & 0b1 + if ch_index >= 24: + ret = (ch >> (ch_index - 24)) & 0b1 else: ret = (frame >> ch_index) & 0b1 diff --git a/test/lib_i2s/tdm_slave_tx16_cb_test/src/tdm_slave_tx16_test.c b/test/lib_i2s/tdm_slave_tx16_cb_test/src/tdm_slave_tx16_test.c index 81bdb69..0e5d591 100644 --- a/test/lib_i2s/tdm_slave_tx16_cb_test/src/tdm_slave_tx16_test.c +++ b/test/lib_i2s/tdm_slave_tx16_cb_test/src/tdm_slave_tx16_test.c @@ -82,7 +82,7 @@ void i2s_init(void *app_data, i2s_config_t *i2s_config) for (int i=1; i<=TEST_FRAME_COUNT; i++) { for (int j=0; j Date: Wed, 26 Jul 2023 07:21:00 +0100 Subject: [PATCH 21/36] Support debug VCD output properly --- test/lib_i2s/test_tdm_slave_tx16_cb.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/test/lib_i2s/test_tdm_slave_tx16_cb.py b/test/lib_i2s/test_tdm_slave_tx16_cb.py index c23c306..33a9b4a 100644 --- a/test/lib_i2s/test_tdm_slave_tx16_cb.py +++ b/test/lib_i2s/test_tdm_slave_tx16_cb.py @@ -25,7 +25,8 @@ def test_tdm_slavetx16_cb(capfd, request, nightly, tx_offset): "tile[0]:XS1_PORT_1D", "tile[0]:XS1_PORT_1E", "tile[0]:XS1_PORT_16B", - "tile[0]:XS1_PORT_1F") + "tile[0]:XS1_PORT_1F", + sample_edge=TDMSlaveTX16Checker.sample_on_rising) ## Temporarily building externally, see hil/build_lib_i2s_tests.sh @@ -39,8 +40,7 @@ def test_tdm_slavetx16_cb(capfd, request, nightly, tx_offset): with capfd.disabled(): Pyxsim.run_with_pyxsim(binary, simthreads = [checker], - simargs = [], - vcdTracing = True, + simargs = ["--vcd-tracing", f"-o tdm_trace_{tx_offset}.vcd -tile tile[0] -cycles -ports -ports-detailed -cores -instructions"], timeout = 100) tester.run(capfd.readouterr().out) From 1350408933753011b9d228c0167c8c73716c1a6a Mon Sep 17 00:00:00 2001 From: Ed Date: Wed, 26 Jul 2023 09:50:57 +0100 Subject: [PATCH 22/36] Working test at 33MHz --- .../expected/tdm_slave_tx16_cb_test.expect | 371 +++++++++++++++++- test/lib_i2s/tdm_slave_checker.py | 9 +- .../i2s_tdm_tx16_slave_test.cmake | 2 +- .../src/tdm_slave_tx16_test.c | 26 +- test/lib_i2s/test_tdm_slave_tx16_cb.py | 3 +- 5 files changed, 395 insertions(+), 16 deletions(-) diff --git a/test/lib_i2s/expected/tdm_slave_tx16_cb_test.expect b/test/lib_i2s/expected/tdm_slave_tx16_cb_test.expect index 83b9957..4542757 100644 --- a/test/lib_i2s/expected/tdm_slave_tx16_cb_test.expect +++ b/test/lib_i2s/expected/tdm_slave_tx16_cb_test.expect @@ -1,3 +1,372 @@ +i2s_init TDM Slave TX 16 Checker Started -CONFIG: bclk:\d+ +CONFIG: bclk:\d+ sample_edge: [A-Z]+ fsynch_len: \d+ Got Settings:tx_offset \d+ +Received word: 0 0 0x0 +Received word: 0 1 0x0 +Received word: 0 2 0x0 +Received word: 0 3 0x0 +Received word: 0 4 0x0 +Received word: 0 5 0x0 +Received word: 0 6 0x0 +Received word: 0 7 0x0 +Received word: 0 8 0x0 +Received word: 0 9 0x0 +Received word: 0 10 0x0 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0x4000013 +Received word: 21 5 0x5000013 +Received word: 21 6 0x6000013 +Received word: 21 7 0x7000013 +Received word: 21 8 0x8000013 +Received word: 21 9 0x9000013 +Received word: 21 10 0xa000013 +Received word: 21 11 0xb000013 +Received word: 21 12 0xc000013 +Received word: 21 13 0xd000013 +Received word: 21 14 0xe000013 +Received word: 21 15 0xf000013 +Received word: 22 0 0x14 +Received word: 22 1 0x1000014 +Received word: 22 2 0x2000014 +Received word: 22 3 0x3000014 +Received word: 22 4 0x4000014 +Received word: 22 5 0x5000014 +Received word: 22 6 0x6000014 +Received word: 22 7 0x7000014 +Received word: 22 8 0x8000014 +Received word: 22 9 0x9000014 +Received word: 22 10 0xa000014 +Received word: 22 11 0xb000014 +Received word: 22 12 0xc000014 +Received word: 22 13 0xd000014 +Received word: 22 14 0xe000014 +Received word: 22 15 0xf000014 diff --git a/test/lib_i2s/tdm_slave_checker.py b/test/lib_i2s/tdm_slave_checker.py index e940a04..36bab4b 100644 --- a/test/lib_i2s/tdm_slave_checker.py +++ b/test/lib_i2s/tdm_slave_checker.py @@ -15,7 +15,8 @@ def __init__( setup_strobe_port, setup_data_port, setup_resp_port, - sample_edge + sample_edge, + sclk_frequency ): self._sclk = sclk self._fsync = fsync @@ -24,6 +25,7 @@ def __init__( self._setup_data_port = setup_data_port self._setup_resp_port = setup_resp_port self._sample_edge = sample_edge + self._sclk_frequency = sclk_frequency def get_setup_data(self, xsi: Pyxsim.pyxsim.Xsi, @@ -45,12 +47,11 @@ def run(self): ch_count = 16 fsync_len = 1 - sclk_frequency = 49152000 blcks_per_frame = bits_per_word * ch_count edge_str = "FALLING" if self._sample_edge==self.sample_on_falling else "RISING" - print(f"CONFIG: bclk:{sclk_frequency} sample_edge: {edge_str} fsynch_len: {fsync_len}") - clock_half_period = float(1000000000) / float(2 * (sclk_frequency/1000)) ## Want freq in khz + print(f"CONFIG: bclk:{self._sclk_frequency} sample_edge: {edge_str} fsynch_len: {fsync_len}") + clock_half_period = float(1000000000) / float(2 * (self._sclk_frequency/1000)) ## Want freq in Hz clock_quarter_period = clock_half_period / 2 #first do the setup rx diff --git a/test/lib_i2s/tdm_slave_tx16_cb_test/i2s_tdm_tx16_slave_test.cmake b/test/lib_i2s/tdm_slave_tx16_cb_test/i2s_tdm_tx16_slave_test.cmake index a02171a..bda00db 100644 --- a/test/lib_i2s/tdm_slave_tx16_cb_test/i2s_tdm_tx16_slave_test.cmake +++ b/test/lib_i2s/tdm_slave_tx16_cb_test/i2s_tdm_tx16_slave_test.cmake @@ -8,7 +8,7 @@ set(APP_INCLUDES ${CMAKE_CURRENT_LIST_DIR}/src) # Flags #********************** set(APP_COMPILER_FLAGS - -Os + -O3 -target=XCORE-AI-EXPLORER ) set(APP_LINK_OPTIONS diff --git a/test/lib_i2s/tdm_slave_tx16_cb_test/src/tdm_slave_tx16_test.c b/test/lib_i2s/tdm_slave_tx16_cb_test/src/tdm_slave_tx16_test.c index 0e5d591..69cf068 100644 --- a/test/lib_i2s/tdm_slave_tx16_cb_test/src/tdm_slave_tx16_test.c +++ b/test/lib_i2s/tdm_slave_tx16_cb_test/src/tdm_slave_tx16_test.c @@ -24,13 +24,14 @@ port_t setup_data_port = XS1_PORT_16B; port_t setup_resp_port = XS1_PORT_1F; #ifndef TEST_FRAME_COUNT -#define TEST_FRAME_COUNT 100 +#define TEST_FRAME_COUNT 20 #endif #ifndef TEST_NUM_CH #define TEST_NUM_CH 16 #endif int32_t test_data[TEST_FRAME_COUNT][TEST_NUM_CH] = {{0}}; +volatile int32_t cnt = 0; DECLARE_JOB(burn, (void)); @@ -78,6 +79,12 @@ void i2s_init(void *app_data, i2s_config_t *i2s_config) (void) app_data; (void) i2s_config; + if (cnt > 0) { + printf("Restart likely due to fsynch error at frame count: %ld\n", cnt); + _Exit(1); + } + + /* Initialize test data */ for (int i=1; i<=TEST_FRAME_COUNT; i++) { for (int j=0; j Date: Wed, 26 Jul 2023 10:29:44 +0100 Subject: [PATCH 23/36] Return mic_array to head of develop for now --- modules/mic_array | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/modules/mic_array b/modules/mic_array index 3e3afc1..c045fc2 160000 --- a/modules/mic_array +++ b/modules/mic_array @@ -1 +1 @@ -Subproject commit 3e3afc1b6603c99691a12d025b19fd2198f276c8 +Subproject commit c045fc228777baccf5defd7710d029312ede4847 From 9173932af16d26da1a2588384efc7522a7ee6f79 Mon Sep 17 00:00:00 2001 From: Ed Date: Wed, 26 Jul 2023 11:10:43 +0100 Subject: [PATCH 24/36] Fix path on pytest invocation --- test/run_tests.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/run_tests.sh b/test/run_tests.sh index 32ee865..9b9e8aa 100755 --- a/test/run_tests.sh +++ b/test/run_tests.sh @@ -36,7 +36,7 @@ for lib in ${hil_test_libs[@]}; do echo "************************" #https://docs.github.com/en/actions/using-github-hosted-runners/about-github-hosted-runners #Looks like runners are 2 cores (maybe 2 HT) so run 4 at a time for speedup - cd ${lib} && pytest -n 4 --junitxml="test_results.xml" + cd ${lib} && pytest -n 4 --junitxml="test_results.xml" ${lib}/test_*.py popd done From 46776aaa6069d0dcdaaa49f01d349e3730452359 Mon Sep 17 00:00:00 2001 From: Ed Date: Wed, 26 Jul 2023 11:23:19 +0100 Subject: [PATCH 25/36] Fix dir --- test/run_tests.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/run_tests.sh b/test/run_tests.sh index 9b9e8aa..3fa5485 100755 --- a/test/run_tests.sh +++ b/test/run_tests.sh @@ -36,7 +36,7 @@ for lib in ${hil_test_libs[@]}; do echo "************************" #https://docs.github.com/en/actions/using-github-hosted-runners/about-github-hosted-runners #Looks like runners are 2 cores (maybe 2 HT) so run 4 at a time for speedup - cd ${lib} && pytest -n 4 --junitxml="test_results.xml" ${lib}/test_*.py + pytest -n 4 --junitxml="test_results.xml" ${lib}/test_*.py popd done From ec69c7c2975abd24ee6d9a9a459dfa27d564b9ed Mon Sep 17 00:00:00 2001 From: Ed Date: Wed, 26 Jul 2023 14:26:03 +0100 Subject: [PATCH 26/36] Fix issue where I2S clock is output before clock start causing test failure --- modules/i2s/src/i2s_master.c | 2 ++ test/lib_i2s/i2s_master_test/src/main.c | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/modules/i2s/src/i2s_master.c b/modules/i2s/src/i2s_master.c index 992a9ce..c8323fd 100644 --- a/modules/i2s/src/i2s_master.c +++ b/modules/i2s/src/i2s_master.c @@ -31,6 +31,8 @@ static void i2s_init_ports( { size_t i; + clock_stop(bclk); + port_reset(p_bclk); port_set_clock(p_bclk, bclk); port_set_out_clock(p_bclk); diff --git a/test/lib_i2s/i2s_master_test/src/main.c b/test/lib_i2s/i2s_master_test/src/main.c index 2ba6501..42824e7 100644 --- a/test/lib_i2s/i2s_master_test/src/main.c +++ b/test/lib_i2s/i2s_master_test/src/main.c @@ -17,7 +17,7 @@ xclock_t bclk = XS1_CLKBLK_2; port_t setup_strobe_port = XS1_PORT_1L; port_t setup_data_port = XS1_PORT_16A; -port_t setup_resp_port = XS1_PORT_1M; +port_t setup_resp_port = XS1_PORT_1M; #define MAX_RATIO 4 From 4f186b369f62c2a927d00e4cf15db7598ede70a1 Mon Sep 17 00:00:00 2001 From: Ed Date: Wed, 26 Jul 2023 14:27:09 +0100 Subject: [PATCH 27/36] Support debug on I2S master test --- test/lib_i2s/i2s_master_checker.py | 2 +- test/lib_i2s/test_i2s_basic_master.py | 11 +++++++++-- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/test/lib_i2s/i2s_master_checker.py b/test/lib_i2s/i2s_master_checker.py index d402244..28d02c2 100644 --- a/test/lib_i2s/i2s_master_checker.py +++ b/test/lib_i2s/i2s_master_checker.py @@ -14,7 +14,7 @@ class Clock(px.SimThread): def __init__(self, port: str) -> None: - self._rate = 1000000000 + self._rate = 100000000 # Just set to arbitrary 100MHz initially self._driving = True self._half_period = float(500000000000) / self._rate self._port = port diff --git a/test/lib_i2s/test_i2s_basic_master.py b/test/lib_i2s/test_i2s_basic_master.py index 00f2a86..a0b77d7 100644 --- a/test/lib_i2s/test_i2s_basic_master.py +++ b/test/lib_i2s/test_i2s_basic_master.py @@ -5,6 +5,9 @@ import Pyxsim as px import pytest +DEBUG = False +# DEBUG = True + num_in_out_args = {"4ch_in,4ch_out": (4, 4), "1ch_in,1ch_out": (1, 1), "4ch_in,0ch_out": (4, 0), @@ -40,7 +43,11 @@ def test_i2s_basic_master(build, capfd, nightly, request, num_in, num_out): # env = {"NUMS_IN_OUT":f'{num_in};{num_out}', "TEST_LEVEL":f'{test_level}'}, # bin_child = id_string) - px.run_with_pyxsim(binary, - simthreads = [clk, checker]) + if DEBUG: + with capfd.disabled(): + px.run_with_pyxsim(binary, simthreads = [clk, checker], + simargs = ["--vcd-tracing", f"-o i2s_trace_{num_in}_{num_out}.vcd -tile tile[0] -cycles -ports -ports-detailed -cores -instructions"]) + else: + px.run_with_pyxsim(binary, simthreads = [clk, checker]) tester.run(capfd.readouterr().out) From 218c18b3a80a9b1f480751a778256c61daa0baa6 Mon Sep 17 00:00:00 2001 From: Ed Date: Wed, 26 Jul 2023 14:50:25 +0100 Subject: [PATCH 28/36] Print tools version in action --- test/run_tests.sh | 2 ++ 1 file changed, 2 insertions(+) diff --git a/test/run_tests.sh b/test/run_tests.sh index 3fa5485..3617242 100755 --- a/test/run_tests.sh +++ b/test/run_tests.sh @@ -24,6 +24,8 @@ fi # Run tests and copy results #**************************** tests_start=`date +%s` +tools_ver=`xcc --version` +echo "Using tools_ver ${tools_ver}" for lib in ${hil_test_libs[@]}; do pushd . From 88dbc3b15eb3044287b65b70ed75b479763cbdba Mon Sep 17 00:00:00 2001 From: Ed Date: Wed, 26 Jul 2023 14:56:27 +0100 Subject: [PATCH 29/36] Fix expected output which seems to be different on CI than local!? --- test/lib_i2s/expected/tdm_slave_tx16_cb_test.expect | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/lib_i2s/expected/tdm_slave_tx16_cb_test.expect b/test/lib_i2s/expected/tdm_slave_tx16_cb_test.expect index 4542757..dcc2fb3 100644 --- a/test/lib_i2s/expected/tdm_slave_tx16_cb_test.expect +++ b/test/lib_i2s/expected/tdm_slave_tx16_cb_test.expect @@ -1,6 +1,6 @@ -i2s_init TDM Slave TX 16 Checker Started CONFIG: bclk:\d+ sample_edge: [A-Z]+ fsynch_len: \d+ +i2s_init Got Settings:tx_offset \d+ Received word: 0 0 0x0 Received word: 0 1 0x0 From 1c8fe555df50f193244e2c004aa7856227f52f20 Mon Sep 17 00:00:00 2001 From: Ed Date: Thu, 27 Jul 2023 11:15:51 +0100 Subject: [PATCH 30/36] Fix verify_tests --- test/conftest.py | 2 ++ test/run_tests.sh | 4 +-- test/test_verify_results.py | 70 ++++++++++++++++++++----------------- 3 files changed, 41 insertions(+), 35 deletions(-) diff --git a/test/conftest.py b/test/conftest.py index 938e25e..7b3a70e 100644 --- a/test/conftest.py +++ b/test/conftest.py @@ -25,6 +25,8 @@ def pytest_collection_modifyitems(config, items): def pytest_addoption(parser): parser.addoption("--nightly", action="store_true") + parser.addoption("--lib_names", action="store", default=[], help="Optional list of libs to verify the output from") + @pytest.fixture def build(): diff --git a/test/run_tests.sh b/test/run_tests.sh index 3617242..2782f1a 100755 --- a/test/run_tests.sh +++ b/test/run_tests.sh @@ -38,7 +38,7 @@ for lib in ${hil_test_libs[@]}; do echo "************************" #https://docs.github.com/en/actions/using-github-hosted-runners/about-github-hosted-runners #Looks like runners are 2 cores (maybe 2 HT) so run 4 at a time for speedup - pytest -n 4 --junitxml="test_results.xml" ${lib}/test_*.py + pytest -n 4 --junitxml="test_results_${lib}.xml" ${lib}/test_*.py popd done @@ -47,7 +47,7 @@ tests_end=`date +%s` #**************************** # Check results #**************************** -pytest test_verify_results.py ${hil_test_libs[*]} +pytest test_verify_results.py --lib_names '${hil_test_libs[*]'} #**************************** # Display time results diff --git a/test/test_verify_results.py b/test/test_verify_results.py index c21e441..b87259f 100644 --- a/test/test_verify_results.py +++ b/test/test_verify_results.py @@ -1,39 +1,43 @@ #!/usr/bin/env python -# Copyright 2021 XMOS LIMITED. +# Copyright 2021-2023 XMOS LIMITED. # This Software is subject to the terms of the XMOS Public Licence: Version 1. import sys import pytest import xml.etree.ElementTree as ET -if len(sys.argv) == 2: - libs = ["lib_uart", "lib_i2c", "lib_i2s", "lib_spi"] -else: - libs = sys.argv[2:] - -acceptable_outcomes = ("skipped",) -result_fname = "test_results.xml" - -test_libs = {lib: lib + "/" + result_fname for lib in libs} - - -@pytest.mark.parametrize("fname", test_libs.values(), ids=test_libs.keys()) -def test_results(fname): - tree = ET.parse(fname) - root = tree.getroot() - tsuite = root.find("testsuite") - - # There should at least be some tests in here. Assert that this is the case. - assert len(tsuite) > 0 - - for testcase in tsuite.iter("testcase"): - # Test passed if there are no children - if len(testcase) == 0: - continue - # Otherwise, test was either skipped, errored, or failed. The testcase - # will have a child with a relevant tag - skipped, error, or failure. - # If the tag is acceptable then carry on, or otherwise assert failure. - else: - for child in testcase: - assert ( - child.tag in acceptable_outcomes - ), f"A test reports as {child.tag}, which is not accepted." + +@pytest.fixture(scope="session") +def lib_names(pytestconfig): + lib_names = pytestconfig.getoption("lib_names").split() + return lib_names + +def test_results(lib_names): + + for lib in lib_names: + result_fname = f"test_results_{lib}.xml" + tree = ET.parse(result_fname) + root = tree.getroot() + tsuite = root.find("testsuite") + + acceptable_outcomes = ("skipped",) + + + # There should at least be some tests in here. Assert that this is the case. + assert len(tsuite) > 0 + + for testcase in tsuite.iter("testcase"): + + # Test passed if there are no children + if len(testcase) == 0: + if "name" in testcase.attrib: + print(testcase.attrib['name'], "passed") + continue + # Otherwise, test was either skipped, errored, or failed. The testcase + # will have a child with a relevant tag - skipped, error, or failure. + # If the tag is acceptable then carry on, or otherwise assert failure. + else: + for child in testcase: + assert ( + child.tag in acceptable_outcomes + ), f"A test reports as {child.tag}, which is not accepted." + print(testcase.attrib['name'], child.tag ) From b90cbe2984289f8332aa8fc0e36847c3beba2d4b Mon Sep 17 00:00:00 2001 From: Ed Date: Thu, 27 Jul 2023 11:39:06 +0100 Subject: [PATCH 31/36] Change to single lib name --- test/conftest.py | 2 +- test/run_tests.sh | 4 ++- test/test_verify_results.py | 67 ++++++++++++++++++------------------- 3 files changed, 37 insertions(+), 36 deletions(-) diff --git a/test/conftest.py b/test/conftest.py index 7b3a70e..2a035aa 100644 --- a/test/conftest.py +++ b/test/conftest.py @@ -25,7 +25,7 @@ def pytest_collection_modifyitems(config, items): def pytest_addoption(parser): parser.addoption("--nightly", action="store_true") - parser.addoption("--lib_names", action="store", default=[], help="Optional list of libs to verify the output from") + parser.addoption("--lib_name", action="store", default=[], help="Optional lib to verify the output from") @pytest.fixture diff --git a/test/run_tests.sh b/test/run_tests.sh index 2782f1a..5525827 100755 --- a/test/run_tests.sh +++ b/test/run_tests.sh @@ -47,7 +47,9 @@ tests_end=`date +%s` #**************************** # Check results #**************************** -pytest test_verify_results.py --lib_names '${hil_test_libs[*]'} +for lib in ${hil_test_libs[@]}; do + pytest test_verify_results.py --lib_name ${lib} +done #**************************** # Display time results diff --git a/test/test_verify_results.py b/test/test_verify_results.py index b87259f..2d234ea 100644 --- a/test/test_verify_results.py +++ b/test/test_verify_results.py @@ -7,37 +7,36 @@ @pytest.fixture(scope="session") -def lib_names(pytestconfig): - lib_names = pytestconfig.getoption("lib_names").split() - return lib_names - -def test_results(lib_names): - - for lib in lib_names: - result_fname = f"test_results_{lib}.xml" - tree = ET.parse(result_fname) - root = tree.getroot() - tsuite = root.find("testsuite") - - acceptable_outcomes = ("skipped",) - - - # There should at least be some tests in here. Assert that this is the case. - assert len(tsuite) > 0 - - for testcase in tsuite.iter("testcase"): - - # Test passed if there are no children - if len(testcase) == 0: - if "name" in testcase.attrib: - print(testcase.attrib['name'], "passed") - continue - # Otherwise, test was either skipped, errored, or failed. The testcase - # will have a child with a relevant tag - skipped, error, or failure. - # If the tag is acceptable then carry on, or otherwise assert failure. - else: - for child in testcase: - assert ( - child.tag in acceptable_outcomes - ), f"A test reports as {child.tag}, which is not accepted." - print(testcase.attrib['name'], child.tag ) +def lib_name(pytestconfig): + lib_name = pytestconfig.getoption("lib_name").split() + return lib_name + +def test_results(lib_name): + lib = lib_name[0] + result_fname = f"test_results_{lib}.xml" + tree = ET.parse(result_fname) + root = tree.getroot() + tsuite = root.find("testsuite") + + acceptable_outcomes = ("skipped",) + + + # There should at least be some tests in here. Assert that this is the case. + assert len(tsuite) > 0 + + for testcase in tsuite.iter("testcase"): + + # Test passed if there are no children + if len(testcase) == 0: + if "name" in testcase.attrib: + print(testcase.attrib['name'], "passed") + continue + # Otherwise, test was either skipped, errored, or failed. The testcase + # will have a child with a relevant tag - skipped, error, or failure. + # If the tag is acceptable then carry on, or otherwise assert failure. + else: + for child in testcase: + assert ( + child.tag in acceptable_outcomes + ), f"A test reports as {child.tag}, which is not accepted." + print(testcase.attrib['name'], child.tag ) From 46ad865d1f9359f761ac142bcc65ca524debf6e0 Mon Sep 17 00:00:00 2001 From: Ed Date: Thu, 27 Jul 2023 11:59:39 +0100 Subject: [PATCH 32/36] Allow out of order printing in TDM test --- test/lib_i2s/test_tdm_slave_tx16_cb.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/test/lib_i2s/test_tdm_slave_tx16_cb.py b/test/lib_i2s/test_tdm_slave_tx16_cb.py index 43dad6c..253d8b6 100644 --- a/test/lib_i2s/test_tdm_slave_tx16_cb.py +++ b/test/lib_i2s/test_tdm_slave_tx16_cb.py @@ -35,7 +35,7 @@ def test_tdm_slavetx16_cb(capfd, request, nightly, tx_offset): tester = Pyxsim.testers.PytestComparisonTester( f'{cwd}/expected/tdm_slave_tx16_cb_test.expect', regexp = True, - ordered = True + ordered = False # We are mixing sim and host prints so avoid race conditions ) with capfd.disabled(): @@ -49,7 +49,7 @@ def test_tdm_slavetx16_cb(capfd, request, nightly, tx_offset): tester = Pyxsim.testers.PytestComparisonTester( f'{cwd}/expected/tdm_slave_tx16_cb_test.expect', regexp = True, - ordered = True, + ordered = False # We are mixing sim and host prints so avoid race conditions ) Pyxsim.run_with_pyxsim(binary, From b88e93dc2b0a3edbc9fc2a85479105c4c5214421 Mon Sep 17 00:00:00 2001 From: Ed Date: Thu, 27 Jul 2023 12:00:13 +0100 Subject: [PATCH 33/36] Allow adjustable BCLK polarity in TDm --- modules/i2s/src/i2s_tdm_slave.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/modules/i2s/src/i2s_tdm_slave.c b/modules/i2s/src/i2s_tdm_slave.c index f2f9249..1373728 100644 --- a/modules/i2s/src/i2s_tdm_slave.c +++ b/modules/i2s/src/i2s_tdm_slave.c @@ -47,7 +47,7 @@ void i2s_tdm_slave_init( ctx->word_len = word_len; ctx->ch_len = ch_len; ctx->ch_per_frame = ch_per_frame; - ctx->slave_bclk_polarity = I2S_SLAVE_SAMPLE_ON_BCLK_RISING; + ctx->slave_bclk_polarity = slave_bclk_pol; ctx->tdm_post_port_init = tdm_post_port_init; ctx->fysnch_error = false; } From 1198b4350029f037078c5c70a4f58d7c3c138995 Mon Sep 17 00:00:00 2001 From: Ed Date: Thu, 27 Jul 2023 17:35:06 +0100 Subject: [PATCH 34/36] Clear up comments/docs in API following review --- modules/i2s/api/i2s_tdm_slave.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/modules/i2s/api/i2s_tdm_slave.h b/modules/i2s/api/i2s_tdm_slave.h index 1117f7f..6e180a6 100644 --- a/modules/i2s/api/i2s_tdm_slave.h +++ b/modules/i2s/api/i2s_tdm_slave.h @@ -36,7 +36,7 @@ * TDM post resource initialization event callback. * * The TDM component will call this after it first initializes the ports. - * This gives the app write the chance to make adjustments to port timing which + * This gives the app the chance to make adjustments to port timing which * are often needed when clocking above 15MHz. * * \param i2s_tdm_ctx Points to i2s_tdm_ctx_t struct allowing the resources to be @@ -73,7 +73,7 @@ typedef struct { uint32_t ch_len; uint32_t ch_per_frame; i2s_slave_bclk_polarity_t slave_bclk_polarity; - bool fysnch_error; + bool fysnch_error; /* This is set (and can be checked in tdm_post_port_init() if needed) */ void *app_data; } i2s_tdm_ctx_t; @@ -134,7 +134,7 @@ void i2s_tdm_slave_tx_16_init( * callbacks over the i2s_callback_group_t callback group to get * data from the application using this component. * - * This thread outputs assumes 1 output port, 32b word length, + * This thread assumes 1 data output port, 32b word length, * 32b channel length, and 16 channels per frame. * * The component performs I2S TDM slave so will expect the fsync and @@ -174,7 +174,7 @@ void i2s_tdm_slave_tx_16_thread( * \param p_bclk The bit clock input port. MUST be a 1b port * \param bclk A clock that will get configured for use with * the bit clock - * \param tx_offset The number of bclks from FSYNC transition to the MSB + * \param tx_offset The number of BCLKS from FSYNC transition to the MSB * of Slot 0 * \param fsync_len The length of the FSYNC in BCLKS * \param word_len The number of bits in each sample frame slot. From 70810a939f531409ee38de7999d002830fcb8980 Mon Sep 17 00:00:00 2001 From: Ed Date: Thu, 27 Jul 2023 17:39:18 +0100 Subject: [PATCH 35/36] Changelog and version bump --- CHANGELOG.rst | 6 ++++++ settings.json | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/CHANGELOG.rst b/CHANGELOG.rst index 195c850..36b95db 100644 --- a/CHANGELOG.rst +++ b/CHANGELOG.rst @@ -1,6 +1,12 @@ IO Framework change log ======================= +3.1.0 +----- + + * ADDED: TDM16 Slave Tx library + + 3.0.0 ----- diff --git a/settings.json b/settings.json index 42183eb..f45574d 100644 --- a/settings.json +++ b/settings.json @@ -1,5 +1,5 @@ { "title": "XCORE Peripheral IO Framework", "project": "fwk_io", - "version": "3.0.0" + "version": "3.1.0" } \ No newline at end of file From 6381e9157200a29677dd4e375c4199c4299ddeaf Mon Sep 17 00:00:00 2001 From: Ed Date: Tue, 8 Aug 2023 14:58:22 +0100 Subject: [PATCH 36/36] Bump mic_array v5.1.0 --- CHANGELOG.rst | 2 +- modules/mic_array | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/CHANGELOG.rst b/CHANGELOG.rst index 4715493..2cf3319 100644 --- a/CHANGELOG.rst +++ b/CHANGELOG.rst @@ -5,7 +5,7 @@ IO Framework change log ----- * ADDED: TDM16 Slave Tx library - + * CHANGE: Updated lib_mic_array to v5.1.0 3.0.1 ----- diff --git a/modules/mic_array b/modules/mic_array index c045fc2..beef6eb 160000 --- a/modules/mic_array +++ b/modules/mic_array @@ -1 +1 @@ -Subproject commit c045fc228777baccf5defd7710d029312ede4847 +Subproject commit beef6eb0640feee8c38cb5f5f98fbf3ea0f3ef87