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StructurePcd.dsc
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StructurePcd.dsc
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## @file
# @copyright
# Copyright 2019 - 2021 Intel Corporation. <BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
##
[Defines]
VPD_TOOL_GUID = 8C3D856A-9BE6-468E-850A-24F7A8D38E08
[SkuIds]
0|DEFAULT # The entry: 0|DEFAULT is reserved and always required.
[DefaultStores]
0|STANDARD # UEFI Standard default 0|STANDARD is reserved.
1|MANUFACTURING # UEFI Manufacturing default 1|MANUFACTURING is reserved.
[PcdsDynamicExVpd.common.DEFAULT]
gEfiMdeModulePkgTokenSpaceGuid.PcdNvStoreDefaultValueBuffer|*
[PcdsDynamicExHii.common.DEFAULT.STANDARD]
gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig|L"FpgaSocketConfig"|gFpgaSocketVariableGuid|0x00||NV, BS, RT
gStructPcdTokenSpaceGuid.PcdPchSetup|L"PchSetup"|gPchSetupVariableGuid|0x00||NV, BS, RT
gStructPcdTokenSpaceGuid.PcdSetup|L"Setup"|gEfiSetupVariableGuid|0x00||NV, BS, RT
gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig|L"SocketCommonRcConfig"|gEfiSocketCommonRcVariableGuid|0x00||NV, BS, RT
gStructPcdTokenSpaceGuid.PcdSocketIioConfig|L"SocketIioConfig"|gEfiSocketIioVariableGuid|0x00||NV, BS, RT
gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig|L"SocketMemoryConfig"|gEfiSocketMemoryVariableGuid|0x00||NV, BS, RT
gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig|L"SocketMpLinkConfig"|gEfiSocketMpLinkVariableGuid|0x00||NV, BS, RT
gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig|L"SocketPowerManagementConfig"|gEfiSocketPowermanagementVarGuid|0x00||NV, BS, RT
gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig|L"SocketProcessorCoreConfig"|gEfiSocketProcessorCoreVarGuid|0x00||NV, BS, RT
!if $(TARGET) == "DEBUG"
gStructPcdTokenSpaceGuid.PcdSetup.serialDebugMsgLvl|0x4
gStructPcdTokenSpaceGuid.PcdSetup.serialDebugMsgLvlTrainResults|0x8
gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.DebugPrintLevel|0xF
!else
gStructPcdTokenSpaceGuid.PcdSetup.serialDebugMsgLvl|0x0
gStructPcdTokenSpaceGuid.PcdSetup.serialDebugMsgLvlTrainResults|0x0
gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.DebugPrintLevel|0x0
!endif
gStructPcdTokenSpaceGuid.PcdEmulationDfxConfig.DfxHybridSystemLevelEmulation|0x0 # Hybrid SLE Mode
gStructPcdTokenSpaceGuid.PcdEmulationDfxConfig.DfxPmMsrTrace|0x0 # MSR Trace for PM
gStructPcdTokenSpaceGuid.PcdEmulationDfxConfig.DfxUbiosGeneration|0x0 # uBIOS Generation
gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig.FpgaSetupEnabled|0x3 # Sockets Enable Bitmap(Hex)
gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig.FpgaSocketGuid[0]|0x0 # Socket 0 BitStream
gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig.FpgaSocketGuid[1]|0x0 # Socket 1 BitStream
gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig.FpgaThermalTH1[0]|0x5a # Socket 0 Threshold 1
gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig.FpgaThermalTH1[1]|0x5a # Socket 1 Threshold 1
gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig.FpgaThermalTH2[0]|0x5d # Socket 0 Threshold 2
gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig.FpgaThermalTH2[1]|0x5d # Socket 1 Threshold 2
gStructPcdTokenSpaceGuid.PcdIeRcConfiguration.IeDidEnabled|0x1 # DRAM Init Done Enable
gStructPcdTokenSpaceGuid.PcdIeRcConfiguration.IeHeci1Enabled|0x0 # HECI-1 Enable
gStructPcdTokenSpaceGuid.PcdIeRcConfiguration.IeHeci2Enabled|0x0 # HECI-2 Enable
gStructPcdTokenSpaceGuid.PcdIeRcConfiguration.IeHeci3Enabled|0x0 # HECI-3 Enable
gStructPcdTokenSpaceGuid.PcdIeRcConfiguration.IeIderEnabled|0x0 # IDER Enable
gStructPcdTokenSpaceGuid.PcdIeRcConfiguration.IeKtEnabled|0x0 # KT Enable
gStructPcdTokenSpaceGuid.PcdIeRcConfiguration.SubsystemId|0x7270 # Subsystem ID
gStructPcdTokenSpaceGuid.PcdIeRcConfiguration.SubsystemVendorId|0x8086 # Subsystem Vendor ID
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.AmtCiraRequest|0x0
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.AmtCiraTimeout|0x0
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.AmtbxHotKeyPressed|0x0
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.AmtbxSelectionScreen|0x0
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.Amt|0x1
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.Asf|0x1
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.BiosPause|0x1 # BIOS Pause Before Booting Capability State
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.BiosReflash|0x1 # BIOS Reflash Capability State
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.BiosSetup|0x1 # BIOS Boot to Setup Capability State
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.BreakRtcEnabled|0x0 # Break RTC Configuration
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.CLINKDisableOverride|0x0
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.CoreBiosDoneEnabled|0x1 # Core Bios Done Message
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.CpuTypeEmulation|0xa
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.DelayedAuthenticationModeOverride|0x0 # Delayed Authentication Mode (DAM) Override
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.DelayedAuthenticationMode|0x0 # Delayed Authentication Mode (DAM)
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.DidInitStat|0x0 # DRAM Initialization Status
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.DisableD0I3SettingForHeci|0x0 # D0I3 Setting for HECI Disable
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.EndOfPostMessage|0x2 # END_OF_POST Message
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.HeciCommunication2|0x2 # HECI-2 Enable
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.HeciCommunication3|0x2 # HECI-3 Enable
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.HeciCommunication|0x2 # HECI-1 Enable
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.FWProgress|0x1
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.Frequency[0]|0x0
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.Frequency[1]|0x0
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.HideUnConfigureMeConfirm|0x0
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.HostResetNotification|0x1 # Host Reset Warning
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.HsioMessagingEnabled|0x0 # Enable HSIO Messaging
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.IccClkOverride|0x0
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.IccProfile|0x0
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.KtDeviceEnable|0x2 # KT Enable
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.LocalFwUpdEnabled|0x0
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MdesCapability|0x0
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeEnableHeciTraces|0x0 # Enable HECI Dump
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeFirmwareMode|0x0
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeFwDowngrade|0x0
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeGrLockEnabled|0x1 # Global Reset Lock
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeGrPromotionEnabled|0x0 # CF9 global reset promotion
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeHeci1HideInMe|0x0 # HECI-1 Hide in ME
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeHeci2HideInMe|0x0 # HECI-2 Hide in ME
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeHeci3HideInMe|0x0 # HECI-3 Hide in ME
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeHmrfpoEnableEnabled|0x0 # HMRFPO_ENABLE Message
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeHmrfpoLockEnabled|0x1 # HMRFPO_LOCK Message
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeIderEnabled|0x2 # IDEr Enable
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeImageType|0x0
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MePttEnabled|0x0 # PTT Support
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MePttSupported|0x0 # ME PTT Supported
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MePttSuppressCommandSend|0x0 # Suppress PTT Commands
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeRegionSelectEnabled|0x0 # REGION_SELECT Message
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeStateControl|0x1
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeTimeout|0x2 # ME Initialization Complete Timeout
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeType|0xee # ME Firmware Type
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MeWatchdogControlEnabled|0x1 # WATCHDOG_CONTROL Message
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MebxDebugMsg|0x0
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MebxGraphicsMode|0x0
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MebxNonUiTextMode|0x0
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MebxUiTextMode|0x0
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.MngState|0x1
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.NmCores2DisableOverride|0x0 # Cores Disable Override
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.NmCores2Disable|0x0 # Cores To Disable
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.NmHwChangeOverride|0x0 # Hardware Change Override
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.NmHwChangeStatus|0x0 # Hardware Changed
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.NmPowerMsmtOverride|0x0 # Power Measurement Override
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.NmPowerMsmtSupport|0x0 # Power Measurement
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.NmPtuLoadOverride|0x0 # PTU Load Override
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.NmPwrOptBootOverride|0x0 # Boot Mode Override
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.NmPwrOptBoot|0x0 # Boot Mode
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.PreDidMeResetEnabled|0x0 # Pre-DramInitDone ME Reset
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.RegLock|0x0
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.RemoteSessionActive|0x0
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.SecureBootExposureToFw|0x1 # BIOS Secure Boot Capability Exposure to FW State
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.Spread[0]|0x0
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.Spread[1]|0x0
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.SendDidMsg|0x1 # DRAM Init Done Enable
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.SpsAltitude|0x8000 # Altitude
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.SpsMctpBusOwner|0x0 # MCTP Bus Owner
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.SpsPsuAddress[0]|0x58 # PSU #1
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.SpsPsuAddress[1]|0x59 # PSU #2
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.SpsPsuAddress[2]|0x0 # PSU #3
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.SpsPsuAddress[3]|0x0 # PSU #4
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.USBProvision|0x1
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.UnConfigureMe|0x0
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.VproAllowed|0x1
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.WatchDogOs|0x0
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.WatchDogTimerBios|0x0
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.WatchDogTimerOs|0x0
gStructPcdTokenSpaceGuid.PcdMeRcConfiguration.WatchDog|0x0
gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.CriticalRxDqsDelayLeftEdge|0x2 # RxDqsDelay Left Edge
gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.CriticalRxDqsDelayRightEdge|0x2 # RxDqsDelay Right Edge
gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.CriticalRxVrefLeftEdge|0x2 # RxVref Left Edge
gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.CriticalRxVrefRightEdge|0x2 # RxVref Right Edge
gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.CriticalTxDqDelayLeftEdge|0x2 # TxDqDelay Left Edge
gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.CriticalTxDqDelayRightEdge|0x2 # TxDqDelay Right Edge
gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.CriticalTxVrefLeftEdge|0x2 # TxVref Left Edge
gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.CriticalTxVrefRightEdge|0x2 # TxVref Right Edge
gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.MemBootHealthCheck|0x2 # Memory Boot Health Check
gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.ResetOnCriticalError|0x1 # Reboot On Critical Failure
gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.WarningRxDqsDelayLeftEdge|0x5 # RxDqsDelay Left Edge
gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.WarningRxDqsDelayRightEdge|0x5 # RxDqsDelay Right Edge
gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.WarningRxVrefLeftEdge|0x5 # RxVref Left Edge
gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.WarningRxVrefRightEdge|0x5 # RxVref Right Edge
gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.WarningTxDqDelayLeftEdge|0x5 # TxDqDelay Left Edge
gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.WarningTxDqDelayRightEdge|0x5 # TxDqDelay Right Edge
gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.WarningTxVrefLeftEdge|0x5 # TxVref Left Edge
gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig.WarningTxVrefRightEdge|0x5 # TxVref Right Edge
gStructPcdTokenSpaceGuid.PcdPchSetup.AdrCpuThermalWdt|0x0 # CPU Thermal WDT ADR Enable
gStructPcdTokenSpaceGuid.PcdPchSetup.AdrGpioSel|0x0 # ADR GPIO
gStructPcdTokenSpaceGuid.PcdPchSetup.AdrHostPartitionReset|0x0 # Host Partition Reset ADR Enable
gStructPcdTokenSpaceGuid.PcdPchSetup.AdrMultiplierVal|0x63 # ADR timer multiplier
gStructPcdTokenSpaceGuid.PcdPchSetup.AdrOverClockingWdt|0x0 # Over-Clocking WDT ADR Enable
gStructPcdTokenSpaceGuid.PcdPchSetup.AdrPmcParityError|0x0 # PMC Parity Error ADR Enable
gStructPcdTokenSpaceGuid.PcdPchSetup.AdrSysPwrOk|0x0 # SYS_PWROK Failure ADR Enable
gStructPcdTokenSpaceGuid.PcdPchSetup.AdrTimerEn|0x0 # Enable/Disable ADR Timer
gStructPcdTokenSpaceGuid.PcdPchSetup.AdrTimerVal|0x4 # ADR timer expire time
gStructPcdTokenSpaceGuid.PcdPchSetup.AetEnableMode|0x0 # AET Enable Mode
gStructPcdTokenSpaceGuid.PcdPchSetup.Btcg|0x1 # Trunk Clock Gating (BTCG)
gStructPcdTokenSpaceGuid.PcdPchSetup.DciEn|0x0 # DCI enable (HDCIEN)
gStructPcdTokenSpaceGuid.PcdPchSetup.DeepSxMode|0x0 # DeepSx Power Policies
gStructPcdTokenSpaceGuid.PcdPchSetup.DfxHdaVcType|0x0 # Virtual Channel for HD Audio
gStructPcdTokenSpaceGuid.PcdPchSetup.DmiLinkDownHangBypass|0x0 # DMI Link Down Hang Bypass (DLDHB)
gStructPcdTokenSpaceGuid.PcdPchSetup.DwrEn_IEWDT|0x0 # IE FW Watchdog Timer
gStructPcdTokenSpaceGuid.PcdPchSetup.DwrEn_MEWDT|0x0 # ME FW Watchdog Timer
gStructPcdTokenSpaceGuid.PcdPchSetup.DwrEn_PMCGBL|0x1 # Host Reset Timeout
gStructPcdTokenSpaceGuid.PcdPchSetup.Dwr_BmcRootPort|0x5 # BMC RootPort
gStructPcdTokenSpaceGuid.PcdPchSetup.Dwr_Enable|0x0 # Dirty Warm Reset
gStructPcdTokenSpaceGuid.PcdPchSetup.Dwr_IeResetPrepDone|0x1 # IE Reset Prep Done
gStructPcdTokenSpaceGuid.PcdPchSetup.Dwr_MeResetPrepDone|0x1 # ME Reset Prep Done
gStructPcdTokenSpaceGuid.PcdPchSetup.Dwr_Stall|0x0 # Dirty Warm Reset Stall
gStructPcdTokenSpaceGuid.PcdPchSetup.EnableClockSpreadSpec|0x1 # External SSC Enable - CK420
gStructPcdTokenSpaceGuid.PcdPchSetup.EnableUsb3Pin[0]|0x0 # USB 3.0 pin #1
gStructPcdTokenSpaceGuid.PcdPchSetup.EnableUsb3Pin[1]|0x0 # USB 3.0 pin #2
gStructPcdTokenSpaceGuid.PcdPchSetup.EnableUsb3Pin[2]|0x0 # USB 3.0 pin #3
gStructPcdTokenSpaceGuid.PcdPchSetup.EnableUsb3Pin[3]|0x0 # USB 3.0 pin #4
gStructPcdTokenSpaceGuid.PcdPchSetup.EnableUsb3Pin[4]|0x0 # USB 3.0 pin #5
gStructPcdTokenSpaceGuid.PcdPchSetup.EnableUsb3Pin[5]|0x0 # USB 3.0 pin #6
gStructPcdTokenSpaceGuid.PcdPchSetup.EnableUsb3Pin[6]|0x0 # USB 3.0 pin #7
gStructPcdTokenSpaceGuid.PcdPchSetup.EnableUsb3Pin[7]|0x0 # USB 3.0 pin #8
gStructPcdTokenSpaceGuid.PcdPchSetup.EnableUsb3Pin[8]|0x0 # USB 3.0 pin #9
gStructPcdTokenSpaceGuid.PcdPchSetup.EnableUsb3Pin[9]|0x0 # USB 3.0 pin #10
gStructPcdTokenSpaceGuid.PcdPchSetup.FirmwareConfiguration|0x0 # Firmware Configuration
gStructPcdTokenSpaceGuid.PcdPchSetup.FlashLockDown|0x0 # Flash Lock-Down
gStructPcdTokenSpaceGuid.PcdPchSetup.GbeRegionInvalid|0x0 # Gbe Region Valid
gStructPcdTokenSpaceGuid.PcdPchSetup.Gp27WakeFromDeepSx|0x0 # GP27 Wake From DeepSx
gStructPcdTokenSpaceGuid.PcdPchSetup.IchPort80Route|0x0 # Port 80h Redirection
gStructPcdTokenSpaceGuid.PcdPchSetup.PchAdrEn|0x0 # Enable/Disable ADR
gStructPcdTokenSpaceGuid.PcdPchSetup.PchAllUnLock|0x0 # Unlock All PCH registers
gStructPcdTokenSpaceGuid.PcdPchSetup.PchBiosLock|0x1 # BIOS Lock
gStructPcdTokenSpaceGuid.PcdPchSetup.PchCrossThrottling|0x1 # PCH Cross Throttling
gStructPcdTokenSpaceGuid.PcdPchSetup.PchDciAutoDetect|0x0 # DCI Auto Detect Enable
gStructPcdTokenSpaceGuid.PcdPchSetup.PchEvaLockDown|0x1 # EVA registers LOCK
gStructPcdTokenSpaceGuid.PcdPchSetup.PchEvaMrom0HookEnable|0x1 # MROM 0 Hook
gStructPcdTokenSpaceGuid.PcdPchSetup.PchEvaMrom1HookEnable|0x1 # MROM 1 Hook
gStructPcdTokenSpaceGuid.PcdPchSetup.PchGpioLockDown|0x1 # GPIO Lockdown
gStructPcdTokenSpaceGuid.PcdPchSetup.PchHdAudio|0x1 # Azalia
gStructPcdTokenSpaceGuid.PcdPchSetup.PchHdAudioCodecSelect|0x0 # HDA-Link Codec Select
gStructPcdTokenSpaceGuid.PcdPchSetup.PchHdAudioPme|0x0 # Azalia PME Enable
gStructPcdTokenSpaceGuid.PcdPchSetup.PchIoApic24119Entries|0x1 # IO-APIC 24-119 RTE
gStructPcdTokenSpaceGuid.PcdPchSetup.PchLanK1Off|0x0 # K1 off
gStructPcdTokenSpaceGuid.PcdPchSetup.PchP2sbDevReveal|0x0 # Reveal PCH P2SB device
gStructPcdTokenSpaceGuid.PcdPchSetup.PchP2sbUnlock|0x0 # Unlock PCH P2SB
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[0]|0x0 # Force LTR Override PCIE1
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[1]|0x0 # Force LTR Override PCIE2
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[2]|0x0 # Force LTR Override PCIE3
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[3]|0x0 # Force LTR Override PCIE4
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[4]|0x0 # Force LTR Override PCIE5
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[5]|0x0 # Force LTR Override PCIE6
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[6]|0x0 # Force LTR Override PCIE7
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[7]|0x0 # Force LTR Override PCIE8
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[8]|0x0 # Force LTR Override PCIE9
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[9]|0x0 # Force LTR Override PCIE10
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[10]|0x0 # Force LTR Override PCIE11
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[11]|0x0 # Force LTR Override PCIE12
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[12]|0x0 # Force LTR Override PCIE13
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[13]|0x0 # Force LTR Override PCIE14
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[14]|0x0 # Force LTR Override PCIE15
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[15]|0x0 # Force LTR Override PCIE16
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[16]|0x0 # Force LTR Override PCIE17
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[17]|0x0 # Force LTR Override PCIE18
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[18]|0x0 # Force LTR Override PCIE19
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieForceLtrOverride[19]|0x0 # Force LTR Override PCIE20
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieGlobalAspm|0x2 # PCI-E ASPM Support (Global)
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[0]|0x1 # PCH PCIE1 LTR
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[1]|0x1 # PCH PCIE2 LTR
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[2]|0x1 # PCH PCIE3 LTR
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[3]|0x1 # PCH PCIE4 LTR
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[4]|0x1 # PCH PCIE5 LTR
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[5]|0x1 # PCH PCIE6 LTR
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[6]|0x1 # PCH PCIE7 LTR
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[7]|0x1 # PCH PCIE8 LTR
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[8]|0x1 # PCH PCIE9 LTR
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[9]|0x1 # PCH PCIE10 LTR
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[10]|0x1 # PCH PCIE11 LTR
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[11]|0x1 # PCH PCIE12 LTR
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[12]|0x1 # PCH PCIE13 LTR
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[13]|0x1 # PCH PCIE14 LTR
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[14]|0x1 # PCH PCIE15 LTR
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[15]|0x1 # PCH PCIE16 LTR
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[16]|0x1 # PCH PCIE17 LTR
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[17]|0x1 # PCH PCIE18 LTR
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[18]|0x1 # PCH PCIE19 LTR
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieLtrEnable[19]|0x1 # PCH PCIE20 LTR
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[0]|0x2 # Non Snoop Latency Override
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[1]|0x2 # Non Snoop Latency Override
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[2]|0x2 # Non Snoop Latency Override
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[3]|0x2 # Non Snoop Latency Override
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[4]|0x2 # Non Snoop Latency Override
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[5]|0x2 # Non Snoop Latency Override
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[6]|0x2 # Non Snoop Latency Override
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[7]|0x2 # Non Snoop Latency Override
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[8]|0x2 # Non Snoop Latency Override
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[9]|0x2 # Non Snoop Latency Override
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[10]|0x2 # Non Snoop Latency Override
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[11]|0x2 # Non Snoop Latency Override
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[12]|0x2 # Non Snoop Latency Override
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[13]|0x2 # Non Snoop Latency Override
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[14]|0x2 # Non Snoop Latency Override
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[15]|0x2 # Non Snoop Latency Override
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[16]|0x2 # Non Snoop Latency Override
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[17]|0x2 # Non Snoop Latency Override
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[18]|0x2 # Non Snoop Latency Override
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMode[19]|0x2 # Non Snoop Latency Override
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[0]|0x2 # Non Snoop Latency Multiplier
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[1]|0x2 # Non Snoop Latency Multiplier
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[2]|0x2 # Non Snoop Latency Multiplier
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[3]|0x2 # Non Snoop Latency Multiplier
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[4]|0x2 # Non Snoop Latency Multiplier
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[5]|0x2 # Non Snoop Latency Multiplier
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[6]|0x2 # Non Snoop Latency Multiplier
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[7]|0x2 # Non Snoop Latency Multiplier
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[8]|0x2 # Non Snoop Latency Multiplier
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[9]|0x2 # Non Snoop Latency Multiplier
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[10]|0x2 # Non Snoop Latency Multiplier
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[11]|0x2 # Non Snoop Latency Multiplier
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[12]|0x2 # Non Snoop Latency Multiplier
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[13]|0x2 # Non Snoop Latency Multiplier
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[14]|0x2 # Non Snoop Latency Multiplier
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[15]|0x2 # Non Snoop Latency Multiplier
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[16]|0x2 # Non Snoop Latency Multiplier
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[17]|0x2 # Non Snoop Latency Multiplier
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[18]|0x2 # Non Snoop Latency Multiplier
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideMultiplier[19]|0x2 # Non Snoop Latency Multiplier
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[0]|0x3c # Non Snoop Latency Value
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[1]|0x3c # Non Snoop Latency Value
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[2]|0x3c # Non Snoop Latency Value
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[3]|0x3c # Non Snoop Latency Value
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[4]|0x3c # Non Snoop Latency Value
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[5]|0x3c # Non Snoop Latency Value
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[6]|0x3c # Non Snoop Latency Value
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[7]|0x3c # Non Snoop Latency Value
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[8]|0x3c # Non Snoop Latency Value
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[9]|0x3c # Non Snoop Latency Value
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[10]|0x3c # Non Snoop Latency Value
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[11]|0x3c # Non Snoop Latency Value
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[12]|0x3c # Non Snoop Latency Value
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[13]|0x3c # Non Snoop Latency Value
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[14]|0x3c # Non Snoop Latency Value
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[15]|0x3c # Non Snoop Latency Value
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[16]|0x3c # Non Snoop Latency Value
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[17]|0x3c # Non Snoop Latency Value
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[18]|0x3c # Non Snoop Latency Value
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieNonSnoopLatencyOverrideValue[19]|0x3c # Non Snoop Latency Value
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[0]|0x2 # Snoop Latency Override
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[1]|0x2 # Snoop Latency Override
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[2]|0x2 # Snoop Latency Override
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[3]|0x2 # Snoop Latency Override
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[4]|0x2 # Snoop Latency Override
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[5]|0x2 # Snoop Latency Override
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[6]|0x2 # Snoop Latency Override
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[7]|0x2 # Snoop Latency Override
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[8]|0x2 # Snoop Latency Override
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[9]|0x2 # Snoop Latency Override
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[10]|0x2 # Snoop Latency Override
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[11]|0x2 # Snoop Latency Override
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[12]|0x2 # Snoop Latency Override
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[13]|0x2 # Snoop Latency Override
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[14]|0x2 # Snoop Latency Override
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[15]|0x2 # Snoop Latency Override
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[16]|0x2 # Snoop Latency Override
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[17]|0x2 # Snoop Latency Override
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[18]|0x2 # Snoop Latency Override
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMode[19]|0x2 # Snoop Latency Override
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier[0]|0x2 # Snoop Latency Multiplier
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier[1]|0x2 # Snoop Latency Multiplier
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier[2]|0x2 # Snoop Latency Multiplier
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier[3]|0x2 # Snoop Latency Multiplier
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier[4]|0x2 # Snoop Latency Multiplier
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier[5]|0x2 # Snoop Latency Multiplier
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier[6]|0x2 # Snoop Latency Multiplier
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier[7]|0x2 # Snoop Latency Multiplier
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier[8]|0x2 # Snoop Latency Multiplier
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier[9]|0x2 # Snoop Latency Multiplier
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier[10]|0x2 # Snoop Latency Multiplier
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier[11]|0x2 # Snoop Latency Multiplier
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier[12]|0x2 # Snoop Latency Multiplier
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier[13]|0x2 # Snoop Latency Multiplier
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier[14]|0x2 # Snoop Latency Multiplier
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier[15]|0x2 # Snoop Latency Multiplier
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier[16]|0x2 # Snoop Latency Multiplier
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier[17]|0x2 # Snoop Latency Multiplier
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier[18]|0x2 # Snoop Latency Multiplier
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideMultiplier[19]|0x2 # Snoop Latency Multiplier
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[0]|0x3c # Snoop Latency Value
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[1]|0x3c # Snoop Latency Value
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[2]|0x3c # Snoop Latency Value
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[3]|0x3c # Snoop Latency Value
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[4]|0x3c # Snoop Latency Value
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[5]|0x3c # Snoop Latency Value
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[6]|0x3c # Snoop Latency Value
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[7]|0x3c # Snoop Latency Value
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[8]|0x3c # Snoop Latency Value
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[9]|0x3c # Snoop Latency Value
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[10]|0x3c # Snoop Latency Value
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[11]|0x3c # Snoop Latency Value
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[12]|0x3c # Snoop Latency Value
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[13]|0x3c # Snoop Latency Value
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[14]|0x3c # Snoop Latency Value
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[15]|0x3c # Snoop Latency Value
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[16]|0x3c # Snoop Latency Value
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[17]|0x3c # Snoop Latency Value
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[18]|0x3c # Snoop Latency Value
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieSnoopLatencyOverrideValue[19]|0x3c # Snoop Latency Value
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieUX16CompletionTimeout|0x0 # CTO for Uplink x16
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieUX16MaxPayloadSize|0x2 # MPL for Uplink x16
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieUX8CompletionTimeout|0x0 # CTO for Uplink x8
gStructPcdTokenSpaceGuid.PcdPchSetup.PchPcieUX8MaxPayloadSize|0x2 # MPL for Uplink x8
gStructPcdTokenSpaceGuid.PcdPchSetup.PchRtcLock|0x1 # RTC Lock
gStructPcdTokenSpaceGuid.PcdPchSetup.PchSSataLtrConfigLock|0x1 # sSATA LTR Lock
gStructPcdTokenSpaceGuid.PcdPchSetup.PchSSataLtrEnable|0x1 # PCH sSATA LTR
gStructPcdTokenSpaceGuid.PcdPchSetup.PchSSataLtrOverride|0x0 # sSATA LTR Override
gStructPcdTokenSpaceGuid.PcdPchSetup.PchSSataSnoopLatencyOverrideMultiplier|0x2 # sSATA Snoop Latency Multiplier
gStructPcdTokenSpaceGuid.PcdPchSetup.PchSSataSnoopLatencyOverrideValue|0x28 # sSATA Snoop Latency Value
gStructPcdTokenSpaceGuid.PcdPchSetup.PchSata|0x1 # SATA Controller
gStructPcdTokenSpaceGuid.PcdPchSetup.PchSataLtrConfigLock|0x1 # SATA LTR Lock
gStructPcdTokenSpaceGuid.PcdPchSetup.PchSataLtrEnable|0x1 # PCH SATA LTR
gStructPcdTokenSpaceGuid.PcdPchSetup.PchSataLtrOverride|0x0 # SATA LTR Override
gStructPcdTokenSpaceGuid.PcdPchSetup.PchSataSnoopLatencyOverrideMultiplier|0x2 # SATA Snoop Latency Multiplier
gStructPcdTokenSpaceGuid.PcdPchSetup.PchSataSnoopLatencyOverrideValue|0x28 # SATA Snoop Latency Value
gStructPcdTokenSpaceGuid.PcdPchSetup.PchSirqMode|0x0 # Serial IRQ Mode
gStructPcdTokenSpaceGuid.PcdPchSetup.PchSlpLanLowDc|0x1 # SLP_LAN# Low on DC Power
gStructPcdTokenSpaceGuid.PcdPchSetup.PchThermalUnlock|0x0 # Unlock Thermal Registers
gStructPcdTokenSpaceGuid.PcdPchSetup.PchTraceHubHide|0x1 # Hide Trace Hub
gStructPcdTokenSpaceGuid.PcdPchSetup.PchTraceHubMemReg0Size|0x0 # MemRegion 0 Buffer Size
gStructPcdTokenSpaceGuid.PcdPchSetup.PchTraceHubMemReg1Size|0x0 # MemRegion 1 Buffer Size
gStructPcdTokenSpaceGuid.PcdPchSetup.PchTraceHubMode|0x2 # TraceHub Enable Mode
gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbDegradeBar|0x0 # Place XHCI BAR below 4GB
gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[0]|0x1 # USB HS Physical Connector #0 Disable
gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[1]|0x1 # USB HS Physical Connector #1 Disable
gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[2]|0x1 # USB HS Physical Connector #2 Disable
gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[3]|0x1 # USB HS Physical Connector #3 Disable
gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[4]|0x1 # USB HS Physical Connector #4 Disable
gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[5]|0x1 # USB HS Physical Connector #5 Disable
gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[6]|0x1 # USB HS Physical Connector #6 Disable
gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[7]|0x1 # USB HS Physical Connector #7 Disable
gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[8]|0x1 # USB HS Physical Connector #8 Disable
gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[9]|0x1 # USB HS Physical Connector #9 Disable
gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[10]|0x1 # USB HS Physical Connector #10 Disable
gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[11]|0x1 # USB HS Physical Connector #11 Disable
gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[12]|0x1 # USB HS Physical Connector #12 Disable
gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbHsPort[13]|0x1 # USB HS Physical Connector #13 Disable
gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbManualMode|0x0 # XHCI Manual Mode
gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbPerPortCtl|0x0 # USB Per-Connector Disable
gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbSsPort[0]|0x1 # USB SS Physical Connector #0 Disable
gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbSsPort[1]|0x1 # USB SS Physical Connector #1 Disable
gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbSsPort[2]|0x1 # USB SS Physical Connector #2 Disable
gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbSsPort[3]|0x1 # USB SS Physical Connector #3 Disable
gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbSsPort[4]|0x1 # USB SS Physical Connector #4 Disable
gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbSsPort[5]|0x1 # USB SS Physical Connector #5 Disable
gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbSsPort[6]|0x1 # USB SS Physical Connector #6 Disable
gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbSsPort[7]|0x1 # USB SS Physical Connector #7 Disable
gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbSsPort[8]|0x1 # USB SS Physical Connector #8 Disable
gStructPcdTokenSpaceGuid.PcdPchSetup.PchUsbSsPort[9]|0x1 # USB SS Physical Connector #9 Disable
gStructPcdTokenSpaceGuid.PcdPchSetup.PchWakeOnLan|0x0 # Wake on LAN
gStructPcdTokenSpaceGuid.PcdPchSetup.PchsSata|0x1 # sSATA Controller
gStructPcdTokenSpaceGuid.PcdPchSetup.PciDelayOptimizationEcr|0x0 # PCI Delay Optimization
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieComplianceTestMode|0x0 # Compliance Test Mode
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieDmiExtSync|0x0 # DMI Link Extended Synch Control
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieDmiStopAndScreamEnable|0x0 # Stop and Scream
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[0]|0x6 # PCIE1 Cm
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[1]|0x6 # PCIE2 Cm
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[2]|0x6 # PCIE3 Cm
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[3]|0x6 # PCIE4 Cm
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[4]|0x6 # PCIE5 Cm
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[5]|0x6 # PCIE6 Cm
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[6]|0x6 # PCIE7 Cm
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[7]|0x6 # PCIE8 Cm
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[8]|0x6 # PCIE9 Cm
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[9]|0x6 # PCIE10 Cm
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[10]|0x6 # PCIE11 Cm
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[11]|0x6 # PCIE12 Cm
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[12]|0x6 # PCIE13 Cm
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[13]|0x6 # PCIE14 Cm
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[14]|0x6 # PCIE15 Cm
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[15]|0x6 # PCIE16 Cm
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[16]|0x6 # PCIE17 Cm
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[17]|0x6 # PCIE18 Cm
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[18]|0x6 # PCIE19 Cm
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCm[19]|0x6 # PCIE20 Cm
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[0]|0x6 # PCIE1 Cp
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[1]|0x6 # PCIE2 Cp
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[2]|0x6 # PCIE3 Cp
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[3]|0x6 # PCIE4 Cp
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[4]|0x6 # PCIE5 Cp
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[5]|0x6 # PCIE6 Cp
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[6]|0x6 # PCIE7 Cp
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[7]|0x6 # PCIE8 Cp
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[8]|0x6 # PCIE9 Cp
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[9]|0x6 # PCIE10 Cp
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[10]|0x6 # PCIE11 Cp
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[11]|0x6 # PCIE12 Cp
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[12]|0x6 # PCIE13 Cp
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[13]|0x6 # PCIE14 Cp
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[14]|0x6 # PCIE15 Cp
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[15]|0x6 # PCIE16 Cp
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[16]|0x6 # PCIE17 Cp
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[17]|0x6 # PCIE18 Cp
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[18]|0x6 # PCIE19 Cp
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieLaneCp[19]|0x6 # PCIE20 Cp
gStructPcdTokenSpaceGuid.PcdPchSetup.PciePllSsc|0xfe # Pcie Pll SSC
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[0]|0x1 # ACS
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[1]|0x1 # ACS
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[2]|0x1 # ACS
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[3]|0x1 # ACS
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[4]|0x1 # ACS
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[5]|0x1 # ACS
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[6]|0x1 # ACS
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[7]|0x1 # ACS
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[8]|0x1 # ACS
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[9]|0x1 # ACS
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[10]|0x1 # ACS
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[11]|0x1 # ACS
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[12]|0x1 # ACS
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[13]|0x1 # ACS
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[14]|0x1 # ACS
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[15]|0x1 # ACS
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[16]|0x1 # ACS
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[17]|0x1 # ACS
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[18]|0x1 # ACS
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortACS[19]|0x1 # ACS
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[0]|0x1 # Advanced Error Reporting
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[1]|0x1 # Advanced Error Reporting
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[2]|0x1 # Advanced Error Reporting
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[3]|0x1 # Advanced Error Reporting
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[4]|0x1 # Advanced Error Reporting
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[5]|0x1 # Advanced Error Reporting
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[6]|0x1 # Advanced Error Reporting
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[7]|0x1 # Advanced Error Reporting
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[8]|0x1 # Advanced Error Reporting
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[9]|0x1 # Advanced Error Reporting
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[10]|0x1 # Advanced Error Reporting
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[11]|0x1 # Advanced Error Reporting
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[12]|0x1 # Advanced Error Reporting
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[13]|0x1 # Advanced Error Reporting
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[14]|0x1 # Advanced Error Reporting
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[15]|0x1 # Advanced Error Reporting
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[16]|0x1 # Advanced Error Reporting
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[17]|0x1 # Advanced Error Reporting
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[18]|0x1 # Advanced Error Reporting
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAER[19]|0x1 # Advanced Error Reporting
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[0]|0x0 # PCIE ASPM
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[1]|0x0 # PCIE ASPM
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[2]|0x0 # PCIE ASPM
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[3]|0x0 # PCIE ASPM
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[4]|0x0 # PCIE ASPM
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[5]|0x0 # PCIE ASPM
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[6]|0x0 # PCIE ASPM
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[7]|0x0 # PCIE ASPM
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[8]|0x0 # PCIE ASPM
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[9]|0x0 # PCIE ASPM
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[10]|0x0 # PCIE ASPM
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[11]|0x0 # PCIE ASPM
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[12]|0x0 # PCIE ASPM
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[13]|0x0 # PCIE ASPM
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[14]|0x0 # PCIE ASPM
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[15]|0x0 # PCIE ASPM
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[16]|0x0 # PCIE ASPM
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[17]|0x0 # PCIE ASPM
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[18]|0x0 # PCIE ASPM
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortAspm[19]|0x0 # PCIE ASPM
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[0]|0x0 # CER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[1]|0x0 # CER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[2]|0x0 # CER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[3]|0x0 # CER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[4]|0x0 # CER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[5]|0x0 # CER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[6]|0x0 # CER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[7]|0x0 # CER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[8]|0x0 # CER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[9]|0x0 # CER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[10]|0x0 # CER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[11]|0x0 # CER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[12]|0x0 # CER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[13]|0x0 # CER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[14]|0x0 # CER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[15]|0x0 # CER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[16]|0x0 # CER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[17]|0x0 # CER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[18]|0x0 # CER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCEE[19]|0x0 # CER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[0]|0x0 # Compl. Timeout
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[1]|0x0 # Compl. Timeout
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[2]|0x0 # Compl. Timeout
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[3]|0x0 # Compl. Timeout
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[4]|0x0 # Compl. Timeout
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[5]|0x0 # Compl. Timeout
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[6]|0x0 # Compl. Timeout
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[7]|0x0 # Compl. Timeout
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[8]|0x0 # Compl. Timeout
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[9]|0x0 # Compl. Timeout
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[10]|0x0 # Compl. Timeout
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[11]|0x0 # Compl. Timeout
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[12]|0x0 # Compl. Timeout
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[13]|0x0 # Compl. Timeout
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[14]|0x0 # Compl. Timeout
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[15]|0x0 # Compl. Timeout
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[16]|0x0 # Compl. Timeout
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[17]|0x0 # Compl. Timeout
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[18]|0x0 # Compl. Timeout
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortCompletionTimeout[19]|0x0 # Compl. Timeout
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[0]|0x1 # PCI Express Root Port 1
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[1]|0x1 # PCI Express Root Port 2
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[2]|0x1 # PCI Express Root Port 3
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[3]|0x1 # PCI Express Root Port 4
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[4]|0x1 # PCI Express Root Port 5
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[5]|0x1 # PCI Express Root Port 6
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[6]|0x1 # PCI Express Root Port 7
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[7]|0x1 # PCI Express Root Port 8
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[8]|0x1 # PCI Express Root Port 9
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[9]|0x1 # PCI Express Root Port 10
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[10]|0x1 # PCI Express Root Port 11
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[11]|0x1 # PCI Express Root Port 12
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[12]|0x1 # PCI Express Root Port 13
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[13]|0x1 # PCI Express Root Port 14
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[14]|0x1 # PCI Express Root Port 15
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[15]|0x1 # PCI Express Root Port 16
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[16]|0x1 # PCI Express Root Port 17
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[17]|0x1 # PCI Express Root Port 18
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[18]|0x1 # PCI Express Root Port 19
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEn[19]|0x1 # PCI Express Root Port 20
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[0]|0x1 # Gen3 Eq Phase3 Method
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[1]|0x1 # Gen3 Eq Phase3 Method
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[2]|0x1 # Gen3 Eq Phase3 Method
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[3]|0x1 # Gen3 Eq Phase3 Method
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[4]|0x1 # Gen3 Eq Phase3 Method
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[5]|0x1 # Gen3 Eq Phase3 Method
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[6]|0x1 # Gen3 Eq Phase3 Method
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[7]|0x1 # Gen3 Eq Phase3 Method
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[8]|0x1 # Gen3 Eq Phase3 Method
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[9]|0x1 # Gen3 Eq Phase3 Method
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[10]|0x1 # Gen3 Eq Phase3 Method
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[11]|0x1 # Gen3 Eq Phase3 Method
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[12]|0x1 # Gen3 Eq Phase3 Method
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[13]|0x1 # Gen3 Eq Phase3 Method
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[14]|0x1 # Gen3 Eq Phase3 Method
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[15]|0x1 # Gen3 Eq Phase3 Method
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[16]|0x1 # Gen3 Eq Phase3 Method
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[17]|0x1 # Gen3 Eq Phase3 Method
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[18]|0x1 # Gen3 Eq Phase3 Method
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortEqPh3Method[19]|0x1 # Gen3 Eq Phase3 Method
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[0]|0x0 # FER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[1]|0x0 # FER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[2]|0x0 # FER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[3]|0x0 # FER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[4]|0x0 # FER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[5]|0x0 # FER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[6]|0x0 # FER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[7]|0x0 # FER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[8]|0x0 # FER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[9]|0x0 # FER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[10]|0x0 # FER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[11]|0x0 # FER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[12]|0x0 # FER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[13]|0x0 # FER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[14]|0x0 # FER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[15]|0x0 # FER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[16]|0x0 # FER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[17]|0x0 # FER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[18]|0x0 # FER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFEE[19]|0x0 # FER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortFunctionSwapping|0x1 # PCIe Root Port Function Swapping
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[0]|0x0 # Hot Plug
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[1]|0x0 # Hot Plug
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[2]|0x0 # Hot Plug
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[3]|0x0 # Hot Plug
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[4]|0x0 # Hot Plug
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[5]|0x0 # Hot Plug
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[6]|0x0 # Hot Plug
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[7]|0x0 # Hot Plug
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[8]|0x0 # Hot Plug
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[9]|0x0 # Hot Plug
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[10]|0x0 # Hot Plug
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[11]|0x0 # Hot Plug
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[12]|0x0 # Hot Plug
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[13]|0x0 # Hot Plug
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[14]|0x0 # Hot Plug
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[15]|0x0 # Hot Plug
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[16]|0x0 # Hot Plug
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[17]|0x0 # Hot Plug
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[18]|0x0 # Hot Plug
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortHPE[19]|0x0 # Hot Plug
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[0]|0x3 # L1 Substates
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[1]|0x3 # L1 Substates
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[2]|0x3 # L1 Substates
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[3]|0x3 # L1 Substates
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[4]|0x3 # L1 Substates
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[5]|0x3 # L1 Substates
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[6]|0x3 # L1 Substates
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[7]|0x3 # L1 Substates
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[8]|0x3 # L1 Substates
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[9]|0x3 # L1 Substates
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[10]|0x3 # L1 Substates
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[11]|0x3 # L1 Substates
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[12]|0x3 # L1 Substates
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[13]|0x3 # L1 Substates
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[14]|0x3 # L1 Substates
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[15]|0x3 # L1 Substates
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[16]|0x3 # L1 Substates
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[17]|0x3 # L1 Substates
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[18]|0x3 # L1 Substates
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortL1SubStates[19]|0x3 # L1 Substates
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[0]|0x1 # Max Payload Size
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[1]|0x1 # Max Payload Size
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[2]|0x1 # Max Payload Size
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[3]|0x1 # Max Payload Size
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[4]|0x1 # Max Payload Size
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[5]|0x1 # Max Payload Size
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[6]|0x1 # Max Payload Size
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[7]|0x1 # Max Payload Size
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[8]|0x1 # Max Payload Size
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[9]|0x1 # Max Payload Size
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[10]|0x1 # Max Payload Size
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[11]|0x1 # Max Payload Size
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[12]|0x1 # Max Payload Size
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[13]|0x1 # Max Payload Size
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[14]|0x1 # Max Payload Size
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[15]|0x1 # Max Payload Size
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[16]|0x1 # Max Payload Size
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[17]|0x1 # Max Payload Size
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[18]|0x1 # Max Payload Size
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxPayLoadSize[19]|0x1 # Max Payload Size
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortMaxReadRequestSize|0x5 # Max Read Request Size
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[0]|0x0 # NFER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[1]|0x0 # NFER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[2]|0x0 # NFER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[3]|0x0 # NFER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[4]|0x0 # NFER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[5]|0x0 # NFER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[6]|0x0 # NFER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[7]|0x0 # NFER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[8]|0x0 # NFER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[9]|0x0 # NFER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[10]|0x0 # NFER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[11]|0x0 # NFER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[12]|0x0 # NFER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[13]|0x0 # NFER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[14]|0x0 # NFER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[15]|0x0 # NFER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[16]|0x0 # NFER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[17]|0x0 # NFER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[18]|0x0 # NFER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortNFE[19]|0x0 # NFER
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[0]|0x0 # PME SCI
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[1]|0x0 # PME SCI
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[2]|0x0 # PME SCI
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[3]|0x0 # PME SCI
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[4]|0x0 # PME SCI
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[5]|0x0 # PME SCI
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[6]|0x0 # PME SCI
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[7]|0x0 # PME SCI
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[8]|0x0 # PME SCI
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[9]|0x0 # PME SCI
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[10]|0x0 # PME SCI
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[11]|0x0 # PME SCI
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[12]|0x0 # PME SCI
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[13]|0x0 # PME SCI
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[14]|0x0 # PME SCI
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[15]|0x0 # PME SCI
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[16]|0x0 # PME SCI
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[17]|0x0 # PME SCI
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[18]|0x0 # PME SCI
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortPMCE[19]|0x0 # PME SCI
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSBDE|0x0 # Subtractive Decode
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[0]|0x0 # SECE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[1]|0x0 # SECE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[2]|0x0 # SECE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[3]|0x0 # SECE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[4]|0x0 # SECE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[5]|0x0 # SECE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[6]|0x0 # SECE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[7]|0x0 # SECE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[8]|0x0 # SECE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[9]|0x0 # SECE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[10]|0x0 # SECE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[11]|0x0 # SECE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[12]|0x0 # SECE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[13]|0x0 # SECE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[14]|0x0 # SECE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[15]|0x0 # SECE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[16]|0x0 # SECE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[17]|0x0 # SECE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[18]|0x0 # SECE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSCE[19]|0x0 # SECE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[0]|0x0 # SEFE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[1]|0x0 # SEFE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[2]|0x0 # SEFE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[3]|0x0 # SEFE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[4]|0x0 # SEFE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[5]|0x0 # SEFE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[6]|0x0 # SEFE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[7]|0x0 # SEFE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[8]|0x0 # SEFE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[9]|0x0 # SEFE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[10]|0x0 # SEFE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[11]|0x0 # SEFE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[12]|0x0 # SEFE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[13]|0x0 # SEFE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[14]|0x0 # SEFE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[15]|0x0 # SEFE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[16]|0x0 # SEFE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[17]|0x0 # SEFE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[18]|0x0 # SEFE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSFE[19]|0x0 # SEFE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[0]|0x0 # SENFE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[1]|0x0 # SENFE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[2]|0x0 # SENFE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[3]|0x0 # SENFE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[4]|0x0 # SENFE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[5]|0x0 # SENFE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[6]|0x0 # SENFE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[7]|0x0 # SENFE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[8]|0x0 # SENFE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[9]|0x0 # SENFE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[10]|0x0 # SENFE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[11]|0x0 # SENFE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[12]|0x0 # SENFE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[13]|0x0 # SENFE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[14]|0x0 # SENFE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[15]|0x0 # SENFE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[16]|0x0 # SENFE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[17]|0x0 # SENFE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[18]|0x0 # SENFE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSNE[19]|0x0 # SENFE
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[0]|0x0 # PCIe Speed
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[1]|0x0 # PCIe Speed
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[2]|0x0 # PCIe Speed
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[3]|0x0 # PCIe Speed
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[4]|0x0 # PCIe Speed
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[5]|0x0 # PCIe Speed
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[6]|0x0 # PCIe Speed
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[7]|0x0 # PCIe Speed
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[8]|0x0 # PCIe Speed
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[9]|0x0 # PCIe Speed
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[10]|0x0 # PCIe Speed
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[11]|0x0 # PCIe Speed
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[12]|0x0 # PCIe Speed
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[13]|0x0 # PCIe Speed
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[14]|0x0 # PCIe Speed
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[15]|0x0 # PCIe Speed
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[16]|0x0 # PCIe Speed
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[17]|0x0 # PCIe Speed
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[18]|0x0 # PCIe Speed
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortSpeed[19]|0x0 # PCIe Speed
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[0]|0x0 # URR
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[1]|0x0 # URR
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[2]|0x0 # URR
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[3]|0x0 # URR
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[4]|0x0 # URR
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[5]|0x0 # URR
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[6]|0x0 # URR
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[7]|0x0 # URR
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[8]|0x0 # URR
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[9]|0x0 # URR
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[10]|0x0 # URR
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[11]|0x0 # URR
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[12]|0x0 # URR
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[13]|0x0 # URR
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[14]|0x0 # URR
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[15]|0x0 # URR
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[16]|0x0 # URR
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[17]|0x0 # URR
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[18]|0x0 # URR
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieRootPortURE[19]|0x0 # URR
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSBDEPort|0x0 # Subtractive Decode Port#
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCm[0]|0x6 # Coeff0 Cm
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCm[1]|0x4 # Coeff1 Cm
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCm[2]|0x8 # Coeff2 Cm
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCm[3]|0x2 # Coeff3 Cm
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCm[4]|0xa # Coeff4 Cm
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCp[0]|0x2 # Coeff0 Cp
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCp[1]|0x2 # Coeff1 Cp
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCp[2]|0x2 # Coeff2 Cp
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCp[3]|0x2 # Coeff3 Cp
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqCoeffCp[4]|0x2 # Coeff4 Cp
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieSwEqOverride|0x0 # Override SW/HW EQ settings
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[0]|0x0 # PCIE Lane Topology
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[1]|0x0 # PCIE Lane Topology
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[2]|0x0 # PCIE Lane Topology
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[3]|0x0 # PCIE Lane Topology
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[4]|0x0 # PCIE Lane Topology
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[5]|0x0 # PCIE Lane Topology
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[6]|0x0 # PCIE Lane Topology
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[7]|0x0 # PCIE Lane Topology
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[8]|0x0 # PCIE Lane Topology
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[9]|0x0 # PCIE Lane Topology
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[10]|0x0 # PCIE Lane Topology
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[11]|0x0 # PCIE Lane Topology
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[12]|0x0 # PCIE Lane Topology
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[13]|0x0 # PCIE Lane Topology
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[14]|0x0 # PCIE Lane Topology
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[15]|0x0 # PCIE Lane Topology
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[16]|0x0 # PCIE Lane Topology
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[17]|0x0 # PCIE Lane Topology
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[18]|0x0 # PCIE Lane Topology
gStructPcdTokenSpaceGuid.PcdPchSetup.PcieTopology[19]|0x0 # PCIE Lane Topology
gStructPcdTokenSpaceGuid.PcdPchSetup.PmcReadDisable|0x1 # PMC Read Disable
gStructPcdTokenSpaceGuid.PcdPchSetup.PxDevSlp[2]|0x0 # SATA Port 2 DevSlp
gStructPcdTokenSpaceGuid.PcdPchSetup.RstPcieStorageRemap[0]|0x0 # NVRAM CYCLE ROUTER 0 ENABLE
gStructPcdTokenSpaceGuid.PcdPchSetup.RstPcieStorageRemap[1]|0x0 # NVRAM CYCLE ROUTER 1 ENABLE
gStructPcdTokenSpaceGuid.PcdPchSetup.RstPcieStorageRemap[2]|0x0 # NVRAM CYCLE ROUTER 2 ENABLE
gStructPcdTokenSpaceGuid.PcdPchSetup.RstPcieStorageRemapPort[0]|0x0 # NVRAM CR0 PCIE Root Port Number
gStructPcdTokenSpaceGuid.PcdPchSetup.RstPcieStorageRemapPort[1]|0x0 # NVRAM CR1 PCIE Root Port Number
gStructPcdTokenSpaceGuid.PcdPchSetup.RstPcieStorageRemapPort[2]|0x0 # NVRAM CR2 PCIE Root Port Number
gStructPcdTokenSpaceGuid.PcdPchSetup.SataAlternateId|0x0 # Alternate Device ID on RAID
gStructPcdTokenSpaceGuid.PcdPchSetup.SataExternal[0]|0x0 # Configure as eSATA
gStructPcdTokenSpaceGuid.PcdPchSetup.SataExternal[1]|0x0 # Configure as eSATA
gStructPcdTokenSpaceGuid.PcdPchSetup.SataExternal[2]|0x0 # Configure as eSATA
gStructPcdTokenSpaceGuid.PcdPchSetup.SataExternal[3]|0x0 # Configure as eSATA
gStructPcdTokenSpaceGuid.PcdPchSetup.SataExternal[4]|0x0 # Configure as eSATA
gStructPcdTokenSpaceGuid.PcdPchSetup.SataExternal[5]|0x0 # Configure as eSATA
gStructPcdTokenSpaceGuid.PcdPchSetup.SataExternal[6]|0x0 # Configure as eSATA
gStructPcdTokenSpaceGuid.PcdPchSetup.SataExternal[7]|0x0 # Configure as eSATA
gStructPcdTokenSpaceGuid.PcdPchSetup.SataHddlk|0x1 # SATA HDD Unlock
gStructPcdTokenSpaceGuid.PcdPchSetup.SataHotPlug[0]|0x0 # Hot Plug
gStructPcdTokenSpaceGuid.PcdPchSetup.SataHotPlug[1]|0x0 # Hot Plug
gStructPcdTokenSpaceGuid.PcdPchSetup.SataHotPlug[2]|0x0 # Hot Plug
gStructPcdTokenSpaceGuid.PcdPchSetup.SataHotPlug[3]|0x0 # Hot Plug
gStructPcdTokenSpaceGuid.PcdPchSetup.SataHotPlug[4]|0x0 # Hot Plug
gStructPcdTokenSpaceGuid.PcdPchSetup.SataHotPlug[5]|0x0 # Hot Plug
gStructPcdTokenSpaceGuid.PcdPchSetup.SataHotPlug[6]|0x0 # Hot Plug
gStructPcdTokenSpaceGuid.PcdPchSetup.SataHotPlug[7]|0x0 # Hot Plug
gStructPcdTokenSpaceGuid.PcdPchSetup.SataInterfaceMode|0x0 # Configure SATA as
gStructPcdTokenSpaceGuid.PcdPchSetup.SataLedl|0x1 # SATA Led locate
gStructPcdTokenSpaceGuid.PcdPchSetup.SataMechanicalSw[0]|0x0 # Mechanical Presence Switch
gStructPcdTokenSpaceGuid.PcdPchSetup.SataMechanicalSw[1]|0x0 # Mechanical Presence Switch
gStructPcdTokenSpaceGuid.PcdPchSetup.SataMechanicalSw[2]|0x0 # Mechanical Presence Switch
gStructPcdTokenSpaceGuid.PcdPchSetup.SataMechanicalSw[3]|0x0 # Mechanical Presence Switch
gStructPcdTokenSpaceGuid.PcdPchSetup.SataMechanicalSw[4]|0x0 # Mechanical Presence Switch
gStructPcdTokenSpaceGuid.PcdPchSetup.SataMechanicalSw[5]|0x0 # Mechanical Presence Switch
gStructPcdTokenSpaceGuid.PcdPchSetup.SataMechanicalSw[6]|0x0 # Mechanical Presence Switch
gStructPcdTokenSpaceGuid.PcdPchSetup.SataMechanicalSw[7]|0x0 # Mechanical Presence Switch
gStructPcdTokenSpaceGuid.PcdPchSetup.SataPort[0]|0x1 # Port 0
gStructPcdTokenSpaceGuid.PcdPchSetup.SataPort[1]|0x1 # Port 1
gStructPcdTokenSpaceGuid.PcdPchSetup.SataPort[2]|0x1 # Port 2
gStructPcdTokenSpaceGuid.PcdPchSetup.SataPort[3]|0x1 # Port 3
gStructPcdTokenSpaceGuid.PcdPchSetup.SataPort[4]|0x1 # Port 4
gStructPcdTokenSpaceGuid.PcdPchSetup.SataPort[5]|0x1 # Port 5
gStructPcdTokenSpaceGuid.PcdPchSetup.SataPort[6]|0x1 # Port 6
gStructPcdTokenSpaceGuid.PcdPchSetup.SataPort[7]|0x1 # Port 7
gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidIooe|0x1 # IRRT Only on ESATA
gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidIrrt|0x1 # Intel Rapid Recovery Technology
gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidLoadEfiDriver[0]|0x0 # Load EFI Driver for RAID
gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidLoadEfiDriver[1]|0x0 # Load EFI Driver for RAID
gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidOromDelay|0x0 # RAID OROM prompt delay
gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidOub|0x1 # RAID Option ROM UI banner
gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidR0|0x1 # RAID 0
gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidR1|0x1 # RAID 1
gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidR10|0x1 # RAID 10
gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidR5|0x1 # RAID 5
gStructPcdTokenSpaceGuid.PcdPchSetup.SataRaidSrt|0x1 # Smart Response Technology
gStructPcdTokenSpaceGuid.PcdPchSetup.SataSalp|0x1 # Support Aggressive Link Power Management
gStructPcdTokenSpaceGuid.PcdPchSetup.SataSpinUp[0]|0x0 # Spin Up Device
gStructPcdTokenSpaceGuid.PcdPchSetup.SataSpinUp[1]|0x0 # Spin Up Device
gStructPcdTokenSpaceGuid.PcdPchSetup.SataSpinUp[2]|0x0 # Spin Up Device
gStructPcdTokenSpaceGuid.PcdPchSetup.SataSpinUp[3]|0x0 # Spin Up Device
gStructPcdTokenSpaceGuid.PcdPchSetup.SataSpinUp[4]|0x0 # Spin Up Device
gStructPcdTokenSpaceGuid.PcdPchSetup.SataSpinUp[5]|0x0 # Spin Up Device
gStructPcdTokenSpaceGuid.PcdPchSetup.SataSpinUp[6]|0x0 # Spin Up Device
gStructPcdTokenSpaceGuid.PcdPchSetup.SataSpinUp[7]|0x0 # Spin Up Device
gStructPcdTokenSpaceGuid.PcdPchSetup.SataTestMode|0x0 # SATA test mode
gStructPcdTokenSpaceGuid.PcdPchSetup.SataTopology[0]|0x0 # SATA Topology
gStructPcdTokenSpaceGuid.PcdPchSetup.SataTopology[1]|0x0 # SATA Topology
gStructPcdTokenSpaceGuid.PcdPchSetup.SataTopology[2]|0x0 # SATA Topology
gStructPcdTokenSpaceGuid.PcdPchSetup.SataTopology[3]|0x0 # SATA Topology
gStructPcdTokenSpaceGuid.PcdPchSetup.SataTopology[4]|0x0 # SATA Topology
gStructPcdTokenSpaceGuid.PcdPchSetup.SataTopology[5]|0x0 # SATA Topology
gStructPcdTokenSpaceGuid.PcdPchSetup.SataTopology[6]|0x0 # SATA Topology
gStructPcdTokenSpaceGuid.PcdPchSetup.SataTopology[7]|0x0 # SATA Topology
gStructPcdTokenSpaceGuid.PcdPchSetup.SataType[0]|0x0 # SATA Device Type
gStructPcdTokenSpaceGuid.PcdPchSetup.SataType[1]|0x0 # SATA Device Type
gStructPcdTokenSpaceGuid.PcdPchSetup.SataType[2]|0x0 # SATA Device Type
gStructPcdTokenSpaceGuid.PcdPchSetup.SataType[3]|0x0 # SATA Device Type
gStructPcdTokenSpaceGuid.PcdPchSetup.SataType[4]|0x0 # SATA Device Type
gStructPcdTokenSpaceGuid.PcdPchSetup.SataType[5]|0x0 # SATA Device Type
gStructPcdTokenSpaceGuid.PcdPchSetup.SataType[6]|0x0 # SATA Device Type
gStructPcdTokenSpaceGuid.PcdPchSetup.SataType[7]|0x0 # SATA Device Type
gStructPcdTokenSpaceGuid.PcdPchSetup.ShutdownPolicySelect|0x1 # Shutdown Policy
gStructPcdTokenSpaceGuid.PcdPchSetup.StateAfterG3|0x0 # PCH state after G3
gStructPcdTokenSpaceGuid.PcdPchSetup.TestDmiAspmCtrl|0x1 # PCH DMI ASPM Testing
gStructPcdTokenSpaceGuid.PcdPchSetup.TestMctpBroadcastCycle|0x0 # MCTP Broadcast Cycle
gStructPcdTokenSpaceGuid.PcdPchSetup.TestSmbusSpdWriteDisable|0x1 # SPD Write Disable
gStructPcdTokenSpaceGuid.PcdPchSetup.ThermalDeviceEnable|0x3 # PCH Thermal Device
gStructPcdTokenSpaceGuid.PcdPchSetup.Usb3PinsTermination|0x1 # Enable USB 3.0 pins
gStructPcdTokenSpaceGuid.PcdPchSetup.UsbPrecondition|0x0 # USB Precondition
gStructPcdTokenSpaceGuid.PcdPchSetup.XTpmLen|0x1 # Expanded SPI TPM Transaction Length Enable
gStructPcdTokenSpaceGuid.PcdPchSetup.XhciDisMSICapability|0x0 # USB XHCI MSI Disable WA
gStructPcdTokenSpaceGuid.PcdPchSetup.XhciIdleL1|0x1 # XHCI Idle L1
gStructPcdTokenSpaceGuid.PcdPchSetup.XhciOcMapEnabled|0x1 # XHCI Over Current Pins
gStructPcdTokenSpaceGuid.PcdPchSetup.sSataAlternateId|0x0 # Alternate Device ID on RAID
gStructPcdTokenSpaceGuid.PcdPchSetup.sSataExternal[0]|0x0 # Configure as eSATA
gStructPcdTokenSpaceGuid.PcdPchSetup.sSataExternal[1]|0x0 # Configure as eSATA
gStructPcdTokenSpaceGuid.PcdPchSetup.sSataExternal[2]|0x0 # Configure as eSATA
gStructPcdTokenSpaceGuid.PcdPchSetup.sSataExternal[3]|0x0 # Configure as eSATA
gStructPcdTokenSpaceGuid.PcdPchSetup.sSataExternal[4]|0x0 # Configure as eSATA
gStructPcdTokenSpaceGuid.PcdPchSetup.sSataExternal[5]|0x0 # Configure as eSATA
gStructPcdTokenSpaceGuid.PcdPchSetup.sSataHddlk|0x1 # SATA HDD Unlock
gStructPcdTokenSpaceGuid.PcdPchSetup.sSataHotPlug[0]|0x0 # Hot Plug
gStructPcdTokenSpaceGuid.PcdPchSetup.sSataHotPlug[1]|0x0 # Hot Plug
gStructPcdTokenSpaceGuid.PcdPchSetup.sSataHotPlug[2]|0x0 # Hot Plug
gStructPcdTokenSpaceGuid.PcdPchSetup.sSataHotPlug[3]|0x0 # Hot Plug
gStructPcdTokenSpaceGuid.PcdPchSetup.sSataHotPlug[4]|0x0 # Hot Plug
gStructPcdTokenSpaceGuid.PcdPchSetup.sSataHotPlug[5]|0x0 # Hot Plug
gStructPcdTokenSpaceGuid.PcdPchSetup.sSataInterfaceMode|0x0 # Configure sSATA as
gStructPcdTokenSpaceGuid.PcdPchSetup.sSataLedl|0x1 # SATA Led locate
gStructPcdTokenSpaceGuid.PcdPchSetup.sSataPort[0]|0x1 # Port 0
gStructPcdTokenSpaceGuid.PcdPchSetup.sSataPort[1]|0x1 # Port 1
gStructPcdTokenSpaceGuid.PcdPchSetup.sSataPort[2]|0x1 # Port 2
gStructPcdTokenSpaceGuid.PcdPchSetup.sSataPort[3]|0x1 # Port 3
gStructPcdTokenSpaceGuid.PcdPchSetup.sSataPort[4]|0x1 # Port 4
gStructPcdTokenSpaceGuid.PcdPchSetup.sSataPort[5]|0x1 # Port 5
gStructPcdTokenSpaceGuid.PcdPchSetup.sSataRaidIooe|0x1 # IRRT Only on ESATA
gStructPcdTokenSpaceGuid.PcdPchSetup.sSataRaidIrrt|0x1 # Intel Rapid Recovery Technology
gStructPcdTokenSpaceGuid.PcdPchSetup.sSataRaidOromDelay|0x0 # RAID OROM prompt delay
gStructPcdTokenSpaceGuid.PcdPchSetup.sSataRaidOub|0x1 # RAID Option ROM UI banner
gStructPcdTokenSpaceGuid.PcdPchSetup.sSataRaidR0|0x1 # RAID 0
gStructPcdTokenSpaceGuid.PcdPchSetup.sSataRaidR1|0x1 # RAID 1
gStructPcdTokenSpaceGuid.PcdPchSetup.sSataRaidR10|0x1 # RAID 10
gStructPcdTokenSpaceGuid.PcdPchSetup.sSataRaidR5|0x1 # RAID 5
gStructPcdTokenSpaceGuid.PcdPchSetup.sSataRaidSrt|0x1 # Smart Response Technology
gStructPcdTokenSpaceGuid.PcdPchSetup.sSataSalp|0x1 # Support Aggressive Link Power Management
gStructPcdTokenSpaceGuid.PcdPchSetup.sSataSpinUp[0]|0x0 # Spin Up Device
gStructPcdTokenSpaceGuid.PcdPchSetup.sSataSpinUp[1]|0x0 # Spin Up Device
gStructPcdTokenSpaceGuid.PcdPchSetup.sSataSpinUp[2]|0x0 # Spin Up Device
gStructPcdTokenSpaceGuid.PcdPchSetup.sSataSpinUp[3]|0x0 # Spin Up Device