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Mult16_map.map
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Mult16_map.map
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Release 14.7 Map P.20131013 (nt64)
Xilinx Map Application Log File for Design 'Mult16'
Design Information
------------------
Command Line : map -intstyle ise -p xc6slx16-csg324-2 -w -logic_opt off -ol
high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off
-pr off -lc off -power off -o Mult16_map.ncd Mult16.ngd Mult16.pcf
Target Device : xc6slx16
Target Package : csg324
Target Speed : -2
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Tue Mar 07 19:07:44 2017
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 5 secs
Total CPU time at the beginning of Placer: 4 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:114e1) REAL time: 6 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:114e1) REAL time: 6 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:114e1) REAL time: 6 secs
Phase 4.2 Initial Placement for Architecture Specific Features
......
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:14cc1d44) REAL time: 8 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:14cc1d44) REAL time: 8 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:14cc1d44) REAL time: 8 secs
Phase 7.3 Local Placement Optimization
...
Phase 7.3 Local Placement Optimization (Checksum:6ea62d33) REAL time: 8 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:6ea62d33) REAL time: 8 secs
Phase 9.8 Global Placement
..............
....
Phase 9.8 Global Placement (Checksum:8e6b4e16) REAL time: 8 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:8e6b4e16) REAL time: 8 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:c970333e) REAL time: 9 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:c970333e) REAL time: 9 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:c970333e) REAL time: 9 secs
Total REAL time to Placer completion: 9 secs
Total CPU time to Placer completion: 8 secs
Running post-placement packing...
Writing output files...
Design Summary
--------------
Design Summary:
Number of errors: 0
Number of warnings: 0
Slice Logic Utilization:
Number of Slice Registers: 81 out of 18,224 1%
Number used as Flip Flops: 80
Number used as Latches: 1
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 129 out of 9,112 1%
Number used as logic: 129 out of 9,112 1%
Number using O6 output only: 111
Number using O5 output only: 0
Number using O5 and O6: 18
Number used as ROM: 0
Number used as Memory: 0 out of 2,176 0%
Slice Logic Distribution:
Number of occupied Slices: 44 out of 2,278 1%
Number of MUXCYs used: 0 out of 4,556 0%
Number of LUT Flip Flop pairs used: 132
Number with an unused Flip Flop: 55 out of 132 41%
Number with an unused LUT: 3 out of 132 2%
Number of fully used LUT-FF pairs: 74 out of 132 56%
Number of unique control sets: 5
Number of slice register sites lost
to control set restrictions: 15 out of 18,224 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 36 out of 232 15%
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 32 0%
Number of RAMB8BWERs: 0 out of 64 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 2 out of 16 12%
Number used as BUFGs: 2
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 4 0%
Number of ILOGIC2/ISERDES2s: 0 out of 248 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 248 0%
Number of OLOGIC2/OSERDES2s: 0 out of 248 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 128 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 32 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 2 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 4.62
Peak Memory Usage: 405 MB
Total REAL time to MAP completion: 10 secs
Total CPU time to MAP completion: 8 secs
Mapping completed.
See MAP report file "Mult16_map.mrp" for details.