From 8946ec58c4723dfa9733844b545489f347a6571d Mon Sep 17 00:00:00 2001 From: Bo Wun Cheng Date: Fri, 19 Jan 2024 17:20:26 -0800 Subject: [PATCH 01/18] updated parse.dot and compute_node.py to generate coreir and use metamapper to map the pe --- sam/onyx/hw_nodes/compute_node.py | 63 +++++++++++++++----------- sam/onyx/hw_nodes/read_scanner_node.py | 2 +- sam/onyx/parse_dot.py | 51 ++++++++++++++++++++- 3 files changed, 87 insertions(+), 29 deletions(-) diff --git a/sam/onyx/hw_nodes/compute_node.py b/sam/onyx/hw_nodes/compute_node.py index 9c6af1e3..30a39afc 100644 --- a/sam/onyx/hw_nodes/compute_node.py +++ b/sam/onyx/hw_nodes/compute_node.py @@ -1,15 +1,25 @@ from sam.onyx.hw_nodes.hw_node import * from lassen.utils import float2bfbin +import coreir +import subprocess +import json +import os class ComputeNode(HWNode): - def __init__(self, name=None, op=None) -> None: + def __init__(self, name=None, op=None, sam_graph_node_id=None) -> None: super().__init__(name=name) self.num_inputs = 2 self.num_outputs = 1 self.num_inputs_connected = 0 self.num_outputs_connected = 0 + self.mapped_input_ports = [] self.op = op + self.opcode = None + # parse the mapped coreir file to get the input ports and opcode + self.parse_mapped_json("/aha/alu_mapped.json", sam_graph_node_id) + assert len(self.mapped_input_ports) > 0 + assert self.opcode is not None def connect(self, other, edge, kwargs=None): @@ -161,6 +171,21 @@ def update_input_connections(self): def get_num_inputs(self): return self.num_inputs_connected + def parse_mapped_json(self, filename, node_id): + with open(filename, 'r') as alu_mapped_file: + alu_mapped = json.load(alu_mapped_file) + # parse out the mapped opcode + opcode = alu_mapped["namespaces"]["global"]["modules"]["ALU_" + node_id + "_mapped"]["instances"]["c0"]["modargs"]["value"][1] + opcode = "0x" + opcode.split('h')[1] + # parse out the mapped input ports + for connection in alu_mapped["namespaces"]["global"]["modules"]["ALU_" + node_id + "_mapped"]["connections"]: + src, dest = connection + # if the connection is to the data port of alu + if "self.in" in src: + # get the port name of the alu + self.mapped_input_ports.append(dest.split(".")[1]) + self.opcode = int(opcode, 0) + def configure(self, attributes): print("PE CONFIGURE") print(attributes) @@ -174,28 +199,13 @@ def configure(self, attributes): pe_only = True # data I/O should interface with other primitive outside of the cluster pe_in_external = 1 - if c_op == 'mul': - op_code = 1 - elif c_op == 'add' and 'sub=1' not in comment: - op_code = 0 - elif c_op == 'add' and 'sub=1' in comment: - op_code = 2 - elif c_op == 'max': - op_code = 4 - elif c_op == 'and': - op_code = 5 - elif c_op == 'fp_mul': - op_code = 6 - elif c_op == 'fgetfint': - op_code = 7 - elif c_op == 'fgetffrac': - op_code = 8 - elif c_op == 'faddiexp': - op_code = 9 - elif c_op == 'fp_max': - op_code = 10 - elif c_op == 'fp_add': - op_code = 11 + # according to the mapped input ports generate input port config + num_sparse_inputs = list("000") + for i in range(3): + if f"data{2 - i}" in self.mapped_input_ports: + num_sparse_inputs[i] = '1' + print("".join(num_sparse_inputs)) + num_sparse_inputs = int("".join(num_sparse_inputs), 2) rb_const = None if "rb_const" in attributes: @@ -210,10 +220,11 @@ def configure(self, attributes): rb_const = int(rb_const) cfg_kwargs = { - 'op': op_code, + 'op': self.opcode, 'use_dense': use_dense, 'pe_only': pe_only, 'pe_in_external': pe_in_external, - 'rb_const': rb_const + 'rb_const': rb_const, + 'num_sparse_inputs': num_sparse_inputs } - return (op_code, use_dense, pe_only, pe_in_external, rb_const), cfg_kwargs + return (op_code, use_dense, pe_only, pe_in_external, rb_const, num_sparse_inputs), cfg_kwargs diff --git a/sam/onyx/hw_nodes/read_scanner_node.py b/sam/onyx/hw_nodes/read_scanner_node.py index b568fe24..1dfd762a 100644 --- a/sam/onyx/hw_nodes/read_scanner_node.py +++ b/sam/onyx/hw_nodes/read_scanner_node.py @@ -215,7 +215,7 @@ def connect(self, other, edge, kwargs=None): assert 0 & "edge connected to faddiexp has to have comment specified to either 'exp' or 'fp'" new_conns = { f'rd_scan_to_compute_{compute_conn}': [ - ([(rd_scan, "coord_out"), (compute, f"data{compute_conn}")], 17), + ([(rd_scan, "coord_out"), (compute, other.mapped_input_ports[compute_conn])], 17), ] } # Now update the PE/compute to use the next connection next time diff --git a/sam/onyx/parse_dot.py b/sam/onyx/parse_dot.py index fa18a557..c31fdb0c 100644 --- a/sam/onyx/parse_dot.py +++ b/sam/onyx/parse_dot.py @@ -1,6 +1,9 @@ import argparse from numpy import broadcast import pydot +import coreir +import os +import subprocess from sam.onyx.hw_nodes.hw_node import HWNodeType @@ -78,11 +81,44 @@ def get_mode_map(self): # return self.mode_map return self.remaining + def generate_coreir_spec(self, context, attributes, name): + # FIXME: change this if we want operation with constant + # Declare I/O of ALU + module_typ = context.Record({"in0": context.Array(1, context.Array(16, context.BitIn())), "in1": context.Array(1, context.Array(16, context.BitIn())), "out": context.Array(16, context.Bit())}) + module = context.global_namespace.new_module("ALU_" + name, module_typ) + assert module.definition is None, "Should not have a definition" + module_def = module.new_definition() + # FIXME: hack for mapping reduce for now, fix reduce function to integer add + if attributes['type'].strip('"') == "reduce": + alu_op = "add" + else: + alu_op = attributes['type'].strip('"') + # import the desired operation from coreir + coreir_op = context.get_namespace("coreir").generators[alu_op] + # configure the width of the op + # FIXME: hardcoded to 16 for now + op = coreir_op(width=16) + # add the operation instance to the module + op_inst = module_def.add_module_instance(alu_op, op) + # connect the input to the op + _input0 = module_def.interface.select("in0").select("0") + _input1 = module_def.interface.select("in1").select("0") + _output = module_def.interface.select("out") + _alu_in0 = op_inst.select("in0") + _alu_in1 = op_inst.select("in1") + _alu_out = op_inst.select("out") + module_def.connect(_input0, _alu_in0) + module_def.connect(_input1, _alu_in1) + module_def.connect(_output, _alu_out) + module.definition = module_def + assert module.definition is not None, "Should have a definitation by now" + def map_nodes(self): ''' Iterate through the nodes and map them to the proper HWNodes ''' - + c = coreir.Context() + contains_compute = False for node in self.graph.get_nodes(): # Simple write the HWNodeType attribute if 'hwnode' not in node.get_attributes(): @@ -101,6 +137,8 @@ def map_nodes(self): hw_nt = f"HWNodeType.Repeat" elif n_type == "mul" or n_type == "add" or n_type == "max" or n_type == "and": hw_nt = f"HWNodeType.Compute" + self.generate_coreir_spec(c, node.get_attributes(), node.get_name()) + contains_compute = True elif n_type == "fgetfint" or n_type == "fgetffrac" or n_type == "faddiexp": hw_nt = f"HWNodeType.Compute" elif n_type == "fp_mul" or n_type == "fp_max" or n_type == "fp_add": @@ -118,8 +156,17 @@ def map_nodes(self): else: print(n_type) raise SAMDotGraphLoweringError(f"Node is of type {n_type}") - node.get_attributes()['hwnode'] = hw_nt + # generates the coreir json file + c.save_to_file("/aha/alu.json") + # use metamapper to map it + # set environment variable PIPELINED to zero to disable input buffering in the alu + # in order to make sure the output comes out within the same cycle the input is given + if contains_compute: + # only runs metamapper if the graph contains compute logic + metamapp_env = os.environ.copy() + metamapp_env["PIPELINED"] = "0" + subprocess.run(["python", "/aha/MetaMapper/scripts/map_app.py", "/aha/alu.json"], env=metamapp_env) def get_next_seq(self): ret = self.seq From 56744d993da7a80a827a35401d7ed441440c20d6 Mon Sep 17 00:00:00 2001 From: Bo Wun Cheng Date: Sun, 21 Jan 2024 13:00:38 -0800 Subject: [PATCH 02/18] update mapped input port storing logic, compute to compute connetion logic, and dedicated reduce primitive mapping logic --- sam/onyx/hw_nodes/compute_node.py | 9 +++++---- sam/onyx/hw_nodes/read_scanner_node.py | 2 +- sam/onyx/hw_nodes/reduce_node.py | 9 ++++++++- 3 files changed, 14 insertions(+), 6 deletions(-) diff --git a/sam/onyx/hw_nodes/compute_node.py b/sam/onyx/hw_nodes/compute_node.py index 30a39afc..de147365 100644 --- a/sam/onyx/hw_nodes/compute_node.py +++ b/sam/onyx/hw_nodes/compute_node.py @@ -139,6 +139,8 @@ def connect(self, other, edge, kwargs=None): other_conn = 1 else: assert 0 & "edge connected to faddiexp has to have comment specified to either 'exp' or 'fp'" + else: + other_conn = other.mapped_input_ports[other_conn] new_conns = { f'pe_to_pe_{other_conn}': [ ([(pe, "res"), (other_pe, f"data{other_conn}")], 17), @@ -183,7 +185,7 @@ def parse_mapped_json(self, filename, node_id): # if the connection is to the data port of alu if "self.in" in src: # get the port name of the alu - self.mapped_input_ports.append(dest.split(".")[1]) + self.mapped_input_ports.append(dest.split(".")[1].strip("data")) self.opcode = int(opcode, 0) def configure(self, attributes): @@ -201,9 +203,8 @@ def configure(self, attributes): pe_in_external = 1 # according to the mapped input ports generate input port config num_sparse_inputs = list("000") - for i in range(3): - if f"data{2 - i}" in self.mapped_input_ports: - num_sparse_inputs[i] = '1' + for port in self.mapped_input_ports: + num_sparse_inputs[2 - int(port)] = '1' print("".join(num_sparse_inputs)) num_sparse_inputs = int("".join(num_sparse_inputs), 2) diff --git a/sam/onyx/hw_nodes/read_scanner_node.py b/sam/onyx/hw_nodes/read_scanner_node.py index 1dfd762a..2d210fb6 100644 --- a/sam/onyx/hw_nodes/read_scanner_node.py +++ b/sam/onyx/hw_nodes/read_scanner_node.py @@ -215,7 +215,7 @@ def connect(self, other, edge, kwargs=None): assert 0 & "edge connected to faddiexp has to have comment specified to either 'exp' or 'fp'" new_conns = { f'rd_scan_to_compute_{compute_conn}': [ - ([(rd_scan, "coord_out"), (compute, other.mapped_input_ports[compute_conn])], 17), + ([(rd_scan, "coord_out"), (compute, f"data{other.mapped_input_ports[compute_conn]}")], 17), ] } # Now update the PE/compute to use the next connection next time diff --git a/sam/onyx/hw_nodes/reduce_node.py b/sam/onyx/hw_nodes/reduce_node.py index b19cf5e2..4a43a9ec 100644 --- a/sam/onyx/hw_nodes/reduce_node.py +++ b/sam/onyx/hw_nodes/reduce_node.py @@ -1,4 +1,8 @@ from sam.onyx.hw_nodes.hw_node import * +from peak.assembler import Assembler +from hwtypes.modifiers import strip_modifiers +from lassen.sim import PE_fc as lassen_fc +import lassen.asm as asm class ReduceNode(HWNode): @@ -112,7 +116,10 @@ def configure(self, attributes): # data I/O to and from the PE should be internal with the reduce pe_in_external = 0 # op is set to integer add for the PE TODO: make this configurable in the sam graph - op = 0 + # TODO: make this use the metamapper + instr_type = strip_modifiers(lassen_fc.Py.input_t.field_dict['inst']) + asm_ = Assembler(instr_type) + op = int(asm_.assemble(asm.add())) cfg_kwargs = { 'stop_lvl': stop_lvl, 'pe_connected_to_reduce': pe_connected_to_reduce, From 6ded96d1141d74e22c44d82f6a5fa17df1b0fbc9 Mon Sep 17 00:00:00 2001 From: Bo Wun Cheng Date: Sun, 21 Jan 2024 20:56:51 -0800 Subject: [PATCH 03/18] update the intersect-to-compute connection logic to use ports metamapper generates, clean up printing statement in read scanner node --- sam/onyx/hw_nodes/intersect_node.py | 6 +----- sam/onyx/hw_nodes/read_scanner_node.py | 7 ------- 2 files changed, 1 insertion(+), 12 deletions(-) diff --git a/sam/onyx/hw_nodes/intersect_node.py b/sam/onyx/hw_nodes/intersect_node.py index f84feeef..c95bb3f1 100644 --- a/sam/onyx/hw_nodes/intersect_node.py +++ b/sam/onyx/hw_nodes/intersect_node.py @@ -175,18 +175,14 @@ def connect(self, other, edge, kwargs=None): # Could be doing a sparse accum compute = other compute_name = other.get_name() - print("INTERSECT TO COMPUTE EDGE!") - print(edge) - print(edge.get_attributes()) edge_comment = edge.get_attributes()['comment'].strip('"') tensor = edge_comment.split('-')[1] - print(self.tensor_to_conn) out_conn = self.tensor_to_conn[tensor] compute_conn = compute.get_num_inputs() new_conns = { 'intersect_to_repeat': [ # send output to rd scanner - ([(isect, f"pos_out_{out_conn}"), (compute_name, f"data{compute_conn}")], 17), + ([(isect, f"pos_out_{out_conn}"), (compute_name, f"data{compute.mapped_input_ports[compute_conn]}")], 17), ] } compute.update_input_connections() diff --git a/sam/onyx/hw_nodes/read_scanner_node.py b/sam/onyx/hw_nodes/read_scanner_node.py index 2d210fb6..0513939a 100644 --- a/sam/onyx/hw_nodes/read_scanner_node.py +++ b/sam/onyx/hw_nodes/read_scanner_node.py @@ -194,13 +194,6 @@ def connect(self, other, edge, kwargs=None): return new_conns elif other_type == ComputeNode: compute = other.get_name() - # compute_conn = 0 - print("CHECKING READ TENSOR - COMPUTE") - print(edge) - print(self.get_tensor()) - # if self.get_tensor() == 'C' or self.get_tensor() == 'c': - # compute_conn = 1 - # Can use dynamic information to assign inputs to compute nodes # since add/mul are commutative compute_conn = other.get_num_inputs() From 126a18b355e4e623e4672901bd97e3de06610167 Mon Sep 17 00:00:00 2001 From: Bo Wun Cheng Date: Sun, 21 Jan 2024 20:57:44 -0800 Subject: [PATCH 04/18] alu mapping with metamapper now happens in a standalone function, also enabled alu mapping for adder in vector_reduce --- sam/onyx/parse_dot.py | 36 +++++++++++++++++++++++------------- 1 file changed, 23 insertions(+), 13 deletions(-) diff --git a/sam/onyx/parse_dot.py b/sam/onyx/parse_dot.py index c31fdb0c..d4baf716 100644 --- a/sam/onyx/parse_dot.py +++ b/sam/onyx/parse_dot.py @@ -28,6 +28,7 @@ def __init__(self, filename=None, local_mems=True, use_fork=False, self.use_fa = use_fa self.fa_color = 0 + self.alu_nodes = [] self.shared_writes = {} if unroll > 1: @@ -51,6 +52,7 @@ def __init__(self, filename=None, local_mems=True, use_fork=False, else: self.rewrite_rsg_broadcast() self.map_nodes() + self.map_alu() def get_mode_map(self): sc = self.graph.get_comment().strip('"') @@ -137,8 +139,7 @@ def map_nodes(self): hw_nt = f"HWNodeType.Repeat" elif n_type == "mul" or n_type == "add" or n_type == "max" or n_type == "and": hw_nt = f"HWNodeType.Compute" - self.generate_coreir_spec(c, node.get_attributes(), node.get_name()) - contains_compute = True + self.alu_nodes.append(node) elif n_type == "fgetfint" or n_type == "fgetffrac" or n_type == "faddiexp": hw_nt = f"HWNodeType.Compute" elif n_type == "fp_mul" or n_type == "fp_max" or n_type == "fp_add": @@ -152,21 +153,29 @@ def map_nodes(self): elif n_type == "crdhold": hw_nt = f"HWNodeType.CrdHold" elif n_type == "vectorreducer": - hw_nt = f"HWNodeType.VectorReducer " + hw_nt = f"HWNodeType.VectorReducer" else: print(n_type) raise SAMDotGraphLoweringError(f"Node is of type {n_type}") node.get_attributes()['hwnode'] = hw_nt - # generates the coreir json file - c.save_to_file("/aha/alu.json") - # use metamapper to map it - # set environment variable PIPELINED to zero to disable input buffering in the alu - # in order to make sure the output comes out within the same cycle the input is given - if contains_compute: - # only runs metamapper if the graph contains compute logic - metamapp_env = os.environ.copy() - metamapp_env["PIPELINED"] = "0" - subprocess.run(["python", "/aha/MetaMapper/scripts/map_app.py", "/aha/alu.json"], env=metamapp_env) + + def map_alu(self): + if len(self.alu_nodes) > 0: + c = coreir.Context() + # iterate through all compute nodes and generate their coreir spec + for alu_node in self.alu_nodes: + self.generate_coreir_spec(c, + alu_node.get_attributes(), + alu_node.get_name()) + c.save_to_file("/aha/alu.json") + + # use metamapper to map it + # set environment variable PIPELINED to zero to disable input buffering in the alu + # in order to make sure the output comes out within the same cycle the input is given + metamapper_env = os.environ.copy() + metamapper_env["PIPELINED"] = "0" + subprocess.run(["python", "aha/MetaMapper/scripts/map_app.py", "/aha/alu.json"], env=metamapper_env) + def get_next_seq(self): ret = self.seq @@ -258,6 +267,7 @@ def rewrite_VectorReducer(self): add = pydot.Node(f"vr_add_{self.get_next_seq()}", label=f"{og_label}_Add", hwnode=f"{HWNodeType.Compute}", type="add", sub="0", comment="type=add,sub=0") + self.alu_nodes.append(add) crd_buffet = pydot.Node(f"vr_crd_buffet_{self.get_next_seq()}", label=f"{og_label}_crd_buffet", hwnode=f"{HWNodeType.Buffet}", From 4187b78f04c9625a6952993565d8846683a6ac0a Mon Sep 17 00:00:00 2001 From: Bo Wun Cheng Date: Sun, 21 Jan 2024 21:57:48 -0800 Subject: [PATCH 05/18] parse_dot now dumps the alu coreir spec and mapped alu coreir spec in to collat dir, update compute node to parse json file in collat dir --- .../.ast_tools/__call__140020533737792.py | 7 + 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diff --git a/sam/onyx/.ast_tools/__call__140020535566688.py b/sam/onyx/.ast_tools/__call__140020535566688.py new file mode 100644 index 00000000..2cbfdd97 --- /dev/null +++ b/sam/onyx/.ast_tools/__call__140020535566688.py @@ -0,0 +1,149 @@ +@name_outputs(res=Data, res_p=Bit, Z=Bit, N=Bit, C=Bit, V=Bit) +def __call__( + self, + alu: Const(ALU_t), + signed_: Const(Signed_t), + a: DataPy, + b: DataPy, + c: DataPy, + d: BitPy, +) -> (DataPy, BitPy, BitPy, BitPy, BitPy, BitPy): + _cond_0 = signed_ == Signed_t.signed + mula_0 = UData32(SData(a).sext(16)) + mulb_0 = UData32(SData(b).sext(16)) + mula_1 = UData(a).zext(16) + mulb_1 = UData(b).zext(16) + mula_2 = __phi(_cond_0, mula_0, mula_1) + mulb_2 = __phi(_cond_0, mulb_0, mulb_1) + mul_0 = mula_2 * mulb_2 + _cond_1 = signed_ == Signed_t.signed + lte_pred_0 = SData(a) <= SData(b) + lte_pred_1 = UData(a) <= UData(b) + lte_pred_2 = __phi(_cond_1, lte_pred_0, lte_pred_1) + min_ab_0 = lte_pred_2.ite(a, b) + _cond_2 = alu == ALU_t.CROP + max_in0_0 = min_ab_0 + max_in0_1 = b + max_in0_2 = __phi(_cond_2, max_in0_0, max_in0_1) + _cond_3 = signed_ == Signed_t.signed + gte_pred_0 = SData(max_in0_2) >= SData(c) + gte_pred_1 = UData(max_in0_2) >= UData(c) + gte_pred_2 = __phi(_cond_3, gte_pred_0, gte_pred_1) + max_bc_0 = gte_pred_2.ite(max_in0_2, c) + _cond_4 = alu == ALU_t.MULSHR + shr_in0_0 = mul_0[:16] + shr_in0_1 = a + shr_in0_2 = __phi(_cond_4, shr_in0_0, shr_in0_1) + _cond_5 = signed_ == Signed_t.signed + shr_0 = Data(SData(shr_in0_2) >> SData(c)) + shr_1 = Data(UData(shr_in0_2) >> UData(c)) + shr_2 = __phi(_cond_5, shr_0, shr_1) + _cond_6 = (alu == ALU_t.Sbc) | (alu == ALU_t.TSA) | (alu == ALU_t.TSS) + b_0 = ~b + b_1 = __phi(_cond_6, b_0, b) + + Cin_0 = d + + # factor out comman add + adder_res_0, adder_C_0 = UData(a).adc(UData(b_1), Cin_0) + _cond_7 = ( + (alu == ALU_t.TAA) + | (alu == ALU_t.TAS) + | (alu == ALU_t.TSA) + | (alu == ALU_t.TSS) + ) + adder2_in0_0 = adder_res_0 + adder2_in0_1 = mul_0[:16] + adder2_in0_2 = __phi(_cond_7, adder2_in0_0, adder2_in0_1) + _cond_8 = (alu == ALU_t.MULSUB) | (alu == ALU_t.TAS) | (alu == ALU_t.TSS) + adder2_in1_0 = ~c + Cin2_0 = Bit(1) + adder2_in1_1 = c + Cin2_1 = Bit(0) + Cin2_2 = __phi(_cond_8, Cin2_0, Cin2_1) + adder2_in1_2 = __phi(_cond_8, adder2_in1_0, adder2_in1_1) + + adder2_res_0, adder2_C_0 = UData(adder2_in0_2).adc(adder2_in1_2, Cin2_2) + + C_0 = Bit(0) + V_0 = Bit(0) + _cond_21 = (alu == ALU_t.Adc) | (alu == ALU_t.Sbc) + res_0, C_1 = adder_res_0, adder_C_0 + V_1 = overflow(a, b_1, res_0) + res_p_0 = C_1 + _cond_20 = alu == ALU_t.Mult0 + res_1, C_2, V_2 = mul_0[:16], Bit(0), Bit(0) + res_p_1 = C_2 + _cond_19 = alu == ALU_t.Mult1 + res_2, C_3, V_3 = mul_0[8:24], Bit(0), Bit(0) + res_p_2 = C_3 + _cond_18 = alu == ALU_t.Mult2 + res_3, C_4, V_4 = mul_0[16:32], Bit(0), Bit(0) + res_p_3 = C_4 + _cond_17 = alu == ALU_t.Abs + abs_pred_0 = SData(a) >= SData(0) + res_4, res_p_4 = abs_pred_0.ite(a, UInt[16](-SInt[16](a))), Bit(a[-1]) + _cond_16 = alu == ALU_t.Sel + res_5, res_p_5 = d.ite(a, b_1), Bit(0) + _cond_15 = alu == ALU_t.And + res_6, res_p_6 = a & b_1, Bit(0) + _cond_14 = alu == ALU_t.Or + res_7, res_p_7 = a | b_1, Bit(0) + _cond_13 = alu == ALU_t.XOr + res_8, res_p_8 = a ^ b_1, Bit(0) + _cond_12 = alu == ALU_t.SHR + res_9, res_p_9 = shr_2, Bit(0) + _cond_11 = alu == ALU_t.SHL + res_10, res_p_10 = a << b_1, Bit(0) + _cond_10 = ( + (alu == ALU_t.MULADD) + | (alu == ALU_t.MULSUB) + | (alu == ALU_t.TAA) + | (alu == ALU_t.TSA) + | (alu == ALU_t.TAS) + | (alu == ALU_t.TSS) + ) + res_11, res_p_11 = adder2_res_0, Bit(0) + _cond_9 = alu == ALU_t.CROP + res_12, res_p_12 = max_bc_0, Bit(0) + res_13, res_p_13 = shr_2, Bit(0) + res_14 = __phi(_cond_9, res_12, res_13) + res_p_14 = __phi(_cond_9, res_p_12, res_p_13) + res_15 = __phi(_cond_10, res_11, res_14) + res_p_15 = __phi(_cond_10, res_p_11, res_p_14) + res_16 = __phi(_cond_11, res_10, res_15) + res_p_16 = __phi(_cond_11, res_p_10, res_p_15) + res_17 = __phi(_cond_12, res_9, res_16) + res_p_17 = __phi(_cond_12, res_p_9, res_p_16) + res_18 = __phi(_cond_13, res_8, res_17) + res_p_18 = __phi(_cond_13, res_p_8, res_p_17) + res_19 = __phi(_cond_14, res_7, res_18) + res_p_19 = __phi(_cond_14, res_p_7, res_p_18) + res_20 = __phi(_cond_15, res_6, res_19) + res_p_20 = __phi(_cond_15, res_p_6, res_p_19) + res_21 = __phi(_cond_16, res_5, res_20) + res_p_21 = __phi(_cond_16, res_p_5, res_p_20) + res_22 = __phi(_cond_17, res_4, res_21) + res_p_22 = __phi(_cond_17, res_p_4, res_p_21) + C_5 = __phi(_cond_18, C_4, C_0) + V_5 = __phi(_cond_18, V_4, V_0) + res_23 = __phi(_cond_18, res_3, res_22) + res_p_23 = __phi(_cond_18, res_p_3, res_p_22) + C_6 = __phi(_cond_19, C_3, C_5) + V_6 = __phi(_cond_19, V_3, V_5) + res_24 = __phi(_cond_19, res_2, res_23) + res_p_24 = __phi(_cond_19, res_p_2, res_p_23) + C_7 = __phi(_cond_20, C_2, C_6) + V_7 = __phi(_cond_20, V_2, V_6) + res_25 = __phi(_cond_20, res_1, res_24) + res_p_25 = __phi(_cond_20, res_p_1, res_p_24) + C_8 = __phi(_cond_21, C_1, C_7) + V_8 = __phi(_cond_21, V_1, V_7) + res_26 = __phi(_cond_21, res_0, res_25) + res_p_26 = __phi(_cond_21, res_p_0, res_p_25) + + N_0 = Bit(res_26[-1]) + Z_0 = res_26 == SData(0) + + __0_return_0 = res_26, res_p_26, Z_0, N_0, C_8, V_8 + return __0_return_0 diff --git a/sam/onyx/.ast_tools/__call__140020542680080.py b/sam/onyx/.ast_tools/__call__140020542680080.py new file mode 100644 index 00000000..c159114e --- /dev/null +++ b/sam/onyx/.ast_tools/__call__140020542680080.py @@ -0,0 +1,40 @@ +@name_outputs(res=Data, N=Bit, Z=Bit) +def __call__(self, fpu_op: Const(FPU_t), a: Data, b: Data) -> (Data, Bit, Bit): + + a_inf_0 = fp_is_inf(a) + b_inf_0 = fp_is_inf(b) + a_neg_0 = fp_is_neg(a) + b_neg_0 = fp_is_neg(b) + + old_b_0 = b + neg_b_0 = (fpu_op == FPU_t.FP_sub) | (fpu_op == FPU_t.FP_cmp) | (fpu_op == FPU_t.FP_max) + _cond_0 = neg_b_0 + b_0 = b ^ (2 ** (16 - 1)) + b_1 = __phi(_cond_0, b_0, b) + Add_val_0 = self.Add(a, b_1) + Mul_val_0 = self.Mul(a, b_1) + _cond_3 = ( + (fpu_op == FPU_t.FP_add) + | (fpu_op == FPU_t.FP_sub) + | (fpu_op == FPU_t.FP_cmp) + ) + res_0 = Add_val_0 + _cond_2 = (fpu_op == FPU_t.FP_max) + _cond_1 = family.Bit(Add_val_0[-1]) + res_1 = old_b_0 + res_2 = a + res_3 = __phi(_cond_1, res_1, res_2) + res_4 = Mul_val_0 + res_5 = __phi(_cond_2, res_3, res_4) + res_6 = __phi(_cond_3, res_0, res_5) + + Z_0 = fp_is_zero(res_6) + _cond_5 = fpu_op == FPU_t.FP_cmp + _cond_4 = (a_inf_0 & b_inf_0) & (a_neg_0 == b_neg_0) + Z_1 = family.Bit(1) + Z_2 = __phi(_cond_4, Z_1, Z_0) + Z_3 = __phi(_cond_5, Z_2, Z_0) + + N_0 = family.Bit(res_6[-1]) + __0_return_0 = res_6, N_0, Z_3 + return __0_return_0 diff --git a/sam/onyx/.ast_tools/__call__140020542812512.py b/sam/onyx/.ast_tools/__call__140020542812512.py new file mode 100644 index 00000000..678a8cde --- /dev/null +++ b/sam/onyx/.ast_tools/__call__140020542812512.py @@ -0,0 +1,7 @@ +def __call__(self, in0: Data, in1: Data) -> Data: + in0_float_0 = cast(in0) + in1_float_0 = cast(in1) + out_float_0 = getattr(in0_float_0, op_name)(in1_float_0) + out_0 = out_float_0.reinterpret_as_bv() + __0_return_0 = out_0 + return __0_return_0 diff --git a/sam/onyx/.ast_tools/__call__140020545582560.py b/sam/onyx/.ast_tools/__call__140020545582560.py new file mode 100644 index 00000000..c8f4fa5a --- /dev/null +++ b/sam/onyx/.ast_tools/__call__140020545582560.py @@ -0,0 +1,16 @@ +def __call__( + self, mode: Mode_t, const_: T, value: T, clk_en: Bit +) -> (T, T): + _cond_0 = mode == Mode_t.DELAY + data_0, en_0 = value, clk_en + data_1, en_1 = value, Bit(0) + data_2 = __phi(_cond_0, data_0, data_1) + en_2 = __phi(_cond_0, en_0, en_1) + + reg_val_0 = self.register(data_2, en_2) + _cond_2 = mode == Mode_t.CONST + __0_return_0 = const_, reg_val_0 + _cond_1 = mode == Mode_t.BYPASS + __0_return_1 = value, reg_val_0 + __0_return_2 = reg_val_0, reg_val_0 + return __phi(_cond_2, __0_return_0, __phi(_cond_1, __0_return_1, __0_return_2)) diff --git a/sam/onyx/.ast_tools/__call__140020545725632.py b/sam/onyx/.ast_tools/__call__140020545725632.py new file mode 100644 index 00000000..c8f4fa5a --- /dev/null +++ b/sam/onyx/.ast_tools/__call__140020545725632.py @@ -0,0 +1,16 @@ +def __call__( + self, mode: Mode_t, const_: T, value: T, clk_en: Bit +) -> (T, T): + _cond_0 = mode == Mode_t.DELAY + data_0, en_0 = value, clk_en + data_1, en_1 = value, Bit(0) + data_2 = __phi(_cond_0, data_0, data_1) + en_2 = __phi(_cond_0, en_0, en_1) + + reg_val_0 = self.register(data_2, en_2) + _cond_2 = mode == Mode_t.CONST + __0_return_0 = const_, reg_val_0 + _cond_1 = mode == Mode_t.BYPASS + __0_return_1 = value, reg_val_0 + __0_return_2 = reg_val_0, reg_val_0 + return __phi(_cond_2, __0_return_0, __phi(_cond_1, __0_return_1, __0_return_2)) diff --git a/sam/onyx/.ast_tools/__call__140154664120672.py b/sam/onyx/.ast_tools/__call__140154664120672.py new file mode 100644 index 00000000..112693cc --- /dev/null +++ b/sam/onyx/.ast_tools/__call__140154664120672.py @@ -0,0 +1,6 @@ +@name_outputs(lut_out=Bit) +def __call__(self, lut: LUT_t, bit0: Bit, bit1: Bit, bit2: Bit) -> Bit: + i_0 = IDX_t([bit0, bit1, bit2]) + i_1 = i_0.zext(5) + __0_return_0 = ((lut >> i_1) & 1)[0] + return __0_return_0 diff --git a/sam/onyx/.ast_tools/__call__140154664294576.py b/sam/onyx/.ast_tools/__call__140154664294576.py new file mode 100644 index 00000000..929fa036 --- /dev/null +++ b/sam/onyx/.ast_tools/__call__140154664294576.py @@ -0,0 +1,91 @@ +@name_outputs( + res=DataPy, + res_p=BitPy, + reg0_config_data=DataPy, + reg1_config_data=DataPy, + reg2_config_data=DataPy, +) +def __call__( + self, + inst: Const(Inst), + data0: DataPy = Data(0), + data1: DataPy = Data(0), + data2: DataPy = Data(0), + bit0: BitPy = Bit(0), + bit1: BitPy = Bit(0), + bit2: BitPy = Bit(0), + clk_en: Global(BitPy) = Bit(1), +) -> (DataPy, BitPy, DataPy, DataPy, DataPy): + + ra_0, ra_rdata_0 = self.rega(inst.rega, inst.data0, data0, clk_en) + rb_0, rb_rdata_0 = self.regb(inst.regb, inst.data1, data1, clk_en) + rc_0, rc_rdata_0 = self.regc(inst.regc, inst.data2, data2, clk_en) + + rd_0, rd_rdata_0 = self.regd(inst.regd, inst.bit0, bit0, clk_en) + re_0, re_rdata_0 = self.rege(inst.rege, inst.bit1, bit1, clk_en) + rf_0, rf_rdata_0 = self.regf(inst.regf, inst.bit2, bit2, clk_en) + + # set default values to each of the op kinds + alu_op_0 = ALU_t_c(ALU_t.Adc) + fpu_op_0 = FPU_t_c(FPU_t.FP_add) + fp_custom_op_0 = FPCustom_t_c(FPCustom_t.FGetMant) + _cond_1 = inst.op.alu.match + alu_op_1 = inst.op.alu.value + _cond_0 = inst.op.fpu.match + fpu_op_1 = inst.op.fpu.value + fp_custom_op_1 = inst.op.fp_custom.value + fp_custom_op_2 = __phi(_cond_0, fp_custom_op_0, fp_custom_op_1) + fpu_op_2 = __phi(_cond_0, fpu_op_1, fpu_op_0) + alu_op_2 = __phi(_cond_1, alu_op_1, alu_op_0) + fp_custom_op_3 = __phi(_cond_1, fp_custom_op_0, fp_custom_op_2) + fpu_op_3 = __phi(_cond_1, fpu_op_0, fpu_op_2) + + # calculate alu results + alu_res_0, alu_res_p_0, alu_Z_0, alu_N_0, C_0, alu_V_0 = self.alu( + alu_op_2, inst.signed, ra_0, rb_0, rc_0, rd_0 + ) + + fpu_res_0, fpu_N_0, fpu_Z_0 = self.fpu(fpu_op_3, ra_0, rb_0) + + fpc_res_0, fpc_res_p_0, fpc_V_0 = self.fp_custom( + fp_custom_op_3, inst.signed, ra_0, rb_0 + ) + + Z_0 = Bit(0) + N_0 = Bit(0) + V_0 = Bit(0) + res_p_0 = Bit(0) + res_0 = Data(0) + _cond_3 = inst.op.alu.match + Z_1 = alu_Z_0 + N_1 = alu_N_0 + V_1 = alu_V_0 + res_p_1 = alu_res_p_0 + res_1 = alu_res_0 + _cond_2 = inst.op.fpu.match + N_2 = fpu_N_0 + Z_2 = fpu_Z_0 + res_2 = fpu_res_0 + V_2 = fpc_V_0 + res_p_2 = fpc_res_p_0 + res_3 = fpc_res_0 + N_3 = __phi(_cond_2, N_2, N_0) + V_3 = __phi(_cond_2, V_0, V_2) + Z_3 = __phi(_cond_2, Z_2, Z_0) + res_4 = __phi(_cond_2, res_2, res_3) + res_p_3 = __phi(_cond_2, res_p_0, res_p_2) + N_4 = __phi(_cond_3, N_1, N_3) + V_4 = __phi(_cond_3, V_1, V_3) + Z_4 = __phi(_cond_3, Z_1, Z_3) + res_5 = __phi(_cond_3, res_1, res_4) + res_p_4 = __phi(_cond_3, res_p_1, res_p_3) + + # calculate lut results + lut_res_0 = self.lut(inst.lut, rd_0, re_0, rf_0) + + # calculate 1-bit result + cond_0 = self.cond(inst.cond, res_p_4, lut_res_0, Z_4, N_4, C_0, V_4) + + # return 16-bit result, 1-bit result + __0_return_0 = res_5, cond_0, ra_rdata_0, rb_rdata_0, rc_rdata_0 + return __0_return_0 diff --git a/sam/onyx/.ast_tools/__call__140154664427872.py b/sam/onyx/.ast_tools/__call__140154664427872.py new file mode 100644 index 00000000..2cbfdd97 --- /dev/null +++ b/sam/onyx/.ast_tools/__call__140154664427872.py @@ -0,0 +1,149 @@ +@name_outputs(res=Data, res_p=Bit, Z=Bit, N=Bit, C=Bit, V=Bit) +def __call__( + self, + alu: Const(ALU_t), + signed_: Const(Signed_t), + a: DataPy, + b: DataPy, + c: DataPy, + d: BitPy, +) -> (DataPy, BitPy, BitPy, BitPy, BitPy, BitPy): + _cond_0 = signed_ == Signed_t.signed + mula_0 = UData32(SData(a).sext(16)) + mulb_0 = UData32(SData(b).sext(16)) + mula_1 = UData(a).zext(16) + mulb_1 = UData(b).zext(16) + mula_2 = __phi(_cond_0, mula_0, mula_1) + mulb_2 = __phi(_cond_0, mulb_0, mulb_1) + mul_0 = mula_2 * mulb_2 + _cond_1 = signed_ == Signed_t.signed + lte_pred_0 = SData(a) <= SData(b) + lte_pred_1 = UData(a) <= UData(b) + lte_pred_2 = __phi(_cond_1, lte_pred_0, lte_pred_1) + min_ab_0 = lte_pred_2.ite(a, b) + _cond_2 = alu == ALU_t.CROP + max_in0_0 = min_ab_0 + max_in0_1 = b + max_in0_2 = __phi(_cond_2, max_in0_0, max_in0_1) + _cond_3 = signed_ == Signed_t.signed + gte_pred_0 = SData(max_in0_2) >= SData(c) + gte_pred_1 = UData(max_in0_2) >= UData(c) + gte_pred_2 = __phi(_cond_3, gte_pred_0, gte_pred_1) + max_bc_0 = gte_pred_2.ite(max_in0_2, c) + _cond_4 = alu == ALU_t.MULSHR + shr_in0_0 = mul_0[:16] + shr_in0_1 = a + shr_in0_2 = __phi(_cond_4, shr_in0_0, shr_in0_1) + _cond_5 = signed_ == Signed_t.signed + shr_0 = Data(SData(shr_in0_2) >> SData(c)) + shr_1 = Data(UData(shr_in0_2) >> UData(c)) + shr_2 = __phi(_cond_5, shr_0, shr_1) + _cond_6 = (alu == ALU_t.Sbc) | (alu == ALU_t.TSA) | (alu == ALU_t.TSS) + b_0 = ~b + b_1 = __phi(_cond_6, b_0, b) + + Cin_0 = d + + # factor out comman add + adder_res_0, adder_C_0 = UData(a).adc(UData(b_1), Cin_0) + _cond_7 = ( + (alu == ALU_t.TAA) + | (alu == ALU_t.TAS) + | (alu == ALU_t.TSA) + | (alu == ALU_t.TSS) + ) + adder2_in0_0 = adder_res_0 + adder2_in0_1 = mul_0[:16] + adder2_in0_2 = __phi(_cond_7, adder2_in0_0, adder2_in0_1) + _cond_8 = (alu == ALU_t.MULSUB) | (alu == ALU_t.TAS) | (alu == ALU_t.TSS) + adder2_in1_0 = ~c + Cin2_0 = Bit(1) + adder2_in1_1 = c + Cin2_1 = Bit(0) + Cin2_2 = __phi(_cond_8, Cin2_0, Cin2_1) + adder2_in1_2 = __phi(_cond_8, adder2_in1_0, adder2_in1_1) + + adder2_res_0, adder2_C_0 = UData(adder2_in0_2).adc(adder2_in1_2, Cin2_2) + + C_0 = Bit(0) + V_0 = Bit(0) + _cond_21 = (alu == ALU_t.Adc) | (alu == ALU_t.Sbc) + res_0, C_1 = adder_res_0, adder_C_0 + V_1 = overflow(a, b_1, res_0) + res_p_0 = C_1 + _cond_20 = alu == ALU_t.Mult0 + res_1, C_2, V_2 = mul_0[:16], Bit(0), Bit(0) + res_p_1 = C_2 + _cond_19 = alu == ALU_t.Mult1 + res_2, C_3, V_3 = mul_0[8:24], Bit(0), Bit(0) + res_p_2 = C_3 + _cond_18 = alu == ALU_t.Mult2 + res_3, C_4, V_4 = mul_0[16:32], Bit(0), Bit(0) + res_p_3 = C_4 + _cond_17 = alu == ALU_t.Abs + abs_pred_0 = SData(a) >= SData(0) + res_4, res_p_4 = abs_pred_0.ite(a, UInt[16](-SInt[16](a))), Bit(a[-1]) + _cond_16 = alu == ALU_t.Sel + res_5, res_p_5 = d.ite(a, b_1), Bit(0) + _cond_15 = alu == ALU_t.And + res_6, res_p_6 = a & b_1, Bit(0) + _cond_14 = alu == ALU_t.Or + res_7, res_p_7 = a | b_1, Bit(0) + _cond_13 = alu == ALU_t.XOr + res_8, res_p_8 = a ^ b_1, Bit(0) + _cond_12 = alu == ALU_t.SHR + res_9, res_p_9 = shr_2, Bit(0) + _cond_11 = alu == ALU_t.SHL + res_10, res_p_10 = a << b_1, Bit(0) + _cond_10 = ( + (alu == ALU_t.MULADD) + | (alu == ALU_t.MULSUB) + | (alu == ALU_t.TAA) + | (alu == ALU_t.TSA) + | (alu == ALU_t.TAS) + | (alu == ALU_t.TSS) + ) + res_11, res_p_11 = adder2_res_0, Bit(0) + _cond_9 = alu == ALU_t.CROP + res_12, res_p_12 = max_bc_0, Bit(0) + res_13, res_p_13 = shr_2, Bit(0) + res_14 = __phi(_cond_9, res_12, res_13) + res_p_14 = __phi(_cond_9, res_p_12, res_p_13) + res_15 = __phi(_cond_10, res_11, res_14) + res_p_15 = __phi(_cond_10, res_p_11, res_p_14) + res_16 = __phi(_cond_11, res_10, res_15) + res_p_16 = __phi(_cond_11, res_p_10, res_p_15) + res_17 = __phi(_cond_12, res_9, res_16) + res_p_17 = __phi(_cond_12, res_p_9, res_p_16) + res_18 = __phi(_cond_13, res_8, res_17) + res_p_18 = __phi(_cond_13, res_p_8, res_p_17) + res_19 = __phi(_cond_14, res_7, res_18) + res_p_19 = __phi(_cond_14, res_p_7, res_p_18) + res_20 = __phi(_cond_15, res_6, res_19) + res_p_20 = __phi(_cond_15, res_p_6, res_p_19) + res_21 = __phi(_cond_16, res_5, res_20) + res_p_21 = __phi(_cond_16, res_p_5, res_p_20) + res_22 = __phi(_cond_17, res_4, res_21) + res_p_22 = __phi(_cond_17, res_p_4, res_p_21) + C_5 = __phi(_cond_18, C_4, C_0) + V_5 = __phi(_cond_18, V_4, V_0) + res_23 = __phi(_cond_18, res_3, res_22) + res_p_23 = __phi(_cond_18, res_p_3, res_p_22) + C_6 = __phi(_cond_19, C_3, C_5) + V_6 = __phi(_cond_19, V_3, V_5) + res_24 = __phi(_cond_19, res_2, res_23) + res_p_24 = __phi(_cond_19, res_p_2, res_p_23) + C_7 = __phi(_cond_20, C_2, C_6) + V_7 = __phi(_cond_20, V_2, V_6) + res_25 = __phi(_cond_20, res_1, res_24) + res_p_25 = __phi(_cond_20, res_p_1, res_p_24) + C_8 = __phi(_cond_21, C_1, C_7) + V_8 = __phi(_cond_21, V_1, V_7) + res_26 = __phi(_cond_21, res_0, res_25) + res_p_26 = __phi(_cond_21, res_p_0, res_p_25) + + N_0 = Bit(res_26[-1]) + Z_0 = res_26 == SData(0) + + __0_return_0 = res_26, res_p_26, Z_0, N_0, C_8, V_8 + return __0_return_0 diff --git a/sam/onyx/.ast_tools/__call__140154666299744.py b/sam/onyx/.ast_tools/__call__140154666299744.py new file mode 100644 index 00000000..678a8cde --- /dev/null +++ b/sam/onyx/.ast_tools/__call__140154666299744.py @@ -0,0 +1,7 @@ +def __call__(self, in0: Data, in1: Data) -> Data: + in0_float_0 = cast(in0) + in1_float_0 = cast(in1) + out_float_0 = getattr(in0_float_0, op_name)(in1_float_0) + out_0 = out_float_0.reinterpret_as_bv() + __0_return_0 = out_0 + return __0_return_0 diff --git a/sam/onyx/.ast_tools/__call__140154666347536.py b/sam/onyx/.ast_tools/__call__140154666347536.py new file mode 100644 index 00000000..c159114e --- /dev/null +++ b/sam/onyx/.ast_tools/__call__140154666347536.py @@ -0,0 +1,40 @@ +@name_outputs(res=Data, N=Bit, Z=Bit) +def __call__(self, fpu_op: Const(FPU_t), a: Data, b: Data) -> (Data, Bit, Bit): + + a_inf_0 = fp_is_inf(a) + b_inf_0 = fp_is_inf(b) + a_neg_0 = fp_is_neg(a) + b_neg_0 = fp_is_neg(b) + + old_b_0 = b + neg_b_0 = (fpu_op == FPU_t.FP_sub) | (fpu_op == FPU_t.FP_cmp) | (fpu_op == FPU_t.FP_max) + _cond_0 = neg_b_0 + b_0 = b ^ (2 ** (16 - 1)) + b_1 = __phi(_cond_0, b_0, b) + Add_val_0 = self.Add(a, b_1) + Mul_val_0 = self.Mul(a, b_1) + _cond_3 = ( + (fpu_op == FPU_t.FP_add) + | (fpu_op == FPU_t.FP_sub) + | (fpu_op == FPU_t.FP_cmp) + ) + res_0 = Add_val_0 + _cond_2 = (fpu_op == FPU_t.FP_max) + _cond_1 = family.Bit(Add_val_0[-1]) + res_1 = old_b_0 + res_2 = a + res_3 = __phi(_cond_1, res_1, res_2) + res_4 = Mul_val_0 + res_5 = __phi(_cond_2, res_3, res_4) + res_6 = __phi(_cond_3, res_0, res_5) + + Z_0 = fp_is_zero(res_6) + _cond_5 = fpu_op == FPU_t.FP_cmp + _cond_4 = (a_inf_0 & b_inf_0) & (a_neg_0 == b_neg_0) + Z_1 = family.Bit(1) + Z_2 = __phi(_cond_4, Z_1, Z_0) + Z_3 = __phi(_cond_5, Z_2, Z_0) + + N_0 = family.Bit(res_6[-1]) + __0_return_0 = res_6, N_0, Z_3 + return __0_return_0 diff --git a/sam/onyx/.ast_tools/__call__140154670632384.py b/sam/onyx/.ast_tools/__call__140154670632384.py new file mode 100644 index 00000000..215df2df --- /dev/null +++ b/sam/onyx/.ast_tools/__call__140154670632384.py @@ -0,0 +1,44 @@ +@name_outputs(cond=Bit) +def __call__( + self, code: Cond_t, alu: Bit, lut: Bit, Z: Bit, N: Bit, C: Bit, V: Bit +) -> Bit: + _cond_18 = code == Cond_t.Z + __0_return_0 = Z + _cond_17 = code == Cond_t.Z_n + __0_return_1 = ~Z + _cond_16 = (code == Cond_t.C) | (code == Cond_t.UGE) + __0_return_2 = C + _cond_15 = (code == Cond_t.C_n) | (code == Cond_t.ULT) + __0_return_3 = ~C + _cond_14 = code == Cond_t._N + __0_return_4 = N + _cond_13 = code == Cond_t._N_n + __0_return_5 = ~N + _cond_12 = code == Cond_t.V + __0_return_6 = V + _cond_11 = code == Cond_t.V_n + __0_return_7 = ~V + _cond_10 = code == Cond_t.UGT + __0_return_8 = C & (~Z) + _cond_9 = code == Cond_t.ULE + __0_return_9 = (~C) | Z + _cond_8 = code == Cond_t.SGE + __0_return_10 = N == V + _cond_7 = code == Cond_t.SLT + __0_return_11 = N != V + _cond_6 = code == Cond_t.SGT + __0_return_12 = (~Z) & (N == V) + _cond_5 = code == Cond_t.SLE + __0_return_13 = Z | (N != V) + _cond_4 = code == Cond_t.ALU + __0_return_14 = alu + _cond_3 = code == Cond_t.LUT + __0_return_15 = lut + _cond_2 = code == Cond_t.FP_GE + __0_return_16 = ~N | Z + _cond_1 = code == Cond_t.FP_GT + __0_return_17 = ~N & ~Z + _cond_0 = code == Cond_t.FP_LE + __0_return_18 = N | Z + __0_return_19 = N & ~Z + return __phi(_cond_18, __0_return_0, __phi(_cond_17, __0_return_1, __phi(_cond_16, __0_return_2, __phi(_cond_15, __0_return_3, __phi(_cond_14, __0_return_4, __phi(_cond_13, __0_return_5, __phi(_cond_12, __0_return_6, __phi(_cond_11, __0_return_7, __phi(_cond_10, __0_return_8, __phi(_cond_9, __0_return_9, __phi(_cond_8, __0_return_10, __phi(_cond_7, __0_return_11, __phi(_cond_6, __0_return_12, __phi(_cond_5, __0_return_13, __phi(_cond_4, __0_return_14, __phi(_cond_3, __0_return_15, __phi(_cond_2, __0_return_16, __phi(_cond_1, __0_return_17, __phi(_cond_0, __0_return_18, __0_return_19))))))))))))))))))) diff --git a/sam/onyx/.ast_tools/__call__140154671532352.py b/sam/onyx/.ast_tools/__call__140154671532352.py new file mode 100644 index 00000000..678a8cde --- /dev/null +++ b/sam/onyx/.ast_tools/__call__140154671532352.py @@ -0,0 +1,7 @@ +def __call__(self, in0: Data, in1: Data) -> Data: + in0_float_0 = cast(in0) + in1_float_0 = cast(in1) + out_float_0 = getattr(in0_float_0, op_name)(in1_float_0) + out_0 = out_float_0.reinterpret_as_bv() + __0_return_0 = out_0 + return __0_return_0 diff --git a/sam/onyx/.ast_tools/__call__140154674464224.py b/sam/onyx/.ast_tools/__call__140154674464224.py new file mode 100644 index 00000000..c8f4fa5a --- /dev/null +++ b/sam/onyx/.ast_tools/__call__140154674464224.py @@ -0,0 +1,16 @@ +def __call__( + self, mode: Mode_t, const_: T, value: T, clk_en: Bit +) -> (T, T): + _cond_0 = mode == Mode_t.DELAY + data_0, en_0 = value, clk_en + data_1, en_1 = value, Bit(0) + data_2 = __phi(_cond_0, data_0, data_1) + en_2 = __phi(_cond_0, en_0, en_1) + + reg_val_0 = self.register(data_2, en_2) + _cond_2 = mode == Mode_t.CONST + __0_return_0 = const_, reg_val_0 + _cond_1 = mode == Mode_t.BYPASS + __0_return_1 = value, reg_val_0 + __0_return_2 = reg_val_0, reg_val_0 + return __phi(_cond_2, __0_return_0, __phi(_cond_1, __0_return_1, __0_return_2)) diff --git a/sam/onyx/.ast_tools/__call__140154676057280.py b/sam/onyx/.ast_tools/__call__140154676057280.py new file mode 100644 index 00000000..c8f4fa5a --- /dev/null +++ b/sam/onyx/.ast_tools/__call__140154676057280.py @@ -0,0 +1,16 @@ +def __call__( + self, mode: Mode_t, const_: T, value: T, clk_en: Bit +) -> (T, T): + _cond_0 = mode == Mode_t.DELAY + data_0, en_0 = value, clk_en + data_1, en_1 = value, Bit(0) + data_2 = __phi(_cond_0, data_0, data_1) + en_2 = __phi(_cond_0, en_0, en_1) + + reg_val_0 = self.register(data_2, en_2) + _cond_2 = mode == Mode_t.CONST + __0_return_0 = const_, reg_val_0 + _cond_1 = mode == Mode_t.BYPASS + __0_return_1 = value, reg_val_0 + __0_return_2 = reg_val_0, reg_val_0 + return __phi(_cond_2, __0_return_0, __phi(_cond_1, __0_return_1, __0_return_2)) diff --git a/sam/onyx/.ast_tools/__call__140154676060016.py b/sam/onyx/.ast_tools/__call__140154676060016.py new file mode 100644 index 00000000..0e11d13a --- /dev/null +++ b/sam/onyx/.ast_tools/__call__140154676060016.py @@ -0,0 +1,236 @@ +@name_outputs(res=Data, res_p=Bit, V=Bit) +def __call__( + self, op: Const(FPCustom_t), signed_: Const(Signed_t), a: Data, b: Data +) -> (Data, Bit, Bit): + _cond_27 = op == FPCustom_t.FCnvExp2F + expa0_0 = BitVector[8](a[7:15]) + biased_exp0_0 = SInt[9](expa0_0.zext(1)) + unbiased_exp0_0 = SInt[9](biased_exp0_0 - SInt[9](127)) + _cond_0 = unbiased_exp0_0 < 0 + sign_0 = BitVector[16](0x8000) + abs_exp0_0 = -unbiased_exp0_0 + sign_1 = BitVector[16](0x0000) + abs_exp0_1 = unbiased_exp0_0 + abs_exp0_2 = __phi(_cond_0, abs_exp0_0, abs_exp0_1) + sign_2 = __phi(_cond_0, sign_0, sign_1) + abs_exp_0 = BitVector[8](abs_exp0_2[0:8]) + scale_0 = SInt[16](-127) + _cond_1 = abs_exp_0[0] == Bit(1) + scale_1 = SInt[16](0) + scale_2 = __phi(_cond_1, scale_1, scale_0) + _cond_2 = abs_exp_0[1] == Bit(1) + scale_3 = SInt[16](1) + scale_4 = __phi(_cond_2, scale_3, scale_2) + _cond_3 = abs_exp_0[2] == Bit(1) + scale_5 = SInt[16](2) + scale_6 = __phi(_cond_3, scale_5, scale_4) + _cond_4 = abs_exp_0[3] == Bit(1) + scale_7 = SInt[16](3) + scale_8 = __phi(_cond_4, scale_7, scale_6) + _cond_5 = abs_exp_0[4] == Bit(1) + scale_9 = SInt[16](4) + scale_10 = __phi(_cond_5, scale_9, scale_8) + _cond_6 = abs_exp_0[5] == Bit(1) + scale_11 = SInt[16](5) + scale_12 = __phi(_cond_6, scale_11, scale_10) + _cond_7 = abs_exp_0[6] == Bit(1) + scale_13 = SInt[16](6) + scale_14 = __phi(_cond_7, scale_13, scale_12) + _cond_8 = abs_exp_0[7] == Bit(1) + scale_15 = SInt[16](7) + scale_16 = __phi(_cond_8, scale_15, scale_14) + normmant_mul_left_0 = SInt[16](abs_exp_0) + normmant_mul_right_0 = SInt[16](7) - scale_16 + normmant_mask_0 = SInt[16](0x7F) + _cond_9 = signed_ == Signed_t.signed + sign_3 = BitVector[16](a & 0x8000) + sign_4 = BitVector[16](0) + sign_5 = __phi(_cond_9, sign_3, sign_4) + _cond_10 = sign_5[15] == Bit(1) + abs_input_0 = BitVector[16](-SInt[16](a)) + abs_input_1 = BitVector[16](a) + abs_input_2 = __phi(_cond_10, abs_input_0, abs_input_1) + scale_17 = SInt[16](-127) + _cond_11 = abs_input_2[0] == Bit(1) + scale_18 = SInt[16](0) + scale_19 = __phi(_cond_11, scale_18, scale_17) + _cond_12 = abs_input_2[1] == Bit(1) + scale_20 = SInt[16](1) + scale_21 = __phi(_cond_12, scale_20, scale_19) + _cond_13 = abs_input_2[2] == Bit(1) + scale_22 = SInt[16](2) + scale_23 = __phi(_cond_13, scale_22, scale_21) + _cond_14 = abs_input_2[3] == Bit(1) + scale_24 = SInt[16](3) + scale_25 = __phi(_cond_14, scale_24, scale_23) + _cond_15 = abs_input_2[4] == Bit(1) + scale_26 = SInt[16](4) + scale_27 = __phi(_cond_15, scale_26, scale_25) + _cond_16 = abs_input_2[5] == Bit(1) + scale_28 = SInt[16](5) + scale_29 = __phi(_cond_16, scale_28, scale_27) + _cond_17 = abs_input_2[6] == Bit(1) + scale_30 = SInt[16](6) + scale_31 = __phi(_cond_17, scale_30, scale_29) + _cond_18 = abs_input_2[7] == Bit(1) + scale_32 = SInt[16](7) + scale_33 = __phi(_cond_18, scale_32, scale_31) + _cond_19 = abs_input_2[8] == Bit(1) + scale_34 = SInt[16](8) + scale_35 = __phi(_cond_19, scale_34, scale_33) + _cond_20 = abs_input_2[9] == Bit(1) + scale_36 = SInt[16](9) + scale_37 = __phi(_cond_20, scale_36, scale_35) + _cond_21 = abs_input_2[10] == Bit(1) + scale_38 = SInt[16](10) + scale_39 = __phi(_cond_21, scale_38, scale_37) + _cond_22 = abs_input_2[11] == Bit(1) + scale_40 = SInt[16](11) + scale_41 = __phi(_cond_22, scale_40, scale_39) + _cond_23 = abs_input_2[12] == Bit(1) + scale_42 = SInt[16](12) + scale_43 = __phi(_cond_23, scale_42, scale_41) + _cond_24 = abs_input_2[13] == Bit(1) + scale_44 = SInt[16](13) + scale_45 = __phi(_cond_24, scale_44, scale_43) + _cond_25 = abs_input_2[14] == Bit(1) + scale_46 = SInt[16](14) + scale_47 = __phi(_cond_25, scale_46, scale_45) + _cond_26 = abs_input_2[15] == Bit(1) + scale_48 = SInt[16](15) + scale_49 = __phi(_cond_26, scale_48, scale_47) + normmant_mul_left_1 = SInt[16](abs_input_2) + normmant_mul_right_1 = SInt[16](15) - scale_49 + normmant_mask_1 = SInt[16](0x7F00) + normmant_mask_2 = __phi(_cond_27, normmant_mask_0, normmant_mask_1) + normmant_mul_left_2 = __phi(_cond_27, normmant_mul_left_0, normmant_mul_left_1) + normmant_mul_right_2 = __phi(_cond_27, normmant_mul_right_0, normmant_mul_right_1) + scale_50 = __phi(_cond_27, scale_16, scale_49) + sign_6 = __phi(_cond_27, sign_2, sign_5) + _cond_28 = scale_50 >= 0 + normmant_0 = BitVector[16]( + (normmant_mul_left_2 << normmant_mul_right_2) & normmant_mask_2 + ) + normmant_1 = BitVector[16](0) + normmant_2 = __phi(_cond_28, normmant_0, normmant_1) + _cond_29 = op == FPCustom_t.FCnvInt2F + normmant_3 = BitVector[16](normmant_2) >> 8 + normmant_4 = __phi(_cond_29, normmant_3, normmant_2) + + biased_scale_0 = scale_50 + 127 + to_float_result_0 = ( + sign_6 | ((BitVector[16](biased_scale_0) << 7) & (0xFF << 7)) | normmant_4 + ) + + V_0 = Bit(0) + _cond_39 = op == FPCustom_t.FGetMant + res_0, res_p_0 = (a & 0x7F), Bit(0) + _cond_38 = op == FPCustom_t.FAddIExp + sign_7 = BitVector[16]((a & 0x8000)) + exp_0 = UData(a)[7:15] + exp_check_0 = exp_0.zext(1) + exp_1 = exp_0 + UData(b)[0:8] + exp_check_1 = exp_check_0 + UData(b)[0:9] + # Augassign not supported by magma yet + # exp += SInt[8](b[0:8]) + # exp_check += SInt[9](b[0:9]) + exp_shift_0 = BitVector[16](exp_1) + exp_shift_1 = exp_shift_0 << 7 + mant_0 = BitVector[16]((a & 0x7F)) + res_1, res_p_1 = (sign_7 | exp_shift_1 | mant_0), (exp_check_1 > 255) + _cond_37 = op == FPCustom_t.FSubExp + signa_0 = BitVector[16]((a & 0x8000)) + expa_0 = UData(a)[7:15] + signb_0 = BitVector[16]((b & 0x8000)) + expb_0 = UData(b)[7:15] + expa_1 = expa_0 - expb_0 + 127 + exp_shift_2 = BitVector[16](expa_1) + exp_shift_3 = exp_shift_2 << 7 + manta_0 = BitVector[16]((a & 0x7F)) + res_2, res_p_2 = ((signa_0 | signb_0) | exp_shift_3 | manta_0), Bit(0) + _cond_36 = op == FPCustom_t.FCnvExp2F + res_3, res_p_3 = to_float_result_0, Bit(0) + _cond_35 = op == FPCustom_t.FGetFInt + signa_1 = BitVector[16]((a & 0x8000)) + manta_1 = BitVector[16]((a & 0x7F)) | 0x80 + expa0_1 = UData(a)[7:15] + biased_exp0_1 = SInt[9](expa0_1.zext(1)) + unbiased_exp0_1 = SInt[9](biased_exp0_1 - SInt[9](127)) + _cond_30 = unbiased_exp0_1 < 0 + manta_shift0_0 = BitVector[23](0) + manta_shift0_1 = BitVector[23](manta_1) << BitVector[23](unbiased_exp0_1) + manta_shift0_2 = __phi(_cond_30, manta_shift0_0, manta_shift0_1) + unsigned_res0_0 = BitVector[23](manta_shift0_2 >> BitVector[23](7)) + unsigned_res_0 = BitVector[16](unsigned_res0_0[0:16]) + _cond_31 = signa_1 == 0x8000 + signed_res_0 = -SInt[16](unsigned_res_0) + signed_res_1 = SInt[16](unsigned_res_0) + signed_res_2 = __phi(_cond_31, signed_res_0, signed_res_1) + # We are not checking for overflow when converting to int + res_4, res_p_4, V_1 = signed_res_2, Bit(0), (expa0_1 > BitVector[8](142)) + _cond_34 = op == FPCustom_t.FGetFFrac + signa_2 = BitVector[16]((a & 0x8000)) + manta_2 = BitVector[16]((a & 0x7F)) | 0x80 + expa0_2 = BitVector[8](a[7:15]) + biased_exp0_2 = SInt[9](expa0_2.zext(1)) + unbiased_exp0_2 = SInt[9](biased_exp0_2 - SInt[9](127)) + _cond_32 = unbiased_exp0_2 < 0 + manta_shift1_0 = BitVector[16](manta_2) >> BitVector[16](-unbiased_exp0_2) + manta_shift1_1 = BitVector[16](manta_2) << BitVector[16](unbiased_exp0_2) + manta_shift1_2 = __phi(_cond_32, manta_shift1_0, manta_shift1_1) + unsigned_res_1 = BitVector[16]((manta_shift1_2 & 0x07F)) + _cond_33 = signa_2 == 0x8000 + signed_res_3 = -SInt[16](unsigned_res_1) + signed_res_4 = SInt[16](unsigned_res_1) + signed_res_5 = __phi(_cond_33, signed_res_3, signed_res_4) + + # We are not checking for overflow when converting to int + res_5, res_p_5 = signed_res_5, Bit(0) + res_6, res_p_6 = to_float_result_0, Bit(0) + biased_exp0_3 = __phi(_cond_34, biased_exp0_2, biased_exp0_0) + expa0_3 = __phi(_cond_34, expa0_2, expa0_0) + res_7 = __phi(_cond_34, res_5, res_6) + res_p_7 = __phi(_cond_34, res_p_5, res_p_6) + unbiased_exp0_3 = __phi(_cond_34, unbiased_exp0_2, unbiased_exp0_0) + V_2 = __phi(_cond_35, V_1, V_0) + biased_exp0_4 = __phi(_cond_35, biased_exp0_1, biased_exp0_3) + expa0_4 = __phi(_cond_35, expa0_1, expa0_3) + manta_3 = __phi(_cond_35, manta_1, manta_2) + res_8 = __phi(_cond_35, res_4, res_7) + res_p_8 = __phi(_cond_35, res_p_4, res_p_7) + signa_3 = __phi(_cond_35, signa_1, signa_2) + signed_res_6 = __phi(_cond_35, signed_res_2, signed_res_5) + unbiased_exp0_4 = __phi(_cond_35, unbiased_exp0_1, unbiased_exp0_3) + unsigned_res_2 = __phi(_cond_35, unsigned_res_0, unsigned_res_1) + V_3 = __phi(_cond_36, V_0, V_2) + biased_exp0_5 = __phi(_cond_36, biased_exp0_0, biased_exp0_4) + expa0_5 = __phi(_cond_36, expa0_0, expa0_4) + res_9 = __phi(_cond_36, res_3, res_8) + res_p_9 = __phi(_cond_36, res_p_3, res_p_8) + unbiased_exp0_5 = __phi(_cond_36, unbiased_exp0_0, unbiased_exp0_4) + V_4 = __phi(_cond_37, V_0, V_3) + biased_exp0_6 = __phi(_cond_37, biased_exp0_0, biased_exp0_5) + expa0_6 = __phi(_cond_37, expa0_0, expa0_5) + manta_4 = __phi(_cond_37, manta_0, manta_3) + res_10 = __phi(_cond_37, res_2, res_9) + res_p_10 = __phi(_cond_37, res_p_2, res_p_9) + signa_4 = __phi(_cond_37, signa_0, signa_3) + unbiased_exp0_6 = __phi(_cond_37, unbiased_exp0_0, unbiased_exp0_5) + V_5 = __phi(_cond_38, V_0, V_4) + biased_exp0_7 = __phi(_cond_38, biased_exp0_0, biased_exp0_6) + exp_shift_4 = __phi(_cond_38, exp_shift_1, exp_shift_3) + expa0_7 = __phi(_cond_38, expa0_0, expa0_6) + res_11 = __phi(_cond_38, res_1, res_10) + res_p_11 = __phi(_cond_38, res_p_1, res_p_10) + sign_8 = __phi(_cond_38, sign_7, sign_6) + unbiased_exp0_7 = __phi(_cond_38, unbiased_exp0_0, unbiased_exp0_6) + V_6 = __phi(_cond_39, V_0, V_5) + biased_exp0_8 = __phi(_cond_39, biased_exp0_0, biased_exp0_7) + expa0_8 = __phi(_cond_39, expa0_0, expa0_7) + res_12 = __phi(_cond_39, res_0, res_11) + res_p_12 = __phi(_cond_39, res_p_0, res_p_11) + sign_9 = __phi(_cond_39, sign_6, sign_8) + unbiased_exp0_8 = __phi(_cond_39, unbiased_exp0_0, unbiased_exp0_7) + + __0_return_0 = res_12, res_p_12, V_6 + return __0_return_0 diff --git a/sam/onyx/.ast_tools/__init__140020533738944.py b/sam/onyx/.ast_tools/__init__140020533738944.py new file mode 100644 index 00000000..5b8fa05f --- /dev/null +++ b/sam/onyx/.ast_tools/__init__140020533738944.py @@ -0,0 +1,3 @@ +def __init__(self): + self._input_vals = None + self._output_vals = None diff --git a/sam/onyx/.ast_tools/__init__140020533770704.py b/sam/onyx/.ast_tools/__init__140020533770704.py new file mode 100644 index 00000000..5b8fa05f --- /dev/null +++ b/sam/onyx/.ast_tools/__init__140020533770704.py @@ -0,0 +1,3 @@ +def __init__(self): + self._input_vals = None + self._output_vals = None diff --git a/sam/onyx/.ast_tools/__init__140020542815392.py b/sam/onyx/.ast_tools/__init__140020542815392.py new file mode 100644 index 00000000..64feacbc --- /dev/null +++ b/sam/onyx/.ast_tools/__init__140020542815392.py @@ -0,0 +1,3 @@ +def __init__(self): + self.Add: FPAdd = FPAdd() + self.Mul: FPU_Mul_10_Bit_Rounding = FPU_Mul_10_Bit_Rounding() diff --git a/sam/onyx/.ast_tools/__init__140020546324656.py b/sam/onyx/.ast_tools/__init__140020546324656.py new file mode 100644 index 00000000..b795dcb9 --- /dev/null +++ b/sam/onyx/.ast_tools/__init__140020546324656.py @@ -0,0 +1,2 @@ +def __init__(self): + self.register: Reg = Reg() diff --git a/sam/onyx/.ast_tools/__init__140020552380624.py b/sam/onyx/.ast_tools/__init__140020552380624.py new file mode 100644 index 00000000..b795dcb9 --- /dev/null +++ b/sam/onyx/.ast_tools/__init__140020552380624.py @@ -0,0 +1,2 @@ +def __init__(self): + self.register: Reg = Reg() diff --git a/sam/onyx/.ast_tools/__init__140154664293712.py b/sam/onyx/.ast_tools/__init__140154664293712.py new file mode 100644 index 00000000..d8f39601 --- /dev/null +++ b/sam/onyx/.ast_tools/__init__140154664293712.py @@ -0,0 +1,22 @@ +def __init__(self): + + # Data registers + self.rega: DataReg = DataReg() + self.regb: DataReg = DataReg() + self.regc: DataReg = DataReg() + + # Bit Registers + self.regd: BitReg = BitReg() + self.rege: BitReg = BitReg() + self.regf: BitReg = BitReg() + + # Execution + self.alu: ALU = ALU() + self.fpu: FPU = FPU() + self.fp_custom: FPCustom = FPCustom() + + # Lut + self.lut: LUT = LUT() + + # Condition code + self.cond: Cond = Cond() diff --git a/sam/onyx/.ast_tools/__init__140154666302624.py b/sam/onyx/.ast_tools/__init__140154666302624.py new file mode 100644 index 00000000..64feacbc --- /dev/null +++ b/sam/onyx/.ast_tools/__init__140154666302624.py @@ -0,0 +1,3 @@ +def __init__(self): + self.Add: FPAdd = FPAdd() + self.Mul: FPU_Mul_10_Bit_Rounding = FPU_Mul_10_Bit_Rounding() diff --git a/sam/onyx/.ast_tools/__init__140154671533504.py b/sam/onyx/.ast_tools/__init__140154671533504.py new file mode 100644 index 00000000..5b8fa05f --- /dev/null +++ b/sam/onyx/.ast_tools/__init__140154671533504.py @@ -0,0 +1,3 @@ +def __init__(self): + self._input_vals = None + self._output_vals = None diff --git a/sam/onyx/.ast_tools/__init__140154671569360.py b/sam/onyx/.ast_tools/__init__140154671569360.py new file mode 100644 index 00000000..5b8fa05f --- /dev/null +++ b/sam/onyx/.ast_tools/__init__140154671569360.py @@ -0,0 +1,3 @@ +def __init__(self): + self._input_vals = None + self._output_vals = None diff --git a/sam/onyx/.ast_tools/__init__140154675218608.py b/sam/onyx/.ast_tools/__init__140154675218608.py new file mode 100644 index 00000000..b795dcb9 --- /dev/null +++ b/sam/onyx/.ast_tools/__init__140154675218608.py @@ -0,0 +1,2 @@ +def __init__(self): + self.register: Reg = Reg() diff --git a/sam/onyx/.ast_tools/__init__140154681262288.py b/sam/onyx/.ast_tools/__init__140154681262288.py new file mode 100644 index 00000000..b795dcb9 --- /dev/null +++ b/sam/onyx/.ast_tools/__init__140154681262288.py @@ -0,0 +1,2 @@ +def __init__(self): + self.register: Reg = Reg() diff --git a/sam/onyx/.magma/ExclusiveNodeFanout_H2-kratos.sv b/sam/onyx/.magma/ExclusiveNodeFanout_H2-kratos.sv new file mode 100644 index 00000000..6182f382 --- /dev/null +++ b/sam/onyx/.magma/ExclusiveNodeFanout_H2-kratos.sv @@ -0,0 +1,9 @@ +module ExclusiveNodeFanout_H2 ( + input logic [1:0] I, + input logic [1:0] S, + output logic O +); + +assign O = (I[0] & S[0]) | (I[1] & S[1]); +endmodule // ExclusiveNodeFanout_H2 + diff --git a/sam/onyx/.magma/FanoutHash_1130FCC7DFE98006-kratos.sv b/sam/onyx/.magma/FanoutHash_1130FCC7DFE98006-kratos.sv new file mode 100644 index 00000000..79e5bc79 --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_1130FCC7DFE98006-kratos.sv @@ -0,0 +1,37 @@ +module FanoutHash_1130FCC7DFE98006 ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +assign sel0 = (~E0) | (~S0[1]) | I0; +assign sel1 = (~E1) | (~S1[2]) | I1; +assign sel2 = (~E2) | (~S2[0]) | I2; +assign sel3 = (~E3) | (~S3[6]) | I3; +assign sel4 = (~E4) | (~S4[6]) | I4; +assign sel5 = (~E5) | (~S5[6]) | I5; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5; +endmodule // FanoutHash_1130FCC7DFE98006 + diff --git a/sam/onyx/.magma/FanoutHash_11B554A18790BBBC-kratos.sv b/sam/onyx/.magma/FanoutHash_11B554A18790BBBC-kratos.sv new file mode 100644 index 00000000..9dfab7a9 --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_11B554A18790BBBC-kratos.sv @@ -0,0 +1,37 @@ +module FanoutHash_11B554A18790BBBC ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +assign sel0 = (~E0) | (~S0[1]) | I0; +assign sel1 = (~E1) | (~S1[1]) | I1; +assign sel2 = (~E2) | (~S2[2]) | I2; +assign sel3 = (~E3) | (~S3[18]) | I3; +assign sel4 = (~E4) | (~S4[18]) | I4; +assign sel5 = (~E5) | (~S5[18]) | I5; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5; +endmodule // FanoutHash_11B554A18790BBBC + diff --git a/sam/onyx/.magma/FanoutHash_13B77C2790BDE4E2-kratos.sv b/sam/onyx/.magma/FanoutHash_13B77C2790BDE4E2-kratos.sv new file mode 100644 index 00000000..13cb393a --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_13B77C2790BDE4E2-kratos.sv @@ -0,0 +1,37 @@ +module FanoutHash_13B77C2790BDE4E2 ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +assign sel0 = (~E0) | (~S0[1]) | I0; +assign sel1 = (~E1) | (~S1[2]) | I1; +assign sel2 = (~E2) | (~S2[1]) | I2; +assign sel3 = (~E3) | (~S3[13]) | I3; +assign sel4 = (~E4) | (~S4[13]) | I4; +assign sel5 = (~E5) | (~S5[13]) | I5; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5; +endmodule // FanoutHash_13B77C2790BDE4E2 + diff --git a/sam/onyx/.magma/FanoutHash_14EBE1E8E49CA541-kratos.sv b/sam/onyx/.magma/FanoutHash_14EBE1E8E49CA541-kratos.sv new file mode 100644 index 00000000..2fdff0f7 --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_14EBE1E8E49CA541-kratos.sv @@ -0,0 +1,22 @@ +module FanoutHash_14EBE1E8E49CA541 ( + input logic E0, + input logic E1, + input logic E2, + input logic I0, + input logic I1, + input logic I2, + input logic [31:0] S0, + input logic [31:0] S1, + input logic [31:0] S2, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +assign sel0 = (~E0) | (~S0[20]) | I0; +assign sel1 = (~E1) | (~S1[20]) | I1; +assign sel2 = (~E2) | (~S2[20]) | I2; +assign O = sel0 & sel1 & sel2; +endmodule // FanoutHash_14EBE1E8E49CA541 + diff --git a/sam/onyx/.magma/FanoutHash_1816466D6957000-kratos.sv b/sam/onyx/.magma/FanoutHash_1816466D6957000-kratos.sv new file mode 100644 index 00000000..8ea373f6 --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_1816466D6957000-kratos.sv @@ -0,0 +1,42 @@ +module FanoutHash_1816466D6957000 ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic E6, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic I6, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + input logic [31:0] S6, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +logic sel6; +assign sel0 = (~E0) | (~S0[2]) | I0; +assign sel1 = (~E1) | (~S1[2]) | I1; +assign sel2 = (~E2) | (~S2[2]) | I2; +assign sel3 = (~E3) | (~S3[19]) | I3; +assign sel4 = (~E4) | (~S4[19]) | I4; +assign sel5 = (~E5) | (~S5[19]) | I5; +assign sel6 = (~E6) | (~S6[19]) | I6; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6; +endmodule // FanoutHash_1816466D6957000 + diff --git a/sam/onyx/.magma/FanoutHash_184DFC10DAF19BE9-kratos.sv b/sam/onyx/.magma/FanoutHash_184DFC10DAF19BE9-kratos.sv new file mode 100644 index 00000000..3bb0346f --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_184DFC10DAF19BE9-kratos.sv @@ -0,0 +1,42 @@ +module FanoutHash_184DFC10DAF19BE9 ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic E6, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic I6, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + input logic [31:0] S6, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +logic sel6; +assign sel0 = (~E0) | (~S0[0]) | I0; +assign sel1 = (~E1) | (~S1[2]) | I1; +assign sel2 = (~E2) | (~S2[2]) | I2; +assign sel3 = (~E3) | (~S3[16]) | I3; +assign sel4 = (~E4) | (~S4[16]) | I4; +assign sel5 = (~E5) | (~S5[16]) | I5; +assign sel6 = (~E6) | (~S6[16]) | I6; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6; +endmodule // FanoutHash_184DFC10DAF19BE9 + diff --git a/sam/onyx/.magma/FanoutHash_1A568579D8E9714B-kratos.sv b/sam/onyx/.magma/FanoutHash_1A568579D8E9714B-kratos.sv new file mode 100644 index 00000000..2360ad99 --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_1A568579D8E9714B-kratos.sv @@ -0,0 +1,37 @@ +module FanoutHash_1A568579D8E9714B ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +assign sel0 = (~E0) | (~S0[0]) | I0; +assign sel1 = (~E1) | (~S1[2]) | I1; +assign sel2 = (~E2) | (~S2[1]) | I2; +assign sel3 = (~E3) | (~S3[7]) | I3; +assign sel4 = (~E4) | (~S4[7]) | I4; +assign sel5 = (~E5) | (~S5[7]) | I5; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5; +endmodule // FanoutHash_1A568579D8E9714B + diff --git a/sam/onyx/.magma/FanoutHash_1B10C32F008C11AC-kratos.sv b/sam/onyx/.magma/FanoutHash_1B10C32F008C11AC-kratos.sv new file mode 100644 index 00000000..f1625866 --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_1B10C32F008C11AC-kratos.sv @@ -0,0 +1,37 @@ +module FanoutHash_1B10C32F008C11AC ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +assign sel0 = (~E0) | (~S0[1]) | I0; +assign sel1 = (~E1) | (~S1[1]) | I1; +assign sel2 = (~E2) | (~S2[2]) | I2; +assign sel3 = (~E3) | (~S3[17]) | I3; +assign sel4 = (~E4) | (~S4[17]) | I4; +assign sel5 = (~E5) | (~S5[17]) | I5; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5; +endmodule // FanoutHash_1B10C32F008C11AC + diff --git a/sam/onyx/.magma/FanoutHash_1EBD0270673B29D7-kratos.sv b/sam/onyx/.magma/FanoutHash_1EBD0270673B29D7-kratos.sv new file mode 100644 index 00000000..40c9a795 --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_1EBD0270673B29D7-kratos.sv @@ -0,0 +1,108 @@ +module FanoutHash_1EBD0270673B29D7 ( + input logic E0, + input logic E1, + input logic E10, + input logic E11, + input logic E12, + input logic E13, + input logic E14, + input logic E15, + input logic E16, + input logic E17, + input logic E18, + input logic E19, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic E6, + input logic E7, + input logic E8, + input logic E9, + input logic I0, + input logic I1, + input logic I10, + input logic I11, + input logic I12, + input logic I13, + input logic I14, + input logic I15, + input logic I16, + input logic I17, + input logic I18, + input logic I19, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic I6, + input logic I7, + input logic I8, + input logic I9, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S10, + input logic [7:0] S11, + input logic [7:0] S12, + input logic [7:0] S13, + input logic [7:0] S14, + input logic [7:0] S15, + input logic [7:0] S16, + input logic [7:0] S17, + input logic [7:0] S18, + input logic [7:0] S19, + input logic [7:0] S2, + input logic [7:0] S3, + input logic [7:0] S4, + input logic [7:0] S5, + input logic [7:0] S6, + input logic [7:0] S7, + input logic [7:0] S8, + input logic [7:0] S9, + output logic O +); + +logic sel0; +logic sel1; +logic sel10; +logic sel11; +logic sel12; +logic sel13; +logic sel14; +logic sel15; +logic sel16; +logic sel17; +logic sel18; +logic sel19; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +logic sel6; +logic sel7; +logic sel8; +logic sel9; +assign sel0 = (~E0) | (~S0[6]) | I0; +assign sel1 = (~E1) | (~S1[6]) | I1; +assign sel2 = (~E2) | (~S2[6]) | I2; +assign sel3 = (~E3) | (~S3[6]) | I3; +assign sel4 = (~E4) | (~S4[6]) | I4; +assign sel5 = (~E5) | (~S5[6]) | I5; +assign sel6 = (~E6) | (~S6[6]) | I6; +assign sel7 = (~E7) | (~S7[6]) | I7; +assign sel8 = (~E8) | (~S8[6]) | I8; +assign sel9 = (~E9) | (~S9[6]) | I9; +assign sel10 = (~E10) | (~S10[6]) | I10; +assign sel11 = (~E11) | (~S11[6]) | I11; +assign sel12 = (~E12) | (~S12[6]) | I12; +assign sel13 = (~E13) | (~S13[6]) | I13; +assign sel14 = (~E14) | (~S14[6]) | I14; +assign sel15 = (~E15) | (~S15[6]) | I15; +assign sel16 = (~E16) | (~S16[6]) | I16; +assign sel17 = (~E17) | (~S17[6]) | I17; +assign sel18 = (~E18) | (~S18[6]) | I18; +assign sel19 = (~E19) | (~S19[6]) | I19; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8 & sel9 & sel10 & + sel11 & sel12 & sel13 & sel14 & sel15 & sel16 & sel17 & sel18 & sel19; +endmodule // FanoutHash_1EBD0270673B29D7 + diff --git a/sam/onyx/.magma/FanoutHash_244497FCED8BEB80-kratos.sv b/sam/onyx/.magma/FanoutHash_244497FCED8BEB80-kratos.sv new file mode 100644 index 00000000..54a42b92 --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_244497FCED8BEB80-kratos.sv @@ -0,0 +1,52 @@ +module FanoutHash_244497FCED8BEB80 ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic E6, + input logic E7, + input logic E8, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic I6, + input logic I7, + input logic I8, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + input logic [31:0] S6, + input logic [31:0] S7, + input logic [31:0] S8, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +logic sel6; +logic sel7; +logic sel8; +assign sel0 = (~E0) | (~S0[0]) | I0; +assign sel1 = (~E1) | (~S1[2]) | I1; +assign sel2 = (~E2) | (~S2[2]) | I2; +assign sel3 = (~E3) | (~S3[16]) | I3; +assign sel4 = (~E4) | (~S4[16]) | I4; +assign sel5 = (~E5) | (~S5[16]) | I5; +assign sel6 = (~E6) | (~S6[16]) | I6; +assign sel7 = (~E7) | (~S7[16]) | I7; +assign sel8 = (~E8) | (~S8[16]) | I8; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8; +endmodule // FanoutHash_244497FCED8BEB80 + diff --git a/sam/onyx/.magma/FanoutHash_245560850976C879-kratos.sv b/sam/onyx/.magma/FanoutHash_245560850976C879-kratos.sv new file mode 100644 index 00000000..c65009f1 --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_245560850976C879-kratos.sv @@ -0,0 +1,52 @@ +module FanoutHash_245560850976C879 ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic E6, + input logic E7, + input logic E8, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic I6, + input logic I7, + input logic I8, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + input logic [31:0] S6, + input logic [31:0] S7, + input logic [31:0] S8, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +logic sel6; +logic sel7; +logic sel8; +assign sel0 = (~E0) | (~S0[1]) | I0; +assign sel1 = (~E1) | (~S1[2]) | I1; +assign sel2 = (~E2) | (~S2[0]) | I2; +assign sel3 = (~E3) | (~S3[6]) | I3; +assign sel4 = (~E4) | (~S4[6]) | I4; +assign sel5 = (~E5) | (~S5[6]) | I5; +assign sel6 = (~E6) | (~S6[6]) | I6; +assign sel7 = (~E7) | (~S7[6]) | I7; +assign sel8 = (~E8) | (~S8[6]) | I8; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8; +endmodule // FanoutHash_245560850976C879 + diff --git a/sam/onyx/.magma/FanoutHash_26B6474864379B6A-kratos.sv b/sam/onyx/.magma/FanoutHash_26B6474864379B6A-kratos.sv new file mode 100644 index 00000000..c381fb8b --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_26B6474864379B6A-kratos.sv @@ -0,0 +1,42 @@ +module FanoutHash_26B6474864379B6A ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic E6, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic I6, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + input logic [31:0] S6, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +logic sel6; +assign sel0 = (~E0) | (~S0[1]) | I0; +assign sel1 = (~E1) | (~S1[1]) | I1; +assign sel2 = (~E2) | (~S2[2]) | I2; +assign sel3 = (~E3) | (~S3[17]) | I3; +assign sel4 = (~E4) | (~S4[17]) | I4; +assign sel5 = (~E5) | (~S5[17]) | I5; +assign sel6 = (~E6) | (~S6[17]) | I6; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6; +endmodule // FanoutHash_26B6474864379B6A + diff --git a/sam/onyx/.magma/FanoutHash_276F8381CE025648-kratos.sv b/sam/onyx/.magma/FanoutHash_276F8381CE025648-kratos.sv new file mode 100644 index 00000000..4bc47134 --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_276F8381CE025648-kratos.sv @@ -0,0 +1,52 @@ +module FanoutHash_276F8381CE025648 ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic E6, + input logic E7, + input logic E8, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic I6, + input logic I7, + input logic I8, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + input logic [31:0] S6, + input logic [31:0] S7, + input logic [31:0] S8, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +logic sel6; +logic sel7; +logic sel8; +assign sel0 = (~E0) | (~S0[0]) | I0; +assign sel1 = (~E1) | (~S1[0]) | I1; +assign sel2 = (~E2) | (~S2[2]) | I2; +assign sel3 = (~E3) | (~S3[14]) | I3; +assign sel4 = (~E4) | (~S4[14]) | I4; +assign sel5 = (~E5) | (~S5[14]) | I5; +assign sel6 = (~E6) | (~S6[14]) | I6; +assign sel7 = (~E7) | (~S7[14]) | I7; +assign sel8 = (~E8) | (~S8[14]) | I8; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8; +endmodule // FanoutHash_276F8381CE025648 + diff --git a/sam/onyx/.magma/FanoutHash_278348DB702230E6-kratos.sv b/sam/onyx/.magma/FanoutHash_278348DB702230E6-kratos.sv new file mode 100644 index 00000000..ca9c496e --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_278348DB702230E6-kratos.sv @@ -0,0 +1,37 @@ +module FanoutHash_278348DB702230E6 ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +assign sel0 = (~E0) | (~S0[0]) | I0; +assign sel1 = (~E1) | (~S1[0]) | I1; +assign sel2 = (~E2) | (~S2[2]) | I2; +assign sel3 = (~E3) | (~S3[10]) | I3; +assign sel4 = (~E4) | (~S4[10]) | I4; +assign sel5 = (~E5) | (~S5[10]) | I5; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5; +endmodule // FanoutHash_278348DB702230E6 + diff --git a/sam/onyx/.magma/FanoutHash_2785CE916183C5C-kratos.sv b/sam/onyx/.magma/FanoutHash_2785CE916183C5C-kratos.sv new file mode 100644 index 00000000..5412996e --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_2785CE916183C5C-kratos.sv @@ -0,0 +1,42 @@ +module FanoutHash_2785CE916183C5C ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic E6, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic I6, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + input logic [31:0] S6, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +logic sel6; +assign sel0 = (~E0) | (~S0[0]) | I0; +assign sel1 = (~E1) | (~S1[2]) | I1; +assign sel2 = (~E2) | (~S2[1]) | I2; +assign sel3 = (~E3) | (~S3[1]) | I3; +assign sel4 = (~E4) | (~S4[1]) | I4; +assign sel5 = (~E5) | (~S5[1]) | I5; +assign sel6 = (~E6) | (~S6[1]) | I6; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6; +endmodule // FanoutHash_2785CE916183C5C + diff --git a/sam/onyx/.magma/FanoutHash_28125A548B305607-kratos.sv b/sam/onyx/.magma/FanoutHash_28125A548B305607-kratos.sv new file mode 100644 index 00000000..3460e627 --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_28125A548B305607-kratos.sv @@ -0,0 +1,42 @@ +module FanoutHash_28125A548B305607 ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic E6, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic I6, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + input logic [31:0] S6, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +logic sel6; +assign sel0 = (~E0) | (~S0[2]) | I0; +assign sel1 = (~E1) | (~S1[1]) | I1; +assign sel2 = (~E2) | (~S2[1]) | I2; +assign sel3 = (~E3) | (~S3[9]) | I3; +assign sel4 = (~E4) | (~S4[9]) | I4; +assign sel5 = (~E5) | (~S5[9]) | I5; +assign sel6 = (~E6) | (~S6[9]) | I6; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6; +endmodule // FanoutHash_28125A548B305607 + diff --git a/sam/onyx/.magma/FanoutHash_2CE3041FDDDDEC1A-kratos.sv b/sam/onyx/.magma/FanoutHash_2CE3041FDDDDEC1A-kratos.sv new file mode 100644 index 00000000..6566169e --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_2CE3041FDDDDEC1A-kratos.sv @@ -0,0 +1,52 @@ +module FanoutHash_2CE3041FDDDDEC1A ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic E6, + input logic E7, + input logic E8, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic I6, + input logic I7, + input logic I8, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + input logic [31:0] S6, + input logic [31:0] S7, + input logic [31:0] S8, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +logic sel6; +logic sel7; +logic sel8; +assign sel0 = (~E0) | (~S0[2]) | I0; +assign sel1 = (~E1) | (~S1[1]) | I1; +assign sel2 = (~E2) | (~S2[1]) | I2; +assign sel3 = (~E3) | (~S3[9]) | I3; +assign sel4 = (~E4) | (~S4[9]) | I4; +assign sel5 = (~E5) | (~S5[9]) | I5; +assign sel6 = (~E6) | (~S6[9]) | I6; +assign sel7 = (~E7) | (~S7[9]) | I7; +assign sel8 = (~E8) | (~S8[9]) | I8; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8; +endmodule // FanoutHash_2CE3041FDDDDEC1A + diff --git a/sam/onyx/.magma/FanoutHash_2F92967E9F56D548-kratos.sv b/sam/onyx/.magma/FanoutHash_2F92967E9F56D548-kratos.sv new file mode 100644 index 00000000..c5fbd2dd --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_2F92967E9F56D548-kratos.sv @@ -0,0 +1,52 @@ +module FanoutHash_2F92967E9F56D548 ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic E6, + input logic E7, + input logic E8, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic I6, + input logic I7, + input logic I8, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + input logic [31:0] S6, + input logic [31:0] S7, + input logic [31:0] S8, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +logic sel6; +logic sel7; +logic sel8; +assign sel0 = (~E0) | (~S0[1]) | I0; +assign sel1 = (~E1) | (~S1[1]) | I1; +assign sel2 = (~E2) | (~S2[1]) | I2; +assign sel3 = (~E3) | (~S3[5]) | I3; +assign sel4 = (~E4) | (~S4[5]) | I4; +assign sel5 = (~E5) | (~S5[5]) | I5; +assign sel6 = (~E6) | (~S6[5]) | I6; +assign sel7 = (~E7) | (~S7[5]) | I7; +assign sel8 = (~E8) | (~S8[5]) | I8; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8; +endmodule // FanoutHash_2F92967E9F56D548 + diff --git a/sam/onyx/.magma/FanoutHash_302974B49BE3F0C4-kratos.sv b/sam/onyx/.magma/FanoutHash_302974B49BE3F0C4-kratos.sv new file mode 100644 index 00000000..db6670d6 --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_302974B49BE3F0C4-kratos.sv @@ -0,0 +1,42 @@ +module FanoutHash_302974B49BE3F0C4 ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic E6, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic I6, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + input logic [31:0] S6, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +logic sel6; +assign sel0 = (~E0) | (~S0[2]) | I0; +assign sel1 = (~E1) | (~S1[0]) | I1; +assign sel2 = (~E2) | (~S2[1]) | I2; +assign sel3 = (~E3) | (~S3[2]) | I3; +assign sel4 = (~E4) | (~S4[2]) | I4; +assign sel5 = (~E5) | (~S5[2]) | I5; +assign sel6 = (~E6) | (~S6[2]) | I6; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6; +endmodule // FanoutHash_302974B49BE3F0C4 + diff --git a/sam/onyx/.magma/FanoutHash_308BAC760F688049-kratos.sv b/sam/onyx/.magma/FanoutHash_308BAC760F688049-kratos.sv new file mode 100644 index 00000000..6a58af8c --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_308BAC760F688049-kratos.sv @@ -0,0 +1,37 @@ +module FanoutHash_308BAC760F688049 ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +assign sel0 = (~E0) | (~S0[2]) | I0; +assign sel1 = (~E1) | (~S1[1]) | I1; +assign sel2 = (~E2) | (~S2[1]) | I2; +assign sel3 = (~E3) | (~S3[9]) | I3; +assign sel4 = (~E4) | (~S4[9]) | I4; +assign sel5 = (~E5) | (~S5[9]) | I5; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5; +endmodule // FanoutHash_308BAC760F688049 + diff --git a/sam/onyx/.magma/FanoutHash_31555E0CDC460B97-kratos.sv b/sam/onyx/.magma/FanoutHash_31555E0CDC460B97-kratos.sv new file mode 100644 index 00000000..2dc5ed1f --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_31555E0CDC460B97-kratos.sv @@ -0,0 +1,37 @@ +module FanoutHash_31555E0CDC460B97 ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +assign sel0 = (~E0) | (~S0[0]) | I0; +assign sel1 = (~E1) | (~S1[1]) | I1; +assign sel2 = (~E2) | (~S2[0]) | I2; +assign sel3 = (~E3) | (~S3[4]) | I3; +assign sel4 = (~E4) | (~S4[4]) | I4; +assign sel5 = (~E5) | (~S5[4]) | I5; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5; +endmodule // FanoutHash_31555E0CDC460B97 + diff --git a/sam/onyx/.magma/FanoutHash_31AE65CCDD94603-kratos.sv b/sam/onyx/.magma/FanoutHash_31AE65CCDD94603-kratos.sv new file mode 100644 index 00000000..a03e54b5 --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_31AE65CCDD94603-kratos.sv @@ -0,0 +1,42 @@ +module FanoutHash_31AE65CCDD94603 ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic E6, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic I6, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + input logic [31:0] S6, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +logic sel6; +assign sel0 = (~E0) | (~S0[2]) | I0; +assign sel1 = (~E1) | (~S1[2]) | I1; +assign sel2 = (~E2) | (~S2[2]) | I2; +assign sel3 = (~E3) | (~S3[15]) | I3; +assign sel4 = (~E4) | (~S4[15]) | I4; +assign sel5 = (~E5) | (~S5[15]) | I5; +assign sel6 = (~E6) | (~S6[15]) | I6; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6; +endmodule // FanoutHash_31AE65CCDD94603 + diff --git a/sam/onyx/.magma/FanoutHash_37B926A0CDF82FCC-kratos.sv b/sam/onyx/.magma/FanoutHash_37B926A0CDF82FCC-kratos.sv new file mode 100644 index 00000000..08be469a --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_37B926A0CDF82FCC-kratos.sv @@ -0,0 +1,37 @@ +module FanoutHash_37B926A0CDF82FCC ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +assign sel0 = (~E0) | (~S0[0]) | I0; +assign sel1 = (~E1) | (~S1[2]) | I1; +assign sel2 = (~E2) | (~S2[2]) | I2; +assign sel3 = (~E3) | (~S3[16]) | I3; +assign sel4 = (~E4) | (~S4[16]) | I4; +assign sel5 = (~E5) | (~S5[16]) | I5; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5; +endmodule // FanoutHash_37B926A0CDF82FCC + diff --git a/sam/onyx/.magma/FanoutHash_37E9FE88073C5BAC-kratos.sv b/sam/onyx/.magma/FanoutHash_37E9FE88073C5BAC-kratos.sv new file mode 100644 index 00000000..a3be7859 --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_37E9FE88073C5BAC-kratos.sv @@ -0,0 +1,52 @@ +module FanoutHash_37E9FE88073C5BAC ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic E6, + input logic E7, + input logic E8, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic I6, + input logic I7, + input logic I8, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + input logic [31:0] S6, + input logic [31:0] S7, + input logic [31:0] S8, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +logic sel6; +logic sel7; +logic sel8; +assign sel0 = (~E0) | (~S0[0]) | I0; +assign sel1 = (~E1) | (~S1[1]) | I1; +assign sel2 = (~E2) | (~S2[0]) | I2; +assign sel3 = (~E3) | (~S3[4]) | I3; +assign sel4 = (~E4) | (~S4[4]) | I4; +assign sel5 = (~E5) | (~S5[4]) | I5; +assign sel6 = (~E6) | (~S6[4]) | I6; +assign sel7 = (~E7) | (~S7[4]) | I7; +assign sel8 = (~E8) | (~S8[4]) | I8; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8; +endmodule // FanoutHash_37E9FE88073C5BAC + diff --git a/sam/onyx/.magma/FanoutHash_3A0064632A577CF5-kratos.sv b/sam/onyx/.magma/FanoutHash_3A0064632A577CF5-kratos.sv new file mode 100644 index 00000000..6437415b --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_3A0064632A577CF5-kratos.sv @@ -0,0 +1,37 @@ +module FanoutHash_3A0064632A577CF5 ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +assign sel0 = (~E0) | (~S0[0]) | I0; +assign sel1 = (~E1) | (~S1[0]) | I1; +assign sel2 = (~E2) | (~S2[0]) | I2; +assign sel3 = (~E3) | (~S3[3]) | I3; +assign sel4 = (~E4) | (~S4[3]) | I4; +assign sel5 = (~E5) | (~S5[3]) | I5; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5; +endmodule // FanoutHash_3A0064632A577CF5 + diff --git a/sam/onyx/.magma/FanoutHash_3A6A5822E84DCC71-kratos.sv b/sam/onyx/.magma/FanoutHash_3A6A5822E84DCC71-kratos.sv new file mode 100644 index 00000000..5e3a3b41 --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_3A6A5822E84DCC71-kratos.sv @@ -0,0 +1,52 @@ +module FanoutHash_3A6A5822E84DCC71 ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic E6, + input logic E7, + input logic E8, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic I6, + input logic I7, + input logic I8, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + input logic [31:0] S6, + input logic [31:0] S7, + input logic [31:0] S8, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +logic sel6; +logic sel7; +logic sel8; +assign sel0 = (~E0) | (~S0[0]) | I0; +assign sel1 = (~E1) | (~S1[0]) | I1; +assign sel2 = (~E2) | (~S2[1]) | I2; +assign sel3 = (~E3) | (~S3[0]) | I3; +assign sel4 = (~E4) | (~S4[0]) | I4; +assign sel5 = (~E5) | (~S5[0]) | I5; +assign sel6 = (~E6) | (~S6[0]) | I6; +assign sel7 = (~E7) | (~S7[0]) | I7; +assign sel8 = (~E8) | (~S8[0]) | I8; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8; +endmodule // FanoutHash_3A6A5822E84DCC71 + diff --git a/sam/onyx/.magma/FanoutHash_3B67229CB02928BA-kratos.sv b/sam/onyx/.magma/FanoutHash_3B67229CB02928BA-kratos.sv new file mode 100644 index 00000000..73c47132 --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_3B67229CB02928BA-kratos.sv @@ -0,0 +1,42 @@ +module FanoutHash_3B67229CB02928BA ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic E6, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic I6, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + input logic [31:0] S6, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +logic sel6; +assign sel0 = (~E0) | (~S0[1]) | I0; +assign sel1 = (~E1) | (~S1[1]) | I1; +assign sel2 = (~E2) | (~S2[0]) | I2; +assign sel3 = (~E3) | (~S3[8]) | I3; +assign sel4 = (~E4) | (~S4[8]) | I4; +assign sel5 = (~E5) | (~S5[8]) | I5; +assign sel6 = (~E6) | (~S6[8]) | I6; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6; +endmodule // FanoutHash_3B67229CB02928BA + diff --git a/sam/onyx/.magma/FanoutHash_3E05574A9CE9CA8A-kratos.sv b/sam/onyx/.magma/FanoutHash_3E05574A9CE9CA8A-kratos.sv new file mode 100644 index 00000000..94a70ac6 --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_3E05574A9CE9CA8A-kratos.sv @@ -0,0 +1,52 @@ +module FanoutHash_3E05574A9CE9CA8A ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic E6, + input logic E7, + input logic E8, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic I6, + input logic I7, + input logic I8, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + input logic [31:0] S6, + input logic [31:0] S7, + input logic [31:0] S8, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +logic sel6; +logic sel7; +logic sel8; +assign sel0 = (~E0) | (~S0[0]) | I0; +assign sel1 = (~E1) | (~S1[2]) | I1; +assign sel2 = (~E2) | (~S2[1]) | I2; +assign sel3 = (~E3) | (~S3[1]) | I3; +assign sel4 = (~E4) | (~S4[1]) | I4; +assign sel5 = (~E5) | (~S5[1]) | I5; +assign sel6 = (~E6) | (~S6[1]) | I6; +assign sel7 = (~E7) | (~S7[1]) | I7; +assign sel8 = (~E8) | (~S8[1]) | I8; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8; +endmodule // FanoutHash_3E05574A9CE9CA8A + diff --git a/sam/onyx/.magma/FanoutHash_41D739158D58E184-kratos.sv b/sam/onyx/.magma/FanoutHash_41D739158D58E184-kratos.sv new file mode 100644 index 00000000..cdbbf50c --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_41D739158D58E184-kratos.sv @@ -0,0 +1,52 @@ +module FanoutHash_41D739158D58E184 ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic E6, + input logic E7, + input logic E8, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic I6, + input logic I7, + input logic I8, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + input logic [31:0] S6, + input logic [31:0] S7, + input logic [31:0] S8, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +logic sel6; +logic sel7; +logic sel8; +assign sel0 = (~E0) | (~S0[2]) | I0; +assign sel1 = (~E1) | (~S1[2]) | I1; +assign sel2 = (~E2) | (~S2[2]) | I2; +assign sel3 = (~E3) | (~S3[15]) | I3; +assign sel4 = (~E4) | (~S4[15]) | I4; +assign sel5 = (~E5) | (~S5[15]) | I5; +assign sel6 = (~E6) | (~S6[15]) | I6; +assign sel7 = (~E7) | (~S7[15]) | I7; +assign sel8 = (~E8) | (~S8[15]) | I8; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8; +endmodule // FanoutHash_41D739158D58E184 + diff --git a/sam/onyx/.magma/FanoutHash_43D5C80ABD816837-kratos.sv b/sam/onyx/.magma/FanoutHash_43D5C80ABD816837-kratos.sv new file mode 100644 index 00000000..998358be --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_43D5C80ABD816837-kratos.sv @@ -0,0 +1,42 @@ +module FanoutHash_43D5C80ABD816837 ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic E6, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic I6, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + input logic [31:0] S6, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +logic sel6; +assign sel0 = (~E0) | (~S0[0]) | I0; +assign sel1 = (~E1) | (~S1[0]) | I1; +assign sel2 = (~E2) | (~S2[2]) | I2; +assign sel3 = (~E3) | (~S3[14]) | I3; +assign sel4 = (~E4) | (~S4[14]) | I4; +assign sel5 = (~E5) | (~S5[14]) | I5; +assign sel6 = (~E6) | (~S6[14]) | I6; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6; +endmodule // FanoutHash_43D5C80ABD816837 + diff --git a/sam/onyx/.magma/FanoutHash_466EB88CFD0CAD7B-kratos.sv b/sam/onyx/.magma/FanoutHash_466EB88CFD0CAD7B-kratos.sv new file mode 100644 index 00000000..3776548c --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_466EB88CFD0CAD7B-kratos.sv @@ -0,0 +1,42 @@ +module FanoutHash_466EB88CFD0CAD7B ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic E6, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic I6, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + input logic [31:0] S6, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +logic sel6; +assign sel0 = (~E0) | (~S0[1]) | I0; +assign sel1 = (~E1) | (~S1[1]) | I1; +assign sel2 = (~E2) | (~S2[1]) | I2; +assign sel3 = (~E3) | (~S3[5]) | I3; +assign sel4 = (~E4) | (~S4[5]) | I4; +assign sel5 = (~E5) | (~S5[5]) | I5; +assign sel6 = (~E6) | (~S6[5]) | I6; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6; +endmodule // FanoutHash_466EB88CFD0CAD7B + diff --git a/sam/onyx/.magma/FanoutHash_4678C6877F96240E-kratos.sv b/sam/onyx/.magma/FanoutHash_4678C6877F96240E-kratos.sv new file mode 100644 index 00000000..17a67836 --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_4678C6877F96240E-kratos.sv @@ -0,0 +1,37 @@ +module FanoutHash_4678C6877F96240E ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +assign sel0 = (~E0) | (~S0[2]) | I0; +assign sel1 = (~E1) | (~S1[0]) | I1; +assign sel2 = (~E2) | (~S2[1]) | I2; +assign sel3 = (~E3) | (~S3[2]) | I3; +assign sel4 = (~E4) | (~S4[2]) | I4; +assign sel5 = (~E5) | (~S5[2]) | I5; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5; +endmodule // FanoutHash_4678C6877F96240E + diff --git a/sam/onyx/.magma/FanoutHash_47712AAC902ADA2-kratos.sv b/sam/onyx/.magma/FanoutHash_47712AAC902ADA2-kratos.sv new file mode 100644 index 00000000..93b6e8dd --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_47712AAC902ADA2-kratos.sv @@ -0,0 +1,42 @@ +module FanoutHash_47712AAC902ADA2 ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic E6, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic I6, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + input logic [31:0] S6, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +logic sel6; +assign sel0 = (~E0) | (~S0[0]) | I0; +assign sel1 = (~E1) | (~S1[0]) | I1; +assign sel2 = (~E2) | (~S2[1]) | I2; +assign sel3 = (~E3) | (~S3[0]) | I3; +assign sel4 = (~E4) | (~S4[0]) | I4; +assign sel5 = (~E5) | (~S5[0]) | I5; +assign sel6 = (~E6) | (~S6[0]) | I6; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6; +endmodule // FanoutHash_47712AAC902ADA2 + diff --git a/sam/onyx/.magma/FanoutHash_4A74B16B611BA7E4-kratos.sv b/sam/onyx/.magma/FanoutHash_4A74B16B611BA7E4-kratos.sv new file mode 100644 index 00000000..f5a2c41c --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_4A74B16B611BA7E4-kratos.sv @@ -0,0 +1,52 @@ +module FanoutHash_4A74B16B611BA7E4 ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic E6, + input logic E7, + input logic E8, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic I6, + input logic I7, + input logic I8, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + input logic [31:0] S6, + input logic [31:0] S7, + input logic [31:0] S8, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +logic sel6; +logic sel7; +logic sel8; +assign sel0 = (~E0) | (~S0[0]) | I0; +assign sel1 = (~E1) | (~S1[2]) | I1; +assign sel2 = (~E2) | (~S2[2]) | I2; +assign sel3 = (~E3) | (~S3[11]) | I3; +assign sel4 = (~E4) | (~S4[11]) | I4; +assign sel5 = (~E5) | (~S5[11]) | I5; +assign sel6 = (~E6) | (~S6[11]) | I6; +assign sel7 = (~E7) | (~S7[11]) | I7; +assign sel8 = (~E8) | (~S8[11]) | I8; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8; +endmodule // FanoutHash_4A74B16B611BA7E4 + diff --git a/sam/onyx/.magma/FanoutHash_4F83851A40824F89-kratos.sv b/sam/onyx/.magma/FanoutHash_4F83851A40824F89-kratos.sv new file mode 100644 index 00000000..325464d3 --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_4F83851A40824F89-kratos.sv @@ -0,0 +1,42 @@ +module FanoutHash_4F83851A40824F89 ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic E6, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic I6, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + input logic [31:0] S6, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +logic sel6; +assign sel0 = (~E0) | (~S0[1]) | I0; +assign sel1 = (~E1) | (~S1[2]) | I1; +assign sel2 = (~E2) | (~S2[0]) | I2; +assign sel3 = (~E3) | (~S3[6]) | I3; +assign sel4 = (~E4) | (~S4[6]) | I4; +assign sel5 = (~E5) | (~S5[6]) | I5; +assign sel6 = (~E6) | (~S6[6]) | I6; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6; +endmodule // FanoutHash_4F83851A40824F89 + diff --git a/sam/onyx/.magma/FanoutHash_4FADDC8F90390680-kratos.sv b/sam/onyx/.magma/FanoutHash_4FADDC8F90390680-kratos.sv new file mode 100644 index 00000000..1bc086bf --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_4FADDC8F90390680-kratos.sv @@ -0,0 +1,42 @@ +module FanoutHash_4FADDC8F90390680 ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic E6, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic I6, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + input logic [31:0] S6, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +logic sel6; +assign sel0 = (~E0) | (~S0[0]) | I0; +assign sel1 = (~E1) | (~S1[1]) | I1; +assign sel2 = (~E2) | (~S2[0]) | I2; +assign sel3 = (~E3) | (~S3[4]) | I3; +assign sel4 = (~E4) | (~S4[4]) | I4; +assign sel5 = (~E5) | (~S5[4]) | I5; +assign sel6 = (~E6) | (~S6[4]) | I6; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6; +endmodule // FanoutHash_4FADDC8F90390680 + diff --git a/sam/onyx/.magma/FanoutHash_4FF010386DB0B737-kratos.sv b/sam/onyx/.magma/FanoutHash_4FF010386DB0B737-kratos.sv new file mode 100644 index 00000000..73d09815 --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_4FF010386DB0B737-kratos.sv @@ -0,0 +1,37 @@ +module FanoutHash_4FF010386DB0B737 ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +assign sel0 = (~E0) | (~S0[1]) | I0; +assign sel1 = (~E1) | (~S1[1]) | I1; +assign sel2 = (~E2) | (~S2[1]) | I2; +assign sel3 = (~E3) | (~S3[5]) | I3; +assign sel4 = (~E4) | (~S4[5]) | I4; +assign sel5 = (~E5) | (~S5[5]) | I5; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5; +endmodule // FanoutHash_4FF010386DB0B737 + diff --git a/sam/onyx/.magma/FanoutHash_55169EB19E10AA09-kratos.sv b/sam/onyx/.magma/FanoutHash_55169EB19E10AA09-kratos.sv new file mode 100644 index 00000000..df5e881a --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_55169EB19E10AA09-kratos.sv @@ -0,0 +1,52 @@ +module FanoutHash_55169EB19E10AA09 ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic E6, + input logic E7, + input logic E8, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic I6, + input logic I7, + input logic I8, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + input logic [31:0] S6, + input logic [31:0] S7, + input logic [31:0] S8, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +logic sel6; +logic sel7; +logic sel8; +assign sel0 = (~E0) | (~S0[1]) | I0; +assign sel1 = (~E1) | (~S1[1]) | I1; +assign sel2 = (~E2) | (~S2[2]) | I2; +assign sel3 = (~E3) | (~S3[18]) | I3; +assign sel4 = (~E4) | (~S4[18]) | I4; +assign sel5 = (~E5) | (~S5[18]) | I5; +assign sel6 = (~E6) | (~S6[18]) | I6; +assign sel7 = (~E7) | (~S7[18]) | I7; +assign sel8 = (~E8) | (~S8[18]) | I8; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8; +endmodule // FanoutHash_55169EB19E10AA09 + diff --git a/sam/onyx/.magma/FanoutHash_55B00FA90A0098BB-kratos.sv b/sam/onyx/.magma/FanoutHash_55B00FA90A0098BB-kratos.sv new file mode 100644 index 00000000..21ec5a6f --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_55B00FA90A0098BB-kratos.sv @@ -0,0 +1,52 @@ +module FanoutHash_55B00FA90A0098BB ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic E6, + input logic E7, + input logic E8, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic I6, + input logic I7, + input logic I8, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + input logic [31:0] S6, + input logic [31:0] S7, + input logic [31:0] S8, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +logic sel6; +logic sel7; +logic sel8; +assign sel0 = (~E0) | (~S0[2]) | I0; +assign sel1 = (~E1) | (~S1[0]) | I1; +assign sel2 = (~E2) | (~S2[1]) | I2; +assign sel3 = (~E3) | (~S3[2]) | I3; +assign sel4 = (~E4) | (~S4[2]) | I4; +assign sel5 = (~E5) | (~S5[2]) | I5; +assign sel6 = (~E6) | (~S6[2]) | I6; +assign sel7 = (~E7) | (~S7[2]) | I7; +assign sel8 = (~E8) | (~S8[2]) | I8; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8; +endmodule // FanoutHash_55B00FA90A0098BB + diff --git a/sam/onyx/.magma/FanoutHash_59B7E37DAE2221E3-kratos.sv b/sam/onyx/.magma/FanoutHash_59B7E37DAE2221E3-kratos.sv new file mode 100644 index 00000000..155886cf --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_59B7E37DAE2221E3-kratos.sv @@ -0,0 +1,52 @@ +module FanoutHash_59B7E37DAE2221E3 ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic E6, + input logic E7, + input logic E8, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic I6, + input logic I7, + input logic I8, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + input logic [31:0] S6, + input logic [31:0] S7, + input logic [31:0] S8, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +logic sel6; +logic sel7; +logic sel8; +assign sel0 = (~E0) | (~S0[1]) | I0; +assign sel1 = (~E1) | (~S1[2]) | I1; +assign sel2 = (~E2) | (~S2[1]) | I2; +assign sel3 = (~E3) | (~S3[13]) | I3; +assign sel4 = (~E4) | (~S4[13]) | I4; +assign sel5 = (~E5) | (~S5[13]) | I5; +assign sel6 = (~E6) | (~S6[13]) | I6; +assign sel7 = (~E7) | (~S7[13]) | I7; +assign sel8 = (~E8) | (~S8[13]) | I8; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8; +endmodule // FanoutHash_59B7E37DAE2221E3 + diff --git a/sam/onyx/.magma/FanoutHash_5CD8077D054B887B-kratos.sv b/sam/onyx/.magma/FanoutHash_5CD8077D054B887B-kratos.sv new file mode 100644 index 00000000..c0c73ff4 --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_5CD8077D054B887B-kratos.sv @@ -0,0 +1,52 @@ +module FanoutHash_5CD8077D054B887B ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic E6, + input logic E7, + input logic E8, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic I6, + input logic I7, + input logic I8, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + input logic [31:0] S6, + input logic [31:0] S7, + input logic [31:0] S8, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +logic sel6; +logic sel7; +logic sel8; +assign sel0 = (~E0) | (~S0[0]) | I0; +assign sel1 = (~E1) | (~S1[0]) | I1; +assign sel2 = (~E2) | (~S2[2]) | I2; +assign sel3 = (~E3) | (~S3[10]) | I3; +assign sel4 = (~E4) | (~S4[10]) | I4; +assign sel5 = (~E5) | (~S5[10]) | I5; +assign sel6 = (~E6) | (~S6[10]) | I6; +assign sel7 = (~E7) | (~S7[10]) | I7; +assign sel8 = (~E8) | (~S8[10]) | I8; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8; +endmodule // FanoutHash_5CD8077D054B887B + diff --git a/sam/onyx/.magma/FanoutHash_5D7AEC1255CDC1CC-kratos.sv b/sam/onyx/.magma/FanoutHash_5D7AEC1255CDC1CC-kratos.sv new file mode 100644 index 00000000..f8d9f2d3 --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_5D7AEC1255CDC1CC-kratos.sv @@ -0,0 +1,42 @@ +module FanoutHash_5D7AEC1255CDC1CC ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic E6, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic I6, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + input logic [31:0] S6, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +logic sel6; +assign sel0 = (~E0) | (~S0[1]) | I0; +assign sel1 = (~E1) | (~S1[1]) | I1; +assign sel2 = (~E2) | (~S2[2]) | I2; +assign sel3 = (~E3) | (~S3[18]) | I3; +assign sel4 = (~E4) | (~S4[18]) | I4; +assign sel5 = (~E5) | (~S5[18]) | I5; +assign sel6 = (~E6) | (~S6[18]) | I6; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6; +endmodule // FanoutHash_5D7AEC1255CDC1CC + diff --git a/sam/onyx/.magma/FanoutHash_5DE101F5B6936D07-kratos.sv b/sam/onyx/.magma/FanoutHash_5DE101F5B6936D07-kratos.sv new file mode 100644 index 00000000..1763b796 --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_5DE101F5B6936D07-kratos.sv @@ -0,0 +1,37 @@ +module FanoutHash_5DE101F5B6936D07 ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +assign sel0 = (~E0) | (~S0[0]) | I0; +assign sel1 = (~E1) | (~S1[0]) | I1; +assign sel2 = (~E2) | (~S2[1]) | I2; +assign sel3 = (~E3) | (~S3[12]) | I3; +assign sel4 = (~E4) | (~S4[12]) | I4; +assign sel5 = (~E5) | (~S5[12]) | I5; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5; +endmodule // FanoutHash_5DE101F5B6936D07 + diff --git a/sam/onyx/.magma/FanoutHash_6211982AB4467DB3-kratos.sv b/sam/onyx/.magma/FanoutHash_6211982AB4467DB3-kratos.sv new file mode 100644 index 00000000..136463d9 --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_6211982AB4467DB3-kratos.sv @@ -0,0 +1,119 @@ +module FanoutHash_6211982AB4467DB3 ( + input logic E0, + input logic E1, + input logic E10, + input logic E11, + input logic E12, + input logic E13, + input logic E14, + input logic E15, + input logic E16, + input logic E17, + input logic E18, + input logic E19, + input logic E2, + input logic E20, + input logic E21, + input logic E3, + input logic E4, + input logic E5, + input logic E6, + input logic E7, + input logic E8, + input logic E9, + input logic I0, + input logic I1, + input logic I10, + input logic I11, + input logic I12, + input logic I13, + input logic I14, + input logic I15, + input logic I16, + input logic I17, + input logic I18, + input logic I19, + input logic I2, + input logic I20, + input logic I21, + input logic I3, + input logic I4, + input logic I5, + input logic I6, + input logic I7, + input logic I8, + input logic I9, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S10, + input logic [7:0] S11, + input logic [7:0] S12, + input logic [7:0] S13, + input logic [7:0] S14, + input logic [7:0] S15, + input logic [7:0] S16, + input logic [7:0] S17, + input logic [7:0] S18, + input logic [7:0] S19, + input logic [7:0] S2, + input logic [31:0] S20, + input logic [31:0] S21, + input logic [7:0] S3, + input logic [7:0] S4, + input logic [7:0] S5, + input logic [7:0] S6, + input logic [7:0] S7, + input logic [7:0] S8, + input logic [7:0] S9, + output logic O +); + +logic sel0; +logic sel1; +logic sel10; +logic sel11; +logic sel12; +logic sel13; +logic sel14; +logic sel15; +logic sel16; +logic sel17; +logic sel18; +logic sel19; +logic sel2; +logic sel20; +logic sel21; +logic sel3; +logic sel4; +logic sel5; +logic sel6; +logic sel7; +logic sel8; +logic sel9; +assign sel0 = (~E0) | (~S0[4]) | I0; +assign sel1 = (~E1) | (~S1[4]) | I1; +assign sel2 = (~E2) | (~S2[4]) | I2; +assign sel3 = (~E3) | (~S3[4]) | I3; +assign sel4 = (~E4) | (~S4[4]) | I4; +assign sel5 = (~E5) | (~S5[4]) | I5; +assign sel6 = (~E6) | (~S6[4]) | I6; +assign sel7 = (~E7) | (~S7[4]) | I7; +assign sel8 = (~E8) | (~S8[4]) | I8; +assign sel9 = (~E9) | (~S9[4]) | I9; +assign sel10 = (~E10) | (~S10[4]) | I10; +assign sel11 = (~E11) | (~S11[4]) | I11; +assign sel12 = (~E12) | (~S12[4]) | I12; +assign sel13 = (~E13) | (~S13[4]) | I13; +assign sel14 = (~E14) | (~S14[4]) | I14; +assign sel15 = (~E15) | (~S15[4]) | I15; +assign sel16 = (~E16) | (~S16[4]) | I16; +assign sel17 = (~E17) | (~S17[4]) | I17; +assign sel18 = (~E18) | (~S18[4]) | I18; +assign sel19 = (~E19) | (~S19[4]) | I19; +assign sel20 = (~E20) | (~S20[20]) | I20; +assign sel21 = (~E21) | (~S21[20]) | I21; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8 & sel9 & sel10 & + sel11 & sel12 & sel13 & sel14 & sel15 & sel16 & sel17 & sel18 & sel19 & sel20 & + sel21; +endmodule // FanoutHash_6211982AB4467DB3 + diff --git a/sam/onyx/.magma/FanoutHash_653384C8EF52B5E3-kratos.sv b/sam/onyx/.magma/FanoutHash_653384C8EF52B5E3-kratos.sv new file mode 100644 index 00000000..af3a47a2 --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_653384C8EF52B5E3-kratos.sv @@ -0,0 +1,52 @@ +module FanoutHash_653384C8EF52B5E3 ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic E6, + input logic E7, + input logic E8, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic I6, + input logic I7, + input logic I8, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + input logic [31:0] S6, + input logic [31:0] S7, + input logic [31:0] S8, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +logic sel6; +logic sel7; +logic sel8; +assign sel0 = (~E0) | (~S0[0]) | I0; +assign sel1 = (~E1) | (~S1[2]) | I1; +assign sel2 = (~E2) | (~S2[1]) | I2; +assign sel3 = (~E3) | (~S3[7]) | I3; +assign sel4 = (~E4) | (~S4[7]) | I4; +assign sel5 = (~E5) | (~S5[7]) | I5; +assign sel6 = (~E6) | (~S6[7]) | I6; +assign sel7 = (~E7) | (~S7[7]) | I7; +assign sel8 = (~E8) | (~S8[7]) | I8; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8; +endmodule // FanoutHash_653384C8EF52B5E3 + diff --git a/sam/onyx/.magma/FanoutHash_65A468071775C7BB-kratos.sv b/sam/onyx/.magma/FanoutHash_65A468071775C7BB-kratos.sv new file mode 100644 index 00000000..8935b861 --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_65A468071775C7BB-kratos.sv @@ -0,0 +1,42 @@ +module FanoutHash_65A468071775C7BB ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic E6, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic I6, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + input logic [31:0] S6, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +logic sel6; +assign sel0 = (~E0) | (~S0[0]) | I0; +assign sel1 = (~E1) | (~S1[0]) | I1; +assign sel2 = (~E2) | (~S2[0]) | I2; +assign sel3 = (~E3) | (~S3[3]) | I3; +assign sel4 = (~E4) | (~S4[3]) | I4; +assign sel5 = (~E5) | (~S5[3]) | I5; +assign sel6 = (~E6) | (~S6[3]) | I6; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6; +endmodule // FanoutHash_65A468071775C7BB + diff --git a/sam/onyx/.magma/FanoutHash_660E59B0DDACF452-kratos.sv b/sam/onyx/.magma/FanoutHash_660E59B0DDACF452-kratos.sv new file mode 100644 index 00000000..9d4632a5 --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_660E59B0DDACF452-kratos.sv @@ -0,0 +1,37 @@ +module FanoutHash_660E59B0DDACF452 ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +assign sel0 = (~E0) | (~S0[2]) | I0; +assign sel1 = (~E1) | (~S1[2]) | I1; +assign sel2 = (~E2) | (~S2[2]) | I2; +assign sel3 = (~E3) | (~S3[19]) | I3; +assign sel4 = (~E4) | (~S4[19]) | I4; +assign sel5 = (~E5) | (~S5[19]) | I5; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5; +endmodule // FanoutHash_660E59B0DDACF452 + diff --git a/sam/onyx/.magma/FanoutHash_66A75CC8494A4D6B-kratos.sv b/sam/onyx/.magma/FanoutHash_66A75CC8494A4D6B-kratos.sv new file mode 100644 index 00000000..08c15fdb --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_66A75CC8494A4D6B-kratos.sv @@ -0,0 +1,42 @@ +module FanoutHash_66A75CC8494A4D6B ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic E6, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic I6, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + input logic [31:0] S6, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +logic sel6; +assign sel0 = (~E0) | (~S0[1]) | I0; +assign sel1 = (~E1) | (~S1[2]) | I1; +assign sel2 = (~E2) | (~S2[1]) | I2; +assign sel3 = (~E3) | (~S3[13]) | I3; +assign sel4 = (~E4) | (~S4[13]) | I4; +assign sel5 = (~E5) | (~S5[13]) | I5; +assign sel6 = (~E6) | (~S6[13]) | I6; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6; +endmodule // FanoutHash_66A75CC8494A4D6B + diff --git a/sam/onyx/.magma/FanoutHash_69376833A2418E2-kratos.sv b/sam/onyx/.magma/FanoutHash_69376833A2418E2-kratos.sv new file mode 100644 index 00000000..a7cbf111 --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_69376833A2418E2-kratos.sv @@ -0,0 +1,42 @@ +module FanoutHash_69376833A2418E2 ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic E6, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic I6, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + input logic [31:0] S6, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +logic sel6; +assign sel0 = (~E0) | (~S0[0]) | I0; +assign sel1 = (~E1) | (~S1[0]) | I1; +assign sel2 = (~E2) | (~S2[1]) | I2; +assign sel3 = (~E3) | (~S3[12]) | I3; +assign sel4 = (~E4) | (~S4[12]) | I4; +assign sel5 = (~E5) | (~S5[12]) | I5; +assign sel6 = (~E6) | (~S6[12]) | I6; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6; +endmodule // FanoutHash_69376833A2418E2 + diff --git a/sam/onyx/.magma/FanoutHash_6E1094CE0D0F6DFA-kratos.sv b/sam/onyx/.magma/FanoutHash_6E1094CE0D0F6DFA-kratos.sv new file mode 100644 index 00000000..2a26a093 --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_6E1094CE0D0F6DFA-kratos.sv @@ -0,0 +1,52 @@ +module FanoutHash_6E1094CE0D0F6DFA ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic E6, + input logic E7, + input logic E8, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic I6, + input logic I7, + input logic I8, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + input logic [31:0] S6, + input logic [31:0] S7, + input logic [31:0] S8, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +logic sel6; +logic sel7; +logic sel8; +assign sel0 = (~E0) | (~S0[2]) | I0; +assign sel1 = (~E1) | (~S1[2]) | I1; +assign sel2 = (~E2) | (~S2[2]) | I2; +assign sel3 = (~E3) | (~S3[19]) | I3; +assign sel4 = (~E4) | (~S4[19]) | I4; +assign sel5 = (~E5) | (~S5[19]) | I5; +assign sel6 = (~E6) | (~S6[19]) | I6; +assign sel7 = (~E7) | (~S7[19]) | I7; +assign sel8 = (~E8) | (~S8[19]) | I8; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8; +endmodule // FanoutHash_6E1094CE0D0F6DFA + diff --git a/sam/onyx/.magma/FanoutHash_6EB42FA08A9B7B5B-kratos.sv b/sam/onyx/.magma/FanoutHash_6EB42FA08A9B7B5B-kratos.sv new file mode 100644 index 00000000..13aa8c2b --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_6EB42FA08A9B7B5B-kratos.sv @@ -0,0 +1,37 @@ +module FanoutHash_6EB42FA08A9B7B5B ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +assign sel0 = (~E0) | (~S0[1]) | I0; +assign sel1 = (~E1) | (~S1[1]) | I1; +assign sel2 = (~E2) | (~S2[0]) | I2; +assign sel3 = (~E3) | (~S3[8]) | I3; +assign sel4 = (~E4) | (~S4[8]) | I4; +assign sel5 = (~E5) | (~S5[8]) | I5; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5; +endmodule // FanoutHash_6EB42FA08A9B7B5B + diff --git a/sam/onyx/.magma/FanoutHash_74A3E41836ECED62-kratos.sv b/sam/onyx/.magma/FanoutHash_74A3E41836ECED62-kratos.sv new file mode 100644 index 00000000..530215cb --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_74A3E41836ECED62-kratos.sv @@ -0,0 +1,52 @@ +module FanoutHash_74A3E41836ECED62 ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic E6, + input logic E7, + input logic E8, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic I6, + input logic I7, + input logic I8, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + input logic [31:0] S6, + input logic [31:0] S7, + input logic [31:0] S8, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +logic sel6; +logic sel7; +logic sel8; +assign sel0 = (~E0) | (~S0[1]) | I0; +assign sel1 = (~E1) | (~S1[1]) | I1; +assign sel2 = (~E2) | (~S2[0]) | I2; +assign sel3 = (~E3) | (~S3[8]) | I3; +assign sel4 = (~E4) | (~S4[8]) | I4; +assign sel5 = (~E5) | (~S5[8]) | I5; +assign sel6 = (~E6) | (~S6[8]) | I6; +assign sel7 = (~E7) | (~S7[8]) | I7; +assign sel8 = (~E8) | (~S8[8]) | I8; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8; +endmodule // FanoutHash_74A3E41836ECED62 + diff --git a/sam/onyx/.magma/FanoutHash_752C11B748DD905C-kratos.sv b/sam/onyx/.magma/FanoutHash_752C11B748DD905C-kratos.sv new file mode 100644 index 00000000..73473a1e --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_752C11B748DD905C-kratos.sv @@ -0,0 +1,42 @@ +module FanoutHash_752C11B748DD905C ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic E6, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic I6, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + input logic [31:0] S6, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +logic sel6; +assign sel0 = (~E0) | (~S0[0]) | I0; +assign sel1 = (~E1) | (~S1[2]) | I1; +assign sel2 = (~E2) | (~S2[2]) | I2; +assign sel3 = (~E3) | (~S3[11]) | I3; +assign sel4 = (~E4) | (~S4[11]) | I4; +assign sel5 = (~E5) | (~S5[11]) | I5; +assign sel6 = (~E6) | (~S6[11]) | I6; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6; +endmodule // FanoutHash_752C11B748DD905C + diff --git a/sam/onyx/.magma/FanoutHash_7E22D83B42537D1D-kratos.sv b/sam/onyx/.magma/FanoutHash_7E22D83B42537D1D-kratos.sv new file mode 100644 index 00000000..96ceac3e --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_7E22D83B42537D1D-kratos.sv @@ -0,0 +1,52 @@ +module FanoutHash_7E22D83B42537D1D ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic E6, + input logic E7, + input logic E8, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic I6, + input logic I7, + input logic I8, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + input logic [31:0] S6, + input logic [31:0] S7, + input logic [31:0] S8, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +logic sel6; +logic sel7; +logic sel8; +assign sel0 = (~E0) | (~S0[0]) | I0; +assign sel1 = (~E1) | (~S1[0]) | I1; +assign sel2 = (~E2) | (~S2[1]) | I2; +assign sel3 = (~E3) | (~S3[12]) | I3; +assign sel4 = (~E4) | (~S4[12]) | I4; +assign sel5 = (~E5) | (~S5[12]) | I5; +assign sel6 = (~E6) | (~S6[12]) | I6; +assign sel7 = (~E7) | (~S7[12]) | I7; +assign sel8 = (~E8) | (~S8[12]) | I8; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8; +endmodule // FanoutHash_7E22D83B42537D1D + diff --git a/sam/onyx/.magma/FanoutHash_7ED1C80229B84786-kratos.sv b/sam/onyx/.magma/FanoutHash_7ED1C80229B84786-kratos.sv new file mode 100644 index 00000000..5cfe0c93 --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_7ED1C80229B84786-kratos.sv @@ -0,0 +1,42 @@ +module FanoutHash_7ED1C80229B84786 ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic E6, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic I6, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + input logic [31:0] S6, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +logic sel6; +assign sel0 = (~E0) | (~S0[0]) | I0; +assign sel1 = (~E1) | (~S1[2]) | I1; +assign sel2 = (~E2) | (~S2[1]) | I2; +assign sel3 = (~E3) | (~S3[7]) | I3; +assign sel4 = (~E4) | (~S4[7]) | I4; +assign sel5 = (~E5) | (~S5[7]) | I5; +assign sel6 = (~E6) | (~S6[7]) | I6; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6; +endmodule // FanoutHash_7ED1C80229B84786 + diff --git a/sam/onyx/.magma/FanoutHash_7F4660D1463D9234-kratos.sv b/sam/onyx/.magma/FanoutHash_7F4660D1463D9234-kratos.sv new file mode 100644 index 00000000..4170771e --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_7F4660D1463D9234-kratos.sv @@ -0,0 +1,42 @@ +module FanoutHash_7F4660D1463D9234 ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic E6, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic I6, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + input logic [31:0] S6, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +logic sel6; +assign sel0 = (~E0) | (~S0[0]) | I0; +assign sel1 = (~E1) | (~S1[0]) | I1; +assign sel2 = (~E2) | (~S2[2]) | I2; +assign sel3 = (~E3) | (~S3[10]) | I3; +assign sel4 = (~E4) | (~S4[10]) | I4; +assign sel5 = (~E5) | (~S5[10]) | I5; +assign sel6 = (~E6) | (~S6[10]) | I6; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6; +endmodule // FanoutHash_7F4660D1463D9234 + diff --git a/sam/onyx/.magma/FanoutHash_7FDF2D3240D4A947-kratos.sv b/sam/onyx/.magma/FanoutHash_7FDF2D3240D4A947-kratos.sv new file mode 100644 index 00000000..5745d42e --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_7FDF2D3240D4A947-kratos.sv @@ -0,0 +1,37 @@ +module FanoutHash_7FDF2D3240D4A947 ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +assign sel0 = (~E0) | (~S0[2]) | I0; +assign sel1 = (~E1) | (~S1[2]) | I1; +assign sel2 = (~E2) | (~S2[2]) | I2; +assign sel3 = (~E3) | (~S3[15]) | I3; +assign sel4 = (~E4) | (~S4[15]) | I4; +assign sel5 = (~E5) | (~S5[15]) | I5; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5; +endmodule // FanoutHash_7FDF2D3240D4A947 + diff --git a/sam/onyx/.magma/FanoutHash_82899D6851EDC11-kratos.sv b/sam/onyx/.magma/FanoutHash_82899D6851EDC11-kratos.sv new file mode 100644 index 00000000..c9b8e44a --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_82899D6851EDC11-kratos.sv @@ -0,0 +1,108 @@ +module FanoutHash_82899D6851EDC11 ( + input logic E0, + input logic E1, + input logic E10, + input logic E11, + input logic E12, + input logic E13, + input logic E14, + input logic E15, + input logic E16, + input logic E17, + input logic E18, + input logic E19, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic E6, + input logic E7, + input logic E8, + input logic E9, + input logic I0, + input logic I1, + input logic I10, + input logic I11, + input logic I12, + input logic I13, + input logic I14, + input logic I15, + input logic I16, + input logic I17, + input logic I18, + input logic I19, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic I6, + input logic I7, + input logic I8, + input logic I9, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S10, + input logic [7:0] S11, + input logic [7:0] S12, + input logic [7:0] S13, + input logic [7:0] S14, + input logic [7:0] S15, + input logic [7:0] S16, + input logic [7:0] S17, + input logic [7:0] S18, + input logic [7:0] S19, + input logic [7:0] S2, + input logic [7:0] S3, + input logic [7:0] S4, + input logic [7:0] S5, + input logic [7:0] S6, + input logic [7:0] S7, + input logic [7:0] S8, + input logic [7:0] S9, + output logic O +); + +logic sel0; +logic sel1; +logic sel10; +logic sel11; +logic sel12; +logic sel13; +logic sel14; +logic sel15; +logic sel16; +logic sel17; +logic sel18; +logic sel19; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +logic sel6; +logic sel7; +logic sel8; +logic sel9; +assign sel0 = (~E0) | (~S0[4]) | I0; +assign sel1 = (~E1) | (~S1[4]) | I1; +assign sel2 = (~E2) | (~S2[4]) | I2; +assign sel3 = (~E3) | (~S3[4]) | I3; +assign sel4 = (~E4) | (~S4[4]) | I4; +assign sel5 = (~E5) | (~S5[4]) | I5; +assign sel6 = (~E6) | (~S6[4]) | I6; +assign sel7 = (~E7) | (~S7[4]) | I7; +assign sel8 = (~E8) | (~S8[4]) | I8; +assign sel9 = (~E9) | (~S9[4]) | I9; +assign sel10 = (~E10) | (~S10[4]) | I10; +assign sel11 = (~E11) | (~S11[4]) | I11; +assign sel12 = (~E12) | (~S12[4]) | I12; +assign sel13 = (~E13) | (~S13[4]) | I13; +assign sel14 = (~E14) | (~S14[4]) | I14; +assign sel15 = (~E15) | (~S15[4]) | I15; +assign sel16 = (~E16) | (~S16[4]) | I16; +assign sel17 = (~E17) | (~S17[4]) | I17; +assign sel18 = (~E18) | (~S18[4]) | I18; +assign sel19 = (~E19) | (~S19[4]) | I19; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8 & sel9 & sel10 & + sel11 & sel12 & sel13 & sel14 & sel15 & sel16 & sel17 & sel18 & sel19; +endmodule // FanoutHash_82899D6851EDC11 + diff --git a/sam/onyx/.magma/FanoutHash_87642A353688B49-kratos.sv b/sam/onyx/.magma/FanoutHash_87642A353688B49-kratos.sv new file mode 100644 index 00000000..393255a6 --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_87642A353688B49-kratos.sv @@ -0,0 +1,52 @@ +module FanoutHash_87642A353688B49 ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic E6, + input logic E7, + input logic E8, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic I6, + input logic I7, + input logic I8, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + input logic [31:0] S6, + input logic [31:0] S7, + input logic [31:0] S8, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +logic sel6; +logic sel7; +logic sel8; +assign sel0 = (~E0) | (~S0[0]) | I0; +assign sel1 = (~E1) | (~S1[0]) | I1; +assign sel2 = (~E2) | (~S2[0]) | I2; +assign sel3 = (~E3) | (~S3[3]) | I3; +assign sel4 = (~E4) | (~S4[3]) | I4; +assign sel5 = (~E5) | (~S5[3]) | I5; +assign sel6 = (~E6) | (~S6[3]) | I6; +assign sel7 = (~E7) | (~S7[3]) | I7; +assign sel8 = (~E8) | (~S8[3]) | I8; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8; +endmodule // FanoutHash_87642A353688B49 + diff --git a/sam/onyx/.magma/FanoutHash_99D793215CEDDD5-kratos.sv b/sam/onyx/.magma/FanoutHash_99D793215CEDDD5-kratos.sv new file mode 100644 index 00000000..f4d4ee5c --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_99D793215CEDDD5-kratos.sv @@ -0,0 +1,37 @@ +module FanoutHash_99D793215CEDDD5 ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +assign sel0 = (~E0) | (~S0[0]) | I0; +assign sel1 = (~E1) | (~S1[2]) | I1; +assign sel2 = (~E2) | (~S2[1]) | I2; +assign sel3 = (~E3) | (~S3[1]) | I3; +assign sel4 = (~E4) | (~S4[1]) | I4; +assign sel5 = (~E5) | (~S5[1]) | I5; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5; +endmodule // FanoutHash_99D793215CEDDD5 + diff --git a/sam/onyx/.magma/FanoutHash_AE7392256DF8B0F-kratos.sv b/sam/onyx/.magma/FanoutHash_AE7392256DF8B0F-kratos.sv new file mode 100644 index 00000000..fc97cdfc --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_AE7392256DF8B0F-kratos.sv @@ -0,0 +1,52 @@ +module FanoutHash_AE7392256DF8B0F ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic E6, + input logic E7, + input logic E8, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic I6, + input logic I7, + input logic I8, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + input logic [31:0] S6, + input logic [31:0] S7, + input logic [31:0] S8, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +logic sel6; +logic sel7; +logic sel8; +assign sel0 = (~E0) | (~S0[1]) | I0; +assign sel1 = (~E1) | (~S1[1]) | I1; +assign sel2 = (~E2) | (~S2[2]) | I2; +assign sel3 = (~E3) | (~S3[17]) | I3; +assign sel4 = (~E4) | (~S4[17]) | I4; +assign sel5 = (~E5) | (~S5[17]) | I5; +assign sel6 = (~E6) | (~S6[17]) | I6; +assign sel7 = (~E7) | (~S7[17]) | I7; +assign sel8 = (~E8) | (~S8[17]) | I8; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8; +endmodule // FanoutHash_AE7392256DF8B0F + diff --git a/sam/onyx/.magma/FanoutHash_CE1AA874B742213-kratos.sv b/sam/onyx/.magma/FanoutHash_CE1AA874B742213-kratos.sv new file mode 100644 index 00000000..c1dc7330 --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_CE1AA874B742213-kratos.sv @@ -0,0 +1,108 @@ +module FanoutHash_CE1AA874B742213 ( + input logic E0, + input logic E1, + input logic E10, + input logic E11, + input logic E12, + input logic E13, + input logic E14, + input logic E15, + input logic E16, + input logic E17, + input logic E18, + input logic E19, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic E6, + input logic E7, + input logic E8, + input logic E9, + input logic I0, + input logic I1, + input logic I10, + input logic I11, + input logic I12, + input logic I13, + input logic I14, + input logic I15, + input logic I16, + input logic I17, + input logic I18, + input logic I19, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic I6, + input logic I7, + input logic I8, + input logic I9, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S10, + input logic [7:0] S11, + input logic [7:0] S12, + input logic [7:0] S13, + input logic [7:0] S14, + input logic [7:0] S15, + input logic [7:0] S16, + input logic [7:0] S17, + input logic [7:0] S18, + input logic [7:0] S19, + input logic [7:0] S2, + input logic [7:0] S3, + input logic [7:0] S4, + input logic [7:0] S5, + input logic [7:0] S6, + input logic [7:0] S7, + input logic [7:0] S8, + input logic [7:0] S9, + output logic O +); + +logic sel0; +logic sel1; +logic sel10; +logic sel11; +logic sel12; +logic sel13; +logic sel14; +logic sel15; +logic sel16; +logic sel17; +logic sel18; +logic sel19; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +logic sel6; +logic sel7; +logic sel8; +logic sel9; +assign sel0 = (~E0) | (~S0[5]) | I0; +assign sel1 = (~E1) | (~S1[5]) | I1; +assign sel2 = (~E2) | (~S2[5]) | I2; +assign sel3 = (~E3) | (~S3[5]) | I3; +assign sel4 = (~E4) | (~S4[5]) | I4; +assign sel5 = (~E5) | (~S5[5]) | I5; +assign sel6 = (~E6) | (~S6[5]) | I6; +assign sel7 = (~E7) | (~S7[5]) | I7; +assign sel8 = (~E8) | (~S8[5]) | I8; +assign sel9 = (~E9) | (~S9[5]) | I9; +assign sel10 = (~E10) | (~S10[5]) | I10; +assign sel11 = (~E11) | (~S11[5]) | I11; +assign sel12 = (~E12) | (~S12[5]) | I12; +assign sel13 = (~E13) | (~S13[5]) | I13; +assign sel14 = (~E14) | (~S14[5]) | I14; +assign sel15 = (~E15) | (~S15[5]) | I15; +assign sel16 = (~E16) | (~S16[5]) | I16; +assign sel17 = (~E17) | (~S17[5]) | I17; +assign sel18 = (~E18) | (~S18[5]) | I18; +assign sel19 = (~E19) | (~S19[5]) | I19; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8 & sel9 & sel10 & + sel11 & sel12 & sel13 & sel14 & sel15 & sel16 & sel17 & sel18 & sel19; +endmodule // FanoutHash_CE1AA874B742213 + diff --git a/sam/onyx/.magma/FanoutHash_D70CFBE8EA3CE7F-kratos.sv b/sam/onyx/.magma/FanoutHash_D70CFBE8EA3CE7F-kratos.sv new file mode 100644 index 00000000..359f72e9 --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_D70CFBE8EA3CE7F-kratos.sv @@ -0,0 +1,37 @@ +module FanoutHash_D70CFBE8EA3CE7F ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +assign sel0 = (~E0) | (~S0[0]) | I0; +assign sel1 = (~E1) | (~S1[0]) | I1; +assign sel2 = (~E2) | (~S2[2]) | I2; +assign sel3 = (~E3) | (~S3[14]) | I3; +assign sel4 = (~E4) | (~S4[14]) | I4; +assign sel5 = (~E5) | (~S5[14]) | I5; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5; +endmodule // FanoutHash_D70CFBE8EA3CE7F + diff --git a/sam/onyx/.magma/FanoutHash_E70AF988E4250F5-kratos.sv b/sam/onyx/.magma/FanoutHash_E70AF988E4250F5-kratos.sv new file mode 100644 index 00000000..7ad618e8 --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_E70AF988E4250F5-kratos.sv @@ -0,0 +1,108 @@ +module FanoutHash_E70AF988E4250F5 ( + input logic E0, + input logic E1, + input logic E10, + input logic E11, + input logic E12, + input logic E13, + input logic E14, + input logic E15, + input logic E16, + input logic E17, + input logic E18, + input logic E19, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic E6, + input logic E7, + input logic E8, + input logic E9, + input logic I0, + input logic I1, + input logic I10, + input logic I11, + input logic I12, + input logic I13, + input logic I14, + input logic I15, + input logic I16, + input logic I17, + input logic I18, + input logic I19, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic I6, + input logic I7, + input logic I8, + input logic I9, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S10, + input logic [7:0] S11, + input logic [7:0] S12, + input logic [7:0] S13, + input logic [7:0] S14, + input logic [7:0] S15, + input logic [7:0] S16, + input logic [7:0] S17, + input logic [7:0] S18, + input logic [7:0] S19, + input logic [7:0] S2, + input logic [7:0] S3, + input logic [7:0] S4, + input logic [7:0] S5, + input logic [7:0] S6, + input logic [7:0] S7, + input logic [7:0] S8, + input logic [7:0] S9, + output logic O +); + +logic sel0; +logic sel1; +logic sel10; +logic sel11; +logic sel12; +logic sel13; +logic sel14; +logic sel15; +logic sel16; +logic sel17; +logic sel18; +logic sel19; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +logic sel6; +logic sel7; +logic sel8; +logic sel9; +assign sel0 = (~E0) | (~S0[3]) | I0; +assign sel1 = (~E1) | (~S1[3]) | I1; +assign sel2 = (~E2) | (~S2[3]) | I2; +assign sel3 = (~E3) | (~S3[3]) | I3; +assign sel4 = (~E4) | (~S4[3]) | I4; +assign sel5 = (~E5) | (~S5[3]) | I5; +assign sel6 = (~E6) | (~S6[3]) | I6; +assign sel7 = (~E7) | (~S7[3]) | I7; +assign sel8 = (~E8) | (~S8[3]) | I8; +assign sel9 = (~E9) | (~S9[3]) | I9; +assign sel10 = (~E10) | (~S10[3]) | I10; +assign sel11 = (~E11) | (~S11[3]) | I11; +assign sel12 = (~E12) | (~S12[3]) | I12; +assign sel13 = (~E13) | (~S13[3]) | I13; +assign sel14 = (~E14) | (~S14[3]) | I14; +assign sel15 = (~E15) | (~S15[3]) | I15; +assign sel16 = (~E16) | (~S16[3]) | I16; +assign sel17 = (~E17) | (~S17[3]) | I17; +assign sel18 = (~E18) | (~S18[3]) | I18; +assign sel19 = (~E19) | (~S19[3]) | I19; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8 & sel9 & sel10 & + sel11 & sel12 & sel13 & sel14 & sel15 & sel16 & sel17 & sel18 & sel19; +endmodule // FanoutHash_E70AF988E4250F5 + diff --git a/sam/onyx/.magma/FanoutHash_F689C91787363AB-kratos.sv b/sam/onyx/.magma/FanoutHash_F689C91787363AB-kratos.sv new file mode 100644 index 00000000..99188fa0 --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_F689C91787363AB-kratos.sv @@ -0,0 +1,113 @@ +module FanoutHash_F689C91787363AB ( + input logic E0, + input logic E1, + input logic E10, + input logic E11, + input logic E12, + input logic E13, + input logic E14, + input logic E15, + input logic E16, + input logic E17, + input logic E18, + input logic E19, + input logic E2, + input logic E20, + input logic E3, + input logic E4, + input logic E5, + input logic E6, + input logic E7, + input logic E8, + input logic E9, + input logic I0, + input logic I1, + input logic I10, + input logic I11, + input logic I12, + input logic I13, + input logic I14, + input logic I15, + input logic I16, + input logic I17, + input logic I18, + input logic I19, + input logic I2, + input logic I20, + input logic I3, + input logic I4, + input logic I5, + input logic I6, + input logic I7, + input logic I8, + input logic I9, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S10, + input logic [7:0] S11, + input logic [7:0] S12, + input logic [7:0] S13, + input logic [7:0] S14, + input logic [7:0] S15, + input logic [7:0] S16, + input logic [7:0] S17, + input logic [7:0] S18, + input logic [7:0] S19, + input logic [7:0] S2, + input logic [31:0] S20, + input logic [7:0] S3, + input logic [7:0] S4, + input logic [7:0] S5, + input logic [7:0] S6, + input logic [7:0] S7, + input logic [7:0] S8, + input logic [7:0] S9, + output logic O +); + +logic sel0; +logic sel1; +logic sel10; +logic sel11; +logic sel12; +logic sel13; +logic sel14; +logic sel15; +logic sel16; +logic sel17; +logic sel18; +logic sel19; +logic sel2; +logic sel20; +logic sel3; +logic sel4; +logic sel5; +logic sel6; +logic sel7; +logic sel8; +logic sel9; +assign sel0 = (~E0) | (~S0[4]) | I0; +assign sel1 = (~E1) | (~S1[4]) | I1; +assign sel2 = (~E2) | (~S2[4]) | I2; +assign sel3 = (~E3) | (~S3[4]) | I3; +assign sel4 = (~E4) | (~S4[4]) | I4; +assign sel5 = (~E5) | (~S5[4]) | I5; +assign sel6 = (~E6) | (~S6[4]) | I6; +assign sel7 = (~E7) | (~S7[4]) | I7; +assign sel8 = (~E8) | (~S8[4]) | I8; +assign sel9 = (~E9) | (~S9[4]) | I9; +assign sel10 = (~E10) | (~S10[4]) | I10; +assign sel11 = (~E11) | (~S11[4]) | I11; +assign sel12 = (~E12) | (~S12[4]) | I12; +assign sel13 = (~E13) | (~S13[4]) | I13; +assign sel14 = (~E14) | (~S14[4]) | I14; +assign sel15 = (~E15) | (~S15[4]) | I15; +assign sel16 = (~E16) | (~S16[4]) | I16; +assign sel17 = (~E17) | (~S17[4]) | I17; +assign sel18 = (~E18) | (~S18[4]) | I18; +assign sel19 = (~E19) | (~S19[4]) | I19; +assign sel20 = (~E20) | (~S20[20]) | I20; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8 & sel9 & sel10 & + sel11 & sel12 & sel13 & sel14 & sel15 & sel16 & sel17 & sel18 & sel19 & sel20; +endmodule // FanoutHash_F689C91787363AB + diff --git a/sam/onyx/.magma/FanoutHash_F8E7A0823DC8CDD-kratos.sv b/sam/onyx/.magma/FanoutHash_F8E7A0823DC8CDD-kratos.sv new file mode 100644 index 00000000..e519ead7 --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_F8E7A0823DC8CDD-kratos.sv @@ -0,0 +1,37 @@ +module FanoutHash_F8E7A0823DC8CDD ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +assign sel0 = (~E0) | (~S0[0]) | I0; +assign sel1 = (~E1) | (~S1[2]) | I1; +assign sel2 = (~E2) | (~S2[2]) | I2; +assign sel3 = (~E3) | (~S3[11]) | I3; +assign sel4 = (~E4) | (~S4[11]) | I4; +assign sel5 = (~E5) | (~S5[11]) | I5; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5; +endmodule // FanoutHash_F8E7A0823DC8CDD + diff --git a/sam/onyx/.magma/FanoutHash_F95D10B01D02012-kratos.sv b/sam/onyx/.magma/FanoutHash_F95D10B01D02012-kratos.sv new file mode 100644 index 00000000..195a0d77 --- /dev/null +++ b/sam/onyx/.magma/FanoutHash_F95D10B01D02012-kratos.sv @@ -0,0 +1,37 @@ +module FanoutHash_F95D10B01D02012 ( + input logic E0, + input logic E1, + input logic E2, + input logic E3, + input logic E4, + input logic E5, + input logic I0, + input logic I1, + input logic I2, + input logic I3, + input logic I4, + input logic I5, + input logic [7:0] S0, + input logic [7:0] S1, + input logic [7:0] S2, + input logic [31:0] S3, + input logic [31:0] S4, + input logic [31:0] S5, + output logic O +); + +logic sel0; +logic sel1; +logic sel2; +logic sel3; +logic sel4; +logic sel5; +assign sel0 = (~E0) | (~S0[0]) | I0; +assign sel1 = (~E1) | (~S1[0]) | I1; +assign sel2 = (~E2) | (~S2[1]) | I2; +assign sel3 = (~E3) | (~S3[0]) | I3; +assign sel4 = (~E4) | (~S4[0]) | I4; +assign sel5 = (~E5) | (~S5[0]) | I5; +assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5; +endmodule // FanoutHash_F95D10B01D02012 + diff --git a/sam/onyx/.magma/MemCore_inner_W-kratos.sv b/sam/onyx/.magma/MemCore_inner_W-kratos.sv new file mode 100644 index 00000000..80260613 --- /dev/null +++ b/sam/onyx/.magma/MemCore_inner_W-kratos.sv @@ -0,0 +1,11527 @@ +module Chain_2_16 ( + input logic [1:0] accessor_output, + input logic [1:0] [15:0] chain_data_in, + input logic chain_en, + input logic clk_en, + input logic [1:0] [15:0] curr_tile_data_out, + input logic flush, + output logic [1:0] [15:0] data_out_tile +); + +always_comb begin + if (accessor_output[0]) begin + data_out_tile[0] = curr_tile_data_out[0]; + end + else if (chain_en) begin + data_out_tile[0] = chain_data_in[0]; + end + else data_out_tile[0] = 16'h0; + if (accessor_output[1]) begin + data_out_tile[1] = curr_tile_data_out[1]; + end + else if (chain_en) begin + data_out_tile[1] = chain_data_in[1]; + end + else data_out_tile[1] = 16'h0; +end +endmodule // Chain_2_16 + +module MemCore_inner ( + input logic [31:0] CONFIG_SPACE_0, + input logic [31:0] CONFIG_SPACE_1, + input logic [31:0] CONFIG_SPACE_10, + input logic [31:0] CONFIG_SPACE_11, + input logic [31:0] CONFIG_SPACE_12, + input logic [31:0] CONFIG_SPACE_13, + input logic [31:0] CONFIG_SPACE_14, + input logic [31:0] CONFIG_SPACE_15, + input logic [31:0] CONFIG_SPACE_16, + input logic [31:0] CONFIG_SPACE_17, + input logic [31:0] CONFIG_SPACE_18, + input logic [31:0] CONFIG_SPACE_19, + input logic [31:0] CONFIG_SPACE_2, + input logic [31:0] CONFIG_SPACE_20, + input logic [31:0] CONFIG_SPACE_21, + input logic [31:0] CONFIG_SPACE_22, + input logic [31:0] CONFIG_SPACE_23, + input logic [31:0] CONFIG_SPACE_24, + input logic [31:0] CONFIG_SPACE_25, + input logic [31:0] CONFIG_SPACE_26, + input logic [31:0] CONFIG_SPACE_27, + input logic [31:0] CONFIG_SPACE_28, + input logic [31:0] CONFIG_SPACE_29, + input logic [31:0] CONFIG_SPACE_3, + input logic [31:0] CONFIG_SPACE_30, + input logic [31:0] CONFIG_SPACE_31, + input logic [31:0] CONFIG_SPACE_32, + input logic [31:0] CONFIG_SPACE_33, + input logic [31:0] CONFIG_SPACE_34, + input logic [31:0] CONFIG_SPACE_35, + input logic [31:0] CONFIG_SPACE_36, + input logic [31:0] CONFIG_SPACE_37, + input logic [31:0] CONFIG_SPACE_38, + input logic [31:0] CONFIG_SPACE_39, + input logic [31:0] CONFIG_SPACE_4, + input logic [31:0] CONFIG_SPACE_40, + input logic [31:0] CONFIG_SPACE_41, + input logic [31:0] CONFIG_SPACE_42, + input logic [31:0] CONFIG_SPACE_43, + input logic [31:0] CONFIG_SPACE_44, + input logic [18:0] CONFIG_SPACE_45, + input logic [31:0] CONFIG_SPACE_5, + input logic [31:0] CONFIG_SPACE_6, + input logic [31:0] CONFIG_SPACE_7, + input logic [31:0] CONFIG_SPACE_8, + input logic [31:0] CONFIG_SPACE_9, + input logic [0:0] [16:0] MEM_input_width_17_num_0, + input logic MEM_input_width_17_num_0_valid, + input logic [0:0] [16:0] MEM_input_width_17_num_1, + input logic MEM_input_width_17_num_1_valid, + input logic [0:0] [16:0] MEM_input_width_17_num_2, + input logic MEM_input_width_17_num_2_valid, + input logic [0:0] [16:0] MEM_input_width_17_num_3, + input logic MEM_input_width_17_num_3_valid, + input logic MEM_input_width_1_num_0, + input logic MEM_input_width_1_num_1, + input logic MEM_output_width_17_num_0_ready, + input logic MEM_output_width_17_num_1_ready, + input logic MEM_output_width_17_num_2_ready, + input logic clk, + input logic clk_en, + input logic [7:0] config_addr_in, + input logic [31:0] config_data_in, + input logic [1:0] config_en, + input logic config_read, + input logic config_write, + input logic flush, + input logic [1:0] mode, + input logic mode_excl, + input logic rst_n, + input logic tile_en, + output logic MEM_input_width_17_num_0_ready, + output logic MEM_input_width_17_num_1_ready, + output logic MEM_input_width_17_num_2_ready, + output logic MEM_input_width_17_num_3_ready, + output logic [0:0] [16:0] MEM_output_width_17_num_0, + output logic MEM_output_width_17_num_0_valid, + output logic [0:0] [16:0] MEM_output_width_17_num_1, + output logic MEM_output_width_17_num_1_valid, + output logic [0:0] [16:0] MEM_output_width_17_num_2, + output logic MEM_output_width_17_num_2_valid, + output logic MEM_output_width_1_num_0, + output logic MEM_output_width_1_num_1, + output logic MEM_output_width_1_num_2, + output logic [1:0] [31:0] config_data_out +); + +logic [1458:0] CONFIG_SPACE; +logic [15:0] config_data_in_shrt; +logic [1:0][15:0] config_data_out_shrt; +logic [8:0] config_seq_addr_out; +logic config_seq_clk_en; +logic [0:0][3:0][15:0] config_seq_rd_data_stg; +logic config_seq_ren_out; +logic config_seq_wen_out; +logic [3:0][15:0] config_seq_wr_data; +logic gclk; +logic [0:0][16:0] input_width_17_num_0_fifo_out; +logic input_width_17_num_0_fifo_out_ready; +logic input_width_17_num_0_fifo_out_valid; +logic input_width_17_num_0_input_fifo_empty; +logic input_width_17_num_0_input_fifo_full; +logic [0:0][16:0] input_width_17_num_1_fifo_out; +logic input_width_17_num_1_fifo_out_ready; +logic input_width_17_num_1_fifo_out_valid; +logic input_width_17_num_1_input_fifo_empty; +logic input_width_17_num_1_input_fifo_full; +logic [0:0][16:0] input_width_17_num_2_fifo_out; +logic input_width_17_num_2_fifo_out_ready; +logic input_width_17_num_2_fifo_out_valid; +logic input_width_17_num_2_input_fifo_empty; +logic input_width_17_num_2_input_fifo_full; +logic [0:0][16:0] input_width_17_num_3_fifo_out; +logic input_width_17_num_3_fifo_out_ready; +logic input_width_17_num_3_fifo_out_valid; +logic input_width_17_num_3_input_fifo_empty; +logic input_width_17_num_3_input_fifo_full; +logic mem_ctrl_fiber_access_16_flat_clk; +logic [8:0] mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_addr_to_mem_lifted_lifted; +logic [3:0] mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_buffet_capacity_log_0; +logic [3:0] mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_buffet_capacity_log_1; +logic [3:0][15:0] mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_data_from_mem_lifted_lifted; +logic [3:0][15:0] mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_data_to_mem_lifted_lifted; +logic mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_ren_to_mem_lifted_lifted; +logic mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_tile_en; +logic mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_wen_to_mem_lifted_lifted; +logic mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_block_mode; +logic mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_dense; +logic [15:0] mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_dim_size; +logic mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_do_repeat; +logic [15:0] mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_inner_dim_offset; +logic mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_lookup; +logic [15:0] mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_repeat_factor; +logic mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_repeat_outer_inner_n; +logic mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_root; +logic mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_tile_en; +logic mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_tile_en; +logic mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_vector_reduce_mode; +logic mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_write_scanner_block_mode; +logic mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_write_scanner_compressed; +logic mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_write_scanner_init_blank; +logic mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_write_scanner_lowest_level; +logic [15:0] mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_write_scanner_stop_lvl; +logic mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_write_scanner_tile_en; +logic [0:0][16:0] mem_ctrl_fiber_access_16_flat_read_scanner_block_rd_out_f_; +logic mem_ctrl_fiber_access_16_flat_read_scanner_block_rd_out_valid_f_; +logic [0:0][16:0] mem_ctrl_fiber_access_16_flat_read_scanner_coord_out_f_; +logic mem_ctrl_fiber_access_16_flat_read_scanner_coord_out_valid_f_; +logic [0:0][16:0] mem_ctrl_fiber_access_16_flat_read_scanner_pos_out_f_; +logic mem_ctrl_fiber_access_16_flat_read_scanner_pos_out_valid_f_; +logic mem_ctrl_fiber_access_16_flat_read_scanner_us_pos_in_ready_f_; +logic mem_ctrl_fiber_access_16_flat_write_scanner_addr_in_ready_f_; +logic mem_ctrl_fiber_access_16_flat_write_scanner_block_wr_in_ready_f_; +logic mem_ctrl_fiber_access_16_flat_write_scanner_data_in_ready_f_; +logic mem_ctrl_stencil_valid_flat_clk; +logic mem_ctrl_stencil_valid_flat_stencil_valid_f_; +logic [3:0] mem_ctrl_stencil_valid_flat_stencil_valid_inst_loops_stencil_valid_dimensionality; +logic [10:0] mem_ctrl_stencil_valid_flat_stencil_valid_inst_loops_stencil_valid_ranges_0; +logic [10:0] mem_ctrl_stencil_valid_flat_stencil_valid_inst_loops_stencil_valid_ranges_1; +logic [10:0] mem_ctrl_stencil_valid_flat_stencil_valid_inst_loops_stencil_valid_ranges_2; +logic [10:0] mem_ctrl_stencil_valid_flat_stencil_valid_inst_loops_stencil_valid_ranges_3; +logic [10:0] mem_ctrl_stencil_valid_flat_stencil_valid_inst_loops_stencil_valid_ranges_4; +logic [10:0] mem_ctrl_stencil_valid_flat_stencil_valid_inst_loops_stencil_valid_ranges_5; +logic mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_enable; +logic [15:0] mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_starting_addr; +logic [15:0] mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_0; +logic [15:0] mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_1; +logic [15:0] mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_2; +logic [15:0] mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_3; +logic [15:0] mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_4; +logic [15:0] mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_5; +logic mem_ctrl_strg_ram_64_512_delay1_flat_clk; +logic [0:0][16:0] mem_ctrl_strg_ram_64_512_delay1_flat_data_out_f_; +logic mem_ctrl_strg_ram_64_512_delay1_flat_ready_f_; +logic [0:0][8:0] mem_ctrl_strg_ram_64_512_delay1_flat_strg_ram_64_512_delay1_inst_addr_out_lifted; +logic [0:0][3:0][15:0] mem_ctrl_strg_ram_64_512_delay1_flat_strg_ram_64_512_delay1_inst_data_from_strg_lifted; +logic [0:0][3:0][15:0] mem_ctrl_strg_ram_64_512_delay1_flat_strg_ram_64_512_delay1_inst_data_to_strg_lifted; +logic mem_ctrl_strg_ram_64_512_delay1_flat_strg_ram_64_512_delay1_inst_ren_to_strg_lifted; +logic mem_ctrl_strg_ram_64_512_delay1_flat_strg_ram_64_512_delay1_inst_wen_to_strg_lifted; +logic mem_ctrl_strg_ram_64_512_delay1_flat_valid_out_f_; +logic mem_ctrl_strg_ub_vec_flat_accessor_output_f_b_0; +logic mem_ctrl_strg_ub_vec_flat_accessor_output_f_b_1; +logic mem_ctrl_strg_ub_vec_flat_clk; +logic [0:0][16:0] mem_ctrl_strg_ub_vec_flat_data_out_f_0; +logic [0:0][16:0] mem_ctrl_strg_ub_vec_flat_data_out_f_1; +logic [8:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_addr_out_lifted; +logic [2:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_starting_addr; +logic [2:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_strides_0; +logic [2:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_strides_1; +logic [2:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_strides_2; +logic [2:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_starting_addr; +logic [2:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_strides_0; +logic [2:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_strides_1; +logic [2:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_strides_2; +logic mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_enable; +logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_starting_addr; +logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_0; +logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_1; +logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_2; +logic mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_enable; +logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_starting_addr; +logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_0; +logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_1; +logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_2; +logic [2:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_0_dimensionality; +logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_0_ranges_0; +logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_0_ranges_1; +logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_0_ranges_2; +logic [2:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_1_dimensionality; +logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_1_ranges_0; +logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_1_ranges_1; +logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_1_ranges_2; +logic [7:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_sram_shared_agg_read_sched_gen_0_agg_read_padding; +logic [7:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_sram_shared_agg_read_sched_gen_1_agg_read_padding; +logic [8:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_sram_shared_agg_sram_shared_addr_gen_0_starting_addr; +logic [8:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_sram_shared_agg_sram_shared_addr_gen_1_starting_addr; +logic [1:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_sram_shared_mode_0; +logic [1:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_sram_shared_mode_1; +logic mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_chain_chain_en; +logic [3:0][15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_data_from_strg_lifted; +logic [3:0][15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_data_to_strg_lifted; +logic mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_ren_to_strg_lifted; +logic [8:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_0_starting_addr; +logic [8:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_0; +logic [8:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_1; +logic [8:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_2; +logic [8:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_3; +logic [8:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_4; +logic [8:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_5; +logic [8:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_1_starting_addr; +logic [8:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_0; +logic [8:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_1; +logic [8:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_2; +logic [8:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_3; +logic [8:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_4; +logic [8:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_5; +logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_dimensionality; +logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_0; +logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_1; +logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_2; +logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_3; +logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_4; +logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_5; +logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_dimensionality; +logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_0; +logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_1; +logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_2; +logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_3; +logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_4; +logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_5; +logic mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_enable; +logic [9:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_delay; +logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_starting_addr; +logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_0; +logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_1; +logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_2; +logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_3; +logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_4; +logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_5; +logic mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_enable; +logic [9:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_delay; +logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_starting_addr; +logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_0; +logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_1; +logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_2; +logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_3; +logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_4; +logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_5; +logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_0_dimensionality; +logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_0; +logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_1; +logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_2; +logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_3; +logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_4; +logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_5; +logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_1_dimensionality; +logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_0; +logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_1; +logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_2; +logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_3; +logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_4; +logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_5; +logic mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_shared_tb_0; +logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_starting_addr; +logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_0; +logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_1; +logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_2; +logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_3; +logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_4; +logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_5; +logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_starting_addr; +logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_0; +logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_1; +logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_2; +logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_3; +logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_4; +logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_5; +logic mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_enable; +logic [9:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_delay; +logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_starting_addr; +logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_0; +logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_1; +logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_2; +logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_3; +logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_4; +logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_5; +logic mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_enable; +logic [9:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_delay; +logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_starting_addr; +logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_0; +logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_1; +logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_2; +logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_3; +logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_4; +logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_5; +logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_starting_addr; +logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_0; +logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_1; +logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_2; +logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_3; +logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_4; +logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_5; +logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_starting_addr; +logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_0; +logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_1; +logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_2; +logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_3; +logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_4; +logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_5; +logic mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_wen_to_strg_lifted; +logic memory_0_clk_en; +logic [63:0] memory_0_data_in_p0; +logic [63:0] memory_0_data_out_p0; +logic [8:0] memory_0_read_addr_p0; +logic memory_0_read_enable_p0; +logic [8:0] memory_0_write_addr_p0; +logic memory_0_write_enable_p0; +logic [0:0][16:0] output_width_17_num_0_fifo_in; +logic output_width_17_num_0_fifo_in_ready; +logic output_width_17_num_0_fifo_in_valid; +logic [0:0][16:0] output_width_17_num_0_output_fifo_data_out; +logic output_width_17_num_0_output_fifo_empty; +logic output_width_17_num_0_output_fifo_full; +logic [0:0][16:0] output_width_17_num_1_fifo_in; +logic output_width_17_num_1_fifo_in_ready; +logic output_width_17_num_1_fifo_in_valid; +logic [0:0][16:0] output_width_17_num_1_output_fifo_data_out; +logic output_width_17_num_1_output_fifo_empty; +logic output_width_17_num_1_output_fifo_full; +logic [0:0][16:0] output_width_17_num_2_fifo_in; +logic output_width_17_num_2_fifo_in_ready; +logic output_width_17_num_2_fifo_in_valid; +logic [0:0][16:0] output_width_17_num_2_output_fifo_data_out; +logic output_width_17_num_2_output_fifo_empty; +logic output_width_17_num_2_output_fifo_full; +assign gclk = clk & tile_en; +assign mem_ctrl_fiber_access_16_flat_clk = gclk & (mode == 2'h0); +assign mem_ctrl_strg_ub_vec_flat_clk = gclk & (mode == 2'h1); +assign mem_ctrl_strg_ram_64_512_delay1_flat_clk = gclk & (mode == 2'h2); +assign mem_ctrl_stencil_valid_flat_clk = gclk; +assign input_width_17_num_0_fifo_out_valid = ~input_width_17_num_0_input_fifo_empty; +always_comb begin + input_width_17_num_0_fifo_out_ready = 1'h1; + if (mode == 2'h0) begin + input_width_17_num_0_fifo_out_ready = mem_ctrl_fiber_access_16_flat_read_scanner_us_pos_in_ready_f_; + end + else input_width_17_num_0_fifo_out_ready = 1'h1; +end +always_comb begin + MEM_input_width_17_num_0_ready = 1'h1; + if (mode == 2'h0) begin + MEM_input_width_17_num_0_ready = ~input_width_17_num_0_input_fifo_full; + end + else if (mode == 2'h1) begin + MEM_input_width_17_num_0_ready = 1'h1; + end + else if (mode == 2'h2) begin + MEM_input_width_17_num_0_ready = 1'h1; + end +end +assign input_width_17_num_1_fifo_out_valid = ~input_width_17_num_1_input_fifo_empty; +always_comb begin + input_width_17_num_1_fifo_out_ready = 1'h1; + if (mode == 2'h0) begin + input_width_17_num_1_fifo_out_ready = mem_ctrl_fiber_access_16_flat_write_scanner_addr_in_ready_f_; + end + else input_width_17_num_1_fifo_out_ready = 1'h1; +end +always_comb begin + MEM_input_width_17_num_1_ready = 1'h1; + if (mode == 2'h0) begin + MEM_input_width_17_num_1_ready = ~input_width_17_num_1_input_fifo_full; + end + else if (mode == 2'h1) begin + MEM_input_width_17_num_1_ready = 1'h1; + end + else if (mode == 2'h2) begin + MEM_input_width_17_num_1_ready = 1'h1; + end +end +assign input_width_17_num_2_fifo_out_valid = ~input_width_17_num_2_input_fifo_empty; +always_comb begin + input_width_17_num_2_fifo_out_ready = 1'h1; + if (mode == 2'h0) begin + input_width_17_num_2_fifo_out_ready = mem_ctrl_fiber_access_16_flat_write_scanner_block_wr_in_ready_f_; + end + else input_width_17_num_2_fifo_out_ready = 1'h1; +end +always_comb begin + MEM_input_width_17_num_2_ready = 1'h1; + if (mode == 2'h0) begin + MEM_input_width_17_num_2_ready = ~input_width_17_num_2_input_fifo_full; + end + else if (mode == 2'h1) begin + MEM_input_width_17_num_2_ready = 1'h1; + end + else if (mode == 2'h2) begin + MEM_input_width_17_num_2_ready = 1'h1; + end +end +assign input_width_17_num_3_fifo_out_valid = ~input_width_17_num_3_input_fifo_empty; +always_comb begin + input_width_17_num_3_fifo_out_ready = 1'h1; + if (mode == 2'h0) begin + input_width_17_num_3_fifo_out_ready = mem_ctrl_fiber_access_16_flat_write_scanner_data_in_ready_f_; + end + else input_width_17_num_3_fifo_out_ready = 1'h1; +end +always_comb begin + MEM_input_width_17_num_3_ready = 1'h1; + if (mode == 2'h0) begin + MEM_input_width_17_num_3_ready = ~input_width_17_num_3_input_fifo_full; + end + else if (mode == 2'h1) begin + MEM_input_width_17_num_3_ready = 1'h1; + end +end +assign output_width_17_num_0_fifo_in_ready = ~output_width_17_num_0_output_fifo_full; +always_comb begin + output_width_17_num_0_fifo_in = 17'h0; + output_width_17_num_0_fifo_in_valid = 1'h0; + output_width_17_num_0_fifo_in = mem_ctrl_fiber_access_16_flat_read_scanner_block_rd_out_f_; + output_width_17_num_0_fifo_in_valid = mem_ctrl_fiber_access_16_flat_read_scanner_block_rd_out_valid_f_; +end +always_comb begin + MEM_output_width_17_num_0 = 17'h0; + if (mode == 2'h0) begin + MEM_output_width_17_num_0 = output_width_17_num_0_output_fifo_data_out; + end + else if (mode == 2'h1) begin + MEM_output_width_17_num_0 = mem_ctrl_strg_ub_vec_flat_data_out_f_0; + end + else if (mode == 2'h2) begin + MEM_output_width_17_num_0 = mem_ctrl_strg_ram_64_512_delay1_flat_data_out_f_; + end +end +always_comb begin + MEM_output_width_17_num_0_valid = 1'h0; + if (mode == 2'h0) begin + MEM_output_width_17_num_0_valid = ~output_width_17_num_0_output_fifo_empty; + end + else if (mode == 2'h1) begin + MEM_output_width_17_num_0_valid = 1'h1; + end + else if (mode == 2'h2) begin + MEM_output_width_17_num_0_valid = 1'h1; + end +end +assign output_width_17_num_1_fifo_in_ready = ~output_width_17_num_1_output_fifo_full; +always_comb begin + output_width_17_num_1_fifo_in = 17'h0; + output_width_17_num_1_fifo_in_valid = 1'h0; + output_width_17_num_1_fifo_in = mem_ctrl_fiber_access_16_flat_read_scanner_coord_out_f_; + output_width_17_num_1_fifo_in_valid = mem_ctrl_fiber_access_16_flat_read_scanner_coord_out_valid_f_; +end +always_comb begin + MEM_output_width_17_num_1 = 17'h0; + if (mode == 2'h0) begin + MEM_output_width_17_num_1 = output_width_17_num_1_output_fifo_data_out; + end + else if (mode == 2'h1) begin + MEM_output_width_17_num_1 = mem_ctrl_strg_ub_vec_flat_data_out_f_1; + end +end +always_comb begin + MEM_output_width_17_num_1_valid = 1'h0; + if (mode == 2'h0) begin + MEM_output_width_17_num_1_valid = ~output_width_17_num_1_output_fifo_empty; + end + else if (mode == 2'h1) begin + MEM_output_width_17_num_1_valid = 1'h1; + end +end +assign output_width_17_num_2_fifo_in_ready = ~output_width_17_num_2_output_fifo_full; +always_comb begin + output_width_17_num_2_fifo_in = 17'h0; + output_width_17_num_2_fifo_in_valid = 1'h0; + output_width_17_num_2_fifo_in = mem_ctrl_fiber_access_16_flat_read_scanner_pos_out_f_; + output_width_17_num_2_fifo_in_valid = mem_ctrl_fiber_access_16_flat_read_scanner_pos_out_valid_f_; +end +always_comb begin + MEM_output_width_17_num_2 = 17'h0; + if (mode == 2'h0) begin + MEM_output_width_17_num_2 = output_width_17_num_2_output_fifo_data_out; + end + else MEM_output_width_17_num_2 = 17'h0; +end +always_comb begin + MEM_output_width_17_num_2_valid = 1'h0; + if (mode == 2'h0) begin + MEM_output_width_17_num_2_valid = ~output_width_17_num_2_output_fifo_empty; + end + else MEM_output_width_17_num_2_valid = 1'h0; +end +always_comb begin + MEM_output_width_1_num_0 = 1'h0; + if (mode == 2'h1) begin + MEM_output_width_1_num_0 = mem_ctrl_strg_ub_vec_flat_accessor_output_f_b_0; + end + else if (mode == 2'h2) begin + MEM_output_width_1_num_0 = mem_ctrl_strg_ram_64_512_delay1_flat_ready_f_; + end +end +always_comb begin + MEM_output_width_1_num_1 = 1'h0; + if (mode == 2'h1) begin + MEM_output_width_1_num_1 = mem_ctrl_strg_ub_vec_flat_accessor_output_f_b_1; + end + else if (mode == 2'h2) begin + MEM_output_width_1_num_1 = mem_ctrl_strg_ram_64_512_delay1_flat_valid_out_f_; + end +end +always_comb begin + MEM_output_width_1_num_2 = 1'h0; + if (mode_excl == 1'h1) begin + MEM_output_width_1_num_2 = mem_ctrl_stencil_valid_flat_stencil_valid_f_; + end + else MEM_output_width_1_num_2 = 1'h0; +end +always_comb begin + memory_0_data_in_p0 = 64'h0; + memory_0_write_addr_p0 = 9'h0; + memory_0_write_enable_p0 = 1'h0; + memory_0_read_addr_p0 = 9'h0; + memory_0_read_enable_p0 = 1'h0; + if (|config_en) begin + memory_0_data_in_p0 = config_seq_wr_data; + memory_0_write_addr_p0 = config_seq_addr_out; + memory_0_write_enable_p0 = config_seq_wen_out; + memory_0_read_addr_p0 = config_seq_addr_out; + memory_0_read_enable_p0 = config_seq_ren_out; + end + else if (mode == 2'h0) begin + memory_0_data_in_p0 = mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_data_to_mem_lifted_lifted; + memory_0_write_addr_p0 = mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_addr_to_mem_lifted_lifted; + memory_0_write_enable_p0 = mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_wen_to_mem_lifted_lifted; + memory_0_read_addr_p0 = mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_addr_to_mem_lifted_lifted; + memory_0_read_enable_p0 = mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_ren_to_mem_lifted_lifted; + end + else if (mode == 2'h1) begin + memory_0_data_in_p0 = mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_data_to_strg_lifted; + memory_0_write_addr_p0 = mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_addr_out_lifted; + memory_0_write_enable_p0 = mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_wen_to_strg_lifted; + memory_0_read_addr_p0 = mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_addr_out_lifted; + memory_0_read_enable_p0 = mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_ren_to_strg_lifted; + end + else if (mode == 2'h2) begin + memory_0_data_in_p0 = mem_ctrl_strg_ram_64_512_delay1_flat_strg_ram_64_512_delay1_inst_data_to_strg_lifted; + memory_0_write_addr_p0 = mem_ctrl_strg_ram_64_512_delay1_flat_strg_ram_64_512_delay1_inst_addr_out_lifted; + memory_0_write_enable_p0 = mem_ctrl_strg_ram_64_512_delay1_flat_strg_ram_64_512_delay1_inst_wen_to_strg_lifted; + memory_0_read_addr_p0 = mem_ctrl_strg_ram_64_512_delay1_flat_strg_ram_64_512_delay1_inst_addr_out_lifted; + memory_0_read_enable_p0 = mem_ctrl_strg_ram_64_512_delay1_flat_strg_ram_64_512_delay1_inst_ren_to_strg_lifted; + end +end +always_comb begin + mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_data_from_mem_lifted_lifted = memory_0_data_out_p0; + mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_data_from_strg_lifted = memory_0_data_out_p0; + mem_ctrl_strg_ram_64_512_delay1_flat_strg_ram_64_512_delay1_inst_data_from_strg_lifted = memory_0_data_out_p0; + config_seq_rd_data_stg = memory_0_data_out_p0; +end +assign config_data_in_shrt = config_data_in[15:0]; +assign config_data_out[0] = 32'(config_data_out_shrt[0]); +assign config_data_out[1] = 32'(config_data_out_shrt[1]); +assign config_seq_clk_en = clk_en | (|config_en); +assign memory_0_clk_en = clk_en | (|config_en); +assign {mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_buffet_capacity_log_0, mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_buffet_capacity_log_1, mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_tile_en, mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_block_mode, mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_dense, mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_dim_size, mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_do_repeat, mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_inner_dim_offset, mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_lookup, mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_repeat_factor, mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_repeat_outer_inner_n, mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_root, mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_tile_en, mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_tile_en, mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_vector_reduce_mode, mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_write_scanner_block_mode, mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_write_scanner_compressed, mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_write_scanner_init_blank, mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_write_scanner_lowest_level, mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_write_scanner_stop_lvl, mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_write_scanner_tile_en} = CONFIG_SPACE[86:0]; +assign {mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_starting_addr, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_strides_0, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_strides_1, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_strides_2, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_starting_addr, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_strides_0, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_strides_1, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_strides_2, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_enable, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_starting_addr, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_0, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_1, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_2, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_enable, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_starting_addr, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_0, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_1, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_2, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_0_dimensionality, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_0_ranges_0, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_0_ranges_1, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_0_ranges_2, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_1_dimensionality, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_1_ranges_0, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_1_ranges_1, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_1_ranges_2, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_sram_shared_agg_read_sched_gen_0_agg_read_padding, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_sram_shared_agg_read_sched_gen_1_agg_read_padding, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_sram_shared_agg_sram_shared_addr_gen_0_starting_addr, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_sram_shared_agg_sram_shared_addr_gen_1_starting_addr, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_sram_shared_mode_0, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_sram_shared_mode_1, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_chain_chain_en, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_0_starting_addr, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_0, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_1, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_2, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_3, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_4, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_5, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_1_starting_addr, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_0, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_1, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_2, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_3, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_4, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_5, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_dimensionality, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_0, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_1, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_2, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_3, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_4, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_5, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_dimensionality, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_0, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_1, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_2, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_3, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_4, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_5, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_enable, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_delay, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_starting_addr, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_0, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_1, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_2, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_3, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_4, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_5, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_enable, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_delay, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_starting_addr, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_0, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_1, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_2, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_3, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_4, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_5, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_0_dimensionality, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_0, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_1, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_2, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_3, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_4, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_5, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_1_dimensionality, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_0, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_1, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_2, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_3, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_4, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_5, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_shared_tb_0, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_starting_addr, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_0, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_1, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_2, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_3, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_4, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_5, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_starting_addr, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_0, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_1, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_2, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_3, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_4, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_5, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_enable, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_delay, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_starting_addr, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_0, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_1, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_2, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_3, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_4, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_5, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_enable, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_delay, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_starting_addr, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_0, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_1, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_2, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_3, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_4, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_5, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_starting_addr, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_0, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_1, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_2, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_3, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_4, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_5, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_starting_addr, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_0, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_1, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_2, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_3, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_4, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_5} = CONFIG_SPACE[1275:0]; +assign {mem_ctrl_stencil_valid_flat_stencil_valid_inst_loops_stencil_valid_dimensionality, mem_ctrl_stencil_valid_flat_stencil_valid_inst_loops_stencil_valid_ranges_0, mem_ctrl_stencil_valid_flat_stencil_valid_inst_loops_stencil_valid_ranges_1, mem_ctrl_stencil_valid_flat_stencil_valid_inst_loops_stencil_valid_ranges_2, mem_ctrl_stencil_valid_flat_stencil_valid_inst_loops_stencil_valid_ranges_3, mem_ctrl_stencil_valid_flat_stencil_valid_inst_loops_stencil_valid_ranges_4, mem_ctrl_stencil_valid_flat_stencil_valid_inst_loops_stencil_valid_ranges_5, mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_enable, mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_starting_addr, mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_0, mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_1, mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_2, mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_3, mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_4, mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_5} = CONFIG_SPACE[1458:1276]; +assign CONFIG_SPACE[31:0] = CONFIG_SPACE_0; +assign CONFIG_SPACE[63:32] = CONFIG_SPACE_1; +assign CONFIG_SPACE[95:64] = CONFIG_SPACE_2; +assign CONFIG_SPACE[127:96] = CONFIG_SPACE_3; +assign CONFIG_SPACE[159:128] = CONFIG_SPACE_4; +assign CONFIG_SPACE[191:160] = CONFIG_SPACE_5; +assign CONFIG_SPACE[223:192] = CONFIG_SPACE_6; +assign CONFIG_SPACE[255:224] = CONFIG_SPACE_7; +assign CONFIG_SPACE[287:256] = CONFIG_SPACE_8; +assign CONFIG_SPACE[319:288] = CONFIG_SPACE_9; +assign CONFIG_SPACE[351:320] = CONFIG_SPACE_10; +assign CONFIG_SPACE[383:352] = CONFIG_SPACE_11; +assign CONFIG_SPACE[415:384] = CONFIG_SPACE_12; +assign CONFIG_SPACE[447:416] = CONFIG_SPACE_13; +assign CONFIG_SPACE[479:448] = CONFIG_SPACE_14; +assign CONFIG_SPACE[511:480] = CONFIG_SPACE_15; +assign CONFIG_SPACE[543:512] = CONFIG_SPACE_16; +assign CONFIG_SPACE[575:544] = CONFIG_SPACE_17; +assign CONFIG_SPACE[607:576] = CONFIG_SPACE_18; +assign CONFIG_SPACE[639:608] = CONFIG_SPACE_19; +assign CONFIG_SPACE[671:640] = CONFIG_SPACE_20; +assign CONFIG_SPACE[703:672] = CONFIG_SPACE_21; +assign CONFIG_SPACE[735:704] = CONFIG_SPACE_22; +assign CONFIG_SPACE[767:736] = CONFIG_SPACE_23; +assign CONFIG_SPACE[799:768] = CONFIG_SPACE_24; +assign CONFIG_SPACE[831:800] = CONFIG_SPACE_25; +assign CONFIG_SPACE[863:832] = CONFIG_SPACE_26; +assign CONFIG_SPACE[895:864] = CONFIG_SPACE_27; +assign CONFIG_SPACE[927:896] = CONFIG_SPACE_28; +assign CONFIG_SPACE[959:928] = CONFIG_SPACE_29; +assign CONFIG_SPACE[991:960] = CONFIG_SPACE_30; +assign CONFIG_SPACE[1023:992] = CONFIG_SPACE_31; +assign CONFIG_SPACE[1055:1024] = CONFIG_SPACE_32; +assign CONFIG_SPACE[1087:1056] = CONFIG_SPACE_33; +assign CONFIG_SPACE[1119:1088] = CONFIG_SPACE_34; +assign CONFIG_SPACE[1151:1120] = CONFIG_SPACE_35; +assign CONFIG_SPACE[1183:1152] = CONFIG_SPACE_36; +assign CONFIG_SPACE[1215:1184] = CONFIG_SPACE_37; +assign CONFIG_SPACE[1247:1216] = CONFIG_SPACE_38; +assign CONFIG_SPACE[1279:1248] = CONFIG_SPACE_39; +assign CONFIG_SPACE[1311:1280] = CONFIG_SPACE_40; +assign CONFIG_SPACE[1343:1312] = CONFIG_SPACE_41; +assign CONFIG_SPACE[1375:1344] = CONFIG_SPACE_42; +assign CONFIG_SPACE[1407:1376] = CONFIG_SPACE_43; +assign CONFIG_SPACE[1439:1408] = CONFIG_SPACE_44; +assign CONFIG_SPACE[1458:1440] = CONFIG_SPACE_45; +fiber_access_16_flat mem_ctrl_fiber_access_16_flat ( + .clk(mem_ctrl_fiber_access_16_flat_clk), + .clk_en(clk_en), + .fiber_access_16_inst_buffet_buffet_capacity_log_0(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_buffet_capacity_log_0), + .fiber_access_16_inst_buffet_buffet_capacity_log_1(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_buffet_capacity_log_1), + .fiber_access_16_inst_buffet_data_from_mem_lifted_lifted(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_data_from_mem_lifted_lifted), + .fiber_access_16_inst_buffet_tile_en(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_tile_en), + .fiber_access_16_inst_read_scanner_block_mode(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_block_mode), + .fiber_access_16_inst_read_scanner_dense(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_dense), + .fiber_access_16_inst_read_scanner_dim_size(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_dim_size), + .fiber_access_16_inst_read_scanner_do_repeat(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_do_repeat), + .fiber_access_16_inst_read_scanner_inner_dim_offset(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_inner_dim_offset), + .fiber_access_16_inst_read_scanner_lookup(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_lookup), + .fiber_access_16_inst_read_scanner_repeat_factor(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_repeat_factor), + .fiber_access_16_inst_read_scanner_repeat_outer_inner_n(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_repeat_outer_inner_n), + .fiber_access_16_inst_read_scanner_root(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_root), + .fiber_access_16_inst_read_scanner_tile_en(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_tile_en), + .fiber_access_16_inst_tile_en(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_tile_en), + .fiber_access_16_inst_vector_reduce_mode(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_vector_reduce_mode), + .fiber_access_16_inst_write_scanner_block_mode(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_write_scanner_block_mode), + .fiber_access_16_inst_write_scanner_compressed(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_write_scanner_compressed), + .fiber_access_16_inst_write_scanner_init_blank(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_write_scanner_init_blank), + .fiber_access_16_inst_write_scanner_lowest_level(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_write_scanner_lowest_level), + .fiber_access_16_inst_write_scanner_stop_lvl(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_write_scanner_stop_lvl), + .fiber_access_16_inst_write_scanner_tile_en(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_write_scanner_tile_en), + .flush(flush), + .read_scanner_block_rd_out_ready_f_(output_width_17_num_0_fifo_in_ready), + .read_scanner_coord_out_ready_f_(output_width_17_num_1_fifo_in_ready), + .read_scanner_pos_out_ready_f_(output_width_17_num_2_fifo_in_ready), + .read_scanner_us_pos_in_f_(input_width_17_num_0_fifo_out), + .read_scanner_us_pos_in_valid_f_(input_width_17_num_0_fifo_out_valid), + .rst_n(rst_n), + .write_scanner_addr_in_f_(input_width_17_num_1_fifo_out), + .write_scanner_addr_in_valid_f_(input_width_17_num_1_fifo_out_valid), + .write_scanner_block_wr_in_f_(input_width_17_num_2_fifo_out), + .write_scanner_block_wr_in_valid_f_(input_width_17_num_2_fifo_out_valid), + .write_scanner_data_in_f_(input_width_17_num_3_fifo_out), + .write_scanner_data_in_valid_f_(input_width_17_num_3_fifo_out_valid), + .fiber_access_16_inst_buffet_addr_to_mem_lifted_lifted(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_addr_to_mem_lifted_lifted), + .fiber_access_16_inst_buffet_data_to_mem_lifted_lifted(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_data_to_mem_lifted_lifted), + .fiber_access_16_inst_buffet_ren_to_mem_lifted_lifted(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_ren_to_mem_lifted_lifted), + .fiber_access_16_inst_buffet_wen_to_mem_lifted_lifted(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_wen_to_mem_lifted_lifted), + .read_scanner_block_rd_out_f_(mem_ctrl_fiber_access_16_flat_read_scanner_block_rd_out_f_), + .read_scanner_block_rd_out_valid_f_(mem_ctrl_fiber_access_16_flat_read_scanner_block_rd_out_valid_f_), + .read_scanner_coord_out_f_(mem_ctrl_fiber_access_16_flat_read_scanner_coord_out_f_), + .read_scanner_coord_out_valid_f_(mem_ctrl_fiber_access_16_flat_read_scanner_coord_out_valid_f_), + .read_scanner_pos_out_f_(mem_ctrl_fiber_access_16_flat_read_scanner_pos_out_f_), + .read_scanner_pos_out_valid_f_(mem_ctrl_fiber_access_16_flat_read_scanner_pos_out_valid_f_), + .read_scanner_us_pos_in_ready_f_(mem_ctrl_fiber_access_16_flat_read_scanner_us_pos_in_ready_f_), + .write_scanner_addr_in_ready_f_(mem_ctrl_fiber_access_16_flat_write_scanner_addr_in_ready_f_), + .write_scanner_block_wr_in_ready_f_(mem_ctrl_fiber_access_16_flat_write_scanner_block_wr_in_ready_f_), + .write_scanner_data_in_ready_f_(mem_ctrl_fiber_access_16_flat_write_scanner_data_in_ready_f_) +); + +strg_ub_vec_flat mem_ctrl_strg_ub_vec_flat ( + .chain_data_in_f_0(MEM_input_width_17_num_0), + .chain_data_in_f_1(MEM_input_width_17_num_1), + .clk(mem_ctrl_strg_ub_vec_flat_clk), + .clk_en(clk_en), + .data_in_f_0(MEM_input_width_17_num_2), + .data_in_f_1(MEM_input_width_17_num_3), + .flush(flush), + .rst_n(rst_n), + .strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_starting_addr(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_starting_addr), + .strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_strides_0(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_strides_0), + .strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_strides_1(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_strides_1), + .strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_strides_2(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_strides_2), + .strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_starting_addr(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_starting_addr), + .strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_strides_0(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_strides_0), + .strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_strides_1(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_strides_1), + .strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_strides_2(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_strides_2), + .strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_enable(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_enable), + .strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_starting_addr(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_starting_addr), + .strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_0(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_0), + .strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_1(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_1), + .strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_2(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_2), + .strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_enable(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_enable), + .strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_starting_addr(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_starting_addr), + .strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_0(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_0), + .strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_1(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_1), + .strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_2(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_2), + .strg_ub_vec_inst_agg_only_loops_in2buf_0_dimensionality(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_0_dimensionality), + .strg_ub_vec_inst_agg_only_loops_in2buf_0_ranges_0(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_0_ranges_0), + .strg_ub_vec_inst_agg_only_loops_in2buf_0_ranges_1(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_0_ranges_1), + .strg_ub_vec_inst_agg_only_loops_in2buf_0_ranges_2(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_0_ranges_2), + .strg_ub_vec_inst_agg_only_loops_in2buf_1_dimensionality(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_1_dimensionality), + .strg_ub_vec_inst_agg_only_loops_in2buf_1_ranges_0(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_1_ranges_0), + .strg_ub_vec_inst_agg_only_loops_in2buf_1_ranges_1(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_1_ranges_1), + .strg_ub_vec_inst_agg_only_loops_in2buf_1_ranges_2(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_1_ranges_2), + .strg_ub_vec_inst_agg_sram_shared_agg_read_sched_gen_0_agg_read_padding(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_sram_shared_agg_read_sched_gen_0_agg_read_padding), + .strg_ub_vec_inst_agg_sram_shared_agg_read_sched_gen_1_agg_read_padding(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_sram_shared_agg_read_sched_gen_1_agg_read_padding), + .strg_ub_vec_inst_agg_sram_shared_agg_sram_shared_addr_gen_0_starting_addr(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_sram_shared_agg_sram_shared_addr_gen_0_starting_addr), + .strg_ub_vec_inst_agg_sram_shared_agg_sram_shared_addr_gen_1_starting_addr(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_sram_shared_agg_sram_shared_addr_gen_1_starting_addr), + .strg_ub_vec_inst_agg_sram_shared_mode_0(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_sram_shared_mode_0), + .strg_ub_vec_inst_agg_sram_shared_mode_1(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_sram_shared_mode_1), + .strg_ub_vec_inst_chain_chain_en(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_chain_chain_en), + .strg_ub_vec_inst_data_from_strg_lifted(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_data_from_strg_lifted), + .strg_ub_vec_inst_sram_only_output_addr_gen_0_starting_addr(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_0_starting_addr), + .strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_0(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_0), + .strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_1(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_1), + .strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_2(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_2), + .strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_3(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_3), + .strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_4(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_4), + .strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_5(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_5), + .strg_ub_vec_inst_sram_only_output_addr_gen_1_starting_addr(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_1_starting_addr), + .strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_0(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_0), + .strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_1(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_1), + .strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_2(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_2), + .strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_3(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_3), + .strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_4(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_4), + .strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_5(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_5), + .strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_dimensionality(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_dimensionality), + .strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_0(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_0), + .strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_1(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_1), + .strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_2(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_2), + .strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_3(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_3), + .strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_4(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_4), + .strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_5(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_5), + .strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_dimensionality(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_dimensionality), + .strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_0(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_0), + .strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_1(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_1), + .strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_2(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_2), + .strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_3(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_3), + .strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_4(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_4), + .strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_5(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_5), + .strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_enable(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_enable), + .strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_delay(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_delay), + .strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_starting_addr(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_starting_addr), + .strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_0(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_0), + .strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_1(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_1), + .strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_2(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_2), + .strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_3(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_3), + .strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_4(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_4), + .strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_5(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_5), + .strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_enable(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_enable), + .strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_delay(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_delay), + .strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_starting_addr(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_starting_addr), + .strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_0(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_0), + .strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_1(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_1), + .strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_2(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_2), + .strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_3(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_3), + .strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_4(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_4), + .strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_5(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_5), + .strg_ub_vec_inst_tb_only_loops_buf2out_read_0_dimensionality(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_0_dimensionality), + .strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_0(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_0), + .strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_1(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_1), + .strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_2(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_2), + .strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_3(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_3), + .strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_4(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_4), + .strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_5(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_5), + .strg_ub_vec_inst_tb_only_loops_buf2out_read_1_dimensionality(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_1_dimensionality), + .strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_0(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_0), + .strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_1(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_1), + .strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_2(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_2), + .strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_3(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_3), + .strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_4(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_4), + .strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_5(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_5), + .strg_ub_vec_inst_tb_only_shared_tb_0(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_shared_tb_0), + .strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_starting_addr(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_starting_addr), + .strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_0(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_0), + .strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_1(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_1), + .strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_2(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_2), + .strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_3(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_3), + .strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_4(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_4), + .strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_5(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_5), + .strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_starting_addr(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_starting_addr), + .strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_0(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_0), + .strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_1(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_1), + .strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_2(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_2), + .strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_3(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_3), + .strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_4(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_4), + .strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_5(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_5), + .strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_enable(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_enable), + .strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_delay(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_delay), + .strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_starting_addr(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_starting_addr), + .strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_0(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_0), + .strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_1(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_1), + .strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_2(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_2), + .strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_3(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_3), + .strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_4(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_4), + .strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_5(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_5), + .strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_enable(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_enable), + .strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_delay(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_delay), + .strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_starting_addr(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_starting_addr), + .strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_0(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_0), + .strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_1(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_1), + .strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_2(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_2), + .strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_3(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_3), + .strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_4(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_4), + .strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_5(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_5), + .strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_starting_addr(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_starting_addr), + .strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_0(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_0), + .strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_1(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_1), + .strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_2(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_2), + .strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_3(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_3), + .strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_4(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_4), + .strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_5(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_5), + .strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_starting_addr(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_starting_addr), + .strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_0(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_0), + .strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_1(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_1), + .strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_2(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_2), + .strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_3(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_3), + .strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_4(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_4), + .strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_5(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_5), + .accessor_output_f_b_0(mem_ctrl_strg_ub_vec_flat_accessor_output_f_b_0), + .accessor_output_f_b_1(mem_ctrl_strg_ub_vec_flat_accessor_output_f_b_1), + .data_out_f_0(mem_ctrl_strg_ub_vec_flat_data_out_f_0), + .data_out_f_1(mem_ctrl_strg_ub_vec_flat_data_out_f_1), + .strg_ub_vec_inst_addr_out_lifted(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_addr_out_lifted), + .strg_ub_vec_inst_data_to_strg_lifted(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_data_to_strg_lifted), + .strg_ub_vec_inst_ren_to_strg_lifted(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_ren_to_strg_lifted), + .strg_ub_vec_inst_wen_to_strg_lifted(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_wen_to_strg_lifted) +); + +strg_ram_64_512_delay1_flat mem_ctrl_strg_ram_64_512_delay1_flat ( + .clk(mem_ctrl_strg_ram_64_512_delay1_flat_clk), + .clk_en(clk_en), + .data_in_f_(MEM_input_width_17_num_0), + .flush(flush), + .rd_addr_in_f_(MEM_input_width_17_num_1), + .ren_f_(MEM_input_width_1_num_0), + .rst_n(rst_n), + .strg_ram_64_512_delay1_inst_data_from_strg_lifted(mem_ctrl_strg_ram_64_512_delay1_flat_strg_ram_64_512_delay1_inst_data_from_strg_lifted), + .wen_f_(MEM_input_width_1_num_1), + .wr_addr_in_f_(MEM_input_width_17_num_2), + .data_out_f_(mem_ctrl_strg_ram_64_512_delay1_flat_data_out_f_), + .ready_f_(mem_ctrl_strg_ram_64_512_delay1_flat_ready_f_), + .strg_ram_64_512_delay1_inst_addr_out_lifted(mem_ctrl_strg_ram_64_512_delay1_flat_strg_ram_64_512_delay1_inst_addr_out_lifted), + .strg_ram_64_512_delay1_inst_data_to_strg_lifted(mem_ctrl_strg_ram_64_512_delay1_flat_strg_ram_64_512_delay1_inst_data_to_strg_lifted), + .strg_ram_64_512_delay1_inst_ren_to_strg_lifted(mem_ctrl_strg_ram_64_512_delay1_flat_strg_ram_64_512_delay1_inst_ren_to_strg_lifted), + .strg_ram_64_512_delay1_inst_wen_to_strg_lifted(mem_ctrl_strg_ram_64_512_delay1_flat_strg_ram_64_512_delay1_inst_wen_to_strg_lifted), + .valid_out_f_(mem_ctrl_strg_ram_64_512_delay1_flat_valid_out_f_) +); + +stencil_valid_flat mem_ctrl_stencil_valid_flat ( + .clk(mem_ctrl_stencil_valid_flat_clk), + .clk_en(clk_en), + .flush(flush), + .rst_n(rst_n), + .stencil_valid_inst_loops_stencil_valid_dimensionality(mem_ctrl_stencil_valid_flat_stencil_valid_inst_loops_stencil_valid_dimensionality), + .stencil_valid_inst_loops_stencil_valid_ranges_0(mem_ctrl_stencil_valid_flat_stencil_valid_inst_loops_stencil_valid_ranges_0), + .stencil_valid_inst_loops_stencil_valid_ranges_1(mem_ctrl_stencil_valid_flat_stencil_valid_inst_loops_stencil_valid_ranges_1), + .stencil_valid_inst_loops_stencil_valid_ranges_2(mem_ctrl_stencil_valid_flat_stencil_valid_inst_loops_stencil_valid_ranges_2), + .stencil_valid_inst_loops_stencil_valid_ranges_3(mem_ctrl_stencil_valid_flat_stencil_valid_inst_loops_stencil_valid_ranges_3), + .stencil_valid_inst_loops_stencil_valid_ranges_4(mem_ctrl_stencil_valid_flat_stencil_valid_inst_loops_stencil_valid_ranges_4), + .stencil_valid_inst_loops_stencil_valid_ranges_5(mem_ctrl_stencil_valid_flat_stencil_valid_inst_loops_stencil_valid_ranges_5), + .stencil_valid_inst_stencil_valid_sched_gen_enable(mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_enable), + .stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_starting_addr(mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_starting_addr), + .stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_0(mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_0), + .stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_1(mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_1), + .stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_2(mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_2), + .stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_3(mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_3), + .stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_4(mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_4), + .stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_5(mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_5), + .stencil_valid_f_(mem_ctrl_stencil_valid_flat_stencil_valid_f_) +); + +reg_fifo_depth_2_w_17_afd_2 input_width_17_num_0_input_fifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in(MEM_input_width_17_num_0), + .flush(flush), + .pop(input_width_17_num_0_fifo_out_ready), + .push(MEM_input_width_17_num_0_valid), + .rst_n(rst_n), + .data_out(input_width_17_num_0_fifo_out), + .empty(input_width_17_num_0_input_fifo_empty), + .full(input_width_17_num_0_input_fifo_full) +); + +reg_fifo_depth_2_w_17_afd_2 input_width_17_num_1_input_fifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in(MEM_input_width_17_num_1), + .flush(flush), + .pop(input_width_17_num_1_fifo_out_ready), + .push(MEM_input_width_17_num_1_valid), + .rst_n(rst_n), + .data_out(input_width_17_num_1_fifo_out), + .empty(input_width_17_num_1_input_fifo_empty), + .full(input_width_17_num_1_input_fifo_full) +); + +reg_fifo_depth_2_w_17_afd_2 input_width_17_num_2_input_fifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in(MEM_input_width_17_num_2), + .flush(flush), + .pop(input_width_17_num_2_fifo_out_ready), + .push(MEM_input_width_17_num_2_valid), + .rst_n(rst_n), + .data_out(input_width_17_num_2_fifo_out), + .empty(input_width_17_num_2_input_fifo_empty), + .full(input_width_17_num_2_input_fifo_full) +); + +reg_fifo_depth_2_w_17_afd_2 input_width_17_num_3_input_fifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in(MEM_input_width_17_num_3), + .flush(flush), + .pop(input_width_17_num_3_fifo_out_ready), + .push(MEM_input_width_17_num_3_valid), + .rst_n(rst_n), + .data_out(input_width_17_num_3_fifo_out), + .empty(input_width_17_num_3_input_fifo_empty), + .full(input_width_17_num_3_input_fifo_full) +); + +reg_fifo_depth_2_w_17_afd_2 output_width_17_num_0_output_fifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in(output_width_17_num_0_fifo_in), + .flush(flush), + .pop(MEM_output_width_17_num_0_ready), + .push(output_width_17_num_0_fifo_in_valid), + .rst_n(rst_n), + .data_out(output_width_17_num_0_output_fifo_data_out), + .empty(output_width_17_num_0_output_fifo_empty), + .full(output_width_17_num_0_output_fifo_full) +); + +reg_fifo_depth_2_w_17_afd_2 output_width_17_num_1_output_fifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in(output_width_17_num_1_fifo_in), + .flush(flush), + .pop(MEM_output_width_17_num_1_ready), + .push(output_width_17_num_1_fifo_in_valid), + .rst_n(rst_n), + .data_out(output_width_17_num_1_output_fifo_data_out), + .empty(output_width_17_num_1_output_fifo_empty), + .full(output_width_17_num_1_output_fifo_full) +); + +reg_fifo_depth_2_w_17_afd_2 output_width_17_num_2_output_fifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in(output_width_17_num_2_fifo_in), + .flush(flush), + .pop(MEM_output_width_17_num_2_ready), + .push(output_width_17_num_2_fifo_in_valid), + .rst_n(rst_n), + .data_out(output_width_17_num_2_output_fifo_data_out), + .empty(output_width_17_num_2_output_fifo_empty), + .full(output_width_17_num_2_output_fifo_full) +); + +sram_sp__0 memory_0 ( + .clk(gclk), + .clk_en(memory_0_clk_en), + .data_in_p0(memory_0_data_in_p0), + .flush(flush), + .read_addr_p0(memory_0_read_addr_p0), + .read_enable_p0(memory_0_read_enable_p0), + .write_addr_p0(memory_0_write_addr_p0), + .write_enable_p0(memory_0_write_enable_p0), + .data_out_p0(memory_0_data_out_p0) +); + +storage_config_seq_2_64_16 config_seq ( + .clk(gclk), + .clk_en(config_seq_clk_en), + .config_addr_in(config_addr_in), + .config_data_in(config_data_in_shrt), + .config_en(config_en), + .config_rd(config_read), + .config_wr(config_write), + .flush(flush), + .rd_data_stg(config_seq_rd_data_stg), + .rst_n(rst_n), + .addr_out(config_seq_addr_out), + .rd_data_out(config_data_out_shrt), + .ren_out(config_seq_ren_out), + .wen_out(config_seq_wen_out), + .wr_data(config_seq_wr_data) +); + +endmodule // MemCore_inner + +module MemCore_inner_W ( + input logic [31:0] CONFIG_SPACE_0, + input logic [31:0] CONFIG_SPACE_1, + input logic [31:0] CONFIG_SPACE_10, + input logic [31:0] CONFIG_SPACE_11, + input logic [31:0] CONFIG_SPACE_12, + input logic [31:0] CONFIG_SPACE_13, + input logic [31:0] CONFIG_SPACE_14, + input logic [31:0] CONFIG_SPACE_15, + input logic [31:0] CONFIG_SPACE_16, + input logic [31:0] CONFIG_SPACE_17, + input logic [31:0] CONFIG_SPACE_18, + input logic [31:0] CONFIG_SPACE_19, + input logic [31:0] CONFIG_SPACE_2, + input logic [31:0] CONFIG_SPACE_20, + input logic [31:0] CONFIG_SPACE_21, + input logic [31:0] CONFIG_SPACE_22, + input logic [31:0] CONFIG_SPACE_23, + input logic [31:0] CONFIG_SPACE_24, + input logic [31:0] CONFIG_SPACE_25, + input logic [31:0] CONFIG_SPACE_26, + input logic [31:0] CONFIG_SPACE_27, + input logic [31:0] CONFIG_SPACE_28, + input logic [31:0] CONFIG_SPACE_29, + input logic [31:0] CONFIG_SPACE_3, + input logic [31:0] CONFIG_SPACE_30, + input logic [31:0] CONFIG_SPACE_31, + input logic [31:0] CONFIG_SPACE_32, + input logic [31:0] CONFIG_SPACE_33, + input logic [31:0] CONFIG_SPACE_34, + input logic [31:0] CONFIG_SPACE_35, + input logic [31:0] CONFIG_SPACE_36, + input logic [31:0] CONFIG_SPACE_37, + input logic [31:0] CONFIG_SPACE_38, + input logic [31:0] CONFIG_SPACE_39, + input logic [31:0] CONFIG_SPACE_4, + input logic [31:0] CONFIG_SPACE_40, + input logic [31:0] CONFIG_SPACE_41, + input logic [31:0] CONFIG_SPACE_42, + input logic [31:0] CONFIG_SPACE_43, + input logic [31:0] CONFIG_SPACE_44, + input logic [18:0] CONFIG_SPACE_45, + input logic [31:0] CONFIG_SPACE_5, + input logic [31:0] CONFIG_SPACE_6, + input logic [31:0] CONFIG_SPACE_7, + input logic [31:0] CONFIG_SPACE_8, + input logic [31:0] CONFIG_SPACE_9, + input logic [0:0] [16:0] MEM_input_width_17_num_0, + input logic MEM_input_width_17_num_0_valid, + input logic [0:0] [16:0] MEM_input_width_17_num_1, + input logic MEM_input_width_17_num_1_valid, + input logic [0:0] [16:0] MEM_input_width_17_num_2, + input logic MEM_input_width_17_num_2_valid, + input logic [0:0] [16:0] MEM_input_width_17_num_3, + input logic MEM_input_width_17_num_3_valid, + input logic MEM_input_width_1_num_0, + input logic MEM_input_width_1_num_1, + input logic MEM_output_width_17_num_0_ready, + input logic MEM_output_width_17_num_1_ready, + input logic MEM_output_width_17_num_2_ready, + input logic clk, + input logic clk_en, + input logic [7:0] config_addr_in, + input logic [31:0] config_data_in, + input logic [1:0] config_en, + input logic config_read, + input logic config_write, + input logic flush, + input logic [1:0] mode, + input logic mode_excl, + input logic rst_n, + input logic tile_en, + output logic MEM_input_width_17_num_0_ready, + output logic MEM_input_width_17_num_1_ready, + output logic MEM_input_width_17_num_2_ready, + output logic MEM_input_width_17_num_3_ready, + output logic [0:0] [16:0] MEM_output_width_17_num_0, + output logic MEM_output_width_17_num_0_valid, + output logic [0:0] [16:0] MEM_output_width_17_num_1, + output logic MEM_output_width_17_num_1_valid, + output logic [0:0] [16:0] MEM_output_width_17_num_2, + output logic MEM_output_width_17_num_2_valid, + output logic MEM_output_width_1_num_0, + output logic MEM_output_width_1_num_1, + output logic MEM_output_width_1_num_2, + output logic [31:0] config_data_out_0, + output logic [31:0] config_data_out_1 +); + +logic [1:0][31:0] MemCore_inner_config_data_out; +assign config_data_out_0 = MemCore_inner_config_data_out[0]; +assign config_data_out_1 = MemCore_inner_config_data_out[1]; +MemCore_inner MemCore_inner ( + .CONFIG_SPACE_0(CONFIG_SPACE_0), + .CONFIG_SPACE_1(CONFIG_SPACE_1), + .CONFIG_SPACE_10(CONFIG_SPACE_10), + .CONFIG_SPACE_11(CONFIG_SPACE_11), + .CONFIG_SPACE_12(CONFIG_SPACE_12), + .CONFIG_SPACE_13(CONFIG_SPACE_13), + .CONFIG_SPACE_14(CONFIG_SPACE_14), + .CONFIG_SPACE_15(CONFIG_SPACE_15), + .CONFIG_SPACE_16(CONFIG_SPACE_16), + .CONFIG_SPACE_17(CONFIG_SPACE_17), + .CONFIG_SPACE_18(CONFIG_SPACE_18), + .CONFIG_SPACE_19(CONFIG_SPACE_19), + .CONFIG_SPACE_2(CONFIG_SPACE_2), + .CONFIG_SPACE_20(CONFIG_SPACE_20), + .CONFIG_SPACE_21(CONFIG_SPACE_21), + .CONFIG_SPACE_22(CONFIG_SPACE_22), + .CONFIG_SPACE_23(CONFIG_SPACE_23), + .CONFIG_SPACE_24(CONFIG_SPACE_24), + .CONFIG_SPACE_25(CONFIG_SPACE_25), + .CONFIG_SPACE_26(CONFIG_SPACE_26), + .CONFIG_SPACE_27(CONFIG_SPACE_27), + .CONFIG_SPACE_28(CONFIG_SPACE_28), + .CONFIG_SPACE_29(CONFIG_SPACE_29), + .CONFIG_SPACE_3(CONFIG_SPACE_3), + .CONFIG_SPACE_30(CONFIG_SPACE_30), + .CONFIG_SPACE_31(CONFIG_SPACE_31), + .CONFIG_SPACE_32(CONFIG_SPACE_32), + .CONFIG_SPACE_33(CONFIG_SPACE_33), + .CONFIG_SPACE_34(CONFIG_SPACE_34), + .CONFIG_SPACE_35(CONFIG_SPACE_35), + .CONFIG_SPACE_36(CONFIG_SPACE_36), + .CONFIG_SPACE_37(CONFIG_SPACE_37), + .CONFIG_SPACE_38(CONFIG_SPACE_38), + .CONFIG_SPACE_39(CONFIG_SPACE_39), + .CONFIG_SPACE_4(CONFIG_SPACE_4), + .CONFIG_SPACE_40(CONFIG_SPACE_40), + .CONFIG_SPACE_41(CONFIG_SPACE_41), + .CONFIG_SPACE_42(CONFIG_SPACE_42), + .CONFIG_SPACE_43(CONFIG_SPACE_43), + .CONFIG_SPACE_44(CONFIG_SPACE_44), + .CONFIG_SPACE_45(CONFIG_SPACE_45), + .CONFIG_SPACE_5(CONFIG_SPACE_5), + .CONFIG_SPACE_6(CONFIG_SPACE_6), + .CONFIG_SPACE_7(CONFIG_SPACE_7), + .CONFIG_SPACE_8(CONFIG_SPACE_8), + .CONFIG_SPACE_9(CONFIG_SPACE_9), + .MEM_input_width_17_num_0(MEM_input_width_17_num_0), + .MEM_input_width_17_num_0_valid(MEM_input_width_17_num_0_valid), + .MEM_input_width_17_num_1(MEM_input_width_17_num_1), + .MEM_input_width_17_num_1_valid(MEM_input_width_17_num_1_valid), + .MEM_input_width_17_num_2(MEM_input_width_17_num_2), + .MEM_input_width_17_num_2_valid(MEM_input_width_17_num_2_valid), + .MEM_input_width_17_num_3(MEM_input_width_17_num_3), + .MEM_input_width_17_num_3_valid(MEM_input_width_17_num_3_valid), + .MEM_input_width_1_num_0(MEM_input_width_1_num_0), + .MEM_input_width_1_num_1(MEM_input_width_1_num_1), + .MEM_output_width_17_num_0_ready(MEM_output_width_17_num_0_ready), + .MEM_output_width_17_num_1_ready(MEM_output_width_17_num_1_ready), + .MEM_output_width_17_num_2_ready(MEM_output_width_17_num_2_ready), + .clk(clk), + .clk_en(clk_en), + .config_addr_in(config_addr_in), + .config_data_in(config_data_in), + .config_en(config_en), + .config_read(config_read), + .config_write(config_write), + .flush(flush), + .mode(mode), + .mode_excl(mode_excl), + .rst_n(rst_n), + .tile_en(tile_en), + .MEM_input_width_17_num_0_ready(MEM_input_width_17_num_0_ready), + .MEM_input_width_17_num_1_ready(MEM_input_width_17_num_1_ready), + .MEM_input_width_17_num_2_ready(MEM_input_width_17_num_2_ready), + .MEM_input_width_17_num_3_ready(MEM_input_width_17_num_3_ready), + .MEM_output_width_17_num_0(MEM_output_width_17_num_0), + .MEM_output_width_17_num_0_valid(MEM_output_width_17_num_0_valid), + .MEM_output_width_17_num_1(MEM_output_width_17_num_1), + .MEM_output_width_17_num_1_valid(MEM_output_width_17_num_1_valid), + .MEM_output_width_17_num_2(MEM_output_width_17_num_2), + .MEM_output_width_17_num_2_valid(MEM_output_width_17_num_2_valid), + .MEM_output_width_1_num_0(MEM_output_width_1_num_0), + .MEM_output_width_1_num_1(MEM_output_width_1_num_1), + .MEM_output_width_1_num_2(MEM_output_width_1_num_2), + .config_data_out(MemCore_inner_config_data_out) +); + +endmodule // MemCore_inner_W + +module addr_gen_3_16 ( + input logic clk, + input logic clk_en, + input logic flush, + input logic [1:0] mux_sel, + input logic restart, + input logic rst_n, + input logic [15:0] starting_addr, + input logic step, + input logic [2:0] [15:0] strides, + output logic [15:0] addr_out +); + +logic [15:0] calc_addr; +logic [15:0] current_addr; +logic [15:0] strt_addr; +assign strt_addr = starting_addr; +assign addr_out = calc_addr; +assign calc_addr = current_addr; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + current_addr <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + current_addr <= strt_addr; + end + else if (step) begin + if (restart) begin + current_addr <= strt_addr; + end + else current_addr <= current_addr + strides[mux_sel]; + end + end +end +endmodule // addr_gen_3_16 + +module addr_gen_3_3 ( + input logic clk, + input logic clk_en, + input logic flush, + input logic [1:0] mux_sel, + input logic restart, + input logic rst_n, + input logic [2:0] starting_addr, + input logic step, + input logic [2:0] [2:0] strides, + output logic [2:0] addr_out +); + +logic [2:0] calc_addr; +logic [2:0] current_addr; +logic [2:0] strt_addr; +assign strt_addr = starting_addr; +assign addr_out = calc_addr; +assign calc_addr = current_addr; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + current_addr <= 3'h0; + end + else if (clk_en) begin + if (flush) begin + current_addr <= strt_addr; + end + else if (step) begin + if (restart) begin + current_addr <= strt_addr; + end + else current_addr <= current_addr + strides[mux_sel]; + end + end +end +endmodule // addr_gen_3_3 + +module addr_gen_6_16 ( + input logic clk, + input logic clk_en, + input logic flush, + input logic [2:0] mux_sel, + input logic restart, + input logic rst_n, + input logic [15:0] starting_addr, + input logic step, + input logic [5:0] [15:0] strides, + output logic [15:0] addr_out +); + +logic [15:0] calc_addr; +logic [15:0] current_addr; +logic [15:0] strt_addr; +assign strt_addr = starting_addr; +assign addr_out = calc_addr; +assign calc_addr = current_addr; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + current_addr <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + current_addr <= strt_addr; + end + else if (step) begin + if (restart) begin + current_addr <= strt_addr; + end + else current_addr <= current_addr + strides[mux_sel]; + end + end +end +endmodule // addr_gen_6_16 + +module addr_gen_6_16_delay_addr_10 ( + input logic clk, + input logic clk_en, + input logic [9:0] delay, + input logic flush, + input logic [2:0] mux_sel, + input logic restart, + input logic rst_n, + input logic [15:0] starting_addr, + input logic step, + input logic [5:0] [15:0] strides, + output logic [15:0] addr_out, + output logic [9:0] delay_out, + output logic [15:0] delayed_addr_out +); + +logic [15:0] calc_addr; +logic [15:0] current_addr; +logic [15:0] strt_addr; +assign delay_out = delay; +assign strt_addr = starting_addr; +assign addr_out = calc_addr; +assign calc_addr = current_addr; +assign delayed_addr_out = current_addr + 16'(delay); + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + current_addr <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + current_addr <= strt_addr; + end + else if (step) begin + if (restart) begin + current_addr <= strt_addr; + end + else current_addr <= current_addr + strides[mux_sel]; + end + end +end +endmodule // addr_gen_6_16_delay_addr_10 + +module addr_gen_6_4 ( + input logic clk, + input logic clk_en, + input logic flush, + input logic [2:0] mux_sel, + input logic restart, + input logic rst_n, + input logic [3:0] starting_addr, + input logic step, + input logic [5:0] [3:0] strides, + output logic [3:0] addr_out +); + +logic [3:0] calc_addr; +logic [3:0] current_addr; +logic [3:0] strt_addr; +assign strt_addr = starting_addr; +assign addr_out = calc_addr; +assign calc_addr = current_addr; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + current_addr <= 4'h0; + end + else if (clk_en) begin + if (flush) begin + current_addr <= strt_addr; + end + else if (step) begin + if (restart) begin + current_addr <= strt_addr; + end + else current_addr <= current_addr + strides[mux_sel]; + end + end +end +endmodule // addr_gen_6_4 + +module addr_gen_6_9 ( + input logic clk, + input logic clk_en, + input logic flush, + input logic [2:0] mux_sel, + input logic restart, + input logic rst_n, + input logic [8:0] starting_addr, + input logic step, + input logic [5:0] [8:0] strides, + output logic [8:0] addr_out +); + +logic [8:0] calc_addr; +logic [8:0] current_addr; +logic [8:0] strt_addr; +assign strt_addr = starting_addr; +assign addr_out = calc_addr; +assign calc_addr = current_addr; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + current_addr <= 9'h0; + end + else if (clk_en) begin + if (flush) begin + current_addr <= strt_addr; + end + else if (step) begin + if (restart) begin + current_addr <= strt_addr; + end + else current_addr <= current_addr + strides[mux_sel]; + end + end +end +endmodule // addr_gen_6_9 + +module agg_sram_shared_addr_gen ( + input logic clk, + input logic clk_en, + input logic flush, + input logic [1:0] mode, + input logic rst_n, + input logic [1:0] sram_read, + input logic [1:0] [8:0] sram_read_addr, + input logic [8:0] starting_addr, + input logic step, + output logic [8:0] addr_out +); + +logic [3:0][8:0] addr_fifo; +logic [8:0] addr_fifo_in; +logic [8:0] addr_fifo_out; +logic addr_fifo_wr_en; +logic [8:0] lin_addr_cnter; +logic [1:0] rd_ptr; +logic [1:0] wr_ptr; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + lin_addr_cnter <= 9'h0; + end + else if (clk_en) begin + if (flush) begin + lin_addr_cnter <= 9'h0; + end + else if (mode[1] == 1'h0) begin + if (step) begin + if (lin_addr_cnter == 9'h1FF) begin + lin_addr_cnter <= 9'h0; + end + else lin_addr_cnter <= lin_addr_cnter + 9'h1; + end + end + end +end +assign addr_fifo_wr_en = mode[0] ? sram_read[1]: sram_read[0]; +assign addr_fifo_in = mode[0] ? sram_read_addr[1]: sram_read_addr[0]; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + wr_ptr <= 2'h0; + rd_ptr <= 2'h0; + addr_fifo <= 36'h0; + addr_fifo_out <= 9'h0; + end + else if (clk_en) begin + if (flush) begin + wr_ptr <= 2'h0; + rd_ptr <= 2'h0; + addr_fifo <= 36'h0; + addr_fifo_out <= 9'h0; + end + else if (mode[1] == 1'h1) begin + if (addr_fifo_wr_en) begin + wr_ptr <= wr_ptr + 2'h1; + addr_fifo[wr_ptr] <= addr_fifo_in; + end + if (step) begin + rd_ptr <= rd_ptr + 2'h1; + end + addr_fifo_out <= addr_fifo[rd_ptr]; + end + end +end +assign addr_out = mode[1] ? addr_fifo_out: lin_addr_cnter + starting_addr; +endmodule // agg_sram_shared_addr_gen + +module agg_sram_shared_sched_gen ( + input logic [7:0] agg_read_padding, + input logic agg_write, + input logic [1:0] agg_write_addr_l2b, + input logic [2:0] agg_write_mux_sel, + input logic agg_write_restart, + input logic clk, + input logic clk_en, + input logic flush, + input logic [1:0] mode, + input logic rst_n, + input logic [1:0] sram_read_d, + output logic valid_output +); + +logic agg_write_4_r; +logic [7:0] pad_cnt; +logic pad_cnt_en; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + agg_write_4_r <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + agg_write_4_r <= 1'h0; + end + else if (mode[1] == 1'h0) begin + agg_write_4_r <= agg_write & (&agg_write_addr_l2b); + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + pad_cnt_en <= 1'h0; + pad_cnt <= 8'h0; + end + else if (clk_en) begin + if (flush) begin + pad_cnt_en <= 1'h0; + pad_cnt <= 8'h0; + end + else if ((mode[1] == 1'h0) & (agg_read_padding != 8'h0)) begin + if (agg_write & ((agg_write_mux_sel != 3'h0) | agg_write_restart)) begin + pad_cnt_en <= 1'h1; + end + else if (pad_cnt == agg_read_padding) begin + pad_cnt_en <= 1'h0; + end + if (pad_cnt == agg_read_padding) begin + pad_cnt <= 8'h0; + end + else if (pad_cnt_en | (agg_write & ((agg_write_mux_sel != 3'h0) | agg_write_restart))) begin + pad_cnt <= pad_cnt + 8'h1; + end + end + end +end +always_comb begin + if (mode[1] == 1'h0) begin + if (agg_read_padding != 8'h0) begin + valid_output = (agg_read_padding == pad_cnt) | agg_write_4_r; + end + else valid_output = agg_write_4_r; + end + else valid_output = mode[0] ? sram_read_d[1]: sram_read_d[0]; +end +endmodule // agg_sram_shared_sched_gen + +module arbiter_2_in_PRIO_algo ( + input logic clk, + input logic clk_en, + input logic flush, + input logic [1:0] request_in, + input logic resource_ready, + input logic rst_n, + output logic [1:0] grant_out +); + +logic [1:0] grant_line; +logic [1:0] grant_line_ready; +logic [1:0] grant_out_consolation; +logic [1:0] grant_out_priority; +logic tmp_done; +logic tmp_out_first; +always_comb begin + grant_line = request_in[1] ? 2'h2: 2'h1; +end +assign grant_line_ready[0] = grant_line[0] & resource_ready; +assign grant_out_priority[0] = grant_line_ready[0] & request_in[0]; +assign grant_line_ready[1] = grant_line[1] & resource_ready; +assign grant_out_priority[1] = grant_line_ready[1] & request_in[1]; +always_comb begin + tmp_done = 1'h0; + tmp_out_first = 1'h0; + if (~tmp_done) begin + if (request_in[0]) begin + tmp_out_first = 1'h0; + tmp_done = 1'h1; + end + end + if (~tmp_done) begin + if (request_in[1]) begin + tmp_out_first = 1'h1; + tmp_done = 1'h1; + end + end +end +assign grant_out_consolation[0] = resource_ready & request_in[0] & (tmp_out_first == 1'h0); +assign grant_out[0] = (|grant_out_priority) ? grant_out_priority[0]: grant_out_consolation[0]; +assign grant_out_consolation[1] = resource_ready & request_in[1] & (tmp_out_first == 1'h1); +assign grant_out[1] = (|grant_out_priority) ? grant_out_priority[1]: grant_out_consolation[1]; +endmodule // arbiter_2_in_PRIO_algo + +module arbiter_4_in_RR_algo ( + input logic clk, + input logic clk_en, + input logic flush, + input logic [3:0] request_in, + input logic resource_ready, + input logic rst_n, + output logic [3:0] grant_out +); + +logic [3:0] grant_line; +logic [3:0] grant_line_ready; +logic [3:0] grant_out_consolation; +logic [3:0] grant_out_priority; +logic tmp_done; +logic [1:0] tmp_out_first; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + grant_line <= 4'h1; + end + else if (clk_en) begin + if (flush) begin + grant_line <= 4'h1; + end + else grant_line <= {grant_line[2:0], grant_line[3]}; + end +end +assign grant_line_ready[0] = grant_line[0] & resource_ready; +assign grant_out_priority[0] = grant_line_ready[0] & request_in[0]; +assign grant_line_ready[1] = grant_line[1] & resource_ready; +assign grant_out_priority[1] = grant_line_ready[1] & request_in[1]; +assign grant_line_ready[2] = grant_line[2] & resource_ready; +assign grant_out_priority[2] = grant_line_ready[2] & request_in[2]; +assign grant_line_ready[3] = grant_line[3] & resource_ready; +assign grant_out_priority[3] = grant_line_ready[3] & request_in[3]; +always_comb begin + tmp_done = 1'h0; + tmp_out_first = 2'h0; + if (~tmp_done) begin + if (request_in[0]) begin + tmp_out_first = 2'h0; + tmp_done = 1'h1; + end + end + if (~tmp_done) begin + if (request_in[1]) begin + tmp_out_first = 2'h1; + tmp_done = 1'h1; + end + end + if (~tmp_done) begin + if (request_in[2]) begin + tmp_out_first = 2'h2; + tmp_done = 1'h1; + end + end + if (~tmp_done) begin + if (request_in[3]) begin + tmp_out_first = 2'h3; + tmp_done = 1'h1; + end + end +end +assign grant_out_consolation[0] = resource_ready & request_in[0] & (tmp_out_first == 2'h0); +assign grant_out[0] = (|grant_out_priority) ? grant_out_priority[0]: grant_out_consolation[0]; +assign grant_out_consolation[1] = resource_ready & request_in[1] & (tmp_out_first == 2'h1); +assign grant_out[1] = (|grant_out_priority) ? grant_out_priority[1]: grant_out_consolation[1]; +assign grant_out_consolation[2] = resource_ready & request_in[2] & (tmp_out_first == 2'h2); +assign grant_out[2] = (|grant_out_priority) ? grant_out_priority[2]: grant_out_consolation[2]; +assign grant_out_consolation[3] = resource_ready & request_in[3] & (tmp_out_first == 2'h3); +assign grant_out[3] = (|grant_out_priority) ? grant_out_priority[3]: grant_out_consolation[3]; +endmodule // arbiter_4_in_RR_algo + +module buffet_like_16 ( + input logic [1:0] [3:0] buffet_capacity_log, + input logic clk, + input logic clk_en, + input logic [3:0] [15:0] data_from_mem, + input logic flush, + input logic [0:0] [16:0] rd_addr_0, + input logic rd_addr_0_valid, + input logic [0:0] [16:0] rd_addr_1, + input logic rd_addr_1_valid, + input logic [0:0] [16:0] rd_op_0, + input logic rd_op_0_valid, + input logic [0:0] [16:0] rd_op_1, + input logic rd_op_1_valid, + input logic rd_rsp_data_0_ready, + input logic rd_rsp_data_1_ready, + input logic rst_n, + input logic tile_en, + input logic [0:0] [16:0] wr_ID, + input logic wr_ID_valid, + input logic [0:0] [16:0] wr_addr, + input logic wr_addr_valid, + input logic [0:0] [16:0] wr_data, + input logic wr_data_valid, + output logic [8:0] addr_to_mem, + output logic [3:0] [15:0] data_to_mem, + output logic rd_addr_0_ready, + output logic rd_addr_1_ready, + output logic rd_op_0_ready, + output logic rd_op_1_ready, + output logic [0:0] [16:0] rd_rsp_data_0, + output logic rd_rsp_data_0_valid, + output logic [0:0] [16:0] rd_rsp_data_1, + output logic rd_rsp_data_1_valid, + output logic ren_to_mem, + output logic wen_to_mem, + output logic wr_ID_ready, + output logic wr_addr_ready, + output logic wr_data_ready +); + +typedef enum logic[1:0] { + RD_PAUSE_0 = 2'h0, + RD_PAUSE_T_0 = 2'h1, + RD_START_0 = 2'h2 +} read_fsm_0_state; +typedef enum logic[1:0] { + RD_PAUSE_1 = 2'h0, + RD_PAUSE_T_1 = 2'h1, + RD_START_1 = 2'h2 +} read_fsm_1_state; +typedef enum logic[1:0] { + MODIFY_0 = 2'h0, + WRITING_0 = 2'h1, + WR_START_0 = 2'h2 +} write_fsm_0_state; +typedef enum logic[1:0] { + MODIFY_1 = 2'h0, + WRITING_1 = 2'h1, + WR_START_1 = 2'h2 +} write_fsm_1_state; +logic PREVIOUS_WR_OP; +logic [15:0] addr_to_mem_local; +logic any_sram_lock; +logic [3:0] base_rr; +logic [1:0][15:0] blk_base; +logic [1:0][15:0] blk_bounds; +logic [7:0] blk_count_0; +logic [7:0] blk_count_1; +logic [0:0][31:0] blk_fifo_0_data_in; +logic [0:0][31:0] blk_fifo_0_data_out; +logic blk_fifo_0_empty; +logic blk_fifo_0_full; +logic [0:0][31:0] blk_fifo_1_data_in; +logic [0:0][31:0] blk_fifo_1_data_out; +logic blk_fifo_1_empty; +logic blk_fifo_1_full; +logic [1:0] blk_full; +logic [1:0] blk_valid; +logic [1:0][15:0] buffet_base; +logic [1:0][15:0] buffet_capacity; +logic [1:0][15:0] buffet_capacity_mask; +logic [15:0] cached_read_word_addr_0; +logic [15:0] cached_read_word_addr_1; +logic [15:0] chosen_read_0; +logic [15:0] chosen_read_1; +logic clr_cached_read_0; +logic clr_cached_read_1; +logic clr_write_wide_word_0; +logic clr_write_wide_word_1; +logic [15:0] curr_base_0; +logic [15:0] curr_base_1; +logic [15:0] curr_base_pre_0; +logic [15:0] curr_base_pre_1; +logic [15:0] curr_bounds_0; +logic [15:0] curr_bounds_1; +logic [1:0][15:0] curr_capacity_pre; +logic [15:0] decode_ret_size_request_full_blk_bounds; +logic decode_sel_done_size_request_full_blk_bounds; +logic [1:0] en_curr_base; +logic [1:0] en_curr_bounds; +logic first_base_set_0_sticky; +logic first_base_set_0_was_high; +logic first_base_set_1_sticky; +logic first_base_set_1_was_high; +logic from_cached_read_0; +logic from_cached_read_1; +logic gclk; +logic joined_in_fifo; +logic [1:0] last_read_addr_0; +logic [1:0] last_read_addr_1; +logic [15:0] last_read_addr_wide_0; +logic [15:0] last_read_addr_wide_1; +logic [3:0] mem_acq; +logic [2:0] num_bits_valid_mask_0_sum; +logic [2:0] num_bits_valid_mask_1_sum; +logic [1:0] pop_blk; +logic pop_in_fifos; +logic [1:0] pop_in_full; +logic [1:0] push_blk; +logic rd_acq_0; +logic rd_acq_1; +logic rd_addr_fifo_0_empty; +logic rd_addr_fifo_0_full; +logic rd_addr_fifo_1_empty; +logic rd_addr_fifo_1_full; +logic [15:0] rd_addr_fifo_out_addr_0; +logic [15:0] rd_addr_fifo_out_addr_1; +logic rd_addr_fifo_pop_0; +logic rd_addr_fifo_pop_1; +logic rd_addr_fifo_valid_0; +logic rd_addr_fifo_valid_1; +logic rd_op_fifo_0_empty; +logic rd_op_fifo_0_full; +logic rd_op_fifo_1_empty; +logic rd_op_fifo_1_full; +logic [15:0] rd_op_fifo_out_op_0; +logic [15:0] rd_op_fifo_out_op_1; +logic rd_op_fifo_pop_0; +logic rd_op_fifo_pop_1; +logic rd_op_fifo_valid_0; +logic rd_op_fifo_valid_1; +logic rd_rsp_fifo_0_almost_full; +logic rd_rsp_fifo_0_empty; +logic rd_rsp_fifo_0_full; +logic [16:0] rd_rsp_fifo_0_in_data; +logic rd_rsp_fifo_0_push; +logic rd_rsp_fifo_1_almost_full; +logic rd_rsp_fifo_1_empty; +logic rd_rsp_fifo_1_full; +logic [16:0] rd_rsp_fifo_1_in_data; +logic rd_rsp_fifo_1_push; +logic [15:0] read_addr_delayed_0; +logic [15:0] read_addr_delayed_1; +logic read_d1; +logic read_from_sram_write_side_0; +logic read_from_sram_write_side_1; +read_fsm_0_state read_fsm_0_current_state; +read_fsm_0_state read_fsm_0_next_state; +read_fsm_1_state read_fsm_1_current_state; +read_fsm_1_state read_fsm_1_next_state; +logic read_joined_0; +logic read_joined_1; +logic read_joined_d1_0; +logic read_joined_d1_1; +logic read_pop_0; +logic read_pop_1; +logic [1:0] read_pop_full; +logic [3:0][15:0] read_wide_word_0; +logic [3:0][15:0] read_wide_word_1; +logic read_wide_word_valid_sticky_0_sticky; +logic read_wide_word_valid_sticky_0_was_high; +logic read_wide_word_valid_sticky_1_sticky; +logic read_wide_word_valid_sticky_1_was_high; +logic [1:0] ren_full; +logic ren_full_delayed_0; +logic ren_full_delayed_1; +logic rr_arbiter_resource_ready; +logic set_cached_read_0; +logic set_cached_read_1; +logic set_read_word_addr_0; +logic set_read_word_addr_1; +logic set_wide_word_addr_0; +logic set_wide_word_addr_1; +logic set_write_wide_word_0; +logic set_write_wide_word_1; +logic [1:0] size_request_full; +logic sram_lock_0; +logic sram_lock_1; +logic [15:0] tmp_addr_0; +logic [15:0] tmp_addr_1; +logic [15:0] tmp_rd_base; +logic [15:0] tmp_wr_base; +logic use_cached_read_0; +logic use_cached_read_1; +logic valid_from_mem; +logic [1:0] wen_full; +logic wr_ID_fifo_empty; +logic wr_ID_fifo_full; +logic [15:0] wr_ID_fifo_out_data; +logic wr_ID_fifo_pop; +logic wr_ID_fifo_valid; +logic wr_acq_0; +logic wr_acq_1; +logic wr_addr_fifo_empty; +logic wr_addr_fifo_full; +logic [15:0] wr_addr_fifo_out_data; +logic wr_addr_fifo_pop; +logic wr_addr_fifo_valid; +logic [0:0][16:0] wr_data_fifo_data_out; +logic wr_data_fifo_empty; +logic wr_data_fifo_full; +logic [15:0] wr_data_fifo_out_data; +logic wr_data_fifo_out_op; +logic wr_data_fifo_pop; +logic wr_data_fifo_valid; +write_fsm_0_state write_fsm_0_current_state; +write_fsm_0_state write_fsm_0_next_state; +write_fsm_1_state write_fsm_1_current_state; +write_fsm_1_state write_fsm_1_next_state; +logic write_full_word_0; +logic write_full_word_1; +logic write_to_sram_0; +logic write_to_sram_1; +logic [3:0][15:0] write_wide_word_comb_in_0; +logic [3:0][15:0] write_wide_word_comb_in_1; +logic [3:0][15:0] write_wide_word_comb_out_0; +logic [3:0][15:0] write_wide_word_comb_out_1; +logic [3:0] write_wide_word_mask_comb_0; +logic [3:0] write_wide_word_mask_comb_1; +logic [3:0] write_wide_word_mask_reg_in_0; +logic [3:0] write_wide_word_mask_reg_in_1; +logic [3:0] write_wide_word_mask_reg_out_0; +logic [3:0] write_wide_word_mask_reg_out_1; +logic [3:0] write_wide_word_mask_reg_strg_0; +logic [3:0] write_wide_word_mask_reg_strg_1; +logic [3:0][15:0] write_wide_word_modified_0; +logic [3:0][15:0] write_wide_word_modified_1; +logic [3:0][15:0] write_wide_word_reg_0; +logic [3:0][15:0] write_wide_word_reg_1; +logic [15:0] write_word_addr_reg_0; +logic [15:0] write_word_addr_reg_1; +logic write_word_addr_valid_sticky_0_sticky; +logic write_word_addr_valid_sticky_0_was_high; +logic write_word_addr_valid_sticky_1_sticky; +logic write_word_addr_valid_sticky_1_was_high; +assign gclk = clk & tile_en; +assign buffet_capacity_mask[0][0] = (buffet_capacity_log[0] > 4'h0) & (buffet_capacity_log[0] != 4'h0); +assign buffet_capacity_mask[0][1] = (buffet_capacity_log[0] > 4'h1) & (buffet_capacity_log[0] != 4'h0); +assign buffet_capacity_mask[0][2] = (buffet_capacity_log[0] > 4'h2) & (buffet_capacity_log[0] != 4'h0); +assign buffet_capacity_mask[0][3] = (buffet_capacity_log[0] > 4'h3) & (buffet_capacity_log[0] != 4'h0); +assign buffet_capacity_mask[0][4] = (buffet_capacity_log[0] > 4'h4) & (buffet_capacity_log[0] != 4'h0); +assign buffet_capacity_mask[0][5] = (buffet_capacity_log[0] > 4'h5) & (buffet_capacity_log[0] != 4'h0); +assign buffet_capacity_mask[0][6] = (buffet_capacity_log[0] > 4'h6) & (buffet_capacity_log[0] != 4'h0); +assign buffet_capacity_mask[0][7] = (buffet_capacity_log[0] > 4'h7) & (buffet_capacity_log[0] != 4'h0); +assign buffet_capacity_mask[0][8] = (buffet_capacity_log[0] > 4'h8) & (buffet_capacity_log[0] != 4'h0); +assign buffet_capacity_mask[0][9] = (buffet_capacity_log[0] > 4'h9) & (buffet_capacity_log[0] != 4'h0); +assign buffet_capacity_mask[0][10] = (buffet_capacity_log[0] > 4'hA) & (buffet_capacity_log[0] != 4'h0); +assign buffet_capacity_mask[0][11] = (buffet_capacity_log[0] > 4'hB) & (buffet_capacity_log[0] != 4'h0); +assign buffet_capacity_mask[0][12] = (buffet_capacity_log[0] > 4'hC) & (buffet_capacity_log[0] != 4'h0); +assign buffet_capacity_mask[0][13] = (buffet_capacity_log[0] > 4'hD) & (buffet_capacity_log[0] != 4'h0); +assign buffet_capacity_mask[0][14] = (buffet_capacity_log[0] > 4'hE) & (buffet_capacity_log[0] != 4'h0); +assign buffet_capacity_mask[0][15] = (buffet_capacity_log[0] > 4'hF) & (buffet_capacity_log[0] != 4'h0); +assign buffet_capacity_mask[1][0] = (buffet_capacity_log[1] > 4'h0) & (buffet_capacity_log[1] != 4'h0); +assign buffet_capacity_mask[1][1] = (buffet_capacity_log[1] > 4'h1) & (buffet_capacity_log[1] != 4'h0); +assign buffet_capacity_mask[1][2] = (buffet_capacity_log[1] > 4'h2) & (buffet_capacity_log[1] != 4'h0); +assign buffet_capacity_mask[1][3] = (buffet_capacity_log[1] > 4'h3) & (buffet_capacity_log[1] != 4'h0); +assign buffet_capacity_mask[1][4] = (buffet_capacity_log[1] > 4'h4) & (buffet_capacity_log[1] != 4'h0); +assign buffet_capacity_mask[1][5] = (buffet_capacity_log[1] > 4'h5) & (buffet_capacity_log[1] != 4'h0); +assign buffet_capacity_mask[1][6] = (buffet_capacity_log[1] > 4'h6) & (buffet_capacity_log[1] != 4'h0); +assign buffet_capacity_mask[1][7] = (buffet_capacity_log[1] > 4'h7) & (buffet_capacity_log[1] != 4'h0); +assign buffet_capacity_mask[1][8] = (buffet_capacity_log[1] > 4'h8) & (buffet_capacity_log[1] != 4'h0); +assign buffet_capacity_mask[1][9] = (buffet_capacity_log[1] > 4'h9) & (buffet_capacity_log[1] != 4'h0); +assign buffet_capacity_mask[1][10] = (buffet_capacity_log[1] > 4'hA) & (buffet_capacity_log[1] != 4'h0); +assign buffet_capacity_mask[1][11] = (buffet_capacity_log[1] > 4'hB) & (buffet_capacity_log[1] != 4'h0); +assign buffet_capacity_mask[1][12] = (buffet_capacity_log[1] > 4'hC) & (buffet_capacity_log[1] != 4'h0); +assign buffet_capacity_mask[1][13] = (buffet_capacity_log[1] > 4'hD) & (buffet_capacity_log[1] != 4'h0); +assign buffet_capacity_mask[1][14] = (buffet_capacity_log[1] > 4'hE) & (buffet_capacity_log[1] != 4'h0); +assign buffet_capacity_mask[1][15] = (buffet_capacity_log[1] > 4'hF) & (buffet_capacity_log[1] != 4'h0); +assign buffet_capacity[0] = (buffet_capacity_log[0] == 4'h0) ? 16'h0: 16'h1 << 16'(buffet_capacity_log[0] + + 4'h2); +assign buffet_capacity[1] = (buffet_capacity_log[1] == 4'h0) ? 16'h0: 16'h1 << 16'(buffet_capacity_log[1] + + 4'h2); +assign buffet_base[0] = 16'h0; +assign buffet_base[1] = 16'h100; +assign {wr_data_fifo_out_op, wr_data_fifo_out_data} = wr_data_fifo_data_out; +assign wr_data_ready = ~wr_data_fifo_full; +assign wr_data_fifo_valid = ~wr_data_fifo_empty; +assign wr_addr_ready = ~wr_addr_fifo_full; +assign wr_addr_fifo_valid = ~wr_addr_fifo_empty; +assign wr_ID_ready = ~wr_ID_fifo_full; +assign wr_ID_fifo_valid = ~wr_ID_fifo_empty; +assign rd_op_0_ready = ~rd_op_fifo_0_full; +assign rd_op_1_ready = ~rd_op_fifo_1_full; +assign rd_op_fifo_valid_0 = ~rd_op_fifo_0_empty; +assign rd_op_fifo_valid_1 = ~rd_op_fifo_1_empty; +assign rd_addr_0_ready = ~rd_addr_fifo_0_full; +assign rd_addr_1_ready = ~rd_addr_fifo_1_full; +assign rd_addr_fifo_valid_0 = ~rd_addr_fifo_0_empty; +assign rd_addr_fifo_valid_1 = ~rd_addr_fifo_1_empty; +assign read_joined_0 = rd_op_fifo_valid_0 & rd_addr_fifo_valid_0; +assign read_joined_1 = rd_op_fifo_valid_1 & rd_addr_fifo_valid_1; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + curr_bounds_0 <= 16'hFFFF; + end + else if (clk_en) begin + if (flush) begin + curr_bounds_0 <= 16'hFFFF; + end + else if (1'h0) begin + curr_bounds_0 <= 16'h0; + end + else if (en_curr_bounds[0]) begin + curr_bounds_0 <= wr_addr_fifo_out_data; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + curr_bounds_1 <= 16'hFFFF; + end + else if (clk_en) begin + if (flush) begin + curr_bounds_1 <= 16'hFFFF; + end + else if (1'h0) begin + curr_bounds_1 <= 16'h0; + end + else if (en_curr_bounds[1]) begin + curr_bounds_1 <= wr_addr_fifo_out_data; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + first_base_set_0_was_high <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + first_base_set_0_was_high <= 1'h0; + end + else if (1'h0) begin + first_base_set_0_was_high <= 1'h0; + end + else if (en_curr_base[0]) begin + first_base_set_0_was_high <= 1'h1; + end + end +end +assign first_base_set_0_sticky = first_base_set_0_was_high; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + first_base_set_1_was_high <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + first_base_set_1_was_high <= 1'h0; + end + else if (1'h0) begin + first_base_set_1_was_high <= 1'h0; + end + else if (en_curr_base[1]) begin + first_base_set_1_was_high <= 1'h1; + end + end +end +assign first_base_set_1_sticky = first_base_set_1_was_high; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + curr_base_0 <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + curr_base_0 <= 16'h0; + end + else if (1'h0) begin + curr_base_0 <= 16'h0; + end + else if (en_curr_base[0]) begin + curr_base_0 <= curr_base_pre_0; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + curr_base_1 <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + curr_base_1 <= 16'h0; + end + else if (1'h0) begin + curr_base_1 <= 16'h0; + end + else if (en_curr_base[1]) begin + curr_base_1 <= curr_base_pre_1; + end + end +end +assign curr_base_pre_0 = 1'h1 ? (curr_bounds_0 >> 16'h2) + 16'h1 + curr_base_0: 16'h0; +assign curr_base_pre_1 = 1'h1 ? (curr_bounds_1 >> 16'h2) + 16'h1 + curr_base_1: 16'h0; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + read_joined_d1_0 <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + read_joined_d1_0 <= 1'h0; + end + else if (1'h0) begin + read_joined_d1_0 <= 1'h0; + end + else if (1'h1) begin + read_joined_d1_0 <= read_joined_0 & read_pop_0; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + read_joined_d1_1 <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + read_joined_d1_1 <= 1'h0; + end + else if (1'h0) begin + read_joined_d1_1 <= 1'h0; + end + else if (1'h1) begin + read_joined_d1_1 <= read_joined_1 & read_pop_1; + end + end +end +assign rd_acq_0 = mem_acq[1] & ren_full[0]; +assign rd_acq_1 = mem_acq[3] & ren_full[1]; +assign wr_acq_0 = mem_acq[0] & write_to_sram_0; +assign wr_acq_1 = mem_acq[2] & write_to_sram_1; +assign addr_to_mem = addr_to_mem_local[8:0]; +assign tmp_addr_0 = ((16'(wr_addr_fifo_out_data[15:2]) + curr_base_0) & buffet_capacity_mask[0]) + + buffet_base[0]; +assign tmp_addr_1 = ((16'(wr_addr_fifo_out_data[15:2]) + curr_base_1) & buffet_capacity_mask[1]) + + buffet_base[1]; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + write_word_addr_reg_0 <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + write_word_addr_reg_0 <= 16'h0; + end + else if (1'h0) begin + write_word_addr_reg_0 <= 16'h0; + end + else if (set_wide_word_addr_0) begin + write_word_addr_reg_0 <= tmp_addr_0; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + write_word_addr_reg_1 <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + write_word_addr_reg_1 <= 16'h0; + end + else if (1'h0) begin + write_word_addr_reg_1 <= 16'h0; + end + else if (set_wide_word_addr_1) begin + write_word_addr_reg_1 <= tmp_addr_1; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + write_word_addr_valid_sticky_0_was_high <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + write_word_addr_valid_sticky_0_was_high <= 1'h0; + end + else if (1'h0) begin + write_word_addr_valid_sticky_0_was_high <= 1'h0; + end + else if (set_wide_word_addr_0) begin + write_word_addr_valid_sticky_0_was_high <= 1'h1; + end + end +end +assign write_word_addr_valid_sticky_0_sticky = write_word_addr_valid_sticky_0_was_high; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + write_word_addr_valid_sticky_1_was_high <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + write_word_addr_valid_sticky_1_was_high <= 1'h0; + end + else if (1'h0) begin + write_word_addr_valid_sticky_1_was_high <= 1'h0; + end + else if (set_wide_word_addr_1) begin + write_word_addr_valid_sticky_1_was_high <= 1'h1; + end + end +end +assign write_word_addr_valid_sticky_1_sticky = write_word_addr_valid_sticky_1_was_high; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + write_wide_word_mask_reg_strg_0 <= 4'h0; + end + else if (clk_en) begin + if (flush) begin + write_wide_word_mask_reg_strg_0 <= 4'h0; + end + else if (1'h0) begin + write_wide_word_mask_reg_strg_0 <= 4'h0; + end + else if (set_write_wide_word_0 | clr_write_wide_word_0) begin + write_wide_word_mask_reg_strg_0 <= write_wide_word_mask_reg_in_0; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + write_wide_word_mask_reg_strg_1 <= 4'h0; + end + else if (clk_en) begin + if (flush) begin + write_wide_word_mask_reg_strg_1 <= 4'h0; + end + else if (1'h0) begin + write_wide_word_mask_reg_strg_1 <= 4'h0; + end + else if (set_write_wide_word_1 | clr_write_wide_word_1) begin + write_wide_word_mask_reg_strg_1 <= write_wide_word_mask_reg_in_1; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + write_wide_word_reg_0 <= 64'h0; + end + else if (clk_en) begin + if (flush) begin + write_wide_word_reg_0 <= 64'h0; + end + else if (1'h0) begin + write_wide_word_reg_0 <= 64'h0; + end + else if (set_write_wide_word_0 | clr_write_wide_word_0) begin + write_wide_word_reg_0 <= write_wide_word_comb_in_0; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + write_wide_word_reg_1 <= 64'h0; + end + else if (clk_en) begin + if (flush) begin + write_wide_word_reg_1 <= 64'h0; + end + else if (1'h0) begin + write_wide_word_reg_1 <= 64'h0; + end + else if (set_write_wide_word_1 | clr_write_wide_word_1) begin + write_wide_word_reg_1 <= write_wide_word_comb_in_1; + end + end +end +assign write_wide_word_comb_out_0[0] = write_wide_word_mask_reg_out_0[0] ? write_wide_word_reg_0[0]: + wr_data_fifo_out_data; +assign write_wide_word_comb_out_0[1] = write_wide_word_mask_reg_out_0[1] ? write_wide_word_reg_0[1]: + wr_data_fifo_out_data; +assign write_wide_word_comb_out_0[2] = write_wide_word_mask_reg_out_0[2] ? write_wide_word_reg_0[2]: + wr_data_fifo_out_data; +assign write_wide_word_comb_out_0[3] = write_wide_word_mask_reg_out_0[3] ? write_wide_word_reg_0[3]: + wr_data_fifo_out_data; +assign write_wide_word_comb_out_1[0] = write_wide_word_mask_reg_out_1[0] ? write_wide_word_reg_1[0]: + wr_data_fifo_out_data; +assign write_wide_word_comb_out_1[1] = write_wide_word_mask_reg_out_1[1] ? write_wide_word_reg_1[1]: + wr_data_fifo_out_data; +assign write_wide_word_comb_out_1[2] = write_wide_word_mask_reg_out_1[2] ? write_wide_word_reg_1[2]: + wr_data_fifo_out_data; +assign write_wide_word_comb_out_1[3] = write_wide_word_mask_reg_out_1[3] ? write_wide_word_reg_1[3]: + wr_data_fifo_out_data; +assign write_wide_word_comb_in_0[0] = (write_wide_word_mask_reg_out_0[0] & (~clr_write_wide_word_0)) ? + write_wide_word_reg_0[0]: wr_data_fifo_out_data; +assign write_wide_word_comb_in_0[1] = (write_wide_word_mask_reg_out_0[1] & (~clr_write_wide_word_0)) ? + write_wide_word_reg_0[1]: wr_data_fifo_out_data; +assign write_wide_word_comb_in_0[2] = (write_wide_word_mask_reg_out_0[2] & (~clr_write_wide_word_0)) ? + write_wide_word_reg_0[2]: wr_data_fifo_out_data; +assign write_wide_word_comb_in_0[3] = (write_wide_word_mask_reg_out_0[3] & (~clr_write_wide_word_0)) ? + write_wide_word_reg_0[3]: wr_data_fifo_out_data; +assign write_wide_word_comb_in_1[0] = (write_wide_word_mask_reg_out_1[0] & (~clr_write_wide_word_1)) ? + write_wide_word_reg_1[0]: wr_data_fifo_out_data; +assign write_wide_word_comb_in_1[1] = (write_wide_word_mask_reg_out_1[1] & (~clr_write_wide_word_1)) ? + write_wide_word_reg_1[1]: wr_data_fifo_out_data; +assign write_wide_word_comb_in_1[2] = (write_wide_word_mask_reg_out_1[2] & (~clr_write_wide_word_1)) ? + write_wide_word_reg_1[2]: wr_data_fifo_out_data; +assign write_wide_word_comb_in_1[3] = (write_wide_word_mask_reg_out_1[3] & (~clr_write_wide_word_1)) ? + write_wide_word_reg_1[3]: wr_data_fifo_out_data; +assign write_wide_word_modified_0[0] = write_wide_word_mask_reg_out_0[0] ? write_wide_word_reg_0[0]: data_from_mem[0]; +assign write_wide_word_modified_0[1] = write_wide_word_mask_reg_out_0[1] ? write_wide_word_reg_0[1]: data_from_mem[1]; +assign write_wide_word_modified_0[2] = write_wide_word_mask_reg_out_0[2] ? write_wide_word_reg_0[2]: data_from_mem[2]; +assign write_wide_word_modified_0[3] = write_wide_word_mask_reg_out_0[3] ? write_wide_word_reg_0[3]: data_from_mem[3]; +assign write_wide_word_modified_1[0] = write_wide_word_mask_reg_out_1[0] ? write_wide_word_reg_1[0]: data_from_mem[0]; +assign write_wide_word_modified_1[1] = write_wide_word_mask_reg_out_1[1] ? write_wide_word_reg_1[1]: data_from_mem[1]; +assign write_wide_word_modified_1[2] = write_wide_word_mask_reg_out_1[2] ? write_wide_word_reg_1[2]: data_from_mem[2]; +assign write_wide_word_modified_1[3] = write_wide_word_mask_reg_out_1[3] ? write_wide_word_reg_1[3]: data_from_mem[3]; +assign write_wide_word_mask_reg_out_0 = write_wide_word_mask_reg_strg_0; +assign write_wide_word_mask_reg_out_1 = write_wide_word_mask_reg_strg_1; +assign write_wide_word_mask_comb_0 = write_wide_word_mask_reg_out_0 | 4'(2'(((tmp_addr_0 == write_word_addr_reg_0) & + joined_in_fifo & (1'h1 == wr_data_fifo_out_op) & (16'h0 == wr_ID_fifo_out_data)) + ? 1'h1: 1'h0) << wr_addr_fifo_out_data[1:0]); +assign write_wide_word_mask_comb_1 = write_wide_word_mask_reg_out_1 | 4'(2'(((tmp_addr_1 == write_word_addr_reg_1) & + joined_in_fifo & (1'h1 == wr_data_fifo_out_op) & (16'h1 == wr_ID_fifo_out_data)) + ? 1'h1: 1'h0) << wr_addr_fifo_out_data[1:0]); +assign write_wide_word_mask_reg_in_0 = (clr_write_wide_word_0 ? 4'h0: write_wide_word_mask_reg_out_0) | + (((((clr_write_wide_word_0 & (tmp_addr_0 != write_word_addr_reg_0)) | + ((tmp_addr_0 == write_word_addr_reg_0) & ((~write_full_word_0) | + (write_full_word_0 & (~mem_acq[0]))))) & (1'h1 == wr_data_fifo_out_op) & (16'h0 + == wr_ID_fifo_out_data)) ? {3'h0, joined_in_fifo}: 4'h0) << + 4'(wr_addr_fifo_out_data[1:0])); +assign write_wide_word_mask_reg_in_1 = (clr_write_wide_word_1 ? 4'h0: write_wide_word_mask_reg_out_1) | + (((((clr_write_wide_word_1 & (tmp_addr_1 != write_word_addr_reg_1)) | + ((tmp_addr_1 == write_word_addr_reg_1) & ((~write_full_word_1) | + (write_full_word_1 & (~mem_acq[2]))))) & (1'h1 == wr_data_fifo_out_op) & (16'h1 + == wr_ID_fifo_out_data)) ? {3'h0, joined_in_fifo}: 4'h0) << + 4'(wr_addr_fifo_out_data[1:0])); +always_comb begin + num_bits_valid_mask_0_sum = 3'h0; + num_bits_valid_mask_0_sum = num_bits_valid_mask_0_sum + 3'(write_wide_word_mask_comb_0[0]); + num_bits_valid_mask_0_sum = num_bits_valid_mask_0_sum + 3'(write_wide_word_mask_comb_0[1]); + num_bits_valid_mask_0_sum = num_bits_valid_mask_0_sum + 3'(write_wide_word_mask_comb_0[2]); + num_bits_valid_mask_0_sum = num_bits_valid_mask_0_sum + 3'(write_wide_word_mask_comb_0[3]); +end +always_comb begin + num_bits_valid_mask_1_sum = 3'h0; + num_bits_valid_mask_1_sum = num_bits_valid_mask_1_sum + 3'(write_wide_word_mask_comb_1[0]); + num_bits_valid_mask_1_sum = num_bits_valid_mask_1_sum + 3'(write_wide_word_mask_comb_1[1]); + num_bits_valid_mask_1_sum = num_bits_valid_mask_1_sum + 3'(write_wide_word_mask_comb_1[2]); + num_bits_valid_mask_1_sum = num_bits_valid_mask_1_sum + 3'(write_wide_word_mask_comb_1[3]); +end +assign write_full_word_0 = 3'h4 == num_bits_valid_mask_0_sum; +assign write_full_word_1 = 3'h4 == num_bits_valid_mask_1_sum; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + read_wide_word_0 <= 64'h0; + end + else if (clk_en) begin + if (flush) begin + read_wide_word_0 <= 64'h0; + end + else if (1'h0) begin + read_wide_word_0 <= 64'h0; + end + else if (set_cached_read_0) begin + read_wide_word_0 <= data_from_mem; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + read_wide_word_1 <= 64'h0; + end + else if (clk_en) begin + if (flush) begin + read_wide_word_1 <= 64'h0; + end + else if (1'h0) begin + read_wide_word_1 <= 64'h0; + end + else if (set_cached_read_1) begin + read_wide_word_1 <= data_from_mem; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + read_wide_word_valid_sticky_0_was_high <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + read_wide_word_valid_sticky_0_was_high <= 1'h0; + end + else if (clr_cached_read_0) begin + read_wide_word_valid_sticky_0_was_high <= 1'h0; + end + else if (set_cached_read_0) begin + read_wide_word_valid_sticky_0_was_high <= 1'h1; + end + end +end +assign read_wide_word_valid_sticky_0_sticky = set_cached_read_0 | read_wide_word_valid_sticky_0_was_high; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + read_wide_word_valid_sticky_1_was_high <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + read_wide_word_valid_sticky_1_was_high <= 1'h0; + end + else if (clr_cached_read_1) begin + read_wide_word_valid_sticky_1_was_high <= 1'h0; + end + else if (set_cached_read_1) begin + read_wide_word_valid_sticky_1_was_high <= 1'h1; + end + end +end +assign read_wide_word_valid_sticky_1_sticky = set_cached_read_1 | read_wide_word_valid_sticky_1_was_high; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + last_read_addr_0 <= 2'h0; + end + else if (clk_en) begin + if (flush) begin + last_read_addr_0 <= 2'h0; + end + else if (1'h0) begin + last_read_addr_0 <= 2'h0; + end + else if (rd_acq_0) begin + last_read_addr_0 <= rd_addr_fifo_out_addr_0[1:0]; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + last_read_addr_1 <= 2'h0; + end + else if (clk_en) begin + if (flush) begin + last_read_addr_1 <= 2'h0; + end + else if (1'h0) begin + last_read_addr_1 <= 2'h0; + end + else if (rd_acq_1) begin + last_read_addr_1 <= rd_addr_fifo_out_addr_1[1:0]; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + last_read_addr_wide_0 <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + last_read_addr_wide_0 <= 16'h0; + end + else if (1'h0) begin + last_read_addr_wide_0 <= 16'h0; + end + else if (rd_acq_0) begin + last_read_addr_wide_0 <= addr_to_mem_local; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + last_read_addr_wide_1 <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + last_read_addr_wide_1 <= 16'h0; + end + else if (1'h0) begin + last_read_addr_wide_1 <= 16'h0; + end + else if (rd_acq_1) begin + last_read_addr_wide_1 <= addr_to_mem_local; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + read_addr_delayed_0 <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + read_addr_delayed_0 <= 16'h0; + end + else if (1'h0) begin + read_addr_delayed_0 <= 16'h0; + end + else if (rd_addr_fifo_pop_0 & rd_addr_fifo_valid_0) begin + read_addr_delayed_0 <= rd_addr_fifo_out_addr_0; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + read_addr_delayed_1 <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + read_addr_delayed_1 <= 16'h0; + end + else if (1'h0) begin + read_addr_delayed_1 <= 16'h0; + end + else if (rd_addr_fifo_pop_1 & rd_addr_fifo_valid_1) begin + read_addr_delayed_1 <= rd_addr_fifo_out_addr_1; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + cached_read_word_addr_0 <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + cached_read_word_addr_0 <= 16'h0; + end + else if (1'h0) begin + cached_read_word_addr_0 <= 16'h0; + end + else if (set_read_word_addr_0) begin + cached_read_word_addr_0 <= addr_to_mem_local; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + cached_read_word_addr_1 <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + cached_read_word_addr_1 <= 16'h0; + end + else if (1'h0) begin + cached_read_word_addr_1 <= 16'h0; + end + else if (set_read_word_addr_1) begin + cached_read_word_addr_1 <= addr_to_mem_local; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + ren_full_delayed_0 <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + ren_full_delayed_0 <= 1'h0; + end + else if (1'h0) begin + ren_full_delayed_0 <= 1'h0; + end + else if (1'h1) begin + ren_full_delayed_0 <= ren_full[0] & rd_acq_0; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + ren_full_delayed_1 <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + ren_full_delayed_1 <= 1'h0; + end + else if (1'h0) begin + ren_full_delayed_1 <= 1'h0; + end + else if (1'h1) begin + ren_full_delayed_1 <= ren_full[1] & rd_acq_1; + end + end +end +assign use_cached_read_0 = read_wide_word_valid_sticky_0_sticky & ((((16'(rd_addr_fifo_out_addr_0[15:2]) + + blk_base[0]) & buffet_capacity_mask[0]) + buffet_base[0]) == + cached_read_word_addr_0) & (16'h1 == rd_op_fifo_out_op_0) & read_joined_0; +assign use_cached_read_1 = read_wide_word_valid_sticky_1_sticky & ((((16'(rd_addr_fifo_out_addr_1[15:2]) + + blk_base[1]) & buffet_capacity_mask[1]) + buffet_base[1]) == + cached_read_word_addr_1) & (16'h1 == rd_op_fifo_out_op_1) & read_joined_1; +assign from_cached_read_0 = read_wide_word_valid_sticky_0_sticky & ((((16'(read_addr_delayed_0[15:2]) + + blk_base[0]) & buffet_capacity_mask[0]) + buffet_base[0]) == + cached_read_word_addr_0) & read_joined_d1_0; +assign from_cached_read_1 = read_wide_word_valid_sticky_1_sticky & ((((16'(read_addr_delayed_1[15:2]) + + blk_base[1]) & buffet_capacity_mask[1]) + buffet_base[1]) == + cached_read_word_addr_1) & read_joined_d1_1; +assign chosen_read_0 = (~ren_full_delayed_0) ? read_wide_word_0[read_addr_delayed_0[1:0]]: + data_from_mem[last_read_addr_0[1:0]]; +assign chosen_read_1 = (~ren_full_delayed_1) ? read_wide_word_1[read_addr_delayed_1[1:0]]: + data_from_mem[last_read_addr_1[1:0]]; +assign any_sram_lock = |{sram_lock_0, sram_lock_1}; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + read_d1 <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + read_d1 <= 1'h0; + end + else if (1'h0) begin + read_d1 <= 1'h0; + end + else if (1'h1) begin + read_d1 <= |{mem_acq[1], mem_acq[3]}; + end + end +end +assign valid_from_mem = read_d1; +assign rd_rsp_data_0_valid = ~rd_rsp_fifo_0_empty; +assign rd_rsp_data_1_valid = ~rd_rsp_fifo_1_empty; +always_comb begin + decode_sel_done_size_request_full_blk_bounds = 1'h0; + decode_ret_size_request_full_blk_bounds = 16'h0; + if ((~decode_sel_done_size_request_full_blk_bounds) & size_request_full[0]) begin + decode_ret_size_request_full_blk_bounds = blk_bounds[0]; + decode_sel_done_size_request_full_blk_bounds = 1'h1; + end + if ((~decode_sel_done_size_request_full_blk_bounds) & size_request_full[1]) begin + decode_ret_size_request_full_blk_bounds = blk_bounds[1]; + decode_sel_done_size_request_full_blk_bounds = 1'h1; + end +end +assign rd_rsp_fifo_0_in_data[15:0] = (from_cached_read_0 & read_wide_word_valid_sticky_0_sticky) ? chosen_read_0: + decode_ret_size_request_full_blk_bounds + 16'h1; +assign rd_rsp_fifo_1_in_data[15:0] = (from_cached_read_1 & read_wide_word_valid_sticky_1_sticky) ? chosen_read_1: + decode_ret_size_request_full_blk_bounds + 16'h1; +assign rd_rsp_fifo_0_in_data[16] = from_cached_read_0 ? 1'h0: 1'h1; +assign rd_rsp_fifo_1_in_data[16] = from_cached_read_1 ? 1'h0: 1'h1; +assign rd_rsp_fifo_0_push = from_cached_read_0 | size_request_full[0]; +assign rd_rsp_fifo_1_push = from_cached_read_1 | size_request_full[1]; +assign joined_in_fifo = wr_data_fifo_valid & wr_addr_fifo_valid & wr_ID_fifo_valid; +assign {wr_addr_fifo_pop, wr_data_fifo_pop, wr_ID_fifo_pop} = {pop_in_fifos, pop_in_fifos, pop_in_fifos}; +assign pop_in_fifos = |pop_in_full; +assign {rd_op_fifo_pop_0, rd_addr_fifo_pop_0} = {read_pop_0, read_pop_0}; +assign {rd_op_fifo_pop_1, rd_addr_fifo_pop_1} = {read_pop_1, read_pop_1}; +assign read_pop_0 = read_pop_full[0]; +assign read_pop_1 = read_pop_full[1]; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + blk_count_0 <= 8'h0; + end + else if (clk_en) begin + if (flush) begin + blk_count_0 <= 8'h0; + end + else if (push_blk[0]) begin + blk_count_0 <= blk_count_0 + 8'h1; + end + else if (pop_blk[0]) begin + blk_count_0 <= blk_count_0 - 8'h1; + end + else blk_count_0 <= blk_count_0; + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + blk_count_1 <= 8'h0; + end + else if (clk_en) begin + if (flush) begin + blk_count_1 <= 8'h0; + end + else if (push_blk[1]) begin + blk_count_1 <= blk_count_1 + 8'h1; + end + else if (pop_blk[1]) begin + blk_count_1 <= blk_count_1 - 8'h1; + end + else blk_count_1 <= blk_count_1; + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + curr_capacity_pre[0] <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + curr_capacity_pre[0] <= 16'h0; + end + else if (push_blk[0] || pop_blk[0]) begin + curr_capacity_pre[0] <= (curr_capacity_pre[0] + (push_blk[0] ? blk_bounds[0]: 16'h0)) - (pop_blk[0] ? + blk_bounds[0]: 16'h0); + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + curr_capacity_pre[1] <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + curr_capacity_pre[1] <= 16'h0; + end + else if (push_blk[1] || pop_blk[1]) begin + curr_capacity_pre[1] <= (curr_capacity_pre[1] + (push_blk[1] ? blk_bounds[1]: 16'h0)) - (pop_blk[1] ? + blk_bounds[1]: 16'h0); + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + PREVIOUS_WR_OP <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + PREVIOUS_WR_OP <= 1'h0; + end + else if (1'h0) begin + PREVIOUS_WR_OP <= 1'h0; + end + else if (1'h1) begin + PREVIOUS_WR_OP <= wr_data_fifo_out_op; + end + end +end +assign blk_fifo_0_data_in = {curr_base_0, curr_bounds_0}; +assign {blk_base[0], blk_bounds[0]} = blk_fifo_0_data_out; +assign blk_full[0] = blk_fifo_0_full; +assign blk_valid[0] = ~blk_fifo_0_empty; +assign blk_fifo_1_data_in = {curr_base_1, curr_bounds_1}; +assign {blk_base[1], blk_bounds[1]} = blk_fifo_1_data_out; +assign blk_full[1] = blk_fifo_1_full; +assign blk_valid[1] = ~blk_fifo_1_empty; + +always_ff @(posedge clk, negedge rst_n) begin + if (!rst_n) begin + read_fsm_0_current_state <= RD_START_0; + end + else if (clk_en) begin + if (flush) begin + read_fsm_0_current_state <= RD_START_0; + end + else read_fsm_0_current_state <= read_fsm_0_next_state; + end +end +always_comb begin + read_fsm_0_next_state = read_fsm_0_current_state; + unique case (read_fsm_0_current_state) + RD_PAUSE_0: begin + if (push_blk[0]) begin + read_fsm_0_next_state = RD_PAUSE_T_0; + end + else read_fsm_0_next_state = RD_PAUSE_0; + end + RD_PAUSE_T_0: read_fsm_0_next_state = RD_START_0; + RD_START_0: begin + if ((blk_count_0 == 8'h0) & (rd_op_fifo_out_op_0 == 16'h0) & read_joined_0 & 1'h1) begin + read_fsm_0_next_state = RD_PAUSE_0; + end + else read_fsm_0_next_state = RD_START_0; + end + default: read_fsm_0_next_state = read_fsm_0_current_state; + endcase +end +always_comb begin + unique case (read_fsm_0_current_state) + RD_PAUSE_0: begin :read_fsm_0_RD_PAUSE_0_Output + pop_blk[0] = 1'h0; + ren_full[0] = 1'h0; + read_pop_full[0] = 1'h0; + size_request_full[0] = 1'h0; + set_cached_read_0 = 1'h0; + clr_cached_read_0 = 1'h0; + set_read_word_addr_0 = 1'h0; + end :read_fsm_0_RD_PAUSE_0_Output + RD_PAUSE_T_0: begin :read_fsm_0_RD_PAUSE_T_0_Output + pop_blk[0] = 1'h1; + ren_full[0] = 1'h0; + read_pop_full[0] = 1'h0; + size_request_full[0] = 1'h0; + set_cached_read_0 = 1'h0; + clr_cached_read_0 = 1'h0; + set_read_word_addr_0 = 1'h0; + end :read_fsm_0_RD_PAUSE_T_0_Output + RD_START_0: begin :read_fsm_0_RD_START_0_Output + pop_blk[0] = (rd_op_fifo_out_op_0 == 16'h0) & read_joined_0 & 1'h1 & (blk_count_0 > 8'h0); + ren_full[0] = (rd_op_fifo_out_op_0 == 16'h1) & (~use_cached_read_0) & read_joined_0 & + (~rd_rsp_fifo_0_almost_full) & blk_valid[0] & + (((16'(rd_addr_fifo_out_addr_0[15:2]) + blk_base[0] + buffet_base[0]) != + cached_read_word_addr_0) | (~read_wide_word_valid_sticky_0_sticky)) & 1'h1; + read_pop_full[0] = ((rd_op_fifo_out_op_0 == 16'h2) ? (~ren_full_delayed_0) & blk_valid[0]: + (rd_op_fifo_out_op_0 == 16'h1) ? (mem_acq[1] | use_cached_read_0) & + (~rd_rsp_fifo_0_full): 1'h1) & read_joined_0 & 1'h1; + size_request_full[0] = blk_valid[0] & (rd_op_fifo_out_op_0 == 16'h2) & read_joined_0 & 1'h1; + set_cached_read_0 = ren_full_delayed_0 & 1'h1; + clr_cached_read_0 = (rd_op_fifo_out_op_0 == 16'h0) & read_joined_0 & 1'h1; + set_read_word_addr_0 = ren_full[0] & mem_acq[1] & (addr_to_mem_local != cached_read_word_addr_0) & 1'h1; + end :read_fsm_0_RD_START_0_Output + default: begin :read_fsm_0_default_Output + pop_blk[0] = (rd_op_fifo_out_op_0 == 16'h0) & read_joined_0 & 1'h1 & (blk_count_0 > 8'h0); + ren_full[0] = (rd_op_fifo_out_op_0 == 16'h1) & (~use_cached_read_0) & read_joined_0 & + (~rd_rsp_fifo_0_almost_full) & blk_valid[0] & + (((16'(rd_addr_fifo_out_addr_0[15:2]) + blk_base[0] + buffet_base[0]) != + cached_read_word_addr_0) | (~read_wide_word_valid_sticky_0_sticky)) & 1'h1; + read_pop_full[0] = ((rd_op_fifo_out_op_0 == 16'h2) ? (~ren_full_delayed_0) & blk_valid[0]: + (rd_op_fifo_out_op_0 == 16'h1) ? (mem_acq[1] | use_cached_read_0) & + (~rd_rsp_fifo_0_full): 1'h1) & read_joined_0 & 1'h1; + size_request_full[0] = blk_valid[0] & (rd_op_fifo_out_op_0 == 16'h2) & read_joined_0 & 1'h1; + set_cached_read_0 = ren_full_delayed_0 & 1'h1; + clr_cached_read_0 = (rd_op_fifo_out_op_0 == 16'h0) & read_joined_0 & 1'h1; + set_read_word_addr_0 = ren_full[0] & mem_acq[1] & (addr_to_mem_local != cached_read_word_addr_0) & 1'h1; + end :read_fsm_0_default_Output + endcase +end + +always_ff @(posedge clk, negedge rst_n) begin + if (!rst_n) begin + read_fsm_1_current_state <= RD_START_1; + end + else if (clk_en) begin + if (flush) begin + read_fsm_1_current_state <= RD_START_1; + end + else read_fsm_1_current_state <= read_fsm_1_next_state; + end +end +always_comb begin + read_fsm_1_next_state = read_fsm_1_current_state; + unique case (read_fsm_1_current_state) + RD_PAUSE_1: begin + if (push_blk[1]) begin + read_fsm_1_next_state = RD_PAUSE_T_1; + end + else read_fsm_1_next_state = RD_PAUSE_1; + end + RD_PAUSE_T_1: read_fsm_1_next_state = RD_START_1; + RD_START_1: begin + if ((blk_count_1 == 8'h0) & (rd_op_fifo_out_op_1 == 16'h0) & read_joined_1 & 1'h1) begin + read_fsm_1_next_state = RD_PAUSE_1; + end + else read_fsm_1_next_state = RD_START_1; + end + default: read_fsm_1_next_state = read_fsm_1_current_state; + endcase +end +always_comb begin + unique case (read_fsm_1_current_state) + RD_PAUSE_1: begin :read_fsm_1_RD_PAUSE_1_Output + pop_blk[1] = 1'h0; + ren_full[1] = 1'h0; + read_pop_full[1] = 1'h0; + size_request_full[1] = 1'h0; + set_cached_read_1 = 1'h0; + clr_cached_read_1 = 1'h0; + set_read_word_addr_1 = 1'h0; + end :read_fsm_1_RD_PAUSE_1_Output + RD_PAUSE_T_1: begin :read_fsm_1_RD_PAUSE_T_1_Output + pop_blk[1] = 1'h1; + ren_full[1] = 1'h0; + read_pop_full[1] = 1'h0; + size_request_full[1] = 1'h0; + set_cached_read_1 = 1'h0; + clr_cached_read_1 = 1'h0; + set_read_word_addr_1 = 1'h0; + end :read_fsm_1_RD_PAUSE_T_1_Output + RD_START_1: begin :read_fsm_1_RD_START_1_Output + pop_blk[1] = (rd_op_fifo_out_op_1 == 16'h0) & read_joined_1 & 1'h1 & (blk_count_1 > 8'h0); + ren_full[1] = (rd_op_fifo_out_op_1 == 16'h1) & (~use_cached_read_1) & read_joined_1 & + (~rd_rsp_fifo_1_almost_full) & blk_valid[1] & + (((16'(rd_addr_fifo_out_addr_1[15:2]) + blk_base[1] + buffet_base[1]) != + cached_read_word_addr_1) | (~read_wide_word_valid_sticky_1_sticky)) & 1'h1; + read_pop_full[1] = ((rd_op_fifo_out_op_1 == 16'h2) ? (~ren_full_delayed_1) & blk_valid[1]: + (rd_op_fifo_out_op_1 == 16'h1) ? (mem_acq[3] | use_cached_read_1) & + (~rd_rsp_fifo_1_full): 1'h1) & read_joined_1 & 1'h1; + size_request_full[1] = blk_valid[1] & (rd_op_fifo_out_op_1 == 16'h2) & read_joined_1 & 1'h1; + set_cached_read_1 = ren_full_delayed_1 & 1'h1; + clr_cached_read_1 = (rd_op_fifo_out_op_1 == 16'h0) & read_joined_1 & 1'h1; + set_read_word_addr_1 = ren_full[1] & mem_acq[3] & (addr_to_mem_local != cached_read_word_addr_1) & 1'h1; + end :read_fsm_1_RD_START_1_Output + default: begin :read_fsm_1_default_Output + pop_blk[1] = (rd_op_fifo_out_op_1 == 16'h0) & read_joined_1 & 1'h1 & (blk_count_1 > 8'h0); + ren_full[1] = (rd_op_fifo_out_op_1 == 16'h1) & (~use_cached_read_1) & read_joined_1 & + (~rd_rsp_fifo_1_almost_full) & blk_valid[1] & + (((16'(rd_addr_fifo_out_addr_1[15:2]) + blk_base[1] + buffet_base[1]) != + cached_read_word_addr_1) | (~read_wide_word_valid_sticky_1_sticky)) & 1'h1; + read_pop_full[1] = ((rd_op_fifo_out_op_1 == 16'h2) ? (~ren_full_delayed_1) & blk_valid[1]: + (rd_op_fifo_out_op_1 == 16'h1) ? (mem_acq[3] | use_cached_read_1) & + (~rd_rsp_fifo_1_full): 1'h1) & read_joined_1 & 1'h1; + size_request_full[1] = blk_valid[1] & (rd_op_fifo_out_op_1 == 16'h2) & read_joined_1 & 1'h1; + set_cached_read_1 = ren_full_delayed_1 & 1'h1; + clr_cached_read_1 = (rd_op_fifo_out_op_1 == 16'h0) & read_joined_1 & 1'h1; + set_read_word_addr_1 = ren_full[1] & mem_acq[3] & (addr_to_mem_local != cached_read_word_addr_1) & 1'h1; + end :read_fsm_1_default_Output + endcase +end + +always_ff @(posedge clk, negedge rst_n) begin + if (!rst_n) begin + write_fsm_0_current_state <= WR_START_0; + end + else if (clk_en) begin + if (flush) begin + write_fsm_0_current_state <= WR_START_0; + end + else write_fsm_0_current_state <= write_fsm_0_next_state; + end +end +always_comb begin + write_fsm_0_next_state = write_fsm_0_current_state; + unique case (write_fsm_0_current_state) + MODIFY_0: begin + if (1'h1 == PREVIOUS_WR_OP) begin + write_fsm_0_next_state = WRITING_0; + end + else if ((1'h0 == PREVIOUS_WR_OP) & (~blk_full[0])) begin + write_fsm_0_next_state = WR_START_0; + end + else write_fsm_0_next_state = MODIFY_0; + end + WRITING_0: begin + if (joined_in_fifo & (wr_data_fifo_out_op == 1'h0) & (~blk_full[0]) & ((write_full_word_0 & mem_acq[0]) | (num_bits_valid_mask_0_sum == 3'h0)) & (16'h0 == wr_ID_fifo_out_data)) begin + write_fsm_0_next_state = WR_START_0; + end + else if (joined_in_fifo & (16'h0 == wr_ID_fifo_out_data) & mem_acq[0] & ((1'h0 == wr_data_fifo_out_op) | ((tmp_addr_0 != write_word_addr_reg_0) & write_word_addr_valid_sticky_0_sticky & (1'h1 == wr_data_fifo_out_op))) & (num_bits_valid_mask_0_sum > 3'h0) & (~write_full_word_0)) begin + write_fsm_0_next_state = MODIFY_0; + end + else write_fsm_0_next_state = WRITING_0; + end + WR_START_0: begin + if (joined_in_fifo & (wr_data_fifo_out_op == 1'h0) & (16'h0 == wr_ID_fifo_out_data) & tile_en) begin + write_fsm_0_next_state = WRITING_0; + end + else write_fsm_0_next_state = WR_START_0; + end + default: write_fsm_0_next_state = write_fsm_0_current_state; + endcase +end +always_comb begin + unique case (write_fsm_0_current_state) + MODIFY_0: begin :write_fsm_0_MODIFY_0_Output + push_blk[0] = (1'h0 == PREVIOUS_WR_OP) & (~blk_full[0]); + en_curr_base[0] = (1'h0 == PREVIOUS_WR_OP) & (~blk_full[0]); + en_curr_bounds[0] = 1'h0; + wen_full[0] = ~blk_full[0]; + pop_in_full[0] = ~blk_full[0]; + set_write_wide_word_0 = 1'h0; + clr_write_wide_word_0 = ~blk_full[0]; + write_to_sram_0 = ~blk_full[0]; + read_from_sram_write_side_0 = 1'h0; + set_wide_word_addr_0 = 1'h0; + sram_lock_0 = ~blk_full[0]; + end :write_fsm_0_MODIFY_0_Output + WRITING_0: begin :write_fsm_0_WRITING_0_Output + push_blk[0] = joined_in_fifo & (wr_data_fifo_out_op == 1'h0) & (~blk_full[0]) & + ((write_full_word_0 & mem_acq[0]) | (num_bits_valid_mask_0_sum == 3'h0)) & + (16'h0 == wr_ID_fifo_out_data); + en_curr_base[0] = joined_in_fifo & (wr_data_fifo_out_op == 1'h0) & (~blk_full[0]) & + ((write_full_word_0 & mem_acq[0]) | (num_bits_valid_mask_0_sum == 3'h0)) & + (16'h0 == wr_ID_fifo_out_data); + set_write_wide_word_0 = (tmp_addr_0 == write_word_addr_reg_0) & write_word_addr_valid_sticky_0_sticky & + joined_in_fifo & (wr_data_fifo_out_op == 1'h1) & (16'h0 == wr_ID_fifo_out_data); + en_curr_bounds[0] = (mem_acq[0] | set_write_wide_word_0) & joined_in_fifo & (wr_data_fifo_out_op == + 1'h1) & (16'h0 == wr_ID_fifo_out_data); + wen_full[0] = joined_in_fifo & (wr_data_fifo_out_op == 1'h1) & ((buffet_capacity[0] - + curr_capacity_pre[0]) > wr_addr_fifo_out_data) & (16'h0 == wr_ID_fifo_out_data); + clr_write_wide_word_0 = ((tmp_addr_0 != write_word_addr_reg_0) | + (~write_word_addr_valid_sticky_0_sticky) | ((tmp_addr_0 == + write_word_addr_reg_0) & write_word_addr_valid_sticky_0_sticky & + write_full_word_0)) & joined_in_fifo & (wr_data_fifo_out_op == 1'h1) & + mem_acq[0] & (16'h0 == wr_ID_fifo_out_data); + write_to_sram_0 = write_full_word_0 & joined_in_fifo & ((buffet_capacity[0] - + curr_capacity_pre[0]) > wr_addr_fifo_out_data) & (16'h0 == wr_ID_fifo_out_data); + set_wide_word_addr_0 = ((tmp_addr_0 != write_word_addr_reg_0) | + (~write_word_addr_valid_sticky_0_sticky)) & joined_in_fifo & + (wr_data_fifo_out_op == 1'h1) & ((|write_wide_word_mask_reg_out_0) ? mem_acq[0]: + 1'h1) & (16'h0 == wr_ID_fifo_out_data); + sram_lock_0 = 1'h0; + read_from_sram_write_side_0 = joined_in_fifo & (16'h0 == wr_ID_fifo_out_data) & (~any_sram_lock) & + ((buffet_capacity[0] - curr_capacity_pre[0]) > wr_addr_fifo_out_data) & ((1'h0 + == wr_data_fifo_out_op) | ((tmp_addr_0 != write_word_addr_reg_0) & + write_word_addr_valid_sticky_0_sticky & (1'h1 == wr_data_fifo_out_op))) & + (num_bits_valid_mask_0_sum > 3'h0) & (~write_full_word_0); + pop_in_full[0] = ((mem_acq[0] | set_write_wide_word_0) & joined_in_fifo & (wr_data_fifo_out_op == + 1'h1) & ((buffet_capacity[0] - curr_capacity_pre[0]) > wr_addr_fifo_out_data) & + (16'h0 == wr_ID_fifo_out_data)) | (joined_in_fifo & (wr_data_fifo_out_op == + 1'h0) & (~blk_full[0]) & ((write_full_word_0 & mem_acq[0]) | + (num_bits_valid_mask_0_sum == 3'h0)) & (16'h0 == wr_ID_fifo_out_data)); + end :write_fsm_0_WRITING_0_Output + WR_START_0: begin :write_fsm_0_WR_START_0_Output + push_blk[0] = 1'h0; + en_curr_base[0] = 1'h0; + en_curr_bounds[0] = 1'h0; + wen_full[0] = 1'h0; + pop_in_full[0] = (wr_data_fifo_out_op == 1'h0) & (16'h0 == wr_ID_fifo_out_data); + set_write_wide_word_0 = 1'h0; + clr_write_wide_word_0 = 1'h0; + write_to_sram_0 = 1'h0; + set_wide_word_addr_0 = 1'h0; + sram_lock_0 = 1'h0; + read_from_sram_write_side_0 = 1'h0; + end :write_fsm_0_WR_START_0_Output + default: begin :write_fsm_0_default_Output + push_blk[0] = 1'h0; + en_curr_base[0] = 1'h0; + en_curr_bounds[0] = 1'h0; + wen_full[0] = 1'h0; + pop_in_full[0] = (wr_data_fifo_out_op == 1'h0) & (16'h0 == wr_ID_fifo_out_data); + set_write_wide_word_0 = 1'h0; + clr_write_wide_word_0 = 1'h0; + write_to_sram_0 = 1'h0; + set_wide_word_addr_0 = 1'h0; + sram_lock_0 = 1'h0; + read_from_sram_write_side_0 = 1'h0; + end :write_fsm_0_default_Output + endcase +end + +always_ff @(posedge clk, negedge rst_n) begin + if (!rst_n) begin + write_fsm_1_current_state <= WR_START_1; + end + else if (clk_en) begin + if (flush) begin + write_fsm_1_current_state <= WR_START_1; + end + else write_fsm_1_current_state <= write_fsm_1_next_state; + end +end +always_comb begin + write_fsm_1_next_state = write_fsm_1_current_state; + unique case (write_fsm_1_current_state) + MODIFY_1: begin + if (1'h1 == PREVIOUS_WR_OP) begin + write_fsm_1_next_state = WRITING_1; + end + else if ((1'h0 == PREVIOUS_WR_OP) & (~blk_full[1])) begin + write_fsm_1_next_state = WR_START_1; + end + else write_fsm_1_next_state = MODIFY_1; + end + WRITING_1: begin + if (joined_in_fifo & (wr_data_fifo_out_op == 1'h0) & (~blk_full[1]) & ((write_full_word_1 & mem_acq[2]) | (num_bits_valid_mask_1_sum == 3'h0)) & (16'h1 == wr_ID_fifo_out_data)) begin + write_fsm_1_next_state = WR_START_1; + end + else if (joined_in_fifo & (16'h1 == wr_ID_fifo_out_data) & mem_acq[2] & ((1'h0 == wr_data_fifo_out_op) | ((tmp_addr_1 != write_word_addr_reg_1) & write_word_addr_valid_sticky_1_sticky & (1'h1 == wr_data_fifo_out_op))) & (num_bits_valid_mask_1_sum > 3'h0) & (~write_full_word_1)) begin + write_fsm_1_next_state = MODIFY_1; + end + else write_fsm_1_next_state = WRITING_1; + end + WR_START_1: begin + if (joined_in_fifo & (wr_data_fifo_out_op == 1'h0) & (16'h1 == wr_ID_fifo_out_data) & tile_en) begin + write_fsm_1_next_state = WRITING_1; + end + else write_fsm_1_next_state = WR_START_1; + end + default: write_fsm_1_next_state = write_fsm_1_current_state; + endcase +end +always_comb begin + unique case (write_fsm_1_current_state) + MODIFY_1: begin :write_fsm_1_MODIFY_1_Output + push_blk[1] = (1'h0 == PREVIOUS_WR_OP) & (~blk_full[1]); + en_curr_base[1] = (1'h0 == PREVIOUS_WR_OP) & (~blk_full[1]); + en_curr_bounds[1] = 1'h0; + wen_full[1] = ~blk_full[1]; + pop_in_full[1] = ~blk_full[1]; + set_write_wide_word_1 = 1'h0; + clr_write_wide_word_1 = ~blk_full[1]; + write_to_sram_1 = ~blk_full[1]; + read_from_sram_write_side_1 = 1'h0; + set_wide_word_addr_1 = 1'h0; + sram_lock_1 = ~blk_full[1]; + end :write_fsm_1_MODIFY_1_Output + WRITING_1: begin :write_fsm_1_WRITING_1_Output + push_blk[1] = joined_in_fifo & (wr_data_fifo_out_op == 1'h0) & (~blk_full[1]) & + ((write_full_word_1 & mem_acq[2]) | (num_bits_valid_mask_1_sum == 3'h0)) & + (16'h1 == wr_ID_fifo_out_data); + en_curr_base[1] = joined_in_fifo & (wr_data_fifo_out_op == 1'h0) & (~blk_full[1]) & + ((write_full_word_1 & mem_acq[2]) | (num_bits_valid_mask_1_sum == 3'h0)) & + (16'h1 == wr_ID_fifo_out_data); + set_write_wide_word_1 = (tmp_addr_1 == write_word_addr_reg_1) & write_word_addr_valid_sticky_1_sticky & + joined_in_fifo & (wr_data_fifo_out_op == 1'h1) & (16'h1 == wr_ID_fifo_out_data); + en_curr_bounds[1] = (mem_acq[2] | set_write_wide_word_1) & joined_in_fifo & (wr_data_fifo_out_op == + 1'h1) & (16'h1 == wr_ID_fifo_out_data); + wen_full[1] = joined_in_fifo & (wr_data_fifo_out_op == 1'h1) & ((buffet_capacity[1] - + curr_capacity_pre[1]) > wr_addr_fifo_out_data) & (16'h1 == wr_ID_fifo_out_data); + clr_write_wide_word_1 = ((tmp_addr_1 != write_word_addr_reg_1) | + (~write_word_addr_valid_sticky_1_sticky) | ((tmp_addr_1 == + write_word_addr_reg_1) & write_word_addr_valid_sticky_1_sticky & + write_full_word_1)) & joined_in_fifo & (wr_data_fifo_out_op == 1'h1) & + mem_acq[2] & (16'h1 == wr_ID_fifo_out_data); + write_to_sram_1 = write_full_word_1 & joined_in_fifo & ((buffet_capacity[1] - + curr_capacity_pre[1]) > wr_addr_fifo_out_data) & (16'h1 == wr_ID_fifo_out_data); + set_wide_word_addr_1 = ((tmp_addr_1 != write_word_addr_reg_1) | + (~write_word_addr_valid_sticky_1_sticky)) & joined_in_fifo & + (wr_data_fifo_out_op == 1'h1) & ((|write_wide_word_mask_reg_out_1) ? mem_acq[2]: + 1'h1) & (16'h1 == wr_ID_fifo_out_data); + sram_lock_1 = 1'h0; + read_from_sram_write_side_1 = joined_in_fifo & (16'h1 == wr_ID_fifo_out_data) & (~any_sram_lock) & + ((buffet_capacity[1] - curr_capacity_pre[1]) > wr_addr_fifo_out_data) & ((1'h0 + == wr_data_fifo_out_op) | ((tmp_addr_1 != write_word_addr_reg_1) & + write_word_addr_valid_sticky_1_sticky & (1'h1 == wr_data_fifo_out_op))) & + (num_bits_valid_mask_1_sum > 3'h0) & (~write_full_word_1); + pop_in_full[1] = ((mem_acq[2] | set_write_wide_word_1) & joined_in_fifo & (wr_data_fifo_out_op == + 1'h1) & ((buffet_capacity[1] - curr_capacity_pre[1]) > wr_addr_fifo_out_data) & + (16'h1 == wr_ID_fifo_out_data)) | (joined_in_fifo & (wr_data_fifo_out_op == + 1'h0) & (~blk_full[1]) & ((write_full_word_1 & mem_acq[2]) | + (num_bits_valid_mask_1_sum == 3'h0)) & (16'h1 == wr_ID_fifo_out_data)); + end :write_fsm_1_WRITING_1_Output + WR_START_1: begin :write_fsm_1_WR_START_1_Output + push_blk[1] = 1'h0; + en_curr_base[1] = 1'h0; + en_curr_bounds[1] = 1'h0; + wen_full[1] = 1'h0; + pop_in_full[1] = (wr_data_fifo_out_op == 1'h0) & (16'h1 == wr_ID_fifo_out_data); + set_write_wide_word_1 = 1'h0; + clr_write_wide_word_1 = 1'h0; + write_to_sram_1 = 1'h0; + set_wide_word_addr_1 = 1'h0; + sram_lock_1 = 1'h0; + read_from_sram_write_side_1 = 1'h0; + end :write_fsm_1_WR_START_1_Output + default: begin :write_fsm_1_default_Output + push_blk[1] = 1'h0; + en_curr_base[1] = 1'h0; + en_curr_bounds[1] = 1'h0; + wen_full[1] = 1'h0; + pop_in_full[1] = (wr_data_fifo_out_op == 1'h0) & (16'h1 == wr_ID_fifo_out_data); + set_write_wide_word_1 = 1'h0; + clr_write_wide_word_1 = 1'h0; + write_to_sram_1 = 1'h0; + set_wide_word_addr_1 = 1'h0; + sram_lock_1 = 1'h0; + read_from_sram_write_side_1 = 1'h0; + end :write_fsm_1_default_Output + endcase +end +assign base_rr = {ren_full[1], write_to_sram_1 | read_from_sram_write_side_1, {ren_full[0], + write_to_sram_0 | read_from_sram_write_side_0}}; +assign rr_arbiter_resource_ready = ~any_sram_lock; +assign ren_to_mem = (|{mem_acq[1] & ren_full[0], mem_acq[3] & ren_full[1]}) | + (|{read_from_sram_write_side_0, read_from_sram_write_side_1}); +assign wen_to_mem = |({mem_acq[0] & write_to_sram_0, mem_acq[2] & write_to_sram_1} | {sram_lock_0, + sram_lock_1}); +assign tmp_wr_base = (mem_acq[2] & write_to_sram_1) ? curr_base_1 + buffet_base[1]: (mem_acq[0] & + write_to_sram_0) ? curr_base_0 + buffet_base[0]: 16'h0; +assign tmp_rd_base = (mem_acq[3] & ren_full[1]) ? blk_base[1] + buffet_base[1]: (mem_acq[1] & + ren_full[0]) ? blk_base[0] + buffet_base[0]: 16'h0; +assign data_to_mem = (mem_acq[0] & write_to_sram_0) ? write_wide_word_comb_out_0: (mem_acq[2] & + write_to_sram_1) ? write_wide_word_comb_out_1: sram_lock_0 ? + write_wide_word_modified_0: sram_lock_1 ? write_wide_word_modified_1: 64'h0; +assign addr_to_mem_local = (wen_to_mem | mem_acq[0] | mem_acq[2]) ? (mem_acq[0] | sram_lock_0) ? + write_word_addr_reg_0: write_word_addr_reg_1: (mem_acq[1] & ren_full[0]) ? + ((16'(rd_addr_fifo_out_addr_0[15:2]) + blk_base[0]) & buffet_capacity_mask[0]) + + buffet_base[0]: ((16'(rd_addr_fifo_out_addr_1[15:2]) + blk_base[1]) & + buffet_capacity_mask[1]) + buffet_base[1]; +reg_fifo_depth_2_w_17_afd_2 wr_data_fifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in(wr_data), + .flush(flush), + .pop(wr_data_fifo_pop), + .push(wr_data_valid), + .rst_n(rst_n), + .data_out(wr_data_fifo_data_out), + .empty(wr_data_fifo_empty), + .full(wr_data_fifo_full) +); + +reg_fifo_depth_2_w_16_afd_2 wr_addr_fifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in(wr_addr[0][15:0]), + .flush(flush), + .pop(wr_addr_fifo_pop), + .push(wr_addr_valid), + .rst_n(rst_n), + .data_out(wr_addr_fifo_out_data), + .empty(wr_addr_fifo_empty), + .full(wr_addr_fifo_full) +); + +reg_fifo_depth_2_w_16_afd_2 wr_ID_fifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in(wr_ID[0][15:0]), + .flush(flush), + .pop(wr_ID_fifo_pop), + .push(wr_ID_valid), + .rst_n(rst_n), + .data_out(wr_ID_fifo_out_data), + .empty(wr_ID_fifo_empty), + .full(wr_ID_fifo_full) +); + +reg_fifo_depth_2_w_16_afd_2 rd_op_fifo_0 ( + .clk(gclk), + .clk_en(clk_en), + .data_in(rd_op_0[0][15:0]), + .flush(flush), + .pop(rd_op_fifo_pop_0), + .push(rd_op_0_valid), + .rst_n(rst_n), + .data_out(rd_op_fifo_out_op_0), + .empty(rd_op_fifo_0_empty), + .full(rd_op_fifo_0_full) +); + +reg_fifo_depth_2_w_16_afd_2 rd_op_fifo_1 ( + .clk(gclk), + .clk_en(clk_en), + .data_in(rd_op_1[0][15:0]), + .flush(flush), + .pop(rd_op_fifo_pop_1), + .push(rd_op_1_valid), + .rst_n(rst_n), + .data_out(rd_op_fifo_out_op_1), + .empty(rd_op_fifo_1_empty), + .full(rd_op_fifo_1_full) +); + +reg_fifo_depth_2_w_16_afd_2 rd_addr_fifo_0 ( + .clk(gclk), + .clk_en(clk_en), + .data_in(rd_addr_0[0][15:0]), + .flush(flush), + .pop(rd_addr_fifo_pop_0), + .push(rd_addr_0_valid), + .rst_n(rst_n), + .data_out(rd_addr_fifo_out_addr_0), + .empty(rd_addr_fifo_0_empty), + .full(rd_addr_fifo_0_full) +); + +reg_fifo_depth_2_w_16_afd_2 rd_addr_fifo_1 ( + .clk(gclk), + .clk_en(clk_en), + .data_in(rd_addr_1[0][15:0]), + .flush(flush), + .pop(rd_addr_fifo_pop_1), + .push(rd_addr_1_valid), + .rst_n(rst_n), + .data_out(rd_addr_fifo_out_addr_1), + .empty(rd_addr_fifo_1_empty), + .full(rd_addr_fifo_1_full) +); + +reg_fifo_depth_2_w_17_afd_0 rd_rsp_fifo_0 ( + .clk(gclk), + .clk_en(clk_en), + .data_in(rd_rsp_fifo_0_in_data), + .flush(flush), + .pop(rd_rsp_data_0_ready), + .push(rd_rsp_fifo_0_push), + .rst_n(rst_n), + .almost_full(rd_rsp_fifo_0_almost_full), + .data_out(rd_rsp_data_0), + .empty(rd_rsp_fifo_0_empty), + .full(rd_rsp_fifo_0_full) +); + +reg_fifo_depth_2_w_17_afd_0 rd_rsp_fifo_1 ( + .clk(gclk), + .clk_en(clk_en), + .data_in(rd_rsp_fifo_1_in_data), + .flush(flush), + .pop(rd_rsp_data_1_ready), + .push(rd_rsp_fifo_1_push), + .rst_n(rst_n), + .almost_full(rd_rsp_fifo_1_almost_full), + .data_out(rd_rsp_data_1), + .empty(rd_rsp_fifo_1_empty), + .full(rd_rsp_fifo_1_full) +); + +reg_fifo_depth_2_w_32_afd_2 blk_fifo_0 ( + .clk(gclk), + .clk_en(clk_en), + .data_in(blk_fifo_0_data_in), + .flush(flush), + .pop(pop_blk[0]), + .push(push_blk[0]), + .rst_n(rst_n), + .data_out(blk_fifo_0_data_out), + .empty(blk_fifo_0_empty), + .full(blk_fifo_0_full) +); + +reg_fifo_depth_2_w_32_afd_2 blk_fifo_1 ( + .clk(gclk), + .clk_en(clk_en), + .data_in(blk_fifo_1_data_in), + .flush(flush), + .pop(pop_blk[1]), + .push(push_blk[1]), + .rst_n(rst_n), + .data_out(blk_fifo_1_data_out), + .empty(blk_fifo_1_empty), + .full(blk_fifo_1_full) +); + +arbiter_4_in_RR_algo rr_arbiter ( + .clk(gclk), + .clk_en(clk_en), + .flush(flush), + .request_in(base_rr), + .resource_ready(rr_arbiter_resource_ready), + .rst_n(rst_n), + .grant_out(mem_acq) +); + +endmodule // buffet_like_16 + +module fiber_access_16 ( + input logic [1:0] [3:0] buffet_buffet_capacity_log, + input logic [3:0] [15:0] buffet_data_from_mem_lifted, + input logic buffet_tile_en, + input logic clk, + input logic clk_en, + input logic flush, + input logic read_scanner_block_mode, + input logic read_scanner_block_rd_out_ready, + input logic read_scanner_coord_out_ready, + input logic read_scanner_dense, + input logic [15:0] read_scanner_dim_size, + input logic read_scanner_do_repeat, + input logic [15:0] read_scanner_inner_dim_offset, + input logic read_scanner_lookup, + input logic read_scanner_pos_out_ready, + input logic [15:0] read_scanner_repeat_factor, + input logic read_scanner_repeat_outer_inner_n, + input logic read_scanner_root, + input logic read_scanner_tile_en, + input logic [16:0] read_scanner_us_pos_in, + input logic read_scanner_us_pos_in_valid, + input logic rst_n, + input logic tile_en, + input logic vector_reduce_mode, + input logic [16:0] write_scanner_addr_in, + input logic write_scanner_addr_in_valid, + input logic write_scanner_block_mode, + input logic [16:0] write_scanner_block_wr_in, + input logic write_scanner_block_wr_in_valid, + input logic write_scanner_compressed, + input logic [16:0] write_scanner_data_in, + input logic write_scanner_data_in_valid, + input logic write_scanner_init_blank, + input logic write_scanner_lowest_level, + input logic [15:0] write_scanner_stop_lvl, + input logic write_scanner_tile_en, + output logic [8:0] buffet_addr_to_mem_lifted, + output logic [3:0] [15:0] buffet_data_to_mem_lifted, + output logic buffet_ren_to_mem_lifted, + output logic buffet_wen_to_mem_lifted, + output logic [16:0] read_scanner_block_rd_out, + output logic read_scanner_block_rd_out_valid, + output logic [16:0] read_scanner_coord_out, + output logic read_scanner_coord_out_valid, + output logic [16:0] read_scanner_pos_out, + output logic read_scanner_pos_out_valid, + output logic read_scanner_us_pos_in_ready, + output logic write_scanner_addr_in_ready, + output logic write_scanner_block_wr_in_ready, + output logic write_scanner_data_in_ready +); + +typedef enum logic[2:0] { + DS_READ_ROW = 3'h0, + INIT_BLANK_SEND_DONE = 3'h1, + INIT_BLANK_SEND_S0 = 3'h2, + ISSUE_READ_SEND_DONE = 3'h3, + ISSUE_READ_SEND_REF_CNT = 3'h4, + ISSUE_READ_SEND_S0 = 3'h5, + PROCESS_ROW = 3'h6, + START = 3'h7 +} vr_seq_state; +logic [16:0] S_level_0; +logic [16:0] S_level_1; +logic [16:0] S_level_2; +logic [0:0][16:0] buffet_wr_ID; +logic buffet_wr_ID_ready; +logic buffet_wr_ID_valid; +logic [0:0][16:0] buffet_wr_addr; +logic buffet_wr_addr_ready; +logic buffet_wr_addr_valid; +logic [0:0][16:0] buffet_wr_data; +logic buffet_wr_data_ready; +logic buffet_wr_data_valid; +logic done_sent_to_ds; +logic done_sent_to_ds_d1; +logic [16:0] done_token; +logic gclk; +logic [2:0] highest_seen_stoken; +logic input_row_fully_processed; +logic input_row_fully_processed_sticky_sticky; +logic input_row_fully_processed_sticky_was_high; +logic is_stop_token; +logic new_highest_stoken_seen; +logic output_matrix_fully_accumulated; +logic output_matrix_fully_accumulated_sticky_sticky; +logic output_matrix_fully_accumulated_sticky_was_high; +logic output_row_fully_accumulated; +logic output_row_fully_accumulated_sticky_sticky; +logic output_row_fully_accumulated_sticky_was_high; +logic [0:0][16:0] read_scanner_addr_out_0; +logic read_scanner_addr_out_0_ready; +logic read_scanner_addr_out_0_valid; +logic [0:0][16:0] read_scanner_addr_out_1; +logic read_scanner_addr_out_1_ready; +logic read_scanner_addr_out_1_valid; +logic [0:0][16:0] read_scanner_op_out_0; +logic read_scanner_op_out_0_ready; +logic read_scanner_op_out_0_valid; +logic [0:0][16:0] read_scanner_op_out_1; +logic read_scanner_op_out_1_ready; +logic read_scanner_op_out_1_valid; +logic [16:0] read_scanner_pos_out_0; +logic read_scanner_pos_out_valid_0; +logic [0:0][16:0] read_scanner_rd_rsp_data_in_0; +logic read_scanner_rd_rsp_data_in_0_ready; +logic read_scanner_rd_rsp_data_in_0_valid; +logic [0:0][16:0] read_scanner_rd_rsp_data_in_1; +logic read_scanner_rd_rsp_data_in_1_ready; +logic read_scanner_rd_rsp_data_in_1_valid; +logic [16:0] read_scanner_us_pos_in_0; +logic read_scanner_us_pos_in_valid_0; +logic rs_has_prepped_ds_row; +logic [16:0] semi_done_token; +logic vr_fsm_init_blank_DONE; +logic vr_fsm_init_blank_S0; +logic [16:0] vr_fsm_pos_to_read_scanner; +logic vr_fsm_pos_valid_to_read_scanner; +vr_seq_state vr_seq_current_state; +vr_seq_state vr_seq_next_state; +assign gclk = clk & tile_en; +assign S_level_0 = {1'h1, 16'h0}; +assign S_level_1 = {1'h1, 15'h0, 1'h1}; +assign S_level_2 = {1'h1, 14'h0, 1'h1, 1'h0}; +assign done_token = {1'h1, 7'h0, 1'h1, 8'h0}; +assign semi_done_token = {1'h1, 11'h0, 1'h1, 4'h0}; +assign done_sent_to_ds = (read_scanner_pos_out_0 == done_token) & read_scanner_pos_out_valid_0 & + read_scanner_pos_out_ready; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + done_sent_to_ds_d1 <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + done_sent_to_ds_d1 <= 1'h0; + end + else done_sent_to_ds_d1 <= done_sent_to_ds; + end +end +assign is_stop_token = (write_scanner_data_in[16] == 1'h1) & (~(write_scanner_data_in == done_token)) & + (~(write_scanner_data_in == semi_done_token)); +assign new_highest_stoken_seen = is_stop_token & (write_scanner_data_in[2:0] > highest_seen_stoken) & + write_scanner_data_in_valid & write_scanner_data_in_ready; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + highest_seen_stoken <= S_level_0[2:0]; + end + else if (clk_en) begin + if (flush) begin + highest_seen_stoken <= S_level_0[2:0]; + end + else if (done_sent_to_ds) begin + highest_seen_stoken <= S_level_0[2:0]; + end + else if (new_highest_stoken_seen) begin + highest_seen_stoken <= write_scanner_data_in[2:0]; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (!rst_n) begin + vr_seq_current_state <= START; + end + else if (clk_en) begin + if (flush) begin + vr_seq_current_state <= START; + end + else vr_seq_current_state <= vr_seq_next_state; + end +end +always_comb begin + vr_seq_next_state = vr_seq_current_state; + unique case (vr_seq_current_state) + DS_READ_ROW: begin + if (rs_has_prepped_ds_row) begin + vr_seq_next_state = INIT_BLANK_SEND_S0; + end + else vr_seq_next_state = DS_READ_ROW; + end + INIT_BLANK_SEND_DONE: begin + if (read_scanner_coord_out_ready) begin + vr_seq_next_state = PROCESS_ROW; + end + else vr_seq_next_state = INIT_BLANK_SEND_DONE; + end + INIT_BLANK_SEND_S0: begin + if (read_scanner_coord_out_ready) begin + vr_seq_next_state = INIT_BLANK_SEND_DONE; + end + else vr_seq_next_state = INIT_BLANK_SEND_S0; + end + ISSUE_READ_SEND_DONE: begin + if (read_scanner_us_pos_in_ready & (~output_row_fully_accumulated)) begin + vr_seq_next_state = PROCESS_ROW; + end + else if (read_scanner_us_pos_in_ready & output_row_fully_accumulated) begin + vr_seq_next_state = DS_READ_ROW; + end + else vr_seq_next_state = ISSUE_READ_SEND_DONE; + end + ISSUE_READ_SEND_REF_CNT: begin + if (read_scanner_us_pos_in_ready & ((~output_matrix_fully_accumulated) | (output_matrix_fully_accumulated & (~(S_level_1[2:0] < highest_seen_stoken))))) begin + vr_seq_next_state = ISSUE_READ_SEND_DONE; + end + else if (read_scanner_us_pos_in_ready & output_matrix_fully_accumulated & (S_level_1[2:0] < highest_seen_stoken)) begin + vr_seq_next_state = ISSUE_READ_SEND_S0; + end + else vr_seq_next_state = ISSUE_READ_SEND_REF_CNT; + end + ISSUE_READ_SEND_S0: begin + if (read_scanner_us_pos_in_ready) begin + vr_seq_next_state = ISSUE_READ_SEND_DONE; + end + else vr_seq_next_state = ISSUE_READ_SEND_S0; + end + PROCESS_ROW: begin + if (input_row_fully_processed) begin + vr_seq_next_state = ISSUE_READ_SEND_REF_CNT; + end + else vr_seq_next_state = PROCESS_ROW; + end + START: begin + if (vector_reduce_mode) begin + vr_seq_next_state = INIT_BLANK_SEND_S0; + end + else vr_seq_next_state = START; + end + default: begin end + endcase +end +always_comb begin + unique case (vr_seq_current_state) + DS_READ_ROW: begin :vr_seq_DS_READ_ROW_Output + vr_fsm_pos_to_read_scanner = 17'h0; + vr_fsm_pos_valid_to_read_scanner = 1'h0; + vr_fsm_init_blank_S0 = 1'h0; + vr_fsm_init_blank_DONE = 1'h0; + end :vr_seq_DS_READ_ROW_Output + INIT_BLANK_SEND_DONE: begin :vr_seq_INIT_BLANK_SEND_DONE_Output + vr_fsm_pos_to_read_scanner = 17'h0; + vr_fsm_pos_valid_to_read_scanner = 1'h0; + vr_fsm_init_blank_S0 = 1'h0; + vr_fsm_init_blank_DONE = 1'h1; + end :vr_seq_INIT_BLANK_SEND_DONE_Output + INIT_BLANK_SEND_S0: begin :vr_seq_INIT_BLANK_SEND_S0_Output + vr_fsm_pos_to_read_scanner = 17'h0; + vr_fsm_pos_valid_to_read_scanner = 1'h0; + vr_fsm_init_blank_S0 = 1'h1; + vr_fsm_init_blank_DONE = 1'h0; + end :vr_seq_INIT_BLANK_SEND_S0_Output + ISSUE_READ_SEND_DONE: begin :vr_seq_ISSUE_READ_SEND_DONE_Output + vr_fsm_pos_to_read_scanner = done_token; + vr_fsm_pos_valid_to_read_scanner = 1'h1; + vr_fsm_init_blank_S0 = 1'h0; + vr_fsm_init_blank_DONE = 1'h0; + end :vr_seq_ISSUE_READ_SEND_DONE_Output + ISSUE_READ_SEND_REF_CNT: begin :vr_seq_ISSUE_READ_SEND_REF_CNT_Output + vr_fsm_pos_to_read_scanner = 17'h0; + vr_fsm_pos_valid_to_read_scanner = 1'h1; + vr_fsm_init_blank_S0 = 1'h0; + vr_fsm_init_blank_DONE = 1'h0; + end :vr_seq_ISSUE_READ_SEND_REF_CNT_Output + ISSUE_READ_SEND_S0: begin :vr_seq_ISSUE_READ_SEND_S0_Output + vr_fsm_pos_to_read_scanner = S_level_0; + vr_fsm_pos_valid_to_read_scanner = 1'h1; + vr_fsm_init_blank_S0 = 1'h0; + vr_fsm_init_blank_DONE = 1'h0; + end :vr_seq_ISSUE_READ_SEND_S0_Output + PROCESS_ROW: begin :vr_seq_PROCESS_ROW_Output + vr_fsm_pos_to_read_scanner = 17'h0; + vr_fsm_pos_valid_to_read_scanner = 1'h0; + vr_fsm_init_blank_S0 = 1'h0; + vr_fsm_init_blank_DONE = 1'h0; + end :vr_seq_PROCESS_ROW_Output + START: begin :vr_seq_START_Output + vr_fsm_pos_to_read_scanner = 17'h0; + vr_fsm_pos_valid_to_read_scanner = 1'h0; + vr_fsm_init_blank_S0 = 1'h0; + vr_fsm_init_blank_DONE = 1'h0; + end :vr_seq_START_Output + default: begin end + endcase +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + input_row_fully_processed_sticky_was_high <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + input_row_fully_processed_sticky_was_high <= 1'h0; + end + else if (vr_seq_current_state == ISSUE_READ_SEND_DONE) begin + input_row_fully_processed_sticky_was_high <= 1'h0; + end + else if (((write_scanner_data_in == S_level_0) | (write_scanner_data_in == S_level_1) | (write_scanner_data_in == S_level_2)) & write_scanner_data_in_valid & write_scanner_data_in_ready) begin + input_row_fully_processed_sticky_was_high <= 1'h1; + end + end +end +assign input_row_fully_processed_sticky_sticky = (((write_scanner_data_in == S_level_0) | (write_scanner_data_in == S_level_1) | + (write_scanner_data_in == S_level_2)) & write_scanner_data_in_valid & + write_scanner_data_in_ready) | input_row_fully_processed_sticky_was_high; +assign input_row_fully_processed = input_row_fully_processed_sticky_sticky; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + output_row_fully_accumulated_sticky_was_high <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + output_row_fully_accumulated_sticky_was_high <= 1'h0; + end + else if (vr_seq_current_state == INIT_BLANK_SEND_S0) begin + output_row_fully_accumulated_sticky_was_high <= 1'h0; + end + else if (((write_scanner_data_in == S_level_1) | (write_scanner_data_in == S_level_2)) & write_scanner_data_in_valid & write_scanner_data_in_ready) begin + output_row_fully_accumulated_sticky_was_high <= 1'h1; + end + end +end +assign output_row_fully_accumulated_sticky_sticky = (((write_scanner_data_in == S_level_1) | (write_scanner_data_in == S_level_2)) & + write_scanner_data_in_valid & write_scanner_data_in_ready) | + output_row_fully_accumulated_sticky_was_high; +assign output_row_fully_accumulated = output_row_fully_accumulated_sticky_sticky; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + output_matrix_fully_accumulated_sticky_was_high <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + output_matrix_fully_accumulated_sticky_was_high <= 1'h0; + end + else if (done_sent_to_ds_d1) begin + output_matrix_fully_accumulated_sticky_was_high <= 1'h0; + end + else if ((write_scanner_data_in == done_token) & write_scanner_data_in_valid & write_scanner_data_in_ready) begin + output_matrix_fully_accumulated_sticky_was_high <= 1'h1; + end + end +end +assign output_matrix_fully_accumulated_sticky_sticky = ((write_scanner_data_in == done_token) & write_scanner_data_in_valid & + write_scanner_data_in_ready) | output_matrix_fully_accumulated_sticky_was_high; +assign output_matrix_fully_accumulated = output_matrix_fully_accumulated_sticky_sticky; +assign read_scanner_pos_out = read_scanner_pos_out_0; +assign read_scanner_pos_out_valid = read_scanner_pos_out_valid_0; +assign read_scanner_us_pos_in_0 = vector_reduce_mode ? vr_fsm_pos_to_read_scanner: read_scanner_us_pos_in; +assign read_scanner_us_pos_in_valid_0 = vector_reduce_mode ? vr_fsm_pos_valid_to_read_scanner: + read_scanner_us_pos_in_valid; +scanner_pipe read_scanner ( + .addr_out_0_ready(read_scanner_addr_out_0_ready), + .addr_out_1_ready(read_scanner_addr_out_1_ready), + .block_mode(read_scanner_block_mode), + .block_rd_out_ready(read_scanner_block_rd_out_ready), + .clk(gclk), + .clk_en(clk_en), + .coord_out_ready(read_scanner_coord_out_ready), + .dense(read_scanner_dense), + .dim_size(read_scanner_dim_size), + .do_repeat(read_scanner_do_repeat), + .flush(flush), + .inner_dim_offset(read_scanner_inner_dim_offset), + .lookup(read_scanner_lookup), + .op_out_0_ready(read_scanner_op_out_0_ready), + .op_out_1_ready(read_scanner_op_out_1_ready), + .output_matrix_fully_accumulated(output_matrix_fully_accumulated), + .output_row_fully_accumulated(output_row_fully_accumulated), + .pos_out_ready(read_scanner_pos_out_ready), + .pos_to_read_scanner_from_vr_fsm(vr_fsm_pos_to_read_scanner), + .rd_rsp_data_in_0(read_scanner_rd_rsp_data_in_0), + .rd_rsp_data_in_0_valid(read_scanner_rd_rsp_data_in_0_valid), + .rd_rsp_data_in_1(read_scanner_rd_rsp_data_in_1), + .rd_rsp_data_in_1_valid(read_scanner_rd_rsp_data_in_1_valid), + .repeat_factor(read_scanner_repeat_factor), + .repeat_outer_inner_n(read_scanner_repeat_outer_inner_n), + .root(read_scanner_root), + .rst_n(rst_n), + .tile_en(read_scanner_tile_en), + .us_pos_in(read_scanner_us_pos_in_0), + .us_pos_in_valid(read_scanner_us_pos_in_valid_0), + .vector_reduce_mode(vector_reduce_mode), + .vr_fsm_state_init_blank_DONE(vr_fsm_init_blank_DONE), + .vr_fsm_state_init_blank_S0(vr_fsm_init_blank_S0), + .addr_out_0(read_scanner_addr_out_0), + .addr_out_0_valid(read_scanner_addr_out_0_valid), + .addr_out_1(read_scanner_addr_out_1), + .addr_out_1_valid(read_scanner_addr_out_1_valid), + .block_rd_out(read_scanner_block_rd_out), + .block_rd_out_valid(read_scanner_block_rd_out_valid), + .coord_out(read_scanner_coord_out), + .coord_out_valid(read_scanner_coord_out_valid), + .op_out_0(read_scanner_op_out_0), + .op_out_0_valid(read_scanner_op_out_0_valid), + .op_out_1(read_scanner_op_out_1), + .op_out_1_valid(read_scanner_op_out_1_valid), + .pos_out(read_scanner_pos_out_0), + .pos_out_valid(read_scanner_pos_out_valid_0), + .rd_rsp_data_in_0_ready(read_scanner_rd_rsp_data_in_0_ready), + .rd_rsp_data_in_1_ready(read_scanner_rd_rsp_data_in_1_ready), + .rs_has_prepped_ds_row(rs_has_prepped_ds_row), + .us_pos_in_ready(read_scanner_us_pos_in_ready) +); + +buffet_like_16 buffet ( + .buffet_capacity_log(buffet_buffet_capacity_log), + .clk(gclk), + .clk_en(clk_en), + .data_from_mem(buffet_data_from_mem_lifted), + .flush(flush), + .rd_addr_0(read_scanner_addr_out_0), + .rd_addr_0_valid(read_scanner_addr_out_0_valid), + .rd_addr_1(read_scanner_addr_out_1), + .rd_addr_1_valid(read_scanner_addr_out_1_valid), + .rd_op_0(read_scanner_op_out_0), + .rd_op_0_valid(read_scanner_op_out_0_valid), + .rd_op_1(read_scanner_op_out_1), + .rd_op_1_valid(read_scanner_op_out_1_valid), + .rd_rsp_data_0_ready(read_scanner_rd_rsp_data_in_0_ready), + .rd_rsp_data_1_ready(read_scanner_rd_rsp_data_in_1_ready), + .rst_n(rst_n), + .tile_en(buffet_tile_en), + .wr_ID(buffet_wr_ID), + .wr_ID_valid(buffet_wr_ID_valid), + .wr_addr(buffet_wr_addr), + .wr_addr_valid(buffet_wr_addr_valid), + .wr_data(buffet_wr_data), + .wr_data_valid(buffet_wr_data_valid), + .addr_to_mem(buffet_addr_to_mem_lifted), + .data_to_mem(buffet_data_to_mem_lifted), + .rd_addr_0_ready(read_scanner_addr_out_0_ready), + .rd_addr_1_ready(read_scanner_addr_out_1_ready), + .rd_op_0_ready(read_scanner_op_out_0_ready), + .rd_op_1_ready(read_scanner_op_out_1_ready), + .rd_rsp_data_0(read_scanner_rd_rsp_data_in_0), + .rd_rsp_data_0_valid(read_scanner_rd_rsp_data_in_0_valid), + .rd_rsp_data_1(read_scanner_rd_rsp_data_in_1), + .rd_rsp_data_1_valid(read_scanner_rd_rsp_data_in_1_valid), + .ren_to_mem(buffet_ren_to_mem_lifted), + .wen_to_mem(buffet_wen_to_mem_lifted), + .wr_ID_ready(buffet_wr_ID_ready), + .wr_addr_ready(buffet_wr_addr_ready), + .wr_data_ready(buffet_wr_data_ready) +); + +write_scanner write_scanner ( + .ID_out_ready(buffet_wr_ID_ready), + .addr_in(write_scanner_addr_in), + .addr_in_valid(write_scanner_addr_in_valid), + .addr_out_ready(buffet_wr_addr_ready), + .block_mode(write_scanner_block_mode), + .block_wr_in(write_scanner_block_wr_in), + .block_wr_in_valid(write_scanner_block_wr_in_valid), + .clk(gclk), + .clk_en(clk_en), + .compressed(write_scanner_compressed), + .data_in(write_scanner_data_in), + .data_in_valid(write_scanner_data_in_valid), + .data_out_ready(buffet_wr_data_ready), + .flush(flush), + .init_blank(write_scanner_init_blank), + .lowest_level(write_scanner_lowest_level), + .rst_n(rst_n), + .stop_lvl(write_scanner_stop_lvl), + .tile_en(write_scanner_tile_en), + .vector_reduce_mode(vector_reduce_mode), + .ID_out(buffet_wr_ID), + .ID_out_valid(buffet_wr_ID_valid), + .addr_in_ready(write_scanner_addr_in_ready), + .addr_out(buffet_wr_addr), + .addr_out_valid(buffet_wr_addr_valid), + .block_wr_in_ready(write_scanner_block_wr_in_ready), + .data_in_ready(write_scanner_data_in_ready), + .data_out(buffet_wr_data), + .data_out_valid(buffet_wr_data_valid) +); + +endmodule // fiber_access_16 + +module fiber_access_16_flat ( + input logic clk, + input logic clk_en, + input logic [3:0] fiber_access_16_inst_buffet_buffet_capacity_log_0, + input logic [3:0] fiber_access_16_inst_buffet_buffet_capacity_log_1, + input logic [3:0] [15:0] fiber_access_16_inst_buffet_data_from_mem_lifted_lifted, + input logic fiber_access_16_inst_buffet_tile_en, + input logic fiber_access_16_inst_read_scanner_block_mode, + input logic fiber_access_16_inst_read_scanner_dense, + input logic [15:0] fiber_access_16_inst_read_scanner_dim_size, + input logic fiber_access_16_inst_read_scanner_do_repeat, + input logic [15:0] fiber_access_16_inst_read_scanner_inner_dim_offset, + input logic fiber_access_16_inst_read_scanner_lookup, + input logic [15:0] fiber_access_16_inst_read_scanner_repeat_factor, + input logic fiber_access_16_inst_read_scanner_repeat_outer_inner_n, + input logic fiber_access_16_inst_read_scanner_root, + input logic fiber_access_16_inst_read_scanner_tile_en, + input logic fiber_access_16_inst_tile_en, + input logic fiber_access_16_inst_vector_reduce_mode, + input logic fiber_access_16_inst_write_scanner_block_mode, + input logic fiber_access_16_inst_write_scanner_compressed, + input logic fiber_access_16_inst_write_scanner_init_blank, + input logic fiber_access_16_inst_write_scanner_lowest_level, + input logic [15:0] fiber_access_16_inst_write_scanner_stop_lvl, + input logic fiber_access_16_inst_write_scanner_tile_en, + input logic flush, + input logic read_scanner_block_rd_out_ready_f_, + input logic read_scanner_coord_out_ready_f_, + input logic read_scanner_pos_out_ready_f_, + input logic [0:0] [16:0] read_scanner_us_pos_in_f_, + input logic read_scanner_us_pos_in_valid_f_, + input logic rst_n, + input logic [0:0] [16:0] write_scanner_addr_in_f_, + input logic write_scanner_addr_in_valid_f_, + input logic [0:0] [16:0] write_scanner_block_wr_in_f_, + input logic write_scanner_block_wr_in_valid_f_, + input logic [0:0] [16:0] write_scanner_data_in_f_, + input logic write_scanner_data_in_valid_f_, + output logic [8:0] fiber_access_16_inst_buffet_addr_to_mem_lifted_lifted, + output logic [3:0] [15:0] fiber_access_16_inst_buffet_data_to_mem_lifted_lifted, + output logic fiber_access_16_inst_buffet_ren_to_mem_lifted_lifted, + output logic fiber_access_16_inst_buffet_wen_to_mem_lifted_lifted, + output logic [0:0] [16:0] read_scanner_block_rd_out_f_, + output logic read_scanner_block_rd_out_valid_f_, + output logic [0:0] [16:0] read_scanner_coord_out_f_, + output logic read_scanner_coord_out_valid_f_, + output logic [0:0] [16:0] read_scanner_pos_out_f_, + output logic read_scanner_pos_out_valid_f_, + output logic read_scanner_us_pos_in_ready_f_, + output logic write_scanner_addr_in_ready_f_, + output logic write_scanner_block_wr_in_ready_f_, + output logic write_scanner_data_in_ready_f_ +); + +logic [1:0][3:0] fiber_access_16_inst_buffet_buffet_capacity_log; +assign fiber_access_16_inst_buffet_buffet_capacity_log[0] = fiber_access_16_inst_buffet_buffet_capacity_log_0; +assign fiber_access_16_inst_buffet_buffet_capacity_log[1] = fiber_access_16_inst_buffet_buffet_capacity_log_1; +fiber_access_16 fiber_access_16_inst ( + .buffet_buffet_capacity_log(fiber_access_16_inst_buffet_buffet_capacity_log), + .buffet_data_from_mem_lifted(fiber_access_16_inst_buffet_data_from_mem_lifted_lifted), + .buffet_tile_en(fiber_access_16_inst_buffet_tile_en), + .clk(clk), + .clk_en(clk_en), + .flush(flush), + .read_scanner_block_mode(fiber_access_16_inst_read_scanner_block_mode), + .read_scanner_block_rd_out_ready(read_scanner_block_rd_out_ready_f_), + .read_scanner_coord_out_ready(read_scanner_coord_out_ready_f_), + .read_scanner_dense(fiber_access_16_inst_read_scanner_dense), + .read_scanner_dim_size(fiber_access_16_inst_read_scanner_dim_size), + .read_scanner_do_repeat(fiber_access_16_inst_read_scanner_do_repeat), + .read_scanner_inner_dim_offset(fiber_access_16_inst_read_scanner_inner_dim_offset), + .read_scanner_lookup(fiber_access_16_inst_read_scanner_lookup), + .read_scanner_pos_out_ready(read_scanner_pos_out_ready_f_), + .read_scanner_repeat_factor(fiber_access_16_inst_read_scanner_repeat_factor), + .read_scanner_repeat_outer_inner_n(fiber_access_16_inst_read_scanner_repeat_outer_inner_n), + .read_scanner_root(fiber_access_16_inst_read_scanner_root), + .read_scanner_tile_en(fiber_access_16_inst_read_scanner_tile_en), + .read_scanner_us_pos_in(read_scanner_us_pos_in_f_), + .read_scanner_us_pos_in_valid(read_scanner_us_pos_in_valid_f_), + .rst_n(rst_n), + .tile_en(fiber_access_16_inst_tile_en), + .vector_reduce_mode(fiber_access_16_inst_vector_reduce_mode), + .write_scanner_addr_in(write_scanner_addr_in_f_), + .write_scanner_addr_in_valid(write_scanner_addr_in_valid_f_), + .write_scanner_block_mode(fiber_access_16_inst_write_scanner_block_mode), + .write_scanner_block_wr_in(write_scanner_block_wr_in_f_), + .write_scanner_block_wr_in_valid(write_scanner_block_wr_in_valid_f_), + .write_scanner_compressed(fiber_access_16_inst_write_scanner_compressed), + .write_scanner_data_in(write_scanner_data_in_f_), + .write_scanner_data_in_valid(write_scanner_data_in_valid_f_), + .write_scanner_init_blank(fiber_access_16_inst_write_scanner_init_blank), + .write_scanner_lowest_level(fiber_access_16_inst_write_scanner_lowest_level), + .write_scanner_stop_lvl(fiber_access_16_inst_write_scanner_stop_lvl), + .write_scanner_tile_en(fiber_access_16_inst_write_scanner_tile_en), + .buffet_addr_to_mem_lifted(fiber_access_16_inst_buffet_addr_to_mem_lifted_lifted), + .buffet_data_to_mem_lifted(fiber_access_16_inst_buffet_data_to_mem_lifted_lifted), + .buffet_ren_to_mem_lifted(fiber_access_16_inst_buffet_ren_to_mem_lifted_lifted), + .buffet_wen_to_mem_lifted(fiber_access_16_inst_buffet_wen_to_mem_lifted_lifted), + .read_scanner_block_rd_out(read_scanner_block_rd_out_f_), + .read_scanner_block_rd_out_valid(read_scanner_block_rd_out_valid_f_), + .read_scanner_coord_out(read_scanner_coord_out_f_), + .read_scanner_coord_out_valid(read_scanner_coord_out_valid_f_), + .read_scanner_pos_out(read_scanner_pos_out_f_), + .read_scanner_pos_out_valid(read_scanner_pos_out_valid_f_), + .read_scanner_us_pos_in_ready(read_scanner_us_pos_in_ready_f_), + .write_scanner_addr_in_ready(write_scanner_addr_in_ready_f_), + .write_scanner_block_wr_in_ready(write_scanner_block_wr_in_ready_f_), + .write_scanner_data_in_ready(write_scanner_data_in_ready_f_) +); + +endmodule // fiber_access_16_flat + +module for_loop_3_11 #( + parameter CONFIG_WIDTH = 5'hB, + parameter ITERATOR_SUPPORT = 3'h3, + parameter ITERATOR_SUPPORT2 = 2'h2 +) +( + input logic clk, + input logic clk_en, + input logic [2:0] dimensionality, + input logic flush, + input logic [2:0] [10:0] ranges, + input logic rst_n, + input logic step, + output logic [1:0] mux_sel_out, + output logic restart +); + +logic [2:0] clear; +logic [2:0][10:0] dim_counter; +logic done; +logic [2:0] inc; +logic [10:0] inced_cnt; +logic [2:0] max_value; +logic maxed_value; +logic [1:0] mux_sel; +assign mux_sel_out = mux_sel; +assign inced_cnt = dim_counter[mux_sel] + 11'h1; +assign maxed_value = (dim_counter[mux_sel] == ranges[mux_sel]) & inc[mux_sel]; +always_comb begin + mux_sel = 2'h0; + done = 1'h0; + if (~done) begin + if ((~max_value[0]) & (dimensionality > 3'h0)) begin + mux_sel = 2'h0; + done = 1'h1; + end + end + if (~done) begin + if ((~max_value[1]) & (dimensionality > 3'h1)) begin + mux_sel = 2'h1; + done = 1'h1; + end + end + if (~done) begin + if ((~max_value[2]) & (dimensionality > 3'h2)) begin + mux_sel = 2'h2; + done = 1'h1; + end + end +end +always_comb begin + clear[0] = 1'h0; + if (((mux_sel > 2'h0) | (~done)) & step) begin + clear[0] = 1'h1; + end +end +always_comb begin + inc[0] = 1'h0; + if ((5'h0 == 5'h0) & step & (dimensionality > 3'h0)) begin + inc[0] = 1'h1; + end + else if ((mux_sel == 2'h0) & step & (dimensionality > 3'h0)) begin + inc[0] = 1'h1; + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + dim_counter[0] <= 11'h0; + end + else if (clk_en) begin + if (flush) begin + dim_counter[0] <= 11'h0; + end + else if (clear[0]) begin + dim_counter[0] <= 11'h0; + end + else if (inc[0]) begin + dim_counter[0] <= inced_cnt; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + max_value[0] <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + max_value[0] <= 1'h0; + end + else if (clear[0]) begin + max_value[0] <= 1'h0; + end + else if (inc[0]) begin + max_value[0] <= maxed_value; + end + end +end +always_comb begin + clear[1] = 1'h0; + if (((mux_sel > 2'h1) | (~done)) & step) begin + clear[1] = 1'h1; + end +end +always_comb begin + inc[1] = 1'h0; + if ((5'h1 == 5'h0) & step & (dimensionality > 3'h1)) begin + inc[1] = 1'h1; + end + else if ((mux_sel == 2'h1) & step & (dimensionality > 3'h1)) begin + inc[1] = 1'h1; + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + dim_counter[1] <= 11'h0; + end + else if (clk_en) begin + if (flush) begin + dim_counter[1] <= 11'h0; + end + else if (clear[1]) begin + dim_counter[1] <= 11'h0; + end + else if (inc[1]) begin + dim_counter[1] <= inced_cnt; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + max_value[1] <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + max_value[1] <= 1'h0; + end + else if (clear[1]) begin + max_value[1] <= 1'h0; + end + else if (inc[1]) begin + max_value[1] <= maxed_value; + end + end +end +always_comb begin + clear[2] = 1'h0; + if (((mux_sel > 2'h2) | (~done)) & step) begin + clear[2] = 1'h1; + end +end +always_comb begin + inc[2] = 1'h0; + if ((5'h2 == 5'h0) & step & (dimensionality > 3'h2)) begin + inc[2] = 1'h1; + end + else if ((mux_sel == 2'h2) & step & (dimensionality > 3'h2)) begin + inc[2] = 1'h1; + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + dim_counter[2] <= 11'h0; + end + else if (clk_en) begin + if (flush) begin + dim_counter[2] <= 11'h0; + end + else if (clear[2]) begin + dim_counter[2] <= 11'h0; + end + else if (inc[2]) begin + dim_counter[2] <= inced_cnt; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + max_value[2] <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + max_value[2] <= 1'h0; + end + else if (clear[2]) begin + max_value[2] <= 1'h0; + end + else if (inc[2]) begin + max_value[2] <= maxed_value; + end + end +end +assign restart = step & (~done); +endmodule // for_loop_3_11 + +module for_loop_6_11 #( + parameter CONFIG_WIDTH = 5'hB, + parameter ITERATOR_SUPPORT = 4'h6, + parameter ITERATOR_SUPPORT2 = 2'h2 +) +( + input logic clk, + input logic clk_en, + input logic [3:0] dimensionality, + input logic flush, + input logic [5:0] [10:0] ranges, + input logic rst_n, + input logic step, + output logic [2:0] mux_sel_out, + output logic restart +); + +logic [5:0] clear; +logic [5:0][10:0] dim_counter; +logic done; +logic [5:0] inc; +logic [10:0] inced_cnt; +logic [5:0] max_value; +logic maxed_value; +logic [2:0] mux_sel; +assign mux_sel_out = mux_sel; +assign inced_cnt = dim_counter[mux_sel] + 11'h1; +assign maxed_value = (dim_counter[mux_sel] == ranges[mux_sel]) & inc[mux_sel]; +always_comb begin + mux_sel = 3'h0; + done = 1'h0; + if (~done) begin + if ((~max_value[0]) & (dimensionality > 4'h0)) begin + mux_sel = 3'h0; + done = 1'h1; + end + end + if (~done) begin + if ((~max_value[1]) & (dimensionality > 4'h1)) begin + mux_sel = 3'h1; + done = 1'h1; + end + end + if (~done) begin + if ((~max_value[2]) & (dimensionality > 4'h2)) begin + mux_sel = 3'h2; + done = 1'h1; + end + end + if (~done) begin + if ((~max_value[3]) & (dimensionality > 4'h3)) begin + mux_sel = 3'h3; + done = 1'h1; + end + end + if (~done) begin + if ((~max_value[4]) & (dimensionality > 4'h4)) begin + mux_sel = 3'h4; + done = 1'h1; + end + end + if (~done) begin + if ((~max_value[5]) & (dimensionality > 4'h5)) begin + mux_sel = 3'h5; + done = 1'h1; + end + end +end +always_comb begin + clear[0] = 1'h0; + if (((mux_sel > 3'h0) | (~done)) & step) begin + clear[0] = 1'h1; + end +end +always_comb begin + inc[0] = 1'h0; + if ((5'h0 == 5'h0) & step & (dimensionality > 4'h0)) begin + inc[0] = 1'h1; + end + else if ((mux_sel == 3'h0) & step & (dimensionality > 4'h0)) begin + inc[0] = 1'h1; + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + dim_counter[0] <= 11'h0; + end + else if (clk_en) begin + if (flush) begin + dim_counter[0] <= 11'h0; + end + else if (clear[0]) begin + dim_counter[0] <= 11'h0; + end + else if (inc[0]) begin + dim_counter[0] <= inced_cnt; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + max_value[0] <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + max_value[0] <= 1'h0; + end + else if (clear[0]) begin + max_value[0] <= 1'h0; + end + else if (inc[0]) begin + max_value[0] <= maxed_value; + end + end +end +always_comb begin + clear[1] = 1'h0; + if (((mux_sel > 3'h1) | (~done)) & step) begin + clear[1] = 1'h1; + end +end +always_comb begin + inc[1] = 1'h0; + if ((5'h1 == 5'h0) & step & (dimensionality > 4'h1)) begin + inc[1] = 1'h1; + end + else if ((mux_sel == 3'h1) & step & (dimensionality > 4'h1)) begin + inc[1] = 1'h1; + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + dim_counter[1] <= 11'h0; + end + else if (clk_en) begin + if (flush) begin + dim_counter[1] <= 11'h0; + end + else if (clear[1]) begin + dim_counter[1] <= 11'h0; + end + else if (inc[1]) begin + dim_counter[1] <= inced_cnt; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + max_value[1] <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + max_value[1] <= 1'h0; + end + else if (clear[1]) begin + max_value[1] <= 1'h0; + end + else if (inc[1]) begin + max_value[1] <= maxed_value; + end + end +end +always_comb begin + clear[2] = 1'h0; + if (((mux_sel > 3'h2) | (~done)) & step) begin + clear[2] = 1'h1; + end +end +always_comb begin + inc[2] = 1'h0; + if ((5'h2 == 5'h0) & step & (dimensionality > 4'h2)) begin + inc[2] = 1'h1; + end + else if ((mux_sel == 3'h2) & step & (dimensionality > 4'h2)) begin + inc[2] = 1'h1; + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + dim_counter[2] <= 11'h0; + end + else if (clk_en) begin + if (flush) begin + dim_counter[2] <= 11'h0; + end + else if (clear[2]) begin + dim_counter[2] <= 11'h0; + end + else if (inc[2]) begin + dim_counter[2] <= inced_cnt; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + max_value[2] <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + max_value[2] <= 1'h0; + end + else if (clear[2]) begin + max_value[2] <= 1'h0; + end + else if (inc[2]) begin + max_value[2] <= maxed_value; + end + end +end +always_comb begin + clear[3] = 1'h0; + if (((mux_sel > 3'h3) | (~done)) & step) begin + clear[3] = 1'h1; + end +end +always_comb begin + inc[3] = 1'h0; + if ((5'h3 == 5'h0) & step & (dimensionality > 4'h3)) begin + inc[3] = 1'h1; + end + else if ((mux_sel == 3'h3) & step & (dimensionality > 4'h3)) begin + inc[3] = 1'h1; + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + dim_counter[3] <= 11'h0; + end + else if (clk_en) begin + if (flush) begin + dim_counter[3] <= 11'h0; + end + else if (clear[3]) begin + dim_counter[3] <= 11'h0; + end + else if (inc[3]) begin + dim_counter[3] <= inced_cnt; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + max_value[3] <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + max_value[3] <= 1'h0; + end + else if (clear[3]) begin + max_value[3] <= 1'h0; + end + else if (inc[3]) begin + max_value[3] <= maxed_value; + end + end +end +always_comb begin + clear[4] = 1'h0; + if (((mux_sel > 3'h4) | (~done)) & step) begin + clear[4] = 1'h1; + end +end +always_comb begin + inc[4] = 1'h0; + if ((5'h4 == 5'h0) & step & (dimensionality > 4'h4)) begin + inc[4] = 1'h1; + end + else if ((mux_sel == 3'h4) & step & (dimensionality > 4'h4)) begin + inc[4] = 1'h1; + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + dim_counter[4] <= 11'h0; + end + else if (clk_en) begin + if (flush) begin + dim_counter[4] <= 11'h0; + end + else if (clear[4]) begin + dim_counter[4] <= 11'h0; + end + else if (inc[4]) begin + dim_counter[4] <= inced_cnt; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + max_value[4] <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + max_value[4] <= 1'h0; + end + else if (clear[4]) begin + max_value[4] <= 1'h0; + end + else if (inc[4]) begin + max_value[4] <= maxed_value; + end + end +end +always_comb begin + clear[5] = 1'h0; + if (((mux_sel > 3'h5) | (~done)) & step) begin + clear[5] = 1'h1; + end +end +always_comb begin + inc[5] = 1'h0; + if ((5'h5 == 5'h0) & step & (dimensionality > 4'h5)) begin + inc[5] = 1'h1; + end + else if ((mux_sel == 3'h5) & step & (dimensionality > 4'h5)) begin + inc[5] = 1'h1; + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + dim_counter[5] <= 11'h0; + end + else if (clk_en) begin + if (flush) begin + dim_counter[5] <= 11'h0; + end + else if (clear[5]) begin + dim_counter[5] <= 11'h0; + end + else if (inc[5]) begin + dim_counter[5] <= inced_cnt; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + max_value[5] <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + max_value[5] <= 1'h0; + end + else if (clear[5]) begin + max_value[5] <= 1'h0; + end + else if (inc[5]) begin + max_value[5] <= maxed_value; + end + end +end +assign restart = step & (~done); +endmodule // for_loop_6_11 + +module reg_fifo_depth_0_w_16_afd_2 ( + input logic clk, + input logic clk_en, + input logic [0:0] [15:0] data_in, + input logic flush, + input logic pop, + input logic push, + input logic rst_n, + output logic almost_full, + output logic [0:0] [15:0] data_out, + output logic empty, + output logic full, + output logic valid +); + +assign data_out = data_in; +assign valid = push; +assign empty = ~push; +assign full = ~pop; +assign almost_full = ~pop; +endmodule // reg_fifo_depth_0_w_16_afd_2 + +module reg_fifo_depth_2_w_16_afd_2 ( + input logic clk, + input logic clk_en, + input logic [0:0] [15:0] data_in, + input logic flush, + input logic pop, + input logic push, + input logic rst_n, + output logic almost_full, + output logic [0:0] [15:0] data_out, + output logic empty, + output logic full, + output logic valid +); + +logic [1:0] num_items; +logic passthru; +logic rd_ptr; +logic read; +logic [1:0][0:0][15:0] reg_array; +logic wr_ptr; +logic write; +assign full = num_items == 2'h2; +assign almost_full = num_items >= 2'h0; +assign empty = num_items == 2'h0; +assign read = pop & (~passthru) & (~empty); +assign passthru = 1'h0; +assign write = push & (~passthru) & (~full); + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + num_items <= 2'h0; + end + else if (flush) begin + num_items <= 2'h0; + end + else if (clk_en) begin + if (write & (~read)) begin + num_items <= num_items + 2'h1; + end + else if ((~write) & read) begin + num_items <= num_items - 2'h1; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + reg_array <= 32'h0; + end + else if (flush) begin + reg_array <= 32'h0; + end + else if (clk_en) begin + if (write) begin + reg_array[wr_ptr] <= data_in; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + wr_ptr <= 1'h0; + end + else if (flush) begin + wr_ptr <= 1'h0; + end + else if (clk_en) begin + if (write) begin + if (wr_ptr == 1'h1) begin + wr_ptr <= 1'h0; + end + else wr_ptr <= wr_ptr + 1'h1; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + rd_ptr <= 1'h0; + end + else if (flush) begin + rd_ptr <= 1'h0; + end + else if (clk_en) begin + if (read) begin + rd_ptr <= rd_ptr + 1'h1; + end + end +end +always_comb begin + if (passthru) begin + data_out = data_in; + end + else data_out = reg_array[rd_ptr]; +end +always_comb begin + valid = (~empty) | passthru; +end +endmodule // reg_fifo_depth_2_w_16_afd_2 + +module reg_fifo_depth_2_w_17_afd_0 ( + input logic clk, + input logic clk_en, + input logic [0:0] [16:0] data_in, + input logic flush, + input logic pop, + input logic push, + input logic rst_n, + output logic almost_full, + output logic [0:0] [16:0] data_out, + output logic empty, + output logic full, + output logic valid +); + +logic [1:0] num_items; +logic passthru; +logic rd_ptr; +logic read; +logic [1:0][0:0][16:0] reg_array; +logic wr_ptr; +logic write; +assign full = num_items == 2'h2; +assign almost_full = num_items >= 2'h2; +assign empty = num_items == 2'h0; +assign read = pop & (~passthru) & (~empty); +assign passthru = 1'h0; +assign write = push & (~passthru) & (~full); + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + num_items <= 2'h0; + end + else if (flush) begin + num_items <= 2'h0; + end + else if (clk_en) begin + if (write & (~read)) begin + num_items <= num_items + 2'h1; + end + else if ((~write) & read) begin + num_items <= num_items - 2'h1; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + reg_array <= 34'h0; + end + else if (flush) begin + reg_array <= 34'h0; + end + else if (clk_en) begin + if (write) begin + reg_array[wr_ptr] <= data_in; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + wr_ptr <= 1'h0; + end + else if (flush) begin + wr_ptr <= 1'h0; + end + else if (clk_en) begin + if (write) begin + if (wr_ptr == 1'h1) begin + wr_ptr <= 1'h0; + end + else wr_ptr <= wr_ptr + 1'h1; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + rd_ptr <= 1'h0; + end + else if (flush) begin + rd_ptr <= 1'h0; + end + else if (clk_en) begin + if (read) begin + rd_ptr <= rd_ptr + 1'h1; + end + end +end +always_comb begin + if (passthru) begin + data_out = data_in; + end + else data_out = reg_array[rd_ptr]; +end +always_comb begin + valid = (~empty) | passthru; +end +endmodule // reg_fifo_depth_2_w_17_afd_0 + +module reg_fifo_depth_2_w_32_afd_2 ( + input logic clk, + input logic clk_en, + input logic [0:0] [31:0] data_in, + input logic flush, + input logic pop, + input logic push, + input logic rst_n, + output logic almost_full, + output logic [0:0] [31:0] data_out, + output logic empty, + output logic full, + output logic valid +); + +logic [1:0] num_items; +logic passthru; +logic rd_ptr; +logic read; +logic [1:0][0:0][31:0] reg_array; +logic wr_ptr; +logic write; +assign full = num_items == 2'h2; +assign almost_full = num_items >= 2'h0; +assign empty = num_items == 2'h0; +assign read = pop & (~passthru) & (~empty); +assign passthru = 1'h0; +assign write = push & (~passthru) & (~full); + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + num_items <= 2'h0; + end + else if (flush) begin + num_items <= 2'h0; + end + else if (clk_en) begin + if (clk_en) begin + if (clk_en) begin + if (write & (~read)) begin + num_items <= num_items + 2'h1; + end + else if ((~write) & read) begin + num_items <= num_items - 2'h1; + end + end + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + reg_array <= 64'h0; + end + else if (flush) begin + reg_array <= 64'h0; + end + else if (clk_en) begin + if (clk_en) begin + if (clk_en) begin + if (write) begin + reg_array[wr_ptr] <= data_in; + end + end + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + wr_ptr <= 1'h0; + end + else if (flush) begin + wr_ptr <= 1'h0; + end + else if (clk_en) begin + if (clk_en) begin + if (clk_en) begin + if (write) begin + if (wr_ptr == 1'h1) begin + wr_ptr <= 1'h0; + end + else wr_ptr <= wr_ptr + 1'h1; + end + end + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + rd_ptr <= 1'h0; + end + else if (flush) begin + rd_ptr <= 1'h0; + end + else if (clk_en) begin + if (clk_en) begin + if (clk_en) begin + if (read) begin + rd_ptr <= rd_ptr + 1'h1; + end + end + end + end +end +always_comb begin + if (passthru) begin + data_out = data_in; + end + else data_out = reg_array[rd_ptr]; +end +always_comb begin + valid = (~empty) | passthru; +end +endmodule // reg_fifo_depth_2_w_32_afd_2 + +module reservation_fifo_depth_32_w_17_num_per_1 ( + input logic clk, + input logic clk_en, + input logic [16:0] data_in_0, + input logic [16:0] fill_data_in, + input logic flush, + input logic pop, + input logic push_alloc, + input logic push_fill, + input logic push_reserve, + input logic rst_n, + output logic [16:0] data_out_0, + output logic empty, + output logic full, + output logic valid +); + +logic clr_item_ptr; +logic clr_read_ptr; +logic clr_write_ptr; +logic [0:0][16:0] data_in_packed; +logic [0:0][16:0] data_out; +logic enable_reserve_ptr; +logic inc_item_ptr; +logic inc_read_ptr; +logic inc_reserve_count; +logic inc_write_ptr; +logic item_ptr; +logic jump_next_0; +logic [4:0] next_0_valid; +logic [4:0] next_0_valid_d1; +logic [4:0] next_0_valid_high; +logic next_0_valid_high_done; +logic next_0_valid_high_found; +logic [4:0] next_0_valid_low; +logic next_0_valid_low_done; +logic next_0_valid_low_found; +logic [5:0] num_items; +logic read; +logic [4:0] read_ptr_addr; +logic [31:0][0:0][16:0] reg_array; +logic [15:0] reserve_count; +logic [4:0] reserve_ptr_val; +logic [31:0] valid_mask; +logic write_alloc; +logic write_fill; +logic [4:0] write_ptr_addr; +logic write_reserve; +logic write_reserve_final; +assign data_in_packed[0] = data_in_0; +assign data_out_0 = data_out[0]; +assign item_ptr = 1'h0; +assign inc_item_ptr = push_reserve; +assign clr_item_ptr = push_reserve & (item_ptr == 1'h0); + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + read_ptr_addr <= 5'h0; + end + else if (flush) begin + read_ptr_addr <= 5'h0; + end + else if (clk_en) begin + if (clk_en) begin + if (clr_read_ptr) begin + read_ptr_addr <= 5'h0; + end + else if (inc_read_ptr) begin + read_ptr_addr <= read_ptr_addr + 5'h1; + end + end + end +end +assign inc_read_ptr = read; +assign clr_read_ptr = 1'h0; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + write_ptr_addr <= 5'h0; + end + else if (flush) begin + write_ptr_addr <= 5'h0; + end + else if (clk_en) begin + if (clk_en) begin + if (clr_write_ptr) begin + write_ptr_addr <= 5'h0; + end + else if (inc_write_ptr) begin + write_ptr_addr <= write_ptr_addr + 5'h1; + end + end + end +end +assign inc_write_ptr = write_alloc | write_fill; +assign clr_write_ptr = 1'h0; +assign jump_next_0 = next_0_valid_high_found | next_0_valid_low_found; +assign enable_reserve_ptr = write_reserve_final | (write_fill & (reserve_ptr_val == write_ptr_addr)); + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + next_0_valid_d1 <= 5'h0; + end + else if (flush) begin + next_0_valid_d1 <= 5'h0; + end + else if (clk_en) begin + if (clk_en) begin + if (1'h0) begin + next_0_valid_d1 <= 5'h0; + end + else if (enable_reserve_ptr) begin + next_0_valid_d1 <= next_0_valid; + end + end + end +end +assign reserve_ptr_val = next_0_valid_d1; +assign next_0_valid = (write_fill & ((next_0_valid_d1 == write_ptr_addr) | ((~next_0_valid_high_found) + & (~next_0_valid_low_found)) | (next_0_valid_high_found ? next_0_valid_high == + write_ptr_addr: next_0_valid_low == write_ptr_addr))) ? write_ptr_addr + 5'h1: + ((~next_0_valid_high_found) & (~next_0_valid_low_found)) ? write_ptr_addr: + next_0_valid_high_found ? next_0_valid_high: next_0_valid_low; +assign full = num_items == 6'h20; +assign empty = num_items == 6'h0; +assign write_fill = push_fill & push_alloc & (~full); +assign write_alloc = push_alloc & (~full); +assign write_reserve = inc_item_ptr; +assign write_reserve_final = clr_item_ptr; +assign read = pop & valid_mask[read_ptr_addr]; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + num_items <= 6'h0; + end + else if (flush) begin + num_items <= 6'h0; + end + else if (clk_en) begin + if (clk_en) begin + if (write_alloc & (~read)) begin + num_items <= num_items + 6'h1; + end + else if ((~write_alloc) & read) begin + num_items <= num_items - 6'h1; + end + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + reg_array <= 544'h0; + end + else if (flush) begin + reg_array <= 544'h0; + end + else if (clk_en) begin + if (clk_en) begin + if (write_fill) begin + reg_array[write_ptr_addr] <= fill_data_in; + end + if (write_reserve) begin + reg_array[next_0_valid_d1] <= data_in_packed; + end + end + end +end +always_comb begin + data_out = reg_array[read_ptr_addr]; +end +always_comb begin + valid = valid_mask[read_ptr_addr]; +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + valid_mask <= 32'h0; + end + else if (flush) begin + valid_mask <= 32'h0; + end + else if (clk_en) begin + if (clk_en) begin + if (write_fill) begin + valid_mask[write_ptr_addr] <= 1'h1; + end + if (write_reserve_final) begin + valid_mask[next_0_valid_d1] <= 1'h1; + end + if (read) begin + valid_mask[read_ptr_addr] <= 1'h0; + end + end + end +end +always_comb begin + next_0_valid_high_found = 1'h0; + next_0_valid_high = 5'h0; + next_0_valid_high_done = 1'h0; + if (~next_0_valid_high_done) begin + if (next_0_valid_d1 < 5'h0) begin + if (valid_mask[0] == 1'h0) begin + next_0_valid_high_found = 1'h1; + next_0_valid_high = 5'h0; + next_0_valid_high_done = 1'h1; + end + end + end + if (~next_0_valid_high_done) begin + if (next_0_valid_d1 < 5'h1) begin + if (valid_mask[1] == 1'h0) begin + next_0_valid_high_found = 1'h1; + next_0_valid_high = 5'h1; + next_0_valid_high_done = 1'h1; + end + end + end + if (~next_0_valid_high_done) begin + if (next_0_valid_d1 < 5'h2) begin + if (valid_mask[2] == 1'h0) begin + next_0_valid_high_found = 1'h1; + next_0_valid_high = 5'h2; + next_0_valid_high_done = 1'h1; + end + end + end + if (~next_0_valid_high_done) begin + if (next_0_valid_d1 < 5'h3) begin + if (valid_mask[3] == 1'h0) begin + next_0_valid_high_found = 1'h1; + next_0_valid_high = 5'h3; + next_0_valid_high_done = 1'h1; + end + end + end + if (~next_0_valid_high_done) begin + if (next_0_valid_d1 < 5'h4) begin + if (valid_mask[4] == 1'h0) begin + next_0_valid_high_found = 1'h1; + next_0_valid_high = 5'h4; + next_0_valid_high_done = 1'h1; + end + end + end + if (~next_0_valid_high_done) begin + if (next_0_valid_d1 < 5'h5) begin + if (valid_mask[5] == 1'h0) begin + next_0_valid_high_found = 1'h1; + next_0_valid_high = 5'h5; + next_0_valid_high_done = 1'h1; + end + end + end + if (~next_0_valid_high_done) begin + if (next_0_valid_d1 < 5'h6) begin + if (valid_mask[6] == 1'h0) begin + next_0_valid_high_found = 1'h1; + next_0_valid_high = 5'h6; + next_0_valid_high_done = 1'h1; + end + end + end + if (~next_0_valid_high_done) begin + if (next_0_valid_d1 < 5'h7) begin + if (valid_mask[7] == 1'h0) begin + next_0_valid_high_found = 1'h1; + next_0_valid_high = 5'h7; + next_0_valid_high_done = 1'h1; + end + end + end + if (~next_0_valid_high_done) begin + if (next_0_valid_d1 < 5'h8) begin + if (valid_mask[8] == 1'h0) begin + next_0_valid_high_found = 1'h1; + next_0_valid_high = 5'h8; + next_0_valid_high_done = 1'h1; + end + end + end + if (~next_0_valid_high_done) begin + if (next_0_valid_d1 < 5'h9) begin + if (valid_mask[9] == 1'h0) begin + next_0_valid_high_found = 1'h1; + next_0_valid_high = 5'h9; + next_0_valid_high_done = 1'h1; + end + end + end + if (~next_0_valid_high_done) begin + if (next_0_valid_d1 < 5'hA) begin + if (valid_mask[10] == 1'h0) begin + next_0_valid_high_found = 1'h1; + next_0_valid_high = 5'hA; + next_0_valid_high_done = 1'h1; + end + end + end + if (~next_0_valid_high_done) begin + if (next_0_valid_d1 < 5'hB) begin + if (valid_mask[11] == 1'h0) begin + next_0_valid_high_found = 1'h1; + next_0_valid_high = 5'hB; + next_0_valid_high_done = 1'h1; + end + end + end + if (~next_0_valid_high_done) begin + if (next_0_valid_d1 < 5'hC) begin + if (valid_mask[12] == 1'h0) begin + next_0_valid_high_found = 1'h1; + next_0_valid_high = 5'hC; + next_0_valid_high_done = 1'h1; + end + end + end + if (~next_0_valid_high_done) begin + if (next_0_valid_d1 < 5'hD) begin + if (valid_mask[13] == 1'h0) begin + next_0_valid_high_found = 1'h1; + next_0_valid_high = 5'hD; + next_0_valid_high_done = 1'h1; + end + end + end + if (~next_0_valid_high_done) begin + if (next_0_valid_d1 < 5'hE) begin + if (valid_mask[14] == 1'h0) begin + next_0_valid_high_found = 1'h1; + next_0_valid_high = 5'hE; + next_0_valid_high_done = 1'h1; + end + end + end + if (~next_0_valid_high_done) begin + if (next_0_valid_d1 < 5'hF) begin + if (valid_mask[15] == 1'h0) begin + next_0_valid_high_found = 1'h1; + next_0_valid_high = 5'hF; + next_0_valid_high_done = 1'h1; + end + end + end + if (~next_0_valid_high_done) begin + if (next_0_valid_d1 < 5'h10) begin + if (valid_mask[16] == 1'h0) begin + next_0_valid_high_found = 1'h1; + next_0_valid_high = 5'h10; + next_0_valid_high_done = 1'h1; + end + end + end + if (~next_0_valid_high_done) begin + if (next_0_valid_d1 < 5'h11) begin + if (valid_mask[17] == 1'h0) begin + next_0_valid_high_found = 1'h1; + next_0_valid_high = 5'h11; + next_0_valid_high_done = 1'h1; + end + end + end + if (~next_0_valid_high_done) begin + if (next_0_valid_d1 < 5'h12) begin + if (valid_mask[18] == 1'h0) begin + next_0_valid_high_found = 1'h1; + next_0_valid_high = 5'h12; + next_0_valid_high_done = 1'h1; + end + end + end + if (~next_0_valid_high_done) begin + if (next_0_valid_d1 < 5'h13) begin + if (valid_mask[19] == 1'h0) begin + next_0_valid_high_found = 1'h1; + next_0_valid_high = 5'h13; + next_0_valid_high_done = 1'h1; + end + end + end + if (~next_0_valid_high_done) begin + if (next_0_valid_d1 < 5'h14) begin + if (valid_mask[20] == 1'h0) begin + next_0_valid_high_found = 1'h1; + next_0_valid_high = 5'h14; + next_0_valid_high_done = 1'h1; + end + end + end + if (~next_0_valid_high_done) begin + if (next_0_valid_d1 < 5'h15) begin + if (valid_mask[21] == 1'h0) begin + next_0_valid_high_found = 1'h1; + next_0_valid_high = 5'h15; + next_0_valid_high_done = 1'h1; + end + end + end + if (~next_0_valid_high_done) begin + if (next_0_valid_d1 < 5'h16) begin + if (valid_mask[22] == 1'h0) begin + next_0_valid_high_found = 1'h1; + next_0_valid_high = 5'h16; + next_0_valid_high_done = 1'h1; + end + end + end + if (~next_0_valid_high_done) begin + if (next_0_valid_d1 < 5'h17) begin + if (valid_mask[23] == 1'h0) begin + next_0_valid_high_found = 1'h1; + next_0_valid_high = 5'h17; + next_0_valid_high_done = 1'h1; + end + end + end + if (~next_0_valid_high_done) begin + if (next_0_valid_d1 < 5'h18) begin + if (valid_mask[24] == 1'h0) begin + next_0_valid_high_found = 1'h1; + next_0_valid_high = 5'h18; + next_0_valid_high_done = 1'h1; + end + end + end + if (~next_0_valid_high_done) begin + if (next_0_valid_d1 < 5'h19) begin + if (valid_mask[25] == 1'h0) begin + next_0_valid_high_found = 1'h1; + next_0_valid_high = 5'h19; + next_0_valid_high_done = 1'h1; + end + end + end + if (~next_0_valid_high_done) begin + if (next_0_valid_d1 < 5'h1A) begin + if (valid_mask[26] == 1'h0) begin + next_0_valid_high_found = 1'h1; + next_0_valid_high = 5'h1A; + next_0_valid_high_done = 1'h1; + end + end + end + if (~next_0_valid_high_done) begin + if (next_0_valid_d1 < 5'h1B) begin + if (valid_mask[27] == 1'h0) begin + next_0_valid_high_found = 1'h1; + next_0_valid_high = 5'h1B; + next_0_valid_high_done = 1'h1; + end + end + end + if (~next_0_valid_high_done) begin + if (next_0_valid_d1 < 5'h1C) begin + if (valid_mask[28] == 1'h0) begin + next_0_valid_high_found = 1'h1; + next_0_valid_high = 5'h1C; + next_0_valid_high_done = 1'h1; + end + end + end + if (~next_0_valid_high_done) begin + if (next_0_valid_d1 < 5'h1D) begin + if (valid_mask[29] == 1'h0) begin + next_0_valid_high_found = 1'h1; + next_0_valid_high = 5'h1D; + next_0_valid_high_done = 1'h1; + end + end + end + if (~next_0_valid_high_done) begin + if (next_0_valid_d1 < 5'h1E) begin + if (valid_mask[30] == 1'h0) begin + next_0_valid_high_found = 1'h1; + next_0_valid_high = 5'h1E; + next_0_valid_high_done = 1'h1; + end + end + end + if (~next_0_valid_high_done) begin + if (next_0_valid_d1 < 5'h1F) begin + if (valid_mask[31] == 1'h0) begin + next_0_valid_high_found = 1'h1; + next_0_valid_high = 5'h1F; + next_0_valid_high_done = 1'h1; + end + end + end +end +always_comb begin + next_0_valid_low_found = 1'h0; + next_0_valid_low = 5'h0; + next_0_valid_low_done = 1'h0; + if (~next_0_valid_low_done) begin + if (next_0_valid_d1 > 5'h0) begin + if (valid_mask[0] == 1'h0) begin + next_0_valid_low_found = 1'h1; + next_0_valid_low = 5'h0; + next_0_valid_low_done = 1'h1; + end + end + end + if (~next_0_valid_low_done) begin + if (next_0_valid_d1 > 5'h1) begin + if (valid_mask[1] == 1'h0) begin + next_0_valid_low_found = 1'h1; + next_0_valid_low = 5'h1; + next_0_valid_low_done = 1'h1; + end + end + end + if (~next_0_valid_low_done) begin + if (next_0_valid_d1 > 5'h2) begin + if (valid_mask[2] == 1'h0) begin + next_0_valid_low_found = 1'h1; + next_0_valid_low = 5'h2; + next_0_valid_low_done = 1'h1; + end + end + end + if (~next_0_valid_low_done) begin + if (next_0_valid_d1 > 5'h3) begin + if (valid_mask[3] == 1'h0) begin + next_0_valid_low_found = 1'h1; + next_0_valid_low = 5'h3; + next_0_valid_low_done = 1'h1; + end + end + end + if (~next_0_valid_low_done) begin + if (next_0_valid_d1 > 5'h4) begin + if (valid_mask[4] == 1'h0) begin + next_0_valid_low_found = 1'h1; + next_0_valid_low = 5'h4; + next_0_valid_low_done = 1'h1; + end + end + end + if (~next_0_valid_low_done) begin + if (next_0_valid_d1 > 5'h5) begin + if (valid_mask[5] == 1'h0) begin + next_0_valid_low_found = 1'h1; + next_0_valid_low = 5'h5; + next_0_valid_low_done = 1'h1; + end + end + end + if (~next_0_valid_low_done) begin + if (next_0_valid_d1 > 5'h6) begin + if (valid_mask[6] == 1'h0) begin + next_0_valid_low_found = 1'h1; + next_0_valid_low = 5'h6; + next_0_valid_low_done = 1'h1; + end + end + end + if (~next_0_valid_low_done) begin + if (next_0_valid_d1 > 5'h7) begin + if (valid_mask[7] == 1'h0) begin + next_0_valid_low_found = 1'h1; + next_0_valid_low = 5'h7; + next_0_valid_low_done = 1'h1; + end + end + end + if (~next_0_valid_low_done) begin + if (next_0_valid_d1 > 5'h8) begin + if (valid_mask[8] == 1'h0) begin + next_0_valid_low_found = 1'h1; + next_0_valid_low = 5'h8; + next_0_valid_low_done = 1'h1; + end + end + end + if (~next_0_valid_low_done) begin + if (next_0_valid_d1 > 5'h9) begin + if (valid_mask[9] == 1'h0) begin + next_0_valid_low_found = 1'h1; + next_0_valid_low = 5'h9; + next_0_valid_low_done = 1'h1; + end + end + end + if (~next_0_valid_low_done) begin + if (next_0_valid_d1 > 5'hA) begin + if (valid_mask[10] == 1'h0) begin + next_0_valid_low_found = 1'h1; + next_0_valid_low = 5'hA; + next_0_valid_low_done = 1'h1; + end + end + end + if (~next_0_valid_low_done) begin + if (next_0_valid_d1 > 5'hB) begin + if (valid_mask[11] == 1'h0) begin + next_0_valid_low_found = 1'h1; + next_0_valid_low = 5'hB; + next_0_valid_low_done = 1'h1; + end + end + end + if (~next_0_valid_low_done) begin + if (next_0_valid_d1 > 5'hC) begin + if (valid_mask[12] == 1'h0) begin + next_0_valid_low_found = 1'h1; + next_0_valid_low = 5'hC; + next_0_valid_low_done = 1'h1; + end + end + end + if (~next_0_valid_low_done) begin + if (next_0_valid_d1 > 5'hD) begin + if (valid_mask[13] == 1'h0) begin + next_0_valid_low_found = 1'h1; + next_0_valid_low = 5'hD; + next_0_valid_low_done = 1'h1; + end + end + end + if (~next_0_valid_low_done) begin + if (next_0_valid_d1 > 5'hE) begin + if (valid_mask[14] == 1'h0) begin + next_0_valid_low_found = 1'h1; + next_0_valid_low = 5'hE; + next_0_valid_low_done = 1'h1; + end + end + end + if (~next_0_valid_low_done) begin + if (next_0_valid_d1 > 5'hF) begin + if (valid_mask[15] == 1'h0) begin + next_0_valid_low_found = 1'h1; + next_0_valid_low = 5'hF; + next_0_valid_low_done = 1'h1; + end + end + end + if (~next_0_valid_low_done) begin + if (next_0_valid_d1 > 5'h10) begin + if (valid_mask[16] == 1'h0) begin + next_0_valid_low_found = 1'h1; + next_0_valid_low = 5'h10; + next_0_valid_low_done = 1'h1; + end + end + end + if (~next_0_valid_low_done) begin + if (next_0_valid_d1 > 5'h11) begin + if (valid_mask[17] == 1'h0) begin + next_0_valid_low_found = 1'h1; + next_0_valid_low = 5'h11; + next_0_valid_low_done = 1'h1; + end + end + end + if (~next_0_valid_low_done) begin + if (next_0_valid_d1 > 5'h12) begin + if (valid_mask[18] == 1'h0) begin + next_0_valid_low_found = 1'h1; + next_0_valid_low = 5'h12; + next_0_valid_low_done = 1'h1; + end + end + end + if (~next_0_valid_low_done) begin + if (next_0_valid_d1 > 5'h13) begin + if (valid_mask[19] == 1'h0) begin + next_0_valid_low_found = 1'h1; + next_0_valid_low = 5'h13; + next_0_valid_low_done = 1'h1; + end + end + end + if (~next_0_valid_low_done) begin + if (next_0_valid_d1 > 5'h14) begin + if (valid_mask[20] == 1'h0) begin + next_0_valid_low_found = 1'h1; + next_0_valid_low = 5'h14; + next_0_valid_low_done = 1'h1; + end + end + end + if (~next_0_valid_low_done) begin + if (next_0_valid_d1 > 5'h15) begin + if (valid_mask[21] == 1'h0) begin + next_0_valid_low_found = 1'h1; + next_0_valid_low = 5'h15; + next_0_valid_low_done = 1'h1; + end + end + end + if (~next_0_valid_low_done) begin + if (next_0_valid_d1 > 5'h16) begin + if (valid_mask[22] == 1'h0) begin + next_0_valid_low_found = 1'h1; + next_0_valid_low = 5'h16; + next_0_valid_low_done = 1'h1; + end + end + end + if (~next_0_valid_low_done) begin + if (next_0_valid_d1 > 5'h17) begin + if (valid_mask[23] == 1'h0) begin + next_0_valid_low_found = 1'h1; + next_0_valid_low = 5'h17; + next_0_valid_low_done = 1'h1; + end + end + end + if (~next_0_valid_low_done) begin + if (next_0_valid_d1 > 5'h18) begin + if (valid_mask[24] == 1'h0) begin + next_0_valid_low_found = 1'h1; + next_0_valid_low = 5'h18; + next_0_valid_low_done = 1'h1; + end + end + end + if (~next_0_valid_low_done) begin + if (next_0_valid_d1 > 5'h19) begin + if (valid_mask[25] == 1'h0) begin + next_0_valid_low_found = 1'h1; + next_0_valid_low = 5'h19; + next_0_valid_low_done = 1'h1; + end + end + end + if (~next_0_valid_low_done) begin + if (next_0_valid_d1 > 5'h1A) begin + if (valid_mask[26] == 1'h0) begin + next_0_valid_low_found = 1'h1; + next_0_valid_low = 5'h1A; + next_0_valid_low_done = 1'h1; + end + end + end + if (~next_0_valid_low_done) begin + if (next_0_valid_d1 > 5'h1B) begin + if (valid_mask[27] == 1'h0) begin + next_0_valid_low_found = 1'h1; + next_0_valid_low = 5'h1B; + next_0_valid_low_done = 1'h1; + end + end + end + if (~next_0_valid_low_done) begin + if (next_0_valid_d1 > 5'h1C) begin + if (valid_mask[28] == 1'h0) begin + next_0_valid_low_found = 1'h1; + next_0_valid_low = 5'h1C; + next_0_valid_low_done = 1'h1; + end + end + end + if (~next_0_valid_low_done) begin + if (next_0_valid_d1 > 5'h1D) begin + if (valid_mask[29] == 1'h0) begin + next_0_valid_low_found = 1'h1; + next_0_valid_low = 5'h1D; + next_0_valid_low_done = 1'h1; + end + end + end + if (~next_0_valid_low_done) begin + if (next_0_valid_d1 > 5'h1E) begin + if (valid_mask[30] == 1'h0) begin + next_0_valid_low_found = 1'h1; + next_0_valid_low = 5'h1E; + next_0_valid_low_done = 1'h1; + end + end + end + if (~next_0_valid_low_done) begin + if (next_0_valid_d1 > 5'h1F) begin + if (valid_mask[31] == 1'h0) begin + next_0_valid_low_found = 1'h1; + next_0_valid_low = 5'h1F; + next_0_valid_low_done = 1'h1; + end + end + end +end +assign inc_reserve_count = write_alloc & (~write_fill); + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + reserve_count <= 16'h0; + end + else if (flush) begin + reserve_count <= 16'h0; + end + else if (clk_en) begin + if (clk_en) begin + if (inc_reserve_count) begin + reserve_count <= reserve_count + 16'h1; + end + end + end +end +endmodule // reservation_fifo_depth_32_w_17_num_per_1 + +module reservation_fifo_depth_8_w_17_num_per_2 ( + input logic clk, + input logic clk_en, + input logic [16:0] data_in_0, + input logic [16:0] data_in_1, + input logic [16:0] fill_data_in, + input logic flush, + input logic pop, + input logic push_alloc, + input logic push_fill, + input logic push_reserve, + input logic rst_n, + output logic [16:0] data_out_0, + output logic [16:0] data_out_1, + output logic empty, + output logic full, + output logic valid +); + +logic clr_item_ptr; +logic clr_read_ptr; +logic clr_write_ptr; +logic [1:0][16:0] data_in_packed; +logic [1:0][16:0] data_out; +logic enable_reserve_ptr; +logic inc_item_ptr; +logic inc_read_ptr; +logic inc_reserve_count; +logic inc_write_ptr; +logic item_ptr_addr; +logic jump_next_0; +logic [2:0] next_0_valid; +logic [2:0] next_0_valid_d1; +logic [2:0] next_0_valid_high; +logic next_0_valid_high_done; +logic next_0_valid_high_found; +logic [2:0] next_0_valid_low; +logic next_0_valid_low_done; +logic next_0_valid_low_found; +logic [3:0] num_items; +logic read; +logic [2:0] read_ptr_addr; +logic [7:0][1:0][16:0] reg_array; +logic [15:0] reserve_count; +logic [2:0] reserve_ptr_val; +logic [7:0] valid_mask; +logic write_alloc; +logic write_fill; +logic [2:0] write_ptr_addr; +logic write_reserve; +logic write_reserve_final; +assign data_in_packed[0] = data_in_0; +assign data_in_packed[1] = data_in_1; +assign data_out_0 = data_out[0]; +assign data_out_1 = data_out[1]; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + item_ptr_addr <= 1'h0; + end + else if (flush) begin + item_ptr_addr <= 1'h0; + end + else if (clk_en) begin + if (clk_en) begin + if (clr_item_ptr) begin + item_ptr_addr <= 1'h0; + end + else if (inc_item_ptr) begin + item_ptr_addr <= item_ptr_addr + 1'h1; + end + end + end +end +assign inc_item_ptr = push_reserve; +assign clr_item_ptr = push_reserve & (item_ptr_addr == 1'h1); + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + read_ptr_addr <= 3'h0; + end + else if (flush) begin + read_ptr_addr <= 3'h0; + end + else if (clk_en) begin + if (clk_en) begin + if (clr_read_ptr) begin + read_ptr_addr <= 3'h0; + end + else if (inc_read_ptr) begin + read_ptr_addr <= read_ptr_addr + 3'h1; + end + end + end +end +assign inc_read_ptr = read; +assign clr_read_ptr = 1'h0; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + write_ptr_addr <= 3'h0; + end + else if (flush) begin + write_ptr_addr <= 3'h0; + end + else if (clk_en) begin + if (clk_en) begin + if (clr_write_ptr) begin + write_ptr_addr <= 3'h0; + end + else if (inc_write_ptr) begin + write_ptr_addr <= write_ptr_addr + 3'h1; + end + end + end +end +assign inc_write_ptr = write_alloc | write_fill; +assign clr_write_ptr = 1'h0; +assign jump_next_0 = next_0_valid_high_found | next_0_valid_low_found; +assign enable_reserve_ptr = write_reserve_final | (write_fill & (reserve_ptr_val == write_ptr_addr)); + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + next_0_valid_d1 <= 3'h0; + end + else if (flush) begin + next_0_valid_d1 <= 3'h0; + end + else if (clk_en) begin + if (clk_en) begin + if (1'h0) begin + next_0_valid_d1 <= 3'h0; + end + else if (enable_reserve_ptr) begin + next_0_valid_d1 <= next_0_valid; + end + end + end +end +assign reserve_ptr_val = next_0_valid_d1; +assign next_0_valid = (write_fill & ((next_0_valid_d1 == write_ptr_addr) | ((~next_0_valid_high_found) + & (~next_0_valid_low_found)) | (next_0_valid_high_found ? next_0_valid_high == + write_ptr_addr: next_0_valid_low == write_ptr_addr))) ? write_ptr_addr + 3'h1: + ((~next_0_valid_high_found) & (~next_0_valid_low_found)) ? write_ptr_addr: + next_0_valid_high_found ? next_0_valid_high: next_0_valid_low; +assign full = num_items == 4'h8; +assign empty = num_items == 4'h0; +assign write_fill = push_fill & push_alloc & (~full); +assign write_alloc = push_alloc & (~full); +assign write_reserve = inc_item_ptr; +assign write_reserve_final = clr_item_ptr; +assign read = pop & valid_mask[read_ptr_addr]; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + num_items <= 4'h0; + end + else if (flush) begin + num_items <= 4'h0; + end + else if (clk_en) begin + if (clk_en) begin + if (write_alloc & (~read)) begin + num_items <= num_items + 4'h1; + end + else if ((~write_alloc) & read) begin + num_items <= num_items - 4'h1; + end + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + reg_array <= 272'h0; + end + else if (flush) begin + reg_array <= 272'h0; + end + else if (clk_en) begin + if (clk_en) begin + if (write_fill) begin + reg_array[write_ptr_addr][0] <= fill_data_in; + end + if (write_reserve) begin + reg_array[next_0_valid_d1][item_ptr_addr] <= data_in_packed[item_ptr_addr]; + end + end + end +end +always_comb begin + data_out = reg_array[read_ptr_addr]; +end +always_comb begin + valid = valid_mask[read_ptr_addr]; +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + valid_mask <= 8'h0; + end + else if (flush) begin + valid_mask <= 8'h0; + end + else if (clk_en) begin + if (clk_en) begin + if (write_fill) begin + valid_mask[write_ptr_addr] <= 1'h1; + end + if (write_reserve_final) begin + valid_mask[next_0_valid_d1] <= 1'h1; + end + if (read) begin + valid_mask[read_ptr_addr] <= 1'h0; + end + end + end +end +always_comb begin + next_0_valid_high_found = 1'h0; + next_0_valid_high = 3'h0; + next_0_valid_high_done = 1'h0; + if (~next_0_valid_high_done) begin + if (next_0_valid_d1 < 3'h0) begin + if (valid_mask[0] == 1'h0) begin + next_0_valid_high_found = 1'h1; + next_0_valid_high = 3'h0; + next_0_valid_high_done = 1'h1; + end + end + end + if (~next_0_valid_high_done) begin + if (next_0_valid_d1 < 3'h1) begin + if (valid_mask[1] == 1'h0) begin + next_0_valid_high_found = 1'h1; + next_0_valid_high = 3'h1; + next_0_valid_high_done = 1'h1; + end + end + end + if (~next_0_valid_high_done) begin + if (next_0_valid_d1 < 3'h2) begin + if (valid_mask[2] == 1'h0) begin + next_0_valid_high_found = 1'h1; + next_0_valid_high = 3'h2; + next_0_valid_high_done = 1'h1; + end + end + end + if (~next_0_valid_high_done) begin + if (next_0_valid_d1 < 3'h3) begin + if (valid_mask[3] == 1'h0) begin + next_0_valid_high_found = 1'h1; + next_0_valid_high = 3'h3; + next_0_valid_high_done = 1'h1; + end + end + end + if (~next_0_valid_high_done) begin + if (next_0_valid_d1 < 3'h4) begin + if (valid_mask[4] == 1'h0) begin + next_0_valid_high_found = 1'h1; + next_0_valid_high = 3'h4; + next_0_valid_high_done = 1'h1; + end + end + end + if (~next_0_valid_high_done) begin + if (next_0_valid_d1 < 3'h5) begin + if (valid_mask[5] == 1'h0) begin + next_0_valid_high_found = 1'h1; + next_0_valid_high = 3'h5; + next_0_valid_high_done = 1'h1; + end + end + end + if (~next_0_valid_high_done) begin + if (next_0_valid_d1 < 3'h6) begin + if (valid_mask[6] == 1'h0) begin + next_0_valid_high_found = 1'h1; + next_0_valid_high = 3'h6; + next_0_valid_high_done = 1'h1; + end + end + end + if (~next_0_valid_high_done) begin + if (next_0_valid_d1 < 3'h7) begin + if (valid_mask[7] == 1'h0) begin + next_0_valid_high_found = 1'h1; + next_0_valid_high = 3'h7; + next_0_valid_high_done = 1'h1; + end + end + end +end +always_comb begin + next_0_valid_low_found = 1'h0; + next_0_valid_low = 3'h0; + next_0_valid_low_done = 1'h0; + if (~next_0_valid_low_done) begin + if (next_0_valid_d1 > 3'h0) begin + if (valid_mask[0] == 1'h0) begin + next_0_valid_low_found = 1'h1; + next_0_valid_low = 3'h0; + next_0_valid_low_done = 1'h1; + end + end + end + if (~next_0_valid_low_done) begin + if (next_0_valid_d1 > 3'h1) begin + if (valid_mask[1] == 1'h0) begin + next_0_valid_low_found = 1'h1; + next_0_valid_low = 3'h1; + next_0_valid_low_done = 1'h1; + end + end + end + if (~next_0_valid_low_done) begin + if (next_0_valid_d1 > 3'h2) begin + if (valid_mask[2] == 1'h0) begin + next_0_valid_low_found = 1'h1; + next_0_valid_low = 3'h2; + next_0_valid_low_done = 1'h1; + end + end + end + if (~next_0_valid_low_done) begin + if (next_0_valid_d1 > 3'h3) begin + if (valid_mask[3] == 1'h0) begin + next_0_valid_low_found = 1'h1; + next_0_valid_low = 3'h3; + next_0_valid_low_done = 1'h1; + end + end + end + if (~next_0_valid_low_done) begin + if (next_0_valid_d1 > 3'h4) begin + if (valid_mask[4] == 1'h0) begin + next_0_valid_low_found = 1'h1; + next_0_valid_low = 3'h4; + next_0_valid_low_done = 1'h1; + end + end + end + if (~next_0_valid_low_done) begin + if (next_0_valid_d1 > 3'h5) begin + if (valid_mask[5] == 1'h0) begin + next_0_valid_low_found = 1'h1; + next_0_valid_low = 3'h5; + next_0_valid_low_done = 1'h1; + end + end + end + if (~next_0_valid_low_done) begin + if (next_0_valid_d1 > 3'h6) begin + if (valid_mask[6] == 1'h0) begin + next_0_valid_low_found = 1'h1; + next_0_valid_low = 3'h6; + next_0_valid_low_done = 1'h1; + end + end + end + if (~next_0_valid_low_done) begin + if (next_0_valid_d1 > 3'h7) begin + if (valid_mask[7] == 1'h0) begin + next_0_valid_low_found = 1'h1; + next_0_valid_low = 3'h7; + next_0_valid_low_done = 1'h1; + end + end + end +end +assign inc_reserve_count = write_alloc & (~write_fill); + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + reserve_count <= 16'h0; + end + else if (flush) begin + reserve_count <= 16'h0; + end + else if (clk_en) begin + if (clk_en) begin + if (inc_reserve_count) begin + reserve_count <= reserve_count + 16'h1; + end + end + end +end +endmodule // reservation_fifo_depth_8_w_17_num_per_2 + +module scanner_pipe ( + input logic addr_out_0_ready, + input logic addr_out_1_ready, + input logic block_mode, + input logic block_rd_out_ready, + input logic clk, + input logic clk_en, + input logic coord_out_ready, + input logic dense, + input logic [15:0] dim_size, + input logic do_repeat, + input logic flush, + input logic [15:0] inner_dim_offset, + input logic lookup, + input logic op_out_0_ready, + input logic op_out_1_ready, + input logic output_matrix_fully_accumulated, + input logic output_row_fully_accumulated, + input logic pos_out_ready, + input logic [16:0] pos_to_read_scanner_from_vr_fsm, + input logic [0:0] [16:0] rd_rsp_data_in_0, + input logic rd_rsp_data_in_0_valid, + input logic [0:0] [16:0] rd_rsp_data_in_1, + input logic rd_rsp_data_in_1_valid, + input logic [15:0] repeat_factor, + input logic repeat_outer_inner_n, + input logic root, + input logic rst_n, + input logic tile_en, + input logic [16:0] us_pos_in, + input logic us_pos_in_valid, + input logic vector_reduce_mode, + input logic vr_fsm_state_init_blank_DONE, + input logic vr_fsm_state_init_blank_S0, + output logic [0:0] [16:0] addr_out_0, + output logic addr_out_0_valid, + output logic [0:0] [16:0] addr_out_1, + output logic addr_out_1_valid, + output logic [16:0] block_rd_out, + output logic block_rd_out_valid, + output logic [16:0] coord_out, + output logic coord_out_valid, + output logic [0:0] [16:0] op_out_0, + output logic op_out_0_valid, + output logic [0:0] [16:0] op_out_1, + output logic op_out_1_valid, + output logic [16:0] pos_out, + output logic pos_out_valid, + output logic rd_rsp_data_in_0_ready, + output logic rd_rsp_data_in_1_ready, + output logic rs_has_prepped_ds_row, + output logic us_pos_in_ready +); + +typedef enum logic[3:0] { + BLOCK_1_RD = 4'h0, + BLOCK_1_SIZE_REC = 4'h1, + BLOCK_1_SIZE_REQ = 4'h2, + BLOCK_2_RD = 4'h3, + BLOCK_2_SIZE_REC = 4'h4, + BLOCK_2_SIZE_REQ = 4'h5, + DENSE_STRM = 4'h6, + DONE_CRD = 4'h7, + FREE_CRD = 4'h8, + FREE_CRD2 = 4'h9, + PASS_DONE_CRD = 4'hA, + READOUT_SYNC_LOCK = 4'hB, + SEQ_STRM = 4'hC, + START_CRD = 4'hD +} scan_seq_crd_state; +typedef enum logic[3:0] { + DONE_SEG = 4'h0, + FREE_SEG = 4'h1, + INJECT_0 = 4'h2, + INJECT_DONE = 4'h3, + INJECT_ROUTING = 4'h4, + LOOKUP = 4'h5, + PASS_DONE_SEG = 4'h6, + PASS_STOP_SEG = 4'h7, + READ = 4'h8, + READ_ALT = 4'h9, + START_SEG = 4'hA +} scan_seq_seg_state; +logic [15:0] READS_MADE; +logic [15:0] READS_REC_CRD_READ; +logic [16:0] S_level_0; +logic [0:0][16:0] addr_out_fifo_0_data_in; +logic addr_out_fifo_0_empty; +logic addr_out_fifo_0_full; +logic addr_out_fifo_0_push; +logic [0:0][16:0] addr_out_fifo_1_data_in; +logic addr_out_fifo_1_empty; +logic addr_out_fifo_1_full; +logic addr_out_fifo_1_push; +logic [0:0][15:0] addr_out_to_fifo_0; +logic [0:0][15:0] addr_out_to_fifo_1; +logic [1:0] base_rr_0; +logic [1:0] base_rr_1; +logic block_rd_fifo_empty; +logic block_rd_fifo_full; +logic block_rd_fifo_push; +logic clr_fiber_addr; +logic clr_final_pushed_done; +logic clr_pop_infifo_sticky; +logic clr_pushed_done_crd; +logic clr_pushed_done_seg; +logic clr_readout_loop_crd; +logic clr_readout_loop_seg; +logic clr_rep; +logic clr_req_made_crd; +logic clr_req_made_seg; +logic clr_req_rec_crd; +logic clr_req_rec_seg; +logic clr_seen_root_eos; +logic clr_used_data; +logic [16:0] coord_fifo_in_packed; +logic [16:0] coord_fifo_out_packed; +logic coord_fifo_push; +logic coordinate_fifo_empty; +logic coordinate_fifo_full; +logic [0:0][15:0] crd_ID_out_to_fifo; +logic [0:0][15:0] crd_addr_out_to_fifo; +logic crd_grant_push_0; +logic crd_grant_push_1; +logic crd_in_done_state; +logic [0:0][15:0] crd_op_out_to_fifo; +logic [16:0] crd_out_to_fifo; +logic crd_pop_infifo; +logic crd_rd_rsp_fifo_pop; +logic crd_req_push; +logic [16:0] crd_res_fifo_data_in_0; +logic [16:0] crd_res_fifo_data_out; +logic [16:0] crd_res_fifo_fill_data_in; +logic crd_res_fifo_full; +logic crd_res_fifo_pop; +logic crd_res_fifo_push_alloc; +logic crd_res_fifo_push_alloc_0; +logic crd_res_fifo_push_fill; +logic crd_res_fifo_push_fill_0; +logic crd_res_fifo_push_reserve_0; +logic crd_res_fifo_valid; +logic done_in; +logic [16:0] done_token; +logic en_reg_data_in; +logic eos_in; +logic [15:0] fiber_addr; +logic [15:0] fiber_addr_pre; +logic [15:0] fiber_addr_pre_d1; +logic [15:0] fiber_addr_pre_d1_d1; +logic fifo_full; +logic [1:0] fifo_full_pre; +logic [16:0] fifo_out_us_packed; +logic fifo_us_full; +logic [16:0] fifo_us_in_packed; +logic final_pushed_done_sticky_sticky; +logic final_pushed_done_sticky_was_high; +logic gclk; +logic inc_fiber_addr; +logic inc_rep; +logic inc_req_made_crd; +logic inc_req_made_seg; +logic inc_req_rec_crd; +logic inc_req_rec_seg; +logic inc_requests_REC_CRD_READ; +logic inc_requests_made_CRDDD_READ; +logic infifo_eos_in; +logic [15:0] infifo_pos_in; +logic [15:0] infifo_pos_in_d1; +logic infifo_pos_in_d1_en; +logic infifo_valid_in; +logic [0:0][16:0] input_fifo_data_out; +logic input_fifo_empty; +logic iter_finish_sticky; +logic iter_finish_was_high; +logic [16:0] last_stop_token; +logic last_valid_accepting; +logic maybe_in; +logic [15:0] next_seq_addr; +logic [15:0] next_seq_length; +logic no_outfifo_full_0; +logic no_outfifo_full_1; +logic non_vr_coord_fifo_push; +logic non_vr_pos_out_fifo_push; +logic [15:0] num_reps; +logic [15:0] num_req_made_crd; +logic [15:0] num_req_made_seg; +logic [15:0] num_req_rec_crd; +logic [15:0] num_req_rec_seg; +logic [0:0][16:0] op_out_fifo_0_data_in; +logic op_out_fifo_0_empty; +logic op_out_fifo_0_full; +logic op_out_fifo_0_push; +logic [0:0][16:0] op_out_fifo_1_data_in; +logic op_out_fifo_1_empty; +logic op_out_fifo_1_full; +logic op_out_fifo_1_push; +logic [0:0][15:0] op_out_to_fifo_0; +logic [0:0][15:0] op_out_to_fifo_1; +logic [15:0] payload_ptr; +logic pop_infifo; +logic pop_infifo_sticky_sticky; +logic pop_infifo_sticky_was_high; +logic [15:0] pos_addr; +logic pos_fifo_empty; +logic pos_fifo_full; +logic [16:0] pos_fifo_in_packed; +logic [16:0] pos_fifo_out_packed; +logic pos_out_fifo_push; +logic [16:0] pos_out_to_fifo; +logic pos_out_valid_mux_sel; +logic [15:0] ptr_in; +logic [15:0] ptr_in_d1; +logic ptr_reg_en; +logic pushed_done_sticky_sticky; +logic pushed_done_sticky_was_high; +logic rd_rsp_fifo_0_empty; +logic rd_rsp_fifo_0_full; +logic [16:0] rd_rsp_fifo_0_out_data; +logic [16:0] rd_rsp_fifo_0_out_data_d1; +logic rd_rsp_fifo_0_valid; +logic rd_rsp_fifo_1_empty; +logic rd_rsp_fifo_1_full; +logic [16:0] rd_rsp_fifo_1_out_data; +logic rd_rsp_fifo_1_valid; +logic readout_dst_crd; +logic readout_dst_seg; +logic readout_loop_sticky_sticky; +logic readout_loop_sticky_was_high; +logic rep_finish_sticky; +logic rep_finish_was_high; +logic [1:0] rr_arbiter_0_grant_out; +logic [1:0] rr_arbiter_1_grant_out; +logic rs_has_prepped_ds_row_sticky_sticky; +logic rs_has_prepped_ds_row_sticky_was_high; +scan_seq_crd_state scan_seq_crd_current_state; +scan_seq_crd_state scan_seq_crd_next_state; +scan_seq_seg_state scan_seq_seg_current_state; +scan_seq_seg_state scan_seq_seg_next_state; +logic seen_root_eos_sticky; +logic seen_root_eos_was_high; +logic [0:0][15:0] seg_ID_out_to_fifo; +logic [0:0][15:0] seg_addr_out_to_fifo; +logic seg_grant_push_0; +logic seg_grant_push_1; +logic seg_in_done_state; +logic seg_in_start_state; +logic [0:0][15:0] seg_op_out_to_fifo; +logic seg_pop_infifo; +logic seg_rd_rsp_fifo_pop; +logic seg_req_push; +logic [16:0] seg_res_fifo_data_out_0; +logic [16:0] seg_res_fifo_data_out_1; +logic seg_res_fifo_done_out; +logic [16:0] seg_res_fifo_fill_data_in; +logic seg_res_fifo_full; +logic seg_res_fifo_pop; +logic seg_res_fifo_pop_0; +logic seg_res_fifo_push_alloc; +logic seg_res_fifo_push_alloc_0; +logic seg_res_fifo_push_fill; +logic seg_res_fifo_push_fill_0; +logic seg_res_fifo_push_reserve_0; +logic seg_res_fifo_valid; +logic [15:0] seq_addr; +logic [15:0] seq_length; +logic [15:0] seq_length_ptr_math; +logic set_final_pushed_done; +logic set_pushed_done_crd; +logic set_pushed_done_seg; +logic set_readout_loop_crd; +logic set_readout_loop_seg; +logic update_seq_state; +logic [15:0] us_fifo_inject_data; +logic us_fifo_inject_eos; +logic us_fifo_inject_push; +logic us_fifo_push; +logic use_data_sticky_sticky; +logic use_data_sticky_was_high; +logic [15:0] valid_cnt; +logic valid_inc; +logic valid_rst; +assign gclk = clk & tile_en; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + fiber_addr_pre <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + fiber_addr_pre <= 16'h0; + end + else if (clr_fiber_addr) begin + fiber_addr_pre <= 16'h0; + end + else if (inc_fiber_addr) begin + fiber_addr_pre <= fiber_addr_pre + 16'h1; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + num_reps <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + num_reps <= 16'h0; + end + else if (clr_rep) begin + num_reps <= 16'h0; + end + else if (inc_rep) begin + num_reps <= num_reps + 16'h1; + end + end +end +assign fifo_us_in_packed[16] = root ? us_fifo_inject_eos: us_pos_in[16]; +assign fifo_us_in_packed[15:0] = root ? us_fifo_inject_data: us_pos_in[15:0]; +assign us_fifo_push = root ? us_fifo_inject_push: us_pos_in_valid; +assign infifo_eos_in = fifo_out_us_packed[16]; +assign infifo_pos_in = fifo_out_us_packed[15:0]; +assign pop_infifo = seg_pop_infifo | crd_pop_infifo; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + pop_infifo_sticky_was_high <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + pop_infifo_sticky_was_high <= 1'h0; + end + else if (clr_pop_infifo_sticky) begin + pop_infifo_sticky_was_high <= 1'h0; + end + else if (pop_infifo) begin + pop_infifo_sticky_was_high <= 1'h1; + end + end +end +assign pop_infifo_sticky_sticky = pop_infifo_sticky_was_high; +assign fifo_out_us_packed = input_fifo_data_out; +assign us_pos_in_ready = ~fifo_us_full; +assign infifo_valid_in = ~input_fifo_empty; +assign rd_rsp_data_in_0_ready = ~rd_rsp_fifo_0_full; +assign rd_rsp_data_in_1_ready = ~rd_rsp_fifo_1_full; +assign rd_rsp_fifo_0_valid = ~rd_rsp_fifo_0_empty; +assign rd_rsp_fifo_1_valid = ~rd_rsp_fifo_1_empty; +assign no_outfifo_full_0 = ~(op_out_fifo_0_full | addr_out_fifo_0_full); +assign no_outfifo_full_1 = ~(op_out_fifo_1_full | addr_out_fifo_1_full); +assign base_rr_0 = {crd_req_push & (16'h0 == crd_ID_out_to_fifo), seg_req_push & (16'h0 == + seg_ID_out_to_fifo)}; +assign base_rr_1 = {crd_req_push & (16'h1 == crd_ID_out_to_fifo), seg_req_push & (16'h1 == + seg_ID_out_to_fifo)}; +assign {crd_grant_push_0, seg_grant_push_0} = rr_arbiter_0_grant_out; +assign {crd_grant_push_1, seg_grant_push_1} = rr_arbiter_1_grant_out; +assign addr_out_to_fifo_0 = crd_grant_push_0 ? crd_addr_out_to_fifo: seg_addr_out_to_fifo; +assign addr_out_to_fifo_1 = crd_grant_push_1 ? crd_addr_out_to_fifo: seg_addr_out_to_fifo; +assign op_out_to_fifo_0 = crd_grant_push_0 ? crd_op_out_to_fifo: seg_op_out_to_fifo; +assign op_out_to_fifo_1 = crd_grant_push_1 ? crd_op_out_to_fifo: seg_op_out_to_fifo; +assign addr_out_fifo_0_push = seg_grant_push_0 | crd_grant_push_0; +assign addr_out_fifo_1_push = seg_grant_push_1 | crd_grant_push_1; +assign op_out_fifo_0_push = seg_grant_push_0 | crd_grant_push_0; +assign op_out_fifo_1_push = seg_grant_push_1 | crd_grant_push_1; +assign addr_out_fifo_0_data_in = {1'h0, addr_out_to_fifo_0}; +assign addr_out_fifo_1_data_in = {1'h0, addr_out_to_fifo_1}; +assign addr_out_0_valid = ~addr_out_fifo_0_empty; +assign addr_out_1_valid = ~addr_out_fifo_1_empty; +assign op_out_fifo_0_data_in = {1'h0, op_out_to_fifo_0}; +assign op_out_fifo_1_data_in = {1'h0, op_out_to_fifo_1}; +assign op_out_0_valid = ~op_out_fifo_0_empty; +assign op_out_1_valid = ~op_out_fifo_1_empty; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + pushed_done_sticky_was_high <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + pushed_done_sticky_was_high <= 1'h0; + end + else if (clr_pushed_done_seg | clr_pushed_done_crd) begin + pushed_done_sticky_was_high <= 1'h0; + end + else if (set_pushed_done_seg | set_pushed_done_crd) begin + pushed_done_sticky_was_high <= 1'h1; + end + end +end +assign pushed_done_sticky_sticky = pushed_done_sticky_was_high; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + readout_loop_sticky_was_high <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + readout_loop_sticky_was_high <= 1'h0; + end + else if (clr_readout_loop_seg | clr_readout_loop_crd) begin + readout_loop_sticky_was_high <= 1'h0; + end + else if (set_readout_loop_seg | set_readout_loop_crd) begin + readout_loop_sticky_was_high <= 1'h1; + end + end +end +assign readout_loop_sticky_sticky = readout_loop_sticky_was_high; +assign seg_res_fifo_push_alloc_0 = seg_res_fifo_push_alloc & (~lookup); +assign seg_res_fifo_push_reserve_0 = rd_rsp_fifo_0_valid & (rd_rsp_fifo_0_out_data[16] == 1'h0) & (~block_mode) & + (~lookup); +assign seg_res_fifo_push_fill_0 = seg_res_fifo_push_fill & (~lookup); +assign seg_res_fifo_pop_0 = seg_res_fifo_pop & (~lookup); +assign crd_res_fifo_data_in_0 = lookup ? {1'h0, rd_rsp_fifo_0_out_data[15:0]}: block_mode ? rd_rsp_fifo_0_valid + ? {1'h0, rd_rsp_fifo_0_out_data[15:0]}: {1'h0, rd_rsp_fifo_1_out_data[15:0]}: + {1'h0, rd_rsp_fifo_1_out_data[15:0]}; +assign crd_res_fifo_fill_data_in = lookup ? seg_res_fifo_fill_data_in: dense ? crd_out_to_fifo: + seg_res_fifo_data_out_0; +assign crd_res_fifo_push_alloc_0 = lookup ? seg_res_fifo_push_alloc: crd_res_fifo_push_alloc; +assign crd_res_fifo_push_reserve_0 = rd_rsp_fifo_1_valid | (rd_rsp_fifo_0_valid & (block_mode | lookup)); +assign crd_res_fifo_push_fill_0 = lookup ? seg_res_fifo_push_fill: crd_res_fifo_push_fill; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + last_stop_token <= 17'h0; + end + else if (clk_en) begin + if (flush) begin + last_stop_token <= 17'h0; + end + else if (1'h0) begin + last_stop_token <= 17'h0; + end + else if (seg_in_start_state ? 1'h0: seg_res_fifo_push_fill & seg_res_fifo_push_alloc & (lookup ? ~crd_res_fifo_full: ~seg_res_fifo_full) & seg_res_fifo_fill_data_in[16] & (seg_res_fifo_fill_data_in[9:8] == 2'h0)) begin + last_stop_token <= seg_in_start_state ? input_fifo_data_out + 17'h1: seg_res_fifo_fill_data_in; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + use_data_sticky_was_high <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + use_data_sticky_was_high <= 1'h0; + end + else if (clr_used_data) begin + use_data_sticky_was_high <= 1'h0; + end + else if (infifo_valid_in & (~infifo_eos_in)) begin + use_data_sticky_was_high <= 1'h1; + end + end +end +assign use_data_sticky_sticky = use_data_sticky_was_high; +assign clr_used_data = 1'h0; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + valid_cnt <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + valid_cnt <= 16'h0; + end + else if (valid_rst) begin + valid_cnt <= 16'h0; + end + else if (valid_inc) begin + valid_cnt <= valid_cnt + 16'h1; + end + end +end +assign ptr_in = block_mode ? rd_rsp_fifo_0_valid ? rd_rsp_fifo_0_out_data[15:0]: + rd_rsp_fifo_1_out_data[15:0]: rd_rsp_fifo_0_out_data[15:0]; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + ptr_in_d1 <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + ptr_in_d1 <= 16'h0; + end + else if (1'h0) begin + ptr_in_d1 <= 16'h0; + end + else if (ptr_reg_en) begin + ptr_in_d1 <= ptr_in; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + fiber_addr_pre_d1 <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + fiber_addr_pre_d1 <= 16'h0; + end + else if (1'h0) begin + fiber_addr_pre_d1 <= 16'h0; + end + else if (1'h1) begin + fiber_addr_pre_d1 <= fiber_addr_pre; + end + end +end +assign seq_length_ptr_math = seg_res_fifo_data_out_1 - seg_res_fifo_data_out_0[15:0]; +assign pos_addr = root ? 16'h0: infifo_pos_in; +assign next_seq_addr = ptr_in_d1 + inner_dim_offset; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + seq_length <= 16'h0; + seq_addr <= 16'h0; + payload_ptr <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + seq_length <= 16'h0; + seq_addr <= 16'h0; + payload_ptr <= 16'h0; + end + else if (update_seq_state) begin + seq_length <= next_seq_length; + seq_addr <= next_seq_addr; + payload_ptr <= ptr_in_d1; + end + end +end +assign fiber_addr = fiber_addr_pre + seq_addr; +assign fifo_full = |fifo_full_pre; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + iter_finish_was_high <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + iter_finish_was_high <= 1'h0; + end + else if (clr_fiber_addr) begin + iter_finish_was_high <= 1'h0; + end + else if (last_valid_accepting) begin + iter_finish_was_high <= 1'h1; + end + end +end +assign iter_finish_sticky = last_valid_accepting | iter_finish_was_high; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + rep_finish_was_high <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + rep_finish_was_high <= 1'h0; + end + else if (clr_rep) begin + rep_finish_was_high <= 1'h0; + end + else if (((repeat_factor - 16'h1) == num_reps) & inc_rep) begin + rep_finish_was_high <= 1'h1; + end + end +end +assign rep_finish_sticky = (((repeat_factor - 16'h1) == num_reps) & inc_rep) | rep_finish_was_high; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + seen_root_eos_was_high <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + seen_root_eos_was_high <= 1'h0; + end + else if (clr_seen_root_eos) begin + seen_root_eos_was_high <= 1'h0; + end + else if (infifo_eos_in & (infifo_pos_in == 16'h0)) begin + seen_root_eos_was_high <= 1'h1; + end + end +end +assign seen_root_eos_sticky = (infifo_eos_in & (infifo_pos_in == 16'h0)) | seen_root_eos_was_high; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + rd_rsp_fifo_0_out_data_d1 <= 17'h0; + end + else if (clk_en) begin + if (flush) begin + rd_rsp_fifo_0_out_data_d1 <= 17'h0; + end + else if (1'h0) begin + rd_rsp_fifo_0_out_data_d1 <= 17'h0; + end + else if (en_reg_data_in) begin + rd_rsp_fifo_0_out_data_d1 <= rd_rsp_fifo_0_out_data; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + fiber_addr_pre_d1_d1 <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + fiber_addr_pre_d1_d1 <= 16'h0; + end + else if (1'h0) begin + fiber_addr_pre_d1_d1 <= 16'h0; + end + else if (en_reg_data_in) begin + fiber_addr_pre_d1_d1 <= fiber_addr_pre_d1; + end + end +end +assign done_in = infifo_eos_in & infifo_valid_in & (infifo_pos_in[9:8] == 2'h1); +assign eos_in = infifo_eos_in & infifo_valid_in & (infifo_pos_in[9:8] == 2'h0); +assign maybe_in = infifo_eos_in & infifo_valid_in & (infifo_pos_in[9:8] == 2'h2); + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + infifo_pos_in_d1 <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + infifo_pos_in_d1 <= 16'h0; + end + else if (1'h0) begin + infifo_pos_in_d1 <= 16'h0; + end + else if (infifo_pos_in_d1_en) begin + infifo_pos_in_d1 <= infifo_pos_in; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + num_req_made_seg <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + num_req_made_seg <= 16'h0; + end + else if (clr_req_made_seg) begin + num_req_made_seg <= 16'h0; + end + else if (inc_req_made_seg) begin + num_req_made_seg <= num_req_made_seg + 16'h1; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + num_req_rec_seg <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + num_req_rec_seg <= 16'h0; + end + else if (clr_req_rec_seg) begin + num_req_rec_seg <= 16'h0; + end + else if (inc_req_rec_seg) begin + num_req_rec_seg <= num_req_rec_seg + 16'h1; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + num_req_made_crd <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + num_req_made_crd <= 16'h0; + end + else if (clr_req_made_crd) begin + num_req_made_crd <= 16'h0; + end + else if (inc_req_made_crd) begin + num_req_made_crd <= num_req_made_crd + 16'h1; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + num_req_rec_crd <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + num_req_rec_crd <= 16'h0; + end + else if (clr_req_rec_crd) begin + num_req_rec_crd <= 16'h0; + end + else if (inc_req_rec_crd) begin + num_req_rec_crd <= num_req_rec_crd + 16'h1; + end + end +end +assign seg_res_fifo_done_out = seg_res_fifo_valid & seg_res_fifo_data_out_0[16] & (seg_res_fifo_data_out_0[9:8] + == 2'h1); +assign readout_dst_crd = readout_loop_sticky_sticky; +assign readout_dst_seg = readout_loop_sticky_sticky; +assign inc_requests_made_CRDDD_READ = |{crd_grant_push_0, crd_grant_push_1}; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + READS_MADE <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + READS_MADE <= 16'h0; + end + else if (inc_requests_made_CRDDD_READ) begin + READS_MADE <= READS_MADE + 16'h1; + end + end +end +assign inc_requests_REC_CRD_READ = rd_rsp_fifo_1_valid & (rd_rsp_fifo_1_out_data[16] == 1'h1); + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + READS_REC_CRD_READ <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + READS_REC_CRD_READ <= 16'h0; + end + else if (inc_requests_REC_CRD_READ) begin + READS_REC_CRD_READ <= READS_REC_CRD_READ + 16'h1; + end + end +end +assign coord_fifo_in_packed = crd_res_fifo_data_out; +assign S_level_0 = {1'h1, 16'h0}; +assign done_token = {1'h1, 7'h0, 1'h1, 8'h0}; +assign coord_out[16] = vr_fsm_state_init_blank_DONE ? done_token[16]: vr_fsm_state_init_blank_S0 ? + S_level_0[16]: coord_fifo_out_packed[16]; +assign coord_out[15:0] = vr_fsm_state_init_blank_DONE ? done_token[15:0]: vr_fsm_state_init_blank_S0 ? + S_level_0[15:0]: coord_fifo_out_packed[15:0]; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + final_pushed_done_sticky_was_high <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + final_pushed_done_sticky_was_high <= 1'h0; + end + else if (clr_final_pushed_done) begin + final_pushed_done_sticky_was_high <= 1'h0; + end + else if (set_final_pushed_done) begin + final_pushed_done_sticky_was_high <= 1'h1; + end + end +end +assign final_pushed_done_sticky_sticky = final_pushed_done_sticky_was_high; +assign set_final_pushed_done = 1'h0; +assign clr_final_pushed_done = 1'h0; +assign non_vr_coord_fifo_push = crd_res_fifo_valid & (~block_mode) & (~(crd_res_fifo_data_out[16] & + crd_res_fifo_valid & (crd_res_fifo_data_out[9:8] == 2'h3))); +assign coord_fifo_push = vector_reduce_mode ? non_vr_coord_fifo_push & (~output_row_fully_accumulated): + non_vr_coord_fifo_push; +assign coord_out_valid = vr_fsm_state_init_blank_S0 | vr_fsm_state_init_blank_DONE | + (~coordinate_fifo_empty); +assign fifo_full_pre[0] = coordinate_fifo_full; +assign crd_res_fifo_pop = (vector_reduce_mode & output_row_fully_accumulated) ? ~pos_fifo_full: block_mode + ? ~block_rd_fifo_full: ~coordinate_fifo_full; +assign pos_fifo_in_packed = vector_reduce_mode ? coord_fifo_in_packed: pos_out_to_fifo; +assign pos_out_fifo_push = vector_reduce_mode ? non_vr_coord_fifo_push & output_row_fully_accumulated: + non_vr_pos_out_fifo_push; +assign pos_out[16] = pos_fifo_out_packed[16]; +assign pos_out[15:0] = pos_fifo_out_packed[15:0]; +assign pos_out_valid_mux_sel = vector_reduce_mode & (pos_out == done_token); +assign pos_out_valid = ((~pos_out_valid_mux_sel) & (~pos_fifo_empty)) | (pos_out_valid_mux_sel & + output_matrix_fully_accumulated & (~pos_fifo_empty)); +assign fifo_full_pre[1] = pos_fifo_full; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + rs_has_prepped_ds_row_sticky_was_high <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + rs_has_prepped_ds_row_sticky_was_high <= 1'h0; + end + else if (vr_fsm_state_init_blank_S0) begin + rs_has_prepped_ds_row_sticky_was_high <= 1'h0; + end + else if ((pos_fifo_in_packed == done_token) & pos_out_fifo_push & (~fifo_full_pre[1])) begin + rs_has_prepped_ds_row_sticky_was_high <= 1'h1; + end + end +end +assign rs_has_prepped_ds_row_sticky_sticky = ((pos_fifo_in_packed == done_token) & pos_out_fifo_push & (~fifo_full_pre[1])) | + rs_has_prepped_ds_row_sticky_was_high; +assign rs_has_prepped_ds_row = rs_has_prepped_ds_row_sticky_sticky; +assign block_rd_fifo_push = crd_res_fifo_valid & block_mode & (~(crd_res_fifo_data_out[16] & + crd_res_fifo_valid & (crd_res_fifo_data_out[9:8] == 2'h3))); +assign block_rd_out_valid = ~block_rd_fifo_empty; + +always_ff @(posedge clk, negedge rst_n) begin + if (!rst_n) begin + scan_seq_crd_current_state <= START_CRD; + end + else if (clk_en) begin + if (flush) begin + scan_seq_crd_current_state <= START_CRD; + end + else scan_seq_crd_current_state <= scan_seq_crd_next_state; + end +end +always_comb begin + scan_seq_crd_next_state = scan_seq_crd_current_state; + unique case (scan_seq_crd_current_state) + BLOCK_1_RD: begin + if ((num_req_rec_crd == ptr_in_d1) & (~lookup)) begin + scan_seq_crd_next_state = BLOCK_2_SIZE_REQ; + end + else if ((num_req_rec_crd == ptr_in_d1) & lookup) begin + scan_seq_crd_next_state = FREE_CRD; + end + else scan_seq_crd_next_state = BLOCK_1_RD; + end + BLOCK_1_SIZE_REC: begin + if (rd_rsp_fifo_0_valid) begin + scan_seq_crd_next_state = BLOCK_1_RD; + end + else scan_seq_crd_next_state = BLOCK_1_SIZE_REC; + end + BLOCK_1_SIZE_REQ: begin + if (|{crd_grant_push_0, crd_grant_push_1}) begin + scan_seq_crd_next_state = BLOCK_1_SIZE_REC; + end + else scan_seq_crd_next_state = BLOCK_1_SIZE_REQ; + end + BLOCK_2_RD: begin + if (num_req_rec_crd == ptr_in_d1) begin + scan_seq_crd_next_state = FREE_CRD; + end + else scan_seq_crd_next_state = BLOCK_2_RD; + end + BLOCK_2_SIZE_REC: begin + if (rd_rsp_fifo_1_valid) begin + scan_seq_crd_next_state = BLOCK_2_RD; + end + else scan_seq_crd_next_state = BLOCK_2_SIZE_REC; + end + BLOCK_2_SIZE_REQ: begin + if (|{crd_grant_push_0, crd_grant_push_1}) begin + scan_seq_crd_next_state = BLOCK_2_SIZE_REC; + end + else scan_seq_crd_next_state = BLOCK_2_SIZE_REQ; + end + DENSE_STRM: scan_seq_crd_next_state = DENSE_STRM; + DONE_CRD: scan_seq_crd_next_state = START_CRD; + FREE_CRD: begin + if ((|{crd_grant_push_0, crd_grant_push_1}) & block_mode & (~lookup)) begin + scan_seq_crd_next_state = FREE_CRD2; + end + else if (|{crd_grant_push_0, crd_grant_push_1}) begin + scan_seq_crd_next_state = DONE_CRD; + end + else scan_seq_crd_next_state = FREE_CRD; + end + FREE_CRD2: begin + if (|{crd_grant_push_0, crd_grant_push_1}) begin + scan_seq_crd_next_state = DONE_CRD; + end + else scan_seq_crd_next_state = FREE_CRD2; + end + PASS_DONE_CRD: begin + if ((~crd_res_fifo_full) & (~pos_fifo_full)) begin + scan_seq_crd_next_state = DONE_CRD; + end + end + READOUT_SYNC_LOCK: scan_seq_crd_next_state = DONE_CRD; + SEQ_STRM: begin + if (seg_res_fifo_done_out & (~crd_res_fifo_full) & (~pos_fifo_full)) begin + scan_seq_crd_next_state = FREE_CRD; + end + end + START_CRD: begin + if (block_mode & tile_en) begin + scan_seq_crd_next_state = BLOCK_1_SIZE_REQ; + end + else if (dense & (~lookup) & tile_en) begin + scan_seq_crd_next_state = DENSE_STRM; + end + else if ((~dense) & (~lookup) & tile_en) begin + scan_seq_crd_next_state = SEQ_STRM; + end + end + default: scan_seq_crd_next_state = scan_seq_crd_current_state; + endcase +end +always_comb begin + unique case (scan_seq_crd_current_state) + BLOCK_1_RD: begin :scan_seq_crd_BLOCK_1_RD_Output + crd_addr_out_to_fifo = num_req_made_crd; + crd_op_out_to_fifo = 16'h1; + crd_ID_out_to_fifo = 16'h0; + crd_req_push = (num_req_made_crd < ptr_in_d1) & (~crd_res_fifo_full); + crd_rd_rsp_fifo_pop = num_req_rec_crd < ptr_in_d1; + non_vr_pos_out_fifo_push = 1'h0; + crd_pop_infifo = 1'h0; + en_reg_data_in = 1'h0; + pos_out_to_fifo = 17'h0; + crd_out_to_fifo = 17'h0; + inc_req_made_crd = (num_req_made_crd < ptr_in_d1) & (|{crd_grant_push_0, crd_grant_push_1}) & + (~crd_res_fifo_full); + clr_req_made_crd = 1'h0; + inc_req_rec_crd = (num_req_rec_crd < ptr_in_d1) & rd_rsp_fifo_0_valid; + clr_req_rec_crd = 1'h0; + crd_res_fifo_push_alloc = (num_req_made_crd < ptr_in_d1) & (|{crd_grant_push_0, crd_grant_push_1}) & + (~crd_res_fifo_full); + crd_res_fifo_push_fill = 1'h0; + ptr_reg_en = 1'h0; + seg_res_fifo_pop = 1'h0; + set_readout_loop_crd = 1'h0; + set_pushed_done_crd = 1'h0; + clr_readout_loop_crd = 1'h0; + crd_in_done_state = 1'h0; + clr_pushed_done_crd = 1'h0; + end :scan_seq_crd_BLOCK_1_RD_Output + BLOCK_1_SIZE_REC: begin :scan_seq_crd_BLOCK_1_SIZE_REC_Output + crd_addr_out_to_fifo = 16'h0; + crd_op_out_to_fifo = 16'h0; + crd_ID_out_to_fifo = 16'h0; + crd_req_push = 1'h0; + crd_rd_rsp_fifo_pop = 1'h1; + non_vr_pos_out_fifo_push = 1'h0; + crd_pop_infifo = 1'h0; + en_reg_data_in = 1'h0; + pos_out_to_fifo = 17'h0; + crd_out_to_fifo = 17'h0; + inc_req_made_crd = 1'h0; + clr_req_made_crd = 1'h1; + inc_req_rec_crd = 1'h0; + clr_req_rec_crd = 1'h0; + crd_res_fifo_push_alloc = 1'h0; + crd_res_fifo_push_fill = 1'h0; + ptr_reg_en = rd_rsp_fifo_0_valid; + seg_res_fifo_pop = 1'h0; + set_readout_loop_crd = 1'h0; + set_pushed_done_crd = 1'h0; + clr_readout_loop_crd = 1'h0; + crd_in_done_state = 1'h0; + clr_pushed_done_crd = 1'h0; + end :scan_seq_crd_BLOCK_1_SIZE_REC_Output + BLOCK_1_SIZE_REQ: begin :scan_seq_crd_BLOCK_1_SIZE_REQ_Output + crd_addr_out_to_fifo = 16'h0; + crd_op_out_to_fifo = 16'h2; + crd_ID_out_to_fifo = 16'h0; + crd_req_push = ~crd_res_fifo_full; + crd_rd_rsp_fifo_pop = 1'h0; + non_vr_pos_out_fifo_push = 1'h0; + crd_pop_infifo = 1'h0; + en_reg_data_in = 1'h0; + pos_out_to_fifo = 17'h0; + crd_out_to_fifo = 17'h0; + inc_req_made_crd = 1'h0; + clr_req_made_crd = 1'h0; + inc_req_rec_crd = 1'h0; + clr_req_rec_crd = 1'h0; + crd_res_fifo_push_alloc = (~crd_res_fifo_full) & (|{crd_grant_push_0, crd_grant_push_1}); + crd_res_fifo_push_fill = 1'h0; + ptr_reg_en = 1'h0; + seg_res_fifo_pop = 1'h0; + set_readout_loop_crd = 1'h0; + set_pushed_done_crd = 1'h0; + clr_readout_loop_crd = 1'h0; + crd_in_done_state = 1'h0; + clr_pushed_done_crd = 1'h0; + end :scan_seq_crd_BLOCK_1_SIZE_REQ_Output + BLOCK_2_RD: begin :scan_seq_crd_BLOCK_2_RD_Output + crd_addr_out_to_fifo = num_req_made_crd; + crd_op_out_to_fifo = 16'h1; + crd_ID_out_to_fifo = 16'h1; + crd_req_push = (num_req_made_crd < ptr_in_d1) & (~crd_res_fifo_full); + crd_rd_rsp_fifo_pop = num_req_rec_crd < ptr_in_d1; + non_vr_pos_out_fifo_push = 1'h0; + crd_pop_infifo = 1'h0; + en_reg_data_in = 1'h0; + pos_out_to_fifo = 17'h0; + crd_out_to_fifo = 17'h0; + inc_req_made_crd = (num_req_made_crd < ptr_in_d1) & (|{crd_grant_push_0, crd_grant_push_1}) & + (~crd_res_fifo_full); + clr_req_made_crd = 1'h0; + inc_req_rec_crd = (num_req_rec_crd < ptr_in_d1) & rd_rsp_fifo_1_valid; + clr_req_rec_crd = 1'h0; + crd_res_fifo_push_alloc = (num_req_made_crd < ptr_in_d1) & (|{crd_grant_push_0, crd_grant_push_1}) & + (~crd_res_fifo_full); + crd_res_fifo_push_fill = 1'h0; + ptr_reg_en = 1'h0; + seg_res_fifo_pop = 1'h0; + set_readout_loop_crd = 1'h0; + set_pushed_done_crd = 1'h0; + clr_readout_loop_crd = 1'h0; + crd_in_done_state = 1'h0; + clr_pushed_done_crd = 1'h0; + end :scan_seq_crd_BLOCK_2_RD_Output + BLOCK_2_SIZE_REC: begin :scan_seq_crd_BLOCK_2_SIZE_REC_Output + crd_addr_out_to_fifo = 16'h0; + crd_op_out_to_fifo = 16'h0; + crd_ID_out_to_fifo = 16'h0; + crd_req_push = 1'h0; + crd_rd_rsp_fifo_pop = 1'h1; + non_vr_pos_out_fifo_push = 1'h0; + crd_pop_infifo = 1'h0; + en_reg_data_in = 1'h0; + pos_out_to_fifo = 17'h0; + crd_out_to_fifo = 17'h0; + inc_req_made_crd = 1'h0; + clr_req_made_crd = 1'h1; + inc_req_rec_crd = 1'h0; + clr_req_rec_crd = 1'h1; + crd_res_fifo_push_alloc = 1'h0; + crd_res_fifo_push_fill = 1'h0; + ptr_reg_en = rd_rsp_fifo_1_valid; + seg_res_fifo_pop = 1'h0; + set_readout_loop_crd = 1'h0; + set_pushed_done_crd = 1'h0; + clr_readout_loop_crd = 1'h0; + crd_in_done_state = 1'h0; + clr_pushed_done_crd = 1'h0; + end :scan_seq_crd_BLOCK_2_SIZE_REC_Output + BLOCK_2_SIZE_REQ: begin :scan_seq_crd_BLOCK_2_SIZE_REQ_Output + crd_addr_out_to_fifo = 16'h0; + crd_op_out_to_fifo = 16'h2; + crd_ID_out_to_fifo = 16'h1; + crd_req_push = ~crd_res_fifo_full; + crd_rd_rsp_fifo_pop = 1'h0; + non_vr_pos_out_fifo_push = 1'h0; + crd_pop_infifo = 1'h0; + en_reg_data_in = 1'h0; + pos_out_to_fifo = 17'h0; + crd_out_to_fifo = 17'h0; + inc_req_made_crd = 1'h0; + clr_req_made_crd = 1'h0; + inc_req_rec_crd = 1'h0; + clr_req_rec_crd = 1'h0; + crd_res_fifo_push_alloc = (~crd_res_fifo_full) & (|{crd_grant_push_0, crd_grant_push_1}); + crd_res_fifo_push_fill = 1'h0; + ptr_reg_en = 1'h0; + seg_res_fifo_pop = 1'h0; + set_readout_loop_crd = 1'h0; + set_pushed_done_crd = 1'h0; + clr_readout_loop_crd = 1'h0; + crd_in_done_state = 1'h0; + clr_pushed_done_crd = 1'h0; + end :scan_seq_crd_BLOCK_2_SIZE_REQ_Output + DENSE_STRM: begin :scan_seq_crd_DENSE_STRM_Output + crd_addr_out_to_fifo = 16'h0; + crd_op_out_to_fifo = 16'h0; + crd_ID_out_to_fifo = 16'h0; + crd_req_push = 1'h0; + crd_rd_rsp_fifo_pop = 1'h0; + non_vr_pos_out_fifo_push = seg_res_fifo_valid & (~pos_fifo_full) & (~crd_res_fifo_full) & + (seg_res_fifo_data_out_0[16] ? 1'h1: dim_size > num_req_made_crd); + crd_pop_infifo = 1'h0; + en_reg_data_in = 1'h0; + pos_out_to_fifo = seg_res_fifo_data_out_0[16] ? seg_res_fifo_data_out_0: + 17'((seg_res_fifo_data_out_0[15:0] * dim_size) + num_req_made_crd); + crd_out_to_fifo = seg_res_fifo_data_out_0[16] ? seg_res_fifo_data_out_0: 17'(num_req_made_crd); + inc_req_made_crd = seg_res_fifo_valid & (dim_size > num_req_made_crd) & + (~seg_res_fifo_data_out_0[16]) & (~pos_fifo_full) & (~crd_res_fifo_full); + clr_req_made_crd = seg_res_fifo_valid & seg_res_fifo_data_out_0[16]; + inc_req_rec_crd = 1'h0; + clr_req_rec_crd = 1'h0; + crd_res_fifo_push_alloc = seg_res_fifo_valid & (~pos_fifo_full) & (~crd_res_fifo_full) & + (seg_res_fifo_data_out_0[16] ? 1'h1: dim_size > num_req_made_crd); + crd_res_fifo_push_fill = seg_res_fifo_valid & (~pos_fifo_full) & (~crd_res_fifo_full) & + (seg_res_fifo_data_out_0[16] ? 1'h1: dim_size > num_req_made_crd); + ptr_reg_en = 1'h0; + seg_res_fifo_pop = seg_res_fifo_valid & (~pos_fifo_full) & (~crd_res_fifo_full) & + (seg_res_fifo_data_out_0[16] ? 1'h1: ((dim_size - 16'h1) == num_req_made_crd) & + inc_req_made_crd); + set_readout_loop_crd = 1'h0; + set_pushed_done_crd = 1'h0; + clr_readout_loop_crd = 1'h0; + crd_in_done_state = 1'h0; + clr_pushed_done_crd = 1'h0; + end :scan_seq_crd_DENSE_STRM_Output + DONE_CRD: begin :scan_seq_crd_DONE_CRD_Output + crd_addr_out_to_fifo = 16'h0; + crd_op_out_to_fifo = 16'h0; + crd_ID_out_to_fifo = 16'h0; + crd_req_push = 1'h0; + crd_rd_rsp_fifo_pop = 1'h0; + non_vr_pos_out_fifo_push = 1'h0; + crd_pop_infifo = 1'h0; + en_reg_data_in = 1'h0; + pos_out_to_fifo = 17'h0; + crd_out_to_fifo = 17'h0; + inc_req_made_crd = 1'h0; + clr_req_made_crd = 1'h1; + inc_req_rec_crd = 1'h0; + clr_req_rec_crd = 1'h1; + crd_res_fifo_push_alloc = 1'h0; + crd_res_fifo_push_fill = 1'h0; + ptr_reg_en = 1'h0; + seg_res_fifo_pop = 1'h0; + crd_in_done_state = 1'h1; + set_readout_loop_crd = 1'h0; + set_pushed_done_crd = 1'h0; + clr_readout_loop_crd = 1'h0; + clr_pushed_done_crd = 1'h0; + end :scan_seq_crd_DONE_CRD_Output + FREE_CRD: begin :scan_seq_crd_FREE_CRD_Output + crd_addr_out_to_fifo = 16'h0; + crd_op_out_to_fifo = 16'h0; + crd_ID_out_to_fifo = block_mode ? 16'h0: 16'h1; + crd_req_push = 1'h1; + crd_rd_rsp_fifo_pop = 1'h0; + non_vr_pos_out_fifo_push = 1'h0; + crd_pop_infifo = 1'h0; + en_reg_data_in = 1'h0; + pos_out_to_fifo = 17'h0; + crd_out_to_fifo = 17'h0; + inc_req_made_crd = 1'h0; + clr_req_made_crd = 1'h1; + inc_req_rec_crd = 1'h0; + clr_req_rec_crd = 1'h1; + crd_res_fifo_push_alloc = 1'h0; + crd_res_fifo_push_fill = 1'h0; + ptr_reg_en = 1'h0; + seg_res_fifo_pop = 1'h0; + set_readout_loop_crd = 1'h0; + set_pushed_done_crd = 1'h0; + clr_readout_loop_crd = 1'h0; + crd_in_done_state = 1'h0; + clr_pushed_done_crd = 1'h0; + end :scan_seq_crd_FREE_CRD_Output + FREE_CRD2: begin :scan_seq_crd_FREE_CRD2_Output + crd_addr_out_to_fifo = 16'h0; + crd_op_out_to_fifo = 16'h0; + crd_ID_out_to_fifo = 16'h1; + crd_req_push = 1'h1; + crd_rd_rsp_fifo_pop = 1'h0; + non_vr_pos_out_fifo_push = 1'h0; + crd_pop_infifo = 1'h0; + en_reg_data_in = 1'h0; + pos_out_to_fifo = 17'h0; + crd_out_to_fifo = 17'h0; + inc_req_made_crd = 1'h0; + clr_req_made_crd = 1'h1; + inc_req_rec_crd = 1'h0; + clr_req_rec_crd = 1'h1; + crd_res_fifo_push_alloc = 1'h0; + crd_res_fifo_push_fill = 1'h0; + ptr_reg_en = 1'h0; + seg_res_fifo_pop = 1'h0; + set_readout_loop_crd = 1'h0; + set_pushed_done_crd = 1'h0; + clr_readout_loop_crd = 1'h0; + crd_in_done_state = 1'h0; + clr_pushed_done_crd = 1'h0; + end :scan_seq_crd_FREE_CRD2_Output + PASS_DONE_CRD: begin :scan_seq_crd_PASS_DONE_CRD_Output + crd_addr_out_to_fifo = 16'h0; + crd_op_out_to_fifo = 16'h0; + crd_ID_out_to_fifo = 16'h0; + crd_req_push = 1'h0; + crd_rd_rsp_fifo_pop = 1'h0; + non_vr_pos_out_fifo_push = (~pos_fifo_full) & (~crd_res_fifo_full) & seg_res_fifo_done_out & + seg_res_fifo_valid; + crd_pop_infifo = 1'h0; + en_reg_data_in = 1'h0; + pos_out_to_fifo = {1'h1, 6'h0, 2'h1, 8'h0}; + crd_out_to_fifo = 17'h0; + inc_req_made_crd = 1'h0; + clr_req_made_crd = 1'h0; + inc_req_rec_crd = 1'h0; + clr_req_rec_crd = 1'h0; + crd_res_fifo_push_alloc = (~pos_fifo_full) & (~crd_res_fifo_full) & seg_res_fifo_done_out & + seg_res_fifo_valid; + crd_res_fifo_push_fill = (~pos_fifo_full) & (~crd_res_fifo_full) & seg_res_fifo_done_out & + seg_res_fifo_valid; + ptr_reg_en = 1'h0; + seg_res_fifo_pop = (~pos_fifo_full) & (~crd_res_fifo_full) & seg_res_fifo_done_out & + seg_res_fifo_valid; + clr_pushed_done_crd = 1'h0; + clr_readout_loop_crd = 1'h0; + set_readout_loop_crd = 1'h0; + set_pushed_done_crd = 1'h0; + crd_in_done_state = 1'h0; + end :scan_seq_crd_PASS_DONE_CRD_Output + READOUT_SYNC_LOCK: begin :scan_seq_crd_READOUT_SYNC_LOCK_Output + crd_addr_out_to_fifo = 16'h0; + crd_op_out_to_fifo = 16'h0; + crd_ID_out_to_fifo = 16'h0; + crd_req_push = 1'h0; + crd_rd_rsp_fifo_pop = 1'h0; + non_vr_pos_out_fifo_push = 1'h0; + crd_pop_infifo = 1'h0; + en_reg_data_in = 1'h0; + pos_out_to_fifo = 17'h0; + crd_out_to_fifo = 17'h0; + inc_req_made_crd = 1'h0; + clr_req_made_crd = 1'h0; + inc_req_rec_crd = 1'h0; + clr_req_rec_crd = 1'h0; + crd_res_fifo_push_alloc = 1'h0; + crd_res_fifo_push_fill = 1'h0; + ptr_reg_en = 1'h0; + seg_res_fifo_pop = 1'h0; + clr_pushed_done_crd = 1'h1; + clr_readout_loop_crd = 1'h1; + set_readout_loop_crd = 1'h0; + set_pushed_done_crd = 1'h0; + crd_in_done_state = 1'h0; + end :scan_seq_crd_READOUT_SYNC_LOCK_Output + SEQ_STRM: begin :scan_seq_crd_SEQ_STRM_Output + crd_addr_out_to_fifo = num_req_made_crd + seg_res_fifo_data_out_0[15:0]; + crd_op_out_to_fifo = 16'h1; + crd_ID_out_to_fifo = 16'h1; + crd_req_push = seg_res_fifo_valid & (~seg_res_fifo_data_out_0[16]) & (~crd_res_fifo_full) & + (num_req_made_crd < seq_length_ptr_math) & (~pos_fifo_full); + crd_rd_rsp_fifo_pop = 1'h1; + non_vr_pos_out_fifo_push = seg_res_fifo_data_out_0[16] ? (~pos_fifo_full) & (~crd_res_fifo_full) & + seg_res_fifo_valid: (|{crd_grant_push_0, crd_grant_push_1}) & (num_req_made_crd + < seq_length_ptr_math) & (~pos_fifo_full) & (~crd_res_fifo_full) & + seg_res_fifo_valid; + crd_pop_infifo = 1'h0; + en_reg_data_in = 1'h0; + pos_out_to_fifo = seg_res_fifo_data_out_0[16] ? seg_res_fifo_data_out_0: {1'h0, num_req_made_crd + + seg_res_fifo_data_out_0[15:0]}; + crd_out_to_fifo = 17'h0; + inc_req_made_crd = (|{crd_grant_push_0, crd_grant_push_1}) & (num_req_made_crd < + seq_length_ptr_math) & (~pos_fifo_full) & (~crd_res_fifo_full) & + seg_res_fifo_valid; + clr_req_made_crd = (((|{crd_grant_push_0, crd_grant_push_1}) & ((seq_length_ptr_math - 16'h1) == + num_req_made_crd)) | (seq_length_ptr_math == 16'h0)) & (~pos_fifo_full) & + (~crd_res_fifo_full) & seg_res_fifo_valid; + inc_req_rec_crd = 1'h0; + clr_req_rec_crd = 1'h0; + crd_res_fifo_push_alloc = seg_res_fifo_data_out_0[16] ? (~pos_fifo_full) & (~crd_res_fifo_full) & + seg_res_fifo_valid: (|{crd_grant_push_0, crd_grant_push_1}) & (num_req_made_crd + < seq_length_ptr_math) & (~pos_fifo_full) & (~crd_res_fifo_full) & + seg_res_fifo_valid; + crd_res_fifo_push_fill = seg_res_fifo_valid & seg_res_fifo_data_out_0[16] & (~pos_fifo_full) & + (~crd_res_fifo_full); + ptr_reg_en = 1'h0; + seg_res_fifo_pop = clr_req_made_crd | (seg_res_fifo_valid & seg_res_fifo_data_out_0[16] & + (~pos_fifo_full) & (~crd_res_fifo_full)); + set_readout_loop_crd = 1'h0; + set_pushed_done_crd = 1'h0; + clr_readout_loop_crd = 1'h0; + crd_in_done_state = 1'h0; + clr_pushed_done_crd = 1'h0; + end :scan_seq_crd_SEQ_STRM_Output + START_CRD: begin :scan_seq_crd_START_CRD_Output + crd_addr_out_to_fifo = 16'h0; + crd_op_out_to_fifo = 16'h0; + crd_ID_out_to_fifo = 16'h0; + crd_req_push = 1'h0; + crd_rd_rsp_fifo_pop = 1'h0; + non_vr_pos_out_fifo_push = 1'h0; + crd_pop_infifo = 1'h0; + en_reg_data_in = 1'h0; + pos_out_to_fifo = 17'h0; + crd_out_to_fifo = 17'h0; + inc_req_made_crd = 1'h0; + clr_req_made_crd = 1'h0; + inc_req_rec_crd = 1'h0; + clr_req_rec_crd = 1'h0; + crd_res_fifo_push_alloc = 1'h0; + crd_res_fifo_push_fill = 1'h0; + ptr_reg_en = 1'h0; + seg_res_fifo_pop = 1'h0; + set_readout_loop_crd = 1'h0; + set_pushed_done_crd = 1'h0; + clr_readout_loop_crd = 1'h0; + crd_in_done_state = 1'h0; + clr_pushed_done_crd = 1'h0; + end :scan_seq_crd_START_CRD_Output + default: begin :scan_seq_crd_default_Output + crd_addr_out_to_fifo = 16'h0; + crd_op_out_to_fifo = 16'h0; + crd_ID_out_to_fifo = 16'h0; + crd_req_push = 1'h0; + crd_rd_rsp_fifo_pop = 1'h0; + non_vr_pos_out_fifo_push = 1'h0; + crd_pop_infifo = 1'h0; + en_reg_data_in = 1'h0; + pos_out_to_fifo = 17'h0; + crd_out_to_fifo = 17'h0; + inc_req_made_crd = 1'h0; + clr_req_made_crd = 1'h0; + inc_req_rec_crd = 1'h0; + clr_req_rec_crd = 1'h0; + crd_res_fifo_push_alloc = 1'h0; + crd_res_fifo_push_fill = 1'h0; + ptr_reg_en = 1'h0; + seg_res_fifo_pop = 1'h0; + set_readout_loop_crd = 1'h0; + set_pushed_done_crd = 1'h0; + clr_readout_loop_crd = 1'h0; + crd_in_done_state = 1'h0; + clr_pushed_done_crd = 1'h0; + end :scan_seq_crd_default_Output + endcase +end + +always_ff @(posedge clk, negedge rst_n) begin + if (!rst_n) begin + scan_seq_seg_current_state <= START_SEG; + end + else if (clk_en) begin + if (flush) begin + scan_seq_seg_current_state <= START_SEG; + end + else scan_seq_seg_current_state <= scan_seq_seg_next_state; + end +end +always_comb begin + scan_seq_seg_next_state = scan_seq_seg_current_state; + unique case (scan_seq_seg_current_state) + DONE_SEG: begin + if (lookup ? 1'h1: (~dense) & crd_in_done_state) begin + scan_seq_seg_next_state = START_SEG; + end + end + FREE_SEG: begin + if (|{seg_grant_push_0, seg_grant_push_1}) begin + scan_seq_seg_next_state = DONE_SEG; + end + end + INJECT_0: scan_seq_seg_next_state = INJECT_DONE; + INJECT_DONE: scan_seq_seg_next_state = READ; + INJECT_ROUTING: begin + if (~seg_res_fifo_full) begin + scan_seq_seg_next_state = READ; + end + end + LOOKUP: begin + if (done_in & (~crd_res_fifo_full)) begin + scan_seq_seg_next_state = FREE_SEG; + end + else scan_seq_seg_next_state = LOOKUP; + end + PASS_DONE_SEG: scan_seq_seg_next_state = FREE_SEG; + PASS_STOP_SEG: begin + if (readout_loop_sticky_sticky & (~seg_res_fifo_full)) begin + scan_seq_seg_next_state = PASS_DONE_SEG; + end + else if (infifo_valid_in & (~lookup) & (~seg_res_fifo_full)) begin + scan_seq_seg_next_state = READ; + end + else scan_seq_seg_next_state = PASS_STOP_SEG; + end + READ: begin + if (maybe_in | (dense & (~done_in) & (~seg_res_fifo_full) & infifo_valid_in) | ((~dense) & eos_in)) begin + scan_seq_seg_next_state = PASS_STOP_SEG; + end + else if ((|{seg_grant_push_0, seg_grant_push_1}) & (~seg_res_fifo_full)) begin + scan_seq_seg_next_state = READ_ALT; + end + else if (done_in & (~seg_res_fifo_full)) begin + scan_seq_seg_next_state = FREE_SEG; + end + else scan_seq_seg_next_state = READ; + end + READ_ALT: begin + if ((|{seg_grant_push_0, seg_grant_push_1}) & (~seg_res_fifo_full) & infifo_valid_in) begin + scan_seq_seg_next_state = READ; + end + else if ((|{seg_grant_push_0, seg_grant_push_1}) & (~seg_res_fifo_full)) begin + scan_seq_seg_next_state = PASS_STOP_SEG; + end + else scan_seq_seg_next_state = READ_ALT; + end + START_SEG: begin + if (block_mode) begin + scan_seq_seg_next_state = START_SEG; + end + else if ((~root) & (~lookup) & (~block_mode) & tile_en) begin + scan_seq_seg_next_state = READ; + end + else if (root & (~lookup) & (~block_mode) & tile_en) begin + scan_seq_seg_next_state = INJECT_0; + end + else if ((~root) & lookup & (~block_mode) & tile_en) begin + scan_seq_seg_next_state = LOOKUP; + end + end + default: scan_seq_seg_next_state = scan_seq_seg_current_state; + endcase +end +always_comb begin + unique case (scan_seq_seg_current_state) + DONE_SEG: begin :scan_seq_seg_DONE_SEG_Output + seg_addr_out_to_fifo = 16'h0; + seg_op_out_to_fifo = 16'h0; + seg_ID_out_to_fifo = 16'h0; + seg_req_push = 1'h0; + seg_rd_rsp_fifo_pop = 1'h1; + seg_pop_infifo = 1'h0; + inc_req_made_seg = 1'h0; + clr_req_made_seg = 1'h0; + inc_req_rec_seg = 1'h0; + clr_req_rec_seg = 1'h0; + us_fifo_inject_data = 16'h0; + us_fifo_inject_eos = 1'h0; + us_fifo_inject_push = 1'h0; + seg_res_fifo_push_alloc = 1'h0; + seg_res_fifo_push_fill = 1'h0; + seg_res_fifo_fill_data_in = 17'h0; + set_readout_loop_seg = 1'h0; + clr_readout_loop_seg = 1'h0; + seg_in_done_state = 1'h1; + infifo_pos_in_d1_en = 1'h0; + clr_pushed_done_seg = 1'h0; + set_pushed_done_seg = 1'h0; + seg_in_start_state = 1'h0; + end :scan_seq_seg_DONE_SEG_Output + FREE_SEG: begin :scan_seq_seg_FREE_SEG_Output + seg_addr_out_to_fifo = 16'h0; + seg_op_out_to_fifo = 16'h0; + seg_ID_out_to_fifo = 16'h0; + seg_req_push = 1'h1; + seg_rd_rsp_fifo_pop = 1'h1; + seg_pop_infifo = 1'h0; + inc_req_made_seg = 1'h0; + clr_req_made_seg = 1'h0; + inc_req_rec_seg = 1'h0; + clr_req_rec_seg = 1'h0; + us_fifo_inject_data = 16'h0; + us_fifo_inject_eos = 1'h0; + us_fifo_inject_push = 1'h0; + seg_res_fifo_push_alloc = 1'h0; + seg_res_fifo_push_fill = 1'h0; + seg_res_fifo_fill_data_in = 17'h0; + infifo_pos_in_d1_en = 1'h0; + clr_pushed_done_seg = 1'h0; + set_pushed_done_seg = 1'h0; + seg_in_done_state = 1'h0; + seg_in_start_state = 1'h0; + set_readout_loop_seg = 1'h0; + clr_readout_loop_seg = 1'h0; + end :scan_seq_seg_FREE_SEG_Output + INJECT_0: begin :scan_seq_seg_INJECT_0_Output + seg_addr_out_to_fifo = 16'h0; + seg_op_out_to_fifo = 16'h0; + seg_ID_out_to_fifo = 16'h0; + seg_req_push = 1'h0; + seg_rd_rsp_fifo_pop = 1'h0; + seg_pop_infifo = 1'h0; + inc_req_made_seg = 1'h0; + clr_req_made_seg = 1'h0; + inc_req_rec_seg = 1'h0; + clr_req_rec_seg = 1'h0; + us_fifo_inject_data = 16'h0; + us_fifo_inject_eos = 1'h0; + us_fifo_inject_push = 1'h1; + seg_res_fifo_push_alloc = 1'h0; + seg_res_fifo_push_fill = 1'h0; + seg_res_fifo_fill_data_in = 17'h0; + infifo_pos_in_d1_en = 1'h0; + clr_pushed_done_seg = 1'h0; + set_pushed_done_seg = 1'h0; + seg_in_done_state = 1'h0; + seg_in_start_state = 1'h0; + set_readout_loop_seg = 1'h0; + clr_readout_loop_seg = 1'h0; + end :scan_seq_seg_INJECT_0_Output + INJECT_DONE: begin :scan_seq_seg_INJECT_DONE_Output + seg_addr_out_to_fifo = 16'h0; + seg_op_out_to_fifo = 16'h0; + seg_ID_out_to_fifo = 16'h0; + seg_req_push = 1'h0; + seg_rd_rsp_fifo_pop = 1'h0; + seg_pop_infifo = 1'h0; + inc_req_made_seg = 1'h0; + clr_req_made_seg = 1'h0; + inc_req_rec_seg = 1'h0; + clr_req_rec_seg = 1'h0; + us_fifo_inject_data = 16'h100; + us_fifo_inject_eos = 1'h1; + us_fifo_inject_push = 1'h1; + seg_res_fifo_push_alloc = 1'h0; + seg_res_fifo_push_fill = 1'h0; + seg_res_fifo_fill_data_in = 17'h0; + infifo_pos_in_d1_en = 1'h0; + clr_pushed_done_seg = 1'h0; + set_pushed_done_seg = 1'h0; + seg_in_done_state = 1'h0; + seg_in_start_state = 1'h0; + set_readout_loop_seg = 1'h0; + clr_readout_loop_seg = 1'h0; + end :scan_seq_seg_INJECT_DONE_Output + INJECT_ROUTING: begin :scan_seq_seg_INJECT_ROUTING_Output + seg_addr_out_to_fifo = 16'h0; + seg_op_out_to_fifo = 16'h0; + seg_ID_out_to_fifo = 16'h0; + seg_req_push = 1'h0; + seg_rd_rsp_fifo_pop = 1'h0; + seg_pop_infifo = 1'h0; + inc_req_made_seg = 1'h0; + clr_req_made_seg = 1'h0; + inc_req_rec_seg = 1'h0; + clr_req_rec_seg = 1'h0; + us_fifo_inject_data = 16'h0; + us_fifo_inject_eos = 1'h0; + us_fifo_inject_push = 1'h1; + seg_res_fifo_push_alloc = ~seg_res_fifo_full; + seg_res_fifo_push_fill = ~seg_res_fifo_full; + seg_res_fifo_fill_data_in = {1'h1, 6'h0, 2'h3, 7'h0, readout_loop_sticky_sticky}; + infifo_pos_in_d1_en = 1'h0; + clr_pushed_done_seg = 1'h0; + set_pushed_done_seg = 1'h0; + seg_in_done_state = 1'h0; + seg_in_start_state = 1'h0; + set_readout_loop_seg = 1'h0; + clr_readout_loop_seg = 1'h0; + end :scan_seq_seg_INJECT_ROUTING_Output + LOOKUP: begin :scan_seq_seg_LOOKUP_Output + seg_addr_out_to_fifo = infifo_pos_in; + seg_op_out_to_fifo = 16'h1; + seg_ID_out_to_fifo = 16'h0; + seg_req_push = infifo_valid_in & (~infifo_eos_in) & (~crd_res_fifo_full); + seg_rd_rsp_fifo_pop = 1'h1; + seg_pop_infifo = infifo_valid_in & (~crd_res_fifo_full) & (infifo_eos_in ? 1'h1: + |{seg_grant_push_0, seg_grant_push_1}); + inc_req_made_seg = 1'h0; + clr_req_made_seg = 1'h1; + inc_req_rec_seg = 1'h0; + clr_req_rec_seg = 1'h1; + us_fifo_inject_data = 16'h0; + us_fifo_inject_eos = 1'h0; + us_fifo_inject_push = 1'h0; + seg_res_fifo_push_alloc = (~crd_res_fifo_full) & ((|{seg_grant_push_0, seg_grant_push_1}) | + (infifo_valid_in & infifo_eos_in)); + seg_res_fifo_push_fill = infifo_valid_in & infifo_eos_in & (~crd_res_fifo_full); + seg_res_fifo_fill_data_in = (infifo_eos_in & (infifo_pos_in[9:8] == 2'h2)) ? 17'h0: {infifo_eos_in, + infifo_pos_in}; + set_pushed_done_seg = 1'h0; + set_readout_loop_seg = 1'h0; + infifo_pos_in_d1_en = 1'h0; + clr_pushed_done_seg = 1'h0; + seg_in_done_state = 1'h0; + seg_in_start_state = 1'h0; + clr_readout_loop_seg = 1'h0; + end :scan_seq_seg_LOOKUP_Output + PASS_DONE_SEG: begin :scan_seq_seg_PASS_DONE_SEG_Output + seg_addr_out_to_fifo = 16'h0; + seg_op_out_to_fifo = 16'h0; + seg_ID_out_to_fifo = 16'h0; + seg_req_push = 1'h0; + seg_rd_rsp_fifo_pop = 1'h1; + seg_pop_infifo = (~readout_loop_sticky_sticky) & done_in & (~seg_res_fifo_full); + inc_req_made_seg = 1'h0; + clr_req_made_seg = 1'h0; + inc_req_rec_seg = 1'h0; + clr_req_rec_seg = 1'h0; + us_fifo_inject_data = 16'h0; + us_fifo_inject_eos = 1'h0; + us_fifo_inject_push = 1'h0; + seg_res_fifo_push_alloc = readout_loop_sticky_sticky & pushed_done_sticky_sticky & (~seg_res_fifo_full); + seg_res_fifo_push_fill = readout_loop_sticky_sticky & pushed_done_sticky_sticky & (~seg_res_fifo_full); + seg_res_fifo_fill_data_in = {1'h1, 6'h0, 2'h1, 8'h0}; + set_pushed_done_seg = 1'h0; + infifo_pos_in_d1_en = 1'h0; + clr_pushed_done_seg = 1'h0; + seg_in_done_state = 1'h0; + seg_in_start_state = 1'h0; + set_readout_loop_seg = 1'h0; + clr_readout_loop_seg = 1'h0; + end :scan_seq_seg_PASS_DONE_SEG_Output + PASS_STOP_SEG: begin :scan_seq_seg_PASS_STOP_SEG_Output + seg_addr_out_to_fifo = 16'h0; + seg_op_out_to_fifo = 16'h0; + seg_ID_out_to_fifo = 16'h0; + seg_req_push = 1'h0; + seg_rd_rsp_fifo_pop = 1'h1; + seg_pop_infifo = (~seg_res_fifo_full) & eos_in & (~readout_loop_sticky_sticky); + inc_req_made_seg = 1'h0; + clr_req_made_seg = 1'h1; + inc_req_rec_seg = 1'h0; + clr_req_rec_seg = 1'h1; + us_fifo_inject_data = 16'h0; + us_fifo_inject_eos = 1'h0; + us_fifo_inject_push = 1'h0; + seg_res_fifo_push_alloc = (infifo_valid_in | readout_loop_sticky_sticky) & (~seg_res_fifo_full); + seg_res_fifo_push_fill = (infifo_valid_in | readout_loop_sticky_sticky) & (~seg_res_fifo_full); + seg_res_fifo_fill_data_in = readout_loop_sticky_sticky ? last_stop_token - 17'h1: eos_in ? {1'h1, + infifo_pos_in + 16'h1}: {1'h1, 16'h0}; + infifo_pos_in_d1_en = 1'h0; + clr_pushed_done_seg = 1'h0; + set_pushed_done_seg = 1'h0; + seg_in_done_state = 1'h0; + seg_in_start_state = 1'h0; + set_readout_loop_seg = 1'h0; + clr_readout_loop_seg = 1'h0; + end :scan_seq_seg_PASS_STOP_SEG_Output + READ: begin :scan_seq_seg_READ_Output + seg_addr_out_to_fifo = readout_loop_sticky_sticky ? 16'h0: infifo_pos_in; + seg_op_out_to_fifo = 16'h1; + seg_ID_out_to_fifo = 16'h0; + seg_req_push = ((infifo_valid_in & (~infifo_eos_in) & (~dense)) | readout_loop_sticky_sticky) & + (~seg_res_fifo_full); + seg_rd_rsp_fifo_pop = 1'h1; + seg_pop_infifo = (((done_in | (infifo_valid_in & (~eos_in) & (dense | (|{seg_grant_push_0, + seg_grant_push_1})))) & (~seg_res_fifo_full)) | maybe_in) & + (~readout_loop_sticky_sticky); + inc_req_made_seg = 1'h0; + clr_req_made_seg = 1'h0; + inc_req_rec_seg = 1'h0; + clr_req_rec_seg = 1'h0; + us_fifo_inject_data = 16'h0; + us_fifo_inject_eos = 1'h0; + us_fifo_inject_push = 1'h0; + seg_res_fifo_push_alloc = (done_in | dense) ? (~seg_res_fifo_full) & infifo_valid_in & (~eos_in): + (~seg_res_fifo_full) & (|{seg_grant_push_0, seg_grant_push_1}) & (~maybe_in); + seg_res_fifo_push_fill = (done_in | (dense & infifo_valid_in & (~eos_in))) & (~seg_res_fifo_full); + seg_res_fifo_fill_data_in = {infifo_eos_in, infifo_pos_in}; + infifo_pos_in_d1_en = (|{seg_grant_push_0, seg_grant_push_1}) & (~seg_res_fifo_full); + clr_pushed_done_seg = 1'h0; + set_pushed_done_seg = 1'h0; + seg_in_done_state = 1'h0; + seg_in_start_state = 1'h0; + set_readout_loop_seg = 1'h0; + clr_readout_loop_seg = 1'h0; + end :scan_seq_seg_READ_Output + READ_ALT: begin :scan_seq_seg_READ_ALT_Output + seg_addr_out_to_fifo = readout_loop_sticky_sticky ? 16'h1: infifo_pos_in_d1 + 16'h1; + seg_op_out_to_fifo = 16'h1; + seg_ID_out_to_fifo = 16'h0; + seg_req_push = ~seg_res_fifo_full; + seg_rd_rsp_fifo_pop = 1'h1; + seg_pop_infifo = eos_in & (~done_in) & (|{seg_grant_push_0, seg_grant_push_1}) & + (~seg_res_fifo_full) & (~readout_loop_sticky_sticky); + inc_req_made_seg = 1'h0; + clr_req_made_seg = 1'h0; + inc_req_rec_seg = 1'h0; + clr_req_rec_seg = 1'h0; + us_fifo_inject_data = 16'h0; + us_fifo_inject_eos = 1'h0; + us_fifo_inject_push = 1'h0; + seg_res_fifo_push_alloc = infifo_valid_in & (|{seg_grant_push_0, seg_grant_push_1}) & (~seg_res_fifo_full) + & (~readout_loop_sticky_sticky); + seg_res_fifo_push_fill = infifo_valid_in & (|{seg_grant_push_0, seg_grant_push_1}) & (~seg_res_fifo_full) + & (~readout_loop_sticky_sticky); + seg_res_fifo_fill_data_in = eos_in ? {1'h1, infifo_pos_in + 16'h1}: {1'h1, 16'h0}; + infifo_pos_in_d1_en = 1'h0; + clr_pushed_done_seg = 1'h0; + set_pushed_done_seg = 1'h0; + seg_in_done_state = 1'h0; + seg_in_start_state = 1'h0; + set_readout_loop_seg = 1'h0; + clr_readout_loop_seg = 1'h0; + end :scan_seq_seg_READ_ALT_Output + START_SEG: begin :scan_seq_seg_START_SEG_Output + seg_addr_out_to_fifo = 16'h0; + seg_op_out_to_fifo = 16'h0; + seg_ID_out_to_fifo = 16'h0; + seg_req_push = 1'h0; + seg_rd_rsp_fifo_pop = 1'h0; + seg_pop_infifo = 1'h0; + inc_req_made_seg = 1'h0; + clr_req_made_seg = 1'h0; + inc_req_rec_seg = 1'h0; + clr_req_rec_seg = 1'h0; + us_fifo_inject_data = 16'h0; + us_fifo_inject_eos = 1'h0; + us_fifo_inject_push = 1'h0; + seg_res_fifo_push_alloc = 1'h0; + seg_res_fifo_push_fill = 1'h0; + seg_res_fifo_fill_data_in = 17'h0; + set_readout_loop_seg = 1'h0; + seg_in_start_state = 1'h1; + infifo_pos_in_d1_en = 1'h0; + clr_pushed_done_seg = 1'h0; + set_pushed_done_seg = 1'h0; + seg_in_done_state = 1'h0; + clr_readout_loop_seg = 1'h0; + end :scan_seq_seg_START_SEG_Output + default: begin :scan_seq_seg_default_Output + seg_addr_out_to_fifo = 16'h0; + seg_op_out_to_fifo = 16'h0; + seg_ID_out_to_fifo = 16'h0; + seg_req_push = 1'h0; + seg_rd_rsp_fifo_pop = 1'h0; + seg_pop_infifo = 1'h0; + inc_req_made_seg = 1'h0; + clr_req_made_seg = 1'h0; + inc_req_rec_seg = 1'h0; + clr_req_rec_seg = 1'h0; + us_fifo_inject_data = 16'h0; + us_fifo_inject_eos = 1'h0; + us_fifo_inject_push = 1'h0; + seg_res_fifo_push_alloc = 1'h0; + seg_res_fifo_push_fill = 1'h0; + seg_res_fifo_fill_data_in = 17'h0; + set_readout_loop_seg = 1'h0; + seg_in_start_state = 1'h1; + infifo_pos_in_d1_en = 1'h0; + clr_pushed_done_seg = 1'h0; + set_pushed_done_seg = 1'h0; + seg_in_done_state = 1'h0; + clr_readout_loop_seg = 1'h0; + end :scan_seq_seg_default_Output + endcase +end +reg_fifo_depth_2_w_17_afd_2 input_fifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in(fifo_us_in_packed), + .flush(flush), + .pop(pop_infifo), + .push(us_fifo_push), + .rst_n(rst_n), + .data_out(input_fifo_data_out), + .empty(input_fifo_empty), + .full(fifo_us_full) +); + +reg_fifo_depth_2_w_17_afd_2 rd_rsp_fifo_0 ( + .clk(gclk), + .clk_en(clk_en), + .data_in(rd_rsp_data_in_0), + .flush(flush), + .pop(1'h1), + .push(rd_rsp_data_in_0_valid), + .rst_n(rst_n), + .data_out(rd_rsp_fifo_0_out_data), + .empty(rd_rsp_fifo_0_empty), + .full(rd_rsp_fifo_0_full) +); + +reg_fifo_depth_2_w_17_afd_2 rd_rsp_fifo_1 ( + .clk(gclk), + .clk_en(clk_en), + .data_in(rd_rsp_data_in_1), + .flush(flush), + .pop(1'h1), + .push(rd_rsp_data_in_1_valid), + .rst_n(rst_n), + .data_out(rd_rsp_fifo_1_out_data), + .empty(rd_rsp_fifo_1_empty), + .full(rd_rsp_fifo_1_full) +); + +arbiter_2_in_PRIO_algo rr_arbiter_0 ( + .clk(gclk), + .clk_en(clk_en), + .flush(flush), + .request_in(base_rr_0), + .resource_ready(no_outfifo_full_0), + .rst_n(rst_n), + .grant_out(rr_arbiter_0_grant_out) +); + +arbiter_2_in_PRIO_algo rr_arbiter_1 ( + .clk(gclk), + .clk_en(clk_en), + .flush(flush), + .request_in(base_rr_1), + .resource_ready(no_outfifo_full_1), + .rst_n(rst_n), + .grant_out(rr_arbiter_1_grant_out) +); + +reg_fifo_depth_2_w_17_afd_2 addr_out_fifo_0 ( + .clk(gclk), + .clk_en(clk_en), + .data_in(addr_out_fifo_0_data_in), + .flush(flush), + .pop(addr_out_0_ready), + .push(addr_out_fifo_0_push), + .rst_n(rst_n), + .data_out(addr_out_0), + .empty(addr_out_fifo_0_empty), + .full(addr_out_fifo_0_full) +); + +reg_fifo_depth_2_w_17_afd_2 addr_out_fifo_1 ( + .clk(gclk), + .clk_en(clk_en), + .data_in(addr_out_fifo_1_data_in), + .flush(flush), + .pop(addr_out_1_ready), + .push(addr_out_fifo_1_push), + .rst_n(rst_n), + .data_out(addr_out_1), + .empty(addr_out_fifo_1_empty), + .full(addr_out_fifo_1_full) +); + +reg_fifo_depth_2_w_17_afd_2 op_out_fifo_0 ( + .clk(gclk), + .clk_en(clk_en), + .data_in(op_out_fifo_0_data_in), + .flush(flush), + .pop(op_out_0_ready), + .push(op_out_fifo_0_push), + .rst_n(rst_n), + .data_out(op_out_0), + .empty(op_out_fifo_0_empty), + .full(op_out_fifo_0_full) +); + +reg_fifo_depth_2_w_17_afd_2 op_out_fifo_1 ( + .clk(gclk), + .clk_en(clk_en), + .data_in(op_out_fifo_1_data_in), + .flush(flush), + .pop(op_out_1_ready), + .push(op_out_fifo_1_push), + .rst_n(rst_n), + .data_out(op_out_1), + .empty(op_out_fifo_1_empty), + .full(op_out_fifo_1_full) +); + +reservation_fifo_depth_8_w_17_num_per_2 seg_res_fifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in_0(rd_rsp_fifo_0_out_data), + .data_in_1(rd_rsp_fifo_0_out_data), + .fill_data_in(seg_res_fifo_fill_data_in), + .flush(flush), + .pop(seg_res_fifo_pop_0), + .push_alloc(seg_res_fifo_push_alloc_0), + .push_fill(seg_res_fifo_push_fill_0), + .push_reserve(seg_res_fifo_push_reserve_0), + .rst_n(rst_n), + .data_out_0(seg_res_fifo_data_out_0), + .data_out_1(seg_res_fifo_data_out_1), + .full(seg_res_fifo_full), + .valid(seg_res_fifo_valid) +); + +reservation_fifo_depth_32_w_17_num_per_1 crd_res_fifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in_0(crd_res_fifo_data_in_0), + .fill_data_in(crd_res_fifo_fill_data_in), + .flush(flush), + .pop(crd_res_fifo_pop), + .push_alloc(crd_res_fifo_push_alloc_0), + .push_fill(crd_res_fifo_push_fill_0), + .push_reserve(crd_res_fifo_push_reserve_0), + .rst_n(rst_n), + .data_out_0(crd_res_fifo_data_out), + .full(crd_res_fifo_full), + .valid(crd_res_fifo_valid) +); + +reg_fifo_depth_0_w_17_afd_2 coordinate_fifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in(coord_fifo_in_packed), + .flush(flush), + .pop(coord_out_ready), + .push(coord_fifo_push), + .rst_n(rst_n), + .data_out(coord_fifo_out_packed), + .empty(coordinate_fifo_empty), + .full(coordinate_fifo_full) +); + +reg_fifo_depth_0_w_17_afd_2 pos_fifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in(pos_fifo_in_packed), + .flush(flush), + .pop(pos_out_ready), + .push(pos_out_fifo_push), + .rst_n(rst_n), + .data_out(pos_fifo_out_packed), + .empty(pos_fifo_empty), + .full(pos_fifo_full) +); + +reg_fifo_depth_0_w_17_afd_2 block_rd_fifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in(crd_res_fifo_data_out), + .flush(flush), + .pop(block_rd_out_ready), + .push(block_rd_fifo_push), + .rst_n(rst_n), + .data_out(block_rd_out), + .empty(block_rd_fifo_empty), + .full(block_rd_fifo_full) +); + +endmodule // scanner_pipe + +module sched_gen_3_16 ( + input logic clk, + input logic clk_en, + input logic [15:0] cycle_count, + input logic enable, + input logic finished, + input logic flush, + input logic [1:0] mux_sel, + input logic rst_n, + input logic [15:0] sched_addr_gen_starting_addr, + input logic [15:0] sched_addr_gen_strides_0, + input logic [15:0] sched_addr_gen_strides_1, + input logic [15:0] sched_addr_gen_strides_2, + output logic valid_output +); + +logic [15:0] addr_out; +logic [2:0][15:0] sched_addr_gen_strides; +logic valid_gate; +logic valid_gate_inv; +logic valid_out; +assign valid_gate = ~valid_gate_inv; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + valid_gate_inv <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + valid_gate_inv <= 1'h0; + end + else if (finished) begin + valid_gate_inv <= 1'h1; + end + end +end +always_comb begin + valid_out = (cycle_count == addr_out) & valid_gate & enable; +end +always_comb begin + valid_output = valid_out; +end +assign sched_addr_gen_strides[0] = sched_addr_gen_strides_0; +assign sched_addr_gen_strides[1] = sched_addr_gen_strides_1; +assign sched_addr_gen_strides[2] = sched_addr_gen_strides_2; +addr_gen_3_16 sched_addr_gen ( + .clk(clk), + .clk_en(clk_en), + .flush(flush), + .mux_sel(mux_sel), + .restart(finished), + .rst_n(rst_n), + .starting_addr(sched_addr_gen_starting_addr), + .step(valid_out), + .strides(sched_addr_gen_strides), + .addr_out(addr_out) +); + +endmodule // sched_gen_3_16 + +module sched_gen_6_16 ( + input logic clk, + input logic clk_en, + input logic [15:0] cycle_count, + input logic enable, + input logic finished, + input logic flush, + input logic [2:0] mux_sel, + input logic rst_n, + input logic [15:0] sched_addr_gen_starting_addr, + input logic [15:0] sched_addr_gen_strides_0, + input logic [15:0] sched_addr_gen_strides_1, + input logic [15:0] sched_addr_gen_strides_2, + input logic [15:0] sched_addr_gen_strides_3, + input logic [15:0] sched_addr_gen_strides_4, + input logic [15:0] sched_addr_gen_strides_5, + output logic valid_output +); + +logic [15:0] addr_out; +logic [5:0][15:0] sched_addr_gen_strides; +logic valid_gate; +logic valid_gate_inv; +logic valid_out; +assign valid_gate = ~valid_gate_inv; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + valid_gate_inv <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + valid_gate_inv <= 1'h0; + end + else if (finished) begin + valid_gate_inv <= 1'h1; + end + end +end +always_comb begin + valid_out = (cycle_count == addr_out) & valid_gate & enable; +end +always_comb begin + valid_output = valid_out; +end +assign sched_addr_gen_strides[0] = sched_addr_gen_strides_0; +assign sched_addr_gen_strides[1] = sched_addr_gen_strides_1; +assign sched_addr_gen_strides[2] = sched_addr_gen_strides_2; +assign sched_addr_gen_strides[3] = sched_addr_gen_strides_3; +assign sched_addr_gen_strides[4] = sched_addr_gen_strides_4; +assign sched_addr_gen_strides[5] = sched_addr_gen_strides_5; +addr_gen_6_16 sched_addr_gen ( + .clk(clk), + .clk_en(clk_en), + .flush(flush), + .mux_sel(mux_sel), + .restart(finished), + .rst_n(rst_n), + .starting_addr(sched_addr_gen_starting_addr), + .step(valid_out), + .strides(sched_addr_gen_strides), + .addr_out(addr_out) +); + +endmodule // sched_gen_6_16 + +module sched_gen_6_16_delay_addr_10_4 ( + input logic clk, + input logic clk_en, + input logic [15:0] cycle_count, + input logic enable, + input logic finished, + input logic flush, + input logic [2:0] mux_sel, + input logic rst_n, + input logic [9:0] sched_addr_gen_delay, + input logic [15:0] sched_addr_gen_starting_addr, + input logic [15:0] sched_addr_gen_strides_0, + input logic [15:0] sched_addr_gen_strides_1, + input logic [15:0] sched_addr_gen_strides_2, + input logic [15:0] sched_addr_gen_strides_3, + input logic [15:0] sched_addr_gen_strides_4, + input logic [15:0] sched_addr_gen_strides_5, + output logic delay_en_out, + output logic valid_output, + output logic valid_output_d +); + +logic [3:0][10:0] addr_fifo; +logic addr_fifo_empty_n; +logic [10:0] addr_fifo_in; +logic [10:0] addr_fifo_out; +logic addr_fifo_wr_en; +logic [15:0] addr_out; +logic [15:0] addr_out_d; +logic delay_en; +logic [1:0] next_rd_ptr; +logic [1:0] rd_ptr; +logic [9:0] sched_addr_gen_delay_out; +logic [5:0][15:0] sched_addr_gen_strides; +logic valid_gate; +logic valid_gate_inv; +logic valid_out; +logic valid_out_d; +logic [1:0] wr_ptr; +assign valid_gate = ~valid_gate_inv; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + valid_gate_inv <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + valid_gate_inv <= 1'h0; + end + else if (finished) begin + valid_gate_inv <= 1'h1; + end + end +end +assign delay_en_out = delay_en; +assign delay_en = sched_addr_gen_delay_out > 10'h0; +assign next_rd_ptr = rd_ptr + 2'h1; +assign addr_fifo_wr_en = valid_out; +assign addr_fifo_in = addr_out_d[10:0]; +assign addr_fifo_out = addr_fifo[rd_ptr]; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + wr_ptr <= 2'h0; + rd_ptr <= 2'h0; + addr_fifo <= 44'h0; + addr_fifo_empty_n <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + wr_ptr <= 2'h0; + rd_ptr <= 2'h0; + addr_fifo <= 44'h0; + addr_fifo_empty_n <= 1'h0; + end + else if (delay_en) begin + if (addr_fifo_wr_en) begin + wr_ptr <= wr_ptr + 2'h1; + addr_fifo[wr_ptr] <= addr_fifo_in; + end + if (valid_out_d) begin + rd_ptr <= next_rd_ptr; + end + if (addr_fifo_wr_en) begin + addr_fifo_empty_n <= 1'h1; + end + else if (valid_out_d) begin + addr_fifo_empty_n <= ~(next_rd_ptr == wr_ptr); + end + else addr_fifo_empty_n <= addr_fifo_empty_n; + end + end +end +always_comb begin + valid_out_d = (cycle_count[10:0] == addr_fifo_out) & addr_fifo_empty_n & enable; + valid_output_d = valid_out_d; +end +always_comb begin + valid_out = (cycle_count == addr_out) & valid_gate & enable; +end +always_comb begin + valid_output = valid_out; +end +assign sched_addr_gen_strides[0] = sched_addr_gen_strides_0; +assign sched_addr_gen_strides[1] = sched_addr_gen_strides_1; +assign sched_addr_gen_strides[2] = sched_addr_gen_strides_2; +assign sched_addr_gen_strides[3] = sched_addr_gen_strides_3; +assign sched_addr_gen_strides[4] = sched_addr_gen_strides_4; +assign sched_addr_gen_strides[5] = sched_addr_gen_strides_5; +addr_gen_6_16_delay_addr_10 sched_addr_gen ( + .clk(clk), + .clk_en(clk_en), + .delay(sched_addr_gen_delay), + .flush(flush), + .mux_sel(mux_sel), + .restart(finished), + .rst_n(rst_n), + .starting_addr(sched_addr_gen_starting_addr), + .step(valid_out), + .strides(sched_addr_gen_strides), + .addr_out(addr_out), + .delay_out(sched_addr_gen_delay_out), + .delayed_addr_out(addr_out_d) +); + +endmodule // sched_gen_6_16_delay_addr_10_4 + +module sched_gen_6_16_delay_addr_10_8 ( + input logic clk, + input logic clk_en, + input logic [15:0] cycle_count, + input logic enable, + input logic finished, + input logic flush, + input logic [2:0] mux_sel, + input logic rst_n, + input logic [9:0] sched_addr_gen_delay, + input logic [15:0] sched_addr_gen_starting_addr, + input logic [15:0] sched_addr_gen_strides_0, + input logic [15:0] sched_addr_gen_strides_1, + input logic [15:0] sched_addr_gen_strides_2, + input logic [15:0] sched_addr_gen_strides_3, + input logic [15:0] sched_addr_gen_strides_4, + input logic [15:0] sched_addr_gen_strides_5, + output logic delay_en_out, + output logic valid_output, + output logic valid_output_d +); + +logic [7:0][10:0] addr_fifo; +logic addr_fifo_empty_n; +logic [10:0] addr_fifo_in; +logic [10:0] addr_fifo_out; +logic addr_fifo_wr_en; +logic [15:0] addr_out; +logic [15:0] addr_out_d; +logic delay_en; +logic [2:0] next_rd_ptr; +logic [2:0] rd_ptr; +logic [9:0] sched_addr_gen_delay_out; +logic [5:0][15:0] sched_addr_gen_strides; +logic valid_gate; +logic valid_gate_inv; +logic valid_out; +logic valid_out_d; +logic [2:0] wr_ptr; +assign valid_gate = ~valid_gate_inv; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + valid_gate_inv <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + valid_gate_inv <= 1'h0; + end + else if (finished) begin + valid_gate_inv <= 1'h1; + end + end +end +assign delay_en_out = delay_en; +assign delay_en = sched_addr_gen_delay_out > 10'h0; +assign next_rd_ptr = rd_ptr + 3'h1; +assign addr_fifo_wr_en = valid_out; +assign addr_fifo_in = addr_out_d[10:0]; +assign addr_fifo_out = addr_fifo[rd_ptr]; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + wr_ptr <= 3'h0; + rd_ptr <= 3'h0; + addr_fifo <= 88'h0; + addr_fifo_empty_n <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + wr_ptr <= 3'h0; + rd_ptr <= 3'h0; + addr_fifo <= 88'h0; + addr_fifo_empty_n <= 1'h0; + end + else if (delay_en) begin + if (addr_fifo_wr_en) begin + wr_ptr <= wr_ptr + 3'h1; + addr_fifo[wr_ptr] <= addr_fifo_in; + end + if (valid_out_d) begin + rd_ptr <= next_rd_ptr; + end + if (addr_fifo_wr_en) begin + addr_fifo_empty_n <= 1'h1; + end + else if (valid_out_d) begin + addr_fifo_empty_n <= ~(next_rd_ptr == wr_ptr); + end + else addr_fifo_empty_n <= addr_fifo_empty_n; + end + end +end +always_comb begin + valid_out_d = (cycle_count[10:0] == addr_fifo_out) & addr_fifo_empty_n & enable; + valid_output_d = valid_out_d; +end +always_comb begin + valid_out = (cycle_count == addr_out) & valid_gate & enable; +end +always_comb begin + valid_output = valid_out; +end +assign sched_addr_gen_strides[0] = sched_addr_gen_strides_0; +assign sched_addr_gen_strides[1] = sched_addr_gen_strides_1; +assign sched_addr_gen_strides[2] = sched_addr_gen_strides_2; +assign sched_addr_gen_strides[3] = sched_addr_gen_strides_3; +assign sched_addr_gen_strides[4] = sched_addr_gen_strides_4; +assign sched_addr_gen_strides[5] = sched_addr_gen_strides_5; +addr_gen_6_16_delay_addr_10 sched_addr_gen ( + .clk(clk), + .clk_en(clk_en), + .delay(sched_addr_gen_delay), + .flush(flush), + .mux_sel(mux_sel), + .restart(finished), + .rst_n(rst_n), + .starting_addr(sched_addr_gen_starting_addr), + .step(valid_out), + .strides(sched_addr_gen_strides), + .addr_out(addr_out), + .delay_out(sched_addr_gen_delay_out), + .delayed_addr_out(addr_out_d) +); + +endmodule // sched_gen_6_16_delay_addr_10_8 + +module sram_sp__0 ( + input logic clk, + input logic clk_en, + input logic [63:0] data_in_p0, + input logic flush, + input logic [8:0] read_addr_p0, + input logic read_enable_p0, + input logic [8:0] write_addr_p0, + input logic write_enable_p0, + output logic [63:0] data_out_p0 +); + +logic [63:0] data_array [511:0]; + +always_ff @(posedge clk) begin + if (clk_en) begin + if (write_enable_p0 == 1'h1) begin + data_array[write_addr_p0] <= data_in_p0; + end + else if (read_enable_p0) begin + data_out_p0 <= data_array[read_addr_p0]; + end + end +end +endmodule // sram_sp__0 + +module stencil_valid ( + input logic clk, + input logic clk_en, + input logic flush, + input logic [3:0] loops_stencil_valid_dimensionality, + input logic [10:0] loops_stencil_valid_ranges_0, + input logic [10:0] loops_stencil_valid_ranges_1, + input logic [10:0] loops_stencil_valid_ranges_2, + input logic [10:0] loops_stencil_valid_ranges_3, + input logic [10:0] loops_stencil_valid_ranges_4, + input logic [10:0] loops_stencil_valid_ranges_5, + input logic rst_n, + input logic stencil_valid_sched_gen_enable, + input logic [15:0] stencil_valid_sched_gen_sched_addr_gen_starting_addr, + input logic [15:0] stencil_valid_sched_gen_sched_addr_gen_strides_0, + input logic [15:0] stencil_valid_sched_gen_sched_addr_gen_strides_1, + input logic [15:0] stencil_valid_sched_gen_sched_addr_gen_strides_2, + input logic [15:0] stencil_valid_sched_gen_sched_addr_gen_strides_3, + input logic [15:0] stencil_valid_sched_gen_sched_addr_gen_strides_4, + input logic [15:0] stencil_valid_sched_gen_sched_addr_gen_strides_5, + output logic stencil_valid +); + +logic [15:0] cycle_count; +logic flushed; +logic [2:0] loops_stencil_valid_mux_sel_out; +logic [5:0][10:0] loops_stencil_valid_ranges; +logic loops_stencil_valid_restart; +logic stencil_valid_internal; +assign stencil_valid = stencil_valid_internal & flushed; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + cycle_count <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + cycle_count <= 16'h0; + end + else if (flushed) begin + cycle_count <= cycle_count + 16'h1; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + flushed <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + flushed <= 1'h1; + end + end +end +assign loops_stencil_valid_ranges[0] = loops_stencil_valid_ranges_0; +assign loops_stencil_valid_ranges[1] = loops_stencil_valid_ranges_1; +assign loops_stencil_valid_ranges[2] = loops_stencil_valid_ranges_2; +assign loops_stencil_valid_ranges[3] = loops_stencil_valid_ranges_3; +assign loops_stencil_valid_ranges[4] = loops_stencil_valid_ranges_4; +assign loops_stencil_valid_ranges[5] = loops_stencil_valid_ranges_5; +for_loop_6_11 loops_stencil_valid ( + .clk(clk), + .clk_en(clk_en), + .dimensionality(loops_stencil_valid_dimensionality), + .flush(flush), + .ranges(loops_stencil_valid_ranges), + .rst_n(rst_n), + .step(stencil_valid_internal), + .mux_sel_out(loops_stencil_valid_mux_sel_out), + .restart(loops_stencil_valid_restart) +); + +sched_gen_6_16 stencil_valid_sched_gen ( + .clk(clk), + .clk_en(clk_en), + .cycle_count(cycle_count), + .enable(stencil_valid_sched_gen_enable), + .finished(loops_stencil_valid_restart), + .flush(flush), + .mux_sel(loops_stencil_valid_mux_sel_out), + .rst_n(rst_n), + .sched_addr_gen_starting_addr(stencil_valid_sched_gen_sched_addr_gen_starting_addr), + .sched_addr_gen_strides_0(stencil_valid_sched_gen_sched_addr_gen_strides_0), + .sched_addr_gen_strides_1(stencil_valid_sched_gen_sched_addr_gen_strides_1), + .sched_addr_gen_strides_2(stencil_valid_sched_gen_sched_addr_gen_strides_2), + .sched_addr_gen_strides_3(stencil_valid_sched_gen_sched_addr_gen_strides_3), + .sched_addr_gen_strides_4(stencil_valid_sched_gen_sched_addr_gen_strides_4), + .sched_addr_gen_strides_5(stencil_valid_sched_gen_sched_addr_gen_strides_5), + .valid_output(stencil_valid_internal) +); + +endmodule // stencil_valid + +module stencil_valid_flat ( + input logic clk, + input logic clk_en, + input logic flush, + input logic rst_n, + input logic [3:0] stencil_valid_inst_loops_stencil_valid_dimensionality, + input logic [10:0] stencil_valid_inst_loops_stencil_valid_ranges_0, + input logic [10:0] stencil_valid_inst_loops_stencil_valid_ranges_1, + input logic [10:0] stencil_valid_inst_loops_stencil_valid_ranges_2, + input logic [10:0] stencil_valid_inst_loops_stencil_valid_ranges_3, + input logic [10:0] stencil_valid_inst_loops_stencil_valid_ranges_4, + input logic [10:0] stencil_valid_inst_loops_stencil_valid_ranges_5, + input logic stencil_valid_inst_stencil_valid_sched_gen_enable, + input logic [15:0] stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_starting_addr, + input logic [15:0] stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_0, + input logic [15:0] stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_1, + input logic [15:0] stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_2, + input logic [15:0] stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_3, + input logic [15:0] stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_4, + input logic [15:0] stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_5, + output logic stencil_valid_f_ +); + +stencil_valid stencil_valid_inst ( + .clk(clk), + .clk_en(clk_en), + .flush(flush), + .loops_stencil_valid_dimensionality(stencil_valid_inst_loops_stencil_valid_dimensionality), + .loops_stencil_valid_ranges_0(stencil_valid_inst_loops_stencil_valid_ranges_0), + .loops_stencil_valid_ranges_1(stencil_valid_inst_loops_stencil_valid_ranges_1), + .loops_stencil_valid_ranges_2(stencil_valid_inst_loops_stencil_valid_ranges_2), + .loops_stencil_valid_ranges_3(stencil_valid_inst_loops_stencil_valid_ranges_3), + .loops_stencil_valid_ranges_4(stencil_valid_inst_loops_stencil_valid_ranges_4), + .loops_stencil_valid_ranges_5(stencil_valid_inst_loops_stencil_valid_ranges_5), + .rst_n(rst_n), + .stencil_valid_sched_gen_enable(stencil_valid_inst_stencil_valid_sched_gen_enable), + .stencil_valid_sched_gen_sched_addr_gen_starting_addr(stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_starting_addr), + .stencil_valid_sched_gen_sched_addr_gen_strides_0(stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_0), + .stencil_valid_sched_gen_sched_addr_gen_strides_1(stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_1), + .stencil_valid_sched_gen_sched_addr_gen_strides_2(stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_2), + .stencil_valid_sched_gen_sched_addr_gen_strides_3(stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_3), + .stencil_valid_sched_gen_sched_addr_gen_strides_4(stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_4), + .stencil_valid_sched_gen_sched_addr_gen_strides_5(stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_5), + .stencil_valid(stencil_valid_f_) +); + +endmodule // stencil_valid_flat + +module storage_config_seq_2_64_16 ( + input logic clk, + input logic clk_en, + input logic [7:0] config_addr_in, + input logic [15:0] config_data_in, + input logic [1:0] config_en, + input logic config_rd, + input logic config_wr, + input logic flush, + input logic [0:0][3:0] [15:0] rd_data_stg, + input logic rst_n, + output logic [8:0] addr_out, + output logic [1:0] [15:0] rd_data_out, + output logic ren_out, + output logic wen_out, + output logic [3:0] [15:0] wr_data +); + +logic [1:0] cnt; +logic [2:0][15:0] data_wr_reg; +logic [1:0] rd_cnt; +logic rd_valid; +logic [1:0] reduce_en; +logic set_to_addr; +assign reduce_en[0] = |config_en[0]; +assign reduce_en[1] = |config_en[1]; +always_comb begin + set_to_addr = 1'h0; + for (int unsigned i = 0; i < 2; i += 1) begin + if (reduce_en[1'(i)]) begin + set_to_addr = 1'(i); + end + end +end +assign addr_out = {set_to_addr, config_addr_in}; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + cnt <= 2'h0; + end + else if (flush) begin + cnt <= 2'h0; + end + else if (config_wr & (|config_en)) begin + cnt <= cnt + 2'h1; + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + rd_valid <= 1'h0; + end + else if (flush) begin + rd_valid <= 1'h0; + end + else rd_valid <= config_rd & (|config_en); +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + rd_cnt <= 2'h0; + end + else if (flush) begin + rd_cnt <= 2'h0; + end + else if (rd_valid & (~(config_rd & (|config_en)))) begin + rd_cnt <= rd_cnt + 2'h1; + end +end +assign rd_data_out[0] = rd_data_stg[0][rd_cnt]; +assign rd_data_out[1] = rd_data_stg[0][rd_cnt]; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + data_wr_reg <= 48'h0; + end + else if (flush) begin + data_wr_reg <= 48'h0; + end + else if (config_wr & (cnt < 2'h3)) begin + data_wr_reg[cnt] <= config_data_in; + end +end +assign wr_data[0] = data_wr_reg[0]; +assign wr_data[1] = data_wr_reg[1]; +assign wr_data[2] = data_wr_reg[2]; +assign wr_data[3] = config_data_in; +assign wen_out = config_wr & (cnt == 2'h3); +assign ren_out = config_rd; +endmodule // storage_config_seq_2_64_16 + +module strg_ram_64_512_delay1 ( + input logic clk, + input logic clk_en, + input logic [0:0][3:0] [15:0] data_from_strg, + input logic [16:0] data_in, + input logic flush, + input logic [16:0] rd_addr_in, + input logic ren, + input logic rst_n, + input logic wen, + input logic [16:0] wr_addr_in, + output logic [0:0] [8:0] addr_out, + output logic [16:0] data_out, + output logic [0:0][3:0] [15:0] data_to_strg, + output logic ready, + output logic ren_to_strg, + output logic valid_out, + output logic wen_to_strg +); + +typedef enum logic[1:0] { + IDLE = 2'h0, + MODIFY = 2'h1, + READ = 2'h2, + _DEFAULT = 2'h3 +} r_w_seq_state; +logic [15:0] addr_to_write; +logic [3:0][15:0] data_combined; +logic [15:0] data_to_write; +r_w_seq_state r_w_seq_current_state; +r_w_seq_state r_w_seq_next_state; +logic [15:0] rd_addr; +logic rd_bank; +logic read_gate; +logic [15:0] wr_addr; +logic write_gate; +assign wr_addr = wr_addr_in[15:0]; +assign rd_addr = wr_addr_in[15:0]; +assign rd_bank = 1'h0; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + data_to_write <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + data_to_write <= 16'h0; + end + else data_to_write <= data_in[15:0]; + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + addr_to_write <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + addr_to_write <= 16'h0; + end + else addr_to_write <= wr_addr; + end +end +assign data_to_strg[0] = data_combined; +assign ren_to_strg = (wen | ren) & read_gate; +assign wen_to_strg = write_gate; +always_comb begin + addr_out[0] = rd_addr[10:2]; + if (wen & (~write_gate)) begin + addr_out[0] = wr_addr[10:2]; + end + else if (write_gate) begin + addr_out[0] = addr_to_write[10:2]; + end +end +always_comb begin + if (addr_to_write[1:0] == 2'h0) begin + data_combined[0] = data_to_write; + end + else data_combined[0] = data_from_strg[rd_bank][0]; +end +always_comb begin + if (addr_to_write[1:0] == 2'h1) begin + data_combined[1] = data_to_write; + end + else data_combined[1] = data_from_strg[rd_bank][1]; +end +always_comb begin + if (addr_to_write[1:0] == 2'h2) begin + data_combined[2] = data_to_write; + end + else data_combined[2] = data_from_strg[rd_bank][2]; +end +always_comb begin + if (addr_to_write[1:0] == 2'h3) begin + data_combined[3] = data_to_write; + end + else data_combined[3] = data_from_strg[rd_bank][3]; +end + +always_ff @(posedge clk, negedge rst_n) begin + if (!rst_n) begin + r_w_seq_current_state <= IDLE; + end + else r_w_seq_current_state <= r_w_seq_next_state; +end +always_comb begin + r_w_seq_next_state = r_w_seq_current_state; + unique case (r_w_seq_current_state) + IDLE: begin + if ((~wen) & (~ren)) begin + r_w_seq_next_state = IDLE; + end + else if (ren & (~wen)) begin + r_w_seq_next_state = READ; + end + else if (wen) begin + r_w_seq_next_state = MODIFY; + end + end + MODIFY: begin + if (1'h1) begin + r_w_seq_next_state = IDLE; + end + end + READ: begin + if ((~wen) & (~ren)) begin + r_w_seq_next_state = IDLE; + end + else if (ren & (~wen)) begin + r_w_seq_next_state = READ; + end + else if (wen) begin + r_w_seq_next_state = MODIFY; + end + end + _DEFAULT: begin + if (1'h1) begin + r_w_seq_next_state = _DEFAULT; + end + end + default: begin end + endcase +end +always_comb begin + unique case (r_w_seq_current_state) + IDLE: begin :r_w_seq_IDLE_Output + ready = 1'h1; + valid_out = 1'h0; + data_out[15:0] = 16'h0; + data_out[16] = 1'h0; + write_gate = 1'h0; + read_gate = 1'h1; + end :r_w_seq_IDLE_Output + MODIFY: begin :r_w_seq_MODIFY_Output + ready = 1'h0; + valid_out = 1'h0; + data_out[15:0] = 16'h0; + data_out[16] = 1'h0; + write_gate = 1'h1; + read_gate = 1'h0; + end :r_w_seq_MODIFY_Output + READ: begin :r_w_seq_READ_Output + ready = 1'h1; + valid_out = 1'h1; + data_out[15:0] = data_from_strg[rd_bank][addr_to_write[1:0]]; + data_out[16] = 1'h0; + write_gate = 1'h0; + read_gate = 1'h1; + end :r_w_seq_READ_Output + _DEFAULT: begin :r_w_seq__DEFAULT_Output + ready = 1'h0; + valid_out = 1'h0; + data_out[15:0] = 16'h0; + data_out[16] = 1'h0; + write_gate = 1'h0; + read_gate = 1'h0; + end :r_w_seq__DEFAULT_Output + default: begin end + endcase +end +endmodule // strg_ram_64_512_delay1 + +module strg_ram_64_512_delay1_flat ( + input logic clk, + input logic clk_en, + input logic [0:0] [16:0] data_in_f_, + input logic flush, + input logic [0:0] [16:0] rd_addr_in_f_, + input logic ren_f_, + input logic rst_n, + input logic [0:0][3:0] [15:0] strg_ram_64_512_delay1_inst_data_from_strg_lifted, + input logic wen_f_, + input logic [0:0] [16:0] wr_addr_in_f_, + output logic [0:0] [16:0] data_out_f_, + output logic ready_f_, + output logic [0:0] [8:0] strg_ram_64_512_delay1_inst_addr_out_lifted, + output logic [0:0][3:0] [15:0] strg_ram_64_512_delay1_inst_data_to_strg_lifted, + output logic strg_ram_64_512_delay1_inst_ren_to_strg_lifted, + output logic strg_ram_64_512_delay1_inst_wen_to_strg_lifted, + output logic valid_out_f_ +); + +strg_ram_64_512_delay1 strg_ram_64_512_delay1_inst ( + .clk(clk), + .clk_en(clk_en), + .data_from_strg(strg_ram_64_512_delay1_inst_data_from_strg_lifted), + .data_in(data_in_f_), + .flush(flush), + .rd_addr_in(rd_addr_in_f_), + .ren(ren_f_), + .rst_n(rst_n), + .wen(wen_f_), + .wr_addr_in(wr_addr_in_f_), + .addr_out(strg_ram_64_512_delay1_inst_addr_out_lifted), + .data_out(data_out_f_), + .data_to_strg(strg_ram_64_512_delay1_inst_data_to_strg_lifted), + .ready(ready_f_), + .ren_to_strg(strg_ram_64_512_delay1_inst_ren_to_strg_lifted), + .valid_out(valid_out_f_), + .wen_to_strg(strg_ram_64_512_delay1_inst_wen_to_strg_lifted) +); + +endmodule // strg_ram_64_512_delay1_flat + +module strg_ub_agg_only ( + input logic [1:0] agg_read, + input logic [2:0] agg_write_addr_gen_0_starting_addr, + input logic [2:0] agg_write_addr_gen_0_strides_0, + input logic [2:0] agg_write_addr_gen_0_strides_1, + input logic [2:0] agg_write_addr_gen_0_strides_2, + input logic [2:0] agg_write_addr_gen_1_starting_addr, + input logic [2:0] agg_write_addr_gen_1_strides_0, + input logic [2:0] agg_write_addr_gen_1_strides_1, + input logic [2:0] agg_write_addr_gen_1_strides_2, + input logic agg_write_sched_gen_0_enable, + input logic [15:0] agg_write_sched_gen_0_sched_addr_gen_starting_addr, + input logic [15:0] agg_write_sched_gen_0_sched_addr_gen_strides_0, + input logic [15:0] agg_write_sched_gen_0_sched_addr_gen_strides_1, + input logic [15:0] agg_write_sched_gen_0_sched_addr_gen_strides_2, + input logic agg_write_sched_gen_1_enable, + input logic [15:0] agg_write_sched_gen_1_sched_addr_gen_starting_addr, + input logic [15:0] agg_write_sched_gen_1_sched_addr_gen_strides_0, + input logic [15:0] agg_write_sched_gen_1_sched_addr_gen_strides_1, + input logic [15:0] agg_write_sched_gen_1_sched_addr_gen_strides_2, + input logic clk, + input logic clk_en, + input logic [15:0] cycle_count, + input logic [1:0] [15:0] data_in, + input logic flush, + input logic [2:0] loops_in2buf_0_dimensionality, + input logic [10:0] loops_in2buf_0_ranges_0, + input logic [10:0] loops_in2buf_0_ranges_1, + input logic [10:0] loops_in2buf_0_ranges_2, + input logic [2:0] loops_in2buf_1_dimensionality, + input logic [10:0] loops_in2buf_1_ranges_0, + input logic [10:0] loops_in2buf_1_ranges_1, + input logic [10:0] loops_in2buf_1_ranges_2, + input logic rst_n, + input logic [1:0] [8:0] sram_read_addr_in, + input logic [1:0] [2:0] tb_read_addr_d_in, + input logic [1:0] tb_read_d_in, + input logic [1:0] [1:0] update_mode_in, + output logic [1:0][3:0] [15:0] agg_data_out, + output logic [1:0] [1:0] agg_write_addr_l2b_out, + output logic [1:0] [2:0] agg_write_mux_sel_out, + output logic [1:0] agg_write_out, + output logic [1:0] agg_write_restart_out +); + +logic [1:0][1:0][3:0][15:0] agg; +logic [1:0] agg_read_addr; +logic [1:0][7:0] agg_read_addr_gen_out; +logic [1:0] agg_read_addr_in; +logic [1:0] agg_write; +logic [1:0][2:0] agg_write_addr; +logic [2:0] agg_write_addr_gen_0_addr_out; +logic [2:0][2:0] agg_write_addr_gen_0_strides; +logic [2:0] agg_write_addr_gen_1_addr_out; +logic [2:0][2:0] agg_write_addr_gen_1_strides; +logic agg_write_sched_gen_0_valid_output; +logic agg_write_sched_gen_1_valid_output; +logic [2:0] fl_mux_sel_0; +logic [2:0] fl_mux_sel_1; +logic [1:0] loops_in2buf_0_mux_sel_out; +logic [2:0][10:0] loops_in2buf_0_ranges; +logic loops_in2buf_0_restart; +logic [1:0] loops_in2buf_1_mux_sel_out; +logic [2:0][10:0] loops_in2buf_1_ranges; +logic loops_in2buf_1_restart; +logic [1:0] mode_0; +logic [1:0] mode_1; +logic [2:0] tb_addr_0; +logic [2:0] tb_addr_1; +logic tb_read_0; +logic tb_read_1; +assign agg_write_out = agg_write; +assign mode_0 = update_mode_in[0]; +assign agg_write_addr_l2b_out[0] = agg_write_addr[0][1:0]; +assign tb_read_0 = mode_0[0] ? tb_read_d_in[1]: tb_read_d_in[0]; +assign tb_addr_0 = mode_0[0] ? tb_read_addr_d_in[1]: tb_read_addr_d_in[0]; +assign fl_mux_sel_0[1:0] = loops_in2buf_0_mux_sel_out; +assign fl_mux_sel_0[2] = 1'h0; +assign agg_write_mux_sel_out[0] = fl_mux_sel_0; +assign agg_write_restart_out[0] = loops_in2buf_0_restart; +assign agg_write_addr[0] = mode_0[1] ? tb_addr_0: agg_write_addr_gen_0_addr_out; +assign agg_write[0] = mode_0[1] ? tb_read_0: agg_write_sched_gen_0_valid_output; + +always_ff @(posedge clk) begin + if (clk_en) begin + if (agg_write[0]) begin + agg[0][agg_write_addr[0][2]][agg_write_addr[0][1:0]] <= data_in[0]; + end + end +end +assign agg_read_addr_in[0] = sram_read_addr_in[0][0]; +assign agg_read_addr_gen_out[0][0] = agg_read_addr_in[0]; +assign agg_read_addr_gen_out[0][7:1] = 7'h0; +assign agg_read_addr[0] = agg_read_addr_gen_out[0][0]; +always_comb begin + agg_data_out[0] = agg[0][agg_read_addr[0]]; +end +assign mode_1 = update_mode_in[1]; +assign agg_write_addr_l2b_out[1] = agg_write_addr[1][1:0]; +assign tb_read_1 = mode_1[0] ? tb_read_d_in[1]: tb_read_d_in[0]; +assign tb_addr_1 = mode_1[0] ? tb_read_addr_d_in[1]: tb_read_addr_d_in[0]; +assign fl_mux_sel_1[1:0] = loops_in2buf_1_mux_sel_out; +assign fl_mux_sel_1[2] = 1'h0; +assign agg_write_mux_sel_out[1] = fl_mux_sel_1; +assign agg_write_restart_out[1] = loops_in2buf_1_restart; +assign agg_write_addr[1] = mode_1[1] ? tb_addr_1: agg_write_addr_gen_1_addr_out; +assign agg_write[1] = mode_1[1] ? tb_read_1: agg_write_sched_gen_1_valid_output; + +always_ff @(posedge clk) begin + if (clk_en) begin + if (agg_write[1]) begin + agg[1][agg_write_addr[1][2]][agg_write_addr[1][1:0]] <= data_in[1]; + end + end +end +assign agg_read_addr_in[1] = sram_read_addr_in[1][0]; +assign agg_read_addr_gen_out[1][0] = agg_read_addr_in[1]; +assign agg_read_addr_gen_out[1][7:1] = 7'h0; +assign agg_read_addr[1] = agg_read_addr_gen_out[1][0]; +always_comb begin + agg_data_out[1] = agg[1][agg_read_addr[1]]; +end +assign loops_in2buf_0_ranges[0] = loops_in2buf_0_ranges_0; +assign loops_in2buf_0_ranges[1] = loops_in2buf_0_ranges_1; +assign loops_in2buf_0_ranges[2] = loops_in2buf_0_ranges_2; +assign agg_write_addr_gen_0_strides[0] = agg_write_addr_gen_0_strides_0; +assign agg_write_addr_gen_0_strides[1] = agg_write_addr_gen_0_strides_1; +assign agg_write_addr_gen_0_strides[2] = agg_write_addr_gen_0_strides_2; +assign loops_in2buf_1_ranges[0] = loops_in2buf_1_ranges_0; +assign loops_in2buf_1_ranges[1] = loops_in2buf_1_ranges_1; +assign loops_in2buf_1_ranges[2] = loops_in2buf_1_ranges_2; +assign agg_write_addr_gen_1_strides[0] = agg_write_addr_gen_1_strides_0; +assign agg_write_addr_gen_1_strides[1] = agg_write_addr_gen_1_strides_1; +assign agg_write_addr_gen_1_strides[2] = agg_write_addr_gen_1_strides_2; +for_loop_3_11 loops_in2buf_0 ( + .clk(clk), + .clk_en(clk_en), + .dimensionality(loops_in2buf_0_dimensionality), + .flush(flush), + .ranges(loops_in2buf_0_ranges), + .rst_n(rst_n), + .step(agg_write[0]), + .mux_sel_out(loops_in2buf_0_mux_sel_out), + .restart(loops_in2buf_0_restart) +); + +addr_gen_3_3 agg_write_addr_gen_0 ( + .clk(clk), + .clk_en(clk_en), + .flush(flush), + .mux_sel(loops_in2buf_0_mux_sel_out), + .restart(loops_in2buf_0_restart), + .rst_n(rst_n), + .starting_addr(agg_write_addr_gen_0_starting_addr), + .step(agg_write[0]), + .strides(agg_write_addr_gen_0_strides), + .addr_out(agg_write_addr_gen_0_addr_out) +); + +sched_gen_3_16 agg_write_sched_gen_0 ( + .clk(clk), + .clk_en(clk_en), + .cycle_count(cycle_count), + .enable(agg_write_sched_gen_0_enable), + .finished(loops_in2buf_0_restart), + .flush(flush), + .mux_sel(loops_in2buf_0_mux_sel_out), + .rst_n(rst_n), + .sched_addr_gen_starting_addr(agg_write_sched_gen_0_sched_addr_gen_starting_addr), + .sched_addr_gen_strides_0(agg_write_sched_gen_0_sched_addr_gen_strides_0), + .sched_addr_gen_strides_1(agg_write_sched_gen_0_sched_addr_gen_strides_1), + .sched_addr_gen_strides_2(agg_write_sched_gen_0_sched_addr_gen_strides_2), + .valid_output(agg_write_sched_gen_0_valid_output) +); + +for_loop_3_11 loops_in2buf_1 ( + .clk(clk), + .clk_en(clk_en), + .dimensionality(loops_in2buf_1_dimensionality), + .flush(flush), + .ranges(loops_in2buf_1_ranges), + .rst_n(rst_n), + .step(agg_write[1]), + .mux_sel_out(loops_in2buf_1_mux_sel_out), + .restart(loops_in2buf_1_restart) +); + +addr_gen_3_3 agg_write_addr_gen_1 ( + .clk(clk), + .clk_en(clk_en), + .flush(flush), + .mux_sel(loops_in2buf_1_mux_sel_out), + .restart(loops_in2buf_1_restart), + .rst_n(rst_n), + .starting_addr(agg_write_addr_gen_1_starting_addr), + .step(agg_write[1]), + .strides(agg_write_addr_gen_1_strides), + .addr_out(agg_write_addr_gen_1_addr_out) +); + +sched_gen_3_16 agg_write_sched_gen_1 ( + .clk(clk), + .clk_en(clk_en), + .cycle_count(cycle_count), + .enable(agg_write_sched_gen_1_enable), + .finished(loops_in2buf_1_restart), + .flush(flush), + .mux_sel(loops_in2buf_1_mux_sel_out), + .rst_n(rst_n), + .sched_addr_gen_starting_addr(agg_write_sched_gen_1_sched_addr_gen_starting_addr), + .sched_addr_gen_strides_0(agg_write_sched_gen_1_sched_addr_gen_strides_0), + .sched_addr_gen_strides_1(agg_write_sched_gen_1_sched_addr_gen_strides_1), + .sched_addr_gen_strides_2(agg_write_sched_gen_1_sched_addr_gen_strides_2), + .valid_output(agg_write_sched_gen_1_valid_output) +); + +endmodule // strg_ub_agg_only + +module strg_ub_agg_sram_shared ( + input logic [7:0] agg_read_sched_gen_0_agg_read_padding, + input logic [7:0] agg_read_sched_gen_1_agg_read_padding, + input logic [8:0] agg_sram_shared_addr_gen_0_starting_addr, + input logic [8:0] agg_sram_shared_addr_gen_1_starting_addr, + input logic [1:0] [1:0] agg_write_addr_l2b_in, + input logic [1:0] agg_write_in, + input logic [1:0] [2:0] agg_write_mux_sel_in, + input logic [1:0] agg_write_restart_in, + input logic clk, + input logic clk_en, + input logic flush, + input logic [1:0] mode_0, + input logic [1:0] mode_1, + input logic rst_n, + input logic [1:0] [8:0] sram_read_addr_in, + input logic [1:0] sram_read_d_in, + input logic [1:0] sram_read_in, + output logic [1:0] agg_read_out, + output logic [1:0] [8:0] agg_sram_shared_addr_out, + output logic [1:0] [1:0] update_mode_out +); + +logic [1:0] agg_read; +logic agg_read_sched_gen_0_valid_output; +logic agg_read_sched_gen_1_valid_output; +logic [8:0] agg_sram_shared_addr_gen_0_addr_out; +logic [8:0] agg_sram_shared_addr_gen_1_addr_out; +assign agg_read_out = agg_read; +assign update_mode_out[0] = mode_0; +assign agg_read[0] = agg_read_sched_gen_0_valid_output; +assign agg_sram_shared_addr_out[0] = agg_sram_shared_addr_gen_0_addr_out; +assign update_mode_out[1] = mode_1; +assign agg_read[1] = agg_read_sched_gen_1_valid_output; +assign agg_sram_shared_addr_out[1] = agg_sram_shared_addr_gen_1_addr_out; +agg_sram_shared_sched_gen agg_read_sched_gen_0 ( + .agg_read_padding(agg_read_sched_gen_0_agg_read_padding), + .agg_write(agg_write_in[0]), + .agg_write_addr_l2b(agg_write_addr_l2b_in[0]), + .agg_write_mux_sel(agg_write_mux_sel_in[0]), + .agg_write_restart(agg_write_restart_in[0]), + .clk(clk), + .clk_en(clk_en), + .flush(flush), + .mode(mode_0), + .rst_n(rst_n), + .sram_read_d(sram_read_d_in), + .valid_output(agg_read_sched_gen_0_valid_output) +); + +agg_sram_shared_addr_gen agg_sram_shared_addr_gen_0 ( + .clk(clk), + .clk_en(clk_en), + .flush(flush), + .mode(mode_0), + .rst_n(rst_n), + .sram_read(sram_read_in), + .sram_read_addr(sram_read_addr_in), + .starting_addr(agg_sram_shared_addr_gen_0_starting_addr), + .step(agg_read[0]), + .addr_out(agg_sram_shared_addr_gen_0_addr_out) +); + +agg_sram_shared_sched_gen agg_read_sched_gen_1 ( + .agg_read_padding(agg_read_sched_gen_1_agg_read_padding), + .agg_write(agg_write_in[1]), + .agg_write_addr_l2b(agg_write_addr_l2b_in[1]), + .agg_write_mux_sel(agg_write_mux_sel_in[1]), + .agg_write_restart(agg_write_restart_in[1]), + .clk(clk), + .clk_en(clk_en), + .flush(flush), + .mode(mode_1), + .rst_n(rst_n), + .sram_read_d(sram_read_d_in), + .valid_output(agg_read_sched_gen_1_valid_output) +); + +agg_sram_shared_addr_gen agg_sram_shared_addr_gen_1 ( + .clk(clk), + .clk_en(clk_en), + .flush(flush), + .mode(mode_1), + .rst_n(rst_n), + .sram_read(sram_read_in), + .sram_read_addr(sram_read_addr_in), + .starting_addr(agg_sram_shared_addr_gen_1_starting_addr), + .step(agg_read[1]), + .addr_out(agg_sram_shared_addr_gen_1_addr_out) +); + +endmodule // strg_ub_agg_sram_shared + +module strg_ub_sram_only ( + input logic [1:0][3:0] [15:0] agg_data_out, + input logic [1:0] agg_read, + input logic clk, + input logic clk_en, + input logic [15:0] cycle_count, + input logic flush, + input logic [1:0] [2:0] loops_sram2tb_mux_sel, + input logic [1:0] loops_sram2tb_restart, + input logic [8:0] output_addr_gen_0_starting_addr, + input logic [8:0] output_addr_gen_0_strides_0, + input logic [8:0] output_addr_gen_0_strides_1, + input logic [8:0] output_addr_gen_0_strides_2, + input logic [8:0] output_addr_gen_0_strides_3, + input logic [8:0] output_addr_gen_0_strides_4, + input logic [8:0] output_addr_gen_0_strides_5, + input logic [8:0] output_addr_gen_1_starting_addr, + input logic [8:0] output_addr_gen_1_strides_0, + input logic [8:0] output_addr_gen_1_strides_1, + input logic [8:0] output_addr_gen_1_strides_2, + input logic [8:0] output_addr_gen_1_strides_3, + input logic [8:0] output_addr_gen_1_strides_4, + input logic [8:0] output_addr_gen_1_strides_5, + input logic rst_n, + input logic [1:0] [8:0] sram_read_addr_in, + input logic [1:0] t_read, + output logic [8:0] addr_to_sram, + output logic cen_to_sram, + output logic [3:0] [15:0] data_to_sram, + output logic [1:0] [8:0] sram_read_addr_out, + output logic wen_to_sram +); + +logic [8:0] addr; +logic [3:0][15:0] decode_ret_agg_read_agg_data_out; +logic [15:0] decode_ret_agg_read_s_write_addr; +logic [15:0] decode_ret_t_read_s_read_addr; +logic decode_sel_done_agg_read_agg_data_out; +logic decode_sel_done_agg_read_s_write_addr; +logic decode_sel_done_t_read_s_read_addr; +logic [8:0] output_addr_gen_0_addr_out; +logic [5:0][8:0] output_addr_gen_0_strides; +logic [8:0] output_addr_gen_1_addr_out; +logic [5:0][8:0] output_addr_gen_1_strides; +logic read; +logic [1:0][15:0] s_read_addr; +logic [1:0][15:0] s_write_addr; +logic [3:0][15:0] sram_write_data; +logic write; +assign s_write_addr[0][8:0] = sram_read_addr_in[0]; +assign s_write_addr[0][15:9] = 7'h0; +assign s_write_addr[1][8:0] = sram_read_addr_in[1]; +assign s_write_addr[1][15:9] = 7'h0; +assign s_read_addr[0][8:0] = output_addr_gen_0_addr_out; +assign s_read_addr[0][15:9] = 7'h0; +assign sram_read_addr_out[0] = output_addr_gen_0_addr_out; +assign s_read_addr[1][8:0] = output_addr_gen_1_addr_out; +assign s_read_addr[1][15:9] = 7'h0; +assign sram_read_addr_out[1] = output_addr_gen_1_addr_out; +assign data_to_sram = sram_write_data; +assign wen_to_sram = write; +always_comb begin + decode_sel_done_agg_read_s_write_addr = 1'h0; + decode_ret_agg_read_s_write_addr = 16'h0; + for (int unsigned i = 0; i < 2; i += 1) begin + if ((~decode_sel_done_agg_read_s_write_addr) & agg_read[1'(i)]) begin + decode_ret_agg_read_s_write_addr = s_write_addr[1'(i)]; + decode_sel_done_agg_read_s_write_addr = 1'h1; + end + end +end +always_comb begin + decode_sel_done_t_read_s_read_addr = 1'h0; + decode_ret_t_read_s_read_addr = 16'h0; + for (int unsigned i = 0; i < 2; i += 1) begin + if ((~decode_sel_done_t_read_s_read_addr) & t_read[1'(i)]) begin + decode_ret_t_read_s_read_addr = s_read_addr[1'(i)]; + decode_sel_done_t_read_s_read_addr = 1'h1; + end + end +end +assign cen_to_sram = write | read; +assign addr_to_sram = addr; +always_comb begin + if (write) begin + addr = decode_ret_agg_read_s_write_addr[8:0]; + end + else addr = decode_ret_t_read_s_read_addr[8:0]; +end +assign write = |agg_read; +assign read = |t_read; +always_comb begin + decode_sel_done_agg_read_agg_data_out = 1'h0; + decode_ret_agg_read_agg_data_out = 64'h0; + for (int unsigned i = 0; i < 2; i += 1) begin + if ((~decode_sel_done_agg_read_agg_data_out) & agg_read[1'(i)]) begin + decode_ret_agg_read_agg_data_out = agg_data_out[1'(i)]; + decode_sel_done_agg_read_agg_data_out = 1'h1; + end + end +end +assign sram_write_data = decode_ret_agg_read_agg_data_out; +assign output_addr_gen_0_strides[0] = output_addr_gen_0_strides_0; +assign output_addr_gen_0_strides[1] = output_addr_gen_0_strides_1; +assign output_addr_gen_0_strides[2] = output_addr_gen_0_strides_2; +assign output_addr_gen_0_strides[3] = output_addr_gen_0_strides_3; +assign output_addr_gen_0_strides[4] = output_addr_gen_0_strides_4; +assign output_addr_gen_0_strides[5] = output_addr_gen_0_strides_5; +assign output_addr_gen_1_strides[0] = output_addr_gen_1_strides_0; +assign output_addr_gen_1_strides[1] = output_addr_gen_1_strides_1; +assign output_addr_gen_1_strides[2] = output_addr_gen_1_strides_2; +assign output_addr_gen_1_strides[3] = output_addr_gen_1_strides_3; +assign output_addr_gen_1_strides[4] = output_addr_gen_1_strides_4; +assign output_addr_gen_1_strides[5] = output_addr_gen_1_strides_5; +addr_gen_6_9 output_addr_gen_0 ( + .clk(clk), + .clk_en(clk_en), + .flush(flush), + .mux_sel(loops_sram2tb_mux_sel[0]), + .restart(loops_sram2tb_restart[0]), + .rst_n(rst_n), + .starting_addr(output_addr_gen_0_starting_addr), + .step(t_read[0]), + .strides(output_addr_gen_0_strides), + .addr_out(output_addr_gen_0_addr_out) +); + +addr_gen_6_9 output_addr_gen_1 ( + .clk(clk), + .clk_en(clk_en), + .flush(flush), + .mux_sel(loops_sram2tb_mux_sel[1]), + .restart(loops_sram2tb_restart[1]), + .rst_n(rst_n), + .starting_addr(output_addr_gen_1_starting_addr), + .step(t_read[1]), + .strides(output_addr_gen_1_strides), + .addr_out(output_addr_gen_1_addr_out) +); + +endmodule // strg_ub_sram_only + +module strg_ub_sram_tb_shared ( + input logic clk, + input logic clk_en, + input logic [15:0] cycle_count, + input logic flush, + input logic [3:0] loops_buf2out_autovec_read_0_dimensionality, + input logic [10:0] loops_buf2out_autovec_read_0_ranges_0, + input logic [10:0] loops_buf2out_autovec_read_0_ranges_1, + input logic [10:0] loops_buf2out_autovec_read_0_ranges_2, + input logic [10:0] loops_buf2out_autovec_read_0_ranges_3, + input logic [10:0] loops_buf2out_autovec_read_0_ranges_4, + input logic [10:0] loops_buf2out_autovec_read_0_ranges_5, + input logic [3:0] loops_buf2out_autovec_read_1_dimensionality, + input logic [10:0] loops_buf2out_autovec_read_1_ranges_0, + input logic [10:0] loops_buf2out_autovec_read_1_ranges_1, + input logic [10:0] loops_buf2out_autovec_read_1_ranges_2, + input logic [10:0] loops_buf2out_autovec_read_1_ranges_3, + input logic [10:0] loops_buf2out_autovec_read_1_ranges_4, + input logic [10:0] loops_buf2out_autovec_read_1_ranges_5, + input logic output_sched_gen_0_enable, + input logic [9:0] output_sched_gen_0_sched_addr_gen_delay, + input logic [15:0] output_sched_gen_0_sched_addr_gen_starting_addr, + input logic [15:0] output_sched_gen_0_sched_addr_gen_strides_0, + input logic [15:0] output_sched_gen_0_sched_addr_gen_strides_1, + input logic [15:0] output_sched_gen_0_sched_addr_gen_strides_2, + input logic [15:0] output_sched_gen_0_sched_addr_gen_strides_3, + input logic [15:0] output_sched_gen_0_sched_addr_gen_strides_4, + input logic [15:0] output_sched_gen_0_sched_addr_gen_strides_5, + input logic output_sched_gen_1_enable, + input logic [9:0] output_sched_gen_1_sched_addr_gen_delay, + input logic [15:0] output_sched_gen_1_sched_addr_gen_starting_addr, + input logic [15:0] output_sched_gen_1_sched_addr_gen_strides_0, + input logic [15:0] output_sched_gen_1_sched_addr_gen_strides_1, + input logic [15:0] output_sched_gen_1_sched_addr_gen_strides_2, + input logic [15:0] output_sched_gen_1_sched_addr_gen_strides_3, + input logic [15:0] output_sched_gen_1_sched_addr_gen_strides_4, + input logic [15:0] output_sched_gen_1_sched_addr_gen_strides_5, + input logic rst_n, + output logic [1:0] [2:0] loops_sram2tb_mux_sel, + output logic [1:0] loops_sram2tb_restart, + output logic [1:0] sram_read_d, + output logic [1:0] t_read_out +); + +logic [2:0] loops_buf2out_autovec_read_0_mux_sel_out; +logic [5:0][10:0] loops_buf2out_autovec_read_0_ranges; +logic loops_buf2out_autovec_read_0_restart; +logic [2:0] loops_buf2out_autovec_read_1_mux_sel_out; +logic [5:0][10:0] loops_buf2out_autovec_read_1_ranges; +logic loops_buf2out_autovec_read_1_restart; +logic output_sched_gen_0_valid_output; +logic output_sched_gen_0_valid_output_d; +logic output_sched_gen_1_valid_output; +logic output_sched_gen_1_valid_output_d; +logic [1:0] t_read; +assign t_read_out = t_read; +assign loops_sram2tb_mux_sel[0] = loops_buf2out_autovec_read_0_mux_sel_out; +assign loops_sram2tb_restart[0] = loops_buf2out_autovec_read_0_restart; +assign t_read[0] = output_sched_gen_0_valid_output; +assign sram_read_d[0] = output_sched_gen_0_valid_output_d; +assign loops_sram2tb_mux_sel[1] = loops_buf2out_autovec_read_1_mux_sel_out; +assign loops_sram2tb_restart[1] = loops_buf2out_autovec_read_1_restart; +assign t_read[1] = output_sched_gen_1_valid_output; +assign sram_read_d[1] = output_sched_gen_1_valid_output_d; +assign loops_buf2out_autovec_read_0_ranges[0] = loops_buf2out_autovec_read_0_ranges_0; +assign loops_buf2out_autovec_read_0_ranges[1] = loops_buf2out_autovec_read_0_ranges_1; +assign loops_buf2out_autovec_read_0_ranges[2] = loops_buf2out_autovec_read_0_ranges_2; +assign loops_buf2out_autovec_read_0_ranges[3] = loops_buf2out_autovec_read_0_ranges_3; +assign loops_buf2out_autovec_read_0_ranges[4] = loops_buf2out_autovec_read_0_ranges_4; +assign loops_buf2out_autovec_read_0_ranges[5] = loops_buf2out_autovec_read_0_ranges_5; +assign loops_buf2out_autovec_read_1_ranges[0] = loops_buf2out_autovec_read_1_ranges_0; +assign loops_buf2out_autovec_read_1_ranges[1] = loops_buf2out_autovec_read_1_ranges_1; +assign loops_buf2out_autovec_read_1_ranges[2] = loops_buf2out_autovec_read_1_ranges_2; +assign loops_buf2out_autovec_read_1_ranges[3] = loops_buf2out_autovec_read_1_ranges_3; +assign loops_buf2out_autovec_read_1_ranges[4] = loops_buf2out_autovec_read_1_ranges_4; +assign loops_buf2out_autovec_read_1_ranges[5] = loops_buf2out_autovec_read_1_ranges_5; +for_loop_6_11 loops_buf2out_autovec_read_0 ( + .clk(clk), + .clk_en(clk_en), + .dimensionality(loops_buf2out_autovec_read_0_dimensionality), + .flush(flush), + .ranges(loops_buf2out_autovec_read_0_ranges), + .rst_n(rst_n), + .step(t_read[0]), + .mux_sel_out(loops_buf2out_autovec_read_0_mux_sel_out), + .restart(loops_buf2out_autovec_read_0_restart) +); + +sched_gen_6_16_delay_addr_10_4 output_sched_gen_0 ( + .clk(clk), + .clk_en(clk_en), + .cycle_count(cycle_count), + .enable(output_sched_gen_0_enable), + .finished(loops_buf2out_autovec_read_0_restart), + .flush(flush), + .mux_sel(loops_buf2out_autovec_read_0_mux_sel_out), + .rst_n(rst_n), + .sched_addr_gen_delay(output_sched_gen_0_sched_addr_gen_delay), + .sched_addr_gen_starting_addr(output_sched_gen_0_sched_addr_gen_starting_addr), + .sched_addr_gen_strides_0(output_sched_gen_0_sched_addr_gen_strides_0), + .sched_addr_gen_strides_1(output_sched_gen_0_sched_addr_gen_strides_1), + .sched_addr_gen_strides_2(output_sched_gen_0_sched_addr_gen_strides_2), + .sched_addr_gen_strides_3(output_sched_gen_0_sched_addr_gen_strides_3), + .sched_addr_gen_strides_4(output_sched_gen_0_sched_addr_gen_strides_4), + .sched_addr_gen_strides_5(output_sched_gen_0_sched_addr_gen_strides_5), + .valid_output(output_sched_gen_0_valid_output), + .valid_output_d(output_sched_gen_0_valid_output_d) +); + +for_loop_6_11 loops_buf2out_autovec_read_1 ( + .clk(clk), + .clk_en(clk_en), + .dimensionality(loops_buf2out_autovec_read_1_dimensionality), + .flush(flush), + .ranges(loops_buf2out_autovec_read_1_ranges), + .rst_n(rst_n), + .step(t_read[1]), + .mux_sel_out(loops_buf2out_autovec_read_1_mux_sel_out), + .restart(loops_buf2out_autovec_read_1_restart) +); + +sched_gen_6_16_delay_addr_10_4 output_sched_gen_1 ( + .clk(clk), + .clk_en(clk_en), + .cycle_count(cycle_count), + .enable(output_sched_gen_1_enable), + .finished(loops_buf2out_autovec_read_1_restart), + .flush(flush), + .mux_sel(loops_buf2out_autovec_read_1_mux_sel_out), + .rst_n(rst_n), + .sched_addr_gen_delay(output_sched_gen_1_sched_addr_gen_delay), + .sched_addr_gen_starting_addr(output_sched_gen_1_sched_addr_gen_starting_addr), + .sched_addr_gen_strides_0(output_sched_gen_1_sched_addr_gen_strides_0), + .sched_addr_gen_strides_1(output_sched_gen_1_sched_addr_gen_strides_1), + .sched_addr_gen_strides_2(output_sched_gen_1_sched_addr_gen_strides_2), + .sched_addr_gen_strides_3(output_sched_gen_1_sched_addr_gen_strides_3), + .sched_addr_gen_strides_4(output_sched_gen_1_sched_addr_gen_strides_4), + .sched_addr_gen_strides_5(output_sched_gen_1_sched_addr_gen_strides_5), + .valid_output(output_sched_gen_1_valid_output), + .valid_output_d(output_sched_gen_1_valid_output_d) +); + +endmodule // strg_ub_sram_tb_shared + +module strg_ub_tb_only ( + input logic clk, + input logic clk_en, + input logic [15:0] cycle_count, + input logic flush, + input logic [3:0] loops_buf2out_read_0_dimensionality, + input logic [10:0] loops_buf2out_read_0_ranges_0, + input logic [10:0] loops_buf2out_read_0_ranges_1, + input logic [10:0] loops_buf2out_read_0_ranges_2, + input logic [10:0] loops_buf2out_read_0_ranges_3, + input logic [10:0] loops_buf2out_read_0_ranges_4, + input logic [10:0] loops_buf2out_read_0_ranges_5, + input logic [3:0] loops_buf2out_read_1_dimensionality, + input logic [10:0] loops_buf2out_read_1_ranges_0, + input logic [10:0] loops_buf2out_read_1_ranges_1, + input logic [10:0] loops_buf2out_read_1_ranges_2, + input logic [10:0] loops_buf2out_read_1_ranges_3, + input logic [10:0] loops_buf2out_read_1_ranges_4, + input logic [10:0] loops_buf2out_read_1_ranges_5, + input logic [1:0] [2:0] loops_sram2tb_mux_sel, + input logic [1:0] loops_sram2tb_restart, + input logic rst_n, + input logic shared_tb_0, + input logic [3:0] [15:0] sram_read_data, + input logic [1:0] t_read, + input logic [3:0] tb_read_addr_gen_0_starting_addr, + input logic [3:0] tb_read_addr_gen_0_strides_0, + input logic [3:0] tb_read_addr_gen_0_strides_1, + input logic [3:0] tb_read_addr_gen_0_strides_2, + input logic [3:0] tb_read_addr_gen_0_strides_3, + input logic [3:0] tb_read_addr_gen_0_strides_4, + input logic [3:0] tb_read_addr_gen_0_strides_5, + input logic [3:0] tb_read_addr_gen_1_starting_addr, + input logic [3:0] tb_read_addr_gen_1_strides_0, + input logic [3:0] tb_read_addr_gen_1_strides_1, + input logic [3:0] tb_read_addr_gen_1_strides_2, + input logic [3:0] tb_read_addr_gen_1_strides_3, + input logic [3:0] tb_read_addr_gen_1_strides_4, + input logic [3:0] tb_read_addr_gen_1_strides_5, + input logic tb_read_sched_gen_0_enable, + input logic [9:0] tb_read_sched_gen_0_sched_addr_gen_delay, + input logic [15:0] tb_read_sched_gen_0_sched_addr_gen_starting_addr, + input logic [15:0] tb_read_sched_gen_0_sched_addr_gen_strides_0, + input logic [15:0] tb_read_sched_gen_0_sched_addr_gen_strides_1, + input logic [15:0] tb_read_sched_gen_0_sched_addr_gen_strides_2, + input logic [15:0] tb_read_sched_gen_0_sched_addr_gen_strides_3, + input logic [15:0] tb_read_sched_gen_0_sched_addr_gen_strides_4, + input logic [15:0] tb_read_sched_gen_0_sched_addr_gen_strides_5, + input logic tb_read_sched_gen_1_enable, + input logic [9:0] tb_read_sched_gen_1_sched_addr_gen_delay, + input logic [15:0] tb_read_sched_gen_1_sched_addr_gen_starting_addr, + input logic [15:0] tb_read_sched_gen_1_sched_addr_gen_strides_0, + input logic [15:0] tb_read_sched_gen_1_sched_addr_gen_strides_1, + input logic [15:0] tb_read_sched_gen_1_sched_addr_gen_strides_2, + input logic [15:0] tb_read_sched_gen_1_sched_addr_gen_strides_3, + input logic [15:0] tb_read_sched_gen_1_sched_addr_gen_strides_4, + input logic [15:0] tb_read_sched_gen_1_sched_addr_gen_strides_5, + input logic [3:0] tb_write_addr_gen_0_starting_addr, + input logic [3:0] tb_write_addr_gen_0_strides_0, + input logic [3:0] tb_write_addr_gen_0_strides_1, + input logic [3:0] tb_write_addr_gen_0_strides_2, + input logic [3:0] tb_write_addr_gen_0_strides_3, + input logic [3:0] tb_write_addr_gen_0_strides_4, + input logic [3:0] tb_write_addr_gen_0_strides_5, + input logic [3:0] tb_write_addr_gen_1_starting_addr, + input logic [3:0] tb_write_addr_gen_1_strides_0, + input logic [3:0] tb_write_addr_gen_1_strides_1, + input logic [3:0] tb_write_addr_gen_1_strides_2, + input logic [3:0] tb_write_addr_gen_1_strides_3, + input logic [3:0] tb_write_addr_gen_1_strides_4, + input logic [3:0] tb_write_addr_gen_1_strides_5, + output logic [1:0] accessor_output, + output logic [1:0] [15:0] data_out, + output logic [1:0] [2:0] tb_read_addr_d_out, + output logic [1:0] tb_read_d_out +); + +logic [2:0] addr_fifo_in_0; +logic [2:0] addr_fifo_in_1; +logic delay_en_0; +logic delay_en_1; +logic [2:0] loops_buf2out_read_0_mux_sel_out; +logic [5:0][10:0] loops_buf2out_read_0_ranges; +logic loops_buf2out_read_0_restart; +logic [2:0] loops_buf2out_read_1_mux_sel_out; +logic [5:0][10:0] loops_buf2out_read_1_ranges; +logic loops_buf2out_read_1_restart; +logic [1:0][2:0] mux_sel_d1; +logic [2:0] rd_ptr_0; +logic [2:0] rd_ptr_1; +logic [1:0] restart_d1; +logic [1:0] t_read_d1; +logic [1:0][1:0][3:0][15:0] tb; +logic [7:0][2:0] tb_addr_fifo_0; +logic [7:0][2:0] tb_addr_fifo_1; +logic [1:0] tb_read; +logic [1:0][3:0] tb_read_addr; +logic [3:0] tb_read_addr_gen_0_addr_out; +logic [5:0][3:0] tb_read_addr_gen_0_strides; +logic [3:0] tb_read_addr_gen_1_addr_out; +logic [5:0][3:0] tb_read_addr_gen_1_strides; +logic tb_read_d_0; +logic tb_read_d_1; +logic tb_read_sched_gen_0_valid_output; +logic tb_read_sched_gen_1_valid_output; +logic tb_read_sel_0; +logic [1:0][2:0] tb_write_addr; +logic [3:0] tb_write_addr_gen_0_addr_out; +logic [5:0][3:0] tb_write_addr_gen_0_strides; +logic [3:0] tb_write_addr_gen_1_addr_out; +logic [5:0][3:0] tb_write_addr_gen_1_strides; +logic tb_write_sel_0; +logic [2:0] wr_ptr_0; +logic [2:0] wr_ptr_1; +assign accessor_output = tb_read; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + t_read_d1[0] <= 1'h0; + mux_sel_d1[0] <= 3'h0; + restart_d1[0] <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + t_read_d1[0] <= 1'h0; + mux_sel_d1[0] <= 3'h0; + restart_d1[0] <= 1'h0; + end + else begin + t_read_d1[0] <= t_read[0]; + mux_sel_d1[0] <= loops_sram2tb_mux_sel[0]; + restart_d1[0] <= loops_sram2tb_restart[0]; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + t_read_d1[1] <= 1'h0; + mux_sel_d1[1] <= 3'h0; + restart_d1[1] <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + t_read_d1[1] <= 1'h0; + mux_sel_d1[1] <= 3'h0; + restart_d1[1] <= 1'h0; + end + else begin + t_read_d1[1] <= t_read[1]; + mux_sel_d1[1] <= loops_sram2tb_mux_sel[1]; + restart_d1[1] <= loops_sram2tb_restart[1]; + end + end +end +assign tb_write_sel_0 = shared_tb_0 ? tb_write_addr[0][1]: 1'h0; +assign tb_read_sel_0 = shared_tb_0 ? tb_read_addr[0][3]: 1'h0; +assign tb_write_addr[0] = tb_write_addr_gen_0_addr_out[2:0]; +assign tb_read_addr[0] = tb_read_addr_gen_0_addr_out; +assign tb_read[0] = tb_read_sched_gen_0_valid_output; +assign addr_fifo_in_0 = tb_read_addr_gen_0_addr_out[2:0]; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + wr_ptr_0 <= 3'h0; + rd_ptr_0 <= 3'h0; + tb_addr_fifo_0 <= 24'h0; + end + else if (clk_en) begin + if (flush) begin + wr_ptr_0 <= 3'h0; + rd_ptr_0 <= 3'h0; + tb_addr_fifo_0 <= 24'h0; + end + else if (delay_en_0) begin + if (tb_read[0]) begin + tb_addr_fifo_0[wr_ptr_0] <= addr_fifo_in_0; + wr_ptr_0 <= wr_ptr_0 + 3'h1; + end + if (tb_read_d_0) begin + rd_ptr_0 <= rd_ptr_0 + 3'h1; + end + end + end +end +assign tb_read_d_out[0] = delay_en_0 ? tb_read_d_0: tb_read[0]; +assign tb_read_addr_d_out[0] = delay_en_0 ? tb_addr_fifo_0[rd_ptr_0]: addr_fifo_in_0; +always_comb begin + data_out[0] = tb[tb_read_sel_0][tb_read_addr[0][2]][tb_read_addr[0][1:0]]; +end +assign tb_write_addr[1] = tb_write_addr_gen_1_addr_out[2:0]; +assign tb_read_addr[1] = tb_read_addr_gen_1_addr_out; +assign tb_read[1] = tb_read_sched_gen_1_valid_output; +assign addr_fifo_in_1 = tb_read_addr_gen_1_addr_out[2:0]; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + wr_ptr_1 <= 3'h0; + rd_ptr_1 <= 3'h0; + tb_addr_fifo_1 <= 24'h0; + end + else if (clk_en) begin + if (flush) begin + wr_ptr_1 <= 3'h0; + rd_ptr_1 <= 3'h0; + tb_addr_fifo_1 <= 24'h0; + end + else if (delay_en_1) begin + if (tb_read[1]) begin + tb_addr_fifo_1[wr_ptr_1] <= addr_fifo_in_1; + wr_ptr_1 <= wr_ptr_1 + 3'h1; + end + if (tb_read_d_1) begin + rd_ptr_1 <= rd_ptr_1 + 3'h1; + end + end + end +end +assign tb_read_d_out[1] = delay_en_1 ? tb_read_d_1: tb_read[1]; +assign tb_read_addr_d_out[1] = delay_en_1 ? tb_addr_fifo_1[rd_ptr_1]: addr_fifo_in_1; +always_comb begin + data_out[1] = tb[1][tb_read_addr[1][2]][tb_read_addr[1][1:0]]; +end + +always_ff @(posedge clk) begin + if (clk_en) begin + for (int unsigned i = 0; i < 2; i += 1) begin + if (t_read_d1[1'(i)]) begin + if (i == 32'h0) begin + tb[tb_write_sel_0][tb_write_addr[1'(i)][0]] <= sram_read_data; + end + else tb[1'(i)][tb_write_addr[1'(i)][0]] <= sram_read_data; + end + end + end +end +assign tb_write_addr_gen_0_strides[0] = tb_write_addr_gen_0_strides_0; +assign tb_write_addr_gen_0_strides[1] = tb_write_addr_gen_0_strides_1; +assign tb_write_addr_gen_0_strides[2] = tb_write_addr_gen_0_strides_2; +assign tb_write_addr_gen_0_strides[3] = tb_write_addr_gen_0_strides_3; +assign tb_write_addr_gen_0_strides[4] = tb_write_addr_gen_0_strides_4; +assign tb_write_addr_gen_0_strides[5] = tb_write_addr_gen_0_strides_5; +assign loops_buf2out_read_0_ranges[0] = loops_buf2out_read_0_ranges_0; +assign loops_buf2out_read_0_ranges[1] = loops_buf2out_read_0_ranges_1; +assign loops_buf2out_read_0_ranges[2] = loops_buf2out_read_0_ranges_2; +assign loops_buf2out_read_0_ranges[3] = loops_buf2out_read_0_ranges_3; +assign loops_buf2out_read_0_ranges[4] = loops_buf2out_read_0_ranges_4; +assign loops_buf2out_read_0_ranges[5] = loops_buf2out_read_0_ranges_5; +assign tb_read_addr_gen_0_strides[0] = tb_read_addr_gen_0_strides_0; +assign tb_read_addr_gen_0_strides[1] = tb_read_addr_gen_0_strides_1; +assign tb_read_addr_gen_0_strides[2] = tb_read_addr_gen_0_strides_2; +assign tb_read_addr_gen_0_strides[3] = tb_read_addr_gen_0_strides_3; +assign tb_read_addr_gen_0_strides[4] = tb_read_addr_gen_0_strides_4; +assign tb_read_addr_gen_0_strides[5] = tb_read_addr_gen_0_strides_5; +assign tb_write_addr_gen_1_strides[0] = tb_write_addr_gen_1_strides_0; +assign tb_write_addr_gen_1_strides[1] = tb_write_addr_gen_1_strides_1; +assign tb_write_addr_gen_1_strides[2] = tb_write_addr_gen_1_strides_2; +assign tb_write_addr_gen_1_strides[3] = tb_write_addr_gen_1_strides_3; +assign tb_write_addr_gen_1_strides[4] = tb_write_addr_gen_1_strides_4; +assign tb_write_addr_gen_1_strides[5] = tb_write_addr_gen_1_strides_5; +assign loops_buf2out_read_1_ranges[0] = loops_buf2out_read_1_ranges_0; +assign loops_buf2out_read_1_ranges[1] = loops_buf2out_read_1_ranges_1; +assign loops_buf2out_read_1_ranges[2] = loops_buf2out_read_1_ranges_2; +assign loops_buf2out_read_1_ranges[3] = loops_buf2out_read_1_ranges_3; +assign loops_buf2out_read_1_ranges[4] = loops_buf2out_read_1_ranges_4; +assign loops_buf2out_read_1_ranges[5] = loops_buf2out_read_1_ranges_5; +assign tb_read_addr_gen_1_strides[0] = tb_read_addr_gen_1_strides_0; +assign tb_read_addr_gen_1_strides[1] = tb_read_addr_gen_1_strides_1; +assign tb_read_addr_gen_1_strides[2] = tb_read_addr_gen_1_strides_2; +assign tb_read_addr_gen_1_strides[3] = tb_read_addr_gen_1_strides_3; +assign tb_read_addr_gen_1_strides[4] = tb_read_addr_gen_1_strides_4; +assign tb_read_addr_gen_1_strides[5] = tb_read_addr_gen_1_strides_5; +addr_gen_6_4 tb_write_addr_gen_0 ( + .clk(clk), + .clk_en(clk_en), + .flush(flush), + .mux_sel(mux_sel_d1[0]), + .restart(restart_d1[0]), + .rst_n(rst_n), + .starting_addr(tb_write_addr_gen_0_starting_addr), + .step(t_read_d1[0]), + .strides(tb_write_addr_gen_0_strides), + .addr_out(tb_write_addr_gen_0_addr_out) +); + +for_loop_6_11 loops_buf2out_read_0 ( + .clk(clk), + .clk_en(clk_en), + .dimensionality(loops_buf2out_read_0_dimensionality), + .flush(flush), + .ranges(loops_buf2out_read_0_ranges), + .rst_n(rst_n), + .step(tb_read[0]), + .mux_sel_out(loops_buf2out_read_0_mux_sel_out), + .restart(loops_buf2out_read_0_restart) +); + +addr_gen_6_4 tb_read_addr_gen_0 ( + .clk(clk), + .clk_en(clk_en), + .flush(flush), + .mux_sel(loops_buf2out_read_0_mux_sel_out), + .restart(loops_buf2out_read_0_restart), + .rst_n(rst_n), + .starting_addr(tb_read_addr_gen_0_starting_addr), + .step(tb_read[0]), + .strides(tb_read_addr_gen_0_strides), + .addr_out(tb_read_addr_gen_0_addr_out) +); + +sched_gen_6_16_delay_addr_10_8 tb_read_sched_gen_0 ( + .clk(clk), + .clk_en(clk_en), + .cycle_count(cycle_count), + .enable(tb_read_sched_gen_0_enable), + .finished(loops_buf2out_read_0_restart), + .flush(flush), + .mux_sel(loops_buf2out_read_0_mux_sel_out), + .rst_n(rst_n), + .sched_addr_gen_delay(tb_read_sched_gen_0_sched_addr_gen_delay), + .sched_addr_gen_starting_addr(tb_read_sched_gen_0_sched_addr_gen_starting_addr), + .sched_addr_gen_strides_0(tb_read_sched_gen_0_sched_addr_gen_strides_0), + .sched_addr_gen_strides_1(tb_read_sched_gen_0_sched_addr_gen_strides_1), + .sched_addr_gen_strides_2(tb_read_sched_gen_0_sched_addr_gen_strides_2), + .sched_addr_gen_strides_3(tb_read_sched_gen_0_sched_addr_gen_strides_3), + .sched_addr_gen_strides_4(tb_read_sched_gen_0_sched_addr_gen_strides_4), + .sched_addr_gen_strides_5(tb_read_sched_gen_0_sched_addr_gen_strides_5), + .delay_en_out(delay_en_0), + .valid_output(tb_read_sched_gen_0_valid_output), + .valid_output_d(tb_read_d_0) +); + +addr_gen_6_4 tb_write_addr_gen_1 ( + .clk(clk), + .clk_en(clk_en), + .flush(flush), + .mux_sel(mux_sel_d1[1]), + .restart(restart_d1[1]), + .rst_n(rst_n), + .starting_addr(tb_write_addr_gen_1_starting_addr), + .step(t_read_d1[1]), + .strides(tb_write_addr_gen_1_strides), + .addr_out(tb_write_addr_gen_1_addr_out) +); + +for_loop_6_11 loops_buf2out_read_1 ( + .clk(clk), + .clk_en(clk_en), + .dimensionality(loops_buf2out_read_1_dimensionality), + .flush(flush), + .ranges(loops_buf2out_read_1_ranges), + .rst_n(rst_n), + .step(tb_read[1]), + .mux_sel_out(loops_buf2out_read_1_mux_sel_out), + .restart(loops_buf2out_read_1_restart) +); + +addr_gen_6_4 tb_read_addr_gen_1 ( + .clk(clk), + .clk_en(clk_en), + .flush(flush), + .mux_sel(loops_buf2out_read_1_mux_sel_out), + .restart(loops_buf2out_read_1_restart), + .rst_n(rst_n), + .starting_addr(tb_read_addr_gen_1_starting_addr), + .step(tb_read[1]), + .strides(tb_read_addr_gen_1_strides), + .addr_out(tb_read_addr_gen_1_addr_out) +); + +sched_gen_6_16_delay_addr_10_8 tb_read_sched_gen_1 ( + .clk(clk), + .clk_en(clk_en), + .cycle_count(cycle_count), + .enable(tb_read_sched_gen_1_enable), + .finished(loops_buf2out_read_1_restart), + .flush(flush), + .mux_sel(loops_buf2out_read_1_mux_sel_out), + .rst_n(rst_n), + .sched_addr_gen_delay(tb_read_sched_gen_1_sched_addr_gen_delay), + .sched_addr_gen_starting_addr(tb_read_sched_gen_1_sched_addr_gen_starting_addr), + .sched_addr_gen_strides_0(tb_read_sched_gen_1_sched_addr_gen_strides_0), + .sched_addr_gen_strides_1(tb_read_sched_gen_1_sched_addr_gen_strides_1), + .sched_addr_gen_strides_2(tb_read_sched_gen_1_sched_addr_gen_strides_2), + .sched_addr_gen_strides_3(tb_read_sched_gen_1_sched_addr_gen_strides_3), + .sched_addr_gen_strides_4(tb_read_sched_gen_1_sched_addr_gen_strides_4), + .sched_addr_gen_strides_5(tb_read_sched_gen_1_sched_addr_gen_strides_5), + .delay_en_out(delay_en_1), + .valid_output(tb_read_sched_gen_1_valid_output), + .valid_output_d(tb_read_d_1) +); + +endmodule // strg_ub_tb_only + +module strg_ub_vec ( + input logic [2:0] agg_only_agg_write_addr_gen_0_starting_addr, + input logic [2:0] agg_only_agg_write_addr_gen_0_strides_0, + input logic [2:0] agg_only_agg_write_addr_gen_0_strides_1, + input logic [2:0] agg_only_agg_write_addr_gen_0_strides_2, + input logic [2:0] agg_only_agg_write_addr_gen_1_starting_addr, + input logic [2:0] agg_only_agg_write_addr_gen_1_strides_0, + input logic [2:0] agg_only_agg_write_addr_gen_1_strides_1, + input logic [2:0] agg_only_agg_write_addr_gen_1_strides_2, + input logic agg_only_agg_write_sched_gen_0_enable, + input logic [15:0] agg_only_agg_write_sched_gen_0_sched_addr_gen_starting_addr, + input logic [15:0] agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_0, + input logic [15:0] agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_1, + input logic [15:0] agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_2, + input logic agg_only_agg_write_sched_gen_1_enable, + input logic [15:0] agg_only_agg_write_sched_gen_1_sched_addr_gen_starting_addr, + input logic [15:0] agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_0, + input logic [15:0] agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_1, + input logic [15:0] agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_2, + input logic [2:0] agg_only_loops_in2buf_0_dimensionality, + input logic [10:0] agg_only_loops_in2buf_0_ranges_0, + input logic [10:0] agg_only_loops_in2buf_0_ranges_1, + input logic [10:0] agg_only_loops_in2buf_0_ranges_2, + input logic [2:0] agg_only_loops_in2buf_1_dimensionality, + input logic [10:0] agg_only_loops_in2buf_1_ranges_0, + input logic [10:0] agg_only_loops_in2buf_1_ranges_1, + input logic [10:0] agg_only_loops_in2buf_1_ranges_2, + input logic [7:0] agg_sram_shared_agg_read_sched_gen_0_agg_read_padding, + input logic [7:0] agg_sram_shared_agg_read_sched_gen_1_agg_read_padding, + input logic [8:0] agg_sram_shared_agg_sram_shared_addr_gen_0_starting_addr, + input logic [8:0] agg_sram_shared_agg_sram_shared_addr_gen_1_starting_addr, + input logic [1:0] agg_sram_shared_mode_0, + input logic [1:0] agg_sram_shared_mode_1, + input logic chain_chain_en, + input logic [1:0] [16:0] chain_data_in, + input logic clk, + input logic clk_en, + input logic [3:0] [15:0] data_from_strg, + input logic [1:0] [16:0] data_in, + input logic flush, + input logic rst_n, + input logic [8:0] sram_only_output_addr_gen_0_starting_addr, + input logic [8:0] sram_only_output_addr_gen_0_strides_0, + input logic [8:0] sram_only_output_addr_gen_0_strides_1, + input logic [8:0] sram_only_output_addr_gen_0_strides_2, + input logic [8:0] sram_only_output_addr_gen_0_strides_3, + input logic [8:0] sram_only_output_addr_gen_0_strides_4, + input logic [8:0] sram_only_output_addr_gen_0_strides_5, + input logic [8:0] sram_only_output_addr_gen_1_starting_addr, + input logic [8:0] sram_only_output_addr_gen_1_strides_0, + input logic [8:0] sram_only_output_addr_gen_1_strides_1, + input logic [8:0] sram_only_output_addr_gen_1_strides_2, + input logic [8:0] sram_only_output_addr_gen_1_strides_3, + input logic [8:0] sram_only_output_addr_gen_1_strides_4, + input logic [8:0] sram_only_output_addr_gen_1_strides_5, + input logic [3:0] sram_tb_shared_loops_buf2out_autovec_read_0_dimensionality, + input logic [10:0] sram_tb_shared_loops_buf2out_autovec_read_0_ranges_0, + input logic [10:0] sram_tb_shared_loops_buf2out_autovec_read_0_ranges_1, + input logic [10:0] sram_tb_shared_loops_buf2out_autovec_read_0_ranges_2, + input logic [10:0] sram_tb_shared_loops_buf2out_autovec_read_0_ranges_3, + input logic [10:0] sram_tb_shared_loops_buf2out_autovec_read_0_ranges_4, + input logic [10:0] sram_tb_shared_loops_buf2out_autovec_read_0_ranges_5, + input logic [3:0] sram_tb_shared_loops_buf2out_autovec_read_1_dimensionality, + input logic [10:0] sram_tb_shared_loops_buf2out_autovec_read_1_ranges_0, + input logic [10:0] sram_tb_shared_loops_buf2out_autovec_read_1_ranges_1, + input logic [10:0] sram_tb_shared_loops_buf2out_autovec_read_1_ranges_2, + input logic [10:0] sram_tb_shared_loops_buf2out_autovec_read_1_ranges_3, + input logic [10:0] sram_tb_shared_loops_buf2out_autovec_read_1_ranges_4, + input logic [10:0] sram_tb_shared_loops_buf2out_autovec_read_1_ranges_5, + input logic sram_tb_shared_output_sched_gen_0_enable, + input logic [9:0] sram_tb_shared_output_sched_gen_0_sched_addr_gen_delay, + input logic [15:0] sram_tb_shared_output_sched_gen_0_sched_addr_gen_starting_addr, + input logic [15:0] sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_0, + input logic [15:0] sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_1, + input logic [15:0] sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_2, + input logic [15:0] sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_3, + input logic [15:0] sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_4, + input logic [15:0] sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_5, + input logic sram_tb_shared_output_sched_gen_1_enable, + input logic [9:0] sram_tb_shared_output_sched_gen_1_sched_addr_gen_delay, + input logic [15:0] sram_tb_shared_output_sched_gen_1_sched_addr_gen_starting_addr, + input logic [15:0] sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_0, + input logic [15:0] sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_1, + input logic [15:0] sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_2, + input logic [15:0] sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_3, + input logic [15:0] sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_4, + input logic [15:0] sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_5, + input logic [3:0] tb_only_loops_buf2out_read_0_dimensionality, + input logic [10:0] tb_only_loops_buf2out_read_0_ranges_0, + input logic [10:0] tb_only_loops_buf2out_read_0_ranges_1, + input logic [10:0] tb_only_loops_buf2out_read_0_ranges_2, + input logic [10:0] tb_only_loops_buf2out_read_0_ranges_3, + input logic [10:0] tb_only_loops_buf2out_read_0_ranges_4, + input logic [10:0] tb_only_loops_buf2out_read_0_ranges_5, + input logic [3:0] tb_only_loops_buf2out_read_1_dimensionality, + input logic [10:0] tb_only_loops_buf2out_read_1_ranges_0, + input logic [10:0] tb_only_loops_buf2out_read_1_ranges_1, + input logic [10:0] tb_only_loops_buf2out_read_1_ranges_2, + input logic [10:0] tb_only_loops_buf2out_read_1_ranges_3, + input logic [10:0] tb_only_loops_buf2out_read_1_ranges_4, + input logic [10:0] tb_only_loops_buf2out_read_1_ranges_5, + input logic tb_only_shared_tb_0, + input logic [3:0] tb_only_tb_read_addr_gen_0_starting_addr, + input logic [3:0] tb_only_tb_read_addr_gen_0_strides_0, + input logic [3:0] tb_only_tb_read_addr_gen_0_strides_1, + input logic [3:0] tb_only_tb_read_addr_gen_0_strides_2, + input logic [3:0] tb_only_tb_read_addr_gen_0_strides_3, + input logic [3:0] tb_only_tb_read_addr_gen_0_strides_4, + input logic [3:0] tb_only_tb_read_addr_gen_0_strides_5, + input logic [3:0] tb_only_tb_read_addr_gen_1_starting_addr, + input logic [3:0] tb_only_tb_read_addr_gen_1_strides_0, + input logic [3:0] tb_only_tb_read_addr_gen_1_strides_1, + input logic [3:0] tb_only_tb_read_addr_gen_1_strides_2, + input logic [3:0] tb_only_tb_read_addr_gen_1_strides_3, + input logic [3:0] tb_only_tb_read_addr_gen_1_strides_4, + input logic [3:0] tb_only_tb_read_addr_gen_1_strides_5, + input logic tb_only_tb_read_sched_gen_0_enable, + input logic [9:0] tb_only_tb_read_sched_gen_0_sched_addr_gen_delay, + input logic [15:0] tb_only_tb_read_sched_gen_0_sched_addr_gen_starting_addr, + input logic [15:0] tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_0, + input logic [15:0] tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_1, + input logic [15:0] tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_2, + input logic [15:0] tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_3, + input logic [15:0] tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_4, + input logic [15:0] tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_5, + input logic tb_only_tb_read_sched_gen_1_enable, + input logic [9:0] tb_only_tb_read_sched_gen_1_sched_addr_gen_delay, + input logic [15:0] tb_only_tb_read_sched_gen_1_sched_addr_gen_starting_addr, + input logic [15:0] tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_0, + input logic [15:0] tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_1, + input logic [15:0] tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_2, + input logic [15:0] tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_3, + input logic [15:0] tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_4, + input logic [15:0] tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_5, + input logic [3:0] tb_only_tb_write_addr_gen_0_starting_addr, + input logic [3:0] tb_only_tb_write_addr_gen_0_strides_0, + input logic [3:0] tb_only_tb_write_addr_gen_0_strides_1, + input logic [3:0] tb_only_tb_write_addr_gen_0_strides_2, + input logic [3:0] tb_only_tb_write_addr_gen_0_strides_3, + input logic [3:0] tb_only_tb_write_addr_gen_0_strides_4, + input logic [3:0] tb_only_tb_write_addr_gen_0_strides_5, + input logic [3:0] tb_only_tb_write_addr_gen_1_starting_addr, + input logic [3:0] tb_only_tb_write_addr_gen_1_strides_0, + input logic [3:0] tb_only_tb_write_addr_gen_1_strides_1, + input logic [3:0] tb_only_tb_write_addr_gen_1_strides_2, + input logic [3:0] tb_only_tb_write_addr_gen_1_strides_3, + input logic [3:0] tb_only_tb_write_addr_gen_1_strides_4, + input logic [3:0] tb_only_tb_write_addr_gen_1_strides_5, + output logic [1:0] accessor_output, + output logic [8:0] addr_out, + output logic [1:0] [16:0] data_out, + output logic [3:0] [15:0] data_to_strg, + output logic ren_to_strg, + output logic wen_to_strg +); + +logic [1:0] accessor_output_int; +logic [1:0][3:0][15:0] agg_only_agg_data_out; +logic [1:0] agg_only_agg_read; +logic [1:0][1:0] agg_only_agg_write_addr_l2b_out; +logic [1:0][2:0] agg_only_agg_write_mux_sel_out; +logic [1:0] agg_only_agg_write_out; +logic [1:0] agg_only_agg_write_restart_out; +logic [1:0][8:0] agg_only_sram_read_addr_in; +logic [1:0][2:0] agg_only_tb_read_addr_d_in; +logic [1:0] agg_only_tb_read_d_in; +logic [1:0][1:0] agg_only_update_mode_in; +logic [1:0] agg_sram_shared_agg_read_out; +logic [1:0][8:0] agg_sram_shared_agg_sram_shared_addr_out; +logic [1:0][8:0] agg_sram_shared_sram_read_addr_in; +logic [1:0] agg_sram_shared_sram_read_d_in; +logic [1:0] agg_sram_shared_sram_read_in; +logic [1:0][15:0] chain_data_in_thin; +logic [15:0] cycle_count; +logic [1:0][15:0] data_in_thin; +logic [1:0][15:0] data_out_int; +logic [1:0][15:0] data_out_int_thin; +logic [1:0][2:0] sram_only_loops_sram2tb_mux_sel; +logic [1:0] sram_only_loops_sram2tb_restart; +logic [1:0] sram_only_t_read; +logic [1:0][2:0] sram_tb_shared_loops_sram2tb_mux_sel; +logic [1:0] sram_tb_shared_loops_sram2tb_restart; +logic [1:0] sram_tb_shared_t_read_out; +assign data_in_thin[0] = data_in[0][15:0]; +assign data_in_thin[1] = data_in[1][15:0]; +assign data_out[0][15:0] = data_out_int_thin[0]; +assign data_out[0][16] = 1'h0; +assign data_out[1][15:0] = data_out_int_thin[1]; +assign data_out[1][16] = 1'h0; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + cycle_count <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + cycle_count <= 16'h0; + end + else if (1'h1) begin + cycle_count <= cycle_count + 16'h1; + end + end +end +assign agg_only_sram_read_addr_in = agg_sram_shared_agg_sram_shared_addr_out; +assign agg_sram_shared_sram_read_in = sram_tb_shared_t_read_out; +assign agg_only_agg_read = agg_sram_shared_agg_read_out; +assign sram_only_loops_sram2tb_mux_sel = sram_tb_shared_loops_sram2tb_mux_sel; +assign sram_only_loops_sram2tb_restart = sram_tb_shared_loops_sram2tb_restart; +assign sram_only_t_read = sram_tb_shared_t_read_out; +assign ren_to_strg = |sram_tb_shared_t_read_out; +assign chain_data_in_thin[0] = chain_data_in[0][15:0]; +assign chain_data_in_thin[1] = chain_data_in[1][15:0]; +assign accessor_output = accessor_output_int; +strg_ub_agg_only agg_only ( + .agg_read(agg_only_agg_read), + .agg_write_addr_gen_0_starting_addr(agg_only_agg_write_addr_gen_0_starting_addr), + .agg_write_addr_gen_0_strides_0(agg_only_agg_write_addr_gen_0_strides_0), + .agg_write_addr_gen_0_strides_1(agg_only_agg_write_addr_gen_0_strides_1), + .agg_write_addr_gen_0_strides_2(agg_only_agg_write_addr_gen_0_strides_2), + .agg_write_addr_gen_1_starting_addr(agg_only_agg_write_addr_gen_1_starting_addr), + .agg_write_addr_gen_1_strides_0(agg_only_agg_write_addr_gen_1_strides_0), + .agg_write_addr_gen_1_strides_1(agg_only_agg_write_addr_gen_1_strides_1), + .agg_write_addr_gen_1_strides_2(agg_only_agg_write_addr_gen_1_strides_2), + .agg_write_sched_gen_0_enable(agg_only_agg_write_sched_gen_0_enable), + .agg_write_sched_gen_0_sched_addr_gen_starting_addr(agg_only_agg_write_sched_gen_0_sched_addr_gen_starting_addr), + .agg_write_sched_gen_0_sched_addr_gen_strides_0(agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_0), + .agg_write_sched_gen_0_sched_addr_gen_strides_1(agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_1), + .agg_write_sched_gen_0_sched_addr_gen_strides_2(agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_2), + .agg_write_sched_gen_1_enable(agg_only_agg_write_sched_gen_1_enable), + .agg_write_sched_gen_1_sched_addr_gen_starting_addr(agg_only_agg_write_sched_gen_1_sched_addr_gen_starting_addr), + .agg_write_sched_gen_1_sched_addr_gen_strides_0(agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_0), + .agg_write_sched_gen_1_sched_addr_gen_strides_1(agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_1), + .agg_write_sched_gen_1_sched_addr_gen_strides_2(agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_2), + .clk(clk), + .clk_en(clk_en), + .cycle_count(cycle_count), + .data_in(data_in_thin), + .flush(flush), + .loops_in2buf_0_dimensionality(agg_only_loops_in2buf_0_dimensionality), + .loops_in2buf_0_ranges_0(agg_only_loops_in2buf_0_ranges_0), + .loops_in2buf_0_ranges_1(agg_only_loops_in2buf_0_ranges_1), + .loops_in2buf_0_ranges_2(agg_only_loops_in2buf_0_ranges_2), + .loops_in2buf_1_dimensionality(agg_only_loops_in2buf_1_dimensionality), + .loops_in2buf_1_ranges_0(agg_only_loops_in2buf_1_ranges_0), + .loops_in2buf_1_ranges_1(agg_only_loops_in2buf_1_ranges_1), + .loops_in2buf_1_ranges_2(agg_only_loops_in2buf_1_ranges_2), + .rst_n(rst_n), + .sram_read_addr_in(agg_only_sram_read_addr_in), + .tb_read_addr_d_in(agg_only_tb_read_addr_d_in), + .tb_read_d_in(agg_only_tb_read_d_in), + .update_mode_in(agg_only_update_mode_in), + .agg_data_out(agg_only_agg_data_out), + .agg_write_addr_l2b_out(agg_only_agg_write_addr_l2b_out), + .agg_write_mux_sel_out(agg_only_agg_write_mux_sel_out), + .agg_write_out(agg_only_agg_write_out), + .agg_write_restart_out(agg_only_agg_write_restart_out) +); + +strg_ub_agg_sram_shared agg_sram_shared ( + .agg_read_sched_gen_0_agg_read_padding(agg_sram_shared_agg_read_sched_gen_0_agg_read_padding), + .agg_read_sched_gen_1_agg_read_padding(agg_sram_shared_agg_read_sched_gen_1_agg_read_padding), + .agg_sram_shared_addr_gen_0_starting_addr(agg_sram_shared_agg_sram_shared_addr_gen_0_starting_addr), + .agg_sram_shared_addr_gen_1_starting_addr(agg_sram_shared_agg_sram_shared_addr_gen_1_starting_addr), + .agg_write_addr_l2b_in(agg_only_agg_write_addr_l2b_out), + .agg_write_in(agg_only_agg_write_out), + .agg_write_mux_sel_in(agg_only_agg_write_mux_sel_out), + .agg_write_restart_in(agg_only_agg_write_restart_out), + .clk(clk), + .clk_en(clk_en), + .flush(flush), + .mode_0(agg_sram_shared_mode_0), + .mode_1(agg_sram_shared_mode_1), + .rst_n(rst_n), + .sram_read_addr_in(agg_sram_shared_sram_read_addr_in), + .sram_read_d_in(agg_sram_shared_sram_read_d_in), + .sram_read_in(agg_sram_shared_sram_read_in), + .agg_read_out(agg_sram_shared_agg_read_out), + .agg_sram_shared_addr_out(agg_sram_shared_agg_sram_shared_addr_out), + .update_mode_out(agg_only_update_mode_in) +); + +strg_ub_sram_only sram_only ( + .agg_data_out(agg_only_agg_data_out), + .agg_read(agg_sram_shared_agg_read_out), + .clk(clk), + .clk_en(clk_en), + .cycle_count(cycle_count), + .flush(flush), + .loops_sram2tb_mux_sel(sram_only_loops_sram2tb_mux_sel), + .loops_sram2tb_restart(sram_only_loops_sram2tb_restart), + .output_addr_gen_0_starting_addr(sram_only_output_addr_gen_0_starting_addr), + .output_addr_gen_0_strides_0(sram_only_output_addr_gen_0_strides_0), + .output_addr_gen_0_strides_1(sram_only_output_addr_gen_0_strides_1), + .output_addr_gen_0_strides_2(sram_only_output_addr_gen_0_strides_2), + .output_addr_gen_0_strides_3(sram_only_output_addr_gen_0_strides_3), + .output_addr_gen_0_strides_4(sram_only_output_addr_gen_0_strides_4), + .output_addr_gen_0_strides_5(sram_only_output_addr_gen_0_strides_5), + .output_addr_gen_1_starting_addr(sram_only_output_addr_gen_1_starting_addr), + .output_addr_gen_1_strides_0(sram_only_output_addr_gen_1_strides_0), + .output_addr_gen_1_strides_1(sram_only_output_addr_gen_1_strides_1), + .output_addr_gen_1_strides_2(sram_only_output_addr_gen_1_strides_2), + .output_addr_gen_1_strides_3(sram_only_output_addr_gen_1_strides_3), + .output_addr_gen_1_strides_4(sram_only_output_addr_gen_1_strides_4), + .output_addr_gen_1_strides_5(sram_only_output_addr_gen_1_strides_5), + .rst_n(rst_n), + .sram_read_addr_in(agg_sram_shared_agg_sram_shared_addr_out), + .t_read(sram_only_t_read), + .addr_to_sram(addr_out), + .data_to_sram(data_to_strg), + .sram_read_addr_out(agg_sram_shared_sram_read_addr_in), + .wen_to_sram(wen_to_strg) +); + +strg_ub_sram_tb_shared sram_tb_shared ( + .clk(clk), + .clk_en(clk_en), + .cycle_count(cycle_count), + .flush(flush), + .loops_buf2out_autovec_read_0_dimensionality(sram_tb_shared_loops_buf2out_autovec_read_0_dimensionality), + .loops_buf2out_autovec_read_0_ranges_0(sram_tb_shared_loops_buf2out_autovec_read_0_ranges_0), + .loops_buf2out_autovec_read_0_ranges_1(sram_tb_shared_loops_buf2out_autovec_read_0_ranges_1), + .loops_buf2out_autovec_read_0_ranges_2(sram_tb_shared_loops_buf2out_autovec_read_0_ranges_2), + .loops_buf2out_autovec_read_0_ranges_3(sram_tb_shared_loops_buf2out_autovec_read_0_ranges_3), + .loops_buf2out_autovec_read_0_ranges_4(sram_tb_shared_loops_buf2out_autovec_read_0_ranges_4), + .loops_buf2out_autovec_read_0_ranges_5(sram_tb_shared_loops_buf2out_autovec_read_0_ranges_5), + .loops_buf2out_autovec_read_1_dimensionality(sram_tb_shared_loops_buf2out_autovec_read_1_dimensionality), + .loops_buf2out_autovec_read_1_ranges_0(sram_tb_shared_loops_buf2out_autovec_read_1_ranges_0), + .loops_buf2out_autovec_read_1_ranges_1(sram_tb_shared_loops_buf2out_autovec_read_1_ranges_1), + .loops_buf2out_autovec_read_1_ranges_2(sram_tb_shared_loops_buf2out_autovec_read_1_ranges_2), + .loops_buf2out_autovec_read_1_ranges_3(sram_tb_shared_loops_buf2out_autovec_read_1_ranges_3), + .loops_buf2out_autovec_read_1_ranges_4(sram_tb_shared_loops_buf2out_autovec_read_1_ranges_4), + .loops_buf2out_autovec_read_1_ranges_5(sram_tb_shared_loops_buf2out_autovec_read_1_ranges_5), + .output_sched_gen_0_enable(sram_tb_shared_output_sched_gen_0_enable), + .output_sched_gen_0_sched_addr_gen_delay(sram_tb_shared_output_sched_gen_0_sched_addr_gen_delay), + .output_sched_gen_0_sched_addr_gen_starting_addr(sram_tb_shared_output_sched_gen_0_sched_addr_gen_starting_addr), + .output_sched_gen_0_sched_addr_gen_strides_0(sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_0), + .output_sched_gen_0_sched_addr_gen_strides_1(sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_1), + .output_sched_gen_0_sched_addr_gen_strides_2(sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_2), + .output_sched_gen_0_sched_addr_gen_strides_3(sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_3), + .output_sched_gen_0_sched_addr_gen_strides_4(sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_4), + .output_sched_gen_0_sched_addr_gen_strides_5(sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_5), + .output_sched_gen_1_enable(sram_tb_shared_output_sched_gen_1_enable), + .output_sched_gen_1_sched_addr_gen_delay(sram_tb_shared_output_sched_gen_1_sched_addr_gen_delay), + .output_sched_gen_1_sched_addr_gen_starting_addr(sram_tb_shared_output_sched_gen_1_sched_addr_gen_starting_addr), + .output_sched_gen_1_sched_addr_gen_strides_0(sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_0), + .output_sched_gen_1_sched_addr_gen_strides_1(sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_1), + .output_sched_gen_1_sched_addr_gen_strides_2(sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_2), + .output_sched_gen_1_sched_addr_gen_strides_3(sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_3), + .output_sched_gen_1_sched_addr_gen_strides_4(sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_4), + .output_sched_gen_1_sched_addr_gen_strides_5(sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_5), + .rst_n(rst_n), + .loops_sram2tb_mux_sel(sram_tb_shared_loops_sram2tb_mux_sel), + .loops_sram2tb_restart(sram_tb_shared_loops_sram2tb_restart), + .sram_read_d(agg_sram_shared_sram_read_d_in), + .t_read_out(sram_tb_shared_t_read_out) +); + +strg_ub_tb_only tb_only ( + .clk(clk), + .clk_en(clk_en), + .cycle_count(cycle_count), + .flush(flush), + .loops_buf2out_read_0_dimensionality(tb_only_loops_buf2out_read_0_dimensionality), + .loops_buf2out_read_0_ranges_0(tb_only_loops_buf2out_read_0_ranges_0), + .loops_buf2out_read_0_ranges_1(tb_only_loops_buf2out_read_0_ranges_1), + .loops_buf2out_read_0_ranges_2(tb_only_loops_buf2out_read_0_ranges_2), + .loops_buf2out_read_0_ranges_3(tb_only_loops_buf2out_read_0_ranges_3), + .loops_buf2out_read_0_ranges_4(tb_only_loops_buf2out_read_0_ranges_4), + .loops_buf2out_read_0_ranges_5(tb_only_loops_buf2out_read_0_ranges_5), + .loops_buf2out_read_1_dimensionality(tb_only_loops_buf2out_read_1_dimensionality), + .loops_buf2out_read_1_ranges_0(tb_only_loops_buf2out_read_1_ranges_0), + .loops_buf2out_read_1_ranges_1(tb_only_loops_buf2out_read_1_ranges_1), + .loops_buf2out_read_1_ranges_2(tb_only_loops_buf2out_read_1_ranges_2), + .loops_buf2out_read_1_ranges_3(tb_only_loops_buf2out_read_1_ranges_3), + .loops_buf2out_read_1_ranges_4(tb_only_loops_buf2out_read_1_ranges_4), + .loops_buf2out_read_1_ranges_5(tb_only_loops_buf2out_read_1_ranges_5), + .loops_sram2tb_mux_sel(sram_tb_shared_loops_sram2tb_mux_sel), + .loops_sram2tb_restart(sram_tb_shared_loops_sram2tb_restart), + .rst_n(rst_n), + .shared_tb_0(tb_only_shared_tb_0), + .sram_read_data(data_from_strg), + .t_read(sram_tb_shared_t_read_out), + .tb_read_addr_gen_0_starting_addr(tb_only_tb_read_addr_gen_0_starting_addr), + .tb_read_addr_gen_0_strides_0(tb_only_tb_read_addr_gen_0_strides_0), + .tb_read_addr_gen_0_strides_1(tb_only_tb_read_addr_gen_0_strides_1), + .tb_read_addr_gen_0_strides_2(tb_only_tb_read_addr_gen_0_strides_2), + .tb_read_addr_gen_0_strides_3(tb_only_tb_read_addr_gen_0_strides_3), + .tb_read_addr_gen_0_strides_4(tb_only_tb_read_addr_gen_0_strides_4), + .tb_read_addr_gen_0_strides_5(tb_only_tb_read_addr_gen_0_strides_5), + .tb_read_addr_gen_1_starting_addr(tb_only_tb_read_addr_gen_1_starting_addr), + .tb_read_addr_gen_1_strides_0(tb_only_tb_read_addr_gen_1_strides_0), + .tb_read_addr_gen_1_strides_1(tb_only_tb_read_addr_gen_1_strides_1), + .tb_read_addr_gen_1_strides_2(tb_only_tb_read_addr_gen_1_strides_2), + .tb_read_addr_gen_1_strides_3(tb_only_tb_read_addr_gen_1_strides_3), + .tb_read_addr_gen_1_strides_4(tb_only_tb_read_addr_gen_1_strides_4), + .tb_read_addr_gen_1_strides_5(tb_only_tb_read_addr_gen_1_strides_5), + .tb_read_sched_gen_0_enable(tb_only_tb_read_sched_gen_0_enable), + .tb_read_sched_gen_0_sched_addr_gen_delay(tb_only_tb_read_sched_gen_0_sched_addr_gen_delay), + .tb_read_sched_gen_0_sched_addr_gen_starting_addr(tb_only_tb_read_sched_gen_0_sched_addr_gen_starting_addr), + .tb_read_sched_gen_0_sched_addr_gen_strides_0(tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_0), + .tb_read_sched_gen_0_sched_addr_gen_strides_1(tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_1), + .tb_read_sched_gen_0_sched_addr_gen_strides_2(tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_2), + .tb_read_sched_gen_0_sched_addr_gen_strides_3(tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_3), + .tb_read_sched_gen_0_sched_addr_gen_strides_4(tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_4), + .tb_read_sched_gen_0_sched_addr_gen_strides_5(tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_5), + .tb_read_sched_gen_1_enable(tb_only_tb_read_sched_gen_1_enable), + .tb_read_sched_gen_1_sched_addr_gen_delay(tb_only_tb_read_sched_gen_1_sched_addr_gen_delay), + .tb_read_sched_gen_1_sched_addr_gen_starting_addr(tb_only_tb_read_sched_gen_1_sched_addr_gen_starting_addr), + .tb_read_sched_gen_1_sched_addr_gen_strides_0(tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_0), + .tb_read_sched_gen_1_sched_addr_gen_strides_1(tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_1), + .tb_read_sched_gen_1_sched_addr_gen_strides_2(tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_2), + .tb_read_sched_gen_1_sched_addr_gen_strides_3(tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_3), + .tb_read_sched_gen_1_sched_addr_gen_strides_4(tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_4), + .tb_read_sched_gen_1_sched_addr_gen_strides_5(tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_5), + .tb_write_addr_gen_0_starting_addr(tb_only_tb_write_addr_gen_0_starting_addr), + .tb_write_addr_gen_0_strides_0(tb_only_tb_write_addr_gen_0_strides_0), + .tb_write_addr_gen_0_strides_1(tb_only_tb_write_addr_gen_0_strides_1), + .tb_write_addr_gen_0_strides_2(tb_only_tb_write_addr_gen_0_strides_2), + .tb_write_addr_gen_0_strides_3(tb_only_tb_write_addr_gen_0_strides_3), + .tb_write_addr_gen_0_strides_4(tb_only_tb_write_addr_gen_0_strides_4), + .tb_write_addr_gen_0_strides_5(tb_only_tb_write_addr_gen_0_strides_5), + .tb_write_addr_gen_1_starting_addr(tb_only_tb_write_addr_gen_1_starting_addr), + .tb_write_addr_gen_1_strides_0(tb_only_tb_write_addr_gen_1_strides_0), + .tb_write_addr_gen_1_strides_1(tb_only_tb_write_addr_gen_1_strides_1), + .tb_write_addr_gen_1_strides_2(tb_only_tb_write_addr_gen_1_strides_2), + .tb_write_addr_gen_1_strides_3(tb_only_tb_write_addr_gen_1_strides_3), + .tb_write_addr_gen_1_strides_4(tb_only_tb_write_addr_gen_1_strides_4), + .tb_write_addr_gen_1_strides_5(tb_only_tb_write_addr_gen_1_strides_5), + .accessor_output(accessor_output_int), + .data_out(data_out_int), + .tb_read_addr_d_out(agg_only_tb_read_addr_d_in), + .tb_read_d_out(agg_only_tb_read_d_in) +); + +Chain_2_16 chain ( + .accessor_output(accessor_output_int), + .chain_data_in(chain_data_in_thin), + .chain_en(chain_chain_en), + .clk_en(clk_en), + .curr_tile_data_out(data_out_int), + .flush(flush), + .data_out_tile(data_out_int_thin) +); + +endmodule // strg_ub_vec + +module strg_ub_vec_flat ( + input logic [0:0] [16:0] chain_data_in_f_0, + input logic [0:0] [16:0] chain_data_in_f_1, + input logic clk, + input logic clk_en, + input logic [0:0] [16:0] data_in_f_0, + input logic [0:0] [16:0] data_in_f_1, + input logic flush, + input logic rst_n, + input logic [2:0] strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_starting_addr, + input logic [2:0] strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_strides_0, + input logic [2:0] strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_strides_1, + input logic [2:0] strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_strides_2, + input logic [2:0] strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_starting_addr, + input logic [2:0] strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_strides_0, + input logic [2:0] strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_strides_1, + input logic [2:0] strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_strides_2, + input logic strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_enable, + input logic [15:0] strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_starting_addr, + input logic [15:0] strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_0, + input logic [15:0] strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_1, + input logic [15:0] strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_2, + input logic strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_enable, + input logic [15:0] strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_starting_addr, + input logic [15:0] strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_0, + input logic [15:0] strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_1, + input logic [15:0] strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_2, + input logic [2:0] strg_ub_vec_inst_agg_only_loops_in2buf_0_dimensionality, + input logic [10:0] strg_ub_vec_inst_agg_only_loops_in2buf_0_ranges_0, + input logic [10:0] strg_ub_vec_inst_agg_only_loops_in2buf_0_ranges_1, + input logic [10:0] strg_ub_vec_inst_agg_only_loops_in2buf_0_ranges_2, + input logic [2:0] strg_ub_vec_inst_agg_only_loops_in2buf_1_dimensionality, + input logic [10:0] strg_ub_vec_inst_agg_only_loops_in2buf_1_ranges_0, + input logic [10:0] strg_ub_vec_inst_agg_only_loops_in2buf_1_ranges_1, + input logic [10:0] strg_ub_vec_inst_agg_only_loops_in2buf_1_ranges_2, + input logic [7:0] strg_ub_vec_inst_agg_sram_shared_agg_read_sched_gen_0_agg_read_padding, + input logic [7:0] strg_ub_vec_inst_agg_sram_shared_agg_read_sched_gen_1_agg_read_padding, + input logic [8:0] strg_ub_vec_inst_agg_sram_shared_agg_sram_shared_addr_gen_0_starting_addr, + input logic [8:0] strg_ub_vec_inst_agg_sram_shared_agg_sram_shared_addr_gen_1_starting_addr, + input logic [1:0] strg_ub_vec_inst_agg_sram_shared_mode_0, + input logic [1:0] strg_ub_vec_inst_agg_sram_shared_mode_1, + input logic strg_ub_vec_inst_chain_chain_en, + input logic [3:0] [15:0] strg_ub_vec_inst_data_from_strg_lifted, + input logic [8:0] strg_ub_vec_inst_sram_only_output_addr_gen_0_starting_addr, + input logic [8:0] strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_0, + input logic [8:0] strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_1, + input logic [8:0] strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_2, + input logic [8:0] strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_3, + input logic [8:0] strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_4, + input logic [8:0] strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_5, + input logic [8:0] strg_ub_vec_inst_sram_only_output_addr_gen_1_starting_addr, + input logic [8:0] strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_0, + input logic [8:0] strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_1, + input logic [8:0] strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_2, + input logic [8:0] strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_3, + input logic [8:0] strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_4, + input logic [8:0] strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_5, + input logic [3:0] strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_dimensionality, + input logic [10:0] strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_0, + input logic [10:0] strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_1, + input logic [10:0] strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_2, + input logic [10:0] strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_3, + input logic [10:0] strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_4, + input logic [10:0] strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_5, + input logic [3:0] strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_dimensionality, + input logic [10:0] strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_0, + input logic [10:0] strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_1, + input logic [10:0] strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_2, + input logic [10:0] strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_3, + input logic [10:0] strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_4, + input logic [10:0] strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_5, + input logic strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_enable, + input logic [9:0] strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_delay, + input logic [15:0] strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_starting_addr, + input logic [15:0] strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_0, + input logic [15:0] strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_1, + input logic [15:0] strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_2, + input logic [15:0] strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_3, + input logic [15:0] strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_4, + input logic [15:0] strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_5, + input logic strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_enable, + input logic [9:0] strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_delay, + input logic [15:0] strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_starting_addr, + input logic [15:0] strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_0, + input logic [15:0] strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_1, + input logic [15:0] strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_2, + input logic [15:0] strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_3, + input logic [15:0] strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_4, + input logic [15:0] strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_5, + input logic [3:0] strg_ub_vec_inst_tb_only_loops_buf2out_read_0_dimensionality, + input logic [10:0] strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_0, + input logic [10:0] strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_1, + input logic [10:0] strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_2, + input logic [10:0] strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_3, + input logic [10:0] strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_4, + input logic [10:0] strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_5, + input logic [3:0] strg_ub_vec_inst_tb_only_loops_buf2out_read_1_dimensionality, + input logic [10:0] strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_0, + input logic [10:0] strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_1, + input logic [10:0] strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_2, + input logic [10:0] strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_3, + input logic [10:0] strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_4, + input logic [10:0] strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_5, + input logic strg_ub_vec_inst_tb_only_shared_tb_0, + input logic [3:0] strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_starting_addr, + input logic [3:0] strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_0, + input logic [3:0] strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_1, + input logic [3:0] strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_2, + input logic [3:0] strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_3, + input logic [3:0] strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_4, + input logic [3:0] strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_5, + input logic [3:0] strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_starting_addr, + input logic [3:0] strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_0, + input logic [3:0] strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_1, + input logic [3:0] strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_2, + input logic [3:0] strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_3, + input logic [3:0] strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_4, + input logic [3:0] strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_5, + input logic strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_enable, + input logic [9:0] strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_delay, + input logic [15:0] strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_starting_addr, + input logic [15:0] strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_0, + input logic [15:0] strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_1, + input logic [15:0] strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_2, + input logic [15:0] strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_3, + input logic [15:0] strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_4, + input logic [15:0] strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_5, + input logic strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_enable, + input logic [9:0] strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_delay, + input logic [15:0] strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_starting_addr, + input logic [15:0] strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_0, + input logic [15:0] strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_1, + input logic [15:0] strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_2, + input logic [15:0] strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_3, + input logic [15:0] strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_4, + input logic [15:0] strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_5, + input logic [3:0] strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_starting_addr, + input logic [3:0] strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_0, + input logic [3:0] strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_1, + input logic [3:0] strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_2, + input logic [3:0] strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_3, + input logic [3:0] strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_4, + input logic [3:0] strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_5, + input logic [3:0] strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_starting_addr, + input logic [3:0] strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_0, + input logic [3:0] strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_1, + input logic [3:0] strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_2, + input logic [3:0] strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_3, + input logic [3:0] strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_4, + input logic [3:0] strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_5, + output logic accessor_output_f_b_0, + output logic accessor_output_f_b_1, + output logic [0:0] [16:0] data_out_f_0, + output logic [0:0] [16:0] data_out_f_1, + output logic [8:0] strg_ub_vec_inst_addr_out_lifted, + output logic [3:0] [15:0] strg_ub_vec_inst_data_to_strg_lifted, + output logic strg_ub_vec_inst_ren_to_strg_lifted, + output logic strg_ub_vec_inst_wen_to_strg_lifted +); + +logic [1:0] strg_ub_vec_inst_accessor_output; +logic [1:0][16:0] strg_ub_vec_inst_chain_data_in; +logic [1:0][16:0] strg_ub_vec_inst_data_in; +logic [1:0][16:0] strg_ub_vec_inst_data_out; +assign strg_ub_vec_inst_data_in[0] = data_in_f_0; +assign strg_ub_vec_inst_data_in[1] = data_in_f_1; +assign strg_ub_vec_inst_chain_data_in[0] = chain_data_in_f_0; +assign strg_ub_vec_inst_chain_data_in[1] = chain_data_in_f_1; +assign data_out_f_0 = strg_ub_vec_inst_data_out[0]; +assign data_out_f_1 = strg_ub_vec_inst_data_out[1]; +assign accessor_output_f_b_0 = strg_ub_vec_inst_accessor_output[0]; +assign accessor_output_f_b_1 = strg_ub_vec_inst_accessor_output[1]; +strg_ub_vec strg_ub_vec_inst ( + .agg_only_agg_write_addr_gen_0_starting_addr(strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_starting_addr), + .agg_only_agg_write_addr_gen_0_strides_0(strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_strides_0), + .agg_only_agg_write_addr_gen_0_strides_1(strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_strides_1), + .agg_only_agg_write_addr_gen_0_strides_2(strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_strides_2), + .agg_only_agg_write_addr_gen_1_starting_addr(strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_starting_addr), + .agg_only_agg_write_addr_gen_1_strides_0(strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_strides_0), + .agg_only_agg_write_addr_gen_1_strides_1(strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_strides_1), + .agg_only_agg_write_addr_gen_1_strides_2(strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_strides_2), + .agg_only_agg_write_sched_gen_0_enable(strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_enable), + .agg_only_agg_write_sched_gen_0_sched_addr_gen_starting_addr(strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_starting_addr), + .agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_0(strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_0), + .agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_1(strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_1), + .agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_2(strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_2), + .agg_only_agg_write_sched_gen_1_enable(strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_enable), + .agg_only_agg_write_sched_gen_1_sched_addr_gen_starting_addr(strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_starting_addr), + .agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_0(strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_0), + .agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_1(strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_1), + .agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_2(strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_2), + .agg_only_loops_in2buf_0_dimensionality(strg_ub_vec_inst_agg_only_loops_in2buf_0_dimensionality), + .agg_only_loops_in2buf_0_ranges_0(strg_ub_vec_inst_agg_only_loops_in2buf_0_ranges_0), + .agg_only_loops_in2buf_0_ranges_1(strg_ub_vec_inst_agg_only_loops_in2buf_0_ranges_1), + .agg_only_loops_in2buf_0_ranges_2(strg_ub_vec_inst_agg_only_loops_in2buf_0_ranges_2), + .agg_only_loops_in2buf_1_dimensionality(strg_ub_vec_inst_agg_only_loops_in2buf_1_dimensionality), + .agg_only_loops_in2buf_1_ranges_0(strg_ub_vec_inst_agg_only_loops_in2buf_1_ranges_0), + .agg_only_loops_in2buf_1_ranges_1(strg_ub_vec_inst_agg_only_loops_in2buf_1_ranges_1), + .agg_only_loops_in2buf_1_ranges_2(strg_ub_vec_inst_agg_only_loops_in2buf_1_ranges_2), + .agg_sram_shared_agg_read_sched_gen_0_agg_read_padding(strg_ub_vec_inst_agg_sram_shared_agg_read_sched_gen_0_agg_read_padding), + .agg_sram_shared_agg_read_sched_gen_1_agg_read_padding(strg_ub_vec_inst_agg_sram_shared_agg_read_sched_gen_1_agg_read_padding), + .agg_sram_shared_agg_sram_shared_addr_gen_0_starting_addr(strg_ub_vec_inst_agg_sram_shared_agg_sram_shared_addr_gen_0_starting_addr), + .agg_sram_shared_agg_sram_shared_addr_gen_1_starting_addr(strg_ub_vec_inst_agg_sram_shared_agg_sram_shared_addr_gen_1_starting_addr), + .agg_sram_shared_mode_0(strg_ub_vec_inst_agg_sram_shared_mode_0), + .agg_sram_shared_mode_1(strg_ub_vec_inst_agg_sram_shared_mode_1), + .chain_chain_en(strg_ub_vec_inst_chain_chain_en), + .chain_data_in(strg_ub_vec_inst_chain_data_in), + .clk(clk), + .clk_en(clk_en), + .data_from_strg(strg_ub_vec_inst_data_from_strg_lifted), + .data_in(strg_ub_vec_inst_data_in), + .flush(flush), + .rst_n(rst_n), + .sram_only_output_addr_gen_0_starting_addr(strg_ub_vec_inst_sram_only_output_addr_gen_0_starting_addr), + .sram_only_output_addr_gen_0_strides_0(strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_0), + .sram_only_output_addr_gen_0_strides_1(strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_1), + .sram_only_output_addr_gen_0_strides_2(strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_2), + .sram_only_output_addr_gen_0_strides_3(strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_3), + .sram_only_output_addr_gen_0_strides_4(strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_4), + .sram_only_output_addr_gen_0_strides_5(strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_5), + .sram_only_output_addr_gen_1_starting_addr(strg_ub_vec_inst_sram_only_output_addr_gen_1_starting_addr), + .sram_only_output_addr_gen_1_strides_0(strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_0), + .sram_only_output_addr_gen_1_strides_1(strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_1), + .sram_only_output_addr_gen_1_strides_2(strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_2), + .sram_only_output_addr_gen_1_strides_3(strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_3), + .sram_only_output_addr_gen_1_strides_4(strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_4), + .sram_only_output_addr_gen_1_strides_5(strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_5), + .sram_tb_shared_loops_buf2out_autovec_read_0_dimensionality(strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_dimensionality), + .sram_tb_shared_loops_buf2out_autovec_read_0_ranges_0(strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_0), + .sram_tb_shared_loops_buf2out_autovec_read_0_ranges_1(strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_1), + .sram_tb_shared_loops_buf2out_autovec_read_0_ranges_2(strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_2), + .sram_tb_shared_loops_buf2out_autovec_read_0_ranges_3(strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_3), + .sram_tb_shared_loops_buf2out_autovec_read_0_ranges_4(strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_4), + .sram_tb_shared_loops_buf2out_autovec_read_0_ranges_5(strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_5), + .sram_tb_shared_loops_buf2out_autovec_read_1_dimensionality(strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_dimensionality), + .sram_tb_shared_loops_buf2out_autovec_read_1_ranges_0(strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_0), + .sram_tb_shared_loops_buf2out_autovec_read_1_ranges_1(strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_1), + .sram_tb_shared_loops_buf2out_autovec_read_1_ranges_2(strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_2), + .sram_tb_shared_loops_buf2out_autovec_read_1_ranges_3(strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_3), + .sram_tb_shared_loops_buf2out_autovec_read_1_ranges_4(strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_4), + .sram_tb_shared_loops_buf2out_autovec_read_1_ranges_5(strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_5), + .sram_tb_shared_output_sched_gen_0_enable(strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_enable), + .sram_tb_shared_output_sched_gen_0_sched_addr_gen_delay(strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_delay), + .sram_tb_shared_output_sched_gen_0_sched_addr_gen_starting_addr(strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_starting_addr), + .sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_0(strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_0), + .sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_1(strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_1), + .sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_2(strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_2), + .sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_3(strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_3), + .sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_4(strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_4), + .sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_5(strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_5), + .sram_tb_shared_output_sched_gen_1_enable(strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_enable), + .sram_tb_shared_output_sched_gen_1_sched_addr_gen_delay(strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_delay), + .sram_tb_shared_output_sched_gen_1_sched_addr_gen_starting_addr(strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_starting_addr), + .sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_0(strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_0), + .sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_1(strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_1), + .sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_2(strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_2), + .sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_3(strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_3), + .sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_4(strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_4), + .sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_5(strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_5), + .tb_only_loops_buf2out_read_0_dimensionality(strg_ub_vec_inst_tb_only_loops_buf2out_read_0_dimensionality), + .tb_only_loops_buf2out_read_0_ranges_0(strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_0), + .tb_only_loops_buf2out_read_0_ranges_1(strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_1), + .tb_only_loops_buf2out_read_0_ranges_2(strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_2), + .tb_only_loops_buf2out_read_0_ranges_3(strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_3), + .tb_only_loops_buf2out_read_0_ranges_4(strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_4), + .tb_only_loops_buf2out_read_0_ranges_5(strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_5), + .tb_only_loops_buf2out_read_1_dimensionality(strg_ub_vec_inst_tb_only_loops_buf2out_read_1_dimensionality), + .tb_only_loops_buf2out_read_1_ranges_0(strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_0), + .tb_only_loops_buf2out_read_1_ranges_1(strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_1), + .tb_only_loops_buf2out_read_1_ranges_2(strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_2), + .tb_only_loops_buf2out_read_1_ranges_3(strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_3), + .tb_only_loops_buf2out_read_1_ranges_4(strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_4), + .tb_only_loops_buf2out_read_1_ranges_5(strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_5), + .tb_only_shared_tb_0(strg_ub_vec_inst_tb_only_shared_tb_0), + .tb_only_tb_read_addr_gen_0_starting_addr(strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_starting_addr), + .tb_only_tb_read_addr_gen_0_strides_0(strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_0), + .tb_only_tb_read_addr_gen_0_strides_1(strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_1), + .tb_only_tb_read_addr_gen_0_strides_2(strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_2), + .tb_only_tb_read_addr_gen_0_strides_3(strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_3), + .tb_only_tb_read_addr_gen_0_strides_4(strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_4), + .tb_only_tb_read_addr_gen_0_strides_5(strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_5), + .tb_only_tb_read_addr_gen_1_starting_addr(strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_starting_addr), + .tb_only_tb_read_addr_gen_1_strides_0(strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_0), + .tb_only_tb_read_addr_gen_1_strides_1(strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_1), + .tb_only_tb_read_addr_gen_1_strides_2(strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_2), + .tb_only_tb_read_addr_gen_1_strides_3(strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_3), + .tb_only_tb_read_addr_gen_1_strides_4(strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_4), + .tb_only_tb_read_addr_gen_1_strides_5(strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_5), + .tb_only_tb_read_sched_gen_0_enable(strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_enable), + .tb_only_tb_read_sched_gen_0_sched_addr_gen_delay(strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_delay), + .tb_only_tb_read_sched_gen_0_sched_addr_gen_starting_addr(strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_starting_addr), + .tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_0(strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_0), + .tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_1(strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_1), + .tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_2(strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_2), + .tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_3(strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_3), + .tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_4(strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_4), + .tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_5(strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_5), + .tb_only_tb_read_sched_gen_1_enable(strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_enable), + .tb_only_tb_read_sched_gen_1_sched_addr_gen_delay(strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_delay), + .tb_only_tb_read_sched_gen_1_sched_addr_gen_starting_addr(strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_starting_addr), + .tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_0(strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_0), + .tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_1(strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_1), + .tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_2(strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_2), + .tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_3(strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_3), + .tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_4(strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_4), + .tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_5(strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_5), + .tb_only_tb_write_addr_gen_0_starting_addr(strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_starting_addr), + .tb_only_tb_write_addr_gen_0_strides_0(strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_0), + .tb_only_tb_write_addr_gen_0_strides_1(strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_1), + .tb_only_tb_write_addr_gen_0_strides_2(strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_2), + .tb_only_tb_write_addr_gen_0_strides_3(strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_3), + .tb_only_tb_write_addr_gen_0_strides_4(strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_4), + .tb_only_tb_write_addr_gen_0_strides_5(strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_5), + .tb_only_tb_write_addr_gen_1_starting_addr(strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_starting_addr), + .tb_only_tb_write_addr_gen_1_strides_0(strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_0), + .tb_only_tb_write_addr_gen_1_strides_1(strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_1), + .tb_only_tb_write_addr_gen_1_strides_2(strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_2), + .tb_only_tb_write_addr_gen_1_strides_3(strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_3), + .tb_only_tb_write_addr_gen_1_strides_4(strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_4), + .tb_only_tb_write_addr_gen_1_strides_5(strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_5), + .accessor_output(strg_ub_vec_inst_accessor_output), + .addr_out(strg_ub_vec_inst_addr_out_lifted), + .data_out(strg_ub_vec_inst_data_out), + .data_to_strg(strg_ub_vec_inst_data_to_strg_lifted), + .ren_to_strg(strg_ub_vec_inst_ren_to_strg_lifted), + .wen_to_strg(strg_ub_vec_inst_wen_to_strg_lifted) +); + +endmodule // strg_ub_vec_flat + +module write_scanner ( + input logic ID_out_ready, + input logic [16:0] addr_in, + input logic addr_in_valid, + input logic addr_out_ready, + input logic block_mode, + input logic [16:0] block_wr_in, + input logic block_wr_in_valid, + input logic clk, + input logic clk_en, + input logic compressed, + input logic [16:0] data_in, + input logic data_in_valid, + input logic data_out_ready, + input logic flush, + input logic init_blank, + input logic lowest_level, + input logic rst_n, + input logic [15:0] stop_lvl, + input logic tile_en, + input logic vector_reduce_mode, + output logic [16:0] ID_out, + output logic ID_out_valid, + output logic addr_in_ready, + output logic [16:0] addr_out, + output logic addr_out_valid, + output logic block_wr_in_ready, + output logic data_in_ready, + output logic [16:0] data_out, + output logic data_out_valid +); + +typedef enum logic[3:0] { + ALLOCATE1 = 4'h0, + ALLOCATE2 = 4'h1, + BLOCK_1_SZ = 4'h2, + BLOCK_1_WR = 4'h3, + BLOCK_2_SZ = 4'h4, + BLOCK_2_WR = 4'h5, + ComLL = 4'h6, + DONE = 4'h7, + FINALIZE1 = 4'h8, + FINALIZE2 = 4'h9, + LL = 4'hA, + START = 4'hB, + UL = 4'hC, + UL_EMIT = 4'hD, + UL_WZ = 4'hE, + UnLL = 4'hF +} scan_seq_state; +logic [0:0][16:0] ID_out_fifo_data_in; +logic ID_out_fifo_empty; +logic ID_out_fifo_full; +logic ID_out_fifo_push; +logic [15:0] ID_to_fifo; +logic IN_DONE; +logic addr_done_in; +logic [15:0] addr_infifo_data_in; +logic addr_infifo_eos_in; +logic [16:0] addr_infifo_in_packed; +logic [16:0] addr_infifo_out_packed; +logic addr_infifo_valid_in; +logic addr_input_fifo_empty; +logic addr_input_fifo_full; +logic [0:0][16:0] addr_out_fifo_data_in; +logic addr_out_fifo_empty; +logic addr_out_fifo_full; +logic addr_out_fifo_push; +logic [15:0] addr_to_fifo; +logic blank_done_stick_sticky; +logic blank_done_stick_was_high; +logic [15:0] block_size; +logic block_wr_fifo_valid; +logic [0:0][15:0] block_wr_input_fifo_data_out; +logic block_wr_input_fifo_empty; +logic block_wr_input_fifo_full; +logic [15:0] block_write_count; +logic clr_blank_done; +logic clr_block_write; +logic clr_coord_addr; +logic clr_curr_coord; +logic clr_seg_addr; +logic clr_seg_ctr; +logic clr_wen_made; +logic [15:0] coord_addr; +logic data_done_in; +logic [15:0] data_infifo_data_in; +logic [15:0] data_infifo_data_in_d1; +logic data_infifo_eos_in; +logic [16:0] data_infifo_in_packed; +logic [16:0] data_infifo_out_packed; +logic data_infifo_valid_in; +logic data_input_fifo_empty; +logic data_input_fifo_full; +logic [0:0][16:0] data_out_fifo_data_in; +logic data_out_fifo_empty; +logic data_out_fifo_full; +logic data_out_fifo_push; +logic [15:0] data_to_fifo; +logic [16:0] done_token; +logic gclk; +logic inc_block_write; +logic inc_coord_addr; +logic inc_seg_addr; +logic inc_seg_ctr; +logic [1:0] infifo_pop; +logic new_coord; +logic op_to_fifo; +logic pop_block_wr; +logic push_to_outs; +scan_seq_state scan_seq_current_state; +scan_seq_state scan_seq_next_state; +logic [15:0] segment_addr; +logic [15:0] segment_counter; +logic [16:0] semi_done_token; +logic set_blank_done; +logic set_block_size; +logic set_curr_coord; +logic stop_in; +logic valid_coord_sticky_sticky; +logic valid_coord_sticky_was_high; +logic [16:0] vr_fsm_wr_scan_data_in; +logic wen_made_sticky; +logic wen_made_was_high; +assign gclk = clk & tile_en; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + blank_done_stick_was_high <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + blank_done_stick_was_high <= 1'h0; + end + else if (clr_blank_done) begin + blank_done_stick_was_high <= 1'h0; + end + else if (set_blank_done) begin + blank_done_stick_was_high <= 1'h1; + end + end +end +assign blank_done_stick_sticky = blank_done_stick_was_high; +assign done_token = {1'h1, 7'h0, 1'h1, 8'h0}; +assign semi_done_token = {1'h1, 11'h0, 1'h1, 4'h0}; +assign vr_fsm_wr_scan_data_in = (data_in == semi_done_token) ? done_token: data_in; +assign data_infifo_in_packed = vector_reduce_mode ? vr_fsm_wr_scan_data_in: data_in; +assign data_infifo_eos_in = data_infifo_out_packed[16]; +assign data_infifo_data_in = data_infifo_out_packed[15:0]; +assign data_in_ready = ~data_input_fifo_full; +assign data_infifo_valid_in = ~data_input_fifo_empty; +assign addr_infifo_in_packed[16] = addr_in[16]; +assign addr_infifo_in_packed[15:0] = addr_in[15:0]; +assign addr_infifo_eos_in = addr_infifo_out_packed[16]; +assign addr_infifo_data_in = addr_infifo_out_packed[15:0]; +assign addr_in_ready = ~addr_input_fifo_full; +assign addr_infifo_valid_in = ~addr_input_fifo_empty; +assign block_wr_in_ready = ~block_wr_input_fifo_full; +assign block_wr_fifo_valid = ~block_wr_input_fifo_empty; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + block_size <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + block_size <= 16'h0; + end + else if (1'h0) begin + block_size <= 16'h0; + end + else if (set_block_size) begin + block_size <= block_wr_input_fifo_data_out; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + block_write_count <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + block_write_count <= 16'h0; + end + else if (clr_block_write) begin + block_write_count <= 16'h0; + end + else if (inc_block_write) begin + block_write_count <= block_write_count + 16'h1; + end + end +end +assign data_out_fifo_data_in = {op_to_fifo, data_to_fifo}; +assign data_out_valid = ~data_out_fifo_empty; +assign addr_out_fifo_data_in = {1'h0, addr_to_fifo}; +assign addr_out_valid = ~addr_out_fifo_empty; +assign ID_out_fifo_data_in = {1'h0, ID_to_fifo}; +assign ID_out_valid = ~ID_out_fifo_empty; +assign {data_out_fifo_push, addr_out_fifo_push, ID_out_fifo_push} = {push_to_outs, push_to_outs, push_to_outs}; +assign data_done_in = data_infifo_valid_in & data_infifo_eos_in & (data_infifo_data_in[9:8] == 2'h1); +assign addr_done_in = addr_infifo_valid_in & addr_infifo_eos_in & (addr_infifo_data_in[9:8] == 2'h1); + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + segment_addr <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + segment_addr <= 16'h0; + end + else if (clr_seg_addr) begin + segment_addr <= 16'h0; + end + else if (inc_seg_addr) begin + segment_addr <= segment_addr + 16'h1; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + coord_addr <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + coord_addr <= 16'h0; + end + else if (clr_coord_addr) begin + coord_addr <= 16'h0; + end + else if (inc_coord_addr) begin + coord_addr <= coord_addr + 16'h1; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + segment_counter <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + segment_counter <= 16'h0; + end + else if (clr_seg_ctr) begin + segment_counter <= 16'h0; + end + else if (inc_seg_ctr) begin + segment_counter <= segment_counter + 16'h1; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + data_infifo_data_in_d1 <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + data_infifo_data_in_d1 <= 16'h0; + end + else if (1'h0) begin + data_infifo_data_in_d1 <= 16'h0; + end + else if (set_curr_coord) begin + data_infifo_data_in_d1 <= data_infifo_data_in; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + valid_coord_sticky_was_high <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + valid_coord_sticky_was_high <= 1'h0; + end + else if (clr_curr_coord) begin + valid_coord_sticky_was_high <= 1'h0; + end + else if (set_curr_coord) begin + valid_coord_sticky_was_high <= 1'h1; + end + end +end +assign valid_coord_sticky_sticky = valid_coord_sticky_was_high; +assign new_coord = data_infifo_valid_in & (~data_infifo_eos_in) & ((~valid_coord_sticky_sticky) | + (data_infifo_data_in != data_infifo_data_in_d1)); +assign stop_in = data_infifo_valid_in & data_infifo_eos_in; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + wen_made_was_high <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + wen_made_was_high <= 1'h0; + end + else if (clr_wen_made) begin + wen_made_was_high <= 1'h0; + end + else if (push_to_outs) begin + wen_made_was_high <= 1'h1; + end + end +end +assign wen_made_sticky = wen_made_was_high; + +always_ff @(posedge clk, negedge rst_n) begin + if (!rst_n) begin + scan_seq_current_state <= START; + end + else if (clk_en) begin + if (flush) begin + scan_seq_current_state <= START; + end + else scan_seq_current_state <= scan_seq_next_state; + end +end +always_comb begin + scan_seq_next_state = scan_seq_current_state; + unique case (scan_seq_current_state) + ALLOCATE1: begin + if (~(&(~{data_out_fifo_full, addr_out_fifo_full, ID_out_fifo_full}))) begin + scan_seq_next_state = ALLOCATE1; + end + else if ((~lowest_level) & (&(~{data_out_fifo_full, addr_out_fifo_full, ID_out_fifo_full}))) begin + scan_seq_next_state = ALLOCATE2; + end + else if (lowest_level & block_mode & (&(~{data_out_fifo_full, addr_out_fifo_full, ID_out_fifo_full}))) begin + scan_seq_next_state = BLOCK_1_SZ; + end + else if (lowest_level & (~block_mode) & (&(~{data_out_fifo_full, addr_out_fifo_full, ID_out_fifo_full}))) begin + scan_seq_next_state = LL; + end + end + ALLOCATE2: begin + if (~(&(~{data_out_fifo_full, addr_out_fifo_full, ID_out_fifo_full}))) begin + scan_seq_next_state = ALLOCATE2; + end + else if (block_mode & (&(~{data_out_fifo_full, addr_out_fifo_full, ID_out_fifo_full}))) begin + scan_seq_next_state = BLOCK_1_SZ; + end + else if ((~block_mode) & (&(~{data_out_fifo_full, addr_out_fifo_full, ID_out_fifo_full}))) begin + scan_seq_next_state = UL_WZ; + end + end + BLOCK_1_SZ: begin + if (block_wr_fifo_valid) begin + scan_seq_next_state = BLOCK_1_WR; + end + else scan_seq_next_state = BLOCK_1_SZ; + end + BLOCK_1_WR: begin + if ((block_write_count == block_size) & (~lowest_level)) begin + scan_seq_next_state = BLOCK_2_SZ; + end + else if ((block_write_count == block_size) & lowest_level) begin + scan_seq_next_state = FINALIZE2; + end + else scan_seq_next_state = BLOCK_1_WR; + end + BLOCK_2_SZ: begin + if (block_wr_fifo_valid) begin + scan_seq_next_state = BLOCK_2_WR; + end + else scan_seq_next_state = BLOCK_2_SZ; + end + BLOCK_2_WR: begin + if (block_write_count == block_size) begin + scan_seq_next_state = FINALIZE1; + end + else scan_seq_next_state = BLOCK_2_WR; + end + ComLL: begin + if (data_done_in) begin + scan_seq_next_state = FINALIZE2; + end + else scan_seq_next_state = ComLL; + end + DONE: scan_seq_next_state = START; + FINALIZE1: begin + if (&(~{data_out_fifo_full, addr_out_fifo_full, ID_out_fifo_full})) begin + scan_seq_next_state = FINALIZE2; + end + else scan_seq_next_state = FINALIZE1; + end + FINALIZE2: begin + if (&(~{data_out_fifo_full, addr_out_fifo_full, ID_out_fifo_full})) begin + scan_seq_next_state = DONE; + end + else scan_seq_next_state = FINALIZE2; + end + LL: begin + if (init_blank & (~blank_done_stick_sticky)) begin + scan_seq_next_state = FINALIZE2; + end + else if (compressed & ((~init_blank) | blank_done_stick_sticky)) begin + scan_seq_next_state = ComLL; + end + else if ((~compressed) & ((~init_blank) | blank_done_stick_sticky)) begin + scan_seq_next_state = UnLL; + end + end + START: begin + if (tile_en) begin + scan_seq_next_state = ALLOCATE1; + end + else scan_seq_next_state = START; + end + UL: begin + if (data_infifo_valid_in) begin + scan_seq_next_state = UL_EMIT; + end + else scan_seq_next_state = UL; + end + UL_EMIT: begin + if (data_done_in) begin + scan_seq_next_state = FINALIZE1; + end + else scan_seq_next_state = UL_EMIT; + end + UL_WZ: begin + if (&(~{data_out_fifo_full, addr_out_fifo_full, ID_out_fifo_full})) begin + scan_seq_next_state = UL; + end + else if (~(&(~{data_out_fifo_full, addr_out_fifo_full, ID_out_fifo_full}))) begin + scan_seq_next_state = UL_WZ; + end + end + UnLL: begin + if (data_done_in & addr_done_in) begin + scan_seq_next_state = FINALIZE2; + end + else scan_seq_next_state = UnLL; + end + default: begin end + endcase +end +always_comb begin + unique case (scan_seq_current_state) + ALLOCATE1: begin :scan_seq_ALLOCATE1_Output + data_to_fifo = 16'h0; + op_to_fifo = 1'h0; + addr_to_fifo = 16'h0; + ID_to_fifo = 16'h0; + push_to_outs = 1'h1; + inc_seg_addr = 1'h0; + clr_seg_addr = 1'h0; + inc_coord_addr = 1'h0; + clr_coord_addr = 1'h0; + inc_seg_ctr = 1'h0; + clr_seg_ctr = 1'h0; + set_curr_coord = 1'h0; + clr_curr_coord = 1'h0; + infifo_pop[0] = 1'h0; + infifo_pop[1] = 1'h0; + clr_wen_made = 1'h0; + set_block_size = 1'h0; + inc_block_write = 1'h0; + clr_block_write = 1'h0; + IN_DONE = 1'h0; + pop_block_wr = 1'h0; + set_blank_done = 1'h0; + clr_blank_done = 1'h0; + end :scan_seq_ALLOCATE1_Output + ALLOCATE2: begin :scan_seq_ALLOCATE2_Output + data_to_fifo = 16'h0; + op_to_fifo = 1'h0; + addr_to_fifo = 16'h0; + ID_to_fifo = 16'h1; + push_to_outs = 1'h1; + inc_seg_addr = 1'h0; + clr_seg_addr = 1'h0; + inc_coord_addr = 1'h0; + clr_coord_addr = 1'h0; + inc_seg_ctr = 1'h0; + clr_seg_ctr = 1'h0; + set_curr_coord = 1'h0; + clr_curr_coord = 1'h0; + infifo_pop[0] = 1'h0; + infifo_pop[1] = 1'h0; + clr_wen_made = 1'h0; + set_block_size = 1'h0; + inc_block_write = 1'h0; + clr_block_write = 1'h0; + IN_DONE = 1'h0; + pop_block_wr = 1'h0; + set_blank_done = 1'h0; + clr_blank_done = 1'h0; + end :scan_seq_ALLOCATE2_Output + BLOCK_1_SZ: begin :scan_seq_BLOCK_1_SZ_Output + data_to_fifo = 16'h0; + op_to_fifo = 1'h0; + addr_to_fifo = 16'h0; + ID_to_fifo = 16'h1; + push_to_outs = 1'h0; + inc_seg_addr = 1'h0; + clr_seg_addr = 1'h0; + inc_coord_addr = 1'h0; + clr_coord_addr = 1'h0; + inc_seg_ctr = 1'h0; + clr_seg_ctr = 1'h0; + set_curr_coord = 1'h0; + clr_curr_coord = 1'h0; + infifo_pop[0] = 1'h0; + infifo_pop[1] = 1'h0; + clr_wen_made = 1'h0; + set_block_size = block_wr_fifo_valid; + inc_block_write = 1'h0; + clr_block_write = 1'h1; + pop_block_wr = block_wr_fifo_valid; + IN_DONE = 1'h0; + set_blank_done = 1'h0; + clr_blank_done = 1'h0; + end :scan_seq_BLOCK_1_SZ_Output + BLOCK_1_WR: begin :scan_seq_BLOCK_1_WR_Output + data_to_fifo = block_wr_input_fifo_data_out; + op_to_fifo = 1'h1; + addr_to_fifo = block_write_count; + ID_to_fifo = 16'h0; + push_to_outs = block_wr_fifo_valid & (block_write_count < block_size); + inc_seg_addr = 1'h0; + clr_seg_addr = 1'h0; + inc_coord_addr = 1'h0; + clr_coord_addr = 1'h0; + inc_seg_ctr = 1'h0; + clr_seg_ctr = 1'h0; + set_curr_coord = 1'h0; + clr_curr_coord = 1'h0; + infifo_pop[0] = 1'h0; + infifo_pop[1] = 1'h0; + clr_wen_made = 1'h0; + set_block_size = 1'h0; + inc_block_write = block_wr_fifo_valid & (block_write_count < block_size) & + (&(~{data_out_fifo_full, addr_out_fifo_full, ID_out_fifo_full})); + clr_block_write = 1'h0; + pop_block_wr = block_wr_fifo_valid & (block_write_count < block_size) & + (&(~{data_out_fifo_full, addr_out_fifo_full, ID_out_fifo_full})); + IN_DONE = 1'h0; + set_blank_done = 1'h0; + clr_blank_done = 1'h0; + end :scan_seq_BLOCK_1_WR_Output + BLOCK_2_SZ: begin :scan_seq_BLOCK_2_SZ_Output + data_to_fifo = 16'h0; + op_to_fifo = 1'h0; + addr_to_fifo = 16'h0; + ID_to_fifo = 16'h0; + push_to_outs = 1'h0; + inc_seg_addr = 1'h0; + clr_seg_addr = 1'h0; + inc_coord_addr = 1'h0; + clr_coord_addr = 1'h0; + inc_seg_ctr = 1'h0; + clr_seg_ctr = 1'h0; + set_curr_coord = 1'h0; + clr_curr_coord = 1'h0; + infifo_pop[0] = 1'h0; + infifo_pop[1] = 1'h0; + clr_wen_made = 1'h0; + set_block_size = block_wr_fifo_valid; + inc_block_write = 1'h0; + clr_block_write = 1'h1; + pop_block_wr = block_wr_fifo_valid; + IN_DONE = 1'h0; + set_blank_done = 1'h0; + clr_blank_done = 1'h0; + end :scan_seq_BLOCK_2_SZ_Output + BLOCK_2_WR: begin :scan_seq_BLOCK_2_WR_Output + data_to_fifo = block_wr_input_fifo_data_out; + op_to_fifo = 1'h1; + addr_to_fifo = block_write_count; + ID_to_fifo = 16'h1; + push_to_outs = block_wr_fifo_valid & (block_write_count < block_size); + inc_seg_addr = 1'h0; + clr_seg_addr = 1'h0; + inc_coord_addr = 1'h0; + clr_coord_addr = 1'h0; + inc_seg_ctr = 1'h0; + clr_seg_ctr = 1'h0; + set_curr_coord = 1'h0; + clr_curr_coord = 1'h0; + infifo_pop[0] = 1'h0; + infifo_pop[1] = 1'h0; + clr_wen_made = 1'h0; + set_block_size = 1'h0; + inc_block_write = block_wr_fifo_valid & (block_write_count < block_size) & + (&(~{data_out_fifo_full, addr_out_fifo_full, ID_out_fifo_full})); + clr_block_write = 1'h0; + pop_block_wr = block_wr_fifo_valid & (block_write_count < block_size) & + (&(~{data_out_fifo_full, addr_out_fifo_full, ID_out_fifo_full})); + IN_DONE = 1'h0; + set_blank_done = 1'h0; + clr_blank_done = 1'h0; + end :scan_seq_BLOCK_2_WR_Output + ComLL: begin :scan_seq_ComLL_Output + data_to_fifo = data_infifo_data_in; + op_to_fifo = 1'h1; + addr_to_fifo = segment_addr; + ID_to_fifo = 16'h0; + push_to_outs = data_infifo_valid_in & (~data_infifo_eos_in); + inc_seg_addr = data_infifo_valid_in & (~data_infifo_eos_in) & (&(~{data_out_fifo_full, + addr_out_fifo_full, ID_out_fifo_full})); + clr_seg_addr = 1'h0; + inc_coord_addr = 1'h0; + clr_coord_addr = 1'h0; + inc_seg_ctr = 1'h0; + clr_seg_ctr = 1'h0; + set_curr_coord = 1'h0; + clr_curr_coord = 1'h0; + infifo_pop[0] = data_infifo_valid_in & (data_infifo_eos_in | (&(~{data_out_fifo_full, + addr_out_fifo_full, ID_out_fifo_full}))); + infifo_pop[1] = 1'h0; + clr_wen_made = 1'h0; + set_block_size = 1'h0; + inc_block_write = 1'h0; + clr_block_write = 1'h0; + IN_DONE = 1'h0; + pop_block_wr = 1'h0; + set_blank_done = 1'h0; + clr_blank_done = 1'h0; + end :scan_seq_ComLL_Output + DONE: begin :scan_seq_DONE_Output + data_to_fifo = 16'h0; + op_to_fifo = 1'h0; + addr_to_fifo = 16'h0; + ID_to_fifo = 16'h0; + push_to_outs = 1'h0; + inc_seg_addr = 1'h0; + clr_seg_addr = 1'h0; + inc_coord_addr = 1'h0; + clr_coord_addr = 1'h0; + inc_seg_ctr = 1'h0; + clr_seg_ctr = 1'h0; + set_curr_coord = 1'h0; + clr_curr_coord = 1'h0; + infifo_pop[0] = data_done_in; + infifo_pop[1] = 1'h0; + clr_wen_made = 1'h0; + set_block_size = 1'h0; + inc_block_write = 1'h0; + clr_block_write = 1'h0; + set_blank_done = 1'h0; + clr_blank_done = 1'h0; + IN_DONE = 1'h1; + pop_block_wr = 1'h0; + end :scan_seq_DONE_Output + FINALIZE1: begin :scan_seq_FINALIZE1_Output + data_to_fifo = 16'h0; + op_to_fifo = 1'h0; + addr_to_fifo = 16'h0; + ID_to_fifo = 16'h1; + push_to_outs = 1'h1; + inc_seg_addr = 1'h0; + clr_seg_addr = 1'h0; + inc_coord_addr = 1'h0; + clr_coord_addr = 1'h0; + inc_seg_ctr = 1'h0; + clr_seg_ctr = 1'h0; + set_curr_coord = 1'h0; + clr_curr_coord = 1'h0; + infifo_pop[0] = 1'h0; + infifo_pop[1] = 1'h0; + clr_wen_made = 1'h0; + set_block_size = 1'h0; + inc_block_write = 1'h0; + clr_block_write = 1'h0; + IN_DONE = 1'h0; + pop_block_wr = 1'h0; + set_blank_done = 1'h0; + clr_blank_done = 1'h0; + end :scan_seq_FINALIZE1_Output + FINALIZE2: begin :scan_seq_FINALIZE2_Output + data_to_fifo = 16'h0; + op_to_fifo = 1'h0; + addr_to_fifo = 16'h0; + ID_to_fifo = 16'h0; + push_to_outs = 1'h1; + inc_seg_addr = 1'h0; + clr_seg_addr = 1'h0; + inc_coord_addr = 1'h0; + clr_coord_addr = 1'h0; + inc_seg_ctr = 1'h0; + clr_seg_ctr = 1'h0; + set_curr_coord = 1'h0; + clr_curr_coord = 1'h0; + infifo_pop[0] = 1'h0; + infifo_pop[1] = 1'h0; + clr_wen_made = 1'h0; + set_block_size = 1'h0; + inc_block_write = 1'h0; + clr_block_write = 1'h0; + IN_DONE = 1'h0; + pop_block_wr = 1'h0; + set_blank_done = 1'h0; + clr_blank_done = 1'h0; + end :scan_seq_FINALIZE2_Output + LL: begin :scan_seq_LL_Output + data_to_fifo = 16'h0; + op_to_fifo = 1'h0; + addr_to_fifo = 16'h0; + ID_to_fifo = 16'h0; + push_to_outs = 1'h0; + inc_seg_addr = 1'h0; + clr_seg_addr = 1'h0; + inc_coord_addr = 1'h0; + clr_coord_addr = 1'h0; + inc_seg_ctr = 1'h0; + clr_seg_ctr = 1'h0; + set_curr_coord = 1'h0; + clr_curr_coord = 1'h0; + infifo_pop[0] = 1'h0; + infifo_pop[1] = 1'h0; + clr_wen_made = 1'h0; + set_block_size = 1'h0; + inc_block_write = 1'h0; + clr_block_write = 1'h0; + IN_DONE = 1'h0; + pop_block_wr = 1'h0; + set_blank_done = 1'h0; + clr_blank_done = 1'h0; + end :scan_seq_LL_Output + START: begin :scan_seq_START_Output + data_to_fifo = 16'h0; + op_to_fifo = 1'h0; + addr_to_fifo = 16'h0; + ID_to_fifo = 16'h0; + push_to_outs = 1'h0; + inc_seg_addr = 1'h0; + clr_seg_addr = 1'h1; + inc_coord_addr = 1'h0; + clr_coord_addr = 1'h1; + inc_seg_ctr = 1'h0; + clr_seg_ctr = 1'h1; + set_curr_coord = 1'h0; + clr_curr_coord = 1'h1; + infifo_pop[0] = 1'h0; + infifo_pop[1] = 1'h0; + clr_wen_made = 1'h1; + set_block_size = 1'h0; + inc_block_write = 1'h0; + clr_block_write = 1'h1; + IN_DONE = 1'h0; + pop_block_wr = 1'h0; + set_blank_done = 1'h0; + clr_blank_done = 1'h0; + end :scan_seq_START_Output + UL: begin :scan_seq_UL_Output + data_to_fifo = 16'h0; + op_to_fifo = 1'h1; + addr_to_fifo = 16'h0; + ID_to_fifo = 16'h0; + push_to_outs = 1'h0; + inc_seg_addr = 1'h0; + clr_seg_addr = 1'h0; + inc_coord_addr = 1'h0; + clr_coord_addr = 1'h0; + inc_seg_ctr = 1'h0; + clr_seg_ctr = 1'h0; + set_curr_coord = new_coord; + clr_curr_coord = 1'h0; + infifo_pop[0] = 1'h0; + infifo_pop[1] = 1'h0; + clr_wen_made = 1'h1; + set_block_size = 1'h0; + inc_block_write = 1'h0; + clr_block_write = 1'h0; + IN_DONE = 1'h0; + pop_block_wr = 1'h0; + set_blank_done = 1'h0; + clr_blank_done = 1'h0; + end :scan_seq_UL_Output + UL_EMIT: begin :scan_seq_UL_EMIT_Output + data_to_fifo = stop_in ? segment_counter: data_infifo_data_in; + op_to_fifo = 1'h1; + addr_to_fifo = stop_in ? segment_addr: coord_addr; + ID_to_fifo = stop_in ? 16'h0: 16'h1; + push_to_outs = data_infifo_valid_in & (&(~{data_out_fifo_full, addr_out_fifo_full, + ID_out_fifo_full})) & (~data_done_in); + inc_seg_addr = stop_in & (&(~{data_out_fifo_full, addr_out_fifo_full, ID_out_fifo_full})) & + (~data_done_in); + clr_seg_addr = 1'h0; + inc_coord_addr = (~data_infifo_eos_in) & data_infifo_valid_in & (&(~{data_out_fifo_full, + addr_out_fifo_full, ID_out_fifo_full})); + clr_coord_addr = 1'h0; + inc_seg_ctr = (~data_infifo_eos_in) & data_infifo_valid_in & (&(~{data_out_fifo_full, + addr_out_fifo_full, ID_out_fifo_full})); + clr_seg_ctr = 1'h0; + set_curr_coord = new_coord; + clr_curr_coord = ~wen_made_sticky; + infifo_pop[0] = data_infifo_valid_in & (&(~{data_out_fifo_full, addr_out_fifo_full, + ID_out_fifo_full})) & (~data_done_in); + infifo_pop[1] = 1'h0; + clr_wen_made = wen_made_sticky & data_infifo_valid_in; + set_block_size = 1'h0; + inc_block_write = 1'h0; + clr_block_write = 1'h0; + IN_DONE = 1'h0; + pop_block_wr = 1'h0; + set_blank_done = 1'h0; + clr_blank_done = 1'h0; + end :scan_seq_UL_EMIT_Output + UL_WZ: begin :scan_seq_UL_WZ_Output + data_to_fifo = 16'h0; + op_to_fifo = 1'h1; + addr_to_fifo = segment_addr; + ID_to_fifo = 16'h0; + push_to_outs = 1'h1; + inc_seg_addr = &(~{data_out_fifo_full, addr_out_fifo_full, ID_out_fifo_full}); + clr_seg_addr = 1'h0; + inc_coord_addr = 1'h0; + clr_coord_addr = 1'h0; + inc_seg_ctr = 1'h0; + clr_seg_ctr = 1'h0; + set_curr_coord = 1'h0; + clr_curr_coord = 1'h0; + infifo_pop[0] = 1'h0; + infifo_pop[1] = 1'h0; + clr_wen_made = 1'h0; + set_block_size = 1'h0; + inc_block_write = 1'h0; + clr_block_write = 1'h0; + IN_DONE = 1'h0; + pop_block_wr = 1'h0; + set_blank_done = 1'h0; + clr_blank_done = 1'h0; + end :scan_seq_UL_WZ_Output + UnLL: begin :scan_seq_UnLL_Output + data_to_fifo = data_infifo_data_in; + op_to_fifo = 1'h1; + addr_to_fifo = addr_infifo_data_in; + ID_to_fifo = 16'h0; + push_to_outs = data_infifo_valid_in & addr_infifo_valid_in & (~(data_infifo_eos_in | + addr_infifo_eos_in)); + inc_seg_addr = 1'h0; + clr_seg_addr = 1'h0; + inc_coord_addr = 1'h0; + clr_coord_addr = 1'h0; + inc_seg_ctr = 1'h0; + clr_seg_ctr = 1'h0; + set_curr_coord = 1'h0; + clr_curr_coord = 1'h0; + infifo_pop[0] = data_infifo_valid_in & addr_infifo_valid_in & ((data_infifo_eos_in & + addr_infifo_eos_in) | (&(~{data_out_fifo_full, addr_out_fifo_full, + ID_out_fifo_full}))); + infifo_pop[1] = data_infifo_valid_in & addr_infifo_valid_in & ((data_infifo_eos_in & + addr_infifo_eos_in) | (&(~{data_out_fifo_full, addr_out_fifo_full, + ID_out_fifo_full}))); + clr_wen_made = 1'h0; + set_block_size = 1'h0; + inc_block_write = 1'h0; + clr_block_write = 1'h0; + IN_DONE = 1'h0; + pop_block_wr = 1'h0; + set_blank_done = 1'h0; + clr_blank_done = 1'h0; + end :scan_seq_UnLL_Output + default: begin end + endcase +end +reg_fifo_depth_2_w_17_afd_2 data_input_fifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in(data_infifo_in_packed), + .flush(flush), + .pop(infifo_pop[0]), + .push(data_in_valid), + .rst_n(rst_n), + .data_out(data_infifo_out_packed), + .empty(data_input_fifo_empty), + .full(data_input_fifo_full) +); + +reg_fifo_depth_0_w_17_afd_2 addr_input_fifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in(addr_infifo_in_packed), + .flush(flush), + .pop(infifo_pop[1]), + .push(addr_in_valid), + .rst_n(rst_n), + .data_out(addr_infifo_out_packed), + .empty(addr_input_fifo_empty), + .full(addr_input_fifo_full) +); + +reg_fifo_depth_0_w_16_afd_2 block_wr_input_fifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in(block_wr_in[15:0]), + .flush(flush), + .pop(pop_block_wr), + .push(block_wr_in_valid), + .rst_n(rst_n), + .data_out(block_wr_input_fifo_data_out), + .empty(block_wr_input_fifo_empty), + .full(block_wr_input_fifo_full) +); + +reg_fifo_depth_2_w_17_afd_2 data_out_fifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in(data_out_fifo_data_in), + .flush(flush), + .pop(data_out_ready), + .push(data_out_fifo_push), + .rst_n(rst_n), + .data_out(data_out), + .empty(data_out_fifo_empty), + .full(data_out_fifo_full) +); + +reg_fifo_depth_2_w_17_afd_2 addr_out_fifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in(addr_out_fifo_data_in), + .flush(flush), + .pop(addr_out_ready), + .push(addr_out_fifo_push), + .rst_n(rst_n), + .data_out(addr_out), + .empty(addr_out_fifo_empty), + .full(addr_out_fifo_full) +); + +reg_fifo_depth_2_w_17_afd_2 ID_out_fifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in(ID_out_fifo_data_in), + .flush(flush), + .pop(ID_out_ready), + .push(ID_out_fifo_push), + .rst_n(rst_n), + .data_out(ID_out), + .empty(ID_out_fifo_empty), + .full(ID_out_fifo_full) +); + +endmodule // write_scanner + diff --git a/sam/onyx/.magma/PE_inner_W-kratos.sv b/sam/onyx/.magma/PE_inner_W-kratos.sv new file mode 100644 index 00000000..23e35031 --- /dev/null +++ b/sam/onyx/.magma/PE_inner_W-kratos.sv @@ -0,0 +1,3389 @@ +module PE_inner ( + input logic [31:0] CONFIG_SPACE_0, + input logic [31:0] CONFIG_SPACE_1, + input logic [31:0] CONFIG_SPACE_2, + input logic [27:0] CONFIG_SPACE_3, + input logic [0:0] [16:0] PE_input_width_17_num_0, + input logic PE_input_width_17_num_0_dense, + input logic PE_input_width_17_num_0_valid, + input logic [0:0] [16:0] PE_input_width_17_num_1, + input logic PE_input_width_17_num_1_dense, + input logic PE_input_width_17_num_1_valid, + input logic [0:0] [16:0] PE_input_width_17_num_2, + input logic PE_input_width_17_num_2_dense, + input logic PE_input_width_17_num_2_valid, + input logic [0:0] [16:0] PE_input_width_17_num_3, + input logic PE_input_width_17_num_3_valid, + input logic PE_input_width_1_num_0, + input logic PE_input_width_1_num_1, + input logic PE_input_width_1_num_2, + input logic PE_output_width_17_num_0_ready, + input logic PE_output_width_17_num_1_dense, + input logic PE_output_width_17_num_1_ready, + input logic PE_output_width_17_num_2_ready, + input logic clk, + input logic clk_en, + input logic flush, + input logic [2:0] mode, + input logic rst_n, + input logic tile_en, + output logic PE_input_width_17_num_0_ready, + output logic PE_input_width_17_num_1_ready, + output logic PE_input_width_17_num_2_ready, + output logic PE_input_width_17_num_3_ready, + output logic [0:0] [16:0] PE_output_width_17_num_0, + output logic PE_output_width_17_num_0_valid, + output logic [0:0] [16:0] PE_output_width_17_num_1, + output logic PE_output_width_17_num_1_valid, + output logic [0:0] [16:0] PE_output_width_17_num_2, + output logic PE_output_width_17_num_2_valid, + output logic PE_output_width_1_num_0, + output logic [15:0] reduce_pe_cluster_inst_pe_onyxpeintf_O2, + output logic [15:0] reduce_pe_cluster_inst_pe_onyxpeintf_O3, + output logic [15:0] reduce_pe_cluster_inst_pe_onyxpeintf_O4 +); + +logic [123:0] CONFIG_SPACE; +logic gclk; +logic [0:0][16:0] input_width_17_num_0_fifo_out; +logic input_width_17_num_0_fifo_out_ready; +logic input_width_17_num_0_fifo_out_valid; +logic input_width_17_num_0_input_fifo_empty; +logic input_width_17_num_0_input_fifo_full; +logic [0:0][16:0] input_width_17_num_1_fifo_out; +logic input_width_17_num_1_fifo_out_ready; +logic input_width_17_num_1_fifo_out_valid; +logic input_width_17_num_1_input_fifo_empty; +logic input_width_17_num_1_input_fifo_full; +logic [0:0][16:0] input_width_17_num_2_fifo_out; +logic input_width_17_num_2_fifo_out_ready; +logic input_width_17_num_2_fifo_out_valid; +logic input_width_17_num_2_input_fifo_empty; +logic input_width_17_num_2_input_fifo_full; +logic [0:0][16:0] input_width_17_num_3_fifo_out; +logic input_width_17_num_3_fifo_out_ready; +logic input_width_17_num_3_fifo_out_valid; +logic input_width_17_num_3_input_fifo_empty; +logic input_width_17_num_3_input_fifo_full; +logic [15:0] mem_ctrl_RepeatSignalGenerator_flat_RepeatSignalGenerator_inst_stop_lvl; +logic mem_ctrl_RepeatSignalGenerator_flat_RepeatSignalGenerator_inst_tile_en; +logic mem_ctrl_RepeatSignalGenerator_flat_base_data_in_ready_f_; +logic mem_ctrl_RepeatSignalGenerator_flat_clk; +logic [0:0][16:0] mem_ctrl_RepeatSignalGenerator_flat_repsig_data_out_f_; +logic mem_ctrl_RepeatSignalGenerator_flat_repsig_data_out_valid_f_; +logic mem_ctrl_Repeat_flat_Repeat_inst_root; +logic mem_ctrl_Repeat_flat_Repeat_inst_spacc_mode; +logic [15:0] mem_ctrl_Repeat_flat_Repeat_inst_stop_lvl; +logic mem_ctrl_Repeat_flat_Repeat_inst_tile_en; +logic mem_ctrl_Repeat_flat_clk; +logic mem_ctrl_Repeat_flat_proc_data_in_ready_f_; +logic [0:0][16:0] mem_ctrl_Repeat_flat_ref_data_out_f_; +logic mem_ctrl_Repeat_flat_ref_data_out_valid_f_; +logic mem_ctrl_Repeat_flat_repsig_data_in_ready_f_; +logic mem_ctrl_crddrop_flat_clk; +logic mem_ctrl_crddrop_flat_cmrg_coord_in_0_ready_f_; +logic mem_ctrl_crddrop_flat_cmrg_coord_in_1_ready_f_; +logic [0:0][16:0] mem_ctrl_crddrop_flat_cmrg_coord_out_0_f_; +logic mem_ctrl_crddrop_flat_cmrg_coord_out_0_valid_f_; +logic [0:0][16:0] mem_ctrl_crddrop_flat_cmrg_coord_out_1_f_; +logic mem_ctrl_crddrop_flat_cmrg_coord_out_1_valid_f_; +logic mem_ctrl_crddrop_flat_crddrop_inst_cmrg_enable; +logic mem_ctrl_crddrop_flat_crddrop_inst_cmrg_mode; +logic [15:0] mem_ctrl_crddrop_flat_crddrop_inst_cmrg_stop_lvl; +logic mem_ctrl_crddrop_flat_crddrop_inst_tile_en; +logic mem_ctrl_crdhold_flat_clk; +logic mem_ctrl_crdhold_flat_cmrg_coord_in_0_ready_f_; +logic mem_ctrl_crdhold_flat_cmrg_coord_in_1_ready_f_; +logic [0:0][16:0] mem_ctrl_crdhold_flat_cmrg_coord_out_0_f_; +logic mem_ctrl_crdhold_flat_cmrg_coord_out_0_valid_f_; +logic [0:0][16:0] mem_ctrl_crdhold_flat_cmrg_coord_out_1_f_; +logic mem_ctrl_crdhold_flat_cmrg_coord_out_1_valid_f_; +logic mem_ctrl_crdhold_flat_crdhold_inst_cmrg_enable; +logic [15:0] mem_ctrl_crdhold_flat_crdhold_inst_cmrg_stop_lvl; +logic mem_ctrl_crdhold_flat_crdhold_inst_tile_en; +logic mem_ctrl_intersect_unit_flat_clk; +logic mem_ctrl_intersect_unit_flat_coord_in_0_ready_f_; +logic mem_ctrl_intersect_unit_flat_coord_in_1_ready_f_; +logic [0:0][16:0] mem_ctrl_intersect_unit_flat_coord_out_f_; +logic mem_ctrl_intersect_unit_flat_coord_out_valid_f_; +logic mem_ctrl_intersect_unit_flat_intersect_unit_inst_joiner_op; +logic mem_ctrl_intersect_unit_flat_intersect_unit_inst_tile_en; +logic mem_ctrl_intersect_unit_flat_intersect_unit_inst_vector_reduce_mode; +logic mem_ctrl_intersect_unit_flat_pos_in_0_ready_f_; +logic mem_ctrl_intersect_unit_flat_pos_in_1_ready_f_; +logic [0:0][16:0] mem_ctrl_intersect_unit_flat_pos_out_0_f_; +logic mem_ctrl_intersect_unit_flat_pos_out_0_valid_f_; +logic [0:0][16:0] mem_ctrl_intersect_unit_flat_pos_out_1_f_; +logic mem_ctrl_intersect_unit_flat_pos_out_1_valid_f_; +logic mem_ctrl_reduce_pe_cluster_flat_clk; +logic [0:0][16:0] mem_ctrl_reduce_pe_cluster_flat_data0_f_; +logic mem_ctrl_reduce_pe_cluster_flat_data0_ready_f_; +logic mem_ctrl_reduce_pe_cluster_flat_data0_valid_f_; +logic [0:0][16:0] mem_ctrl_reduce_pe_cluster_flat_data1_f_; +logic mem_ctrl_reduce_pe_cluster_flat_data1_ready_f_; +logic mem_ctrl_reduce_pe_cluster_flat_data1_valid_f_; +logic [0:0][16:0] mem_ctrl_reduce_pe_cluster_flat_data2_f_; +logic mem_ctrl_reduce_pe_cluster_flat_data2_ready_f_; +logic mem_ctrl_reduce_pe_cluster_flat_data2_valid_f_; +logic mem_ctrl_reduce_pe_cluster_flat_reduce_data_in_ready_f_; +logic [0:0][16:0] mem_ctrl_reduce_pe_cluster_flat_reduce_data_out_f_; +logic mem_ctrl_reduce_pe_cluster_flat_reduce_data_out_valid_f_; +logic mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_pe_dense_mode; +logic mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_pe_in_external; +logic [83:0] mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_pe_onyxpeintf_inst; +logic [2:0] mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_pe_sparse_num_inputs; +logic mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_pe_tile_en; +logic [15:0] mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_reduce_default_value; +logic [15:0] mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_reduce_stop_lvl; +logic mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_reduce_tile_en; +logic mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_tile_en; +logic [0:0][16:0] mem_ctrl_reduce_pe_cluster_flat_res_f_; +logic mem_ctrl_reduce_pe_cluster_flat_res_p_f_; +logic mem_ctrl_reduce_pe_cluster_flat_res_ready_f_; +logic mem_ctrl_reduce_pe_cluster_flat_res_valid_f_; +logic [0:0][16:0] output_width_17_num_0_fifo_in; +logic output_width_17_num_0_fifo_in_ready; +logic output_width_17_num_0_fifo_in_valid; +logic [0:0][16:0] output_width_17_num_0_output_fifo_data_out; +logic output_width_17_num_0_output_fifo_empty; +logic output_width_17_num_0_output_fifo_full; +logic [0:0][16:0] output_width_17_num_1_fifo_in; +logic output_width_17_num_1_fifo_in_ready; +logic output_width_17_num_1_fifo_in_valid; +logic [0:0][16:0] output_width_17_num_1_output_fifo_data_out; +logic output_width_17_num_1_output_fifo_empty; +logic output_width_17_num_1_output_fifo_full; +logic [0:0][16:0] output_width_17_num_2_fifo_in; +logic output_width_17_num_2_fifo_in_ready; +logic output_width_17_num_2_fifo_in_valid; +logic [0:0][16:0] output_width_17_num_2_output_fifo_data_out; +logic output_width_17_num_2_output_fifo_empty; +logic output_width_17_num_2_output_fifo_full; +assign gclk = clk & tile_en; +assign mem_ctrl_intersect_unit_flat_clk = gclk & (mode == 3'h0); +assign mem_ctrl_crddrop_flat_clk = gclk & (mode == 3'h1); +assign mem_ctrl_crdhold_flat_clk = gclk & (mode == 3'h2); +assign mem_ctrl_Repeat_flat_clk = gclk & (mode == 3'h3); +assign mem_ctrl_RepeatSignalGenerator_flat_clk = gclk & (mode == 3'h4); +assign mem_ctrl_reduce_pe_cluster_flat_clk = gclk & (mode == 3'h5); +assign input_width_17_num_0_fifo_out_valid = ~input_width_17_num_0_input_fifo_empty; +always_comb begin + input_width_17_num_0_fifo_out_ready = 1'h1; + if (mode == 3'h0) begin + input_width_17_num_0_fifo_out_ready = mem_ctrl_intersect_unit_flat_coord_in_0_ready_f_; + end + else if (mode == 3'h1) begin + input_width_17_num_0_fifo_out_ready = mem_ctrl_crddrop_flat_cmrg_coord_in_0_ready_f_; + end + else if (mode == 3'h2) begin + input_width_17_num_0_fifo_out_ready = mem_ctrl_crdhold_flat_cmrg_coord_in_0_ready_f_; + end + else if (mode == 3'h3) begin + input_width_17_num_0_fifo_out_ready = mem_ctrl_Repeat_flat_proc_data_in_ready_f_; + end + else if (mode == 3'h4) begin + input_width_17_num_0_fifo_out_ready = mem_ctrl_RepeatSignalGenerator_flat_base_data_in_ready_f_; + end + else if (mode == 3'h5) begin + input_width_17_num_0_fifo_out_ready = mem_ctrl_reduce_pe_cluster_flat_data0_ready_f_; + end +end +assign mem_ctrl_reduce_pe_cluster_flat_data0_f_ = PE_input_width_17_num_0_dense ? PE_input_width_17_num_0: + input_width_17_num_0_fifo_out; +assign mem_ctrl_reduce_pe_cluster_flat_data0_valid_f_ = PE_input_width_17_num_0_dense ? 1'h1: input_width_17_num_0_fifo_out_valid; +always_comb begin + PE_input_width_17_num_0_ready = 1'h1; + if (mode == 3'h0) begin + PE_input_width_17_num_0_ready = ~input_width_17_num_0_input_fifo_full; + end + else if (mode == 3'h1) begin + PE_input_width_17_num_0_ready = ~input_width_17_num_0_input_fifo_full; + end + else if (mode == 3'h2) begin + PE_input_width_17_num_0_ready = ~input_width_17_num_0_input_fifo_full; + end + else if (mode == 3'h3) begin + PE_input_width_17_num_0_ready = ~input_width_17_num_0_input_fifo_full; + end + else if (mode == 3'h4) begin + PE_input_width_17_num_0_ready = ~input_width_17_num_0_input_fifo_full; + end + else if (mode == 3'h5) begin + PE_input_width_17_num_0_ready = PE_input_width_17_num_0_dense ? 1'h1: ~input_width_17_num_0_input_fifo_full; + end +end +assign input_width_17_num_1_fifo_out_valid = ~input_width_17_num_1_input_fifo_empty; +always_comb begin + input_width_17_num_1_fifo_out_ready = 1'h1; + if (mode == 3'h0) begin + input_width_17_num_1_fifo_out_ready = mem_ctrl_intersect_unit_flat_coord_in_1_ready_f_; + end + else if (mode == 3'h1) begin + input_width_17_num_1_fifo_out_ready = mem_ctrl_crddrop_flat_cmrg_coord_in_1_ready_f_; + end + else if (mode == 3'h2) begin + input_width_17_num_1_fifo_out_ready = mem_ctrl_crdhold_flat_cmrg_coord_in_1_ready_f_; + end + else if (mode == 3'h3) begin + input_width_17_num_1_fifo_out_ready = mem_ctrl_Repeat_flat_repsig_data_in_ready_f_; + end + else if (mode == 3'h5) begin + input_width_17_num_1_fifo_out_ready = mem_ctrl_reduce_pe_cluster_flat_data1_ready_f_; + end +end +assign mem_ctrl_reduce_pe_cluster_flat_data1_f_ = PE_input_width_17_num_1_dense ? PE_input_width_17_num_1: + input_width_17_num_1_fifo_out; +assign mem_ctrl_reduce_pe_cluster_flat_data1_valid_f_ = PE_input_width_17_num_1_dense ? 1'h1: input_width_17_num_1_fifo_out_valid; +always_comb begin + PE_input_width_17_num_1_ready = 1'h1; + if (mode == 3'h0) begin + PE_input_width_17_num_1_ready = ~input_width_17_num_1_input_fifo_full; + end + else if (mode == 3'h1) begin + PE_input_width_17_num_1_ready = ~input_width_17_num_1_input_fifo_full; + end + else if (mode == 3'h2) begin + PE_input_width_17_num_1_ready = ~input_width_17_num_1_input_fifo_full; + end + else if (mode == 3'h3) begin + PE_input_width_17_num_1_ready = ~input_width_17_num_1_input_fifo_full; + end + else if (mode == 3'h5) begin + PE_input_width_17_num_1_ready = PE_input_width_17_num_1_dense ? 1'h1: ~input_width_17_num_1_input_fifo_full; + end +end +assign input_width_17_num_2_fifo_out_valid = ~input_width_17_num_2_input_fifo_empty; +always_comb begin + input_width_17_num_2_fifo_out_ready = 1'h1; + if (mode == 3'h0) begin + input_width_17_num_2_fifo_out_ready = mem_ctrl_intersect_unit_flat_pos_in_0_ready_f_; + end + else if (mode == 3'h5) begin + input_width_17_num_2_fifo_out_ready = mem_ctrl_reduce_pe_cluster_flat_data2_ready_f_; + end +end +assign mem_ctrl_reduce_pe_cluster_flat_data2_f_ = PE_input_width_17_num_2_dense ? PE_input_width_17_num_2: + input_width_17_num_2_fifo_out; +assign mem_ctrl_reduce_pe_cluster_flat_data2_valid_f_ = PE_input_width_17_num_2_dense ? 1'h1: input_width_17_num_2_fifo_out_valid; +always_comb begin + PE_input_width_17_num_2_ready = 1'h1; + if (mode == 3'h0) begin + PE_input_width_17_num_2_ready = ~input_width_17_num_2_input_fifo_full; + end + else if (mode == 3'h5) begin + PE_input_width_17_num_2_ready = PE_input_width_17_num_2_dense ? 1'h1: ~input_width_17_num_2_input_fifo_full; + end +end +assign input_width_17_num_3_fifo_out_valid = ~input_width_17_num_3_input_fifo_empty; +always_comb begin + input_width_17_num_3_fifo_out_ready = 1'h1; + if (mode == 3'h0) begin + input_width_17_num_3_fifo_out_ready = mem_ctrl_intersect_unit_flat_pos_in_1_ready_f_; + end + else if (mode == 3'h5) begin + input_width_17_num_3_fifo_out_ready = mem_ctrl_reduce_pe_cluster_flat_reduce_data_in_ready_f_; + end +end +always_comb begin + PE_input_width_17_num_3_ready = 1'h1; + if (mode == 3'h0) begin + PE_input_width_17_num_3_ready = ~input_width_17_num_3_input_fifo_full; + end + else if (mode == 3'h5) begin + PE_input_width_17_num_3_ready = ~input_width_17_num_3_input_fifo_full; + end +end +assign output_width_17_num_0_fifo_in_ready = ~output_width_17_num_0_output_fifo_full; +always_comb begin + output_width_17_num_0_fifo_in = 17'h0; + output_width_17_num_0_fifo_in_valid = 1'h0; + if (mode == 3'h0) begin + output_width_17_num_0_fifo_in = mem_ctrl_intersect_unit_flat_coord_out_f_; + output_width_17_num_0_fifo_in_valid = mem_ctrl_intersect_unit_flat_coord_out_valid_f_; + end + else if (mode == 3'h1) begin + output_width_17_num_0_fifo_in = mem_ctrl_crddrop_flat_cmrg_coord_out_0_f_; + output_width_17_num_0_fifo_in_valid = mem_ctrl_crddrop_flat_cmrg_coord_out_0_valid_f_; + end + else if (mode == 3'h2) begin + output_width_17_num_0_fifo_in = mem_ctrl_crdhold_flat_cmrg_coord_out_0_f_; + output_width_17_num_0_fifo_in_valid = mem_ctrl_crdhold_flat_cmrg_coord_out_0_valid_f_; + end + else if (mode == 3'h3) begin + output_width_17_num_0_fifo_in = mem_ctrl_Repeat_flat_ref_data_out_f_; + output_width_17_num_0_fifo_in_valid = mem_ctrl_Repeat_flat_ref_data_out_valid_f_; + end + else if (mode == 3'h4) begin + output_width_17_num_0_fifo_in = mem_ctrl_RepeatSignalGenerator_flat_repsig_data_out_f_; + output_width_17_num_0_fifo_in_valid = mem_ctrl_RepeatSignalGenerator_flat_repsig_data_out_valid_f_; + end + else if (mode == 3'h5) begin + output_width_17_num_0_fifo_in = mem_ctrl_reduce_pe_cluster_flat_reduce_data_out_f_; + output_width_17_num_0_fifo_in_valid = mem_ctrl_reduce_pe_cluster_flat_reduce_data_out_valid_f_; + end +end +always_comb begin + PE_output_width_17_num_0 = 17'h0; + if (mode == 3'h0) begin + PE_output_width_17_num_0 = output_width_17_num_0_output_fifo_data_out; + end + else if (mode == 3'h1) begin + PE_output_width_17_num_0 = output_width_17_num_0_output_fifo_data_out; + end + else if (mode == 3'h2) begin + PE_output_width_17_num_0 = output_width_17_num_0_output_fifo_data_out; + end + else if (mode == 3'h3) begin + PE_output_width_17_num_0 = output_width_17_num_0_output_fifo_data_out; + end + else if (mode == 3'h4) begin + PE_output_width_17_num_0 = output_width_17_num_0_output_fifo_data_out; + end + else if (mode == 3'h5) begin + PE_output_width_17_num_0 = output_width_17_num_0_output_fifo_data_out; + end +end +always_comb begin + PE_output_width_17_num_0_valid = 1'h0; + if (mode == 3'h0) begin + PE_output_width_17_num_0_valid = ~output_width_17_num_0_output_fifo_empty; + end + else if (mode == 3'h1) begin + PE_output_width_17_num_0_valid = ~output_width_17_num_0_output_fifo_empty; + end + else if (mode == 3'h2) begin + PE_output_width_17_num_0_valid = ~output_width_17_num_0_output_fifo_empty; + end + else if (mode == 3'h3) begin + PE_output_width_17_num_0_valid = ~output_width_17_num_0_output_fifo_empty; + end + else if (mode == 3'h4) begin + PE_output_width_17_num_0_valid = ~output_width_17_num_0_output_fifo_empty; + end + else if (mode == 3'h5) begin + PE_output_width_17_num_0_valid = ~output_width_17_num_0_output_fifo_empty; + end +end +assign output_width_17_num_1_fifo_in_ready = ~output_width_17_num_1_output_fifo_full; +always_comb begin + output_width_17_num_1_fifo_in = 17'h0; + output_width_17_num_1_fifo_in_valid = 1'h0; + if (mode == 3'h0) begin + output_width_17_num_1_fifo_in = mem_ctrl_intersect_unit_flat_pos_out_0_f_; + output_width_17_num_1_fifo_in_valid = mem_ctrl_intersect_unit_flat_pos_out_0_valid_f_; + end + else if (mode == 3'h1) begin + output_width_17_num_1_fifo_in = mem_ctrl_crddrop_flat_cmrg_coord_out_1_f_; + output_width_17_num_1_fifo_in_valid = mem_ctrl_crddrop_flat_cmrg_coord_out_1_valid_f_; + end + else if (mode == 3'h2) begin + output_width_17_num_1_fifo_in = mem_ctrl_crdhold_flat_cmrg_coord_out_1_f_; + output_width_17_num_1_fifo_in_valid = mem_ctrl_crdhold_flat_cmrg_coord_out_1_valid_f_; + end + else if (mode == 3'h5) begin + output_width_17_num_1_fifo_in = mem_ctrl_reduce_pe_cluster_flat_res_f_; + output_width_17_num_1_fifo_in_valid = mem_ctrl_reduce_pe_cluster_flat_res_valid_f_; + end +end +assign mem_ctrl_reduce_pe_cluster_flat_res_ready_f_ = PE_output_width_17_num_1_dense ? 1'h1: output_width_17_num_1_fifo_in_ready; +always_comb begin + PE_output_width_17_num_1 = 17'h0; + if (mode == 3'h0) begin + PE_output_width_17_num_1 = output_width_17_num_1_output_fifo_data_out; + end + else if (mode == 3'h1) begin + PE_output_width_17_num_1 = output_width_17_num_1_output_fifo_data_out; + end + else if (mode == 3'h2) begin + PE_output_width_17_num_1 = output_width_17_num_1_output_fifo_data_out; + end + else if (mode == 3'h5) begin + PE_output_width_17_num_1 = PE_output_width_17_num_1_dense ? mem_ctrl_reduce_pe_cluster_flat_res_f_: + output_width_17_num_1_output_fifo_data_out; + end +end +always_comb begin + PE_output_width_17_num_1_valid = 1'h0; + if (mode == 3'h0) begin + PE_output_width_17_num_1_valid = ~output_width_17_num_1_output_fifo_empty; + end + else if (mode == 3'h1) begin + PE_output_width_17_num_1_valid = ~output_width_17_num_1_output_fifo_empty; + end + else if (mode == 3'h2) begin + PE_output_width_17_num_1_valid = ~output_width_17_num_1_output_fifo_empty; + end + else if (mode == 3'h5) begin + PE_output_width_17_num_1_valid = PE_output_width_17_num_1_dense ? 1'h1: ~output_width_17_num_1_output_fifo_empty; + end +end +assign output_width_17_num_2_fifo_in_ready = ~output_width_17_num_2_output_fifo_full; +always_comb begin + output_width_17_num_2_fifo_in = 17'h0; + output_width_17_num_2_fifo_in_valid = 1'h0; + output_width_17_num_2_fifo_in = mem_ctrl_intersect_unit_flat_pos_out_1_f_; + output_width_17_num_2_fifo_in_valid = mem_ctrl_intersect_unit_flat_pos_out_1_valid_f_; +end +always_comb begin + PE_output_width_17_num_2 = 17'h0; + if (mode == 3'h0) begin + PE_output_width_17_num_2 = output_width_17_num_2_output_fifo_data_out; + end + else PE_output_width_17_num_2 = 17'h0; +end +always_comb begin + PE_output_width_17_num_2_valid = 1'h0; + if (mode == 3'h0) begin + PE_output_width_17_num_2_valid = ~output_width_17_num_2_output_fifo_empty; + end + else PE_output_width_17_num_2_valid = 1'h0; +end +always_comb begin + PE_output_width_1_num_0 = 1'h0; + if (mode == 3'h5) begin + PE_output_width_1_num_0 = mem_ctrl_reduce_pe_cluster_flat_res_p_f_; + end + else PE_output_width_1_num_0 = 1'h0; +end +assign {mem_ctrl_intersect_unit_flat_intersect_unit_inst_joiner_op, mem_ctrl_intersect_unit_flat_intersect_unit_inst_tile_en, mem_ctrl_intersect_unit_flat_intersect_unit_inst_vector_reduce_mode} = CONFIG_SPACE[2:0]; +assign {mem_ctrl_crddrop_flat_crddrop_inst_cmrg_enable, mem_ctrl_crddrop_flat_crddrop_inst_cmrg_mode, mem_ctrl_crddrop_flat_crddrop_inst_cmrg_stop_lvl, mem_ctrl_crddrop_flat_crddrop_inst_tile_en} = CONFIG_SPACE[18:0]; +assign {mem_ctrl_crdhold_flat_crdhold_inst_cmrg_enable, mem_ctrl_crdhold_flat_crdhold_inst_cmrg_stop_lvl, mem_ctrl_crdhold_flat_crdhold_inst_tile_en} = CONFIG_SPACE[17:0]; +assign {mem_ctrl_Repeat_flat_Repeat_inst_root, mem_ctrl_Repeat_flat_Repeat_inst_spacc_mode, mem_ctrl_Repeat_flat_Repeat_inst_stop_lvl, mem_ctrl_Repeat_flat_Repeat_inst_tile_en} = CONFIG_SPACE[18:0]; +assign {mem_ctrl_RepeatSignalGenerator_flat_RepeatSignalGenerator_inst_stop_lvl, mem_ctrl_RepeatSignalGenerator_flat_RepeatSignalGenerator_inst_tile_en} = CONFIG_SPACE[16:0]; +assign {mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_pe_dense_mode, mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_pe_in_external, mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_pe_onyxpeintf_inst, mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_pe_sparse_num_inputs, mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_pe_tile_en, mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_reduce_default_value, mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_reduce_stop_lvl, mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_reduce_tile_en, mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_tile_en} = CONFIG_SPACE[123:0]; +assign CONFIG_SPACE[31:0] = CONFIG_SPACE_0; +assign CONFIG_SPACE[63:32] = CONFIG_SPACE_1; +assign CONFIG_SPACE[95:64] = CONFIG_SPACE_2; +assign CONFIG_SPACE[123:96] = CONFIG_SPACE_3; +intersect_unit_flat mem_ctrl_intersect_unit_flat ( + .clk(mem_ctrl_intersect_unit_flat_clk), + .clk_en(clk_en), + .coord_in_0_f_(input_width_17_num_0_fifo_out), + .coord_in_0_valid_f_(input_width_17_num_0_fifo_out_valid), + .coord_in_1_f_(input_width_17_num_1_fifo_out), + .coord_in_1_valid_f_(input_width_17_num_1_fifo_out_valid), + .coord_out_ready_f_(output_width_17_num_0_fifo_in_ready), + .flush(flush), + .intersect_unit_inst_joiner_op(mem_ctrl_intersect_unit_flat_intersect_unit_inst_joiner_op), + .intersect_unit_inst_tile_en(mem_ctrl_intersect_unit_flat_intersect_unit_inst_tile_en), + .intersect_unit_inst_vector_reduce_mode(mem_ctrl_intersect_unit_flat_intersect_unit_inst_vector_reduce_mode), + .pos_in_0_f_(input_width_17_num_2_fifo_out), + .pos_in_0_valid_f_(input_width_17_num_2_fifo_out_valid), + .pos_in_1_f_(input_width_17_num_3_fifo_out), + .pos_in_1_valid_f_(input_width_17_num_3_fifo_out_valid), + .pos_out_0_ready_f_(output_width_17_num_1_fifo_in_ready), + .pos_out_1_ready_f_(output_width_17_num_2_fifo_in_ready), + .rst_n(rst_n), + .coord_in_0_ready_f_(mem_ctrl_intersect_unit_flat_coord_in_0_ready_f_), + .coord_in_1_ready_f_(mem_ctrl_intersect_unit_flat_coord_in_1_ready_f_), + .coord_out_f_(mem_ctrl_intersect_unit_flat_coord_out_f_), + .coord_out_valid_f_(mem_ctrl_intersect_unit_flat_coord_out_valid_f_), + .pos_in_0_ready_f_(mem_ctrl_intersect_unit_flat_pos_in_0_ready_f_), + .pos_in_1_ready_f_(mem_ctrl_intersect_unit_flat_pos_in_1_ready_f_), + .pos_out_0_f_(mem_ctrl_intersect_unit_flat_pos_out_0_f_), + .pos_out_0_valid_f_(mem_ctrl_intersect_unit_flat_pos_out_0_valid_f_), + .pos_out_1_f_(mem_ctrl_intersect_unit_flat_pos_out_1_f_), + .pos_out_1_valid_f_(mem_ctrl_intersect_unit_flat_pos_out_1_valid_f_) +); + +crddrop_flat mem_ctrl_crddrop_flat ( + .clk(mem_ctrl_crddrop_flat_clk), + .clk_en(clk_en), + .cmrg_coord_in_0_f_(input_width_17_num_0_fifo_out), + .cmrg_coord_in_0_valid_f_(input_width_17_num_0_fifo_out_valid), + .cmrg_coord_in_1_f_(input_width_17_num_1_fifo_out), + .cmrg_coord_in_1_valid_f_(input_width_17_num_1_fifo_out_valid), + .cmrg_coord_out_0_ready_f_(output_width_17_num_0_fifo_in_ready), + .cmrg_coord_out_1_ready_f_(output_width_17_num_1_fifo_in_ready), + .crddrop_inst_cmrg_enable(mem_ctrl_crddrop_flat_crddrop_inst_cmrg_enable), + .crddrop_inst_cmrg_mode(mem_ctrl_crddrop_flat_crddrop_inst_cmrg_mode), + .crddrop_inst_cmrg_stop_lvl(mem_ctrl_crddrop_flat_crddrop_inst_cmrg_stop_lvl), + .crddrop_inst_tile_en(mem_ctrl_crddrop_flat_crddrop_inst_tile_en), + .flush(flush), + .rst_n(rst_n), + .cmrg_coord_in_0_ready_f_(mem_ctrl_crddrop_flat_cmrg_coord_in_0_ready_f_), + .cmrg_coord_in_1_ready_f_(mem_ctrl_crddrop_flat_cmrg_coord_in_1_ready_f_), + .cmrg_coord_out_0_f_(mem_ctrl_crddrop_flat_cmrg_coord_out_0_f_), + .cmrg_coord_out_0_valid_f_(mem_ctrl_crddrop_flat_cmrg_coord_out_0_valid_f_), + .cmrg_coord_out_1_f_(mem_ctrl_crddrop_flat_cmrg_coord_out_1_f_), + .cmrg_coord_out_1_valid_f_(mem_ctrl_crddrop_flat_cmrg_coord_out_1_valid_f_) +); + +crdhold_flat mem_ctrl_crdhold_flat ( + .clk(mem_ctrl_crdhold_flat_clk), + .clk_en(clk_en), + .cmrg_coord_in_0_f_(input_width_17_num_0_fifo_out), + .cmrg_coord_in_0_valid_f_(input_width_17_num_0_fifo_out_valid), + .cmrg_coord_in_1_f_(input_width_17_num_1_fifo_out), + .cmrg_coord_in_1_valid_f_(input_width_17_num_1_fifo_out_valid), + .cmrg_coord_out_0_ready_f_(output_width_17_num_0_fifo_in_ready), + .cmrg_coord_out_1_ready_f_(output_width_17_num_1_fifo_in_ready), + .crdhold_inst_cmrg_enable(mem_ctrl_crdhold_flat_crdhold_inst_cmrg_enable), + .crdhold_inst_cmrg_stop_lvl(mem_ctrl_crdhold_flat_crdhold_inst_cmrg_stop_lvl), + .crdhold_inst_tile_en(mem_ctrl_crdhold_flat_crdhold_inst_tile_en), + .flush(flush), + .rst_n(rst_n), + .cmrg_coord_in_0_ready_f_(mem_ctrl_crdhold_flat_cmrg_coord_in_0_ready_f_), + .cmrg_coord_in_1_ready_f_(mem_ctrl_crdhold_flat_cmrg_coord_in_1_ready_f_), + .cmrg_coord_out_0_f_(mem_ctrl_crdhold_flat_cmrg_coord_out_0_f_), + .cmrg_coord_out_0_valid_f_(mem_ctrl_crdhold_flat_cmrg_coord_out_0_valid_f_), + .cmrg_coord_out_1_f_(mem_ctrl_crdhold_flat_cmrg_coord_out_1_f_), + .cmrg_coord_out_1_valid_f_(mem_ctrl_crdhold_flat_cmrg_coord_out_1_valid_f_) +); + +Repeat_flat mem_ctrl_Repeat_flat ( + .Repeat_inst_root(mem_ctrl_Repeat_flat_Repeat_inst_root), + .Repeat_inst_spacc_mode(mem_ctrl_Repeat_flat_Repeat_inst_spacc_mode), + .Repeat_inst_stop_lvl(mem_ctrl_Repeat_flat_Repeat_inst_stop_lvl), + .Repeat_inst_tile_en(mem_ctrl_Repeat_flat_Repeat_inst_tile_en), + .clk(mem_ctrl_Repeat_flat_clk), + .clk_en(clk_en), + .flush(flush), + .proc_data_in_f_(input_width_17_num_0_fifo_out), + .proc_data_in_valid_f_(input_width_17_num_0_fifo_out_valid), + .ref_data_out_ready_f_(output_width_17_num_0_fifo_in_ready), + .repsig_data_in_f_(input_width_17_num_1_fifo_out), + .repsig_data_in_valid_f_(input_width_17_num_1_fifo_out_valid), + .rst_n(rst_n), + .proc_data_in_ready_f_(mem_ctrl_Repeat_flat_proc_data_in_ready_f_), + .ref_data_out_f_(mem_ctrl_Repeat_flat_ref_data_out_f_), + .ref_data_out_valid_f_(mem_ctrl_Repeat_flat_ref_data_out_valid_f_), + .repsig_data_in_ready_f_(mem_ctrl_Repeat_flat_repsig_data_in_ready_f_) +); + +RepeatSignalGenerator_flat mem_ctrl_RepeatSignalGenerator_flat ( + .RepeatSignalGenerator_inst_stop_lvl(mem_ctrl_RepeatSignalGenerator_flat_RepeatSignalGenerator_inst_stop_lvl), + .RepeatSignalGenerator_inst_tile_en(mem_ctrl_RepeatSignalGenerator_flat_RepeatSignalGenerator_inst_tile_en), + .base_data_in_f_(input_width_17_num_0_fifo_out), + .base_data_in_valid_f_(input_width_17_num_0_fifo_out_valid), + .clk(mem_ctrl_RepeatSignalGenerator_flat_clk), + .clk_en(clk_en), + .flush(flush), + .repsig_data_out_ready_f_(output_width_17_num_0_fifo_in_ready), + .rst_n(rst_n), + .base_data_in_ready_f_(mem_ctrl_RepeatSignalGenerator_flat_base_data_in_ready_f_), + .repsig_data_out_f_(mem_ctrl_RepeatSignalGenerator_flat_repsig_data_out_f_), + .repsig_data_out_valid_f_(mem_ctrl_RepeatSignalGenerator_flat_repsig_data_out_valid_f_) +); + +reduce_pe_cluster_flat mem_ctrl_reduce_pe_cluster_flat ( + .bit0_f_(PE_input_width_1_num_0), + .bit1_f_(PE_input_width_1_num_1), + .bit2_f_(PE_input_width_1_num_2), + .clk(mem_ctrl_reduce_pe_cluster_flat_clk), + .clk_en(clk_en), + .data0_f_(mem_ctrl_reduce_pe_cluster_flat_data0_f_), + .data0_valid_f_(mem_ctrl_reduce_pe_cluster_flat_data0_valid_f_), + .data1_f_(mem_ctrl_reduce_pe_cluster_flat_data1_f_), + .data1_valid_f_(mem_ctrl_reduce_pe_cluster_flat_data1_valid_f_), + .data2_f_(mem_ctrl_reduce_pe_cluster_flat_data2_f_), + .data2_valid_f_(mem_ctrl_reduce_pe_cluster_flat_data2_valid_f_), + .flush(flush), + .reduce_data_in_f_(input_width_17_num_3_fifo_out), + .reduce_data_in_valid_f_(input_width_17_num_3_fifo_out_valid), + .reduce_data_out_ready_f_(output_width_17_num_0_fifo_in_ready), + .reduce_pe_cluster_inst_pe_dense_mode(mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_pe_dense_mode), + .reduce_pe_cluster_inst_pe_in_external(mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_pe_in_external), + .reduce_pe_cluster_inst_pe_onyxpeintf_inst(mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_pe_onyxpeintf_inst), + .reduce_pe_cluster_inst_pe_sparse_num_inputs(mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_pe_sparse_num_inputs), + .reduce_pe_cluster_inst_pe_tile_en(mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_pe_tile_en), + .reduce_pe_cluster_inst_reduce_default_value(mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_reduce_default_value), + .reduce_pe_cluster_inst_reduce_stop_lvl(mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_reduce_stop_lvl), + .reduce_pe_cluster_inst_reduce_tile_en(mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_reduce_tile_en), + .reduce_pe_cluster_inst_tile_en(mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_tile_en), + .res_ready_f_(mem_ctrl_reduce_pe_cluster_flat_res_ready_f_), + .rst_n(rst_n), + .data0_ready_f_(mem_ctrl_reduce_pe_cluster_flat_data0_ready_f_), + .data1_ready_f_(mem_ctrl_reduce_pe_cluster_flat_data1_ready_f_), + .data2_ready_f_(mem_ctrl_reduce_pe_cluster_flat_data2_ready_f_), + .reduce_data_in_ready_f_(mem_ctrl_reduce_pe_cluster_flat_reduce_data_in_ready_f_), + .reduce_data_out_f_(mem_ctrl_reduce_pe_cluster_flat_reduce_data_out_f_), + .reduce_data_out_valid_f_(mem_ctrl_reduce_pe_cluster_flat_reduce_data_out_valid_f_), + .reduce_pe_cluster_inst_pe_onyxpeintf_O2(reduce_pe_cluster_inst_pe_onyxpeintf_O2), + .reduce_pe_cluster_inst_pe_onyxpeintf_O3(reduce_pe_cluster_inst_pe_onyxpeintf_O3), + .reduce_pe_cluster_inst_pe_onyxpeintf_O4(reduce_pe_cluster_inst_pe_onyxpeintf_O4), + .res_f_(mem_ctrl_reduce_pe_cluster_flat_res_f_), + .res_p_f_(mem_ctrl_reduce_pe_cluster_flat_res_p_f_), + .res_valid_f_(mem_ctrl_reduce_pe_cluster_flat_res_valid_f_) +); + +reg_fifo_depth_2_w_17_afd_2 input_width_17_num_0_input_fifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in(PE_input_width_17_num_0), + .flush(flush), + .pop(input_width_17_num_0_fifo_out_ready), + .push(PE_input_width_17_num_0_valid), + .rst_n(rst_n), + .data_out(input_width_17_num_0_fifo_out), + .empty(input_width_17_num_0_input_fifo_empty), + .full(input_width_17_num_0_input_fifo_full) +); + +reg_fifo_depth_2_w_17_afd_2 input_width_17_num_1_input_fifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in(PE_input_width_17_num_1), + .flush(flush), + .pop(input_width_17_num_1_fifo_out_ready), + .push(PE_input_width_17_num_1_valid), + .rst_n(rst_n), + .data_out(input_width_17_num_1_fifo_out), + .empty(input_width_17_num_1_input_fifo_empty), + .full(input_width_17_num_1_input_fifo_full) +); + +reg_fifo_depth_2_w_17_afd_2 input_width_17_num_2_input_fifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in(PE_input_width_17_num_2), + .flush(flush), + .pop(input_width_17_num_2_fifo_out_ready), + .push(PE_input_width_17_num_2_valid), + .rst_n(rst_n), + .data_out(input_width_17_num_2_fifo_out), + .empty(input_width_17_num_2_input_fifo_empty), + .full(input_width_17_num_2_input_fifo_full) +); + +reg_fifo_depth_2_w_17_afd_2 input_width_17_num_3_input_fifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in(PE_input_width_17_num_3), + .flush(flush), + .pop(input_width_17_num_3_fifo_out_ready), + .push(PE_input_width_17_num_3_valid), + .rst_n(rst_n), + .data_out(input_width_17_num_3_fifo_out), + .empty(input_width_17_num_3_input_fifo_empty), + .full(input_width_17_num_3_input_fifo_full) +); + +reg_fifo_depth_2_w_17_afd_2 output_width_17_num_0_output_fifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in(output_width_17_num_0_fifo_in), + .flush(flush), + .pop(PE_output_width_17_num_0_ready), + .push(output_width_17_num_0_fifo_in_valid), + .rst_n(rst_n), + .data_out(output_width_17_num_0_output_fifo_data_out), + .empty(output_width_17_num_0_output_fifo_empty), + .full(output_width_17_num_0_output_fifo_full) +); + +reg_fifo_depth_2_w_17_afd_2 output_width_17_num_1_output_fifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in(output_width_17_num_1_fifo_in), + .flush(flush), + .pop(PE_output_width_17_num_1_ready), + .push(output_width_17_num_1_fifo_in_valid), + .rst_n(rst_n), + .data_out(output_width_17_num_1_output_fifo_data_out), + .empty(output_width_17_num_1_output_fifo_empty), + .full(output_width_17_num_1_output_fifo_full) +); + +reg_fifo_depth_2_w_17_afd_2 output_width_17_num_2_output_fifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in(output_width_17_num_2_fifo_in), + .flush(flush), + .pop(PE_output_width_17_num_2_ready), + .push(output_width_17_num_2_fifo_in_valid), + .rst_n(rst_n), + .data_out(output_width_17_num_2_output_fifo_data_out), + .empty(output_width_17_num_2_output_fifo_empty), + .full(output_width_17_num_2_output_fifo_full) +); + +endmodule // PE_inner + +module PE_inner_W ( + input logic [31:0] CONFIG_SPACE_0, + input logic [31:0] CONFIG_SPACE_1, + input logic [31:0] CONFIG_SPACE_2, + input logic [27:0] CONFIG_SPACE_3, + input logic [0:0] [16:0] PE_input_width_17_num_0, + input logic PE_input_width_17_num_0_dense, + input logic PE_input_width_17_num_0_valid, + input logic [0:0] [16:0] PE_input_width_17_num_1, + input logic PE_input_width_17_num_1_dense, + input logic PE_input_width_17_num_1_valid, + input logic [0:0] [16:0] PE_input_width_17_num_2, + input logic PE_input_width_17_num_2_dense, + input logic PE_input_width_17_num_2_valid, + input logic [0:0] [16:0] PE_input_width_17_num_3, + input logic PE_input_width_17_num_3_valid, + input logic PE_input_width_1_num_0, + input logic PE_input_width_1_num_1, + input logic PE_input_width_1_num_2, + input logic PE_output_width_17_num_0_ready, + input logic PE_output_width_17_num_1_dense, + input logic PE_output_width_17_num_1_ready, + input logic PE_output_width_17_num_2_ready, + input logic clk, + input logic clk_en, + input logic flush, + input logic [2:0] mode, + input logic rst_n, + input logic tile_en, + output logic PE_input_width_17_num_0_ready, + output logic PE_input_width_17_num_1_ready, + output logic PE_input_width_17_num_2_ready, + output logic PE_input_width_17_num_3_ready, + output logic [0:0] [16:0] PE_output_width_17_num_0, + output logic PE_output_width_17_num_0_valid, + output logic [0:0] [16:0] PE_output_width_17_num_1, + output logic PE_output_width_17_num_1_valid, + output logic [0:0] [16:0] PE_output_width_17_num_2, + output logic PE_output_width_17_num_2_valid, + output logic PE_output_width_1_num_0, + output logic [15:0] reduce_pe_cluster_inst_pe_onyxpeintf_O2, + output logic [15:0] reduce_pe_cluster_inst_pe_onyxpeintf_O3, + output logic [15:0] reduce_pe_cluster_inst_pe_onyxpeintf_O4 +); + +PE_inner PE_inner ( + .CONFIG_SPACE_0(CONFIG_SPACE_0), + .CONFIG_SPACE_1(CONFIG_SPACE_1), + .CONFIG_SPACE_2(CONFIG_SPACE_2), + .CONFIG_SPACE_3(CONFIG_SPACE_3), + .PE_input_width_17_num_0(PE_input_width_17_num_0), + .PE_input_width_17_num_0_dense(PE_input_width_17_num_0_dense), + .PE_input_width_17_num_0_valid(PE_input_width_17_num_0_valid), + .PE_input_width_17_num_1(PE_input_width_17_num_1), + .PE_input_width_17_num_1_dense(PE_input_width_17_num_1_dense), + .PE_input_width_17_num_1_valid(PE_input_width_17_num_1_valid), + .PE_input_width_17_num_2(PE_input_width_17_num_2), + .PE_input_width_17_num_2_dense(PE_input_width_17_num_2_dense), + .PE_input_width_17_num_2_valid(PE_input_width_17_num_2_valid), + .PE_input_width_17_num_3(PE_input_width_17_num_3), + .PE_input_width_17_num_3_valid(PE_input_width_17_num_3_valid), + .PE_input_width_1_num_0(PE_input_width_1_num_0), + .PE_input_width_1_num_1(PE_input_width_1_num_1), + .PE_input_width_1_num_2(PE_input_width_1_num_2), + .PE_output_width_17_num_0_ready(PE_output_width_17_num_0_ready), + .PE_output_width_17_num_1_dense(PE_output_width_17_num_1_dense), + .PE_output_width_17_num_1_ready(PE_output_width_17_num_1_ready), + .PE_output_width_17_num_2_ready(PE_output_width_17_num_2_ready), + .clk(clk), + .clk_en(clk_en), + .flush(flush), + .mode(mode), + .rst_n(rst_n), + .tile_en(tile_en), + .PE_input_width_17_num_0_ready(PE_input_width_17_num_0_ready), + .PE_input_width_17_num_1_ready(PE_input_width_17_num_1_ready), + .PE_input_width_17_num_2_ready(PE_input_width_17_num_2_ready), + .PE_input_width_17_num_3_ready(PE_input_width_17_num_3_ready), + .PE_output_width_17_num_0(PE_output_width_17_num_0), + .PE_output_width_17_num_0_valid(PE_output_width_17_num_0_valid), + .PE_output_width_17_num_1(PE_output_width_17_num_1), + .PE_output_width_17_num_1_valid(PE_output_width_17_num_1_valid), + .PE_output_width_17_num_2(PE_output_width_17_num_2), + .PE_output_width_17_num_2_valid(PE_output_width_17_num_2_valid), + .PE_output_width_1_num_0(PE_output_width_1_num_0), + .reduce_pe_cluster_inst_pe_onyxpeintf_O2(reduce_pe_cluster_inst_pe_onyxpeintf_O2), + .reduce_pe_cluster_inst_pe_onyxpeintf_O3(reduce_pe_cluster_inst_pe_onyxpeintf_O3), + .reduce_pe_cluster_inst_pe_onyxpeintf_O4(reduce_pe_cluster_inst_pe_onyxpeintf_O4) +); + +endmodule // PE_inner_W + +module PE_onyx ( + input logic bit0, + input logic bit1, + input logic bit2, + input logic clk, + input logic clk_en, + input logic [16:0] data0, + input logic data0_valid, + input logic [16:0] data1, + input logic data1_valid, + input logic [16:0] data2, + input logic data2_valid, + input logic dense_mode, + input logic flush, + input logic [83:0] onyxpeintf_inst, + input logic res_ready, + input logic rst_n, + input logic [2:0] sparse_num_inputs, + input logic tile_en, + output logic data0_ready, + output logic data1_ready, + output logic data2_ready, + output logic [15:0] onyxpeintf_O2, + output logic [15:0] onyxpeintf_O3, + output logic [15:0] onyxpeintf_O4, + output logic [16:0] res, + output logic res_p, + output logic res_valid +); + +logic [15:0] data_to_fifo; +logic gclk; +logic [2:0][16:0] infifo_in_packed; +logic [2:0][15:0] infifo_out_data; +logic [2:0] infifo_out_eos; +logic infifo_out_maybe_0; +logic infifo_out_maybe_1; +logic infifo_out_maybe_2; +logic [2:0][16:0] infifo_out_packed; +logic [2:0] infifo_out_valid; +logic [2:0] infifo_pop; +logic infifo_push_0; +logic infifo_push_1; +logic infifo_push_2; +logic [0:0][16:0] input_fifo_0_data_out; +logic input_fifo_0_empty; +logic input_fifo_0_full; +logic [0:0][16:0] input_fifo_1_data_out; +logic input_fifo_1_empty; +logic input_fifo_1_full; +logic [0:0][16:0] input_fifo_2_data_out; +logic input_fifo_2_empty; +logic input_fifo_2_full; +logic onyxpeintf_ASYNCRESET; +logic [15:0] onyxpeintf_data0; +logic [15:0] onyxpeintf_data1; +logic [15:0] onyxpeintf_data2; +logic outfifo_full; +logic outfifo_in_eos; +logic [16:0] outfifo_in_packed; +logic [16:0] outfifo_out_packed; +logic outfifo_pop; +logic outfifo_push; +logic output_fifo_empty; +logic [15:0] pe_output; +assign gclk = clk & tile_en; +assign data0_ready = dense_mode ? 1'h1: ~input_fifo_0_full; +assign data1_ready = dense_mode ? 1'h1: ~input_fifo_1_full; +assign data2_ready = dense_mode ? 1'h1: ~input_fifo_2_full; +assign infifo_in_packed[0] = data0; +assign infifo_out_eos[0] = infifo_out_packed[0][16]; +assign infifo_out_data[0] = infifo_out_packed[0][15:0]; +assign infifo_in_packed[1] = data1; +assign infifo_out_eos[1] = infifo_out_packed[1][16]; +assign infifo_out_data[1] = infifo_out_packed[1][15:0]; +assign infifo_in_packed[2] = data2; +assign infifo_out_eos[2] = infifo_out_packed[2][16]; +assign infifo_out_data[2] = infifo_out_packed[2][15:0]; +assign infifo_push_0 = data0_valid; +assign infifo_push_1 = data1_valid; +assign infifo_push_2 = data2_valid; +assign infifo_out_packed[0] = input_fifo_0_data_out; +assign infifo_out_packed[1] = input_fifo_1_data_out; +assign infifo_out_packed[2] = input_fifo_2_data_out; +assign infifo_out_valid[0] = ~input_fifo_0_empty; +assign infifo_out_valid[1] = ~input_fifo_1_empty; +assign infifo_out_valid[2] = ~input_fifo_2_empty; +assign outfifo_in_packed[16] = outfifo_in_eos; +assign outfifo_in_packed[15:0] = data_to_fifo; +assign res = dense_mode ? 17'(pe_output): outfifo_out_packed; +assign res_valid = dense_mode ? 1'h1: ~output_fifo_empty; +assign outfifo_pop = res_ready; +assign infifo_out_maybe_0 = infifo_out_eos[0] & infifo_out_valid[0] & (infifo_out_data[0][9:8] == 2'h2); +assign infifo_out_maybe_1 = infifo_out_eos[1] & infifo_out_valid[1] & (infifo_out_data[1][9:8] == 2'h2); +assign infifo_out_maybe_2 = infifo_out_eos[2] & infifo_out_valid[2] & (infifo_out_data[2][9:8] == 2'h2); +assign onyxpeintf_ASYNCRESET = ~rst_n; +assign onyxpeintf_data0 = dense_mode ? data0[15:0]: infifo_out_maybe_0 ? 16'h0: infifo_out_data[0]; +assign onyxpeintf_data1 = dense_mode ? data1[15:0]: infifo_out_maybe_1 ? 16'h0: infifo_out_data[1]; +assign onyxpeintf_data2 = dense_mode ? data2[15:0]: infifo_out_maybe_2 ? 16'h0: infifo_out_data[2]; +always_comb begin + outfifo_push = 1'h0; + outfifo_in_eos = 1'h0; + data_to_fifo = 16'h0; + infifo_pop[0] = 1'h0; + infifo_pop[1] = 1'h0; + infifo_pop[2] = 1'h0; + if (((infifo_out_valid & sparse_num_inputs) == sparse_num_inputs) & (~outfifo_full) & (~dense_mode)) begin + if (~((infifo_out_eos & sparse_num_inputs) == sparse_num_inputs)) begin + outfifo_push = 1'h1; + outfifo_in_eos = 1'h0; + data_to_fifo = pe_output; + infifo_pop[0] = infifo_out_valid[0] & sparse_num_inputs[0]; + infifo_pop[1] = infifo_out_valid[1] & sparse_num_inputs[1]; + infifo_pop[2] = infifo_out_valid[2] & sparse_num_inputs[2]; + end + else begin + outfifo_push = 1'h1; + outfifo_in_eos = 1'h1; + data_to_fifo = sparse_num_inputs[0] ? infifo_out_data[0]: sparse_num_inputs[1] ? + infifo_out_data[1]: infifo_out_data[2]; + infifo_pop[0] = infifo_out_valid[0] & sparse_num_inputs[0]; + infifo_pop[1] = infifo_out_valid[1] & sparse_num_inputs[1]; + infifo_pop[2] = infifo_out_valid[2] & sparse_num_inputs[2]; + end + end +end +reg_fifo_depth_0_w_17_afd_2 input_fifo_0 ( + .clk(gclk), + .clk_en(clk_en), + .data_in(infifo_in_packed[0]), + .flush(flush), + .pop(infifo_pop[0]), + .push(infifo_push_0), + .rst_n(rst_n), + .data_out(input_fifo_0_data_out), + .empty(input_fifo_0_empty), + .full(input_fifo_0_full) +); + +reg_fifo_depth_0_w_17_afd_2 input_fifo_1 ( + .clk(gclk), + .clk_en(clk_en), + .data_in(infifo_in_packed[1]), + .flush(flush), + .pop(infifo_pop[1]), + .push(infifo_push_1), + .rst_n(rst_n), + .data_out(input_fifo_1_data_out), + .empty(input_fifo_1_empty), + .full(input_fifo_1_full) +); + +reg_fifo_depth_0_w_17_afd_2 input_fifo_2 ( + .clk(gclk), + .clk_en(clk_en), + .data_in(infifo_in_packed[2]), + .flush(flush), + .pop(infifo_pop[2]), + .push(infifo_push_2), + .rst_n(rst_n), + .data_out(input_fifo_2_data_out), + .empty(input_fifo_2_empty), + .full(input_fifo_2_full) +); + +reg_fifo_depth_2_w_17_afd_2 output_fifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in(outfifo_in_packed), + .flush(flush), + .pop(outfifo_pop), + .push(outfifo_push), + .rst_n(rst_n), + .data_out(outfifo_out_packed), + .empty(output_fifo_empty), + .full(outfifo_full) +); + +PEGEN_PE onyxpeintf ( + .ASYNCRESET(onyxpeintf_ASYNCRESET), + .CLK(gclk), + .bit0(bit0), + .bit1(bit1), + .bit2(bit2), + .clk_en(clk_en), + .data0(onyxpeintf_data0), + .data1(onyxpeintf_data1), + .data2(onyxpeintf_data2), + .inst(onyxpeintf_inst), + .O0(pe_output), + .O1(res_p), + .O2(onyxpeintf_O2), + .O3(onyxpeintf_O3), + .O4(onyxpeintf_O4) +); + +endmodule // PE_onyx + +module Repeat ( + input logic clk, + input logic clk_en, + input logic flush, + input logic [16:0] proc_data_in, + input logic proc_data_in_valid, + input logic ref_data_out_ready, + input logic [16:0] repsig_data_in, + input logic repsig_data_in_valid, + input logic root, + input logic rst_n, + input logic spacc_mode, + input logic [15:0] stop_lvl, + input logic tile_en, + output logic proc_data_in_ready, + output logic [16:0] ref_data_out, + output logic ref_data_out_valid, + output logic repsig_data_in_ready +); + +typedef enum logic[1:0] { + INJECT0 = 2'h0, + INJECT1 = 2'h1, + PASS_REPEAT = 2'h2, + START = 2'h3 +} repeat_fsm_state; +logic blank_repeat; +logic blank_repeat_stop; +logic clr_last_pushed_data; +logic gclk; +logic proc_data; +logic proc_done; +logic proc_fifo_full; +logic [15:0] proc_fifo_inject_data; +logic proc_fifo_inject_eos; +logic proc_fifo_inject_push; +logic [15:0] proc_fifo_out_data; +logic proc_fifo_out_eos; +logic proc_fifo_pop; +logic proc_fifo_push; +logic proc_fifo_valid; +logic [0:0][16:0] proc_in_fifo_data_in; +logic [0:0][16:0] proc_in_fifo_data_out; +logic proc_in_fifo_empty; +logic proc_in_fifo_full; +logic proc_stop; +logic pushed_data_sticky_sticky; +logic pushed_data_sticky_was_high; +logic ref_fifo_full; +logic [15:0] ref_fifo_in_data; +logic ref_fifo_in_eos; +logic ref_fifo_push; +logic ref_maybe; +logic [0:0][16:0] ref_out_fifo_data_in; +logic ref_out_fifo_empty; +repeat_fsm_state repeat_fsm_current_state; +repeat_fsm_state repeat_fsm_next_state; +logic repsig_done; +logic [15:0] repsig_fifo_out_data; +logic repsig_fifo_out_eos; +logic repsig_fifo_pop; +logic repsig_fifo_valid; +logic [0:0][16:0] repsig_in_fifo_data_out; +logic repsig_in_fifo_empty; +logic repsig_in_fifo_full; +logic repsig_sig; +logic repsig_stop; +logic seen_root_eos_sticky; +logic seen_root_eos_was_high; +logic set_last_pushed_data; +assign gclk = clk & tile_en; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + pushed_data_sticky_was_high <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + pushed_data_sticky_was_high <= 1'h0; + end + else if (clr_last_pushed_data) begin + pushed_data_sticky_was_high <= 1'h0; + end + else if (set_last_pushed_data) begin + pushed_data_sticky_was_high <= 1'h1; + end + end +end +assign pushed_data_sticky_sticky = pushed_data_sticky_was_high; +assign {repsig_fifo_out_eos, repsig_fifo_out_data} = repsig_in_fifo_data_out; +assign repsig_data_in_ready = ~repsig_in_fifo_full; +assign repsig_fifo_valid = ~repsig_in_fifo_empty; +assign proc_fifo_push = root ? proc_fifo_inject_push: proc_data_in_valid; +assign proc_in_fifo_data_in = root ? {proc_fifo_inject_eos, proc_fifo_inject_data}: proc_data_in; +assign {proc_fifo_out_eos, proc_fifo_out_data} = proc_in_fifo_data_out; +assign proc_data_in_ready = ~proc_in_fifo_full; +assign proc_fifo_full = proc_in_fifo_full; +assign proc_fifo_valid = ~proc_in_fifo_empty; +assign ref_out_fifo_data_in = {ref_fifo_in_eos, ref_fifo_in_data}; +assign ref_data_out_valid = ~ref_out_fifo_empty; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + seen_root_eos_was_high <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + seen_root_eos_was_high <= 1'h0; + end + else if (1'h0) begin + seen_root_eos_was_high <= 1'h0; + end + else if ((proc_fifo_out_data == 16'h0) & proc_fifo_out_eos & proc_fifo_valid) begin + seen_root_eos_was_high <= 1'h1; + end + end +end +assign seen_root_eos_sticky = ((proc_fifo_out_data == 16'h0) & proc_fifo_out_eos & proc_fifo_valid) | + seen_root_eos_was_high; +assign ref_maybe = proc_fifo_valid & proc_fifo_out_eos & (proc_fifo_out_data[9:8] == 2'h2); +assign proc_data = ((~proc_fifo_out_eos) | ref_maybe) & proc_fifo_valid; +assign proc_stop = (proc_fifo_out_data[9:8] == 2'h0) & proc_fifo_out_eos & proc_fifo_valid; +assign proc_done = (proc_fifo_out_data[9:8] == 2'h1) & proc_fifo_out_eos & proc_fifo_valid; +assign repsig_stop = (repsig_fifo_out_data[9:8] == 2'h0) & repsig_fifo_out_eos & repsig_fifo_valid; +assign repsig_sig = (~repsig_fifo_out_eos) & repsig_fifo_valid; +assign repsig_done = (repsig_fifo_out_data[9:8] == 2'h1) & repsig_fifo_out_eos & repsig_fifo_valid; +assign blank_repeat = proc_stop & (~repsig_stop) & repsig_fifo_valid; +assign blank_repeat_stop = proc_stop & repsig_stop & pushed_data_sticky_sticky; + +always_ff @(posedge clk, negedge rst_n) begin + if (!rst_n) begin + repeat_fsm_current_state <= START; + end + else if (clk_en) begin + if (flush) begin + repeat_fsm_current_state <= START; + end + else repeat_fsm_current_state <= repeat_fsm_next_state; + end +end +always_comb begin + repeat_fsm_next_state = repeat_fsm_current_state; + unique case (repeat_fsm_current_state) + INJECT0: begin + if (~proc_fifo_full) begin + repeat_fsm_next_state = INJECT1; + end + else repeat_fsm_next_state = INJECT0; + end + INJECT1: begin + if (~proc_fifo_full) begin + repeat_fsm_next_state = PASS_REPEAT; + end + else repeat_fsm_next_state = INJECT1; + end + PASS_REPEAT: begin + if (proc_done & repsig_done & (~ref_fifo_full)) begin + repeat_fsm_next_state = START; + end + else repeat_fsm_next_state = PASS_REPEAT; + end + START: begin + if (root & tile_en) begin + repeat_fsm_next_state = INJECT0; + end + else if ((~root) & tile_en) begin + repeat_fsm_next_state = PASS_REPEAT; + end + else repeat_fsm_next_state = START; + end + default: begin end + endcase +end +always_comb begin + unique case (repeat_fsm_current_state) + INJECT0: begin :repeat_fsm_INJECT0_Output + ref_fifo_in_data = 16'h0; + ref_fifo_in_eos = 1'h0; + ref_fifo_push = 1'h0; + proc_fifo_pop = 1'h0; + repsig_fifo_pop = 1'h0; + proc_fifo_inject_push = 1'h1; + proc_fifo_inject_data = 16'h0; + proc_fifo_inject_eos = 1'h0; + set_last_pushed_data = 1'h0; + clr_last_pushed_data = 1'h0; + end :repeat_fsm_INJECT0_Output + INJECT1: begin :repeat_fsm_INJECT1_Output + ref_fifo_in_data = 16'h0; + ref_fifo_in_eos = 1'h0; + ref_fifo_push = 1'h0; + proc_fifo_pop = 1'h0; + repsig_fifo_pop = 1'h0; + proc_fifo_inject_push = 1'h1; + proc_fifo_inject_data = 16'h100; + proc_fifo_inject_eos = 1'h1; + set_last_pushed_data = 1'h0; + clr_last_pushed_data = 1'h0; + end :repeat_fsm_INJECT1_Output + PASS_REPEAT: begin :repeat_fsm_PASS_REPEAT_Output + ref_fifo_in_data = repsig_stop ? repsig_fifo_out_data: proc_fifo_out_data; + ref_fifo_in_eos = ref_maybe | repsig_done | repsig_stop; + ref_fifo_push = (~ref_fifo_full) & ((proc_done & repsig_done) | (proc_data & repsig_fifo_valid) + | (proc_stop & (~pushed_data_sticky_sticky) & repsig_stop)); + proc_fifo_pop = proc_done ? repsig_done & (~ref_fifo_full): proc_stop ? + pushed_data_sticky_sticky | (repsig_stop & (~ref_fifo_full) & + (~pushed_data_sticky_sticky)): repsig_stop & (~ref_fifo_full); + repsig_fifo_pop = repsig_done ? proc_done & (~ref_fifo_full): repsig_stop ? (proc_data | + (proc_stop & (~pushed_data_sticky_sticky))) & (~ref_fifo_full): (proc_data & + (~ref_fifo_full)) | (proc_stop & (~pushed_data_sticky_sticky)); + proc_fifo_inject_push = 1'h0; + proc_fifo_inject_data = 16'h0; + proc_fifo_inject_eos = 1'h0; + set_last_pushed_data = proc_data; + clr_last_pushed_data = proc_stop | (proc_done & repsig_done & (~ref_fifo_full)); + end :repeat_fsm_PASS_REPEAT_Output + START: begin :repeat_fsm_START_Output + ref_fifo_in_data = 16'h0; + ref_fifo_in_eos = 1'h0; + ref_fifo_push = 1'h0; + proc_fifo_pop = 1'h0; + repsig_fifo_pop = 1'h0; + proc_fifo_inject_push = 1'h0; + proc_fifo_inject_data = 16'h0; + proc_fifo_inject_eos = 1'h0; + set_last_pushed_data = 1'h0; + clr_last_pushed_data = 1'h0; + end :repeat_fsm_START_Output + default: begin end + endcase +end +reg_fifo_depth_0_w_17_afd_2 repsig_in_fifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in(repsig_data_in), + .flush(flush), + .pop(repsig_fifo_pop), + .push(repsig_data_in_valid), + .rst_n(rst_n), + .data_out(repsig_in_fifo_data_out), + .empty(repsig_in_fifo_empty), + .full(repsig_in_fifo_full) +); + +reg_fifo_depth_2_w_17_afd_2 proc_in_fifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in(proc_in_fifo_data_in), + .flush(flush), + .pop(proc_fifo_pop), + .push(proc_fifo_push), + .rst_n(rst_n), + .data_out(proc_in_fifo_data_out), + .empty(proc_in_fifo_empty), + .full(proc_in_fifo_full) +); + +reg_fifo_depth_0_w_17_afd_2 ref_out_fifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in(ref_out_fifo_data_in), + .flush(flush), + .pop(ref_data_out_ready), + .push(ref_fifo_push), + .rst_n(rst_n), + .data_out(ref_data_out), + .empty(ref_out_fifo_empty), + .full(ref_fifo_full) +); + +endmodule // Repeat + +module RepeatSignalGenerator ( + input logic [16:0] base_data_in, + input logic base_data_in_valid, + input logic clk, + input logic clk_en, + input logic flush, + input logic repsig_data_out_ready, + input logic rst_n, + input logic [15:0] stop_lvl, + input logic tile_en, + output logic base_data_in_ready, + output logic [16:0] repsig_data_out, + output logic repsig_data_out_valid +); + +typedef enum logic[1:0] { + DONE = 2'h0, + PASS_REPEAT = 2'h1, + PASS_STOP = 2'h2, + START = 2'h3 +} rsg_fsm_state; +logic already_pushed_repsig_eos_sticky; +logic already_pushed_repsig_eos_was_high; +logic [15:0] base_fifo_out_data; +logic base_fifo_out_eos; +logic base_fifo_pop; +logic base_fifo_valid; +logic [0:0][16:0] base_in_fifo_data_out; +logic base_in_fifo_empty; +logic base_in_fifo_full; +logic clr_already_pushed_repsig_eos; +logic gclk; +logic repsig_fifo_full; +logic [15:0] repsig_fifo_in_data; +logic repsig_fifo_in_eos; +logic repsig_fifo_push; +logic [0:0][16:0] repsig_out_fifo_data_in; +logic repsig_out_fifo_empty; +rsg_fsm_state rsg_fsm_current_state; +rsg_fsm_state rsg_fsm_next_state; +logic seen_root_eos_sticky; +logic seen_root_eos_was_high; +assign gclk = clk & tile_en; +assign {base_fifo_out_eos, base_fifo_out_data} = base_in_fifo_data_out; +assign base_data_in_ready = ~base_in_fifo_full; +assign base_fifo_valid = ~base_in_fifo_empty; +assign repsig_out_fifo_data_in = {repsig_fifo_in_eos, repsig_fifo_in_data}; +assign repsig_data_out_valid = ~repsig_out_fifo_empty; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + seen_root_eos_was_high <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + seen_root_eos_was_high <= 1'h0; + end + else if (1'h0) begin + seen_root_eos_was_high <= 1'h0; + end + else if ((base_fifo_out_data[9:8] == 2'h1) & base_fifo_out_eos & base_fifo_valid) begin + seen_root_eos_was_high <= 1'h1; + end + end +end +assign seen_root_eos_sticky = ((base_fifo_out_data[9:8] == 2'h1) & base_fifo_out_eos & base_fifo_valid) | + seen_root_eos_was_high; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + already_pushed_repsig_eos_was_high <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + already_pushed_repsig_eos_was_high <= 1'h0; + end + else if (clr_already_pushed_repsig_eos) begin + already_pushed_repsig_eos_was_high <= 1'h0; + end + else if (repsig_fifo_push & (~repsig_fifo_full)) begin + already_pushed_repsig_eos_was_high <= 1'h1; + end + end +end +assign already_pushed_repsig_eos_sticky = already_pushed_repsig_eos_was_high; + +always_ff @(posedge clk, negedge rst_n) begin + if (!rst_n) begin + rsg_fsm_current_state <= START; + end + else if (clk_en) begin + if (flush) begin + rsg_fsm_current_state <= START; + end + else rsg_fsm_current_state <= rsg_fsm_next_state; + end +end +always_comb begin + rsg_fsm_next_state = rsg_fsm_current_state; + unique case (rsg_fsm_current_state) + DONE: rsg_fsm_next_state = START; + PASS_REPEAT: begin + if (base_fifo_out_eos & base_fifo_valid) begin + rsg_fsm_next_state = PASS_STOP; + end + else rsg_fsm_next_state = PASS_REPEAT; + end + PASS_STOP: begin + if (base_fifo_valid & base_fifo_out_eos & (base_fifo_out_data[9:8] == 2'h1) & (~repsig_fifo_full)) begin + rsg_fsm_next_state = DONE; + end + else if (base_fifo_valid & (~base_fifo_out_eos)) begin + rsg_fsm_next_state = PASS_REPEAT; + end + else rsg_fsm_next_state = PASS_STOP; + end + START: begin + if (tile_en) begin + rsg_fsm_next_state = PASS_REPEAT; + end + else rsg_fsm_next_state = START; + end + default: begin end + endcase +end +always_comb begin + unique case (rsg_fsm_current_state) + DONE: begin :rsg_fsm_DONE_Output + repsig_fifo_in_data = 16'h0; + repsig_fifo_in_eos = 1'h0; + repsig_fifo_push = 1'h0; + base_fifo_pop = 1'h0; + clr_already_pushed_repsig_eos = 1'h0; + end :rsg_fsm_DONE_Output + PASS_REPEAT: begin :rsg_fsm_PASS_REPEAT_Output + repsig_fifo_in_data = 16'h1; + repsig_fifo_in_eos = 1'h0; + repsig_fifo_push = (~base_fifo_out_eos) & base_fifo_valid; + clr_already_pushed_repsig_eos = 1'h1; + base_fifo_pop = (~base_fifo_out_eos) & base_fifo_valid & (~repsig_fifo_full); + end :rsg_fsm_PASS_REPEAT_Output + PASS_STOP: begin :rsg_fsm_PASS_STOP_Output + repsig_fifo_in_data = (base_fifo_out_data[9:8] == 2'h1) ? base_fifo_out_data: base_fifo_out_data; + repsig_fifo_in_eos = 1'h1; + repsig_fifo_push = base_fifo_out_eos & base_fifo_valid; + clr_already_pushed_repsig_eos = 1'h0; + base_fifo_pop = base_fifo_out_eos & base_fifo_valid & (~repsig_fifo_full); + end :rsg_fsm_PASS_STOP_Output + START: begin :rsg_fsm_START_Output + repsig_fifo_in_data = 16'h0; + repsig_fifo_in_eos = 1'h0; + repsig_fifo_push = 1'h0; + base_fifo_pop = 1'h0; + clr_already_pushed_repsig_eos = 1'h0; + end :rsg_fsm_START_Output + default: begin end + endcase +end +reg_fifo_depth_0_w_17_afd_2 base_in_fifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in(base_data_in), + .flush(flush), + .pop(base_fifo_pop), + .push(base_data_in_valid), + .rst_n(rst_n), + .data_out(base_in_fifo_data_out), + .empty(base_in_fifo_empty), + .full(base_in_fifo_full) +); + +reg_fifo_depth_0_w_17_afd_2 repsig_out_fifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in(repsig_out_fifo_data_in), + .flush(flush), + .pop(repsig_data_out_ready), + .push(repsig_fifo_push), + .rst_n(rst_n), + .data_out(repsig_data_out), + .empty(repsig_out_fifo_empty), + .full(repsig_fifo_full) +); + +endmodule // RepeatSignalGenerator + +module RepeatSignalGenerator_flat ( + input logic [15:0] RepeatSignalGenerator_inst_stop_lvl, + input logic RepeatSignalGenerator_inst_tile_en, + input logic [0:0] [16:0] base_data_in_f_, + input logic base_data_in_valid_f_, + input logic clk, + input logic clk_en, + input logic flush, + input logic repsig_data_out_ready_f_, + input logic rst_n, + output logic base_data_in_ready_f_, + output logic [0:0] [16:0] repsig_data_out_f_, + output logic repsig_data_out_valid_f_ +); + +RepeatSignalGenerator RepeatSignalGenerator_inst ( + .base_data_in(base_data_in_f_), + .base_data_in_valid(base_data_in_valid_f_), + .clk(clk), + .clk_en(clk_en), + .flush(flush), + .repsig_data_out_ready(repsig_data_out_ready_f_), + .rst_n(rst_n), + .stop_lvl(RepeatSignalGenerator_inst_stop_lvl), + .tile_en(RepeatSignalGenerator_inst_tile_en), + .base_data_in_ready(base_data_in_ready_f_), + .repsig_data_out(repsig_data_out_f_), + .repsig_data_out_valid(repsig_data_out_valid_f_) +); + +endmodule // RepeatSignalGenerator_flat + +module Repeat_flat ( + input logic Repeat_inst_root, + input logic Repeat_inst_spacc_mode, + input logic [15:0] Repeat_inst_stop_lvl, + input logic Repeat_inst_tile_en, + input logic clk, + input logic clk_en, + input logic flush, + input logic [0:0] [16:0] proc_data_in_f_, + input logic proc_data_in_valid_f_, + input logic ref_data_out_ready_f_, + input logic [0:0] [16:0] repsig_data_in_f_, + input logic repsig_data_in_valid_f_, + input logic rst_n, + output logic proc_data_in_ready_f_, + output logic [0:0] [16:0] ref_data_out_f_, + output logic ref_data_out_valid_f_, + output logic repsig_data_in_ready_f_ +); + +Repeat Repeat_inst ( + .clk(clk), + .clk_en(clk_en), + .flush(flush), + .proc_data_in(proc_data_in_f_), + .proc_data_in_valid(proc_data_in_valid_f_), + .ref_data_out_ready(ref_data_out_ready_f_), + .repsig_data_in(repsig_data_in_f_), + .repsig_data_in_valid(repsig_data_in_valid_f_), + .root(Repeat_inst_root), + .rst_n(rst_n), + .spacc_mode(Repeat_inst_spacc_mode), + .stop_lvl(Repeat_inst_stop_lvl), + .tile_en(Repeat_inst_tile_en), + .proc_data_in_ready(proc_data_in_ready_f_), + .ref_data_out(ref_data_out_f_), + .ref_data_out_valid(ref_data_out_valid_f_), + .repsig_data_in_ready(repsig_data_in_ready_f_) +); + +endmodule // Repeat_flat + +module crddrop ( + input logic clk, + input logic clk_en, + input logic [16:0] cmrg_coord_in_0, + input logic cmrg_coord_in_0_valid, + input logic [16:0] cmrg_coord_in_1, + input logic cmrg_coord_in_1_valid, + input logic cmrg_coord_out_0_ready, + input logic cmrg_coord_out_1_ready, + input logic cmrg_enable, + input logic cmrg_mode, + input logic [15:0] cmrg_stop_lvl, + input logic flush, + input logic rst_n, + input logic tile_en, + output logic cmrg_coord_in_0_ready, + output logic cmrg_coord_in_1_ready, + output logic [16:0] cmrg_coord_out_0, + output logic cmrg_coord_out_0_valid, + output logic [16:0] cmrg_coord_out_1, + output logic cmrg_coord_out_1_valid +); + +typedef enum logic[1:0] { + DROPZERO = 2'h0, + PROCESS = 2'h1, + START = 2'h2 +} proc_seq_state; +logic base_data_seen; +logic [16:0] base_delay; +logic base_done; +logic base_done_seen; +logic base_eos_seen; +logic base_infifo_empty; +logic base_infifo_full; +logic [15:0] base_infifo_in_data; +logic base_infifo_in_eos; +logic [16:0] base_infifo_in_packed; +logic base_infifo_in_valid; +logic [16:0] base_infifo_out_packed; +logic base_infifo_true_pop; +logic base_outfifo_empty; +logic base_outfifo_full; +logic [16:0] base_outfifo_in_packed; +logic base_outfifo_in_ready; +logic [16:0] base_outfifo_out_packed; +logic base_valid_delay; +logic both_done; +logic clr_pushed_data_lower; +logic clr_pushed_proc; +logic clr_pushed_stop_lvl; +logic cmrg_base_fifo_pop; +logic cmrg_base_fifo_push; +logic cmrg_coord_in_0_eos; +logic cmrg_coord_in_1_eos; +logic [1:0] cmrg_fifo_pop; +logic [1:0] cmrg_fifo_push; +logic cmrg_proc_fifo_pop; +logic cmrg_proc_fifo_push; +logic delay_data; +logic delay_done; +logic delay_eos; +logic delay_stop; +logic gclk; +logic proc_data_seen; +logic proc_done; +logic proc_infifo_empty; +logic proc_infifo_full; +logic [15:0] proc_infifo_in_data; +logic proc_infifo_in_eos; +logic [16:0] proc_infifo_in_packed; +logic proc_infifo_in_valid; +logic [16:0] proc_infifo_out_packed; +logic proc_outfifo_empty; +logic proc_outfifo_full; +logic [16:0] proc_outfifo_in_packed; +logic proc_outfifo_in_ready; +logic [16:0] proc_outfifo_out_packed; +proc_seq_state proc_seq_current_state; +proc_seq_state proc_seq_next_state; +logic pushed_data_sticky_sticky; +logic pushed_data_sticky_was_high; +logic pushed_proc_sticky; +logic pushed_proc_was_high; +logic pushed_stop_lvl_sticky; +logic pushed_stop_lvl_was_high; +logic pushing_done; +logic set_pushed_data_lower; +assign gclk = clk & tile_en; +assign cmrg_coord_in_0_eos = cmrg_coord_in_0[16]; +assign cmrg_coord_in_1_eos = cmrg_coord_in_1[16]; +assign delay_eos = base_valid_delay & base_delay[16]; +assign delay_data = base_valid_delay & (~delay_eos); +assign delay_done = delay_eos & (base_delay[9:8] == 2'h1); +assign delay_stop = delay_eos & (base_delay[9:8] == 2'h0); +assign base_infifo_in_packed[16] = cmrg_coord_in_0_eos; +assign base_infifo_in_packed[15:0] = cmrg_coord_in_0[15:0]; +assign base_infifo_in_eos = base_infifo_out_packed[16]; +assign base_infifo_in_data = base_infifo_out_packed[15:0]; +assign base_infifo_in_valid = ~base_infifo_empty; +assign cmrg_coord_in_0_ready = ~base_infifo_full; +assign proc_infifo_in_packed[16] = cmrg_coord_in_1_eos; +assign proc_infifo_in_packed[15:0] = cmrg_coord_in_1[15:0]; +assign proc_infifo_in_eos = proc_infifo_out_packed[16]; +assign proc_infifo_in_data = proc_infifo_out_packed[15:0]; +assign proc_infifo_in_valid = ~proc_infifo_empty; +assign cmrg_coord_in_1_ready = ~proc_infifo_full; +assign base_data_seen = base_infifo_in_valid & (~base_infifo_in_eos); +assign proc_data_seen = proc_infifo_in_valid & (~proc_infifo_in_eos); + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + pushed_data_sticky_was_high <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + pushed_data_sticky_was_high <= 1'h0; + end + else if (clr_pushed_data_lower) begin + pushed_data_sticky_was_high <= 1'h0; + end + else if (set_pushed_data_lower) begin + pushed_data_sticky_was_high <= 1'h1; + end + end +end +assign pushed_data_sticky_sticky = pushed_data_sticky_was_high; +assign base_eos_seen = base_infifo_in_valid & base_infifo_in_eos & (base_infifo_in_data[9:8] == 2'h0); +assign base_done_seen = base_infifo_in_valid & base_infifo_in_eos & (base_infifo_in_data[9:8] == 2'h1); +assign base_done = base_infifo_in_valid & base_infifo_in_eos & (base_infifo_in_data[9:8] == 2'h1); +assign proc_done = proc_infifo_in_valid & proc_infifo_in_eos & (proc_infifo_in_data[9:8] == 2'h1); + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + pushed_proc_was_high <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + pushed_proc_was_high <= 1'h0; + end + else if (clr_pushed_proc) begin + pushed_proc_was_high <= 1'h0; + end + else if (cmrg_fifo_push[1]) begin + pushed_proc_was_high <= 1'h1; + end + end +end +assign pushed_proc_sticky = pushed_proc_was_high; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + pushed_stop_lvl_was_high <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + pushed_stop_lvl_was_high <= 1'h0; + end + else if (clr_pushed_stop_lvl) begin + pushed_stop_lvl_was_high <= 1'h0; + end + else if (cmrg_fifo_push[0] & base_infifo_in_valid & base_infifo_in_eos) begin + pushed_stop_lvl_was_high <= 1'h1; + end + end +end +assign pushed_stop_lvl_sticky = pushed_stop_lvl_was_high; +assign both_done = base_infifo_in_valid & base_infifo_in_eos & proc_infifo_in_valid & + proc_infifo_in_eos & (base_infifo_in_data[9:8] == 2'h1) & + (proc_infifo_in_data[9:8] == 2'h1); +assign pushing_done = base_infifo_in_valid & base_infifo_in_eos & proc_infifo_in_valid & + proc_infifo_in_eos & (base_infifo_in_data[9:8] == 2'h1) & + (proc_infifo_in_data[9:8] == 2'h1) & (~base_outfifo_full) & (~proc_outfifo_full); +assign base_infifo_true_pop = cmrg_mode ? cmrg_fifo_pop[0] & (~(delay_stop & base_done_seen)): + cmrg_fifo_pop[0]; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + base_delay <= 17'h0; + base_valid_delay <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + base_delay <= 17'h0; + base_valid_delay <= 1'h0; + end + else if (cmrg_fifo_pop[0] & (~(delay_done & base_done_seen))) begin + base_delay <= ((~base_valid_delay) | base_data_seen | base_done_seen | delay_data) ? + base_infifo_out_packed: (base_infifo_out_packed < base_delay) ? base_delay: + base_infifo_out_packed; + base_valid_delay <= base_infifo_in_valid; + end + else if (cmrg_fifo_pop[0] & delay_done & base_done_seen) begin + base_delay <= 17'h0; + base_valid_delay <= 1'h0; + end + else begin + base_delay <= base_delay; + base_valid_delay <= base_valid_delay; + end + end +end +assign base_outfifo_in_packed[16] = cmrg_mode ? base_delay[16]: base_infifo_in_eos; +assign base_outfifo_in_packed[15:0] = cmrg_mode ? base_delay[15:0]: base_infifo_in_data; +assign cmrg_coord_out_0[16] = base_outfifo_out_packed[16]; +assign cmrg_coord_out_0[15:0] = base_outfifo_out_packed[15:0]; +assign cmrg_coord_out_0_valid = ~base_outfifo_empty; +assign base_outfifo_in_ready = ~base_outfifo_full; +assign proc_outfifo_in_packed[16] = proc_infifo_in_eos; +assign proc_outfifo_in_packed[15:0] = proc_infifo_in_data; +assign cmrg_coord_out_1[16] = proc_outfifo_out_packed[16]; +assign cmrg_coord_out_1[15:0] = proc_outfifo_out_packed[15:0]; +assign cmrg_coord_out_1_valid = ~proc_outfifo_empty; +assign proc_outfifo_in_ready = ~proc_outfifo_full; +always_comb begin + if (base_infifo_in_valid & proc_infifo_in_valid) begin + if ((base_infifo_in_data == 16'h0) & (~base_eos_seen) & (~base_done)) begin + cmrg_base_fifo_pop = 1'h1; + cmrg_proc_fifo_pop = 1'h1; + cmrg_base_fifo_push = 1'h0; + cmrg_proc_fifo_push = 1'h0; + end + else if (base_outfifo_in_ready & proc_outfifo_in_ready) begin + cmrg_base_fifo_pop = 1'h1; + cmrg_proc_fifo_pop = 1'h1; + cmrg_base_fifo_push = 1'h1; + cmrg_proc_fifo_push = 1'h1; + end + else begin + cmrg_base_fifo_pop = 1'h0; + cmrg_proc_fifo_pop = 1'h0; + cmrg_base_fifo_push = 1'h0; + cmrg_proc_fifo_push = 1'h0; + end + end + else begin + cmrg_base_fifo_pop = 1'h0; + cmrg_proc_fifo_pop = 1'h0; + cmrg_base_fifo_push = 1'h0; + cmrg_proc_fifo_push = 1'h0; + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (!rst_n) begin + proc_seq_current_state <= START; + end + else if (clk_en) begin + if (flush) begin + proc_seq_current_state <= START; + end + else proc_seq_current_state <= proc_seq_next_state; + end +end +always_comb begin + proc_seq_next_state = proc_seq_current_state; + unique case (proc_seq_current_state) + DROPZERO: proc_seq_next_state = DROPZERO; + PROCESS: proc_seq_next_state = PROCESS; + START: begin + if (tile_en & cmrg_mode) begin + proc_seq_next_state = PROCESS; + end + else if (tile_en & (~cmrg_mode)) begin + proc_seq_next_state = DROPZERO; + end + else proc_seq_next_state = START; + end + default: proc_seq_next_state = proc_seq_current_state; + endcase +end +always_comb begin + unique case (proc_seq_current_state) + DROPZERO: begin :proc_seq_DROPZERO_Output + cmrg_fifo_pop[0] = cmrg_base_fifo_pop; + cmrg_fifo_pop[1] = cmrg_proc_fifo_pop; + cmrg_fifo_push[0] = cmrg_base_fifo_push; + cmrg_fifo_push[1] = cmrg_proc_fifo_push; + clr_pushed_proc = 1'h1; + clr_pushed_stop_lvl = 1'h1; + set_pushed_data_lower = 1'h0; + clr_pushed_data_lower = 1'h1; + end :proc_seq_DROPZERO_Output + PROCESS: begin :proc_seq_PROCESS_Output + cmrg_fifo_pop[0] = (~base_valid_delay) | (delay_done ? proc_done & (~base_outfifo_full) & + (~proc_outfifo_full): delay_data ? (~base_outfifo_full) & base_infifo_in_valid & + (base_data_seen | (base_eos_seen & proc_infifo_in_valid & (~proc_infifo_in_eos) + & (~proc_outfifo_full))): delay_eos ? base_infifo_in_valid & + ((proc_infifo_in_valid & (~proc_infifo_in_eos)) | proc_done) & (((base_data_seen + | base_done) & ((pushed_data_sticky_sticky & (~base_outfifo_full)) | + (~pushed_data_sticky_sticky))) | base_eos_seen): 1'h0); + cmrg_fifo_pop[1] = proc_done ? delay_done & (~base_outfifo_full) & (~proc_outfifo_full): + (proc_infifo_in_valid & (~proc_infifo_in_eos)) ? base_eos_seen & + (((~proc_outfifo_full) & delay_data & (~base_outfifo_full)) | delay_eos | + (~base_valid_delay)): (proc_infifo_in_valid & proc_infifo_in_eos) ? + ~proc_outfifo_full: 1'h0; + cmrg_fifo_push[0] = delay_done ? proc_done & (~base_outfifo_full) & (~proc_outfifo_full): delay_data + ? (~base_outfifo_full) & base_infifo_in_valid & (base_data_seen | (base_eos_seen + & proc_infifo_in_valid & (~proc_infifo_in_eos) & (~proc_outfifo_full))): + delay_eos ? base_infifo_in_valid & ((proc_infifo_in_valid & + (~proc_infifo_in_eos)) | proc_done) & (base_data_seen | base_done) & + pushed_data_sticky_sticky & (~base_outfifo_full): 1'h0; + cmrg_fifo_push[1] = proc_done ? delay_done & (~base_outfifo_full) & (~proc_outfifo_full): + (proc_infifo_in_valid & (~proc_infifo_in_eos)) ? base_eos_seen & + (~proc_outfifo_full) & delay_data & (~base_outfifo_full): (proc_infifo_in_valid + & proc_infifo_in_eos) ? ~proc_outfifo_full: 1'h0; + clr_pushed_proc = 1'h0; + clr_pushed_stop_lvl = 1'h0; + set_pushed_data_lower = delay_data & (~base_outfifo_full) & base_infifo_in_valid & (base_data_seen | + (base_eos_seen & proc_infifo_in_valid & (~proc_infifo_in_eos) & + (~proc_outfifo_full))); + clr_pushed_data_lower = delay_done | (delay_eos & base_infifo_in_valid & ((proc_infifo_in_valid & + (~proc_infifo_in_eos)) | proc_done) & (base_data_seen | base_done) & + pushed_data_sticky_sticky & (~base_outfifo_full)); + end :proc_seq_PROCESS_Output + START: begin :proc_seq_START_Output + cmrg_fifo_pop[0] = 1'h0; + cmrg_fifo_pop[1] = 1'h0; + cmrg_fifo_push[0] = 1'h0; + cmrg_fifo_push[1] = 1'h0; + clr_pushed_proc = 1'h1; + clr_pushed_stop_lvl = 1'h1; + set_pushed_data_lower = 1'h0; + clr_pushed_data_lower = 1'h1; + end :proc_seq_START_Output + default: begin :proc_seq_default_Output + cmrg_fifo_pop[0] = 1'h0; + cmrg_fifo_pop[1] = 1'h0; + cmrg_fifo_push[0] = 1'h0; + cmrg_fifo_push[1] = 1'h0; + clr_pushed_proc = 1'h1; + clr_pushed_stop_lvl = 1'h1; + set_pushed_data_lower = 1'h0; + clr_pushed_data_lower = 1'h1; + end :proc_seq_default_Output + endcase +end +reg_fifo_depth_0_w_17_afd_2 base_infifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in(base_infifo_in_packed), + .flush(flush), + .pop(base_infifo_true_pop), + .push(cmrg_coord_in_0_valid), + .rst_n(rst_n), + .data_out(base_infifo_out_packed), + .empty(base_infifo_empty), + .full(base_infifo_full) +); + +reg_fifo_depth_0_w_17_afd_2 proc_infifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in(proc_infifo_in_packed), + .flush(flush), + .pop(cmrg_fifo_pop[1]), + .push(cmrg_coord_in_1_valid), + .rst_n(rst_n), + .data_out(proc_infifo_out_packed), + .empty(proc_infifo_empty), + .full(proc_infifo_full) +); + +reg_fifo_depth_0_w_17_afd_2 base_outfifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in(base_outfifo_in_packed), + .flush(flush), + .pop(cmrg_coord_out_0_ready), + .push(cmrg_fifo_push[0]), + .rst_n(rst_n), + .data_out(base_outfifo_out_packed), + .empty(base_outfifo_empty), + .full(base_outfifo_full) +); + +reg_fifo_depth_0_w_17_afd_2 proc_outfifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in(proc_outfifo_in_packed), + .flush(flush), + .pop(cmrg_coord_out_1_ready), + .push(cmrg_fifo_push[1]), + .rst_n(rst_n), + .data_out(proc_outfifo_out_packed), + .empty(proc_outfifo_empty), + .full(proc_outfifo_full) +); + +endmodule // crddrop + +module crddrop_flat ( + input logic clk, + input logic clk_en, + input logic [0:0] [16:0] cmrg_coord_in_0_f_, + input logic cmrg_coord_in_0_valid_f_, + input logic [0:0] [16:0] cmrg_coord_in_1_f_, + input logic cmrg_coord_in_1_valid_f_, + input logic cmrg_coord_out_0_ready_f_, + input logic cmrg_coord_out_1_ready_f_, + input logic crddrop_inst_cmrg_enable, + input logic crddrop_inst_cmrg_mode, + input logic [15:0] crddrop_inst_cmrg_stop_lvl, + input logic crddrop_inst_tile_en, + input logic flush, + input logic rst_n, + output logic cmrg_coord_in_0_ready_f_, + output logic cmrg_coord_in_1_ready_f_, + output logic [0:0] [16:0] cmrg_coord_out_0_f_, + output logic cmrg_coord_out_0_valid_f_, + output logic [0:0] [16:0] cmrg_coord_out_1_f_, + output logic cmrg_coord_out_1_valid_f_ +); + +crddrop crddrop_inst ( + .clk(clk), + .clk_en(clk_en), + .cmrg_coord_in_0(cmrg_coord_in_0_f_), + .cmrg_coord_in_0_valid(cmrg_coord_in_0_valid_f_), + .cmrg_coord_in_1(cmrg_coord_in_1_f_), + .cmrg_coord_in_1_valid(cmrg_coord_in_1_valid_f_), + .cmrg_coord_out_0_ready(cmrg_coord_out_0_ready_f_), + .cmrg_coord_out_1_ready(cmrg_coord_out_1_ready_f_), + .cmrg_enable(crddrop_inst_cmrg_enable), + .cmrg_mode(crddrop_inst_cmrg_mode), + .cmrg_stop_lvl(crddrop_inst_cmrg_stop_lvl), + .flush(flush), + .rst_n(rst_n), + .tile_en(crddrop_inst_tile_en), + .cmrg_coord_in_0_ready(cmrg_coord_in_0_ready_f_), + .cmrg_coord_in_1_ready(cmrg_coord_in_1_ready_f_), + .cmrg_coord_out_0(cmrg_coord_out_0_f_), + .cmrg_coord_out_0_valid(cmrg_coord_out_0_valid_f_), + .cmrg_coord_out_1(cmrg_coord_out_1_f_), + .cmrg_coord_out_1_valid(cmrg_coord_out_1_valid_f_) +); + +endmodule // crddrop_flat + +module crdhold ( + input logic clk, + input logic clk_en, + input logic [16:0] cmrg_coord_in_0, + input logic cmrg_coord_in_0_valid, + input logic [16:0] cmrg_coord_in_1, + input logic cmrg_coord_in_1_valid, + input logic cmrg_coord_out_0_ready, + input logic cmrg_coord_out_1_ready, + input logic cmrg_enable, + input logic [15:0] cmrg_stop_lvl, + input logic flush, + input logic rst_n, + input logic tile_en, + output logic cmrg_coord_in_0_ready, + output logic cmrg_coord_in_1_ready, + output logic [16:0] cmrg_coord_out_0, + output logic cmrg_coord_out_0_valid, + output logic [16:0] cmrg_coord_out_1, + output logic cmrg_coord_out_1_valid +); + +typedef enum logic[1:0] { + DATA_SEEN = 2'h0, + DONE = 2'h1, + START = 2'h2 +} proc_seq_state; +logic base_data_seen; +logic base_done_seen; +logic base_eos_seen; +logic base_infifo_empty; +logic base_infifo_full; +logic [15:0] base_infifo_in_data; +logic base_infifo_in_eos; +logic [16:0] base_infifo_in_packed; +logic base_infifo_in_valid; +logic [16:0] base_infifo_out_packed; +logic base_outfifo_empty; +logic base_outfifo_full; +logic [16:0] base_outfifo_in_packed; +logic [16:0] base_outfifo_out_packed; +logic both_done; +logic clr_pushed_base; +logic clr_pushed_proc; +logic cmrg_coord_in_0_eos; +logic cmrg_coord_in_1_eos; +logic [1:0] cmrg_fifo_pop; +logic [1:0] cmrg_fifo_push; +logic [15:0] data_to_fifo; +logic eos_to_fifo; +logic gclk; +logic [15:0] hold_reg; +logic proc_data_seen; +logic proc_done_seen; +logic proc_eos_seen; +logic proc_infifo_empty; +logic proc_infifo_full; +logic [15:0] proc_infifo_in_data; +logic proc_infifo_in_eos; +logic [16:0] proc_infifo_in_packed; +logic proc_infifo_in_valid; +logic [16:0] proc_infifo_out_packed; +logic proc_outfifo_empty; +logic proc_outfifo_full; +logic [16:0] proc_outfifo_in_packed; +logic [16:0] proc_outfifo_out_packed; +proc_seq_state proc_seq_current_state; +proc_seq_state proc_seq_next_state; +logic pushed_base_sticky; +logic pushed_base_was_high; +logic pushed_proc_sticky; +logic pushed_proc_was_high; +logic pushing_done; +logic reg_clr; +logic reg_hold; +assign gclk = clk & tile_en; +assign cmrg_coord_in_0_eos = cmrg_coord_in_0[16]; +assign cmrg_coord_in_1_eos = cmrg_coord_in_1[16]; +assign base_infifo_in_packed[16] = cmrg_coord_in_0_eos; +assign base_infifo_in_packed[15:0] = cmrg_coord_in_0[15:0]; +assign base_infifo_in_eos = base_infifo_out_packed[16]; +assign base_infifo_in_data = base_infifo_out_packed[15:0]; +assign base_infifo_in_valid = ~base_infifo_empty; +assign cmrg_coord_in_0_ready = ~base_infifo_full; +assign proc_infifo_in_packed[16] = cmrg_coord_in_1_eos; +assign proc_infifo_in_packed[15:0] = cmrg_coord_in_1[15:0]; +assign proc_infifo_in_eos = proc_infifo_out_packed[16]; +assign proc_infifo_in_data = proc_infifo_out_packed[15:0]; +assign proc_infifo_in_valid = ~proc_infifo_empty; +assign cmrg_coord_in_1_ready = ~proc_infifo_full; +assign base_data_seen = base_infifo_in_valid & (~base_infifo_in_eos); +assign proc_data_seen = proc_infifo_in_valid & (~proc_infifo_in_eos); +assign base_eos_seen = base_infifo_in_valid & base_infifo_in_eos & (base_infifo_in_data[9:8] == 2'h0); +assign proc_eos_seen = proc_infifo_in_valid & proc_infifo_in_eos & (proc_infifo_in_data[9:8] == 2'h0); +assign base_done_seen = base_infifo_in_valid & base_infifo_in_eos & (base_infifo_in_data[9:8] == 2'h1); +assign proc_done_seen = proc_infifo_in_valid & proc_infifo_in_eos & (proc_infifo_in_data[9:8] == 2'h1); + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + pushed_proc_was_high <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + pushed_proc_was_high <= 1'h0; + end + else if (clr_pushed_proc) begin + pushed_proc_was_high <= 1'h0; + end + else if (cmrg_fifo_push[1]) begin + pushed_proc_was_high <= 1'h1; + end + end +end +assign pushed_proc_sticky = pushed_proc_was_high; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + pushed_base_was_high <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + pushed_base_was_high <= 1'h0; + end + else if (clr_pushed_base) begin + pushed_base_was_high <= 1'h0; + end + else if (cmrg_fifo_push[0]) begin + pushed_base_was_high <= 1'h1; + end + end +end +assign pushed_base_sticky = pushed_base_was_high; +assign both_done = base_infifo_in_valid & base_infifo_in_eos & proc_infifo_in_valid & + proc_infifo_in_eos & (base_infifo_in_data[9:8] == 2'h1) & + (proc_infifo_in_data[9:8] == 2'h1); +assign pushing_done = base_infifo_in_valid & base_infifo_in_eos & proc_infifo_in_valid & + proc_infifo_in_eos & (base_infifo_in_data[9:8] == 2'h1) & + (proc_infifo_in_data[9:8] == 2'h1) & (~base_outfifo_full) & (~proc_outfifo_full); + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + hold_reg <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + hold_reg <= 16'h0; + end + else if (reg_clr) begin + hold_reg <= 16'h0; + end + else if (reg_hold) begin + hold_reg <= proc_infifo_in_data; + end + end +end +assign base_outfifo_in_packed[16] = base_infifo_in_eos; +assign base_outfifo_in_packed[15:0] = base_infifo_in_data; +assign cmrg_coord_out_0[16] = base_outfifo_out_packed[16]; +assign cmrg_coord_out_0[15:0] = base_outfifo_out_packed[15:0]; +assign cmrg_coord_out_0_valid = ~base_outfifo_empty; +assign proc_outfifo_in_packed[16] = eos_to_fifo; +assign proc_outfifo_in_packed[15:0] = data_to_fifo; +assign cmrg_coord_out_1[16] = proc_outfifo_out_packed[16]; +assign cmrg_coord_out_1[15:0] = proc_outfifo_out_packed[15:0]; +assign cmrg_coord_out_1_valid = ~proc_outfifo_empty; + +always_ff @(posedge clk, negedge rst_n) begin + if (!rst_n) begin + proc_seq_current_state <= START; + end + else if (clk_en) begin + if (flush) begin + proc_seq_current_state <= START; + end + else proc_seq_current_state <= proc_seq_next_state; + end +end +always_comb begin + proc_seq_next_state = proc_seq_current_state; + unique case (proc_seq_current_state) + DATA_SEEN: begin + if (both_done) begin + proc_seq_next_state = DONE; + end + else proc_seq_next_state = DATA_SEEN; + end + DONE: begin + if ((~base_outfifo_full) & (~proc_outfifo_full)) begin + proc_seq_next_state = START; + end + end + START: begin + if (tile_en) begin + proc_seq_next_state = DATA_SEEN; + end + else proc_seq_next_state = START; + end + default: proc_seq_next_state = proc_seq_current_state; + endcase +end +always_comb begin + unique case (proc_seq_current_state) + DATA_SEEN: begin :proc_seq_DATA_SEEN_Output + cmrg_fifo_pop[0] = (base_eos_seen ? 1'h1 & (proc_data_seen | proc_done_seen): base_infifo_in_valid + & (~base_infifo_in_eos) & proc_infifo_in_valid & (~proc_infifo_in_eos)) & + (~base_outfifo_full) & (~proc_outfifo_full) & (~base_done_seen); + cmrg_fifo_pop[1] = (proc_eos_seen ? 1'h1: base_eos_seen & (~base_outfifo_full) & + (~proc_outfifo_full)) & (~proc_done_seen); + cmrg_fifo_push[0] = (base_eos_seen ? 1'h1 & (proc_data_seen | proc_done_seen): base_infifo_in_valid + & (~base_infifo_in_eos) & proc_infifo_in_valid & (~proc_infifo_in_eos)) & + (~base_outfifo_full) & (~proc_outfifo_full) & (~base_done_seen); + cmrg_fifo_push[1] = (base_eos_seen ? 1'h1 & (proc_data_seen | proc_done_seen): base_infifo_in_valid + & (~base_infifo_in_eos) & proc_infifo_in_valid & (~proc_infifo_in_eos)) & + (~base_outfifo_full) & (~proc_outfifo_full) & (~base_done_seen); + data_to_fifo = base_infifo_in_eos ? base_infifo_in_data: proc_infifo_in_data; + eos_to_fifo = base_infifo_in_eos; + clr_pushed_proc = 1'h1; + clr_pushed_base = 1'h1; + reg_clr = 1'h1; + reg_hold = 1'h0; + end :proc_seq_DATA_SEEN_Output + DONE: begin :proc_seq_DONE_Output + cmrg_fifo_pop[0] = (~proc_outfifo_full) & (~base_outfifo_full); + cmrg_fifo_pop[1] = (~proc_outfifo_full) & (~base_outfifo_full); + cmrg_fifo_push[0] = (~proc_outfifo_full) & (~base_outfifo_full); + cmrg_fifo_push[1] = (~proc_outfifo_full) & (~base_outfifo_full); + data_to_fifo = base_infifo_in_data; + eos_to_fifo = 1'h1; + clr_pushed_proc = 1'h1; + clr_pushed_base = 1'h1; + reg_clr = 1'h1; + reg_hold = 1'h0; + end :proc_seq_DONE_Output + START: begin :proc_seq_START_Output + cmrg_fifo_pop[0] = 1'h0; + cmrg_fifo_pop[1] = 1'h0; + cmrg_fifo_push[0] = 1'h0; + cmrg_fifo_push[1] = 1'h0; + data_to_fifo = 16'h0; + eos_to_fifo = 1'h0; + clr_pushed_proc = 1'h1; + clr_pushed_base = 1'h1; + reg_clr = 1'h0; + reg_hold = 1'h0; + end :proc_seq_START_Output + default: begin :proc_seq_default_Output + cmrg_fifo_pop[0] = 1'h0; + cmrg_fifo_pop[1] = 1'h0; + cmrg_fifo_push[0] = 1'h0; + cmrg_fifo_push[1] = 1'h0; + data_to_fifo = 16'h0; + eos_to_fifo = 1'h0; + clr_pushed_proc = 1'h1; + clr_pushed_base = 1'h1; + reg_clr = 1'h0; + reg_hold = 1'h0; + end :proc_seq_default_Output + endcase +end +reg_fifo_depth_0_w_17_afd_2 base_infifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in(base_infifo_in_packed), + .flush(flush), + .pop(cmrg_fifo_pop[0]), + .push(cmrg_coord_in_0_valid), + .rst_n(rst_n), + .data_out(base_infifo_out_packed), + .empty(base_infifo_empty), + .full(base_infifo_full) +); + +reg_fifo_depth_0_w_17_afd_2 proc_infifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in(proc_infifo_in_packed), + .flush(flush), + .pop(cmrg_fifo_pop[1]), + .push(cmrg_coord_in_1_valid), + .rst_n(rst_n), + .data_out(proc_infifo_out_packed), + .empty(proc_infifo_empty), + .full(proc_infifo_full) +); + +reg_fifo_depth_0_w_17_afd_2 base_outfifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in(base_outfifo_in_packed), + .flush(flush), + .pop(cmrg_coord_out_0_ready), + .push(cmrg_fifo_push[0]), + .rst_n(rst_n), + .data_out(base_outfifo_out_packed), + .empty(base_outfifo_empty), + .full(base_outfifo_full) +); + +reg_fifo_depth_0_w_17_afd_2 proc_outfifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in(proc_outfifo_in_packed), + .flush(flush), + .pop(cmrg_coord_out_1_ready), + .push(cmrg_fifo_push[1]), + .rst_n(rst_n), + .data_out(proc_outfifo_out_packed), + .empty(proc_outfifo_empty), + .full(proc_outfifo_full) +); + +endmodule // crdhold + +module crdhold_flat ( + input logic clk, + input logic clk_en, + input logic [0:0] [16:0] cmrg_coord_in_0_f_, + input logic cmrg_coord_in_0_valid_f_, + input logic [0:0] [16:0] cmrg_coord_in_1_f_, + input logic cmrg_coord_in_1_valid_f_, + input logic cmrg_coord_out_0_ready_f_, + input logic cmrg_coord_out_1_ready_f_, + input logic crdhold_inst_cmrg_enable, + input logic [15:0] crdhold_inst_cmrg_stop_lvl, + input logic crdhold_inst_tile_en, + input logic flush, + input logic rst_n, + output logic cmrg_coord_in_0_ready_f_, + output logic cmrg_coord_in_1_ready_f_, + output logic [0:0] [16:0] cmrg_coord_out_0_f_, + output logic cmrg_coord_out_0_valid_f_, + output logic [0:0] [16:0] cmrg_coord_out_1_f_, + output logic cmrg_coord_out_1_valid_f_ +); + +crdhold crdhold_inst ( + .clk(clk), + .clk_en(clk_en), + .cmrg_coord_in_0(cmrg_coord_in_0_f_), + .cmrg_coord_in_0_valid(cmrg_coord_in_0_valid_f_), + .cmrg_coord_in_1(cmrg_coord_in_1_f_), + .cmrg_coord_in_1_valid(cmrg_coord_in_1_valid_f_), + .cmrg_coord_out_0_ready(cmrg_coord_out_0_ready_f_), + .cmrg_coord_out_1_ready(cmrg_coord_out_1_ready_f_), + .cmrg_enable(crdhold_inst_cmrg_enable), + .cmrg_stop_lvl(crdhold_inst_cmrg_stop_lvl), + .flush(flush), + .rst_n(rst_n), + .tile_en(crdhold_inst_tile_en), + .cmrg_coord_in_0_ready(cmrg_coord_in_0_ready_f_), + .cmrg_coord_in_1_ready(cmrg_coord_in_1_ready_f_), + .cmrg_coord_out_0(cmrg_coord_out_0_f_), + .cmrg_coord_out_0_valid(cmrg_coord_out_0_valid_f_), + .cmrg_coord_out_1(cmrg_coord_out_1_f_), + .cmrg_coord_out_1_valid(cmrg_coord_out_1_valid_f_) +); + +endmodule // crdhold_flat + +module intersect_unit ( + input logic clk, + input logic clk_en, + input logic [16:0] coord_in_0, + input logic coord_in_0_valid, + input logic [16:0] coord_in_1, + input logic coord_in_1_valid, + input logic coord_out_ready, + input logic flush, + input logic joiner_op, + input logic [16:0] pos_in_0, + input logic pos_in_0_valid, + input logic [16:0] pos_in_1, + input logic pos_in_1_valid, + input logic pos_out_0_ready, + input logic pos_out_1_ready, + input logic rst_n, + input logic tile_en, + input logic vector_reduce_mode, + output logic coord_in_0_ready, + output logic coord_in_1_ready, + output logic [16:0] coord_out, + output logic coord_out_valid, + output logic pos_in_0_ready, + output logic pos_in_1_ready, + output logic [16:0] pos_out_0, + output logic pos_out_0_valid, + output logic [16:0] pos_out_1, + output logic pos_out_1_valid +); + +typedef enum logic[2:0] { + ALIGN = 3'h0, + DONE = 3'h1, + DRAIN = 3'h2, + IDLE = 3'h3, + ITER = 3'h4, + PASS_DONE = 3'h5, + UNION = 3'h6, + WAIT_FOR_VALID = 3'h7 +} intersect_seq_state; +logic all_are_valid; +logic all_are_valid_but_no_eos; +logic all_have_eos; +logic [1:0] all_have_eos_and_all_valid; +logic any_has_eos; +logic [1:0] clr_eos_sticky; +logic [16:0] coord_fifo_in_packed; +logic [16:0] coord_fifo_out_packed; +logic coord_in_0_fifo_eos_in; +logic [16:0] coord_in_0_fifo_in; +logic coord_in_0_fifo_valid_in; +logic coord_in_1_fifo_eos_in; +logic [16:0] coord_in_1_fifo_in; +logic coord_in_1_fifo_valid_in; +logic coord_in_fifo_0_empty; +logic coord_in_fifo_0_full; +logic coord_in_fifo_1_empty; +logic coord_in_fifo_1_full; +logic [15:0] coord_to_fifo; +logic coord_to_fifo_eos; +logic coordinate_fifo_empty; +logic coordinate_fifo_full; +logic [16:0] done_token; +logic [1:0] eos_in_sticky; +logic eos_sticky_0_sticky; +logic eos_sticky_0_was_high; +logic eos_sticky_1_sticky; +logic eos_sticky_1_was_high; +logic [2:0] fifo_full; +logic fifo_push; +logic gclk; +intersect_seq_state intersect_seq_current_state; +intersect_seq_state intersect_seq_next_state; +logic [15:0] maybe; +logic [1:0] pop_fifo; +logic pos0_fifo_empty; +logic pos0_fifo_full; +logic [16:0] pos0_fifo_in_packed; +logic [16:0] pos0_fifo_out_packed; +logic pos1_fifo_empty; +logic pos1_fifo_full; +logic [16:0] pos1_fifo_in_packed; +logic [16:0] pos1_fifo_out_packed; +logic pos_in_0_fifo_eos_in; +logic [16:0] pos_in_0_fifo_in; +logic pos_in_0_fifo_valid_in; +logic pos_in_1_fifo_eos_in; +logic [16:0] pos_in_1_fifo_in; +logic pos_in_1_fifo_valid_in; +logic pos_in_fifo_0_empty; +logic pos_in_fifo_0_full; +logic pos_in_fifo_1_empty; +logic pos_in_fifo_1_full; +logic [1:0][15:0] pos_to_fifo; +logic [1:0] pos_to_fifo_eos; +logic [16:0] semi_done_token; +assign gclk = clk & tile_en; +assign coord_in_0_fifo_eos_in = coord_in_0_fifo_in[16]; +assign coord_in_0_ready = ~coord_in_fifo_0_full; +assign coord_in_0_fifo_valid_in = ~coord_in_fifo_0_empty; +assign pos_in_0_fifo_eos_in = pos_in_0_fifo_in[16]; +assign pos_in_0_ready = ~pos_in_fifo_0_full; +assign pos_in_0_fifo_valid_in = ~pos_in_fifo_0_empty; +assign coord_in_1_fifo_eos_in = coord_in_1_fifo_in[16]; +assign coord_in_1_ready = ~coord_in_fifo_1_full; +assign coord_in_1_fifo_valid_in = ~coord_in_fifo_1_empty; +assign pos_in_1_fifo_eos_in = pos_in_1_fifo_in[16]; +assign pos_in_1_ready = ~pos_in_fifo_1_full; +assign pos_in_1_fifo_valid_in = ~pos_in_fifo_1_empty; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + eos_sticky_0_was_high <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + eos_sticky_0_was_high <= 1'h0; + end + else if (clr_eos_sticky[0]) begin + eos_sticky_0_was_high <= 1'h0; + end + else if (coord_in_0_fifo_eos_in & coord_in_0_fifo_valid_in & pos_in_0_fifo_eos_in & pos_in_0_fifo_valid_in) begin + eos_sticky_0_was_high <= 1'h1; + end + end +end +assign eos_sticky_0_sticky = (coord_in_0_fifo_eos_in & coord_in_0_fifo_valid_in & pos_in_0_fifo_eos_in & + pos_in_0_fifo_valid_in) | eos_sticky_0_was_high; +assign eos_in_sticky[0] = eos_sticky_0_sticky; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + eos_sticky_1_was_high <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + eos_sticky_1_was_high <= 1'h0; + end + else if (clr_eos_sticky[1]) begin + eos_sticky_1_was_high <= 1'h0; + end + else if (coord_in_1_fifo_eos_in & coord_in_1_fifo_valid_in & pos_in_1_fifo_eos_in & pos_in_1_fifo_valid_in) begin + eos_sticky_1_was_high <= 1'h1; + end + end +end +assign eos_sticky_1_sticky = (coord_in_1_fifo_eos_in & coord_in_1_fifo_valid_in & pos_in_1_fifo_eos_in & + pos_in_1_fifo_valid_in) | eos_sticky_1_was_high; +assign eos_in_sticky[1] = eos_sticky_1_sticky; +assign all_are_valid_but_no_eos = (&{coord_in_0_fifo_valid_in, coord_in_1_fifo_valid_in, pos_in_0_fifo_valid_in, + pos_in_1_fifo_valid_in}) & (~any_has_eos); +assign all_are_valid = &{coord_in_0_fifo_valid_in, coord_in_1_fifo_valid_in, pos_in_0_fifo_valid_in, + pos_in_1_fifo_valid_in}; +assign all_have_eos_and_all_valid[0] = coord_in_0_fifo_eos_in & pos_in_0_fifo_eos_in & coord_in_0_fifo_valid_in & + pos_in_0_fifo_valid_in; +assign all_have_eos_and_all_valid[1] = coord_in_1_fifo_eos_in & pos_in_1_fifo_eos_in & coord_in_1_fifo_valid_in & + pos_in_1_fifo_valid_in; +assign any_has_eos = |({coord_in_0_fifo_eos_in, coord_in_1_fifo_eos_in, pos_in_0_fifo_eos_in, + pos_in_1_fifo_eos_in} & {coord_in_0_fifo_valid_in, coord_in_1_fifo_valid_in, + pos_in_0_fifo_valid_in, pos_in_1_fifo_valid_in}); +assign all_have_eos = &({coord_in_0_fifo_eos_in, coord_in_1_fifo_eos_in, pos_in_0_fifo_eos_in, + pos_in_1_fifo_eos_in} & {coord_in_0_fifo_valid_in, coord_in_1_fifo_valid_in, + pos_in_0_fifo_valid_in, pos_in_1_fifo_valid_in}); +assign maybe = vector_reduce_mode ? 16'h0: {6'h0, 2'h2, 8'h0}; +assign semi_done_token = {1'h1, 11'h0, 1'h1, 4'h0}; +assign done_token = {1'h1, 7'h0, 1'h1, 8'h0}; +assign coord_fifo_in_packed[16] = coord_to_fifo_eos; +assign coord_fifo_in_packed[15:0] = coord_to_fifo; +assign coord_out[16] = coord_fifo_out_packed[16]; +assign coord_out[15:0] = coord_fifo_out_packed[15:0]; +assign pos0_fifo_in_packed[16] = pos_to_fifo_eos[0]; +assign pos0_fifo_in_packed[15:0] = pos_to_fifo[0]; +assign pos_out_0[16] = pos0_fifo_out_packed[16]; +assign pos_out_0[15:0] = pos0_fifo_out_packed[15:0]; +assign pos1_fifo_in_packed[16] = pos_to_fifo_eos[1]; +assign pos1_fifo_in_packed[15:0] = pos_to_fifo[1]; +assign pos_out_1[16] = pos1_fifo_out_packed[16]; +assign pos_out_1[15:0] = pos1_fifo_out_packed[15:0]; +assign fifo_full[0] = coordinate_fifo_full; +assign fifo_full[1] = pos0_fifo_full; +assign fifo_full[2] = pos1_fifo_full; +assign coord_out_valid = ~coordinate_fifo_empty; +assign pos_out_0_valid = ~pos0_fifo_empty; +assign pos_out_1_valid = ~pos1_fifo_empty; + +always_ff @(posedge clk, negedge rst_n) begin + if (!rst_n) begin + intersect_seq_current_state <= IDLE; + end + else if (clk_en) begin + if (flush) begin + intersect_seq_current_state <= IDLE; + end + else intersect_seq_current_state <= intersect_seq_next_state; + end +end +always_comb begin + intersect_seq_next_state = intersect_seq_current_state; + unique case (intersect_seq_current_state) + ALIGN: begin + if (all_have_eos) begin + intersect_seq_next_state = ITER; + end + else intersect_seq_next_state = ALIGN; + end + DONE: intersect_seq_next_state = IDLE; + DRAIN: begin + if (vector_reduce_mode & (~(|fifo_full)) & (&{coord_in_0_fifo_valid_in, coord_in_1_fifo_valid_in, pos_in_0_fifo_valid_in, pos_in_1_fifo_valid_in})) begin + intersect_seq_next_state = PASS_DONE; + end + else if ((~vector_reduce_mode) & (~all_have_eos) & (&{coord_in_0_fifo_valid_in, coord_in_1_fifo_valid_in, pos_in_0_fifo_valid_in, pos_in_1_fifo_valid_in})) begin + intersect_seq_next_state = DONE; + end + else intersect_seq_next_state = DRAIN; + end + IDLE: begin + if (all_are_valid & (joiner_op == 1'h1) & tile_en) begin + intersect_seq_next_state = UNION; + end + else if (any_has_eos & (joiner_op == 1'h0) & tile_en) begin + intersect_seq_next_state = ALIGN; + end + else if (all_are_valid_but_no_eos & (joiner_op == 1'h0) & tile_en) begin + intersect_seq_next_state = ITER; + end + else intersect_seq_next_state = IDLE; + end + ITER: begin + if (any_has_eos & (~all_have_eos)) begin + intersect_seq_next_state = ALIGN; + end + else intersect_seq_next_state = ITER; + end + PASS_DONE: begin + if ((~(|fifo_full)) & (&{coord_in_0_fifo_valid_in, coord_in_1_fifo_valid_in, pos_in_0_fifo_valid_in, pos_in_1_fifo_valid_in})) begin + intersect_seq_next_state = WAIT_FOR_VALID; + end + else intersect_seq_next_state = PASS_DONE; + end + UNION: begin + if (&eos_in_sticky) begin + intersect_seq_next_state = DRAIN; + end + else intersect_seq_next_state = UNION; + end + WAIT_FOR_VALID: begin + if (vector_reduce_mode & (&{coord_in_0_fifo_valid_in, coord_in_1_fifo_valid_in, pos_in_0_fifo_valid_in, pos_in_1_fifo_valid_in})) begin + intersect_seq_next_state = DONE; + end + else if ((~all_have_eos) & (&{coord_in_0_fifo_valid_in, coord_in_1_fifo_valid_in, pos_in_0_fifo_valid_in, pos_in_1_fifo_valid_in})) begin + intersect_seq_next_state = DONE; + end + else intersect_seq_next_state = WAIT_FOR_VALID; + end + default: begin end + endcase +end +always_comb begin + unique case (intersect_seq_current_state) + ALIGN: begin :intersect_seq_ALIGN_Output + pop_fifo[0] = ((~eos_in_sticky[0]) & coord_in_0_fifo_valid_in & pos_in_0_fifo_valid_in) | + (all_have_eos & (~(|fifo_full))); + pop_fifo[1] = ((~eos_in_sticky[1]) & coord_in_1_fifo_valid_in & pos_in_1_fifo_valid_in) | + (all_have_eos & (~(|fifo_full))); + fifo_push = all_have_eos & (~(|fifo_full)); + clr_eos_sticky[0] = all_have_eos & (~(|fifo_full)); + clr_eos_sticky[1] = all_have_eos & (~(|fifo_full)); + coord_to_fifo = coord_in_0_fifo_in[15:0]; + pos_to_fifo[0] = pos_in_0_fifo_in[15:0]; + pos_to_fifo[1] = pos_in_1_fifo_in[15:0]; + coord_to_fifo_eos = 1'h1; + pos_to_fifo_eos[0] = 1'h1; + pos_to_fifo_eos[1] = 1'h1; + end :intersect_seq_ALIGN_Output + DONE: begin :intersect_seq_DONE_Output + pop_fifo[0] = 1'h0; + pop_fifo[1] = 1'h0; + fifo_push = 1'h0; + clr_eos_sticky[0] = 1'h1; + clr_eos_sticky[1] = 1'h1; + coord_to_fifo = 16'h0; + pos_to_fifo[0] = 16'h0; + pos_to_fifo[1] = 16'h0; + coord_to_fifo_eos = 1'h0; + pos_to_fifo_eos[0] = 1'h0; + pos_to_fifo_eos[1] = 1'h0; + end :intersect_seq_DONE_Output + DRAIN: begin :intersect_seq_DRAIN_Output + pop_fifo[0] = (~(|fifo_full)) & all_have_eos & (&{coord_in_0_fifo_valid_in, + coord_in_1_fifo_valid_in, pos_in_0_fifo_valid_in, pos_in_1_fifo_valid_in}); + pop_fifo[1] = (~(|fifo_full)) & all_have_eos & (&{coord_in_0_fifo_valid_in, + coord_in_1_fifo_valid_in, pos_in_0_fifo_valid_in, pos_in_1_fifo_valid_in}); + fifo_push = (~(|fifo_full)) & all_have_eos & (&{coord_in_0_fifo_valid_in, + coord_in_1_fifo_valid_in, pos_in_0_fifo_valid_in, pos_in_1_fifo_valid_in}); + clr_eos_sticky[0] = 1'h0; + clr_eos_sticky[1] = 1'h0; + coord_to_fifo = coord_in_0_fifo_in[15:0]; + pos_to_fifo[0] = pos_in_0_fifo_in[15:0]; + pos_to_fifo[1] = pos_in_0_fifo_in[15:0]; + coord_to_fifo_eos = any_has_eos; + pos_to_fifo_eos[0] = any_has_eos; + pos_to_fifo_eos[1] = any_has_eos; + end :intersect_seq_DRAIN_Output + IDLE: begin :intersect_seq_IDLE_Output + pop_fifo[0] = 1'h0; + pop_fifo[1] = 1'h0; + fifo_push = 1'h0; + clr_eos_sticky[0] = 1'h0; + clr_eos_sticky[1] = 1'h0; + coord_to_fifo = 16'h0; + pos_to_fifo[0] = 16'h0; + pos_to_fifo[1] = 16'h0; + coord_to_fifo_eos = 1'h0; + pos_to_fifo_eos[0] = 1'h0; + pos_to_fifo_eos[1] = 1'h0; + end :intersect_seq_IDLE_Output + ITER: begin :intersect_seq_ITER_Output + pop_fifo[0] = (all_are_valid_but_no_eos | (all_are_valid & all_have_eos)) & + (coord_in_0_fifo_in <= coord_in_1_fifo_in) & (~(|fifo_full)); + pop_fifo[1] = (all_are_valid_but_no_eos | (all_are_valid & all_have_eos)) & + (coord_in_0_fifo_in >= coord_in_1_fifo_in) & (~(|fifo_full)); + fifo_push = all_are_valid & (((coord_in_0_fifo_in == coord_in_1_fifo_in) & (~any_has_eos)) | + all_have_eos) & (~(|fifo_full)); + clr_eos_sticky[0] = all_have_eos & (~(|fifo_full)); + clr_eos_sticky[1] = all_have_eos & (~(|fifo_full)); + coord_to_fifo = coord_in_0_fifo_in[15:0]; + pos_to_fifo[0] = pos_in_0_fifo_in[15:0]; + pos_to_fifo[1] = pos_in_1_fifo_in[15:0]; + coord_to_fifo_eos = all_have_eos; + pos_to_fifo_eos[0] = all_have_eos; + pos_to_fifo_eos[1] = all_have_eos; + end :intersect_seq_ITER_Output + PASS_DONE: begin :intersect_seq_PASS_DONE_Output + pop_fifo[0] = (&{coord_in_0_fifo_valid_in, coord_in_1_fifo_valid_in, pos_in_0_fifo_valid_in, + pos_in_1_fifo_valid_in}) & (coord_in_0_fifo_in == done_token); + pop_fifo[1] = (&{coord_in_0_fifo_valid_in, coord_in_1_fifo_valid_in, pos_in_0_fifo_valid_in, + pos_in_1_fifo_valid_in}) & (coord_in_1_fifo_in == done_token); + fifo_push = (~(|fifo_full)) & (&{coord_in_0_fifo_valid_in, coord_in_1_fifo_valid_in, + pos_in_0_fifo_valid_in, pos_in_1_fifo_valid_in}); + clr_eos_sticky[0] = 1'h0; + clr_eos_sticky[1] = 1'h0; + coord_to_fifo = (coord_in_0_fifo_in == done_token) ? done_token[15:0]: semi_done_token[15:0]; + pos_to_fifo[0] = (coord_in_0_fifo_in == done_token) ? done_token[15:0]: semi_done_token[15:0]; + pos_to_fifo[1] = (coord_in_0_fifo_in == done_token) ? done_token[15:0]: semi_done_token[15:0]; + coord_to_fifo_eos = 1'h1; + pos_to_fifo_eos[0] = 1'h1; + pos_to_fifo_eos[1] = 1'h1; + end :intersect_seq_PASS_DONE_Output + UNION: begin :intersect_seq_UNION_Output + pop_fifo[0] = all_are_valid & ((coord_in_0_fifo_in <= coord_in_1_fifo_in) | + coord_in_1_fifo_eos_in) & (~(|fifo_full)) & (~coord_in_0_fifo_eos_in); + pop_fifo[1] = all_are_valid & ((coord_in_0_fifo_in >= coord_in_1_fifo_in) | + coord_in_0_fifo_eos_in) & (~(|fifo_full)) & (~coord_in_1_fifo_eos_in); + fifo_push = all_are_valid & (~(|fifo_full)) & (~all_have_eos); + clr_eos_sticky[0] = 1'h0; + clr_eos_sticky[1] = 1'h0; + coord_to_fifo = pop_fifo[0] ? coord_in_0_fifo_in[15:0]: coord_in_1_fifo_in[15:0]; + pos_to_fifo[0] = pop_fifo[0] ? pos_in_0_fifo_in[15:0]: maybe; + pos_to_fifo[1] = pop_fifo[1] ? pos_in_1_fifo_in[15:0]: maybe; + coord_to_fifo_eos = 1'h0; + pos_to_fifo_eos[0] = (~vector_reduce_mode) & (~pop_fifo[0]); + pos_to_fifo_eos[1] = (~vector_reduce_mode) & (~pop_fifo[1]); + end :intersect_seq_UNION_Output + WAIT_FOR_VALID: begin :intersect_seq_WAIT_FOR_VALID_Output + pop_fifo[0] = 1'h0; + pop_fifo[1] = 1'h0; + fifo_push = 1'h0; + clr_eos_sticky[0] = 1'h0; + clr_eos_sticky[1] = 1'h0; + coord_to_fifo = 16'h0; + pos_to_fifo[0] = 16'h0; + pos_to_fifo[1] = 16'h0; + coord_to_fifo_eos = 1'h0; + pos_to_fifo_eos[0] = 1'h0; + pos_to_fifo_eos[1] = 1'h0; + end :intersect_seq_WAIT_FOR_VALID_Output + default: begin end + endcase +end +reg_fifo_depth_0_w_17_afd_2 coord_in_fifo_0 ( + .clk(gclk), + .clk_en(clk_en), + .data_in(coord_in_0), + .flush(flush), + .pop(pop_fifo[0]), + .push(coord_in_0_valid), + .rst_n(rst_n), + .data_out(coord_in_0_fifo_in), + .empty(coord_in_fifo_0_empty), + .full(coord_in_fifo_0_full) +); + +reg_fifo_depth_0_w_17_afd_2 pos_in_fifo_0 ( + .clk(gclk), + .clk_en(clk_en), + .data_in(pos_in_0), + .flush(flush), + .pop(pop_fifo[0]), + .push(pos_in_0_valid), + .rst_n(rst_n), + .data_out(pos_in_0_fifo_in), + .empty(pos_in_fifo_0_empty), + .full(pos_in_fifo_0_full) +); + +reg_fifo_depth_0_w_17_afd_2 coord_in_fifo_1 ( + .clk(gclk), + .clk_en(clk_en), + .data_in(coord_in_1), + .flush(flush), + .pop(pop_fifo[1]), + .push(coord_in_1_valid), + .rst_n(rst_n), + .data_out(coord_in_1_fifo_in), + .empty(coord_in_fifo_1_empty), + .full(coord_in_fifo_1_full) +); + +reg_fifo_depth_0_w_17_afd_2 pos_in_fifo_1 ( + .clk(gclk), + .clk_en(clk_en), + .data_in(pos_in_1), + .flush(flush), + .pop(pop_fifo[1]), + .push(pos_in_1_valid), + .rst_n(rst_n), + .data_out(pos_in_1_fifo_in), + .empty(pos_in_fifo_1_empty), + .full(pos_in_fifo_1_full) +); + +reg_fifo_depth_0_w_17_afd_2 coordinate_fifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in(coord_fifo_in_packed), + .flush(flush), + .pop(coord_out_ready), + .push(fifo_push), + .rst_n(rst_n), + .data_out(coord_fifo_out_packed), + .empty(coordinate_fifo_empty), + .full(coordinate_fifo_full) +); + +reg_fifo_depth_0_w_17_afd_2 pos0_fifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in(pos0_fifo_in_packed), + .flush(flush), + .pop(pos_out_0_ready), + .push(fifo_push), + .rst_n(rst_n), + .data_out(pos0_fifo_out_packed), + .empty(pos0_fifo_empty), + .full(pos0_fifo_full) +); + +reg_fifo_depth_0_w_17_afd_2 pos1_fifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in(pos1_fifo_in_packed), + .flush(flush), + .pop(pos_out_1_ready), + .push(fifo_push), + .rst_n(rst_n), + .data_out(pos1_fifo_out_packed), + .empty(pos1_fifo_empty), + .full(pos1_fifo_full) +); + +endmodule // intersect_unit + +module intersect_unit_flat ( + input logic clk, + input logic clk_en, + input logic [0:0] [16:0] coord_in_0_f_, + input logic coord_in_0_valid_f_, + input logic [0:0] [16:0] coord_in_1_f_, + input logic coord_in_1_valid_f_, + input logic coord_out_ready_f_, + input logic flush, + input logic intersect_unit_inst_joiner_op, + input logic intersect_unit_inst_tile_en, + input logic intersect_unit_inst_vector_reduce_mode, + input logic [0:0] [16:0] pos_in_0_f_, + input logic pos_in_0_valid_f_, + input logic [0:0] [16:0] pos_in_1_f_, + input logic pos_in_1_valid_f_, + input logic pos_out_0_ready_f_, + input logic pos_out_1_ready_f_, + input logic rst_n, + output logic coord_in_0_ready_f_, + output logic coord_in_1_ready_f_, + output logic [0:0] [16:0] coord_out_f_, + output logic coord_out_valid_f_, + output logic pos_in_0_ready_f_, + output logic pos_in_1_ready_f_, + output logic [0:0] [16:0] pos_out_0_f_, + output logic pos_out_0_valid_f_, + output logic [0:0] [16:0] pos_out_1_f_, + output logic pos_out_1_valid_f_ +); + +intersect_unit intersect_unit_inst ( + .clk(clk), + .clk_en(clk_en), + .coord_in_0(coord_in_0_f_), + .coord_in_0_valid(coord_in_0_valid_f_), + .coord_in_1(coord_in_1_f_), + .coord_in_1_valid(coord_in_1_valid_f_), + .coord_out_ready(coord_out_ready_f_), + .flush(flush), + .joiner_op(intersect_unit_inst_joiner_op), + .pos_in_0(pos_in_0_f_), + .pos_in_0_valid(pos_in_0_valid_f_), + .pos_in_1(pos_in_1_f_), + .pos_in_1_valid(pos_in_1_valid_f_), + .pos_out_0_ready(pos_out_0_ready_f_), + .pos_out_1_ready(pos_out_1_ready_f_), + .rst_n(rst_n), + .tile_en(intersect_unit_inst_tile_en), + .vector_reduce_mode(intersect_unit_inst_vector_reduce_mode), + .coord_in_0_ready(coord_in_0_ready_f_), + .coord_in_1_ready(coord_in_1_ready_f_), + .coord_out(coord_out_f_), + .coord_out_valid(coord_out_valid_f_), + .pos_in_0_ready(pos_in_0_ready_f_), + .pos_in_1_ready(pos_in_1_ready_f_), + .pos_out_0(pos_out_0_f_), + .pos_out_0_valid(pos_out_0_valid_f_), + .pos_out_1(pos_out_1_f_), + .pos_out_1_valid(pos_out_1_valid_f_) +); + +endmodule // intersect_unit_flat + +module reduce_pe_cluster ( + input logic bit0, + input logic bit1, + input logic bit2, + input logic clk, + input logic clk_en, + input logic [16:0] data0, + input logic data0_valid, + input logic [16:0] data1, + input logic data1_valid, + input logic [16:0] data2, + input logic data2_valid, + input logic flush, + input logic pe_dense_mode, + input logic pe_in_external, + input logic [83:0] pe_onyxpeintf_inst, + input logic [2:0] pe_sparse_num_inputs, + input logic pe_tile_en, + input logic [16:0] reduce_data_in, + input logic reduce_data_in_valid, + input logic reduce_data_out_ready, + input logic [15:0] reduce_default_value, + input logic [15:0] reduce_stop_lvl, + input logic reduce_tile_en, + input logic res_ready, + input logic rst_n, + input logic tile_en, + output logic data0_ready, + output logic data1_ready, + output logic data2_ready, + output logic [15:0] pe_onyxpeintf_O2, + output logic [15:0] pe_onyxpeintf_O3, + output logic [15:0] pe_onyxpeintf_O4, + output logic reduce_data_in_ready, + output logic [16:0] reduce_data_out, + output logic reduce_data_out_valid, + output logic [16:0] res, + output logic res_p, + output logic res_valid +); + +logic gclk; +logic [16:0] pe_data0; +logic [16:0] pe_data1; +logic [16:0] pe_data2; +logic [16:0] pe_data_to_reduce; +logic [16:0] pe_res; +logic [16:0] reduce_data_to_pe0; +logic [16:0] reduce_data_to_pe1; +assign gclk = clk & tile_en; +assign res = pe_res; +assign pe_data0 = pe_in_external ? data0: reduce_data_to_pe0; +assign pe_data1 = pe_in_external ? data1: reduce_data_to_pe1; +assign pe_data2 = data2; +assign pe_data_to_reduce = pe_res; +reg_cr reduce ( + .clk(gclk), + .clk_en(clk_en), + .data_from_pe(pe_data_to_reduce), + .data_in(reduce_data_in), + .data_in_valid(reduce_data_in_valid), + .data_out_ready(reduce_data_out_ready), + .default_value(reduce_default_value), + .flush(flush), + .rst_n(rst_n), + .stop_lvl(reduce_stop_lvl), + .tile_en(reduce_tile_en), + .data_in_ready(reduce_data_in_ready), + .data_out(reduce_data_out), + .data_out_valid(reduce_data_out_valid), + .data_to_pe0(reduce_data_to_pe0), + .data_to_pe1(reduce_data_to_pe1) +); + +PE_onyx pe ( + .bit0(bit0), + .bit1(bit1), + .bit2(bit2), + .clk(gclk), + .clk_en(clk_en), + .data0(pe_data0), + .data0_valid(data0_valid), + .data1(pe_data1), + .data1_valid(data1_valid), + .data2(pe_data2), + .data2_valid(data2_valid), + .dense_mode(pe_dense_mode), + .flush(flush), + .onyxpeintf_inst(pe_onyxpeintf_inst), + .res_ready(res_ready), + .rst_n(rst_n), + .sparse_num_inputs(pe_sparse_num_inputs), + .tile_en(pe_tile_en), + .data0_ready(data0_ready), + .data1_ready(data1_ready), + .data2_ready(data2_ready), + .onyxpeintf_O2(pe_onyxpeintf_O2), + .onyxpeintf_O3(pe_onyxpeintf_O3), + .onyxpeintf_O4(pe_onyxpeintf_O4), + .res(pe_res), + .res_p(res_p), + .res_valid(res_valid) +); + +endmodule // reduce_pe_cluster + +module reduce_pe_cluster_flat ( + input logic bit0_f_, + input logic bit1_f_, + input logic bit2_f_, + input logic clk, + input logic clk_en, + input logic [0:0] [16:0] data0_f_, + input logic data0_valid_f_, + input logic [0:0] [16:0] data1_f_, + input logic data1_valid_f_, + input logic [0:0] [16:0] data2_f_, + input logic data2_valid_f_, + input logic flush, + input logic [0:0] [16:0] reduce_data_in_f_, + input logic reduce_data_in_valid_f_, + input logic reduce_data_out_ready_f_, + input logic reduce_pe_cluster_inst_pe_dense_mode, + input logic reduce_pe_cluster_inst_pe_in_external, + input logic [83:0] reduce_pe_cluster_inst_pe_onyxpeintf_inst, + input logic [2:0] reduce_pe_cluster_inst_pe_sparse_num_inputs, + input logic reduce_pe_cluster_inst_pe_tile_en, + input logic [15:0] reduce_pe_cluster_inst_reduce_default_value, + input logic [15:0] reduce_pe_cluster_inst_reduce_stop_lvl, + input logic reduce_pe_cluster_inst_reduce_tile_en, + input logic reduce_pe_cluster_inst_tile_en, + input logic res_ready_f_, + input logic rst_n, + output logic data0_ready_f_, + output logic data1_ready_f_, + output logic data2_ready_f_, + output logic reduce_data_in_ready_f_, + output logic [0:0] [16:0] reduce_data_out_f_, + output logic reduce_data_out_valid_f_, + output logic [15:0] reduce_pe_cluster_inst_pe_onyxpeintf_O2, + output logic [15:0] reduce_pe_cluster_inst_pe_onyxpeintf_O3, + output logic [15:0] reduce_pe_cluster_inst_pe_onyxpeintf_O4, + output logic [0:0] [16:0] res_f_, + output logic res_p_f_, + output logic res_valid_f_ +); + +reduce_pe_cluster reduce_pe_cluster_inst ( + .bit0(bit0_f_), + .bit1(bit1_f_), + .bit2(bit2_f_), + .clk(clk), + .clk_en(clk_en), + .data0(data0_f_), + .data0_valid(data0_valid_f_), + .data1(data1_f_), + .data1_valid(data1_valid_f_), + .data2(data2_f_), + .data2_valid(data2_valid_f_), + .flush(flush), + .pe_dense_mode(reduce_pe_cluster_inst_pe_dense_mode), + .pe_in_external(reduce_pe_cluster_inst_pe_in_external), + .pe_onyxpeintf_inst(reduce_pe_cluster_inst_pe_onyxpeintf_inst), + .pe_sparse_num_inputs(reduce_pe_cluster_inst_pe_sparse_num_inputs), + .pe_tile_en(reduce_pe_cluster_inst_pe_tile_en), + .reduce_data_in(reduce_data_in_f_), + .reduce_data_in_valid(reduce_data_in_valid_f_), + .reduce_data_out_ready(reduce_data_out_ready_f_), + .reduce_default_value(reduce_pe_cluster_inst_reduce_default_value), + .reduce_stop_lvl(reduce_pe_cluster_inst_reduce_stop_lvl), + .reduce_tile_en(reduce_pe_cluster_inst_reduce_tile_en), + .res_ready(res_ready_f_), + .rst_n(rst_n), + .tile_en(reduce_pe_cluster_inst_tile_en), + .data0_ready(data0_ready_f_), + .data1_ready(data1_ready_f_), + .data2_ready(data2_ready_f_), + .pe_onyxpeintf_O2(reduce_pe_cluster_inst_pe_onyxpeintf_O2), + .pe_onyxpeintf_O3(reduce_pe_cluster_inst_pe_onyxpeintf_O3), + .pe_onyxpeintf_O4(reduce_pe_cluster_inst_pe_onyxpeintf_O4), + .reduce_data_in_ready(reduce_data_in_ready_f_), + .reduce_data_out(reduce_data_out_f_), + .reduce_data_out_valid(reduce_data_out_valid_f_), + .res(res_f_), + .res_p(res_p_f_), + .res_valid(res_valid_f_) +); + +endmodule // reduce_pe_cluster_flat + +module reg_cr ( + input logic clk, + input logic clk_en, + input logic [16:0] data_from_pe, + input logic [16:0] data_in, + input logic data_in_valid, + input logic data_out_ready, + input logic [15:0] default_value, + input logic flush, + input logic rst_n, + input logic [15:0] stop_lvl, + input logic tile_en, + output logic data_in_ready, + output logic [16:0] data_out, + output logic data_out_valid, + output logic [16:0] data_to_pe0, + output logic [16:0] data_to_pe1 +); + +typedef enum logic[2:0] { + ACCUM = 3'h0, + DONE = 3'h1, + OUTPUT = 3'h2, + START = 3'h3, + STOP_PASS = 3'h4 +} accum_seq_state; +logic [15:0] accum_reg; +accum_seq_state accum_seq_current_state; +accum_seq_state accum_seq_next_state; +logic [15:0] data_to_fifo; +logic gclk; +logic [16:0] infifo_in_packed; +logic [15:0] infifo_out_data; +logic infifo_out_eos; +logic [16:0] infifo_out_packed; +logic infifo_out_valid; +logic infifo_pop; +logic infifo_push; +logic input_fifo_empty; +logic input_fifo_full; +logic outfifo_full; +logic outfifo_in_eos; +logic [16:0] outfifo_in_packed; +logic [16:0] outfifo_out_packed; +logic outfifo_pop; +logic outfifo_push; +logic output_fifo_empty; +logic reg_clr; +logic update_accum_reg; +assign gclk = clk & tile_en; +assign data_in_ready = ~input_fifo_full; +assign infifo_in_packed[16:0] = data_in; +assign infifo_out_eos = infifo_out_packed[16]; +assign infifo_out_data = infifo_out_packed[15:0]; +assign infifo_push = data_in_valid; +assign infifo_out_valid = ~input_fifo_empty; +assign data_to_pe0 = infifo_out_packed; +assign data_to_pe1[15:0] = accum_reg; +assign data_to_pe1[16] = 1'h0; +assign outfifo_in_packed[16] = outfifo_in_eos; +assign outfifo_in_packed[15:0] = data_to_fifo; +assign data_out = outfifo_out_packed[16:0]; +assign data_out_valid = ~output_fifo_empty; +assign outfifo_pop = data_out_ready; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + accum_reg <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + accum_reg <= 16'h0; + end + else if (reg_clr) begin + accum_reg <= default_value; + end + else if (update_accum_reg) begin + accum_reg <= data_from_pe[15:0]; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (!rst_n) begin + accum_seq_current_state <= START; + end + else if (clk_en) begin + if (flush) begin + accum_seq_current_state <= START; + end + else accum_seq_current_state <= accum_seq_next_state; + end +end +always_comb begin + accum_seq_next_state = accum_seq_current_state; + unique case (accum_seq_current_state) + ACCUM: begin + if (infifo_out_valid & infifo_out_eos) begin + accum_seq_next_state = OUTPUT; + end + else accum_seq_next_state = ACCUM; + end + DONE: begin + if (~outfifo_full) begin + accum_seq_next_state = START; + end + else accum_seq_next_state = DONE; + end + OUTPUT: begin + if (~outfifo_full) begin + accum_seq_next_state = STOP_PASS; + end + else accum_seq_next_state = OUTPUT; + end + START: begin + if (infifo_out_valid & (~infifo_out_eos)) begin + accum_seq_next_state = ACCUM; + end + else if (infifo_out_valid & infifo_out_eos & (infifo_out_data[9:8] == 2'h1)) begin + accum_seq_next_state = DONE; + end + else if (infifo_out_valid & infifo_out_eos & (infifo_out_data[9:8] == 2'h0)) begin + accum_seq_next_state = OUTPUT; + end + else accum_seq_next_state = START; + end + STOP_PASS: begin + if (~outfifo_full) begin + accum_seq_next_state = START; + end + else accum_seq_next_state = STOP_PASS; + end + default: accum_seq_next_state = accum_seq_current_state; + endcase +end +always_comb begin + unique case (accum_seq_current_state) + ACCUM: begin :accum_seq_ACCUM_Output + infifo_pop = infifo_out_valid & (~infifo_out_eos); + outfifo_push = 1'h0; + data_to_fifo = 16'h0; + outfifo_in_eos = 1'h0; + reg_clr = 1'h0; + update_accum_reg = infifo_out_valid & (~infifo_out_eos); + end :accum_seq_ACCUM_Output + DONE: begin :accum_seq_DONE_Output + infifo_pop = ~outfifo_full; + outfifo_push = ~outfifo_full; + reg_clr = 1'h1; + data_to_fifo = infifo_out_data; + outfifo_in_eos = infifo_out_eos; + update_accum_reg = 1'h0; + end :accum_seq_DONE_Output + OUTPUT: begin :accum_seq_OUTPUT_Output + infifo_pop = 1'h0; + outfifo_push = ~outfifo_full; + reg_clr = 1'h0; + data_to_fifo = accum_reg; + outfifo_in_eos = 1'h0; + update_accum_reg = 1'h0; + end :accum_seq_OUTPUT_Output + START: begin :accum_seq_START_Output + infifo_pop = 1'h0; + outfifo_push = 1'h0; + data_to_fifo = 16'h0; + outfifo_in_eos = 1'h0; + reg_clr = 1'h0; + update_accum_reg = 1'h0; + end :accum_seq_START_Output + STOP_PASS: begin :accum_seq_STOP_PASS_Output + infifo_pop = (~outfifo_full) & infifo_out_valid & infifo_out_eos & (infifo_out_data[9:8] == + 2'h0); + outfifo_push = (~outfifo_full) & infifo_out_valid & infifo_out_eos & (infifo_out_data[9:8] == + 2'h0) & (infifo_out_data[7:0] > 8'h0); + reg_clr = 1'h1; + data_to_fifo = infifo_out_data - 16'h1; + outfifo_in_eos = 1'h1; + update_accum_reg = 1'h0; + end :accum_seq_STOP_PASS_Output + default: begin :accum_seq_default_Output + infifo_pop = 1'h0; + outfifo_push = 1'h0; + data_to_fifo = 16'h0; + outfifo_in_eos = 1'h0; + reg_clr = 1'h0; + update_accum_reg = 1'h0; + end :accum_seq_default_Output + endcase +end +reg_fifo_depth_0_w_17_afd_2 input_fifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in(infifo_in_packed), + .flush(flush), + .pop(infifo_pop), + .push(infifo_push), + .rst_n(rst_n), + .data_out(infifo_out_packed), + .empty(input_fifo_empty), + .full(input_fifo_full) +); + +reg_fifo_depth_0_w_17_afd_2 output_fifo ( + .clk(gclk), + .clk_en(clk_en), + .data_in(outfifo_in_packed), + .flush(flush), + .pop(outfifo_pop), + .push(outfifo_push), + .rst_n(rst_n), + .data_out(outfifo_out_packed), + .empty(output_fifo_empty), + .full(outfifo_full) +); + +endmodule // reg_cr + +module reg_fifo_depth_0_w_17_afd_2 ( + input logic clk, + input logic clk_en, + input logic [0:0] [16:0] data_in, + input logic flush, + input logic pop, + input logic push, + input logic rst_n, + output logic almost_full, + output logic [0:0] [16:0] data_out, + output logic empty, + output logic full, + output logic valid +); + +assign data_out = data_in; +assign valid = push; +assign empty = ~push; +assign full = ~pop; +assign almost_full = ~pop; +endmodule // reg_fifo_depth_0_w_17_afd_2 + +module reg_fifo_depth_2_w_17_afd_2 ( + input logic clk, + input logic clk_en, + input logic [0:0] [16:0] data_in, + input logic flush, + input logic pop, + input logic push, + input logic rst_n, + output logic almost_full, + output logic [0:0] [16:0] data_out, + output logic empty, + output logic full, + output logic valid +); + +logic [1:0] num_items; +logic passthru; +logic rd_ptr; +logic read; +logic [1:0][0:0][16:0] reg_array; +logic wr_ptr; +logic write; +assign full = num_items == 2'h2; +assign almost_full = num_items >= 2'h0; +assign empty = num_items == 2'h0; +assign read = pop & (~passthru) & (~empty); +assign passthru = 1'h0; +assign write = push & (~passthru) & (~full); + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + num_items <= 2'h0; + end + else if (flush) begin + num_items <= 2'h0; + end + else if (clk_en) begin + if (write & (~read)) begin + num_items <= num_items + 2'h1; + end + else if ((~write) & read) begin + num_items <= num_items - 2'h1; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + reg_array <= 34'h0; + end + else if (flush) begin + reg_array <= 34'h0; + end + else if (clk_en) begin + if (write) begin + reg_array[wr_ptr] <= data_in; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + wr_ptr <= 1'h0; + end + else if (flush) begin + wr_ptr <= 1'h0; + end + else if (clk_en) begin + if (write) begin + if (wr_ptr == 1'h1) begin + wr_ptr <= 1'h0; + end + else wr_ptr <= wr_ptr + 1'h1; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + rd_ptr <= 1'h0; + end + else if (flush) begin + rd_ptr <= 1'h0; + end + else if (clk_en) begin + if (read) begin + rd_ptr <= rd_ptr + 1'h1; + end + end +end +always_comb begin + if (passthru) begin + data_out = data_in; + end + else data_out = reg_array[rd_ptr]; +end +always_comb begin + valid = (~empty) | passthru; +end +endmodule // reg_fifo_depth_2_w_17_afd_2 + diff --git a/sam/onyx/.magma/PondTop_W-kratos.sv b/sam/onyx/.magma/PondTop_W-kratos.sv new file mode 100644 index 00000000..f23d7e2e --- /dev/null +++ b/sam/onyx/.magma/PondTop_W-kratos.sv @@ -0,0 +1,1362 @@ +module PondTop ( + input logic [31:0] CONFIG_SPACE_0, + input logic [31:0] CONFIG_SPACE_1, + input logic [31:0] CONFIG_SPACE_10, + input logic [31:0] CONFIG_SPACE_11, + input logic [31:0] CONFIG_SPACE_12, + input logic [31:0] CONFIG_SPACE_13, + input logic [31:0] CONFIG_SPACE_14, + input logic [31:0] CONFIG_SPACE_15, + input logic [29:0] CONFIG_SPACE_16, + input logic [31:0] CONFIG_SPACE_2, + input logic [31:0] CONFIG_SPACE_3, + input logic [31:0] CONFIG_SPACE_4, + input logic [31:0] CONFIG_SPACE_5, + input logic [31:0] CONFIG_SPACE_6, + input logic [31:0] CONFIG_SPACE_7, + input logic [31:0] CONFIG_SPACE_8, + input logic [31:0] CONFIG_SPACE_9, + input logic [0:0] [16:0] PondTop_input_width_17_num_0, + input logic [0:0] [16:0] PondTop_input_width_17_num_1, + input logic clk, + input logic clk_en, + input logic [7:0] config_addr_in, + input logic [31:0] config_data_in, + input logic config_en, + input logic config_read, + input logic config_write, + input logic flush, + input logic rst_n, + input logic tile_en, + output logic [0:0] [16:0] PondTop_output_width_17_num_0, + output logic [0:0] [16:0] PondTop_output_width_17_num_1, + output logic PondTop_output_width_1_num_0, + output logic PondTop_output_width_1_num_1, + output logic [0:0] [31:0] config_data_out +); + +logic [541:0] CONFIG_SPACE; +logic [15:0] config_data_in_shrt; +logic [0:0][15:0] config_data_out_shrt; +logic [4:0] config_seq_addr_out; +logic config_seq_clk_en; +logic [0:0][0:0][15:0] config_seq_rd_data_stg; +logic config_seq_ren_out; +logic config_seq_wen_out; +logic [0:0][15:0] config_seq_wr_data; +logic gclk; +logic mem_ctrl_strg_ub_thin_PondTop_flat_clk; +logic [0:0][16:0] mem_ctrl_strg_ub_thin_PondTop_flat_data_out_f_0; +logic [0:0][16:0] mem_ctrl_strg_ub_thin_PondTop_flat_data_out_f_1; +logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_data_from_strg_lifted; +logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_data_to_strg_lifted; +logic [4:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_starting_addr; +logic [4:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_starting_addr2; +logic [4:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides2_0; +logic [4:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides2_1; +logic [4:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_0; +logic [4:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_1; +logic [4:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_2; +logic [4:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_3; +logic [2:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_dimensionality; +logic [1:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_dimensionality2; +logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges2_0; +logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges2_1; +logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_0; +logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_1; +logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_2; +logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_3; +logic mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_enable; +logic mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_enable2; +logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_starting_addr; +logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_starting_addr2; +logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides2_0; +logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides2_1; +logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_0; +logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_1; +logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_2; +logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_3; +logic [4:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_rd_addr_out_lifted; +logic [4:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_starting_addr; +logic [4:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_starting_addr2; +logic [4:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides2_0; +logic [4:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides2_1; +logic [4:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_0; +logic [4:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_1; +logic [4:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_2; +logic [4:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_3; +logic [2:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_dimensionality; +logic [1:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_dimensionality2; +logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges2_0; +logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges2_1; +logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_0; +logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_1; +logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_2; +logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_3; +logic mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_enable; +logic mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_enable2; +logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_starting_addr; +logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_starting_addr2; +logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides2_0; +logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides2_1; +logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_0; +logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_1; +logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_2; +logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_3; +logic mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_ren_to_strg_lifted; +logic [4:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_tmp0_rdaddr_lifted; +logic mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_tmp0_rden_lifted; +logic mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_wen_to_strg_lifted; +logic [4:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_wr_addr_out_lifted; +logic mem_ctrl_strg_ub_thin_PondTop_flat_valid_out_f_b_0; +logic mem_ctrl_strg_ub_thin_PondTop_flat_valid_out_f_b_1; +logic memory_0_clk_en; +logic [15:0] memory_0_data_in_p0; +logic [15:0] memory_0_data_out_p0; +logic [15:0] memory_0_data_out_p1; +logic [4:0] memory_0_read_addr_p0; +logic [4:0] memory_0_read_addr_p1; +logic memory_0_read_enable_p0; +logic memory_0_read_enable_p1; +logic [4:0] memory_0_write_addr_p0; +logic memory_0_write_enable_p0; +logic mode; +assign mode = 1'h0; +assign gclk = clk & tile_en; +assign mem_ctrl_strg_ub_thin_PondTop_flat_clk = gclk; +always_comb begin + PondTop_output_width_17_num_0 = 17'h0; + if (1'h0 == mode) begin + PondTop_output_width_17_num_0 = mem_ctrl_strg_ub_thin_PondTop_flat_data_out_f_0; + end + else PondTop_output_width_17_num_0 = 17'h0; +end +always_comb begin + PondTop_output_width_17_num_1 = 17'h0; + if (1'h0 == mode) begin + PondTop_output_width_17_num_1 = mem_ctrl_strg_ub_thin_PondTop_flat_data_out_f_1; + end + else PondTop_output_width_17_num_1 = 17'h0; +end +always_comb begin + PondTop_output_width_1_num_0 = 1'h0; + if (1'h0 == mode) begin + PondTop_output_width_1_num_0 = mem_ctrl_strg_ub_thin_PondTop_flat_valid_out_f_b_0; + end + else PondTop_output_width_1_num_0 = 1'h0; +end +always_comb begin + PondTop_output_width_1_num_1 = 1'h0; + if (1'h0 == mode) begin + PondTop_output_width_1_num_1 = mem_ctrl_strg_ub_thin_PondTop_flat_valid_out_f_b_1; + end + else PondTop_output_width_1_num_1 = 1'h0; +end +always_comb begin + memory_0_data_in_p0 = 16'h0; + memory_0_write_addr_p0 = 5'h0; + memory_0_write_enable_p0 = 1'h0; + memory_0_read_addr_p0 = 5'h0; + memory_0_read_enable_p0 = 1'h0; + if (|config_en) begin + memory_0_data_in_p0 = config_seq_wr_data; + memory_0_write_addr_p0 = config_seq_addr_out; + memory_0_write_enable_p0 = config_seq_wen_out; + memory_0_read_addr_p0 = config_seq_addr_out; + memory_0_read_enable_p0 = config_seq_ren_out; + end + else if (1'h0 == mode) begin + memory_0_data_in_p0 = mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_data_to_strg_lifted; + memory_0_write_addr_p0 = mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_wr_addr_out_lifted; + memory_0_write_enable_p0 = mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_wen_to_strg_lifted; + memory_0_read_addr_p0 = mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_tmp0_rdaddr_lifted; + memory_0_read_enable_p0 = mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_tmp0_rden_lifted; + end +end +always_comb begin + config_seq_rd_data_stg = memory_0_data_out_p0; +end +always_comb begin + memory_0_read_addr_p1 = 5'h0; + memory_0_read_enable_p1 = 1'h0; + if (1'h0 == mode) begin + memory_0_read_addr_p1 = mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_rd_addr_out_lifted; + memory_0_read_enable_p1 = mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_ren_to_strg_lifted; + end +end +always_comb begin + mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_data_from_strg_lifted = memory_0_data_out_p1; +end +assign config_data_in_shrt = config_data_in[15:0]; +assign config_data_out[0] = 32'(config_data_out_shrt[0]); +assign config_seq_clk_en = clk_en | (|config_en); +assign memory_0_clk_en = clk_en | (|config_en); +assign {mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_starting_addr, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_starting_addr2, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides2_0, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides2_1, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_0, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_1, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_2, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_3, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_dimensionality, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_dimensionality2, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges2_0, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges2_1, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_0, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_1, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_2, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_3, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_enable, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_enable2, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_starting_addr, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_starting_addr2, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides2_0, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides2_1, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_0, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_1, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_2, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_3, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_starting_addr, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_starting_addr2, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides2_0, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides2_1, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_0, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_1, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_2, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_3, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_dimensionality, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_dimensionality2, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges2_0, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges2_1, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_0, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_1, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_2, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_3, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_enable, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_enable2, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_starting_addr, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_starting_addr2, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides2_0, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides2_1, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_0, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_1, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_2, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_3} = CONFIG_SPACE[541:0]; +assign CONFIG_SPACE[31:0] = CONFIG_SPACE_0; +assign CONFIG_SPACE[63:32] = CONFIG_SPACE_1; +assign CONFIG_SPACE[95:64] = CONFIG_SPACE_2; +assign CONFIG_SPACE[127:96] = CONFIG_SPACE_3; +assign CONFIG_SPACE[159:128] = CONFIG_SPACE_4; +assign CONFIG_SPACE[191:160] = CONFIG_SPACE_5; +assign CONFIG_SPACE[223:192] = CONFIG_SPACE_6; +assign CONFIG_SPACE[255:224] = CONFIG_SPACE_7; +assign CONFIG_SPACE[287:256] = CONFIG_SPACE_8; +assign CONFIG_SPACE[319:288] = CONFIG_SPACE_9; +assign CONFIG_SPACE[351:320] = CONFIG_SPACE_10; +assign CONFIG_SPACE[383:352] = CONFIG_SPACE_11; +assign CONFIG_SPACE[415:384] = CONFIG_SPACE_12; +assign CONFIG_SPACE[447:416] = CONFIG_SPACE_13; +assign CONFIG_SPACE[479:448] = CONFIG_SPACE_14; +assign CONFIG_SPACE[511:480] = CONFIG_SPACE_15; +assign CONFIG_SPACE[541:512] = CONFIG_SPACE_16; +strg_ub_thin_PondTop_flat mem_ctrl_strg_ub_thin_PondTop_flat ( + .clk(mem_ctrl_strg_ub_thin_PondTop_flat_clk), + .clk_en(clk_en), + .data_in_f_0(PondTop_input_width_17_num_0), + .data_in_f_1(PondTop_input_width_17_num_1), + .flush(flush), + .rst_n(rst_n), + .strg_ub_thin_PondTop_inst_data_from_strg_lifted(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_data_from_strg_lifted), + .strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_starting_addr(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_starting_addr), + .strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_starting_addr2(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_starting_addr2), + .strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides2_0(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides2_0), + .strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides2_1(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides2_1), + .strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_0(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_0), + .strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_1(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_1), + .strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_2(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_2), + .strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_3(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_3), + .strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_dimensionality(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_dimensionality), + .strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_dimensionality2(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_dimensionality2), + .strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges2_0(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges2_0), + .strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges2_1(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges2_1), + .strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_0(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_0), + .strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_1(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_1), + .strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_2(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_2), + .strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_3(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_3), + .strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_enable(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_enable), + .strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_enable2(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_enable2), + .strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_starting_addr(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_starting_addr), + .strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_starting_addr2(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_starting_addr2), + .strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides2_0(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides2_0), + .strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides2_1(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides2_1), + .strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_0(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_0), + .strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_1(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_1), + .strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_2(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_2), + .strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_3(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_3), + .strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_starting_addr(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_starting_addr), + .strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_starting_addr2(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_starting_addr2), + .strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides2_0(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides2_0), + .strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides2_1(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides2_1), + .strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_0(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_0), + .strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_1(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_1), + .strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_2(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_2), + .strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_3(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_3), + .strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_dimensionality(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_dimensionality), + .strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_dimensionality2(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_dimensionality2), + .strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges2_0(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges2_0), + .strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges2_1(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges2_1), + .strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_0(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_0), + .strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_1(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_1), + .strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_2(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_2), + .strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_3(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_3), + .strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_enable(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_enable), + .strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_enable2(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_enable2), + .strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_starting_addr(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_starting_addr), + .strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_starting_addr2(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_starting_addr2), + .strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides2_0(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides2_0), + .strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides2_1(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides2_1), + .strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_0(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_0), + .strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_1(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_1), + .strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_2(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_2), + .strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_3(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_3), + .data_out_f_0(mem_ctrl_strg_ub_thin_PondTop_flat_data_out_f_0), + .data_out_f_1(mem_ctrl_strg_ub_thin_PondTop_flat_data_out_f_1), + .strg_ub_thin_PondTop_inst_data_to_strg_lifted(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_data_to_strg_lifted), + .strg_ub_thin_PondTop_inst_rd_addr_out_lifted(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_rd_addr_out_lifted), + .strg_ub_thin_PondTop_inst_ren_to_strg_lifted(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_ren_to_strg_lifted), + .strg_ub_thin_PondTop_inst_tmp0_rdaddr_lifted(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_tmp0_rdaddr_lifted), + .strg_ub_thin_PondTop_inst_tmp0_rden_lifted(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_tmp0_rden_lifted), + .strg_ub_thin_PondTop_inst_wen_to_strg_lifted(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_wen_to_strg_lifted), + .strg_ub_thin_PondTop_inst_wr_addr_out_lifted(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_wr_addr_out_lifted), + .valid_out_f_b_0(mem_ctrl_strg_ub_thin_PondTop_flat_valid_out_f_b_0), + .valid_out_f_b_1(mem_ctrl_strg_ub_thin_PondTop_flat_valid_out_f_b_1) +); + +sram_dp__0 memory_0 ( + .clk(gclk), + .clk_en(memory_0_clk_en), + .data_in_p0(memory_0_data_in_p0), + .flush(flush), + .read_addr_p0(memory_0_read_addr_p0), + .read_addr_p1(memory_0_read_addr_p1), + .read_enable_p0(memory_0_read_enable_p0), + .read_enable_p1(memory_0_read_enable_p1), + .write_addr_p0(memory_0_write_addr_p0), + .write_enable_p0(memory_0_write_enable_p0), + .data_out_p0(memory_0_data_out_p0), + .data_out_p1(memory_0_data_out_p1) +); + +storage_config_seq_1_16_16 config_seq ( + .clk(gclk), + .clk_en(config_seq_clk_en), + .config_addr_in(config_addr_in), + .config_data_in(config_data_in_shrt), + .config_en(config_en), + .config_rd(config_read), + .config_wr(config_write), + .flush(flush), + .rd_data_stg(config_seq_rd_data_stg), + .rst_n(rst_n), + .addr_out(config_seq_addr_out), + .rd_data_out(config_data_out_shrt), + .ren_out(config_seq_ren_out), + .wen_out(config_seq_wen_out), + .wr_data(config_seq_wr_data) +); + +endmodule // PondTop + +module PondTop_W ( + input logic [31:0] CONFIG_SPACE_0, + input logic [31:0] CONFIG_SPACE_1, + input logic [31:0] CONFIG_SPACE_10, + input logic [31:0] CONFIG_SPACE_11, + input logic [31:0] CONFIG_SPACE_12, + input logic [31:0] CONFIG_SPACE_13, + input logic [31:0] CONFIG_SPACE_14, + input logic [31:0] CONFIG_SPACE_15, + input logic [29:0] CONFIG_SPACE_16, + input logic [31:0] CONFIG_SPACE_2, + input logic [31:0] CONFIG_SPACE_3, + input logic [31:0] CONFIG_SPACE_4, + input logic [31:0] CONFIG_SPACE_5, + input logic [31:0] CONFIG_SPACE_6, + input logic [31:0] CONFIG_SPACE_7, + input logic [31:0] CONFIG_SPACE_8, + input logic [31:0] CONFIG_SPACE_9, + input logic [0:0] [16:0] PondTop_input_width_17_num_0, + input logic [0:0] [16:0] PondTop_input_width_17_num_1, + input logic clk, + input logic clk_en, + input logic [7:0] config_addr_in, + input logic [31:0] config_data_in, + input logic config_en, + input logic config_read, + input logic config_write, + input logic flush, + input logic rst_n, + input logic tile_en, + output logic [0:0] [16:0] PondTop_output_width_17_num_0, + output logic [0:0] [16:0] PondTop_output_width_17_num_1, + output logic PondTop_output_width_1_num_0, + output logic PondTop_output_width_1_num_1, + output logic [0:0] [31:0] config_data_out +); + +PondTop PondTop ( + .CONFIG_SPACE_0(CONFIG_SPACE_0), + .CONFIG_SPACE_1(CONFIG_SPACE_1), + .CONFIG_SPACE_10(CONFIG_SPACE_10), + .CONFIG_SPACE_11(CONFIG_SPACE_11), + .CONFIG_SPACE_12(CONFIG_SPACE_12), + .CONFIG_SPACE_13(CONFIG_SPACE_13), + .CONFIG_SPACE_14(CONFIG_SPACE_14), + .CONFIG_SPACE_15(CONFIG_SPACE_15), + .CONFIG_SPACE_16(CONFIG_SPACE_16), + .CONFIG_SPACE_2(CONFIG_SPACE_2), + .CONFIG_SPACE_3(CONFIG_SPACE_3), + .CONFIG_SPACE_4(CONFIG_SPACE_4), + .CONFIG_SPACE_5(CONFIG_SPACE_5), + .CONFIG_SPACE_6(CONFIG_SPACE_6), + .CONFIG_SPACE_7(CONFIG_SPACE_7), + .CONFIG_SPACE_8(CONFIG_SPACE_8), + .CONFIG_SPACE_9(CONFIG_SPACE_9), + .PondTop_input_width_17_num_0(PondTop_input_width_17_num_0), + .PondTop_input_width_17_num_1(PondTop_input_width_17_num_1), + .clk(clk), + .clk_en(clk_en), + .config_addr_in(config_addr_in), + .config_data_in(config_data_in), + .config_en(config_en), + .config_read(config_read), + .config_write(config_write), + .flush(flush), + .rst_n(rst_n), + .tile_en(tile_en), + .PondTop_output_width_17_num_0(PondTop_output_width_17_num_0), + .PondTop_output_width_17_num_1(PondTop_output_width_17_num_1), + .PondTop_output_width_1_num_0(PondTop_output_width_1_num_0), + .PondTop_output_width_1_num_1(PondTop_output_width_1_num_1), + .config_data_out(config_data_out) +); + +endmodule // PondTop_W + +module addr_gen_4_16_dual_config_2 ( + input logic clk, + input logic clk_en, + input logic flush, + input logic [2:0] mux_sel, + input logic mux_sel_msb_init, + input logic restart, + input logic rst_n, + input logic [15:0] starting_addr, + input logic [15:0] starting_addr2, + input logic step, + input logic [3:0] [15:0] strides, + input logic [1:0] [15:0] strides2, + output logic [15:0] addr_out, + output logic starting_addr_comp +); + +logic [15:0] calc_addr; +logic [15:0] cur_stride; +logic [15:0] current_addr; +logic [15:0] flush_addr; +logic [1:0] mux_sel_iter1; +logic mux_sel_iter2; +logic mux_sel_msb; +logic [15:0] restart_addr; +logic [15:0] strt_addr; +assign starting_addr_comp = starting_addr2 < starting_addr; +assign mux_sel_iter1 = mux_sel[1:0]; +assign mux_sel_iter2 = mux_sel[0]; +assign mux_sel_msb = mux_sel[2]; +assign flush_addr = mux_sel_msb_init ? starting_addr2: starting_addr; +assign strt_addr = mux_sel_msb ? starting_addr2: starting_addr; +assign restart_addr = (~mux_sel_msb) ? starting_addr2: starting_addr; +assign cur_stride = mux_sel_msb ? strides2[mux_sel_iter2]: strides[mux_sel_iter1]; +assign addr_out = calc_addr; +assign calc_addr = current_addr; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + current_addr <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + current_addr <= flush_addr; + end + else if (step) begin + if (restart) begin + current_addr <= restart_addr; + end + else current_addr <= current_addr + cur_stride; + end + end +end +endmodule // addr_gen_4_16_dual_config_2 + +module addr_gen_4_5_dual_config_2 ( + input logic clk, + input logic clk_en, + input logic flush, + input logic [2:0] mux_sel, + input logic mux_sel_msb_init, + input logic restart, + input logic rst_n, + input logic [4:0] starting_addr, + input logic [4:0] starting_addr2, + input logic step, + input logic [3:0] [4:0] strides, + input logic [1:0] [4:0] strides2, + output logic [4:0] addr_out, + output logic starting_addr_comp +); + +logic [4:0] calc_addr; +logic [4:0] cur_stride; +logic [4:0] current_addr; +logic [4:0] flush_addr; +logic [1:0] mux_sel_iter1; +logic mux_sel_iter2; +logic mux_sel_msb; +logic [4:0] restart_addr; +logic [4:0] strt_addr; +assign starting_addr_comp = starting_addr2 < starting_addr; +assign mux_sel_iter1 = mux_sel[1:0]; +assign mux_sel_iter2 = mux_sel[0]; +assign mux_sel_msb = mux_sel[2]; +assign flush_addr = mux_sel_msb_init ? starting_addr2: starting_addr; +assign strt_addr = mux_sel_msb ? starting_addr2: starting_addr; +assign restart_addr = (~mux_sel_msb) ? starting_addr2: starting_addr; +assign cur_stride = mux_sel_msb ? strides2[mux_sel_iter2]: strides[mux_sel_iter1]; +assign addr_out = calc_addr; +assign calc_addr = current_addr; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + current_addr <= 5'h0; + end + else if (clk_en) begin + if (flush) begin + current_addr <= flush_addr; + end + else if (step) begin + if (restart) begin + current_addr <= restart_addr; + end + else current_addr <= current_addr + cur_stride; + end + end +end +endmodule // addr_gen_4_5_dual_config_2 + +module for_loop_dual_config_4_2_16 #( + parameter CONFIG_WIDTH = 5'h10, + parameter ITERATOR_SUPPORT = 3'h4, + parameter ITERATOR_SUPPORT2 = 2'h2 +) +( + input logic clk, + input logic clk_en, + input logic [2:0] dimensionality, + input logic [1:0] dimensionality2, + input logic flush, + input logic mux_sel_msb_init, + input logic [3:0] [15:0] ranges, + input logic [1:0] [15:0] ranges2, + input logic rst_n, + input logic step, + output logic [2:0] mux_sel_out, + output logic restart +); + +logic [3:0] clear; +logic [2:0] cur_dimensionality; +logic [15:0] cur_range; +logic [3:0][15:0] dim_counter; +logic done; +logic [3:0] inc; +logic [15:0] inced_cnt; +logic [3:0] max_value; +logic maxed_value; +logic [1:0] mux_sel; +logic [1:0] mux_sel_iter1; +logic mux_sel_iter2; +logic mux_sel_msb; +logic mux_sel_msb_r; +assign mux_sel_msb = mux_sel_msb_r; +assign cur_dimensionality = mux_sel_msb ? 3'(dimensionality2): dimensionality; +assign mux_sel_iter1 = mux_sel[1:0]; +assign mux_sel_iter2 = mux_sel[0]; +assign mux_sel_out = {mux_sel_msb, mux_sel}; +assign inced_cnt = dim_counter[mux_sel] + 16'h1; +assign cur_range = mux_sel_msb ? ranges2[mux_sel_iter2]: ranges[mux_sel_iter1]; +assign maxed_value = (dim_counter[mux_sel] == cur_range) & inc[mux_sel]; +always_comb begin + mux_sel = 2'h0; + done = 1'h0; + if (~done) begin + if ((~max_value[0]) & (cur_dimensionality > 3'h0)) begin + mux_sel = 2'h0; + done = 1'h1; + end + end + if (~done) begin + if ((~max_value[1]) & (cur_dimensionality > 3'h1)) begin + mux_sel = 2'h1; + done = 1'h1; + end + end + if (~done) begin + if ((~max_value[2]) & (cur_dimensionality > 3'h2)) begin + mux_sel = 2'h2; + done = 1'h1; + end + end + if (~done) begin + if ((~max_value[3]) & (cur_dimensionality > 3'h3)) begin + mux_sel = 2'h3; + done = 1'h1; + end + end +end +always_comb begin + clear[0] = 1'h0; + if (((mux_sel > 2'h0) | (~done)) & step) begin + clear[0] = 1'h1; + end +end +always_comb begin + inc[0] = 1'h0; + if ((5'h0 == 5'h0) & step & (cur_dimensionality > 3'h0)) begin + inc[0] = 1'h1; + end + else if ((mux_sel == 2'h0) & step & (cur_dimensionality > 3'h0)) begin + inc[0] = 1'h1; + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + dim_counter[0] <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + dim_counter[0] <= 16'h0; + end + else if (clear[0]) begin + dim_counter[0] <= 16'h0; + end + else if (inc[0]) begin + dim_counter[0] <= inced_cnt; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + max_value[0] <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + max_value[0] <= 1'h0; + end + else if (clear[0]) begin + max_value[0] <= 1'h0; + end + else if (inc[0]) begin + max_value[0] <= maxed_value; + end + end +end +always_comb begin + clear[1] = 1'h0; + if (((mux_sel > 2'h1) | (~done)) & step) begin + clear[1] = 1'h1; + end +end +always_comb begin + inc[1] = 1'h0; + if ((5'h1 == 5'h0) & step & (cur_dimensionality > 3'h1)) begin + inc[1] = 1'h1; + end + else if ((mux_sel == 2'h1) & step & (cur_dimensionality > 3'h1)) begin + inc[1] = 1'h1; + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + dim_counter[1] <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + dim_counter[1] <= 16'h0; + end + else if (clear[1]) begin + dim_counter[1] <= 16'h0; + end + else if (inc[1]) begin + dim_counter[1] <= inced_cnt; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + max_value[1] <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + max_value[1] <= 1'h0; + end + else if (clear[1]) begin + max_value[1] <= 1'h0; + end + else if (inc[1]) begin + max_value[1] <= maxed_value; + end + end +end +always_comb begin + clear[2] = 1'h0; + if (((mux_sel > 2'h2) | (~done)) & step) begin + clear[2] = 1'h1; + end +end +always_comb begin + inc[2] = 1'h0; + if ((5'h2 == 5'h0) & step & (cur_dimensionality > 3'h2)) begin + inc[2] = 1'h1; + end + else if ((mux_sel == 2'h2) & step & (cur_dimensionality > 3'h2)) begin + inc[2] = 1'h1; + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + dim_counter[2] <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + dim_counter[2] <= 16'h0; + end + else if (clear[2]) begin + dim_counter[2] <= 16'h0; + end + else if (inc[2]) begin + dim_counter[2] <= inced_cnt; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + max_value[2] <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + max_value[2] <= 1'h0; + end + else if (clear[2]) begin + max_value[2] <= 1'h0; + end + else if (inc[2]) begin + max_value[2] <= maxed_value; + end + end +end +always_comb begin + clear[3] = 1'h0; + if (((mux_sel > 2'h3) | (~done)) & step) begin + clear[3] = 1'h1; + end +end +always_comb begin + inc[3] = 1'h0; + if ((5'h3 == 5'h0) & step & (cur_dimensionality > 3'h3)) begin + inc[3] = 1'h1; + end + else if ((mux_sel == 2'h3) & step & (cur_dimensionality > 3'h3)) begin + inc[3] = 1'h1; + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + dim_counter[3] <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + dim_counter[3] <= 16'h0; + end + else if (clear[3]) begin + dim_counter[3] <= 16'h0; + end + else if (inc[3]) begin + dim_counter[3] <= inced_cnt; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + max_value[3] <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + max_value[3] <= 1'h0; + end + else if (clear[3]) begin + max_value[3] <= 1'h0; + end + else if (inc[3]) begin + max_value[3] <= maxed_value; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + mux_sel_msb_r <= 1'h0; + end + else if (clk_en) begin + if (flush) begin + mux_sel_msb_r <= mux_sel_msb_init; + end + else if (restart) begin + mux_sel_msb_r <= ~mux_sel_msb_r; + end + end +end +assign restart = step & (~done); +endmodule // for_loop_dual_config_4_2_16 + +module sched_gen_4_16_dual_config_2 ( + input logic clk, + input logic clk_en, + input logic [15:0] cycle_count, + input logic enable, + input logic enable2, + input logic finished, + input logic flush, + input logic [2:0] mux_sel, + input logic rst_n, + input logic [15:0] sched_addr_gen_starting_addr, + input logic [15:0] sched_addr_gen_starting_addr2, + input logic [15:0] sched_addr_gen_strides2_0, + input logic [15:0] sched_addr_gen_strides2_1, + input logic [15:0] sched_addr_gen_strides_0, + input logic [15:0] sched_addr_gen_strides_1, + input logic [15:0] sched_addr_gen_strides_2, + input logic [15:0] sched_addr_gen_strides_3, + output logic mux_sel_msb_init, + output logic valid_output +); + +logic [15:0] addr_out; +logic cur_enable; +logic cur_valid_gate; +logic mux_sel_msb_init_w; +logic sched_addr_gen_starting_addr_comp; +logic [3:0][15:0] sched_addr_gen_strides; +logic [1:0][15:0] sched_addr_gen_strides2; +logic [1:0] valid_gate; +logic [1:0] valid_gate_inv; +logic valid_out; +assign cur_valid_gate = valid_gate[mux_sel[2]]; +assign valid_gate = ~valid_gate_inv; +assign cur_enable = mux_sel[2] ? enable2: enable; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + valid_gate_inv <= 2'h0; + end + else if (clk_en) begin + if (flush) begin + valid_gate_inv <= 2'h0; + end + else if (finished) begin + valid_gate_inv[mux_sel[2]] <= 1'h1; + end + end +end +always_comb begin + if (enable & enable2) begin + mux_sel_msb_init_w = sched_addr_gen_starting_addr_comp; + end + else if (enable & (~enable2)) begin + mux_sel_msb_init_w = 1'h0; + end + else if ((~enable) & enable2) begin + mux_sel_msb_init_w = 1'h1; + end + else mux_sel_msb_init_w = 1'h0; +end +assign mux_sel_msb_init = mux_sel_msb_init_w; +always_comb begin + valid_out = (cycle_count == addr_out) & cur_valid_gate & cur_enable; +end +always_comb begin + valid_output = valid_out; +end +assign sched_addr_gen_strides2[0] = sched_addr_gen_strides2_0; +assign sched_addr_gen_strides2[1] = sched_addr_gen_strides2_1; +assign sched_addr_gen_strides[0] = sched_addr_gen_strides_0; +assign sched_addr_gen_strides[1] = sched_addr_gen_strides_1; +assign sched_addr_gen_strides[2] = sched_addr_gen_strides_2; +assign sched_addr_gen_strides[3] = sched_addr_gen_strides_3; +addr_gen_4_16_dual_config_2 sched_addr_gen ( + .clk(clk), + .clk_en(clk_en), + .flush(flush), + .mux_sel(mux_sel), + .mux_sel_msb_init(mux_sel_msb_init_w), + .restart(finished), + .rst_n(rst_n), + .starting_addr(sched_addr_gen_starting_addr), + .starting_addr2(sched_addr_gen_starting_addr2), + .step(valid_out), + .strides(sched_addr_gen_strides), + .strides2(sched_addr_gen_strides2), + .addr_out(addr_out), + .starting_addr_comp(sched_addr_gen_starting_addr_comp) +); + +endmodule // sched_gen_4_16_dual_config_2 + +module sram_dp__0 ( + input logic clk, + input logic clk_en, + input logic [15:0] data_in_p0, + input logic flush, + input logic [4:0] read_addr_p0, + input logic [4:0] read_addr_p1, + input logic read_enable_p0, + input logic read_enable_p1, + input logic [4:0] write_addr_p0, + input logic write_enable_p0, + output logic [15:0] data_out_p0, + output logic [15:0] data_out_p1 +); + +logic [15:0] data_array [31:0]; + +always_ff @(posedge clk) begin + if (clk_en) begin + if (write_enable_p0 == 1'h1) begin + data_array[write_addr_p0] <= data_in_p0; + end + end +end +assign data_out_p0 = data_array[read_addr_p0]; +always_comb begin + data_out_p1 = data_array[read_addr_p1]; +end +endmodule // sram_dp__0 + +module storage_config_seq_1_16_16 ( + input logic clk, + input logic clk_en, + input logic [7:0] config_addr_in, + input logic [15:0] config_data_in, + input logic config_en, + input logic config_rd, + input logic config_wr, + input logic flush, + input logic [0:0][0:0] [15:0] rd_data_stg, + input logic rst_n, + output logic [4:0] addr_out, + output logic [0:0] [15:0] rd_data_out, + output logic ren_out, + output logic wen_out, + output logic [0:0] [15:0] wr_data +); + +assign addr_out = config_addr_in[4:0]; +assign wr_data[0] = config_data_in; +assign rd_data_out[0] = rd_data_stg[0]; +assign wen_out = config_wr; +assign ren_out = config_rd; +endmodule // storage_config_seq_1_16_16 + +module strg_ub_thin_PondTop ( + input logic clk, + input logic clk_en, + input logic [15:0] data_from_strg, + input logic [1:0] [16:0] data_in, + input logic flush, + input logic [4:0] in2regfile_0_addr_gen_starting_addr, + input logic [4:0] in2regfile_0_addr_gen_starting_addr2, + input logic [4:0] in2regfile_0_addr_gen_strides2_0, + input logic [4:0] in2regfile_0_addr_gen_strides2_1, + input logic [4:0] in2regfile_0_addr_gen_strides_0, + input logic [4:0] in2regfile_0_addr_gen_strides_1, + input logic [4:0] in2regfile_0_addr_gen_strides_2, + input logic [4:0] in2regfile_0_addr_gen_strides_3, + input logic [2:0] in2regfile_0_for_loop_dimensionality, + input logic [1:0] in2regfile_0_for_loop_dimensionality2, + input logic [15:0] in2regfile_0_for_loop_ranges2_0, + input logic [15:0] in2regfile_0_for_loop_ranges2_1, + input logic [15:0] in2regfile_0_for_loop_ranges_0, + input logic [15:0] in2regfile_0_for_loop_ranges_1, + input logic [15:0] in2regfile_0_for_loop_ranges_2, + input logic [15:0] in2regfile_0_for_loop_ranges_3, + input logic in2regfile_0_sched_gen_enable, + input logic in2regfile_0_sched_gen_enable2, + input logic [15:0] in2regfile_0_sched_gen_sched_addr_gen_starting_addr, + input logic [15:0] in2regfile_0_sched_gen_sched_addr_gen_starting_addr2, + input logic [15:0] in2regfile_0_sched_gen_sched_addr_gen_strides2_0, + input logic [15:0] in2regfile_0_sched_gen_sched_addr_gen_strides2_1, + input logic [15:0] in2regfile_0_sched_gen_sched_addr_gen_strides_0, + input logic [15:0] in2regfile_0_sched_gen_sched_addr_gen_strides_1, + input logic [15:0] in2regfile_0_sched_gen_sched_addr_gen_strides_2, + input logic [15:0] in2regfile_0_sched_gen_sched_addr_gen_strides_3, + input logic [4:0] regfile2out_0_addr_gen_starting_addr, + input logic [4:0] regfile2out_0_addr_gen_starting_addr2, + input logic [4:0] regfile2out_0_addr_gen_strides2_0, + input logic [4:0] regfile2out_0_addr_gen_strides2_1, + input logic [4:0] regfile2out_0_addr_gen_strides_0, + input logic [4:0] regfile2out_0_addr_gen_strides_1, + input logic [4:0] regfile2out_0_addr_gen_strides_2, + input logic [4:0] regfile2out_0_addr_gen_strides_3, + input logic [2:0] regfile2out_0_for_loop_dimensionality, + input logic [1:0] regfile2out_0_for_loop_dimensionality2, + input logic [15:0] regfile2out_0_for_loop_ranges2_0, + input logic [15:0] regfile2out_0_for_loop_ranges2_1, + input logic [15:0] regfile2out_0_for_loop_ranges_0, + input logic [15:0] regfile2out_0_for_loop_ranges_1, + input logic [15:0] regfile2out_0_for_loop_ranges_2, + input logic [15:0] regfile2out_0_for_loop_ranges_3, + input logic regfile2out_0_sched_gen_enable, + input logic regfile2out_0_sched_gen_enable2, + input logic [15:0] regfile2out_0_sched_gen_sched_addr_gen_starting_addr, + input logic [15:0] regfile2out_0_sched_gen_sched_addr_gen_starting_addr2, + input logic [15:0] regfile2out_0_sched_gen_sched_addr_gen_strides2_0, + input logic [15:0] regfile2out_0_sched_gen_sched_addr_gen_strides2_1, + input logic [15:0] regfile2out_0_sched_gen_sched_addr_gen_strides_0, + input logic [15:0] regfile2out_0_sched_gen_sched_addr_gen_strides_1, + input logic [15:0] regfile2out_0_sched_gen_sched_addr_gen_strides_2, + input logic [15:0] regfile2out_0_sched_gen_sched_addr_gen_strides_3, + input logic rst_n, + output logic [1:0] [16:0] data_out, + output logic [15:0] data_to_strg, + output logic [4:0] rd_addr_out, + output logic ren_to_strg, + output logic [4:0] tmp0_rdaddr, + output logic tmp0_rden, + output logic [1:0] valid_out, + output logic wen_to_strg, + output logic [4:0] wr_addr_out +); + +logic [15:0] cycle_count; +logic [1:0][15:0] data_in_thin; +logic [1:0][15:0] data_out_int; +logic [1:0][15:0] data_out_int_thin; +logic in2regfile_0_addr_gen_mux_sel_msb_init; +logic [3:0][4:0] in2regfile_0_addr_gen_strides; +logic [1:0][4:0] in2regfile_0_addr_gen_strides2; +logic in2regfile_0_for_loop_mux_sel_msb_init; +logic [2:0] in2regfile_0_for_loop_mux_sel_out; +logic [3:0][15:0] in2regfile_0_for_loop_ranges; +logic [1:0][15:0] in2regfile_0_for_loop_ranges2; +logic in2regfile_0_for_loop_restart; +logic in2regfile_0_sched_gen_mux_sel_msb_init; +logic in2regfile_0_sched_gen_valid_output; +logic read; +logic [4:0] read_addr; +logic read_mux_sel_msb; +logic regfile2out_0_addr_gen_mux_sel_msb_init; +logic [3:0][4:0] regfile2out_0_addr_gen_strides; +logic [1:0][4:0] regfile2out_0_addr_gen_strides2; +logic regfile2out_0_for_loop_mux_sel_msb_init; +logic [2:0] regfile2out_0_for_loop_mux_sel_out; +logic [3:0][15:0] regfile2out_0_for_loop_ranges; +logic [1:0][15:0] regfile2out_0_for_loop_ranges2; +logic regfile2out_0_for_loop_restart; +logic regfile2out_0_sched_gen_mux_sel_msb_init; +logic regfile2out_0_sched_gen_valid_output; +logic [1:0] valid_out_int; +logic write; +logic [4:0] write_addr; +logic write_mux_sel_msb; +assign data_in_thin[0] = data_in[0][15:0]; +assign data_in_thin[1] = data_in[1][15:0]; + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + cycle_count <= 16'h0; + end + else if (clk_en) begin + if (flush) begin + cycle_count <= 16'h0; + end + else cycle_count <= cycle_count + 16'h1; + end +end +assign valid_out_int[0] = read & (~read_mux_sel_msb); +assign valid_out_int[1] = read & read_mux_sel_msb; +assign data_out_int_thin = data_out_int; +assign data_out[0][15:0] = data_out_int_thin[0]; +assign data_out[0][16] = 1'h0; +assign data_out[1][15:0] = data_out_int_thin[1]; +assign data_out[1][16] = 1'h0; +assign valid_out = valid_out_int; +assign write = in2regfile_0_sched_gen_valid_output; +assign in2regfile_0_for_loop_mux_sel_msb_init = in2regfile_0_sched_gen_mux_sel_msb_init; +assign in2regfile_0_addr_gen_mux_sel_msb_init = in2regfile_0_sched_gen_mux_sel_msb_init; +assign write_mux_sel_msb = in2regfile_0_for_loop_mux_sel_out[2]; +assign read = regfile2out_0_sched_gen_valid_output; +assign regfile2out_0_for_loop_mux_sel_msb_init = regfile2out_0_sched_gen_mux_sel_msb_init; +assign regfile2out_0_addr_gen_mux_sel_msb_init = regfile2out_0_sched_gen_mux_sel_msb_init; +assign read_mux_sel_msb = regfile2out_0_for_loop_mux_sel_out[2]; +assign wen_to_strg = |write; +assign ren_to_strg = |read; +assign data_out_int[0] = data_from_strg; +assign data_out_int[1] = data_from_strg; +assign wr_addr_out = write_addr[4:0]; +assign data_to_strg = data_in_thin[write_mux_sel_msb]; +assign rd_addr_out = read_addr[4:0]; +assign tmp0_rdaddr = 5'h0; +assign tmp0_rden = 1'h0; +assign in2regfile_0_for_loop_ranges[0] = in2regfile_0_for_loop_ranges_0; +assign in2regfile_0_for_loop_ranges[1] = in2regfile_0_for_loop_ranges_1; +assign in2regfile_0_for_loop_ranges[2] = in2regfile_0_for_loop_ranges_2; +assign in2regfile_0_for_loop_ranges[3] = in2regfile_0_for_loop_ranges_3; +assign in2regfile_0_for_loop_ranges2[0] = in2regfile_0_for_loop_ranges2_0; +assign in2regfile_0_for_loop_ranges2[1] = in2regfile_0_for_loop_ranges2_1; +assign in2regfile_0_addr_gen_strides2[0] = in2regfile_0_addr_gen_strides2_0; +assign in2regfile_0_addr_gen_strides2[1] = in2regfile_0_addr_gen_strides2_1; +assign in2regfile_0_addr_gen_strides[0] = in2regfile_0_addr_gen_strides_0; +assign in2regfile_0_addr_gen_strides[1] = in2regfile_0_addr_gen_strides_1; +assign in2regfile_0_addr_gen_strides[2] = in2regfile_0_addr_gen_strides_2; +assign in2regfile_0_addr_gen_strides[3] = in2regfile_0_addr_gen_strides_3; +assign regfile2out_0_for_loop_ranges[0] = regfile2out_0_for_loop_ranges_0; +assign regfile2out_0_for_loop_ranges[1] = regfile2out_0_for_loop_ranges_1; +assign regfile2out_0_for_loop_ranges[2] = regfile2out_0_for_loop_ranges_2; +assign regfile2out_0_for_loop_ranges[3] = regfile2out_0_for_loop_ranges_3; +assign regfile2out_0_for_loop_ranges2[0] = regfile2out_0_for_loop_ranges2_0; +assign regfile2out_0_for_loop_ranges2[1] = regfile2out_0_for_loop_ranges2_1; +assign regfile2out_0_addr_gen_strides2[0] = regfile2out_0_addr_gen_strides2_0; +assign regfile2out_0_addr_gen_strides2[1] = regfile2out_0_addr_gen_strides2_1; +assign regfile2out_0_addr_gen_strides[0] = regfile2out_0_addr_gen_strides_0; +assign regfile2out_0_addr_gen_strides[1] = regfile2out_0_addr_gen_strides_1; +assign regfile2out_0_addr_gen_strides[2] = regfile2out_0_addr_gen_strides_2; +assign regfile2out_0_addr_gen_strides[3] = regfile2out_0_addr_gen_strides_3; +for_loop_dual_config_4_2_16 in2regfile_0_for_loop ( + .clk(clk), + .clk_en(clk_en), + .dimensionality(in2regfile_0_for_loop_dimensionality), + .dimensionality2(in2regfile_0_for_loop_dimensionality2), + .flush(flush), + .mux_sel_msb_init(in2regfile_0_for_loop_mux_sel_msb_init), + .ranges(in2regfile_0_for_loop_ranges), + .ranges2(in2regfile_0_for_loop_ranges2), + .rst_n(rst_n), + .step(write), + .mux_sel_out(in2regfile_0_for_loop_mux_sel_out), + .restart(in2regfile_0_for_loop_restart) +); + +addr_gen_4_5_dual_config_2 in2regfile_0_addr_gen ( + .clk(clk), + .clk_en(clk_en), + .flush(flush), + .mux_sel(in2regfile_0_for_loop_mux_sel_out), + .mux_sel_msb_init(in2regfile_0_addr_gen_mux_sel_msb_init), + .restart(in2regfile_0_for_loop_restart), + .rst_n(rst_n), + .starting_addr(in2regfile_0_addr_gen_starting_addr), + .starting_addr2(in2regfile_0_addr_gen_starting_addr2), + .step(write), + .strides(in2regfile_0_addr_gen_strides), + .strides2(in2regfile_0_addr_gen_strides2), + .addr_out(write_addr) +); + +sched_gen_4_16_dual_config_2 in2regfile_0_sched_gen ( + .clk(clk), + .clk_en(clk_en), + .cycle_count(cycle_count), + .enable(in2regfile_0_sched_gen_enable), + .enable2(in2regfile_0_sched_gen_enable2), + .finished(in2regfile_0_for_loop_restart), + .flush(flush), + .mux_sel(in2regfile_0_for_loop_mux_sel_out), + .rst_n(rst_n), + .sched_addr_gen_starting_addr(in2regfile_0_sched_gen_sched_addr_gen_starting_addr), + .sched_addr_gen_starting_addr2(in2regfile_0_sched_gen_sched_addr_gen_starting_addr2), + .sched_addr_gen_strides2_0(in2regfile_0_sched_gen_sched_addr_gen_strides2_0), + .sched_addr_gen_strides2_1(in2regfile_0_sched_gen_sched_addr_gen_strides2_1), + .sched_addr_gen_strides_0(in2regfile_0_sched_gen_sched_addr_gen_strides_0), + .sched_addr_gen_strides_1(in2regfile_0_sched_gen_sched_addr_gen_strides_1), + .sched_addr_gen_strides_2(in2regfile_0_sched_gen_sched_addr_gen_strides_2), + .sched_addr_gen_strides_3(in2regfile_0_sched_gen_sched_addr_gen_strides_3), + .mux_sel_msb_init(in2regfile_0_sched_gen_mux_sel_msb_init), + .valid_output(in2regfile_0_sched_gen_valid_output) +); + +for_loop_dual_config_4_2_16 regfile2out_0_for_loop ( + .clk(clk), + .clk_en(clk_en), + .dimensionality(regfile2out_0_for_loop_dimensionality), + .dimensionality2(regfile2out_0_for_loop_dimensionality2), + .flush(flush), + .mux_sel_msb_init(regfile2out_0_for_loop_mux_sel_msb_init), + .ranges(regfile2out_0_for_loop_ranges), + .ranges2(regfile2out_0_for_loop_ranges2), + .rst_n(rst_n), + .step(read), + .mux_sel_out(regfile2out_0_for_loop_mux_sel_out), + .restart(regfile2out_0_for_loop_restart) +); + +addr_gen_4_5_dual_config_2 regfile2out_0_addr_gen ( + .clk(clk), + .clk_en(clk_en), + .flush(flush), + .mux_sel(regfile2out_0_for_loop_mux_sel_out), + .mux_sel_msb_init(regfile2out_0_addr_gen_mux_sel_msb_init), + .restart(regfile2out_0_for_loop_restart), + .rst_n(rst_n), + .starting_addr(regfile2out_0_addr_gen_starting_addr), + .starting_addr2(regfile2out_0_addr_gen_starting_addr2), + .step(read), + .strides(regfile2out_0_addr_gen_strides), + .strides2(regfile2out_0_addr_gen_strides2), + .addr_out(read_addr) +); + +sched_gen_4_16_dual_config_2 regfile2out_0_sched_gen ( + .clk(clk), + .clk_en(clk_en), + .cycle_count(cycle_count), + .enable(regfile2out_0_sched_gen_enable), + .enable2(regfile2out_0_sched_gen_enable2), + .finished(regfile2out_0_for_loop_restart), + .flush(flush), + .mux_sel(regfile2out_0_for_loop_mux_sel_out), + .rst_n(rst_n), + .sched_addr_gen_starting_addr(regfile2out_0_sched_gen_sched_addr_gen_starting_addr), + .sched_addr_gen_starting_addr2(regfile2out_0_sched_gen_sched_addr_gen_starting_addr2), + .sched_addr_gen_strides2_0(regfile2out_0_sched_gen_sched_addr_gen_strides2_0), + .sched_addr_gen_strides2_1(regfile2out_0_sched_gen_sched_addr_gen_strides2_1), + .sched_addr_gen_strides_0(regfile2out_0_sched_gen_sched_addr_gen_strides_0), + .sched_addr_gen_strides_1(regfile2out_0_sched_gen_sched_addr_gen_strides_1), + .sched_addr_gen_strides_2(regfile2out_0_sched_gen_sched_addr_gen_strides_2), + .sched_addr_gen_strides_3(regfile2out_0_sched_gen_sched_addr_gen_strides_3), + .mux_sel_msb_init(regfile2out_0_sched_gen_mux_sel_msb_init), + .valid_output(regfile2out_0_sched_gen_valid_output) +); + +endmodule // strg_ub_thin_PondTop + +module strg_ub_thin_PondTop_flat ( + input logic clk, + input logic clk_en, + input logic [0:0] [16:0] data_in_f_0, + input logic [0:0] [16:0] data_in_f_1, + input logic flush, + input logic rst_n, + input logic [15:0] strg_ub_thin_PondTop_inst_data_from_strg_lifted, + input logic [4:0] strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_starting_addr, + input logic [4:0] strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_starting_addr2, + input logic [4:0] strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides2_0, + input logic [4:0] strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides2_1, + input logic [4:0] strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_0, + input logic [4:0] strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_1, + input logic [4:0] strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_2, + input logic [4:0] strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_3, + input logic [2:0] strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_dimensionality, + input logic [1:0] strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_dimensionality2, + input logic [15:0] strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges2_0, + input logic [15:0] strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges2_1, + input logic [15:0] strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_0, + input logic [15:0] strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_1, + input logic [15:0] strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_2, + input logic [15:0] strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_3, + input logic strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_enable, + input logic strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_enable2, + input logic [15:0] strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_starting_addr, + input logic [15:0] strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_starting_addr2, + input logic [15:0] strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides2_0, + input logic [15:0] strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides2_1, + input logic [15:0] strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_0, + input logic [15:0] strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_1, + input logic [15:0] strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_2, + input logic [15:0] strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_3, + input logic [4:0] strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_starting_addr, + input logic [4:0] strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_starting_addr2, + input logic [4:0] strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides2_0, + input logic [4:0] strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides2_1, + input logic [4:0] strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_0, + input logic [4:0] strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_1, + input logic [4:0] strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_2, + input logic [4:0] strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_3, + input logic [2:0] strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_dimensionality, + input logic [1:0] strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_dimensionality2, + input logic [15:0] strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges2_0, + input logic [15:0] strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges2_1, + input logic [15:0] strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_0, + input logic [15:0] strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_1, + input logic [15:0] strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_2, + input logic [15:0] strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_3, + input logic strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_enable, + input logic strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_enable2, + input logic [15:0] strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_starting_addr, + input logic [15:0] strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_starting_addr2, + input logic [15:0] strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides2_0, + input logic [15:0] strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides2_1, + input logic [15:0] strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_0, + input logic [15:0] strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_1, + input logic [15:0] strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_2, + input logic [15:0] strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_3, + output logic [0:0] [16:0] data_out_f_0, + output logic [0:0] [16:0] data_out_f_1, + output logic [15:0] strg_ub_thin_PondTop_inst_data_to_strg_lifted, + output logic [4:0] strg_ub_thin_PondTop_inst_rd_addr_out_lifted, + output logic strg_ub_thin_PondTop_inst_ren_to_strg_lifted, + output logic [4:0] strg_ub_thin_PondTop_inst_tmp0_rdaddr_lifted, + output logic strg_ub_thin_PondTop_inst_tmp0_rden_lifted, + output logic strg_ub_thin_PondTop_inst_wen_to_strg_lifted, + output logic [4:0] strg_ub_thin_PondTop_inst_wr_addr_out_lifted, + output logic valid_out_f_b_0, + output logic valid_out_f_b_1 +); + +logic [1:0][16:0] strg_ub_thin_PondTop_inst_data_in; +logic [1:0][16:0] strg_ub_thin_PondTop_inst_data_out; +logic [1:0] strg_ub_thin_PondTop_inst_valid_out; +assign strg_ub_thin_PondTop_inst_data_in[0] = data_in_f_0; +assign strg_ub_thin_PondTop_inst_data_in[1] = data_in_f_1; +assign valid_out_f_b_0 = strg_ub_thin_PondTop_inst_valid_out[0]; +assign valid_out_f_b_1 = strg_ub_thin_PondTop_inst_valid_out[1]; +assign data_out_f_0 = strg_ub_thin_PondTop_inst_data_out[0]; +assign data_out_f_1 = strg_ub_thin_PondTop_inst_data_out[1]; +strg_ub_thin_PondTop strg_ub_thin_PondTop_inst ( + .clk(clk), + .clk_en(clk_en), + .data_from_strg(strg_ub_thin_PondTop_inst_data_from_strg_lifted), + .data_in(strg_ub_thin_PondTop_inst_data_in), + .flush(flush), + .in2regfile_0_addr_gen_starting_addr(strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_starting_addr), + .in2regfile_0_addr_gen_starting_addr2(strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_starting_addr2), + .in2regfile_0_addr_gen_strides2_0(strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides2_0), + .in2regfile_0_addr_gen_strides2_1(strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides2_1), + .in2regfile_0_addr_gen_strides_0(strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_0), + .in2regfile_0_addr_gen_strides_1(strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_1), + .in2regfile_0_addr_gen_strides_2(strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_2), + .in2regfile_0_addr_gen_strides_3(strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_3), + .in2regfile_0_for_loop_dimensionality(strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_dimensionality), + .in2regfile_0_for_loop_dimensionality2(strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_dimensionality2), + .in2regfile_0_for_loop_ranges2_0(strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges2_0), + .in2regfile_0_for_loop_ranges2_1(strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges2_1), + .in2regfile_0_for_loop_ranges_0(strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_0), + .in2regfile_0_for_loop_ranges_1(strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_1), + .in2regfile_0_for_loop_ranges_2(strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_2), + .in2regfile_0_for_loop_ranges_3(strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_3), + .in2regfile_0_sched_gen_enable(strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_enable), + .in2regfile_0_sched_gen_enable2(strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_enable2), + .in2regfile_0_sched_gen_sched_addr_gen_starting_addr(strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_starting_addr), + .in2regfile_0_sched_gen_sched_addr_gen_starting_addr2(strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_starting_addr2), + .in2regfile_0_sched_gen_sched_addr_gen_strides2_0(strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides2_0), + .in2regfile_0_sched_gen_sched_addr_gen_strides2_1(strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides2_1), + .in2regfile_0_sched_gen_sched_addr_gen_strides_0(strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_0), + .in2regfile_0_sched_gen_sched_addr_gen_strides_1(strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_1), + .in2regfile_0_sched_gen_sched_addr_gen_strides_2(strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_2), + .in2regfile_0_sched_gen_sched_addr_gen_strides_3(strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_3), + .regfile2out_0_addr_gen_starting_addr(strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_starting_addr), + .regfile2out_0_addr_gen_starting_addr2(strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_starting_addr2), + .regfile2out_0_addr_gen_strides2_0(strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides2_0), + .regfile2out_0_addr_gen_strides2_1(strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides2_1), + .regfile2out_0_addr_gen_strides_0(strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_0), + .regfile2out_0_addr_gen_strides_1(strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_1), + .regfile2out_0_addr_gen_strides_2(strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_2), + .regfile2out_0_addr_gen_strides_3(strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_3), + .regfile2out_0_for_loop_dimensionality(strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_dimensionality), + .regfile2out_0_for_loop_dimensionality2(strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_dimensionality2), + .regfile2out_0_for_loop_ranges2_0(strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges2_0), + .regfile2out_0_for_loop_ranges2_1(strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges2_1), + .regfile2out_0_for_loop_ranges_0(strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_0), + .regfile2out_0_for_loop_ranges_1(strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_1), + .regfile2out_0_for_loop_ranges_2(strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_2), + .regfile2out_0_for_loop_ranges_3(strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_3), + .regfile2out_0_sched_gen_enable(strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_enable), + .regfile2out_0_sched_gen_enable2(strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_enable2), + .regfile2out_0_sched_gen_sched_addr_gen_starting_addr(strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_starting_addr), + .regfile2out_0_sched_gen_sched_addr_gen_starting_addr2(strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_starting_addr2), + .regfile2out_0_sched_gen_sched_addr_gen_strides2_0(strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides2_0), + .regfile2out_0_sched_gen_sched_addr_gen_strides2_1(strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides2_1), + .regfile2out_0_sched_gen_sched_addr_gen_strides_0(strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_0), + .regfile2out_0_sched_gen_sched_addr_gen_strides_1(strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_1), + .regfile2out_0_sched_gen_sched_addr_gen_strides_2(strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_2), + .regfile2out_0_sched_gen_sched_addr_gen_strides_3(strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_3), + .rst_n(rst_n), + .data_out(strg_ub_thin_PondTop_inst_data_out), + .data_to_strg(strg_ub_thin_PondTop_inst_data_to_strg_lifted), + .rd_addr_out(strg_ub_thin_PondTop_inst_rd_addr_out_lifted), + .ren_to_strg(strg_ub_thin_PondTop_inst_ren_to_strg_lifted), + .tmp0_rdaddr(strg_ub_thin_PondTop_inst_tmp0_rdaddr_lifted), + .tmp0_rden(strg_ub_thin_PondTop_inst_tmp0_rden_lifted), + .valid_out(strg_ub_thin_PondTop_inst_valid_out), + .wen_to_strg(strg_ub_thin_PondTop_inst_wen_to_strg_lifted), + .wr_addr_out(strg_ub_thin_PondTop_inst_wr_addr_out_lifted) +); + +endmodule // strg_ub_thin_PondTop_flat + diff --git a/sam/onyx/.magma/ReadyValidLoopBack-kratos.sv b/sam/onyx/.magma/ReadyValidLoopBack-kratos.sv new file mode 100644 index 00000000..5cb19020 --- /dev/null +++ b/sam/onyx/.magma/ReadyValidLoopBack-kratos.sv @@ -0,0 +1,9 @@ +module ReadyValidLoopBack ( + input logic ready_in, + input logic valid_in, + output logic valid_out +); + +assign valid_out = ready_in & valid_in; +endmodule // ReadyValidLoopBack + diff --git a/sam/onyx/.magma/SplitFifo_1-kratos.sv b/sam/onyx/.magma/SplitFifo_1-kratos.sv new file mode 100644 index 00000000..24d28540 --- /dev/null +++ b/sam/onyx/.magma/SplitFifo_1-kratos.sv @@ -0,0 +1,57 @@ +module SplitFifo_1 ( + input logic clk, + input logic clk_en, + input logic data_in, + input logic end_fifo, + input logic fifo_en, + input logic ready1, + input logic rst, + input logic start_fifo, + input logic valid0, + output logic data_out, + output logic ready0, + output logic valid1 +); + +logic empty; +logic empty_n; +logic ready_in; +logic valid_in; +logic value; +assign empty = ~empty_n; +assign ready_in = ready1 && (~start_fifo); +assign ready0 = fifo_en ? empty || ready_in: clk_en; +assign valid_in = valid0 && (~end_fifo); +assign valid1 = fifo_en ? (~empty) || valid_in: clk_en; +assign data_out = (empty && fifo_en) ? data_in: value; + +always_ff @(posedge clk, posedge rst) begin + if (rst) begin + value <= 1'h0; + end + else if (clk_en) begin + if ((~fifo_en) || (valid0 && ready0 && (~(empty && ready1 && valid1)))) begin + value <= data_in; + end + end +end + +always_ff @(posedge clk, posedge rst) begin + if (rst) begin + empty_n <= 1'h0; + end + else if (clk_en) begin + if (fifo_en) begin + if (valid1 && ready1) begin + if (~(valid0 && ready0)) begin + empty_n <= 1'h0; + end + end + else if (valid0 && ready0) begin + empty_n <= 1'h1; + end + end + end +end +endmodule // SplitFifo_1 + diff --git a/sam/onyx/.magma/SplitFifo_17-kratos.sv b/sam/onyx/.magma/SplitFifo_17-kratos.sv new file mode 100644 index 00000000..e204afd4 --- /dev/null +++ b/sam/onyx/.magma/SplitFifo_17-kratos.sv @@ -0,0 +1,57 @@ +module SplitFifo_17 ( + input logic clk, + input logic clk_en, + input logic [16:0] data_in, + input logic end_fifo, + input logic fifo_en, + input logic ready1, + input logic rst, + input logic start_fifo, + input logic valid0, + output logic [16:0] data_out, + output logic ready0, + output logic valid1 +); + +logic empty; +logic empty_n; +logic ready_in; +logic valid_in; +logic [16:0] value; +assign empty = ~empty_n; +assign ready_in = ready1 && (~start_fifo); +assign ready0 = fifo_en ? empty || ready_in: clk_en; +assign valid_in = valid0 && (~end_fifo); +assign valid1 = fifo_en ? (~empty) || valid_in: clk_en; +assign data_out = (empty && fifo_en) ? data_in: value; + +always_ff @(posedge clk, posedge rst) begin + if (rst) begin + value <= 17'h0; + end + else if (clk_en) begin + if ((~fifo_en) || (valid0 && ready0 && (~(empty && ready1 && valid1)))) begin + value <= data_in; + end + end +end + +always_ff @(posedge clk, posedge rst) begin + if (rst) begin + empty_n <= 1'h0; + end + else if (clk_en) begin + if (fifo_en) begin + if (valid1 && ready1) begin + if (~(valid0 && ready0)) begin + empty_n <= 1'h0; + end + end + else if (valid0 && ready0) begin + empty_n <= 1'h1; + end + end + end +end +endmodule // SplitFifo_17 + diff --git a/sam/onyx/.magma/io_core_W-kratos.sv b/sam/onyx/.magma/io_core_W-kratos.sv new file mode 100644 index 00000000..6b07ee15 --- /dev/null +++ b/sam/onyx/.magma/io_core_W-kratos.sv @@ -0,0 +1,376 @@ +module io_core ( + input logic clk, + input logic clk_en, + input logic f2io_1, + input logic [16:0] f2io_17, + input logic f2io_17_valid, + input logic f2io_1_valid, + input logic flush, + input logic glb2io_1, + input logic [16:0] glb2io_17, + input logic glb2io_17_valid, + input logic glb2io_1_valid, + input logic io2f_17_ready, + input logic io2f_1_ready, + input logic io2glb_17_ready, + input logic io2glb_1_ready, + input logic rst_n, + input logic tile_en, + output logic f2io_17_ready, + output logic f2io_1_ready, + output logic glb2io_17_ready, + output logic glb2io_1_ready, + output logic io2f_1, + output logic [16:0] io2f_17, + output logic io2f_17_valid, + output logic io2f_1_valid, + output logic io2glb_1, + output logic [16:0] io2glb_17, + output logic io2glb_17_valid, + output logic io2glb_1_valid +); + +logic [0:0][16:0] f2io_2_io2glb_17_data_out; +logic f2io_2_io2glb_17_empty; +logic f2io_2_io2glb_17_full; +logic [0:0] f2io_2_io2glb_1_data_out; +logic f2io_2_io2glb_1_empty; +logic f2io_2_io2glb_1_full; +logic gclk; +logic glb2io_2_io2f_17_empty; +logic glb2io_2_io2f_17_full; +logic glb2io_2_io2f_1_empty; +logic glb2io_2_io2f_1_full; +assign gclk = clk & tile_en; +assign io2glb_1 = f2io_2_io2glb_1_data_out; +assign f2io_1_ready = ~f2io_2_io2glb_1_full; +assign io2glb_1_valid = ~f2io_2_io2glb_1_empty; +assign glb2io_1_ready = ~glb2io_2_io2f_1_full; +assign io2f_1_valid = ~glb2io_2_io2f_1_empty; +assign io2glb_17 = f2io_2_io2glb_17_data_out[0][16:0]; +assign f2io_17_ready = ~f2io_2_io2glb_17_full; +assign io2glb_17_valid = ~f2io_2_io2glb_17_empty; +assign glb2io_17_ready = ~glb2io_2_io2f_17_full; +assign io2f_17_valid = ~glb2io_2_io2f_17_empty; +reg_fifo_depth_2_w_1_afd_1_iocore_nof f2io_2_io2glb_1 ( + .clk(clk), + .clk_en(clk_en), + .data_in(f2io_1), + .flush(flush), + .pop(io2glb_1_ready), + .push(f2io_1_valid), + .rst_n(rst_n), + .data_out(f2io_2_io2glb_1_data_out), + .empty(f2io_2_io2glb_1_empty), + .full(f2io_2_io2glb_1_full) +); + +reg_fifo_depth_2_w_1_afd_1_iocore_nof glb2io_2_io2f_1 ( + .clk(gclk), + .clk_en(clk_en), + .data_in(glb2io_1), + .flush(flush), + .pop(io2f_1_ready), + .push(glb2io_1_valid), + .rst_n(rst_n), + .data_out(io2f_1), + .empty(glb2io_2_io2f_1_empty), + .full(glb2io_2_io2f_1_full) +); + +reg_fifo_depth_2_w_17_afd_1_iocore_nof f2io_2_io2glb_17 ( + .clk(clk), + .clk_en(clk_en), + .data_in(f2io_17), + .flush(flush), + .pop(io2glb_17_ready), + .push(f2io_17_valid), + .rst_n(rst_n), + .data_out(f2io_2_io2glb_17_data_out), + .empty(f2io_2_io2glb_17_empty), + .full(f2io_2_io2glb_17_full) +); + +reg_fifo_depth_2_w_17_afd_1_iocore_nof glb2io_2_io2f_17 ( + .clk(gclk), + .clk_en(clk_en), + .data_in(glb2io_17), + .flush(flush), + .pop(io2f_17_ready), + .push(glb2io_17_valid), + .rst_n(rst_n), + .data_out(io2f_17), + .empty(glb2io_2_io2f_17_empty), + .full(glb2io_2_io2f_17_full) +); + +endmodule // io_core + +module io_core_W ( + input logic clk, + input logic clk_en, + input logic f2io_1, + input logic [16:0] f2io_17, + input logic f2io_17_valid, + input logic f2io_1_valid, + input logic flush, + input logic glb2io_1, + input logic [16:0] glb2io_17, + input logic glb2io_17_valid, + input logic glb2io_1_valid, + input logic io2f_17_ready, + input logic io2f_1_ready, + input logic io2glb_17_ready, + input logic io2glb_1_ready, + input logic rst_n, + input logic tile_en, + output logic f2io_17_ready, + output logic f2io_1_ready, + output logic glb2io_17_ready, + output logic glb2io_1_ready, + output logic io2f_1, + output logic [16:0] io2f_17, + output logic io2f_17_valid, + output logic io2f_1_valid, + output logic io2glb_1, + output logic [16:0] io2glb_17, + output logic io2glb_17_valid, + output logic io2glb_1_valid +); + +io_core io_core ( + .clk(clk), + .clk_en(clk_en), + .f2io_1(f2io_1), + .f2io_17(f2io_17), + .f2io_17_valid(f2io_17_valid), + .f2io_1_valid(f2io_1_valid), + .flush(flush), + .glb2io_1(glb2io_1), + .glb2io_17(glb2io_17), + .glb2io_17_valid(glb2io_17_valid), + .glb2io_1_valid(glb2io_1_valid), + .io2f_17_ready(io2f_17_ready), + .io2f_1_ready(io2f_1_ready), + .io2glb_17_ready(io2glb_17_ready), + .io2glb_1_ready(io2glb_1_ready), + .rst_n(rst_n), + .tile_en(tile_en), + .f2io_17_ready(f2io_17_ready), + .f2io_1_ready(f2io_1_ready), + .glb2io_17_ready(glb2io_17_ready), + .glb2io_1_ready(glb2io_1_ready), + .io2f_1(io2f_1), + .io2f_17(io2f_17), + .io2f_17_valid(io2f_17_valid), + .io2f_1_valid(io2f_1_valid), + .io2glb_1(io2glb_1), + .io2glb_17(io2glb_17), + .io2glb_17_valid(io2glb_17_valid), + .io2glb_1_valid(io2glb_1_valid) +); + +endmodule // io_core_W + +module reg_fifo_depth_2_w_17_afd_1_iocore_nof ( + input logic clk, + input logic clk_en, + input logic [0:0] [16:0] data_in, + input logic flush, + input logic pop, + input logic push, + input logic rst_n, + output logic almost_full, + output logic [0:0] [16:0] data_out, + output logic empty, + output logic full, + output logic valid +); + +logic [1:0] num_items; +logic passthru; +logic rd_ptr; +logic read; +logic [1:0][0:0][16:0] reg_array; +logic wr_ptr; +logic write; +assign full = num_items == 2'h2; +assign almost_full = num_items >= 2'h1; +assign empty = num_items == 2'h0; +assign read = pop & (~passthru) & (~empty); +assign passthru = 1'h0; +assign write = push & (~passthru) & (~full); + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + num_items <= 2'h0; + end + else if (flush) begin + num_items <= 2'h0; + end + else if (clk_en) begin + if (write & (~read)) begin + num_items <= num_items + 2'h1; + end + else if ((~write) & read) begin + num_items <= num_items - 2'h1; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + reg_array <= 34'h0; + end + else if (flush) begin + reg_array <= 34'h0; + end + else if (clk_en) begin + if (write) begin + reg_array[wr_ptr] <= data_in; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + wr_ptr <= 1'h0; + end + else if (flush) begin + wr_ptr <= 1'h0; + end + else if (clk_en) begin + if (write) begin + if (wr_ptr == 1'h1) begin + wr_ptr <= 1'h0; + end + else wr_ptr <= wr_ptr + 1'h1; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + rd_ptr <= 1'h0; + end + else if (flush) begin + rd_ptr <= 1'h0; + end + else if (clk_en) begin + if (read) begin + rd_ptr <= rd_ptr + 1'h1; + end + end +end +always_comb begin + if (passthru) begin + data_out = data_in; + end + else data_out = reg_array[rd_ptr]; +end +always_comb begin + valid = (~empty) | passthru; +end +endmodule // reg_fifo_depth_2_w_17_afd_1_iocore_nof + +module reg_fifo_depth_2_w_1_afd_1_iocore_nof ( + input logic clk, + input logic clk_en, + input logic [0:0] data_in, + input logic flush, + input logic pop, + input logic push, + input logic rst_n, + output logic almost_full, + output logic [0:0] data_out, + output logic empty, + output logic full, + output logic valid +); + +logic [1:0] num_items; +logic passthru; +logic rd_ptr; +logic read; +logic [1:0][0:0] reg_array; +logic wr_ptr; +logic write; +assign full = num_items == 2'h2; +assign almost_full = num_items >= 2'h1; +assign empty = num_items == 2'h0; +assign read = pop & (~passthru) & (~empty); +assign passthru = 1'h0; +assign write = push & (~passthru) & (~full); + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + num_items <= 2'h0; + end + else if (flush) begin + num_items <= 2'h0; + end + else if (clk_en) begin + if (write & (~read)) begin + num_items <= num_items + 2'h1; + end + else if ((~write) & read) begin + num_items <= num_items - 2'h1; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + reg_array <= 2'h0; + end + else if (flush) begin + reg_array <= 2'h0; + end + else if (clk_en) begin + if (write) begin + reg_array[wr_ptr] <= data_in; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + wr_ptr <= 1'h0; + end + else if (flush) begin + wr_ptr <= 1'h0; + end + else if (clk_en) begin + if (write) begin + if (wr_ptr == 1'h1) begin + wr_ptr <= 1'h0; + end + else wr_ptr <= wr_ptr + 1'h1; + end + end +end + +always_ff @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + rd_ptr <= 1'h0; + end + else if (flush) begin + rd_ptr <= 1'h0; + end + else if (clk_en) begin + if (read) begin + rd_ptr <= rd_ptr + 1'h1; + end + end +end +always_comb begin + if (passthru) begin + data_out = data_in; + end + else data_out = reg_array[rd_ptr]; +end +always_comb begin + valid = (~empty) | passthru; +end +endmodule // reg_fifo_depth_2_w_1_afd_1_iocore_nof + diff --git a/sam/onyx/garnet_PE.v b/sam/onyx/garnet_PE.v new file mode 100644 index 00000000..fd0bd370 --- /dev/null +++ b/sam/onyx/garnet_PE.v @@ -0,0 +1,5223 @@ +module PEGEN_mul_hack #( + parameter exp_bits = 1, + parameter frac_bits = 1, + parameter ieee_compliance = 1 +) ( + input [exp_bits+frac_bits:0] a, + input [exp_bits+frac_bits:0] b, + input [2:0] rnd, + output [exp_bits+frac_bits:0] z, + output [7:0] status +); + +wire [exp_bits+frac_bits:0] int_out; +wire [2:0] results_x; +reg sign; +reg [exp_bits-1:0] exp; +reg [frac_bits:0] frac; + +CW_fp_mult #(.sig_width(frac_bits+3), .exp_width(exp_bits), .ieee_compliance(ieee_compliance)) mul1 (.a({a,3'h0}),.b({b,3'h0}),.rnd(rnd),.z({int_out,results_x}),.status(status)); + +always @(*) begin + sign = int_out[exp_bits+frac_bits]; + exp = int_out[exp_bits+frac_bits-1:frac_bits]; + frac = {1'b0,int_out[frac_bits-1:0]}; + if ((results_x[2]&(results_x[1] | results_x[0])) | (int_out[0] & results_x[2])) begin + frac = frac + 1'd1; + if (~&exp) begin + exp = exp + {{(exp_bits-1){1'b0}},frac[frac_bits]}; + end + end +end +assign z = {sign, exp, frac[frac_bits-1:0]}; + +endmodule + +module PEGEN_add #( + parameter exp_bits = 1, + parameter frac_bits = 1, + parameter ieee_compliance = 1 +) ( + input [exp_bits+frac_bits:0] a, + input [exp_bits+frac_bits:0] b, + input [2:0] rnd, + output [exp_bits+frac_bits:0] z, + output [7:0] status +); +CW_fp_add #(.sig_width(frac_bits), .exp_width(exp_bits), .ieee_compliance(ieee_compliance)) add_inst (.a(a),.b(b),.rnd(rnd),.z(z),.status(status)); +endmodule + +module PEGEN_coreir_xor #( + parameter width = 1 +) ( + input [width-1:0] in0, + input [width-1:0] in1, + output [width-1:0] out +); + assign out = in0 ^ in1; +endmodule + +module PEGEN_coreir_ule #( + parameter width = 1 +) ( + input [width-1:0] in0, + input [width-1:0] in1, + output out +); + assign out = in0 <= in1; +endmodule + +module PEGEN_coreir_ugt #( + parameter width = 1 +) ( + input [width-1:0] in0, + input [width-1:0] in1, + output out +); + assign out = in0 > in1; +endmodule + +module PEGEN_coreir_uge #( + parameter width = 1 +) ( + input [width-1:0] in0, + input [width-1:0] in1, + output out +); + assign out = in0 >= in1; +endmodule + +module PEGEN_coreir_sub #( + parameter width = 1 +) ( + input [width-1:0] in0, + input [width-1:0] in1, + output [width-1:0] out +); + assign out = in0 - in1; +endmodule + +module PEGEN_coreir_slt #( + parameter width = 1 +) ( + input [width-1:0] in0, + input [width-1:0] in1, + output out +); + assign out = $signed(in0) < $signed(in1); +endmodule + +module PEGEN_coreir_sle #( + parameter width = 1 +) ( + input [width-1:0] in0, + input [width-1:0] in1, + output out +); + assign out = $signed(in0) <= $signed(in1); +endmodule + +module PEGEN_coreir_shl #( + parameter width = 1 +) ( + input [width-1:0] in0, + input [width-1:0] in1, + output [width-1:0] out +); + assign out = in0 << in1; +endmodule + +module PEGEN_coreir_sge #( + parameter width = 1 +) ( + input [width-1:0] in0, + input [width-1:0] in1, + output out +); + assign out = $signed(in0) >= $signed(in1); +endmodule + +module PEGEN_coreir_reg_arst #( + parameter width = 1, + parameter arst_posedge = 1, + parameter clk_posedge = 1, + parameter init = 1 +) ( + input clk, + input arst, + input [width-1:0] in, + output [width-1:0] out +); + reg [width-1:0] outReg; + wire real_rst; + assign real_rst = arst_posedge ? arst : ~arst; + wire real_clk; + assign real_clk = clk_posedge ? clk : ~clk; + always @(posedge real_clk, posedge real_rst) begin + if (real_rst) outReg <= init; + else outReg <= in; + end + assign out = outReg; +endmodule + +module PEGEN_coreir_or #( + parameter width = 1 +) ( + input [width-1:0] in0, + input [width-1:0] in1, + output [width-1:0] out +); + assign out = in0 | in1; +endmodule + +module PEGEN_coreir_not #( + parameter width = 1 +) ( + input [width-1:0] in, + output [width-1:0] out +); + assign out = ~in; +endmodule + +module PEGEN_coreir_neg #( + parameter width = 1 +) ( + input [width-1:0] in, + output [width-1:0] out +); + assign out = -in; +endmodule + +module PEGEN_coreir_mux #( + parameter width = 1 +) ( + input [width-1:0] in0, + input [width-1:0] in1, + input sel, + output [width-1:0] out +); + assign out = sel ? in1 : in0; +endmodule + +module PEGEN_coreir_mul #( + parameter width = 1 +) ( + input [width-1:0] in0, + input [width-1:0] in1, + output [width-1:0] out +); + assign out = in0 * in1; +endmodule + +module PEGEN_coreir_lshr #( + parameter width = 1 +) ( + input [width-1:0] in0, + input [width-1:0] in1, + output [width-1:0] out +); + assign out = in0 >> in1; +endmodule + +module PEGEN_coreir_eq #( + parameter width = 1 +) ( + input [width-1:0] in0, + input [width-1:0] in1, + output out +); + assign out = in0 == in1; +endmodule + +module PEGEN_coreir_const #( + parameter width = 1, + parameter value = 1 +) ( + output [width-1:0] out +); + assign out = value; +endmodule + +module PEGEN_float_mul__exp_bits8__frac_bits7 ( + input [15:0] in0, + input [15:0] in1, + output [15:0] out +); +wire [2:0] _$_U1_out; +wire [15:0] mi_z; +wire [7:0] mi_status; +PEGEN_coreir_const #( + .value(3'h1), + .width(3) +) _$_U1 ( + .out(_$_U1_out) +); +PEGEN_mul_hack #( + .exp_bits(8), + .frac_bits(7), + .ieee_compliance(1'b1) +) mi ( + .a(in0), + .b(in1), + .rnd(_$_U1_out), + .z(mi_z), + .status(mi_status) +); +assign out = mi_z; +endmodule + +module PEGEN_float_add__exp_bits8__frac_bits7 ( + input [15:0] in0, + input [15:0] in1, + output [15:0] out +); +wire [2:0] _$_U0_out; +wire [15:0] mi_z; +wire [7:0] mi_status; +PEGEN_coreir_const #( + .value(3'h0), + .width(3) +) _$_U0 ( + .out(_$_U0_out) +); +PEGEN_add #( + .exp_bits(8), + .frac_bits(7), + .ieee_compliance(1'b1) +) mi ( + .a(in0), + .b(in1), + .rnd(_$_U0_out), + .z(mi_z), + .status(mi_status) +); +assign out = mi_z; +endmodule + +module PEGEN_coreir_ashr #( + parameter width = 1 +) ( + input [width-1:0] in0, + input [width-1:0] in1, + output [width-1:0] out +); + assign out = $signed(in0) >>> in1; +endmodule + +module PEGEN_coreir_and #( + parameter width = 1 +) ( + input [width-1:0] in0, + input [width-1:0] in1, + output [width-1:0] out +); + assign out = in0 & in1; +endmodule + +module PEGEN_coreir_add #( + parameter width = 1 +) ( + input [width-1:0] in0, + input [width-1:0] in1, + output [width-1:0] out +); + assign out = in0 + in1; +endmodule + +module PEGEN_corebit_xor ( + input in0, + input in1, + output out +); + assign out = in0 ^ in1; +endmodule + +module PEGEN_corebit_or ( + input in0, + input in1, + output out +); + assign out = in0 | in1; +endmodule + +module PEGEN_corebit_not ( + input in, + output out +); + assign out = ~in; +endmodule + +module PEGEN_corebit_const #( + parameter value = 1 +) ( + output out +); + assign out = value; +endmodule + +module PEGEN_corebit_and ( + input in0, + input in1, + output out +); + assign out = in0 & in1; +endmodule + +module PEGEN_commonlib_muxn__N2__width9 ( + input [8:0] in_data [1:0], + input [0:0] in_sel, + output [8:0] out +); +wire [8:0] _join_out; +PEGEN_coreir_mux #( + .width(9) +) _join ( + .in0(in_data[0]), + .in1(in_data[1]), + .sel(in_sel[0]), + .out(_join_out) +); +assign out = _join_out; +endmodule + +module PEGEN_commonlib_muxn__N2__width8 ( + input [7:0] in_data [1:0], + input [0:0] in_sel, + output [7:0] out +); +wire [7:0] _join_out; +PEGEN_coreir_mux #( + .width(8) +) _join ( + .in0(in_data[0]), + .in1(in_data[1]), + .sel(in_sel[0]), + .out(_join_out) +); +assign out = _join_out; +endmodule + +module PEGEN_commonlib_muxn__N2__width5 ( + input [4:0] in_data [1:0], + input [0:0] in_sel, + output [4:0] out +); +wire [4:0] _join_out; +PEGEN_coreir_mux #( + .width(5) +) _join ( + .in0(in_data[0]), + .in1(in_data[1]), + .sel(in_sel[0]), + .out(_join_out) +); +assign out = _join_out; +endmodule + +module PEGEN_commonlib_muxn__N2__width32 ( + input [31:0] in_data [1:0], + input [0:0] in_sel, + output [31:0] out +); +wire [31:0] _join_out; +PEGEN_coreir_mux #( + .width(32) +) _join ( + .in0(in_data[0]), + .in1(in_data[1]), + .sel(in_sel[0]), + .out(_join_out) +); +assign out = _join_out; +endmodule + +module PEGEN_commonlib_muxn__N2__width3 ( + input [2:0] in_data [1:0], + input [0:0] in_sel, + output [2:0] out +); +wire [2:0] _join_out; +PEGEN_coreir_mux #( + .width(3) +) _join ( + .in0(in_data[0]), + .in1(in_data[1]), + .sel(in_sel[0]), + .out(_join_out) +); +assign out = _join_out; +endmodule + +module PEGEN_commonlib_muxn__N2__width23 ( + input [22:0] in_data [1:0], + input [0:0] in_sel, + output [22:0] out +); +wire [22:0] _join_out; +PEGEN_coreir_mux #( + .width(23) +) _join ( + .in0(in_data[0]), + .in1(in_data[1]), + .sel(in_sel[0]), + .out(_join_out) +); +assign out = _join_out; +endmodule + +module PEGEN_commonlib_muxn__N2__width16 ( + input [15:0] in_data [1:0], + input [0:0] in_sel, + output [15:0] out +); +wire [15:0] _join_out; +PEGEN_coreir_mux #( + .width(16) +) _join ( + .in0(in_data[0]), + .in1(in_data[1]), + .sel(in_sel[0]), + .out(_join_out) +); +assign out = _join_out; +endmodule + +module PEGEN_commonlib_muxn__N2__width1 ( + input [0:0] in_data [1:0], + input [0:0] in_sel, + output [0:0] out +); +wire [0:0] _join_out; +PEGEN_coreir_mux #( + .width(1) +) _join ( + .in0(in_data[0]), + .in1(in_data[1]), + .sel(in_sel[0]), + .out(_join_out) +); +assign out = _join_out; +endmodule + +module PEGEN_Op_unq1 ( + input [15:0] in0, + input [15:0] in1, + output [15:0] O, + input CLK, + input ASYNCRESET +); +wire [15:0] magma_BFloat_16_mul_inst0_out; +PEGEN_float_mul__exp_bits8__frac_bits7 magma_BFloat_16_mul_inst0 ( + .in0(in0), + .in1(in1), + .out(magma_BFloat_16_mul_inst0_out) +); +assign O = magma_BFloat_16_mul_inst0_out; +endmodule + +module PEGEN_Op ( + input [15:0] in0, + input [15:0] in1, + output [15:0] O, + input CLK, + input ASYNCRESET +); +wire [15:0] magma_BFloat_16_add_inst0_out; +PEGEN_float_add__exp_bits8__frac_bits7 magma_BFloat_16_add_inst0 ( + .in0(in0), + .in1(in1), + .out(magma_BFloat_16_add_inst0_out) +); +assign O = magma_BFloat_16_add_inst0_out; +endmodule + +module PEGEN_Mux2xUInt32 ( + input [31:0] I0, + input [31:0] I1, + input S, + output [31:0] O +); +wire [31:0] coreir_commonlib_mux2x32_inst0_out; +wire [31:0] coreir_commonlib_mux2x32_inst0_in_data [1:0]; +assign coreir_commonlib_mux2x32_inst0_in_data[1] = I1; +assign coreir_commonlib_mux2x32_inst0_in_data[0] = I0; +PEGEN_commonlib_muxn__N2__width32 coreir_commonlib_mux2x32_inst0 ( + .in_data(coreir_commonlib_mux2x32_inst0_in_data), + .in_sel(S), + .out(coreir_commonlib_mux2x32_inst0_out) +); +assign O = coreir_commonlib_mux2x32_inst0_out; +endmodule + +module PEGEN_Mux2xUInt16 ( + input [15:0] I0, + input [15:0] I1, + input S, + output [15:0] O +); +wire [15:0] coreir_commonlib_mux2x16_inst0_out; +wire [15:0] coreir_commonlib_mux2x16_inst0_in_data [1:0]; +assign coreir_commonlib_mux2x16_inst0_in_data[1] = I1; +assign coreir_commonlib_mux2x16_inst0_in_data[0] = I0; +PEGEN_commonlib_muxn__N2__width16 coreir_commonlib_mux2x16_inst0 ( + .in_data(coreir_commonlib_mux2x16_inst0_in_data), + .in_sel(S), + .out(coreir_commonlib_mux2x16_inst0_out) +); +assign O = coreir_commonlib_mux2x16_inst0_out; +endmodule + +module PEGEN_Mux2xSInt9 ( + input [8:0] I0, + input [8:0] I1, + input S, + output [8:0] O +); +wire [8:0] coreir_commonlib_mux2x9_inst0_out; +wire [8:0] coreir_commonlib_mux2x9_inst0_in_data [1:0]; +assign coreir_commonlib_mux2x9_inst0_in_data[1] = I1; +assign coreir_commonlib_mux2x9_inst0_in_data[0] = I0; +PEGEN_commonlib_muxn__N2__width9 coreir_commonlib_mux2x9_inst0 ( + .in_data(coreir_commonlib_mux2x9_inst0_in_data), + .in_sel(S), + .out(coreir_commonlib_mux2x9_inst0_out) +); +assign O = coreir_commonlib_mux2x9_inst0_out; +endmodule + +module PEGEN_Mux2xSInt16 ( + input [15:0] I0, + input [15:0] I1, + input S, + output [15:0] O +); +wire [15:0] coreir_commonlib_mux2x16_inst0_out; +wire [15:0] coreir_commonlib_mux2x16_inst0_in_data [1:0]; +assign coreir_commonlib_mux2x16_inst0_in_data[1] = I1; +assign coreir_commonlib_mux2x16_inst0_in_data[0] = I0; +PEGEN_commonlib_muxn__N2__width16 coreir_commonlib_mux2x16_inst0 ( + .in_data(coreir_commonlib_mux2x16_inst0_in_data), + .in_sel(S), + .out(coreir_commonlib_mux2x16_inst0_out) +); +assign O = coreir_commonlib_mux2x16_inst0_out; +endmodule + +module PEGEN_Mux2xMagmaADTFPU_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3 ( + input [2:0] I0, + input [2:0] I1, + input S, + output [2:0] O +); +wire [2:0] coreir_commonlib_mux2x3_inst0_out; +wire [2:0] coreir_commonlib_mux2x3_inst0_in_data [1:0]; +assign coreir_commonlib_mux2x3_inst0_in_data[1] = I1; +assign coreir_commonlib_mux2x3_inst0_in_data[0] = I0; +PEGEN_commonlib_muxn__N2__width3 coreir_commonlib_mux2x3_inst0 ( + .in_data(coreir_commonlib_mux2x3_inst0_in_data), + .in_sel(S), + .out(coreir_commonlib_mux2x3_inst0_out) +); +assign O = coreir_commonlib_mux2x3_inst0_out; +endmodule + +module PEGEN_Mux2xMagmaADTFPCustom_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3 ( + input [2:0] I0, + input [2:0] I1, + input S, + output [2:0] O +); +wire [2:0] coreir_commonlib_mux2x3_inst0_out; +wire [2:0] coreir_commonlib_mux2x3_inst0_in_data [1:0]; +assign coreir_commonlib_mux2x3_inst0_in_data[1] = I1; +assign coreir_commonlib_mux2x3_inst0_in_data[0] = I0; +PEGEN_commonlib_muxn__N2__width3 coreir_commonlib_mux2x3_inst0 ( + .in_data(coreir_commonlib_mux2x3_inst0_in_data), + .in_sel(S), + .out(coreir_commonlib_mux2x3_inst0_out) +); +assign O = coreir_commonlib_mux2x3_inst0_out; +endmodule + +module PEGEN_Mux2xMagmaADTALU_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3 ( + input [4:0] I0, + input [4:0] I1, + input S, + output [4:0] O +); +wire [4:0] coreir_commonlib_mux2x5_inst0_out; +wire [4:0] coreir_commonlib_mux2x5_inst0_in_data [1:0]; +assign coreir_commonlib_mux2x5_inst0_in_data[1] = I1; +assign coreir_commonlib_mux2x5_inst0_in_data[0] = I0; +PEGEN_commonlib_muxn__N2__width5 coreir_commonlib_mux2x5_inst0 ( + .in_data(coreir_commonlib_mux2x5_inst0_in_data), + .in_sel(S), + .out(coreir_commonlib_mux2x5_inst0_out) +); +assign O = coreir_commonlib_mux2x5_inst0_out; +endmodule + +module PEGEN_Mux2xBits8 ( + input [7:0] I0, + input [7:0] I1, + input S, + output [7:0] O +); +wire [7:0] coreir_commonlib_mux2x8_inst0_out; +wire [7:0] coreir_commonlib_mux2x8_inst0_in_data [1:0]; +assign coreir_commonlib_mux2x8_inst0_in_data[1] = I1; +assign coreir_commonlib_mux2x8_inst0_in_data[0] = I0; +PEGEN_commonlib_muxn__N2__width8 coreir_commonlib_mux2x8_inst0 ( + .in_data(coreir_commonlib_mux2x8_inst0_in_data), + .in_sel(S), + .out(coreir_commonlib_mux2x8_inst0_out) +); +assign O = coreir_commonlib_mux2x8_inst0_out; +endmodule + +module PEGEN_Mux2xBits23 ( + input [22:0] I0, + input [22:0] I1, + input S, + output [22:0] O +); +wire [22:0] coreir_commonlib_mux2x23_inst0_out; +wire [22:0] coreir_commonlib_mux2x23_inst0_in_data [1:0]; +assign coreir_commonlib_mux2x23_inst0_in_data[1] = I1; +assign coreir_commonlib_mux2x23_inst0_in_data[0] = I0; +PEGEN_commonlib_muxn__N2__width23 coreir_commonlib_mux2x23_inst0 ( + .in_data(coreir_commonlib_mux2x23_inst0_in_data), + .in_sel(S), + .out(coreir_commonlib_mux2x23_inst0_out) +); +assign O = coreir_commonlib_mux2x23_inst0_out; +endmodule + +module PEGEN_Mux2xBits16 ( + input [15:0] I0, + input [15:0] I1, + input S, + output [15:0] O +); +wire [15:0] coreir_commonlib_mux2x16_inst0_out; +wire [15:0] coreir_commonlib_mux2x16_inst0_in_data [1:0]; +assign coreir_commonlib_mux2x16_inst0_in_data[1] = I1; +assign coreir_commonlib_mux2x16_inst0_in_data[0] = I0; +PEGEN_commonlib_muxn__N2__width16 coreir_commonlib_mux2x16_inst0 ( + .in_data(coreir_commonlib_mux2x16_inst0_in_data), + .in_sel(S), + .out(coreir_commonlib_mux2x16_inst0_out) +); +assign O = coreir_commonlib_mux2x16_inst0_out; +endmodule + +module PEGEN_Register ( + input [15:0] value, + output [15:0] O, + input en, + input CLK, + input ASYNCRESET +); +wire [15:0] enable_mux_O; +wire [15:0] reg_PR16_inst0_out; +PEGEN_Mux2xBits16 enable_mux ( + .I0(reg_PR16_inst0_out), + .I1(value), + .S(en), + .O(enable_mux_O) +); +PEGEN_coreir_reg_arst #( + .arst_posedge(1'b1), + .clk_posedge(1'b1), + .init(16'h0000), + .width(16) +) reg_PR16_inst0 ( + .clk(CLK), + .arst(ASYNCRESET), + .in(enable_mux_O), + .out(reg_PR16_inst0_out) +); +assign O = reg_PR16_inst0_out; +endmodule + +module PEGEN_Mux2xBit ( + input I0, + input I1, + input S, + output O +); +wire [0:0] coreir_commonlib_mux2x1_inst0_out; +wire [0:0] coreir_commonlib_mux2x1_inst0_in_data [1:0]; +assign coreir_commonlib_mux2x1_inst0_in_data[1] = I1; +assign coreir_commonlib_mux2x1_inst0_in_data[0] = I0; +PEGEN_commonlib_muxn__N2__width1 coreir_commonlib_mux2x1_inst0 ( + .in_data(coreir_commonlib_mux2x1_inst0_in_data), + .in_sel(S), + .out(coreir_commonlib_mux2x1_inst0_out) +); +assign O = coreir_commonlib_mux2x1_inst0_out[0]; +endmodule + +module PEGEN_Register_unq1 ( + input value, + output O, + input en, + input CLK, + input ASYNCRESET +); +wire enable_mux_O; +wire [0:0] reg_PR1_inst0_out; +PEGEN_Mux2xBit enable_mux ( + .I0(reg_PR1_inst0_out[0]), + .I1(value), + .S(en), + .O(enable_mux_O) +); +PEGEN_coreir_reg_arst #( + .arst_posedge(1'b1), + .clk_posedge(1'b1), + .init(1'h0), + .width(1) +) reg_PR1_inst0 ( + .clk(CLK), + .arst(ASYNCRESET), + .in(enable_mux_O), + .out(reg_PR1_inst0_out) +); +assign O = reg_PR1_inst0_out[0]; +endmodule + +module PEGEN_RegisterMode_unq1 ( + input [1:0] mode, + input const_, + input value, + input clk_en, + output O0, + output O1, + input CLK, + input ASYNCRESET +); +wire Mux2xBit_inst0_O; +wire Mux2xBit_inst1_O; +wire Mux2xBit_inst2_O; +wire Mux2xBit_inst3_O; +wire Mux2xBit_inst4_O; +wire Mux2xBit_inst5_O; +wire Register_inst0_O; +wire bit_const_0_None_out; +wire [1:0] const_0_2_out; +wire [1:0] const_2_2_out; +wire [1:0] const_3_2_out; +wire magma_Bits_2_eq_inst0_out; +wire magma_Bits_2_eq_inst1_out; +wire magma_Bits_2_eq_inst2_out; +PEGEN_Mux2xBit Mux2xBit_inst0 ( + .I0(value), + .I1(value), + .S(magma_Bits_2_eq_inst0_out), + .O(Mux2xBit_inst0_O) +); +PEGEN_Mux2xBit Mux2xBit_inst1 ( + .I0(bit_const_0_None_out), + .I1(clk_en), + .S(magma_Bits_2_eq_inst0_out), + .O(Mux2xBit_inst1_O) +); +PEGEN_Mux2xBit Mux2xBit_inst2 ( + .I0(Register_inst0_O), + .I1(value), + .S(magma_Bits_2_eq_inst2_out), + .O(Mux2xBit_inst2_O) +); +PEGEN_Mux2xBit Mux2xBit_inst3 ( + .I0(Register_inst0_O), + .I1(Register_inst0_O), + .S(magma_Bits_2_eq_inst2_out), + .O(Mux2xBit_inst3_O) +); +PEGEN_Mux2xBit Mux2xBit_inst4 ( + .I0(Mux2xBit_inst2_O), + .I1(const_), + .S(magma_Bits_2_eq_inst1_out), + .O(Mux2xBit_inst4_O) +); +PEGEN_Mux2xBit Mux2xBit_inst5 ( + .I0(Mux2xBit_inst3_O), + .I1(Register_inst0_O), + .S(magma_Bits_2_eq_inst1_out), + .O(Mux2xBit_inst5_O) +); +PEGEN_Register_unq1 Register_inst0 ( + .value(Mux2xBit_inst0_O), + .O(Register_inst0_O), + .en(Mux2xBit_inst1_O), + .CLK(CLK), + .ASYNCRESET(ASYNCRESET) +); +PEGEN_corebit_const #( + .value(1'b0) +) bit_const_0_None ( + .out(bit_const_0_None_out) +); +PEGEN_coreir_const #( + .value(2'h0), + .width(2) +) const_0_2 ( + .out(const_0_2_out) +); +PEGEN_coreir_const #( + .value(2'h2), + .width(2) +) const_2_2 ( + .out(const_2_2_out) +); +PEGEN_coreir_const #( + .value(2'h3), + .width(2) +) const_3_2 ( + .out(const_3_2_out) +); +PEGEN_coreir_eq #( + .width(2) +) magma_Bits_2_eq_inst0 ( + .in0(mode), + .in1(const_3_2_out), + .out(magma_Bits_2_eq_inst0_out) +); +PEGEN_coreir_eq #( + .width(2) +) magma_Bits_2_eq_inst1 ( + .in0(mode), + .in1(const_0_2_out), + .out(magma_Bits_2_eq_inst1_out) +); +PEGEN_coreir_eq #( + .width(2) +) magma_Bits_2_eq_inst2 ( + .in0(mode), + .in1(const_2_2_out), + .out(magma_Bits_2_eq_inst2_out) +); +assign O0 = Mux2xBit_inst4_O; +assign O1 = Mux2xBit_inst5_O; +endmodule + +module PEGEN_RegisterMode ( + input [1:0] mode, + input [15:0] const_, + input [15:0] value, + input clk_en, + output [15:0] O0, + output [15:0] O1, + input CLK, + input ASYNCRESET +); +wire Mux2xBit_inst0_O; +wire [15:0] Mux2xBits16_inst0_O; +wire [15:0] Mux2xBits16_inst1_O; +wire [15:0] Mux2xBits16_inst2_O; +wire [15:0] Mux2xBits16_inst3_O; +wire [15:0] Mux2xBits16_inst4_O; +wire [15:0] Register_inst0_O; +wire bit_const_0_None_out; +wire [1:0] const_0_2_out; +wire [1:0] const_2_2_out; +wire [1:0] const_3_2_out; +wire magma_Bits_2_eq_inst0_out; +wire magma_Bits_2_eq_inst1_out; +wire magma_Bits_2_eq_inst2_out; +PEGEN_Mux2xBit Mux2xBit_inst0 ( + .I0(bit_const_0_None_out), + .I1(clk_en), + .S(magma_Bits_2_eq_inst0_out), + .O(Mux2xBit_inst0_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst0 ( + .I0(value), + .I1(value), + .S(magma_Bits_2_eq_inst0_out), + .O(Mux2xBits16_inst0_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst1 ( + .I0(Register_inst0_O), + .I1(value), + .S(magma_Bits_2_eq_inst2_out), + .O(Mux2xBits16_inst1_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst2 ( + .I0(Register_inst0_O), + .I1(Register_inst0_O), + .S(magma_Bits_2_eq_inst2_out), + .O(Mux2xBits16_inst2_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst3 ( + .I0(Mux2xBits16_inst1_O), + .I1(const_), + .S(magma_Bits_2_eq_inst1_out), + .O(Mux2xBits16_inst3_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst4 ( + .I0(Mux2xBits16_inst2_O), + .I1(Register_inst0_O), + .S(magma_Bits_2_eq_inst1_out), + .O(Mux2xBits16_inst4_O) +); +PEGEN_Register Register_inst0 ( + .value(Mux2xBits16_inst0_O), + .O(Register_inst0_O), + .en(Mux2xBit_inst0_O), + .CLK(CLK), + .ASYNCRESET(ASYNCRESET) +); +PEGEN_corebit_const #( + .value(1'b0) +) bit_const_0_None ( + .out(bit_const_0_None_out) +); +PEGEN_coreir_const #( + .value(2'h0), + .width(2) +) const_0_2 ( + .out(const_0_2_out) +); +PEGEN_coreir_const #( + .value(2'h2), + .width(2) +) const_2_2 ( + .out(const_2_2_out) +); +PEGEN_coreir_const #( + .value(2'h3), + .width(2) +) const_3_2 ( + .out(const_3_2_out) +); +PEGEN_coreir_eq #( + .width(2) +) magma_Bits_2_eq_inst0 ( + .in0(mode), + .in1(const_3_2_out), + .out(magma_Bits_2_eq_inst0_out) +); +PEGEN_coreir_eq #( + .width(2) +) magma_Bits_2_eq_inst1 ( + .in0(mode), + .in1(const_0_2_out), + .out(magma_Bits_2_eq_inst1_out) +); +PEGEN_coreir_eq #( + .width(2) +) magma_Bits_2_eq_inst2 ( + .in0(mode), + .in1(const_2_2_out), + .out(magma_Bits_2_eq_inst2_out) +); +assign O0 = Mux2xBits16_inst3_O; +assign O1 = Mux2xBits16_inst4_O; +endmodule + +module PEGEN_LUT ( + input [7:0] lut, + input bit0, + input bit1, + input bit2, + output O, + input CLK, + input ASYNCRESET +); +wire bit_const_0_None_out; +wire [7:0] const_1_8_out; +wire [7:0] magma_Bits_8_and_inst0_out; +wire [7:0] magma_Bits_8_lshr_inst0_out; +PEGEN_corebit_const #( + .value(1'b0) +) bit_const_0_None ( + .out(bit_const_0_None_out) +); +PEGEN_coreir_const #( + .value(8'h01), + .width(8) +) const_1_8 ( + .out(const_1_8_out) +); +PEGEN_coreir_and #( + .width(8) +) magma_Bits_8_and_inst0 ( + .in0(magma_Bits_8_lshr_inst0_out), + .in1(const_1_8_out), + .out(magma_Bits_8_and_inst0_out) +); +wire [7:0] magma_Bits_8_lshr_inst0_in1; +assign magma_Bits_8_lshr_inst0_in1 = {bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit2,bit1,bit0}; +PEGEN_coreir_lshr #( + .width(8) +) magma_Bits_8_lshr_inst0 ( + .in0(lut), + .in1(magma_Bits_8_lshr_inst0_in1), + .out(magma_Bits_8_lshr_inst0_out) +); +assign O = magma_Bits_8_and_inst0_out[0]; +endmodule + +module PEGEN_FPU ( + input [2:0] fpu_op, + input [15:0] a, + input [15:0] b, + output [15:0] res, + output N, + output Z, + input CLK, + input ASYNCRESET +); +wire Mux2xBit_inst0_O; +wire Mux2xBit_inst1_O; +wire [15:0] Mux2xBits16_inst0_O; +wire [15:0] Mux2xBits16_inst1_O; +wire [15:0] Mux2xBits16_inst2_O; +wire [15:0] Mux2xBits16_inst3_O; +wire [15:0] Op_inst0_O; +wire [15:0] Op_inst1_O; +wire bit_const_1_None_out; +wire [2:0] const_0_3_out; +wire [6:0] const_0_7_out; +wire [7:0] const_0_8_out; +wire [2:0] const_1_3_out; +wire [7:0] const_255_8_out; +wire [2:0] const_2_3_out; +wire [15:0] const_32768_16_out; +wire [2:0] const_4_3_out; +wire magma_Bit_and_inst0_out; +wire magma_Bit_and_inst1_out; +wire magma_Bit_and_inst2_out; +wire magma_Bit_and_inst3_out; +wire magma_Bit_and_inst4_out; +wire magma_Bit_not_inst0_out; +wire magma_Bit_or_inst0_out; +wire magma_Bit_or_inst1_out; +wire magma_Bit_or_inst2_out; +wire magma_Bit_or_inst3_out; +wire magma_Bit_xor_inst0_out; +wire [15:0] magma_Bits_16_xor_inst0_out; +wire magma_Bits_3_eq_inst0_out; +wire magma_Bits_3_eq_inst1_out; +wire magma_Bits_3_eq_inst2_out; +wire magma_Bits_3_eq_inst3_out; +wire magma_Bits_3_eq_inst4_out; +wire magma_Bits_3_eq_inst5_out; +wire magma_Bits_3_eq_inst6_out; +wire magma_Bits_3_eq_inst7_out; +wire magma_Bits_7_eq_inst0_out; +wire magma_Bits_7_eq_inst1_out; +wire magma_Bits_7_eq_inst2_out; +wire magma_Bits_8_eq_inst0_out; +wire magma_Bits_8_eq_inst1_out; +wire magma_Bits_8_eq_inst2_out; +PEGEN_Mux2xBit Mux2xBit_inst0 ( + .I0(magma_Bit_and_inst2_out), + .I1(bit_const_1_None_out), + .S(magma_Bit_and_inst4_out), + .O(Mux2xBit_inst0_O) +); +PEGEN_Mux2xBit Mux2xBit_inst1 ( + .I0(magma_Bit_and_inst2_out), + .I1(Mux2xBit_inst0_O), + .S(magma_Bits_3_eq_inst7_out), + .O(Mux2xBit_inst1_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst0 ( + .I0(b), + .I1(magma_Bits_16_xor_inst0_out), + .S(magma_Bit_or_inst1_out), + .O(Mux2xBits16_inst0_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst1 ( + .I0(a), + .I1(b), + .S(Op_inst0_O[15]), + .O(Mux2xBits16_inst1_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst2 ( + .I0(Op_inst1_O), + .I1(Mux2xBits16_inst1_O), + .S(magma_Bits_3_eq_inst6_out), + .O(Mux2xBits16_inst2_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst3 ( + .I0(Mux2xBits16_inst2_O), + .I1(Op_inst0_O), + .S(magma_Bit_or_inst3_out), + .O(Mux2xBits16_inst3_O) +); +PEGEN_Op Op_inst0 ( + .in0(a), + .in1(Mux2xBits16_inst0_O), + .O(Op_inst0_O), + .CLK(CLK), + .ASYNCRESET(ASYNCRESET) +); +PEGEN_Op_unq1 Op_inst1 ( + .in0(a), + .in1(Mux2xBits16_inst0_O), + .O(Op_inst1_O), + .CLK(CLK), + .ASYNCRESET(ASYNCRESET) +); +PEGEN_corebit_const #( + .value(1'b1) +) bit_const_1_None ( + .out(bit_const_1_None_out) +); +PEGEN_coreir_const #( + .value(3'h0), + .width(3) +) const_0_3 ( + .out(const_0_3_out) +); +PEGEN_coreir_const #( + .value(7'h00), + .width(7) +) const_0_7 ( + .out(const_0_7_out) +); +PEGEN_coreir_const #( + .value(8'h00), + .width(8) +) const_0_8 ( + .out(const_0_8_out) +); +PEGEN_coreir_const #( + .value(3'h1), + .width(3) +) const_1_3 ( + .out(const_1_3_out) +); +PEGEN_coreir_const #( + .value(8'hff), + .width(8) +) const_255_8 ( + .out(const_255_8_out) +); +PEGEN_coreir_const #( + .value(3'h2), + .width(3) +) const_2_3 ( + .out(const_2_3_out) +); +PEGEN_coreir_const #( + .value(16'h8000), + .width(16) +) const_32768_16 ( + .out(const_32768_16_out) +); +PEGEN_coreir_const #( + .value(3'h4), + .width(3) +) const_4_3 ( + .out(const_4_3_out) +); +PEGEN_corebit_and magma_Bit_and_inst0 ( + .in0(magma_Bits_8_eq_inst0_out), + .in1(magma_Bits_7_eq_inst0_out), + .out(magma_Bit_and_inst0_out) +); +PEGEN_corebit_and magma_Bit_and_inst1 ( + .in0(magma_Bits_8_eq_inst1_out), + .in1(magma_Bits_7_eq_inst1_out), + .out(magma_Bit_and_inst1_out) +); +PEGEN_corebit_and magma_Bit_and_inst2 ( + .in0(magma_Bits_8_eq_inst2_out), + .in1(magma_Bits_7_eq_inst2_out), + .out(magma_Bit_and_inst2_out) +); +PEGEN_corebit_and magma_Bit_and_inst3 ( + .in0(magma_Bit_and_inst0_out), + .in1(magma_Bit_and_inst1_out), + .out(magma_Bit_and_inst3_out) +); +PEGEN_corebit_and magma_Bit_and_inst4 ( + .in0(magma_Bit_and_inst3_out), + .in1(magma_Bit_not_inst0_out), + .out(magma_Bit_and_inst4_out) +); +PEGEN_corebit_not magma_Bit_not_inst0 ( + .in(magma_Bit_xor_inst0_out), + .out(magma_Bit_not_inst0_out) +); +PEGEN_corebit_or magma_Bit_or_inst0 ( + .in0(magma_Bits_3_eq_inst0_out), + .in1(magma_Bits_3_eq_inst1_out), + .out(magma_Bit_or_inst0_out) +); +PEGEN_corebit_or magma_Bit_or_inst1 ( + .in0(magma_Bit_or_inst0_out), + .in1(magma_Bits_3_eq_inst2_out), + .out(magma_Bit_or_inst1_out) +); +PEGEN_corebit_or magma_Bit_or_inst2 ( + .in0(magma_Bits_3_eq_inst3_out), + .in1(magma_Bits_3_eq_inst4_out), + .out(magma_Bit_or_inst2_out) +); +PEGEN_corebit_or magma_Bit_or_inst3 ( + .in0(magma_Bit_or_inst2_out), + .in1(magma_Bits_3_eq_inst5_out), + .out(magma_Bit_or_inst3_out) +); +PEGEN_corebit_xor magma_Bit_xor_inst0 ( + .in0(a[15]), + .in1(b[15]), + .out(magma_Bit_xor_inst0_out) +); +PEGEN_coreir_xor #( + .width(16) +) magma_Bits_16_xor_inst0 ( + .in0(b), + .in1(const_32768_16_out), + .out(magma_Bits_16_xor_inst0_out) +); +PEGEN_coreir_eq #( + .width(3) +) magma_Bits_3_eq_inst0 ( + .in0(fpu_op), + .in1(const_1_3_out), + .out(magma_Bits_3_eq_inst0_out) +); +PEGEN_coreir_eq #( + .width(3) +) magma_Bits_3_eq_inst1 ( + .in0(fpu_op), + .in1(const_2_3_out), + .out(magma_Bits_3_eq_inst1_out) +); +PEGEN_coreir_eq #( + .width(3) +) magma_Bits_3_eq_inst2 ( + .in0(fpu_op), + .in1(const_4_3_out), + .out(magma_Bits_3_eq_inst2_out) +); +PEGEN_coreir_eq #( + .width(3) +) magma_Bits_3_eq_inst3 ( + .in0(fpu_op), + .in1(const_0_3_out), + .out(magma_Bits_3_eq_inst3_out) +); +PEGEN_coreir_eq #( + .width(3) +) magma_Bits_3_eq_inst4 ( + .in0(fpu_op), + .in1(const_1_3_out), + .out(magma_Bits_3_eq_inst4_out) +); +PEGEN_coreir_eq #( + .width(3) +) magma_Bits_3_eq_inst5 ( + .in0(fpu_op), + .in1(const_2_3_out), + .out(magma_Bits_3_eq_inst5_out) +); +PEGEN_coreir_eq #( + .width(3) +) magma_Bits_3_eq_inst6 ( + .in0(fpu_op), + .in1(const_4_3_out), + .out(magma_Bits_3_eq_inst6_out) +); +PEGEN_coreir_eq #( + .width(3) +) magma_Bits_3_eq_inst7 ( + .in0(fpu_op), + .in1(const_2_3_out), + .out(magma_Bits_3_eq_inst7_out) +); +PEGEN_coreir_eq #( + .width(7) +) magma_Bits_7_eq_inst0 ( + .in0(a[6:0]), + .in1(const_0_7_out), + .out(magma_Bits_7_eq_inst0_out) +); +PEGEN_coreir_eq #( + .width(7) +) magma_Bits_7_eq_inst1 ( + .in0(b[6:0]), + .in1(const_0_7_out), + .out(magma_Bits_7_eq_inst1_out) +); +PEGEN_coreir_eq #( + .width(7) +) magma_Bits_7_eq_inst2 ( + .in0(Mux2xBits16_inst3_O[6:0]), + .in1(const_0_7_out), + .out(magma_Bits_7_eq_inst2_out) +); +PEGEN_coreir_eq #( + .width(8) +) magma_Bits_8_eq_inst0 ( + .in0(a[14:7]), + .in1(const_255_8_out), + .out(magma_Bits_8_eq_inst0_out) +); +PEGEN_coreir_eq #( + .width(8) +) magma_Bits_8_eq_inst1 ( + .in0(b[14:7]), + .in1(const_255_8_out), + .out(magma_Bits_8_eq_inst1_out) +); +PEGEN_coreir_eq #( + .width(8) +) magma_Bits_8_eq_inst2 ( + .in0(Mux2xBits16_inst3_O[14:7]), + .in1(const_0_8_out), + .out(magma_Bits_8_eq_inst2_out) +); +assign res = Mux2xBits16_inst3_O; +assign N = Mux2xBits16_inst3_O[15]; +assign Z = Mux2xBit_inst1_O; +endmodule + +module PEGEN_FPCustom ( + input [2:0] op, + input [0:0] signed_, + input [15:0] a, + input [15:0] b, + output [15:0] res, + output res_p, + output V, + input CLK, + input ASYNCRESET +); +wire Mux2xBit_inst0_O; +wire Mux2xBit_inst1_O; +wire Mux2xBit_inst10_O; +wire Mux2xBit_inst2_O; +wire Mux2xBit_inst3_O; +wire Mux2xBit_inst4_O; +wire Mux2xBit_inst5_O; +wire Mux2xBit_inst6_O; +wire Mux2xBit_inst7_O; +wire Mux2xBit_inst8_O; +wire Mux2xBit_inst9_O; +wire [15:0] Mux2xBits16_inst0_O; +wire [15:0] Mux2xBits16_inst1_O; +wire [15:0] Mux2xBits16_inst10_O; +wire [15:0] Mux2xBits16_inst11_O; +wire [15:0] Mux2xBits16_inst12_O; +wire [15:0] Mux2xBits16_inst13_O; +wire [15:0] Mux2xBits16_inst14_O; +wire [15:0] Mux2xBits16_inst15_O; +wire [15:0] Mux2xBits16_inst16_O; +wire [15:0] Mux2xBits16_inst17_O; +wire [15:0] Mux2xBits16_inst18_O; +wire [15:0] Mux2xBits16_inst19_O; +wire [15:0] Mux2xBits16_inst2_O; +wire [15:0] Mux2xBits16_inst20_O; +wire [15:0] Mux2xBits16_inst3_O; +wire [15:0] Mux2xBits16_inst4_O; +wire [15:0] Mux2xBits16_inst5_O; +wire [15:0] Mux2xBits16_inst6_O; +wire [15:0] Mux2xBits16_inst7_O; +wire [15:0] Mux2xBits16_inst8_O; +wire [15:0] Mux2xBits16_inst9_O; +wire [22:0] Mux2xBits23_inst0_O; +wire [7:0] Mux2xBits8_inst0_O; +wire [7:0] Mux2xBits8_inst1_O; +wire [7:0] Mux2xBits8_inst2_O; +wire [7:0] Mux2xBits8_inst3_O; +wire [7:0] Mux2xBits8_inst4_O; +wire [7:0] Mux2xBits8_inst5_O; +wire [15:0] Mux2xSInt16_inst0_O; +wire [15:0] Mux2xSInt16_inst1_O; +wire [15:0] Mux2xSInt16_inst10_O; +wire [15:0] Mux2xSInt16_inst11_O; +wire [15:0] Mux2xSInt16_inst12_O; +wire [15:0] Mux2xSInt16_inst13_O; +wire [15:0] Mux2xSInt16_inst14_O; +wire [15:0] Mux2xSInt16_inst15_O; +wire [15:0] Mux2xSInt16_inst16_O; +wire [15:0] Mux2xSInt16_inst17_O; +wire [15:0] Mux2xSInt16_inst18_O; +wire [15:0] Mux2xSInt16_inst19_O; +wire [15:0] Mux2xSInt16_inst2_O; +wire [15:0] Mux2xSInt16_inst20_O; +wire [15:0] Mux2xSInt16_inst21_O; +wire [15:0] Mux2xSInt16_inst22_O; +wire [15:0] Mux2xSInt16_inst23_O; +wire [15:0] Mux2xSInt16_inst24_O; +wire [15:0] Mux2xSInt16_inst25_O; +wire [15:0] Mux2xSInt16_inst26_O; +wire [15:0] Mux2xSInt16_inst27_O; +wire [15:0] Mux2xSInt16_inst28_O; +wire [15:0] Mux2xSInt16_inst29_O; +wire [15:0] Mux2xSInt16_inst3_O; +wire [15:0] Mux2xSInt16_inst30_O; +wire [15:0] Mux2xSInt16_inst4_O; +wire [15:0] Mux2xSInt16_inst5_O; +wire [15:0] Mux2xSInt16_inst6_O; +wire [15:0] Mux2xSInt16_inst7_O; +wire [15:0] Mux2xSInt16_inst8_O; +wire [15:0] Mux2xSInt16_inst9_O; +wire [8:0] Mux2xSInt9_inst0_O; +wire [8:0] Mux2xSInt9_inst1_O; +wire [8:0] Mux2xSInt9_inst10_O; +wire [8:0] Mux2xSInt9_inst11_O; +wire [8:0] Mux2xSInt9_inst12_O; +wire [8:0] Mux2xSInt9_inst2_O; +wire [8:0] Mux2xSInt9_inst3_O; +wire [8:0] Mux2xSInt9_inst4_O; +wire [8:0] Mux2xSInt9_inst5_O; +wire [8:0] Mux2xSInt9_inst6_O; +wire [8:0] Mux2xSInt9_inst7_O; +wire [8:0] Mux2xSInt9_inst8_O; +wire [8:0] Mux2xSInt9_inst9_O; +wire bit_const_0_None_out; +wire bit_const_1_None_out; +wire [15:0] const_0_16_out; +wire [22:0] const_0_23_out; +wire [2:0] const_0_3_out; +wire [8:0] const_0_9_out; +wire [15:0] const_10_16_out; +wire [15:0] const_11_16_out; +wire [15:0] const_127_16_out; +wire [7:0] const_127_8_out; +wire [8:0] const_127_9_out; +wire [15:0] const_128_16_out; +wire [15:0] const_12_16_out; +wire [15:0] const_13_16_out; +wire [7:0] const_142_8_out; +wire [15:0] const_14_16_out; +wire [15:0] const_15_16_out; +wire [0:0] const_1_1_out; +wire [15:0] const_1_16_out; +wire [2:0] const_1_3_out; +wire [8:0] const_255_9_out; +wire [15:0] const_2_16_out; +wire [2:0] const_2_3_out; +wire [15:0] const_32512_16_out; +wire [15:0] const_32640_16_out; +wire [15:0] const_32768_16_out; +wire [15:0] const_3_16_out; +wire [2:0] const_3_3_out; +wire [15:0] const_4_16_out; +wire [2:0] const_4_3_out; +wire [15:0] const_5_16_out; +wire [2:0] const_5_3_out; +wire [15:0] const_65409_16_out; +wire [15:0] const_6_16_out; +wire [2:0] const_6_3_out; +wire [15:0] const_7_16_out; +wire [22:0] const_7_23_out; +wire [15:0] const_8_16_out; +wire [15:0] const_9_16_out; +wire magma_Bit_not_inst0_out; +wire magma_Bit_not_inst1_out; +wire magma_Bit_not_inst10_out; +wire magma_Bit_not_inst11_out; +wire magma_Bit_not_inst12_out; +wire magma_Bit_not_inst13_out; +wire magma_Bit_not_inst14_out; +wire magma_Bit_not_inst15_out; +wire magma_Bit_not_inst16_out; +wire magma_Bit_not_inst17_out; +wire magma_Bit_not_inst18_out; +wire magma_Bit_not_inst19_out; +wire magma_Bit_not_inst2_out; +wire magma_Bit_not_inst20_out; +wire magma_Bit_not_inst21_out; +wire magma_Bit_not_inst22_out; +wire magma_Bit_not_inst23_out; +wire magma_Bit_not_inst24_out; +wire magma_Bit_not_inst3_out; +wire magma_Bit_not_inst4_out; +wire magma_Bit_not_inst5_out; +wire magma_Bit_not_inst6_out; +wire magma_Bit_not_inst7_out; +wire magma_Bit_not_inst8_out; +wire magma_Bit_not_inst9_out; +wire magma_Bit_xor_inst0_out; +wire magma_Bit_xor_inst1_out; +wire magma_Bit_xor_inst10_out; +wire magma_Bit_xor_inst11_out; +wire magma_Bit_xor_inst12_out; +wire magma_Bit_xor_inst13_out; +wire magma_Bit_xor_inst14_out; +wire magma_Bit_xor_inst15_out; +wire magma_Bit_xor_inst16_out; +wire magma_Bit_xor_inst17_out; +wire magma_Bit_xor_inst18_out; +wire magma_Bit_xor_inst19_out; +wire magma_Bit_xor_inst2_out; +wire magma_Bit_xor_inst20_out; +wire magma_Bit_xor_inst21_out; +wire magma_Bit_xor_inst22_out; +wire magma_Bit_xor_inst23_out; +wire magma_Bit_xor_inst24_out; +wire magma_Bit_xor_inst3_out; +wire magma_Bit_xor_inst4_out; +wire magma_Bit_xor_inst5_out; +wire magma_Bit_xor_inst6_out; +wire magma_Bit_xor_inst7_out; +wire magma_Bit_xor_inst8_out; +wire magma_Bit_xor_inst9_out; +wire [15:0] magma_Bits_16_and_inst0_out; +wire [15:0] magma_Bits_16_and_inst1_out; +wire [15:0] magma_Bits_16_and_inst10_out; +wire [15:0] magma_Bits_16_and_inst11_out; +wire [15:0] magma_Bits_16_and_inst12_out; +wire [15:0] magma_Bits_16_and_inst2_out; +wire [15:0] magma_Bits_16_and_inst3_out; +wire [15:0] magma_Bits_16_and_inst4_out; +wire [15:0] magma_Bits_16_and_inst5_out; +wire [15:0] magma_Bits_16_and_inst6_out; +wire [15:0] magma_Bits_16_and_inst7_out; +wire [15:0] magma_Bits_16_and_inst8_out; +wire [15:0] magma_Bits_16_and_inst9_out; +wire magma_Bits_16_eq_inst0_out; +wire magma_Bits_16_eq_inst1_out; +wire [15:0] magma_Bits_16_lshr_inst0_out; +wire [15:0] magma_Bits_16_lshr_inst1_out; +wire [15:0] magma_Bits_16_or_inst0_out; +wire [15:0] magma_Bits_16_or_inst1_out; +wire [15:0] magma_Bits_16_or_inst2_out; +wire [15:0] magma_Bits_16_or_inst3_out; +wire [15:0] magma_Bits_16_or_inst4_out; +wire [15:0] magma_Bits_16_or_inst5_out; +wire [15:0] magma_Bits_16_or_inst6_out; +wire [15:0] magma_Bits_16_or_inst7_out; +wire [15:0] magma_Bits_16_or_inst8_out; +wire [15:0] magma_Bits_16_shl_inst0_out; +wire [15:0] magma_Bits_16_shl_inst1_out; +wire [15:0] magma_Bits_16_shl_inst2_out; +wire [15:0] magma_Bits_16_shl_inst3_out; +wire magma_Bits_1_eq_inst0_out; +wire [22:0] magma_Bits_23_lshr_inst0_out; +wire [22:0] magma_Bits_23_shl_inst0_out; +wire magma_Bits_3_eq_inst0_out; +wire magma_Bits_3_eq_inst1_out; +wire magma_Bits_3_eq_inst2_out; +wire magma_Bits_3_eq_inst3_out; +wire magma_Bits_3_eq_inst4_out; +wire magma_Bits_3_eq_inst5_out; +wire magma_Bits_3_eq_inst6_out; +wire magma_Bits_3_eq_inst7_out; +wire [15:0] magma_SInt_16_add_inst0_out; +wire [15:0] magma_SInt_16_and_inst0_out; +wire [15:0] magma_SInt_16_neg_inst0_out; +wire [15:0] magma_SInt_16_neg_inst1_out; +wire [15:0] magma_SInt_16_neg_inst2_out; +wire magma_SInt_16_sge_inst0_out; +wire [15:0] magma_SInt_16_shl_inst0_out; +wire [15:0] magma_SInt_16_sub_inst0_out; +wire [15:0] magma_SInt_16_sub_inst1_out; +wire [8:0] magma_SInt_9_neg_inst0_out; +wire [8:0] magma_SInt_9_neg_inst1_out; +wire magma_SInt_9_slt_inst0_out; +wire magma_SInt_9_slt_inst1_out; +wire magma_SInt_9_slt_inst2_out; +wire [8:0] magma_SInt_9_sub_inst0_out; +wire [8:0] magma_SInt_9_sub_inst1_out; +wire [8:0] magma_SInt_9_sub_inst2_out; +wire [7:0] magma_UInt_8_add_inst0_out; +wire [7:0] magma_UInt_8_add_inst1_out; +wire [7:0] magma_UInt_8_sub_inst0_out; +wire magma_UInt_8_ugt_inst0_out; +wire [8:0] magma_UInt_9_add_inst0_out; +wire magma_UInt_9_ugt_inst0_out; +PEGEN_Mux2xBit Mux2xBit_inst0 ( + .I0(bit_const_0_None_out), + .I1(bit_const_0_None_out), + .S(magma_Bits_3_eq_inst7_out), + .O(Mux2xBit_inst0_O) +); +PEGEN_Mux2xBit Mux2xBit_inst1 ( + .I0(bit_const_0_None_out), + .I1(magma_UInt_8_ugt_inst0_out), + .S(magma_Bits_3_eq_inst6_out), + .O(Mux2xBit_inst1_O) +); +PEGEN_Mux2xBit Mux2xBit_inst10 ( + .I0(Mux2xBit_inst8_O), + .I1(bit_const_0_None_out), + .S(magma_Bits_3_eq_inst2_out), + .O(Mux2xBit_inst10_O) +); +PEGEN_Mux2xBit Mux2xBit_inst2 ( + .I0(Mux2xBit_inst0_O), + .I1(bit_const_0_None_out), + .S(magma_Bits_3_eq_inst6_out), + .O(Mux2xBit_inst2_O) +); +PEGEN_Mux2xBit Mux2xBit_inst3 ( + .I0(Mux2xBit_inst1_O), + .I1(bit_const_0_None_out), + .S(magma_Bits_3_eq_inst5_out), + .O(Mux2xBit_inst3_O) +); +PEGEN_Mux2xBit Mux2xBit_inst4 ( + .I0(Mux2xBit_inst2_O), + .I1(bit_const_0_None_out), + .S(magma_Bits_3_eq_inst5_out), + .O(Mux2xBit_inst4_O) +); +PEGEN_Mux2xBit Mux2xBit_inst5 ( + .I0(Mux2xBit_inst3_O), + .I1(bit_const_0_None_out), + .S(magma_Bits_3_eq_inst4_out), + .O(Mux2xBit_inst5_O) +); +PEGEN_Mux2xBit Mux2xBit_inst6 ( + .I0(Mux2xBit_inst4_O), + .I1(bit_const_0_None_out), + .S(magma_Bits_3_eq_inst4_out), + .O(Mux2xBit_inst6_O) +); +PEGEN_Mux2xBit Mux2xBit_inst7 ( + .I0(Mux2xBit_inst5_O), + .I1(bit_const_0_None_out), + .S(magma_Bits_3_eq_inst3_out), + .O(Mux2xBit_inst7_O) +); +PEGEN_Mux2xBit Mux2xBit_inst8 ( + .I0(Mux2xBit_inst6_O), + .I1(magma_UInt_9_ugt_inst0_out), + .S(magma_Bits_3_eq_inst3_out), + .O(Mux2xBit_inst8_O) +); +PEGEN_Mux2xBit Mux2xBit_inst9 ( + .I0(Mux2xBit_inst7_O), + .I1(bit_const_0_None_out), + .S(magma_Bits_3_eq_inst2_out), + .O(Mux2xBit_inst9_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst0 ( + .I0(const_0_16_out), + .I1(const_32768_16_out), + .S(magma_SInt_9_slt_inst0_out), + .O(Mux2xBits16_inst0_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst1 ( + .I0(const_0_16_out), + .I1(magma_Bits_16_and_inst0_out), + .S(magma_Bits_1_eq_inst0_out), + .O(Mux2xBits16_inst1_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst10 ( + .I0(magma_Bits_16_and_inst10_out), + .I1(magma_Bits_16_and_inst8_out), + .S(magma_Bits_3_eq_inst6_out), + .O(Mux2xBits16_inst10_O) +); +wire [15:0] Mux2xBits16_inst11_I1; +assign Mux2xBits16_inst11_I1 = {magma_Bits_23_lshr_inst0_out[15],magma_Bits_23_lshr_inst0_out[14],magma_Bits_23_lshr_inst0_out[13],magma_Bits_23_lshr_inst0_out[12],magma_Bits_23_lshr_inst0_out[11],magma_Bits_23_lshr_inst0_out[10],magma_Bits_23_lshr_inst0_out[9],magma_Bits_23_lshr_inst0_out[8],magma_Bits_23_lshr_inst0_out[7],magma_Bits_23_lshr_inst0_out[6],magma_Bits_23_lshr_inst0_out[5],magma_Bits_23_lshr_inst0_out[4],magma_Bits_23_lshr_inst0_out[3],magma_Bits_23_lshr_inst0_out[2],magma_Bits_23_lshr_inst0_out[1],magma_Bits_23_lshr_inst0_out[0]}; +PEGEN_Mux2xBits16 Mux2xBits16_inst11 ( + .I0(magma_Bits_16_and_inst12_out), + .I1(Mux2xBits16_inst11_I1), + .S(magma_Bits_3_eq_inst6_out), + .O(Mux2xBits16_inst11_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst12 ( + .I0(Mux2xBits16_inst9_O), + .I1(magma_Bits_16_or_inst1_out), + .S(magma_Bits_3_eq_inst5_out), + .O(Mux2xBits16_inst12_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst13 ( + .I0(Mux2xBits16_inst8_O), + .I1(magma_Bits_16_and_inst7_out), + .S(magma_Bits_3_eq_inst4_out), + .O(Mux2xBits16_inst13_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst14 ( + .I0(Mux2xBits16_inst12_O), + .I1(magma_Bits_16_or_inst6_out), + .S(magma_Bits_3_eq_inst4_out), + .O(Mux2xBits16_inst14_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst15 ( + .I0(Mux2xBits16_inst10_O), + .I1(magma_Bits_16_and_inst5_out), + .S(magma_Bits_3_eq_inst4_out), + .O(Mux2xBits16_inst15_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst16 ( + .I0(magma_Bits_16_shl_inst2_out), + .I1(magma_Bits_16_shl_inst1_out), + .S(magma_Bits_3_eq_inst3_out), + .O(Mux2xBits16_inst16_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst17 ( + .I0(Mux2xBits16_inst14_O), + .I1(magma_Bits_16_or_inst3_out), + .S(magma_Bits_3_eq_inst3_out), + .O(Mux2xBits16_inst17_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst18 ( + .I0(Mux2xBits16_inst3_O), + .I1(magma_Bits_16_and_inst3_out), + .S(magma_Bits_3_eq_inst3_out), + .O(Mux2xBits16_inst18_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst19 ( + .I0(Mux2xBits16_inst17_O), + .I1(magma_Bits_16_and_inst2_out), + .S(magma_Bits_3_eq_inst2_out), + .O(Mux2xBits16_inst19_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst2 ( + .I0(a), + .I1(magma_SInt_16_neg_inst0_out), + .S(magma_Bit_not_inst8_out), + .O(Mux2xBits16_inst2_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst20 ( + .I0(Mux2xBits16_inst18_O), + .I1(Mux2xBits16_inst3_O), + .S(magma_Bits_3_eq_inst2_out), + .O(Mux2xBits16_inst20_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst3 ( + .I0(Mux2xBits16_inst1_O), + .I1(Mux2xBits16_inst0_O), + .S(magma_Bits_3_eq_inst0_out), + .O(Mux2xBits16_inst3_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst4 ( + .I0(const_0_16_out), + .I1(magma_SInt_16_and_inst0_out), + .S(magma_SInt_16_sge_inst0_out), + .O(Mux2xBits16_inst4_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst5 ( + .I0(Mux2xBits16_inst4_O), + .I1(magma_Bits_16_lshr_inst0_out), + .S(magma_Bits_3_eq_inst1_out), + .O(Mux2xBits16_inst5_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst6 ( + .I0(magma_Bits_16_shl_inst3_out), + .I1(magma_Bits_16_lshr_inst1_out), + .S(magma_SInt_9_slt_inst2_out), + .O(Mux2xBits16_inst6_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst7 ( + .I0(magma_Bits_16_or_inst1_out), + .I1(Mux2xSInt16_inst29_O), + .S(magma_Bits_3_eq_inst7_out), + .O(Mux2xBits16_inst7_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst8 ( + .I0(magma_Bits_16_or_inst8_out), + .I1(magma_Bits_16_or_inst7_out), + .S(magma_Bits_3_eq_inst6_out), + .O(Mux2xBits16_inst8_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst9 ( + .I0(Mux2xBits16_inst7_O), + .I1(Mux2xSInt16_inst28_O), + .S(magma_Bits_3_eq_inst6_out), + .O(Mux2xBits16_inst9_O) +); +PEGEN_Mux2xBits23 Mux2xBits23_inst0 ( + .I0(magma_Bits_23_shl_inst0_out), + .I1(const_0_23_out), + .S(magma_SInt_9_slt_inst1_out), + .O(Mux2xBits23_inst0_O) +); +wire [7:0] Mux2xBits8_inst0_I0; +assign Mux2xBits8_inst0_I0 = {a[14],a[13],a[12],a[11],a[10],a[9],a[8],a[7]}; +wire [7:0] Mux2xBits8_inst0_I1; +assign Mux2xBits8_inst0_I1 = {a[14],a[13],a[12],a[11],a[10],a[9],a[8],a[7]}; +PEGEN_Mux2xBits8 Mux2xBits8_inst0 ( + .I0(Mux2xBits8_inst0_I0), + .I1(Mux2xBits8_inst0_I1), + .S(magma_Bits_3_eq_inst7_out), + .O(Mux2xBits8_inst0_O) +); +wire [7:0] Mux2xBits8_inst1_I1; +assign Mux2xBits8_inst1_I1 = {a[14],a[13],a[12],a[11],a[10],a[9],a[8],a[7]}; +PEGEN_Mux2xBits8 Mux2xBits8_inst1 ( + .I0(Mux2xBits8_inst0_O), + .I1(Mux2xBits8_inst1_I1), + .S(magma_Bits_3_eq_inst6_out), + .O(Mux2xBits8_inst1_O) +); +wire [7:0] Mux2xBits8_inst2_I1; +assign Mux2xBits8_inst2_I1 = {a[14],a[13],a[12],a[11],a[10],a[9],a[8],a[7]}; +PEGEN_Mux2xBits8 Mux2xBits8_inst2 ( + .I0(Mux2xBits8_inst1_O), + .I1(Mux2xBits8_inst2_I1), + .S(magma_Bits_3_eq_inst5_out), + .O(Mux2xBits8_inst2_O) +); +wire [7:0] Mux2xBits8_inst3_I1; +assign Mux2xBits8_inst3_I1 = {a[14],a[13],a[12],a[11],a[10],a[9],a[8],a[7]}; +PEGEN_Mux2xBits8 Mux2xBits8_inst3 ( + .I0(Mux2xBits8_inst2_O), + .I1(Mux2xBits8_inst3_I1), + .S(magma_Bits_3_eq_inst4_out), + .O(Mux2xBits8_inst3_O) +); +wire [7:0] Mux2xBits8_inst4_I1; +assign Mux2xBits8_inst4_I1 = {a[14],a[13],a[12],a[11],a[10],a[9],a[8],a[7]}; +PEGEN_Mux2xBits8 Mux2xBits8_inst4 ( + .I0(Mux2xBits8_inst3_O), + .I1(Mux2xBits8_inst4_I1), + .S(magma_Bits_3_eq_inst3_out), + .O(Mux2xBits8_inst4_O) +); +wire [7:0] Mux2xBits8_inst5_I1; +assign Mux2xBits8_inst5_I1 = {a[14],a[13],a[12],a[11],a[10],a[9],a[8],a[7]}; +PEGEN_Mux2xBits8 Mux2xBits8_inst5 ( + .I0(Mux2xBits8_inst4_O), + .I1(Mux2xBits8_inst5_I1), + .S(magma_Bits_3_eq_inst2_out), + .O(Mux2xBits8_inst5_O) +); +PEGEN_Mux2xSInt16 Mux2xSInt16_inst0 ( + .I0(const_65409_16_out), + .I1(const_0_16_out), + .S(magma_Bit_not_inst0_out), + .O(Mux2xSInt16_inst0_O) +); +PEGEN_Mux2xSInt16 Mux2xSInt16_inst1 ( + .I0(Mux2xSInt16_inst0_O), + .I1(const_1_16_out), + .S(magma_Bit_not_inst1_out), + .O(Mux2xSInt16_inst1_O) +); +PEGEN_Mux2xSInt16 Mux2xSInt16_inst10 ( + .I0(Mux2xSInt16_inst9_O), + .I1(const_2_16_out), + .S(magma_Bit_not_inst11_out), + .O(Mux2xSInt16_inst10_O) +); +PEGEN_Mux2xSInt16 Mux2xSInt16_inst11 ( + .I0(Mux2xSInt16_inst10_O), + .I1(const_3_16_out), + .S(magma_Bit_not_inst12_out), + .O(Mux2xSInt16_inst11_O) +); +PEGEN_Mux2xSInt16 Mux2xSInt16_inst12 ( + .I0(Mux2xSInt16_inst11_O), + .I1(const_4_16_out), + .S(magma_Bit_not_inst13_out), + .O(Mux2xSInt16_inst12_O) +); +PEGEN_Mux2xSInt16 Mux2xSInt16_inst13 ( + .I0(Mux2xSInt16_inst12_O), + .I1(const_5_16_out), + .S(magma_Bit_not_inst14_out), + .O(Mux2xSInt16_inst13_O) +); +PEGEN_Mux2xSInt16 Mux2xSInt16_inst14 ( + .I0(Mux2xSInt16_inst13_O), + .I1(const_6_16_out), + .S(magma_Bit_not_inst15_out), + .O(Mux2xSInt16_inst14_O) +); +PEGEN_Mux2xSInt16 Mux2xSInt16_inst15 ( + .I0(Mux2xSInt16_inst14_O), + .I1(const_7_16_out), + .S(magma_Bit_not_inst16_out), + .O(Mux2xSInt16_inst15_O) +); +PEGEN_Mux2xSInt16 Mux2xSInt16_inst16 ( + .I0(Mux2xSInt16_inst15_O), + .I1(const_8_16_out), + .S(magma_Bit_not_inst17_out), + .O(Mux2xSInt16_inst16_O) +); +PEGEN_Mux2xSInt16 Mux2xSInt16_inst17 ( + .I0(Mux2xSInt16_inst16_O), + .I1(const_9_16_out), + .S(magma_Bit_not_inst18_out), + .O(Mux2xSInt16_inst17_O) +); +PEGEN_Mux2xSInt16 Mux2xSInt16_inst18 ( + .I0(Mux2xSInt16_inst17_O), + .I1(const_10_16_out), + .S(magma_Bit_not_inst19_out), + .O(Mux2xSInt16_inst18_O) +); +PEGEN_Mux2xSInt16 Mux2xSInt16_inst19 ( + .I0(Mux2xSInt16_inst18_O), + .I1(const_11_16_out), + .S(magma_Bit_not_inst20_out), + .O(Mux2xSInt16_inst19_O) +); +PEGEN_Mux2xSInt16 Mux2xSInt16_inst2 ( + .I0(Mux2xSInt16_inst1_O), + .I1(const_2_16_out), + .S(magma_Bit_not_inst2_out), + .O(Mux2xSInt16_inst2_O) +); +PEGEN_Mux2xSInt16 Mux2xSInt16_inst20 ( + .I0(Mux2xSInt16_inst19_O), + .I1(const_12_16_out), + .S(magma_Bit_not_inst21_out), + .O(Mux2xSInt16_inst20_O) +); +PEGEN_Mux2xSInt16 Mux2xSInt16_inst21 ( + .I0(Mux2xSInt16_inst20_O), + .I1(const_13_16_out), + .S(magma_Bit_not_inst22_out), + .O(Mux2xSInt16_inst21_O) +); +PEGEN_Mux2xSInt16 Mux2xSInt16_inst22 ( + .I0(Mux2xSInt16_inst21_O), + .I1(const_14_16_out), + .S(magma_Bit_not_inst23_out), + .O(Mux2xSInt16_inst22_O) +); +PEGEN_Mux2xSInt16 Mux2xSInt16_inst23 ( + .I0(Mux2xSInt16_inst22_O), + .I1(const_15_16_out), + .S(magma_Bit_not_inst24_out), + .O(Mux2xSInt16_inst23_O) +); +PEGEN_Mux2xSInt16 Mux2xSInt16_inst24 ( + .I0(const_32512_16_out), + .I1(const_127_16_out), + .S(magma_Bits_3_eq_inst0_out), + .O(Mux2xSInt16_inst24_O) +); +wire [15:0] Mux2xSInt16_inst25_I1; +assign Mux2xSInt16_inst25_I1 = {Mux2xSInt9_inst0_O[7],Mux2xSInt9_inst0_O[7],Mux2xSInt9_inst0_O[7],Mux2xSInt9_inst0_O[7],Mux2xSInt9_inst0_O[7],Mux2xSInt9_inst0_O[7],Mux2xSInt9_inst0_O[7],Mux2xSInt9_inst0_O[7],Mux2xSInt9_inst0_O[7],Mux2xSInt9_inst0_O[6],Mux2xSInt9_inst0_O[5],Mux2xSInt9_inst0_O[4],Mux2xSInt9_inst0_O[3],Mux2xSInt9_inst0_O[2],Mux2xSInt9_inst0_O[1],Mux2xSInt9_inst0_O[0]}; +PEGEN_Mux2xSInt16 Mux2xSInt16_inst25 ( + .I0(Mux2xBits16_inst2_O), + .I1(Mux2xSInt16_inst25_I1), + .S(magma_Bits_3_eq_inst0_out), + .O(Mux2xSInt16_inst25_O) +); +PEGEN_Mux2xSInt16 Mux2xSInt16_inst26 ( + .I0(magma_SInt_16_sub_inst1_out), + .I1(magma_SInt_16_sub_inst0_out), + .S(magma_Bits_3_eq_inst0_out), + .O(Mux2xSInt16_inst26_O) +); +PEGEN_Mux2xSInt16 Mux2xSInt16_inst27 ( + .I0(Mux2xSInt16_inst23_O), + .I1(Mux2xSInt16_inst7_O), + .S(magma_Bits_3_eq_inst0_out), + .O(Mux2xSInt16_inst27_O) +); +wire [15:0] Mux2xSInt16_inst28_I0; +assign Mux2xSInt16_inst28_I0 = {magma_Bits_23_lshr_inst0_out[15],magma_Bits_23_lshr_inst0_out[14],magma_Bits_23_lshr_inst0_out[13],magma_Bits_23_lshr_inst0_out[12],magma_Bits_23_lshr_inst0_out[11],magma_Bits_23_lshr_inst0_out[10],magma_Bits_23_lshr_inst0_out[9],magma_Bits_23_lshr_inst0_out[8],magma_Bits_23_lshr_inst0_out[7],magma_Bits_23_lshr_inst0_out[6],magma_Bits_23_lshr_inst0_out[5],magma_Bits_23_lshr_inst0_out[4],magma_Bits_23_lshr_inst0_out[3],magma_Bits_23_lshr_inst0_out[2],magma_Bits_23_lshr_inst0_out[1],magma_Bits_23_lshr_inst0_out[0]}; +PEGEN_Mux2xSInt16 Mux2xSInt16_inst28 ( + .I0(Mux2xSInt16_inst28_I0), + .I1(magma_SInt_16_neg_inst1_out), + .S(magma_Bits_16_eq_inst0_out), + .O(Mux2xSInt16_inst28_O) +); +PEGEN_Mux2xSInt16 Mux2xSInt16_inst29 ( + .I0(magma_Bits_16_and_inst12_out), + .I1(magma_SInt_16_neg_inst2_out), + .S(magma_Bits_16_eq_inst1_out), + .O(Mux2xSInt16_inst29_O) +); +PEGEN_Mux2xSInt16 Mux2xSInt16_inst3 ( + .I0(Mux2xSInt16_inst2_O), + .I1(const_3_16_out), + .S(magma_Bit_not_inst3_out), + .O(Mux2xSInt16_inst3_O) +); +PEGEN_Mux2xSInt16 Mux2xSInt16_inst30 ( + .I0(Mux2xSInt16_inst29_O), + .I1(Mux2xSInt16_inst28_O), + .S(magma_Bits_3_eq_inst6_out), + .O(Mux2xSInt16_inst30_O) +); +PEGEN_Mux2xSInt16 Mux2xSInt16_inst4 ( + .I0(Mux2xSInt16_inst3_O), + .I1(const_4_16_out), + .S(magma_Bit_not_inst4_out), + .O(Mux2xSInt16_inst4_O) +); +PEGEN_Mux2xSInt16 Mux2xSInt16_inst5 ( + .I0(Mux2xSInt16_inst4_O), + .I1(const_5_16_out), + .S(magma_Bit_not_inst5_out), + .O(Mux2xSInt16_inst5_O) +); +PEGEN_Mux2xSInt16 Mux2xSInt16_inst6 ( + .I0(Mux2xSInt16_inst5_O), + .I1(const_6_16_out), + .S(magma_Bit_not_inst6_out), + .O(Mux2xSInt16_inst6_O) +); +PEGEN_Mux2xSInt16 Mux2xSInt16_inst7 ( + .I0(Mux2xSInt16_inst6_O), + .I1(const_7_16_out), + .S(magma_Bit_not_inst7_out), + .O(Mux2xSInt16_inst7_O) +); +PEGEN_Mux2xSInt16 Mux2xSInt16_inst8 ( + .I0(const_65409_16_out), + .I1(const_0_16_out), + .S(magma_Bit_not_inst9_out), + .O(Mux2xSInt16_inst8_O) +); +PEGEN_Mux2xSInt16 Mux2xSInt16_inst9 ( + .I0(Mux2xSInt16_inst8_O), + .I1(const_1_16_out), + .S(magma_Bit_not_inst10_out), + .O(Mux2xSInt16_inst9_O) +); +PEGEN_Mux2xSInt9 Mux2xSInt9_inst0 ( + .I0(magma_SInt_9_sub_inst0_out), + .I1(magma_SInt_9_neg_inst0_out), + .S(magma_SInt_9_slt_inst0_out), + .O(Mux2xSInt9_inst0_O) +); +wire [8:0] Mux2xSInt9_inst1_I0; +assign Mux2xSInt9_inst1_I0 = {bit_const_0_None_out,a[14],a[13],a[12],a[11],a[10],a[9],a[8],a[7]}; +wire [8:0] Mux2xSInt9_inst1_I1; +assign Mux2xSInt9_inst1_I1 = {bit_const_0_None_out,a[14],a[13],a[12],a[11],a[10],a[9],a[8],a[7]}; +PEGEN_Mux2xSInt9 Mux2xSInt9_inst1 ( + .I0(Mux2xSInt9_inst1_I0), + .I1(Mux2xSInt9_inst1_I1), + .S(magma_Bits_3_eq_inst7_out), + .O(Mux2xSInt9_inst1_O) +); +PEGEN_Mux2xSInt9 Mux2xSInt9_inst10 ( + .I0(Mux2xSInt9_inst8_O), + .I1(magma_SInt_9_sub_inst0_out), + .S(magma_Bits_3_eq_inst3_out), + .O(Mux2xSInt9_inst10_O) +); +wire [8:0] Mux2xSInt9_inst11_I1; +assign Mux2xSInt9_inst11_I1 = {bit_const_0_None_out,a[14],a[13],a[12],a[11],a[10],a[9],a[8],a[7]}; +PEGEN_Mux2xSInt9 Mux2xSInt9_inst11 ( + .I0(Mux2xSInt9_inst9_O), + .I1(Mux2xSInt9_inst11_I1), + .S(magma_Bits_3_eq_inst2_out), + .O(Mux2xSInt9_inst11_O) +); +PEGEN_Mux2xSInt9 Mux2xSInt9_inst12 ( + .I0(Mux2xSInt9_inst10_O), + .I1(magma_SInt_9_sub_inst0_out), + .S(magma_Bits_3_eq_inst2_out), + .O(Mux2xSInt9_inst12_O) +); +PEGEN_Mux2xSInt9 Mux2xSInt9_inst2 ( + .I0(magma_SInt_9_sub_inst0_out), + .I1(magma_SInt_9_sub_inst2_out), + .S(magma_Bits_3_eq_inst7_out), + .O(Mux2xSInt9_inst2_O) +); +wire [8:0] Mux2xSInt9_inst3_I1; +assign Mux2xSInt9_inst3_I1 = {bit_const_0_None_out,a[14],a[13],a[12],a[11],a[10],a[9],a[8],a[7]}; +PEGEN_Mux2xSInt9 Mux2xSInt9_inst3 ( + .I0(Mux2xSInt9_inst1_O), + .I1(Mux2xSInt9_inst3_I1), + .S(magma_Bits_3_eq_inst6_out), + .O(Mux2xSInt9_inst3_O) +); +PEGEN_Mux2xSInt9 Mux2xSInt9_inst4 ( + .I0(Mux2xSInt9_inst2_O), + .I1(magma_SInt_9_sub_inst1_out), + .S(magma_Bits_3_eq_inst6_out), + .O(Mux2xSInt9_inst4_O) +); +wire [8:0] Mux2xSInt9_inst5_I1; +assign Mux2xSInt9_inst5_I1 = {bit_const_0_None_out,a[14],a[13],a[12],a[11],a[10],a[9],a[8],a[7]}; +PEGEN_Mux2xSInt9 Mux2xSInt9_inst5 ( + .I0(Mux2xSInt9_inst3_O), + .I1(Mux2xSInt9_inst5_I1), + .S(magma_Bits_3_eq_inst5_out), + .O(Mux2xSInt9_inst5_O) +); +PEGEN_Mux2xSInt9 Mux2xSInt9_inst6 ( + .I0(Mux2xSInt9_inst4_O), + .I1(magma_SInt_9_sub_inst0_out), + .S(magma_Bits_3_eq_inst5_out), + .O(Mux2xSInt9_inst6_O) +); +wire [8:0] Mux2xSInt9_inst7_I1; +assign Mux2xSInt9_inst7_I1 = {bit_const_0_None_out,a[14],a[13],a[12],a[11],a[10],a[9],a[8],a[7]}; +PEGEN_Mux2xSInt9 Mux2xSInt9_inst7 ( + .I0(Mux2xSInt9_inst5_O), + .I1(Mux2xSInt9_inst7_I1), + .S(magma_Bits_3_eq_inst4_out), + .O(Mux2xSInt9_inst7_O) +); +PEGEN_Mux2xSInt9 Mux2xSInt9_inst8 ( + .I0(Mux2xSInt9_inst6_O), + .I1(magma_SInt_9_sub_inst0_out), + .S(magma_Bits_3_eq_inst4_out), + .O(Mux2xSInt9_inst8_O) +); +wire [8:0] Mux2xSInt9_inst9_I1; +assign Mux2xSInt9_inst9_I1 = {bit_const_0_None_out,a[14],a[13],a[12],a[11],a[10],a[9],a[8],a[7]}; +PEGEN_Mux2xSInt9 Mux2xSInt9_inst9 ( + .I0(Mux2xSInt9_inst7_O), + .I1(Mux2xSInt9_inst9_I1), + .S(magma_Bits_3_eq_inst3_out), + .O(Mux2xSInt9_inst9_O) +); +PEGEN_corebit_const #( + .value(1'b0) +) bit_const_0_None ( + .out(bit_const_0_None_out) +); +PEGEN_corebit_const #( + .value(1'b1) +) bit_const_1_None ( + .out(bit_const_1_None_out) +); +PEGEN_coreir_const #( + .value(16'h0000), + .width(16) +) const_0_16 ( + .out(const_0_16_out) +); +PEGEN_coreir_const #( + .value(23'h000000), + .width(23) +) const_0_23 ( + .out(const_0_23_out) +); +PEGEN_coreir_const #( + .value(3'h0), + .width(3) +) const_0_3 ( + .out(const_0_3_out) +); +PEGEN_coreir_const #( + .value(9'h000), + .width(9) +) const_0_9 ( + .out(const_0_9_out) +); +PEGEN_coreir_const #( + .value(16'h000a), + .width(16) +) const_10_16 ( + .out(const_10_16_out) +); +PEGEN_coreir_const #( + .value(16'h000b), + .width(16) +) const_11_16 ( + .out(const_11_16_out) +); +PEGEN_coreir_const #( + .value(16'h007f), + .width(16) +) const_127_16 ( + .out(const_127_16_out) +); +PEGEN_coreir_const #( + .value(8'h7f), + .width(8) +) const_127_8 ( + .out(const_127_8_out) +); +PEGEN_coreir_const #( + .value(9'h07f), + .width(9) +) const_127_9 ( + .out(const_127_9_out) +); +PEGEN_coreir_const #( + .value(16'h0080), + .width(16) +) const_128_16 ( + .out(const_128_16_out) +); +PEGEN_coreir_const #( + .value(16'h000c), + .width(16) +) const_12_16 ( + .out(const_12_16_out) +); +PEGEN_coreir_const #( + .value(16'h000d), + .width(16) +) const_13_16 ( + .out(const_13_16_out) +); +PEGEN_coreir_const #( + .value(8'h8e), + .width(8) +) const_142_8 ( + .out(const_142_8_out) +); +PEGEN_coreir_const #( + .value(16'h000e), + .width(16) +) const_14_16 ( + .out(const_14_16_out) +); +PEGEN_coreir_const #( + .value(16'h000f), + .width(16) +) const_15_16 ( + .out(const_15_16_out) +); +PEGEN_coreir_const #( + .value(1'h1), + .width(1) +) const_1_1 ( + .out(const_1_1_out) +); +PEGEN_coreir_const #( + .value(16'h0001), + .width(16) +) const_1_16 ( + .out(const_1_16_out) +); +PEGEN_coreir_const #( + .value(3'h1), + .width(3) +) const_1_3 ( + .out(const_1_3_out) +); +PEGEN_coreir_const #( + .value(9'h0ff), + .width(9) +) const_255_9 ( + .out(const_255_9_out) +); +PEGEN_coreir_const #( + .value(16'h0002), + .width(16) +) const_2_16 ( + .out(const_2_16_out) +); +PEGEN_coreir_const #( + .value(3'h2), + .width(3) +) const_2_3 ( + .out(const_2_3_out) +); +PEGEN_coreir_const #( + .value(16'h7f00), + .width(16) +) const_32512_16 ( + .out(const_32512_16_out) +); +PEGEN_coreir_const #( + .value(16'h7f80), + .width(16) +) const_32640_16 ( + .out(const_32640_16_out) +); +PEGEN_coreir_const #( + .value(16'h8000), + .width(16) +) const_32768_16 ( + .out(const_32768_16_out) +); +PEGEN_coreir_const #( + .value(16'h0003), + .width(16) +) const_3_16 ( + .out(const_3_16_out) +); +PEGEN_coreir_const #( + .value(3'h3), + .width(3) +) const_3_3 ( + .out(const_3_3_out) +); +PEGEN_coreir_const #( + .value(16'h0004), + .width(16) +) const_4_16 ( + .out(const_4_16_out) +); +PEGEN_coreir_const #( + .value(3'h4), + .width(3) +) const_4_3 ( + .out(const_4_3_out) +); +PEGEN_coreir_const #( + .value(16'h0005), + .width(16) +) const_5_16 ( + .out(const_5_16_out) +); +PEGEN_coreir_const #( + .value(3'h5), + .width(3) +) const_5_3 ( + .out(const_5_3_out) +); +PEGEN_coreir_const #( + .value(16'hff81), + .width(16) +) const_65409_16 ( + .out(const_65409_16_out) +); +PEGEN_coreir_const #( + .value(16'h0006), + .width(16) +) const_6_16 ( + .out(const_6_16_out) +); +PEGEN_coreir_const #( + .value(3'h6), + .width(3) +) const_6_3 ( + .out(const_6_3_out) +); +PEGEN_coreir_const #( + .value(16'h0007), + .width(16) +) const_7_16 ( + .out(const_7_16_out) +); +PEGEN_coreir_const #( + .value(23'h000007), + .width(23) +) const_7_23 ( + .out(const_7_23_out) +); +PEGEN_coreir_const #( + .value(16'h0008), + .width(16) +) const_8_16 ( + .out(const_8_16_out) +); +PEGEN_coreir_const #( + .value(16'h0009), + .width(16) +) const_9_16 ( + .out(const_9_16_out) +); +PEGEN_corebit_not magma_Bit_not_inst0 ( + .in(magma_Bit_xor_inst0_out), + .out(magma_Bit_not_inst0_out) +); +PEGEN_corebit_not magma_Bit_not_inst1 ( + .in(magma_Bit_xor_inst1_out), + .out(magma_Bit_not_inst1_out) +); +PEGEN_corebit_not magma_Bit_not_inst10 ( + .in(magma_Bit_xor_inst10_out), + .out(magma_Bit_not_inst10_out) +); +PEGEN_corebit_not magma_Bit_not_inst11 ( + .in(magma_Bit_xor_inst11_out), + .out(magma_Bit_not_inst11_out) +); +PEGEN_corebit_not magma_Bit_not_inst12 ( + .in(magma_Bit_xor_inst12_out), + .out(magma_Bit_not_inst12_out) +); +PEGEN_corebit_not magma_Bit_not_inst13 ( + .in(magma_Bit_xor_inst13_out), + .out(magma_Bit_not_inst13_out) +); +PEGEN_corebit_not magma_Bit_not_inst14 ( + .in(magma_Bit_xor_inst14_out), + .out(magma_Bit_not_inst14_out) +); +PEGEN_corebit_not magma_Bit_not_inst15 ( + .in(magma_Bit_xor_inst15_out), + .out(magma_Bit_not_inst15_out) +); +PEGEN_corebit_not magma_Bit_not_inst16 ( + .in(magma_Bit_xor_inst16_out), + .out(magma_Bit_not_inst16_out) +); +PEGEN_corebit_not magma_Bit_not_inst17 ( + .in(magma_Bit_xor_inst17_out), + .out(magma_Bit_not_inst17_out) +); +PEGEN_corebit_not magma_Bit_not_inst18 ( + .in(magma_Bit_xor_inst18_out), + .out(magma_Bit_not_inst18_out) +); +PEGEN_corebit_not magma_Bit_not_inst19 ( + .in(magma_Bit_xor_inst19_out), + .out(magma_Bit_not_inst19_out) +); +PEGEN_corebit_not magma_Bit_not_inst2 ( + .in(magma_Bit_xor_inst2_out), + .out(magma_Bit_not_inst2_out) +); +PEGEN_corebit_not magma_Bit_not_inst20 ( + .in(magma_Bit_xor_inst20_out), + .out(magma_Bit_not_inst20_out) +); +PEGEN_corebit_not magma_Bit_not_inst21 ( + .in(magma_Bit_xor_inst21_out), + .out(magma_Bit_not_inst21_out) +); +PEGEN_corebit_not magma_Bit_not_inst22 ( + .in(magma_Bit_xor_inst22_out), + .out(magma_Bit_not_inst22_out) +); +PEGEN_corebit_not magma_Bit_not_inst23 ( + .in(magma_Bit_xor_inst23_out), + .out(magma_Bit_not_inst23_out) +); +PEGEN_corebit_not magma_Bit_not_inst24 ( + .in(magma_Bit_xor_inst24_out), + .out(magma_Bit_not_inst24_out) +); +PEGEN_corebit_not magma_Bit_not_inst3 ( + .in(magma_Bit_xor_inst3_out), + .out(magma_Bit_not_inst3_out) +); +PEGEN_corebit_not magma_Bit_not_inst4 ( + .in(magma_Bit_xor_inst4_out), + .out(magma_Bit_not_inst4_out) +); +PEGEN_corebit_not magma_Bit_not_inst5 ( + .in(magma_Bit_xor_inst5_out), + .out(magma_Bit_not_inst5_out) +); +PEGEN_corebit_not magma_Bit_not_inst6 ( + .in(magma_Bit_xor_inst6_out), + .out(magma_Bit_not_inst6_out) +); +PEGEN_corebit_not magma_Bit_not_inst7 ( + .in(magma_Bit_xor_inst7_out), + .out(magma_Bit_not_inst7_out) +); +PEGEN_corebit_not magma_Bit_not_inst8 ( + .in(magma_Bit_xor_inst8_out), + .out(magma_Bit_not_inst8_out) +); +PEGEN_corebit_not magma_Bit_not_inst9 ( + .in(magma_Bit_xor_inst9_out), + .out(magma_Bit_not_inst9_out) +); +PEGEN_corebit_xor magma_Bit_xor_inst0 ( + .in0(Mux2xSInt9_inst0_O[0]), + .in1(bit_const_1_None_out), + .out(magma_Bit_xor_inst0_out) +); +PEGEN_corebit_xor magma_Bit_xor_inst1 ( + .in0(Mux2xSInt9_inst0_O[1]), + .in1(bit_const_1_None_out), + .out(magma_Bit_xor_inst1_out) +); +PEGEN_corebit_xor magma_Bit_xor_inst10 ( + .in0(Mux2xBits16_inst2_O[1]), + .in1(bit_const_1_None_out), + .out(magma_Bit_xor_inst10_out) +); +PEGEN_corebit_xor magma_Bit_xor_inst11 ( + .in0(Mux2xBits16_inst2_O[2]), + .in1(bit_const_1_None_out), + .out(magma_Bit_xor_inst11_out) +); +PEGEN_corebit_xor magma_Bit_xor_inst12 ( + .in0(Mux2xBits16_inst2_O[3]), + .in1(bit_const_1_None_out), + .out(magma_Bit_xor_inst12_out) +); +PEGEN_corebit_xor magma_Bit_xor_inst13 ( + .in0(Mux2xBits16_inst2_O[4]), + .in1(bit_const_1_None_out), + .out(magma_Bit_xor_inst13_out) +); +PEGEN_corebit_xor magma_Bit_xor_inst14 ( + .in0(Mux2xBits16_inst2_O[5]), + .in1(bit_const_1_None_out), + .out(magma_Bit_xor_inst14_out) +); +PEGEN_corebit_xor magma_Bit_xor_inst15 ( + .in0(Mux2xBits16_inst2_O[6]), + .in1(bit_const_1_None_out), + .out(magma_Bit_xor_inst15_out) +); +PEGEN_corebit_xor magma_Bit_xor_inst16 ( + .in0(Mux2xBits16_inst2_O[7]), + .in1(bit_const_1_None_out), + .out(magma_Bit_xor_inst16_out) +); +PEGEN_corebit_xor magma_Bit_xor_inst17 ( + .in0(Mux2xBits16_inst2_O[8]), + .in1(bit_const_1_None_out), + .out(magma_Bit_xor_inst17_out) +); +PEGEN_corebit_xor magma_Bit_xor_inst18 ( + .in0(Mux2xBits16_inst2_O[9]), + .in1(bit_const_1_None_out), + .out(magma_Bit_xor_inst18_out) +); +PEGEN_corebit_xor magma_Bit_xor_inst19 ( + .in0(Mux2xBits16_inst2_O[10]), + .in1(bit_const_1_None_out), + .out(magma_Bit_xor_inst19_out) +); +PEGEN_corebit_xor magma_Bit_xor_inst2 ( + .in0(Mux2xSInt9_inst0_O[2]), + .in1(bit_const_1_None_out), + .out(magma_Bit_xor_inst2_out) +); +PEGEN_corebit_xor magma_Bit_xor_inst20 ( + .in0(Mux2xBits16_inst2_O[11]), + .in1(bit_const_1_None_out), + .out(magma_Bit_xor_inst20_out) +); +PEGEN_corebit_xor magma_Bit_xor_inst21 ( + .in0(Mux2xBits16_inst2_O[12]), + .in1(bit_const_1_None_out), + .out(magma_Bit_xor_inst21_out) +); +PEGEN_corebit_xor magma_Bit_xor_inst22 ( + .in0(Mux2xBits16_inst2_O[13]), + .in1(bit_const_1_None_out), + .out(magma_Bit_xor_inst22_out) +); +PEGEN_corebit_xor magma_Bit_xor_inst23 ( + .in0(Mux2xBits16_inst2_O[14]), + .in1(bit_const_1_None_out), + .out(magma_Bit_xor_inst23_out) +); +PEGEN_corebit_xor magma_Bit_xor_inst24 ( + .in0(Mux2xBits16_inst2_O[15]), + .in1(bit_const_1_None_out), + .out(magma_Bit_xor_inst24_out) +); +PEGEN_corebit_xor magma_Bit_xor_inst3 ( + .in0(Mux2xSInt9_inst0_O[3]), + .in1(bit_const_1_None_out), + .out(magma_Bit_xor_inst3_out) +); +PEGEN_corebit_xor magma_Bit_xor_inst4 ( + .in0(Mux2xSInt9_inst0_O[4]), + .in1(bit_const_1_None_out), + .out(magma_Bit_xor_inst4_out) +); +PEGEN_corebit_xor magma_Bit_xor_inst5 ( + .in0(Mux2xSInt9_inst0_O[5]), + .in1(bit_const_1_None_out), + .out(magma_Bit_xor_inst5_out) +); +PEGEN_corebit_xor magma_Bit_xor_inst6 ( + .in0(Mux2xSInt9_inst0_O[6]), + .in1(bit_const_1_None_out), + .out(magma_Bit_xor_inst6_out) +); +PEGEN_corebit_xor magma_Bit_xor_inst7 ( + .in0(Mux2xSInt9_inst0_O[7]), + .in1(bit_const_1_None_out), + .out(magma_Bit_xor_inst7_out) +); +PEGEN_corebit_xor magma_Bit_xor_inst8 ( + .in0(Mux2xBits16_inst1_O[15]), + .in1(bit_const_1_None_out), + .out(magma_Bit_xor_inst8_out) +); +PEGEN_corebit_xor magma_Bit_xor_inst9 ( + .in0(Mux2xBits16_inst2_O[0]), + .in1(bit_const_1_None_out), + .out(magma_Bit_xor_inst9_out) +); +PEGEN_coreir_and #( + .width(16) +) magma_Bits_16_and_inst0 ( + .in0(a), + .in1(const_32768_16_out), + .out(magma_Bits_16_and_inst0_out) +); +PEGEN_coreir_and #( + .width(16) +) magma_Bits_16_and_inst1 ( + .in0(magma_Bits_16_shl_inst0_out), + .in1(const_32640_16_out), + .out(magma_Bits_16_and_inst1_out) +); +PEGEN_coreir_and #( + .width(16) +) magma_Bits_16_and_inst10 ( + .in0(a), + .in1(const_32768_16_out), + .out(magma_Bits_16_and_inst10_out) +); +PEGEN_coreir_and #( + .width(16) +) magma_Bits_16_and_inst11 ( + .in0(a), + .in1(const_127_16_out), + .out(magma_Bits_16_and_inst11_out) +); +PEGEN_coreir_and #( + .width(16) +) magma_Bits_16_and_inst12 ( + .in0(Mux2xBits16_inst6_O), + .in1(const_127_16_out), + .out(magma_Bits_16_and_inst12_out) +); +PEGEN_coreir_and #( + .width(16) +) magma_Bits_16_and_inst2 ( + .in0(a), + .in1(const_127_16_out), + .out(magma_Bits_16_and_inst2_out) +); +PEGEN_coreir_and #( + .width(16) +) magma_Bits_16_and_inst3 ( + .in0(a), + .in1(const_32768_16_out), + .out(magma_Bits_16_and_inst3_out) +); +PEGEN_coreir_and #( + .width(16) +) magma_Bits_16_and_inst4 ( + .in0(a), + .in1(const_127_16_out), + .out(magma_Bits_16_and_inst4_out) +); +PEGEN_coreir_and #( + .width(16) +) magma_Bits_16_and_inst5 ( + .in0(a), + .in1(const_32768_16_out), + .out(magma_Bits_16_and_inst5_out) +); +PEGEN_coreir_and #( + .width(16) +) magma_Bits_16_and_inst6 ( + .in0(b), + .in1(const_32768_16_out), + .out(magma_Bits_16_and_inst6_out) +); +PEGEN_coreir_and #( + .width(16) +) magma_Bits_16_and_inst7 ( + .in0(a), + .in1(const_127_16_out), + .out(magma_Bits_16_and_inst7_out) +); +PEGEN_coreir_and #( + .width(16) +) magma_Bits_16_and_inst8 ( + .in0(a), + .in1(const_32768_16_out), + .out(magma_Bits_16_and_inst8_out) +); +PEGEN_coreir_and #( + .width(16) +) magma_Bits_16_and_inst9 ( + .in0(a), + .in1(const_127_16_out), + .out(magma_Bits_16_and_inst9_out) +); +PEGEN_coreir_eq #( + .width(16) +) magma_Bits_16_eq_inst0 ( + .in0(magma_Bits_16_and_inst8_out), + .in1(const_32768_16_out), + .out(magma_Bits_16_eq_inst0_out) +); +PEGEN_coreir_eq #( + .width(16) +) magma_Bits_16_eq_inst1 ( + .in0(magma_Bits_16_and_inst10_out), + .in1(const_32768_16_out), + .out(magma_Bits_16_eq_inst1_out) +); +PEGEN_coreir_lshr #( + .width(16) +) magma_Bits_16_lshr_inst0 ( + .in0(Mux2xBits16_inst4_O), + .in1(const_8_16_out), + .out(magma_Bits_16_lshr_inst0_out) +); +wire [15:0] magma_Bits_16_lshr_inst1_in1; +assign magma_Bits_16_lshr_inst1_in1 = {bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,magma_SInt_9_neg_inst1_out}; +PEGEN_coreir_lshr #( + .width(16) +) magma_Bits_16_lshr_inst1 ( + .in0(magma_Bits_16_or_inst8_out), + .in1(magma_Bits_16_lshr_inst1_in1), + .out(magma_Bits_16_lshr_inst1_out) +); +PEGEN_coreir_or #( + .width(16) +) magma_Bits_16_or_inst0 ( + .in0(Mux2xBits16_inst3_O), + .in1(magma_Bits_16_and_inst1_out), + .out(magma_Bits_16_or_inst0_out) +); +PEGEN_coreir_or #( + .width(16) +) magma_Bits_16_or_inst1 ( + .in0(magma_Bits_16_or_inst0_out), + .in1(Mux2xBits16_inst5_O), + .out(magma_Bits_16_or_inst1_out) +); +PEGEN_coreir_or #( + .width(16) +) magma_Bits_16_or_inst2 ( + .in0(magma_Bits_16_and_inst3_out), + .in1(magma_Bits_16_shl_inst1_out), + .out(magma_Bits_16_or_inst2_out) +); +PEGEN_coreir_or #( + .width(16) +) magma_Bits_16_or_inst3 ( + .in0(magma_Bits_16_or_inst2_out), + .in1(magma_Bits_16_and_inst4_out), + .out(magma_Bits_16_or_inst3_out) +); +PEGEN_coreir_or #( + .width(16) +) magma_Bits_16_or_inst4 ( + .in0(magma_Bits_16_and_inst5_out), + .in1(magma_Bits_16_and_inst6_out), + .out(magma_Bits_16_or_inst4_out) +); +PEGEN_coreir_or #( + .width(16) +) magma_Bits_16_or_inst5 ( + .in0(magma_Bits_16_or_inst4_out), + .in1(magma_Bits_16_shl_inst2_out), + .out(magma_Bits_16_or_inst5_out) +); +PEGEN_coreir_or #( + .width(16) +) magma_Bits_16_or_inst6 ( + .in0(magma_Bits_16_or_inst5_out), + .in1(magma_Bits_16_and_inst7_out), + .out(magma_Bits_16_or_inst6_out) +); +PEGEN_coreir_or #( + .width(16) +) magma_Bits_16_or_inst7 ( + .in0(magma_Bits_16_and_inst9_out), + .in1(const_128_16_out), + .out(magma_Bits_16_or_inst7_out) +); +PEGEN_coreir_or #( + .width(16) +) magma_Bits_16_or_inst8 ( + .in0(magma_Bits_16_and_inst11_out), + .in1(const_128_16_out), + .out(magma_Bits_16_or_inst8_out) +); +PEGEN_coreir_shl #( + .width(16) +) magma_Bits_16_shl_inst0 ( + .in0(magma_SInt_16_add_inst0_out), + .in1(const_7_16_out), + .out(magma_Bits_16_shl_inst0_out) +); +wire [15:0] magma_Bits_16_shl_inst1_in0; +assign magma_Bits_16_shl_inst1_in0 = {bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,magma_UInt_8_add_inst0_out}; +PEGEN_coreir_shl #( + .width(16) +) magma_Bits_16_shl_inst1 ( + .in0(magma_Bits_16_shl_inst1_in0), + .in1(const_7_16_out), + .out(magma_Bits_16_shl_inst1_out) +); +wire [15:0] magma_Bits_16_shl_inst2_in0; +assign magma_Bits_16_shl_inst2_in0 = {bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,magma_UInt_8_add_inst1_out}; +PEGEN_coreir_shl #( + .width(16) +) magma_Bits_16_shl_inst2 ( + .in0(magma_Bits_16_shl_inst2_in0), + .in1(const_7_16_out), + .out(magma_Bits_16_shl_inst2_out) +); +wire [15:0] magma_Bits_16_shl_inst3_in1; +assign magma_Bits_16_shl_inst3_in1 = {bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,magma_SInt_9_sub_inst2_out}; +PEGEN_coreir_shl #( + .width(16) +) magma_Bits_16_shl_inst3 ( + .in0(magma_Bits_16_or_inst8_out), + .in1(magma_Bits_16_shl_inst3_in1), + .out(magma_Bits_16_shl_inst3_out) +); +PEGEN_coreir_eq #( + .width(1) +) magma_Bits_1_eq_inst0 ( + .in0(signed_), + .in1(const_1_1_out), + .out(magma_Bits_1_eq_inst0_out) +); +PEGEN_coreir_lshr #( + .width(23) +) magma_Bits_23_lshr_inst0 ( + .in0(Mux2xBits23_inst0_O), + .in1(const_7_23_out), + .out(magma_Bits_23_lshr_inst0_out) +); +wire [22:0] magma_Bits_23_shl_inst0_in0; +assign magma_Bits_23_shl_inst0_in0 = {bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,magma_Bits_16_or_inst7_out}; +wire [22:0] magma_Bits_23_shl_inst0_in1; +assign magma_Bits_23_shl_inst0_in1 = {bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,magma_SInt_9_sub_inst1_out}; +PEGEN_coreir_shl #( + .width(23) +) magma_Bits_23_shl_inst0 ( + .in0(magma_Bits_23_shl_inst0_in0), + .in1(magma_Bits_23_shl_inst0_in1), + .out(magma_Bits_23_shl_inst0_out) +); +PEGEN_coreir_eq #( + .width(3) +) magma_Bits_3_eq_inst0 ( + .in0(op), + .in1(const_3_3_out), + .out(magma_Bits_3_eq_inst0_out) +); +PEGEN_coreir_eq #( + .width(3) +) magma_Bits_3_eq_inst1 ( + .in0(op), + .in1(const_6_3_out), + .out(magma_Bits_3_eq_inst1_out) +); +PEGEN_coreir_eq #( + .width(3) +) magma_Bits_3_eq_inst2 ( + .in0(op), + .in1(const_0_3_out), + .out(magma_Bits_3_eq_inst2_out) +); +PEGEN_coreir_eq #( + .width(3) +) magma_Bits_3_eq_inst3 ( + .in0(op), + .in1(const_1_3_out), + .out(magma_Bits_3_eq_inst3_out) +); +PEGEN_coreir_eq #( + .width(3) +) magma_Bits_3_eq_inst4 ( + .in0(op), + .in1(const_2_3_out), + .out(magma_Bits_3_eq_inst4_out) +); +PEGEN_coreir_eq #( + .width(3) +) magma_Bits_3_eq_inst5 ( + .in0(op), + .in1(const_3_3_out), + .out(magma_Bits_3_eq_inst5_out) +); +PEGEN_coreir_eq #( + .width(3) +) magma_Bits_3_eq_inst6 ( + .in0(op), + .in1(const_4_3_out), + .out(magma_Bits_3_eq_inst6_out) +); +PEGEN_coreir_eq #( + .width(3) +) magma_Bits_3_eq_inst7 ( + .in0(op), + .in1(const_5_3_out), + .out(magma_Bits_3_eq_inst7_out) +); +PEGEN_coreir_add #( + .width(16) +) magma_SInt_16_add_inst0 ( + .in0(Mux2xSInt16_inst27_O), + .in1(const_127_16_out), + .out(magma_SInt_16_add_inst0_out) +); +PEGEN_coreir_and #( + .width(16) +) magma_SInt_16_and_inst0 ( + .in0(magma_SInt_16_shl_inst0_out), + .in1(Mux2xSInt16_inst24_O), + .out(magma_SInt_16_and_inst0_out) +); +PEGEN_coreir_neg #( + .width(16) +) magma_SInt_16_neg_inst0 ( + .in(a), + .out(magma_SInt_16_neg_inst0_out) +); +wire [15:0] magma_SInt_16_neg_inst1_in; +assign magma_SInt_16_neg_inst1_in = {magma_Bits_23_lshr_inst0_out[15],magma_Bits_23_lshr_inst0_out[14],magma_Bits_23_lshr_inst0_out[13],magma_Bits_23_lshr_inst0_out[12],magma_Bits_23_lshr_inst0_out[11],magma_Bits_23_lshr_inst0_out[10],magma_Bits_23_lshr_inst0_out[9],magma_Bits_23_lshr_inst0_out[8],magma_Bits_23_lshr_inst0_out[7],magma_Bits_23_lshr_inst0_out[6],magma_Bits_23_lshr_inst0_out[5],magma_Bits_23_lshr_inst0_out[4],magma_Bits_23_lshr_inst0_out[3],magma_Bits_23_lshr_inst0_out[2],magma_Bits_23_lshr_inst0_out[1],magma_Bits_23_lshr_inst0_out[0]}; +PEGEN_coreir_neg #( + .width(16) +) magma_SInt_16_neg_inst1 ( + .in(magma_SInt_16_neg_inst1_in), + .out(magma_SInt_16_neg_inst1_out) +); +PEGEN_coreir_neg #( + .width(16) +) magma_SInt_16_neg_inst2 ( + .in(magma_Bits_16_and_inst12_out), + .out(magma_SInt_16_neg_inst2_out) +); +PEGEN_coreir_sge #( + .width(16) +) magma_SInt_16_sge_inst0 ( + .in0(Mux2xSInt16_inst27_O), + .in1(const_0_16_out), + .out(magma_SInt_16_sge_inst0_out) +); +PEGEN_coreir_shl #( + .width(16) +) magma_SInt_16_shl_inst0 ( + .in0(Mux2xSInt16_inst25_O), + .in1(Mux2xSInt16_inst26_O), + .out(magma_SInt_16_shl_inst0_out) +); +PEGEN_coreir_sub #( + .width(16) +) magma_SInt_16_sub_inst0 ( + .in0(const_7_16_out), + .in1(Mux2xSInt16_inst7_O), + .out(magma_SInt_16_sub_inst0_out) +); +PEGEN_coreir_sub #( + .width(16) +) magma_SInt_16_sub_inst1 ( + .in0(const_15_16_out), + .in1(Mux2xSInt16_inst23_O), + .out(magma_SInt_16_sub_inst1_out) +); +PEGEN_coreir_neg #( + .width(9) +) magma_SInt_9_neg_inst0 ( + .in(magma_SInt_9_sub_inst0_out), + .out(magma_SInt_9_neg_inst0_out) +); +PEGEN_coreir_neg #( + .width(9) +) magma_SInt_9_neg_inst1 ( + .in(magma_SInt_9_sub_inst2_out), + .out(magma_SInt_9_neg_inst1_out) +); +PEGEN_coreir_slt #( + .width(9) +) magma_SInt_9_slt_inst0 ( + .in0(magma_SInt_9_sub_inst0_out), + .in1(const_0_9_out), + .out(magma_SInt_9_slt_inst0_out) +); +PEGEN_coreir_slt #( + .width(9) +) magma_SInt_9_slt_inst1 ( + .in0(magma_SInt_9_sub_inst1_out), + .in1(const_0_9_out), + .out(magma_SInt_9_slt_inst1_out) +); +PEGEN_coreir_slt #( + .width(9) +) magma_SInt_9_slt_inst2 ( + .in0(magma_SInt_9_sub_inst2_out), + .in1(const_0_9_out), + .out(magma_SInt_9_slt_inst2_out) +); +wire [8:0] magma_SInt_9_sub_inst0_in0; +assign magma_SInt_9_sub_inst0_in0 = {bit_const_0_None_out,a[14],a[13],a[12],a[11],a[10],a[9],a[8],a[7]}; +PEGEN_coreir_sub #( + .width(9) +) magma_SInt_9_sub_inst0 ( + .in0(magma_SInt_9_sub_inst0_in0), + .in1(const_127_9_out), + .out(magma_SInt_9_sub_inst0_out) +); +wire [8:0] magma_SInt_9_sub_inst1_in0; +assign magma_SInt_9_sub_inst1_in0 = {bit_const_0_None_out,a[14],a[13],a[12],a[11],a[10],a[9],a[8],a[7]}; +PEGEN_coreir_sub #( + .width(9) +) magma_SInt_9_sub_inst1 ( + .in0(magma_SInt_9_sub_inst1_in0), + .in1(const_127_9_out), + .out(magma_SInt_9_sub_inst1_out) +); +wire [8:0] magma_SInt_9_sub_inst2_in0; +assign magma_SInt_9_sub_inst2_in0 = {bit_const_0_None_out,a[14],a[13],a[12],a[11],a[10],a[9],a[8],a[7]}; +PEGEN_coreir_sub #( + .width(9) +) magma_SInt_9_sub_inst2 ( + .in0(magma_SInt_9_sub_inst2_in0), + .in1(const_127_9_out), + .out(magma_SInt_9_sub_inst2_out) +); +wire [7:0] magma_UInt_8_add_inst0_in0; +assign magma_UInt_8_add_inst0_in0 = {a[14],a[13],a[12],a[11],a[10],a[9],a[8],a[7]}; +wire [7:0] magma_UInt_8_add_inst0_in1; +assign magma_UInt_8_add_inst0_in1 = {b[7],b[6],b[5],b[4],b[3],b[2],b[1],b[0]}; +PEGEN_coreir_add #( + .width(8) +) magma_UInt_8_add_inst0 ( + .in0(magma_UInt_8_add_inst0_in0), + .in1(magma_UInt_8_add_inst0_in1), + .out(magma_UInt_8_add_inst0_out) +); +PEGEN_coreir_add #( + .width(8) +) magma_UInt_8_add_inst1 ( + .in0(magma_UInt_8_sub_inst0_out), + .in1(const_127_8_out), + .out(magma_UInt_8_add_inst1_out) +); +wire [7:0] magma_UInt_8_sub_inst0_in0; +assign magma_UInt_8_sub_inst0_in0 = {a[14],a[13],a[12],a[11],a[10],a[9],a[8],a[7]}; +wire [7:0] magma_UInt_8_sub_inst0_in1; +assign magma_UInt_8_sub_inst0_in1 = {b[14],b[13],b[12],b[11],b[10],b[9],b[8],b[7]}; +PEGEN_coreir_sub #( + .width(8) +) magma_UInt_8_sub_inst0 ( + .in0(magma_UInt_8_sub_inst0_in0), + .in1(magma_UInt_8_sub_inst0_in1), + .out(magma_UInt_8_sub_inst0_out) +); +wire [7:0] magma_UInt_8_ugt_inst0_in0; +assign magma_UInt_8_ugt_inst0_in0 = {a[14],a[13],a[12],a[11],a[10],a[9],a[8],a[7]}; +PEGEN_coreir_ugt #( + .width(8) +) magma_UInt_8_ugt_inst0 ( + .in0(magma_UInt_8_ugt_inst0_in0), + .in1(const_142_8_out), + .out(magma_UInt_8_ugt_inst0_out) +); +wire [8:0] magma_UInt_9_add_inst0_in0; +assign magma_UInt_9_add_inst0_in0 = {bit_const_0_None_out,a[14],a[13],a[12],a[11],a[10],a[9],a[8],a[7]}; +wire [8:0] magma_UInt_9_add_inst0_in1; +assign magma_UInt_9_add_inst0_in1 = {b[8],b[7],b[6],b[5],b[4],b[3],b[2],b[1],b[0]}; +PEGEN_coreir_add #( + .width(9) +) magma_UInt_9_add_inst0 ( + .in0(magma_UInt_9_add_inst0_in0), + .in1(magma_UInt_9_add_inst0_in1), + .out(magma_UInt_9_add_inst0_out) +); +PEGEN_coreir_ugt #( + .width(9) +) magma_UInt_9_ugt_inst0 ( + .in0(magma_UInt_9_add_inst0_out), + .in1(const_255_9_out), + .out(magma_UInt_9_ugt_inst0_out) +); +assign res = Mux2xBits16_inst19_O; +assign res_p = Mux2xBit_inst10_O; +assign V = Mux2xBit_inst9_O; +endmodule + +module PEGEN_Cond ( + input [4:0] code, + input alu, + input lut, + input Z, + input N, + input C, + input V, + output O, + input CLK, + input ASYNCRESET +); +wire Mux2xBit_inst0_O; +wire Mux2xBit_inst1_O; +wire Mux2xBit_inst10_O; +wire Mux2xBit_inst11_O; +wire Mux2xBit_inst12_O; +wire Mux2xBit_inst13_O; +wire Mux2xBit_inst14_O; +wire Mux2xBit_inst15_O; +wire Mux2xBit_inst16_O; +wire Mux2xBit_inst17_O; +wire Mux2xBit_inst18_O; +wire Mux2xBit_inst2_O; +wire Mux2xBit_inst3_O; +wire Mux2xBit_inst4_O; +wire Mux2xBit_inst5_O; +wire Mux2xBit_inst6_O; +wire Mux2xBit_inst7_O; +wire Mux2xBit_inst8_O; +wire Mux2xBit_inst9_O; +wire [4:0] const_0_5_out; +wire [4:0] const_10_5_out; +wire [4:0] const_11_5_out; +wire [4:0] const_12_5_out; +wire [4:0] const_13_5_out; +wire [4:0] const_14_5_out; +wire [4:0] const_15_5_out; +wire [4:0] const_16_5_out; +wire [4:0] const_17_5_out; +wire [4:0] const_18_5_out; +wire [4:0] const_1_5_out; +wire [4:0] const_2_5_out; +wire [4:0] const_3_5_out; +wire [4:0] const_4_5_out; +wire [4:0] const_5_5_out; +wire [4:0] const_6_5_out; +wire [4:0] const_7_5_out; +wire [4:0] const_8_5_out; +wire [4:0] const_9_5_out; +wire magma_Bit_and_inst0_out; +wire magma_Bit_and_inst1_out; +wire magma_Bit_and_inst2_out; +wire magma_Bit_and_inst3_out; +wire magma_Bit_not_inst0_out; +wire magma_Bit_not_inst1_out; +wire magma_Bit_not_inst10_out; +wire magma_Bit_not_inst11_out; +wire magma_Bit_not_inst12_out; +wire magma_Bit_not_inst2_out; +wire magma_Bit_not_inst3_out; +wire magma_Bit_not_inst4_out; +wire magma_Bit_not_inst5_out; +wire magma_Bit_not_inst6_out; +wire magma_Bit_not_inst7_out; +wire magma_Bit_not_inst8_out; +wire magma_Bit_not_inst9_out; +wire magma_Bit_or_inst0_out; +wire magma_Bit_or_inst1_out; +wire magma_Bit_or_inst2_out; +wire magma_Bit_or_inst3_out; +wire magma_Bit_or_inst4_out; +wire magma_Bit_or_inst5_out; +wire magma_Bit_xor_inst0_out; +wire magma_Bit_xor_inst1_out; +wire magma_Bit_xor_inst2_out; +wire magma_Bit_xor_inst3_out; +wire magma_Bits_5_eq_inst0_out; +wire magma_Bits_5_eq_inst1_out; +wire magma_Bits_5_eq_inst10_out; +wire magma_Bits_5_eq_inst11_out; +wire magma_Bits_5_eq_inst12_out; +wire magma_Bits_5_eq_inst13_out; +wire magma_Bits_5_eq_inst14_out; +wire magma_Bits_5_eq_inst15_out; +wire magma_Bits_5_eq_inst16_out; +wire magma_Bits_5_eq_inst17_out; +wire magma_Bits_5_eq_inst18_out; +wire magma_Bits_5_eq_inst19_out; +wire magma_Bits_5_eq_inst2_out; +wire magma_Bits_5_eq_inst20_out; +wire magma_Bits_5_eq_inst3_out; +wire magma_Bits_5_eq_inst4_out; +wire magma_Bits_5_eq_inst5_out; +wire magma_Bits_5_eq_inst6_out; +wire magma_Bits_5_eq_inst7_out; +wire magma_Bits_5_eq_inst8_out; +wire magma_Bits_5_eq_inst9_out; +PEGEN_Mux2xBit Mux2xBit_inst0 ( + .I0(magma_Bit_and_inst3_out), + .I1(magma_Bit_or_inst5_out), + .S(magma_Bits_5_eq_inst20_out), + .O(Mux2xBit_inst0_O) +); +PEGEN_Mux2xBit Mux2xBit_inst1 ( + .I0(Mux2xBit_inst0_O), + .I1(magma_Bit_and_inst2_out), + .S(magma_Bits_5_eq_inst19_out), + .O(Mux2xBit_inst1_O) +); +PEGEN_Mux2xBit Mux2xBit_inst10 ( + .I0(Mux2xBit_inst9_O), + .I1(magma_Bit_and_inst0_out), + .S(magma_Bits_5_eq_inst10_out), + .O(Mux2xBit_inst10_O) +); +PEGEN_Mux2xBit Mux2xBit_inst11 ( + .I0(Mux2xBit_inst10_O), + .I1(magma_Bit_not_inst3_out), + .S(magma_Bits_5_eq_inst9_out), + .O(Mux2xBit_inst11_O) +); +PEGEN_Mux2xBit Mux2xBit_inst12 ( + .I0(Mux2xBit_inst11_O), + .I1(V), + .S(magma_Bits_5_eq_inst8_out), + .O(Mux2xBit_inst12_O) +); +PEGEN_Mux2xBit Mux2xBit_inst13 ( + .I0(Mux2xBit_inst12_O), + .I1(magma_Bit_not_inst2_out), + .S(magma_Bits_5_eq_inst7_out), + .O(Mux2xBit_inst13_O) +); +PEGEN_Mux2xBit Mux2xBit_inst14 ( + .I0(Mux2xBit_inst13_O), + .I1(N), + .S(magma_Bits_5_eq_inst6_out), + .O(Mux2xBit_inst14_O) +); +PEGEN_Mux2xBit Mux2xBit_inst15 ( + .I0(Mux2xBit_inst14_O), + .I1(magma_Bit_not_inst1_out), + .S(magma_Bit_or_inst1_out), + .O(Mux2xBit_inst15_O) +); +PEGEN_Mux2xBit Mux2xBit_inst16 ( + .I0(Mux2xBit_inst15_O), + .I1(C), + .S(magma_Bit_or_inst0_out), + .O(Mux2xBit_inst16_O) +); +PEGEN_Mux2xBit Mux2xBit_inst17 ( + .I0(Mux2xBit_inst16_O), + .I1(magma_Bit_not_inst0_out), + .S(magma_Bits_5_eq_inst1_out), + .O(Mux2xBit_inst17_O) +); +PEGEN_Mux2xBit Mux2xBit_inst18 ( + .I0(Mux2xBit_inst17_O), + .I1(Z), + .S(magma_Bits_5_eq_inst0_out), + .O(Mux2xBit_inst18_O) +); +PEGEN_Mux2xBit Mux2xBit_inst2 ( + .I0(Mux2xBit_inst1_O), + .I1(magma_Bit_or_inst4_out), + .S(magma_Bits_5_eq_inst18_out), + .O(Mux2xBit_inst2_O) +); +PEGEN_Mux2xBit Mux2xBit_inst3 ( + .I0(Mux2xBit_inst2_O), + .I1(lut), + .S(magma_Bits_5_eq_inst17_out), + .O(Mux2xBit_inst3_O) +); +PEGEN_Mux2xBit Mux2xBit_inst4 ( + .I0(Mux2xBit_inst3_O), + .I1(alu), + .S(magma_Bits_5_eq_inst16_out), + .O(Mux2xBit_inst4_O) +); +PEGEN_Mux2xBit Mux2xBit_inst5 ( + .I0(Mux2xBit_inst4_O), + .I1(magma_Bit_or_inst3_out), + .S(magma_Bits_5_eq_inst15_out), + .O(Mux2xBit_inst5_O) +); +PEGEN_Mux2xBit Mux2xBit_inst6 ( + .I0(Mux2xBit_inst5_O), + .I1(magma_Bit_and_inst1_out), + .S(magma_Bits_5_eq_inst14_out), + .O(Mux2xBit_inst6_O) +); +PEGEN_Mux2xBit Mux2xBit_inst7 ( + .I0(Mux2xBit_inst6_O), + .I1(magma_Bit_xor_inst1_out), + .S(magma_Bits_5_eq_inst13_out), + .O(Mux2xBit_inst7_O) +); +PEGEN_Mux2xBit Mux2xBit_inst8 ( + .I0(Mux2xBit_inst7_O), + .I1(magma_Bit_not_inst6_out), + .S(magma_Bits_5_eq_inst12_out), + .O(Mux2xBit_inst8_O) +); +PEGEN_Mux2xBit Mux2xBit_inst9 ( + .I0(Mux2xBit_inst8_O), + .I1(magma_Bit_or_inst2_out), + .S(magma_Bits_5_eq_inst11_out), + .O(Mux2xBit_inst9_O) +); +PEGEN_coreir_const #( + .value(5'h00), + .width(5) +) const_0_5 ( + .out(const_0_5_out) +); +PEGEN_coreir_const #( + .value(5'h0a), + .width(5) +) const_10_5 ( + .out(const_10_5_out) +); +PEGEN_coreir_const #( + .value(5'h0b), + .width(5) +) const_11_5 ( + .out(const_11_5_out) +); +PEGEN_coreir_const #( + .value(5'h0c), + .width(5) +) const_12_5 ( + .out(const_12_5_out) +); +PEGEN_coreir_const #( + .value(5'h0d), + .width(5) +) const_13_5 ( + .out(const_13_5_out) +); +PEGEN_coreir_const #( + .value(5'h0e), + .width(5) +) const_14_5 ( + .out(const_14_5_out) +); +PEGEN_coreir_const #( + .value(5'h0f), + .width(5) +) const_15_5 ( + .out(const_15_5_out) +); +PEGEN_coreir_const #( + .value(5'h10), + .width(5) +) const_16_5 ( + .out(const_16_5_out) +); +PEGEN_coreir_const #( + .value(5'h11), + .width(5) +) const_17_5 ( + .out(const_17_5_out) +); +PEGEN_coreir_const #( + .value(5'h12), + .width(5) +) const_18_5 ( + .out(const_18_5_out) +); +PEGEN_coreir_const #( + .value(5'h01), + .width(5) +) const_1_5 ( + .out(const_1_5_out) +); +PEGEN_coreir_const #( + .value(5'h02), + .width(5) +) const_2_5 ( + .out(const_2_5_out) +); +PEGEN_coreir_const #( + .value(5'h03), + .width(5) +) const_3_5 ( + .out(const_3_5_out) +); +PEGEN_coreir_const #( + .value(5'h04), + .width(5) +) const_4_5 ( + .out(const_4_5_out) +); +PEGEN_coreir_const #( + .value(5'h05), + .width(5) +) const_5_5 ( + .out(const_5_5_out) +); +PEGEN_coreir_const #( + .value(5'h06), + .width(5) +) const_6_5 ( + .out(const_6_5_out) +); +PEGEN_coreir_const #( + .value(5'h07), + .width(5) +) const_7_5 ( + .out(const_7_5_out) +); +PEGEN_coreir_const #( + .value(5'h08), + .width(5) +) const_8_5 ( + .out(const_8_5_out) +); +PEGEN_coreir_const #( + .value(5'h09), + .width(5) +) const_9_5 ( + .out(const_9_5_out) +); +PEGEN_corebit_and magma_Bit_and_inst0 ( + .in0(C), + .in1(magma_Bit_not_inst4_out), + .out(magma_Bit_and_inst0_out) +); +PEGEN_corebit_and magma_Bit_and_inst1 ( + .in0(magma_Bit_not_inst7_out), + .in1(magma_Bit_not_inst8_out), + .out(magma_Bit_and_inst1_out) +); +PEGEN_corebit_and magma_Bit_and_inst2 ( + .in0(magma_Bit_not_inst10_out), + .in1(magma_Bit_not_inst11_out), + .out(magma_Bit_and_inst2_out) +); +PEGEN_corebit_and magma_Bit_and_inst3 ( + .in0(N), + .in1(magma_Bit_not_inst12_out), + .out(magma_Bit_and_inst3_out) +); +PEGEN_corebit_not magma_Bit_not_inst0 ( + .in(Z), + .out(magma_Bit_not_inst0_out) +); +PEGEN_corebit_not magma_Bit_not_inst1 ( + .in(C), + .out(magma_Bit_not_inst1_out) +); +PEGEN_corebit_not magma_Bit_not_inst10 ( + .in(N), + .out(magma_Bit_not_inst10_out) +); +PEGEN_corebit_not magma_Bit_not_inst11 ( + .in(Z), + .out(magma_Bit_not_inst11_out) +); +PEGEN_corebit_not magma_Bit_not_inst12 ( + .in(Z), + .out(magma_Bit_not_inst12_out) +); +PEGEN_corebit_not magma_Bit_not_inst2 ( + .in(N), + .out(magma_Bit_not_inst2_out) +); +PEGEN_corebit_not magma_Bit_not_inst3 ( + .in(V), + .out(magma_Bit_not_inst3_out) +); +PEGEN_corebit_not magma_Bit_not_inst4 ( + .in(Z), + .out(magma_Bit_not_inst4_out) +); +PEGEN_corebit_not magma_Bit_not_inst5 ( + .in(C), + .out(magma_Bit_not_inst5_out) +); +PEGEN_corebit_not magma_Bit_not_inst6 ( + .in(magma_Bit_xor_inst0_out), + .out(magma_Bit_not_inst6_out) +); +PEGEN_corebit_not magma_Bit_not_inst7 ( + .in(Z), + .out(magma_Bit_not_inst7_out) +); +PEGEN_corebit_not magma_Bit_not_inst8 ( + .in(magma_Bit_xor_inst2_out), + .out(magma_Bit_not_inst8_out) +); +PEGEN_corebit_not magma_Bit_not_inst9 ( + .in(N), + .out(magma_Bit_not_inst9_out) +); +PEGEN_corebit_or magma_Bit_or_inst0 ( + .in0(magma_Bits_5_eq_inst2_out), + .in1(magma_Bits_5_eq_inst3_out), + .out(magma_Bit_or_inst0_out) +); +PEGEN_corebit_or magma_Bit_or_inst1 ( + .in0(magma_Bits_5_eq_inst4_out), + .in1(magma_Bits_5_eq_inst5_out), + .out(magma_Bit_or_inst1_out) +); +PEGEN_corebit_or magma_Bit_or_inst2 ( + .in0(magma_Bit_not_inst5_out), + .in1(Z), + .out(magma_Bit_or_inst2_out) +); +PEGEN_corebit_or magma_Bit_or_inst3 ( + .in0(Z), + .in1(magma_Bit_xor_inst3_out), + .out(magma_Bit_or_inst3_out) +); +PEGEN_corebit_or magma_Bit_or_inst4 ( + .in0(magma_Bit_not_inst9_out), + .in1(Z), + .out(magma_Bit_or_inst4_out) +); +PEGEN_corebit_or magma_Bit_or_inst5 ( + .in0(N), + .in1(Z), + .out(magma_Bit_or_inst5_out) +); +PEGEN_corebit_xor magma_Bit_xor_inst0 ( + .in0(N), + .in1(V), + .out(magma_Bit_xor_inst0_out) +); +PEGEN_corebit_xor magma_Bit_xor_inst1 ( + .in0(N), + .in1(V), + .out(magma_Bit_xor_inst1_out) +); +PEGEN_corebit_xor magma_Bit_xor_inst2 ( + .in0(N), + .in1(V), + .out(magma_Bit_xor_inst2_out) +); +PEGEN_corebit_xor magma_Bit_xor_inst3 ( + .in0(N), + .in1(V), + .out(magma_Bit_xor_inst3_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst0 ( + .in0(code), + .in1(const_0_5_out), + .out(magma_Bits_5_eq_inst0_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst1 ( + .in0(code), + .in1(const_1_5_out), + .out(magma_Bits_5_eq_inst1_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst10 ( + .in0(code), + .in1(const_8_5_out), + .out(magma_Bits_5_eq_inst10_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst11 ( + .in0(code), + .in1(const_9_5_out), + .out(magma_Bits_5_eq_inst11_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst12 ( + .in0(code), + .in1(const_10_5_out), + .out(magma_Bits_5_eq_inst12_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst13 ( + .in0(code), + .in1(const_11_5_out), + .out(magma_Bits_5_eq_inst13_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst14 ( + .in0(code), + .in1(const_12_5_out), + .out(magma_Bits_5_eq_inst14_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst15 ( + .in0(code), + .in1(const_13_5_out), + .out(magma_Bits_5_eq_inst15_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst16 ( + .in0(code), + .in1(const_15_5_out), + .out(magma_Bits_5_eq_inst16_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst17 ( + .in0(code), + .in1(const_14_5_out), + .out(magma_Bits_5_eq_inst17_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst18 ( + .in0(code), + .in1(const_16_5_out), + .out(magma_Bits_5_eq_inst18_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst19 ( + .in0(code), + .in1(const_17_5_out), + .out(magma_Bits_5_eq_inst19_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst2 ( + .in0(code), + .in1(const_2_5_out), + .out(magma_Bits_5_eq_inst2_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst20 ( + .in0(code), + .in1(const_18_5_out), + .out(magma_Bits_5_eq_inst20_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst3 ( + .in0(code), + .in1(const_2_5_out), + .out(magma_Bits_5_eq_inst3_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst4 ( + .in0(code), + .in1(const_3_5_out), + .out(magma_Bits_5_eq_inst4_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst5 ( + .in0(code), + .in1(const_3_5_out), + .out(magma_Bits_5_eq_inst5_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst6 ( + .in0(code), + .in1(const_4_5_out), + .out(magma_Bits_5_eq_inst6_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst7 ( + .in0(code), + .in1(const_5_5_out), + .out(magma_Bits_5_eq_inst7_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst8 ( + .in0(code), + .in1(const_6_5_out), + .out(magma_Bits_5_eq_inst8_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst9 ( + .in0(code), + .in1(const_7_5_out), + .out(magma_Bits_5_eq_inst9_out) +); +assign O = Mux2xBit_inst18_O; +endmodule + +module PEGEN_ALU ( + input [4:0] alu, + input [0:0] signed_, + input [15:0] a, + input [15:0] b, + input [15:0] c, + input d, + output [15:0] res, + output res_p, + output Z, + output N, + output C, + output V, + input CLK, + input ASYNCRESET +); +wire Mux2xBit_inst0_O; +wire Mux2xBit_inst1_O; +wire Mux2xBit_inst10_O; +wire Mux2xBit_inst11_O; +wire Mux2xBit_inst12_O; +wire Mux2xBit_inst13_O; +wire Mux2xBit_inst14_O; +wire Mux2xBit_inst15_O; +wire Mux2xBit_inst16_O; +wire Mux2xBit_inst17_O; +wire Mux2xBit_inst18_O; +wire Mux2xBit_inst19_O; +wire Mux2xBit_inst2_O; +wire Mux2xBit_inst20_O; +wire Mux2xBit_inst21_O; +wire Mux2xBit_inst22_O; +wire Mux2xBit_inst23_O; +wire Mux2xBit_inst3_O; +wire Mux2xBit_inst4_O; +wire Mux2xBit_inst5_O; +wire Mux2xBit_inst6_O; +wire Mux2xBit_inst7_O; +wire Mux2xBit_inst8_O; +wire Mux2xBit_inst9_O; +wire [15:0] Mux2xBits16_inst0_O; +wire [15:0] Mux2xBits16_inst1_O; +wire [15:0] Mux2xBits16_inst10_O; +wire [15:0] Mux2xBits16_inst11_O; +wire [15:0] Mux2xBits16_inst12_O; +wire [15:0] Mux2xBits16_inst13_O; +wire [15:0] Mux2xBits16_inst14_O; +wire [15:0] Mux2xBits16_inst15_O; +wire [15:0] Mux2xBits16_inst16_O; +wire [15:0] Mux2xBits16_inst17_O; +wire [15:0] Mux2xBits16_inst18_O; +wire [15:0] Mux2xBits16_inst19_O; +wire [15:0] Mux2xBits16_inst2_O; +wire [15:0] Mux2xBits16_inst20_O; +wire [15:0] Mux2xBits16_inst21_O; +wire [15:0] Mux2xBits16_inst3_O; +wire [15:0] Mux2xBits16_inst4_O; +wire [15:0] Mux2xBits16_inst5_O; +wire [15:0] Mux2xBits16_inst6_O; +wire [15:0] Mux2xBits16_inst7_O; +wire [15:0] Mux2xBits16_inst8_O; +wire [15:0] Mux2xBits16_inst9_O; +wire [15:0] Mux2xUInt16_inst0_O; +wire [31:0] Mux2xUInt32_inst0_O; +wire [31:0] Mux2xUInt32_inst1_O; +wire bit_const_0_None_out; +wire bit_const_1_None_out; +wire [15:0] const_0_16_out; +wire [4:0] const_0_5_out; +wire [4:0] const_10_5_out; +wire [4:0] const_11_5_out; +wire [4:0] const_12_5_out; +wire [4:0] const_13_5_out; +wire [4:0] const_14_5_out; +wire [4:0] const_15_5_out; +wire [4:0] const_16_5_out; +wire [4:0] const_17_5_out; +wire [4:0] const_18_5_out; +wire [4:0] const_19_5_out; +wire [0:0] const_1_1_out; +wire [4:0] const_1_5_out; +wire [4:0] const_2_5_out; +wire [4:0] const_3_5_out; +wire [4:0] const_4_5_out; +wire [4:0] const_5_5_out; +wire [4:0] const_6_5_out; +wire [4:0] const_7_5_out; +wire [4:0] const_8_5_out; +wire [4:0] const_9_5_out; +wire magma_Bit_and_inst0_out; +wire magma_Bit_and_inst1_out; +wire magma_Bit_and_inst2_out; +wire magma_Bit_and_inst3_out; +wire magma_Bit_not_inst0_out; +wire magma_Bit_not_inst1_out; +wire magma_Bit_not_inst2_out; +wire magma_Bit_or_inst0_out; +wire magma_Bit_or_inst1_out; +wire magma_Bit_or_inst10_out; +wire magma_Bit_or_inst11_out; +wire magma_Bit_or_inst12_out; +wire magma_Bit_or_inst13_out; +wire magma_Bit_or_inst2_out; +wire magma_Bit_or_inst3_out; +wire magma_Bit_or_inst4_out; +wire magma_Bit_or_inst5_out; +wire magma_Bit_or_inst6_out; +wire magma_Bit_or_inst7_out; +wire magma_Bit_or_inst8_out; +wire magma_Bit_or_inst9_out; +wire [15:0] magma_Bits_16_and_inst0_out; +wire [15:0] magma_Bits_16_not_inst0_out; +wire [15:0] magma_Bits_16_not_inst1_out; +wire [15:0] magma_Bits_16_or_inst0_out; +wire [15:0] magma_Bits_16_shl_inst0_out; +wire [15:0] magma_Bits_16_xor_inst0_out; +wire magma_Bits_1_eq_inst0_out; +wire magma_Bits_1_eq_inst1_out; +wire magma_Bits_1_eq_inst2_out; +wire magma_Bits_1_eq_inst3_out; +wire magma_Bits_5_eq_inst0_out; +wire magma_Bits_5_eq_inst1_out; +wire magma_Bits_5_eq_inst10_out; +wire magma_Bits_5_eq_inst11_out; +wire magma_Bits_5_eq_inst12_out; +wire magma_Bits_5_eq_inst13_out; +wire magma_Bits_5_eq_inst14_out; +wire magma_Bits_5_eq_inst15_out; +wire magma_Bits_5_eq_inst16_out; +wire magma_Bits_5_eq_inst17_out; +wire magma_Bits_5_eq_inst18_out; +wire magma_Bits_5_eq_inst19_out; +wire magma_Bits_5_eq_inst2_out; +wire magma_Bits_5_eq_inst20_out; +wire magma_Bits_5_eq_inst21_out; +wire magma_Bits_5_eq_inst22_out; +wire magma_Bits_5_eq_inst23_out; +wire magma_Bits_5_eq_inst24_out; +wire magma_Bits_5_eq_inst25_out; +wire magma_Bits_5_eq_inst26_out; +wire magma_Bits_5_eq_inst27_out; +wire magma_Bits_5_eq_inst28_out; +wire magma_Bits_5_eq_inst29_out; +wire magma_Bits_5_eq_inst3_out; +wire magma_Bits_5_eq_inst30_out; +wire magma_Bits_5_eq_inst4_out; +wire magma_Bits_5_eq_inst5_out; +wire magma_Bits_5_eq_inst6_out; +wire magma_Bits_5_eq_inst7_out; +wire magma_Bits_5_eq_inst8_out; +wire magma_Bits_5_eq_inst9_out; +wire [15:0] magma_SInt_16_ashr_inst0_out; +wire magma_SInt_16_eq_inst0_out; +wire [15:0] magma_SInt_16_neg_inst0_out; +wire magma_SInt_16_sge_inst0_out; +wire magma_SInt_16_sle_inst0_out; +wire magma_SInt_16_sle_inst1_out; +wire [15:0] magma_UInt_16_lshr_inst0_out; +wire magma_UInt_16_uge_inst0_out; +wire magma_UInt_16_ule_inst0_out; +wire [16:0] magma_UInt_17_add_inst0_out; +wire [16:0] magma_UInt_17_add_inst1_out; +wire [16:0] magma_UInt_17_add_inst2_out; +wire [16:0] magma_UInt_17_add_inst3_out; +wire [31:0] magma_UInt_32_mul_inst0_out; +PEGEN_Mux2xBit Mux2xBit_inst0 ( + .I0(magma_UInt_16_ule_inst0_out), + .I1(magma_SInt_16_sle_inst0_out), + .S(magma_Bits_1_eq_inst1_out), + .O(Mux2xBit_inst0_O) +); +PEGEN_Mux2xBit Mux2xBit_inst1 ( + .I0(magma_UInt_16_uge_inst0_out), + .I1(magma_SInt_16_sge_inst0_out), + .S(magma_Bits_1_eq_inst2_out), + .O(Mux2xBit_inst1_O) +); +PEGEN_Mux2xBit Mux2xBit_inst10 ( + .I0(Mux2xBit_inst9_O), + .I1(bit_const_0_None_out), + .S(magma_Bits_5_eq_inst18_out), + .O(Mux2xBit_inst10_O) +); +PEGEN_Mux2xBit Mux2xBit_inst11 ( + .I0(Mux2xBit_inst10_O), + .I1(a[15]), + .S(magma_Bits_5_eq_inst17_out), + .O(Mux2xBit_inst11_O) +); +PEGEN_Mux2xBit Mux2xBit_inst12 ( + .I0(bit_const_0_None_out), + .I1(bit_const_0_None_out), + .S(magma_Bits_5_eq_inst16_out), + .O(Mux2xBit_inst12_O) +); +PEGEN_Mux2xBit Mux2xBit_inst13 ( + .I0(bit_const_0_None_out), + .I1(bit_const_0_None_out), + .S(magma_Bits_5_eq_inst16_out), + .O(Mux2xBit_inst13_O) +); +PEGEN_Mux2xBit Mux2xBit_inst14 ( + .I0(Mux2xBit_inst11_O), + .I1(bit_const_0_None_out), + .S(magma_Bits_5_eq_inst16_out), + .O(Mux2xBit_inst14_O) +); +PEGEN_Mux2xBit Mux2xBit_inst15 ( + .I0(Mux2xBit_inst12_O), + .I1(bit_const_0_None_out), + .S(magma_Bits_5_eq_inst15_out), + .O(Mux2xBit_inst15_O) +); +PEGEN_Mux2xBit Mux2xBit_inst16 ( + .I0(Mux2xBit_inst13_O), + .I1(bit_const_0_None_out), + .S(magma_Bits_5_eq_inst15_out), + .O(Mux2xBit_inst16_O) +); +PEGEN_Mux2xBit Mux2xBit_inst17 ( + .I0(Mux2xBit_inst14_O), + .I1(bit_const_0_None_out), + .S(magma_Bits_5_eq_inst15_out), + .O(Mux2xBit_inst17_O) +); +PEGEN_Mux2xBit Mux2xBit_inst18 ( + .I0(Mux2xBit_inst15_O), + .I1(bit_const_0_None_out), + .S(magma_Bits_5_eq_inst14_out), + .O(Mux2xBit_inst18_O) +); +PEGEN_Mux2xBit Mux2xBit_inst19 ( + .I0(Mux2xBit_inst16_O), + .I1(bit_const_0_None_out), + .S(magma_Bits_5_eq_inst14_out), + .O(Mux2xBit_inst19_O) +); +PEGEN_Mux2xBit Mux2xBit_inst2 ( + .I0(bit_const_0_None_out), + .I1(bit_const_1_None_out), + .S(magma_Bit_or_inst6_out), + .O(Mux2xBit_inst2_O) +); +PEGEN_Mux2xBit Mux2xBit_inst20 ( + .I0(Mux2xBit_inst17_O), + .I1(bit_const_0_None_out), + .S(magma_Bits_5_eq_inst14_out), + .O(Mux2xBit_inst20_O) +); +PEGEN_Mux2xBit Mux2xBit_inst21 ( + .I0(Mux2xBit_inst18_O), + .I1(magma_UInt_17_add_inst1_out[16]), + .S(magma_Bit_or_inst7_out), + .O(Mux2xBit_inst21_O) +); +PEGEN_Mux2xBit Mux2xBit_inst22 ( + .I0(Mux2xBit_inst19_O), + .I1(magma_Bit_or_inst8_out), + .S(magma_Bit_or_inst7_out), + .O(Mux2xBit_inst22_O) +); +PEGEN_Mux2xBit Mux2xBit_inst23 ( + .I0(Mux2xBit_inst20_O), + .I1(magma_UInt_17_add_inst1_out[16]), + .S(magma_Bit_or_inst7_out), + .O(Mux2xBit_inst23_O) +); +PEGEN_Mux2xBit Mux2xBit_inst3 ( + .I0(bit_const_0_None_out), + .I1(bit_const_0_None_out), + .S(magma_Bits_5_eq_inst30_out), + .O(Mux2xBit_inst3_O) +); +PEGEN_Mux2xBit Mux2xBit_inst4 ( + .I0(Mux2xBit_inst3_O), + .I1(bit_const_0_None_out), + .S(magma_Bit_or_inst13_out), + .O(Mux2xBit_inst4_O) +); +PEGEN_Mux2xBit Mux2xBit_inst5 ( + .I0(Mux2xBit_inst4_O), + .I1(bit_const_0_None_out), + .S(magma_Bits_5_eq_inst23_out), + .O(Mux2xBit_inst5_O) +); +PEGEN_Mux2xBit Mux2xBit_inst6 ( + .I0(Mux2xBit_inst5_O), + .I1(bit_const_0_None_out), + .S(magma_Bits_5_eq_inst22_out), + .O(Mux2xBit_inst6_O) +); +PEGEN_Mux2xBit Mux2xBit_inst7 ( + .I0(Mux2xBit_inst6_O), + .I1(bit_const_0_None_out), + .S(magma_Bits_5_eq_inst21_out), + .O(Mux2xBit_inst7_O) +); +PEGEN_Mux2xBit Mux2xBit_inst8 ( + .I0(Mux2xBit_inst7_O), + .I1(bit_const_0_None_out), + .S(magma_Bits_5_eq_inst20_out), + .O(Mux2xBit_inst8_O) +); +PEGEN_Mux2xBit Mux2xBit_inst9 ( + .I0(Mux2xBit_inst8_O), + .I1(bit_const_0_None_out), + .S(magma_Bits_5_eq_inst19_out), + .O(Mux2xBit_inst9_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst0 ( + .I0(b), + .I1(a), + .S(Mux2xBit_inst0_O), + .O(Mux2xBits16_inst0_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst1 ( + .I0(b), + .I1(Mux2xBits16_inst0_O), + .S(magma_Bits_5_eq_inst0_out), + .O(Mux2xBits16_inst1_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst10 ( + .I0(Mux2xBits16_inst9_O), + .I1(magma_UInt_17_add_inst3_out[15:0]), + .S(magma_Bit_or_inst13_out), + .O(Mux2xBits16_inst10_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst11 ( + .I0(Mux2xBits16_inst10_O), + .I1(magma_Bits_16_shl_inst0_out), + .S(magma_Bits_5_eq_inst23_out), + .O(Mux2xBits16_inst11_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst12 ( + .I0(Mux2xBits16_inst11_O), + .I1(Mux2xBits16_inst4_O), + .S(magma_Bits_5_eq_inst22_out), + .O(Mux2xBits16_inst12_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst13 ( + .I0(Mux2xBits16_inst12_O), + .I1(magma_Bits_16_xor_inst0_out), + .S(magma_Bits_5_eq_inst21_out), + .O(Mux2xBits16_inst13_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst14 ( + .I0(Mux2xBits16_inst13_O), + .I1(magma_Bits_16_or_inst0_out), + .S(magma_Bits_5_eq_inst20_out), + .O(Mux2xBits16_inst14_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst15 ( + .I0(Mux2xBits16_inst14_O), + .I1(magma_Bits_16_and_inst0_out), + .S(magma_Bits_5_eq_inst19_out), + .O(Mux2xBits16_inst15_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst16 ( + .I0(Mux2xBits16_inst15_O), + .I1(Mux2xBits16_inst8_O), + .S(magma_Bits_5_eq_inst18_out), + .O(Mux2xBits16_inst16_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst17 ( + .I0(Mux2xBits16_inst16_O), + .I1(Mux2xBits16_inst7_O), + .S(magma_Bits_5_eq_inst17_out), + .O(Mux2xBits16_inst17_O) +); +wire [15:0] Mux2xBits16_inst18_I1; +assign Mux2xBits16_inst18_I1 = {magma_UInt_32_mul_inst0_out[31],magma_UInt_32_mul_inst0_out[30],magma_UInt_32_mul_inst0_out[29],magma_UInt_32_mul_inst0_out[28],magma_UInt_32_mul_inst0_out[27],magma_UInt_32_mul_inst0_out[26],magma_UInt_32_mul_inst0_out[25],magma_UInt_32_mul_inst0_out[24],magma_UInt_32_mul_inst0_out[23],magma_UInt_32_mul_inst0_out[22],magma_UInt_32_mul_inst0_out[21],magma_UInt_32_mul_inst0_out[20],magma_UInt_32_mul_inst0_out[19],magma_UInt_32_mul_inst0_out[18],magma_UInt_32_mul_inst0_out[17],magma_UInt_32_mul_inst0_out[16]}; +PEGEN_Mux2xBits16 Mux2xBits16_inst18 ( + .I0(Mux2xBits16_inst17_O), + .I1(Mux2xBits16_inst18_I1), + .S(magma_Bits_5_eq_inst16_out), + .O(Mux2xBits16_inst18_O) +); +wire [15:0] Mux2xBits16_inst19_I1; +assign Mux2xBits16_inst19_I1 = {magma_UInt_32_mul_inst0_out[23],magma_UInt_32_mul_inst0_out[22],magma_UInt_32_mul_inst0_out[21],magma_UInt_32_mul_inst0_out[20],magma_UInt_32_mul_inst0_out[19],magma_UInt_32_mul_inst0_out[18],magma_UInt_32_mul_inst0_out[17],magma_UInt_32_mul_inst0_out[16],magma_UInt_32_mul_inst0_out[15],magma_UInt_32_mul_inst0_out[14],magma_UInt_32_mul_inst0_out[13],magma_UInt_32_mul_inst0_out[12],magma_UInt_32_mul_inst0_out[11],magma_UInt_32_mul_inst0_out[10],magma_UInt_32_mul_inst0_out[9],magma_UInt_32_mul_inst0_out[8]}; +PEGEN_Mux2xBits16 Mux2xBits16_inst19 ( + .I0(Mux2xBits16_inst18_O), + .I1(Mux2xBits16_inst19_I1), + .S(magma_Bits_5_eq_inst15_out), + .O(Mux2xBits16_inst19_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst2 ( + .I0(c), + .I1(Mux2xBits16_inst1_O), + .S(Mux2xBit_inst1_O), + .O(Mux2xBits16_inst2_O) +); +wire [15:0] Mux2xBits16_inst20_I1; +assign Mux2xBits16_inst20_I1 = {magma_UInt_32_mul_inst0_out[15],magma_UInt_32_mul_inst0_out[14],magma_UInt_32_mul_inst0_out[13],magma_UInt_32_mul_inst0_out[12],magma_UInt_32_mul_inst0_out[11],magma_UInt_32_mul_inst0_out[10],magma_UInt_32_mul_inst0_out[9],magma_UInt_32_mul_inst0_out[8],magma_UInt_32_mul_inst0_out[7],magma_UInt_32_mul_inst0_out[6],magma_UInt_32_mul_inst0_out[5],magma_UInt_32_mul_inst0_out[4],magma_UInt_32_mul_inst0_out[3],magma_UInt_32_mul_inst0_out[2],magma_UInt_32_mul_inst0_out[1],magma_UInt_32_mul_inst0_out[0]}; +PEGEN_Mux2xBits16 Mux2xBits16_inst20 ( + .I0(Mux2xBits16_inst19_O), + .I1(Mux2xBits16_inst20_I1), + .S(magma_Bits_5_eq_inst14_out), + .O(Mux2xBits16_inst20_O) +); +wire [15:0] Mux2xBits16_inst21_I1; +assign Mux2xBits16_inst21_I1 = {magma_UInt_17_add_inst1_out[15],magma_UInt_17_add_inst1_out[14],magma_UInt_17_add_inst1_out[13],magma_UInt_17_add_inst1_out[12],magma_UInt_17_add_inst1_out[11],magma_UInt_17_add_inst1_out[10],magma_UInt_17_add_inst1_out[9],magma_UInt_17_add_inst1_out[8],magma_UInt_17_add_inst1_out[7],magma_UInt_17_add_inst1_out[6],magma_UInt_17_add_inst1_out[5],magma_UInt_17_add_inst1_out[4],magma_UInt_17_add_inst1_out[3],magma_UInt_17_add_inst1_out[2],magma_UInt_17_add_inst1_out[1],magma_UInt_17_add_inst1_out[0]}; +PEGEN_Mux2xBits16 Mux2xBits16_inst21 ( + .I0(Mux2xBits16_inst20_O), + .I1(Mux2xBits16_inst21_I1), + .S(magma_Bit_or_inst7_out), + .O(Mux2xBits16_inst21_O) +); +wire [15:0] Mux2xBits16_inst3_I1; +assign Mux2xBits16_inst3_I1 = {magma_UInt_32_mul_inst0_out[15],magma_UInt_32_mul_inst0_out[14],magma_UInt_32_mul_inst0_out[13],magma_UInt_32_mul_inst0_out[12],magma_UInt_32_mul_inst0_out[11],magma_UInt_32_mul_inst0_out[10],magma_UInt_32_mul_inst0_out[9],magma_UInt_32_mul_inst0_out[8],magma_UInt_32_mul_inst0_out[7],magma_UInt_32_mul_inst0_out[6],magma_UInt_32_mul_inst0_out[5],magma_UInt_32_mul_inst0_out[4],magma_UInt_32_mul_inst0_out[3],magma_UInt_32_mul_inst0_out[2],magma_UInt_32_mul_inst0_out[1],magma_UInt_32_mul_inst0_out[0]}; +PEGEN_Mux2xBits16 Mux2xBits16_inst3 ( + .I0(a), + .I1(Mux2xBits16_inst3_I1), + .S(magma_Bits_5_eq_inst1_out), + .O(Mux2xBits16_inst3_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst4 ( + .I0(magma_UInt_16_lshr_inst0_out), + .I1(magma_SInt_16_ashr_inst0_out), + .S(magma_Bits_1_eq_inst3_out), + .O(Mux2xBits16_inst4_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst5 ( + .I0(b), + .I1(magma_Bits_16_not_inst0_out), + .S(magma_Bit_or_inst1_out), + .O(Mux2xBits16_inst5_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst6 ( + .I0(c), + .I1(magma_Bits_16_not_inst1_out), + .S(magma_Bit_or_inst6_out), + .O(Mux2xBits16_inst6_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst7 ( + .I0(magma_SInt_16_neg_inst0_out), + .I1(a), + .S(magma_SInt_16_sle_inst1_out), + .O(Mux2xBits16_inst7_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst8 ( + .I0(Mux2xBits16_inst5_O), + .I1(a), + .S(d), + .O(Mux2xBits16_inst8_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst9 ( + .I0(Mux2xBits16_inst4_O), + .I1(Mux2xBits16_inst2_O), + .S(magma_Bits_5_eq_inst30_out), + .O(Mux2xBits16_inst9_O) +); +wire [15:0] Mux2xUInt16_inst0_I0; +assign Mux2xUInt16_inst0_I0 = {magma_UInt_32_mul_inst0_out[15],magma_UInt_32_mul_inst0_out[14],magma_UInt_32_mul_inst0_out[13],magma_UInt_32_mul_inst0_out[12],magma_UInt_32_mul_inst0_out[11],magma_UInt_32_mul_inst0_out[10],magma_UInt_32_mul_inst0_out[9],magma_UInt_32_mul_inst0_out[8],magma_UInt_32_mul_inst0_out[7],magma_UInt_32_mul_inst0_out[6],magma_UInt_32_mul_inst0_out[5],magma_UInt_32_mul_inst0_out[4],magma_UInt_32_mul_inst0_out[3],magma_UInt_32_mul_inst0_out[2],magma_UInt_32_mul_inst0_out[1],magma_UInt_32_mul_inst0_out[0]}; +wire [15:0] Mux2xUInt16_inst0_I1; +assign Mux2xUInt16_inst0_I1 = {magma_UInt_17_add_inst1_out[15],magma_UInt_17_add_inst1_out[14],magma_UInt_17_add_inst1_out[13],magma_UInt_17_add_inst1_out[12],magma_UInt_17_add_inst1_out[11],magma_UInt_17_add_inst1_out[10],magma_UInt_17_add_inst1_out[9],magma_UInt_17_add_inst1_out[8],magma_UInt_17_add_inst1_out[7],magma_UInt_17_add_inst1_out[6],magma_UInt_17_add_inst1_out[5],magma_UInt_17_add_inst1_out[4],magma_UInt_17_add_inst1_out[3],magma_UInt_17_add_inst1_out[2],magma_UInt_17_add_inst1_out[1],magma_UInt_17_add_inst1_out[0]}; +PEGEN_Mux2xUInt16 Mux2xUInt16_inst0 ( + .I0(Mux2xUInt16_inst0_I0), + .I1(Mux2xUInt16_inst0_I1), + .S(magma_Bit_or_inst4_out), + .O(Mux2xUInt16_inst0_O) +); +wire [31:0] Mux2xUInt32_inst0_I0; +assign Mux2xUInt32_inst0_I0 = {bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,a}; +wire [31:0] Mux2xUInt32_inst0_I1; +assign Mux2xUInt32_inst0_I1 = {a[15],a[15],a[15],a[15],a[15],a[15],a[15],a[15],a[15],a[15],a[15],a[15],a[15],a[15],a[15],a[15],a}; +PEGEN_Mux2xUInt32 Mux2xUInt32_inst0 ( + .I0(Mux2xUInt32_inst0_I0), + .I1(Mux2xUInt32_inst0_I1), + .S(magma_Bits_1_eq_inst0_out), + .O(Mux2xUInt32_inst0_O) +); +wire [31:0] Mux2xUInt32_inst1_I0; +assign Mux2xUInt32_inst1_I0 = {bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,b}; +wire [31:0] Mux2xUInt32_inst1_I1; +assign Mux2xUInt32_inst1_I1 = {b[15],b[15],b[15],b[15],b[15],b[15],b[15],b[15],b[15],b[15],b[15],b[15],b[15],b[15],b[15],b[15],b}; +PEGEN_Mux2xUInt32 Mux2xUInt32_inst1 ( + .I0(Mux2xUInt32_inst1_I0), + .I1(Mux2xUInt32_inst1_I1), + .S(magma_Bits_1_eq_inst0_out), + .O(Mux2xUInt32_inst1_O) +); +PEGEN_corebit_const #( + .value(1'b0) +) bit_const_0_None ( + .out(bit_const_0_None_out) +); +PEGEN_corebit_const #( + .value(1'b1) +) bit_const_1_None ( + .out(bit_const_1_None_out) +); +PEGEN_coreir_const #( + .value(16'h0000), + .width(16) +) const_0_16 ( + .out(const_0_16_out) +); +PEGEN_coreir_const #( + .value(5'h00), + .width(5) +) const_0_5 ( + .out(const_0_5_out) +); +PEGEN_coreir_const #( + .value(5'h0a), + .width(5) +) const_10_5 ( + .out(const_10_5_out) +); +PEGEN_coreir_const #( + .value(5'h0b), + .width(5) +) const_11_5 ( + .out(const_11_5_out) +); +PEGEN_coreir_const #( + .value(5'h0c), + .width(5) +) const_12_5 ( + .out(const_12_5_out) +); +PEGEN_coreir_const #( + .value(5'h0d), + .width(5) +) const_13_5 ( + .out(const_13_5_out) +); +PEGEN_coreir_const #( + .value(5'h0e), + .width(5) +) const_14_5 ( + .out(const_14_5_out) +); +PEGEN_coreir_const #( + .value(5'h0f), + .width(5) +) const_15_5 ( + .out(const_15_5_out) +); +PEGEN_coreir_const #( + .value(5'h10), + .width(5) +) const_16_5 ( + .out(const_16_5_out) +); +PEGEN_coreir_const #( + .value(5'h11), + .width(5) +) const_17_5 ( + .out(const_17_5_out) +); +PEGEN_coreir_const #( + .value(5'h12), + .width(5) +) const_18_5 ( + .out(const_18_5_out) +); +PEGEN_coreir_const #( + .value(5'h13), + .width(5) +) const_19_5 ( + .out(const_19_5_out) +); +PEGEN_coreir_const #( + .value(1'h1), + .width(1) +) const_1_1 ( + .out(const_1_1_out) +); +PEGEN_coreir_const #( + .value(5'h01), + .width(5) +) const_1_5 ( + .out(const_1_5_out) +); +PEGEN_coreir_const #( + .value(5'h02), + .width(5) +) const_2_5 ( + .out(const_2_5_out) +); +PEGEN_coreir_const #( + .value(5'h03), + .width(5) +) const_3_5 ( + .out(const_3_5_out) +); +PEGEN_coreir_const #( + .value(5'h04), + .width(5) +) const_4_5 ( + .out(const_4_5_out) +); +PEGEN_coreir_const #( + .value(5'h05), + .width(5) +) const_5_5 ( + .out(const_5_5_out) +); +PEGEN_coreir_const #( + .value(5'h06), + .width(5) +) const_6_5 ( + .out(const_6_5_out) +); +PEGEN_coreir_const #( + .value(5'h07), + .width(5) +) const_7_5 ( + .out(const_7_5_out) +); +PEGEN_coreir_const #( + .value(5'h08), + .width(5) +) const_8_5 ( + .out(const_8_5_out) +); +PEGEN_coreir_const #( + .value(5'h09), + .width(5) +) const_9_5 ( + .out(const_9_5_out) +); +PEGEN_corebit_and magma_Bit_and_inst0 ( + .in0(a[15]), + .in1(Mux2xBits16_inst5_O[15]), + .out(magma_Bit_and_inst0_out) +); +PEGEN_corebit_and magma_Bit_and_inst1 ( + .in0(magma_Bit_and_inst0_out), + .in1(magma_Bit_not_inst0_out), + .out(magma_Bit_and_inst1_out) +); +PEGEN_corebit_and magma_Bit_and_inst2 ( + .in0(magma_Bit_not_inst1_out), + .in1(magma_Bit_not_inst2_out), + .out(magma_Bit_and_inst2_out) +); +PEGEN_corebit_and magma_Bit_and_inst3 ( + .in0(magma_Bit_and_inst2_out), + .in1(magma_UInt_17_add_inst1_out[15]), + .out(magma_Bit_and_inst3_out) +); +PEGEN_corebit_not magma_Bit_not_inst0 ( + .in(magma_UInt_17_add_inst1_out[15]), + .out(magma_Bit_not_inst0_out) +); +PEGEN_corebit_not magma_Bit_not_inst1 ( + .in(a[15]), + .out(magma_Bit_not_inst1_out) +); +PEGEN_corebit_not magma_Bit_not_inst2 ( + .in(Mux2xBits16_inst5_O[15]), + .out(magma_Bit_not_inst2_out) +); +PEGEN_corebit_or magma_Bit_or_inst0 ( + .in0(magma_Bits_5_eq_inst2_out), + .in1(magma_Bits_5_eq_inst3_out), + .out(magma_Bit_or_inst0_out) +); +PEGEN_corebit_or magma_Bit_or_inst1 ( + .in0(magma_Bit_or_inst0_out), + .in1(magma_Bits_5_eq_inst4_out), + .out(magma_Bit_or_inst1_out) +); +PEGEN_corebit_or magma_Bit_or_inst10 ( + .in0(magma_Bit_or_inst9_out), + .in1(magma_Bits_5_eq_inst26_out), + .out(magma_Bit_or_inst10_out) +); +PEGEN_corebit_or magma_Bit_or_inst11 ( + .in0(magma_Bit_or_inst10_out), + .in1(magma_Bits_5_eq_inst27_out), + .out(magma_Bit_or_inst11_out) +); +PEGEN_corebit_or magma_Bit_or_inst12 ( + .in0(magma_Bit_or_inst11_out), + .in1(magma_Bits_5_eq_inst28_out), + .out(magma_Bit_or_inst12_out) +); +PEGEN_corebit_or magma_Bit_or_inst13 ( + .in0(magma_Bit_or_inst12_out), + .in1(magma_Bits_5_eq_inst29_out), + .out(magma_Bit_or_inst13_out) +); +PEGEN_corebit_or magma_Bit_or_inst2 ( + .in0(magma_Bits_5_eq_inst5_out), + .in1(magma_Bits_5_eq_inst6_out), + .out(magma_Bit_or_inst2_out) +); +PEGEN_corebit_or magma_Bit_or_inst3 ( + .in0(magma_Bit_or_inst2_out), + .in1(magma_Bits_5_eq_inst7_out), + .out(magma_Bit_or_inst3_out) +); +PEGEN_corebit_or magma_Bit_or_inst4 ( + .in0(magma_Bit_or_inst3_out), + .in1(magma_Bits_5_eq_inst8_out), + .out(magma_Bit_or_inst4_out) +); +PEGEN_corebit_or magma_Bit_or_inst5 ( + .in0(magma_Bits_5_eq_inst9_out), + .in1(magma_Bits_5_eq_inst10_out), + .out(magma_Bit_or_inst5_out) +); +PEGEN_corebit_or magma_Bit_or_inst6 ( + .in0(magma_Bit_or_inst5_out), + .in1(magma_Bits_5_eq_inst11_out), + .out(magma_Bit_or_inst6_out) +); +PEGEN_corebit_or magma_Bit_or_inst7 ( + .in0(magma_Bits_5_eq_inst12_out), + .in1(magma_Bits_5_eq_inst13_out), + .out(magma_Bit_or_inst7_out) +); +PEGEN_corebit_or magma_Bit_or_inst8 ( + .in0(magma_Bit_and_inst1_out), + .in1(magma_Bit_and_inst3_out), + .out(magma_Bit_or_inst8_out) +); +PEGEN_corebit_or magma_Bit_or_inst9 ( + .in0(magma_Bits_5_eq_inst24_out), + .in1(magma_Bits_5_eq_inst25_out), + .out(magma_Bit_or_inst9_out) +); +PEGEN_coreir_and #( + .width(16) +) magma_Bits_16_and_inst0 ( + .in0(a), + .in1(Mux2xBits16_inst5_O), + .out(magma_Bits_16_and_inst0_out) +); +PEGEN_coreir_not #( + .width(16) +) magma_Bits_16_not_inst0 ( + .in(b), + .out(magma_Bits_16_not_inst0_out) +); +PEGEN_coreir_not #( + .width(16) +) magma_Bits_16_not_inst1 ( + .in(c), + .out(magma_Bits_16_not_inst1_out) +); +PEGEN_coreir_or #( + .width(16) +) magma_Bits_16_or_inst0 ( + .in0(a), + .in1(Mux2xBits16_inst5_O), + .out(magma_Bits_16_or_inst0_out) +); +PEGEN_coreir_shl #( + .width(16) +) magma_Bits_16_shl_inst0 ( + .in0(a), + .in1(Mux2xBits16_inst5_O), + .out(magma_Bits_16_shl_inst0_out) +); +PEGEN_coreir_xor #( + .width(16) +) magma_Bits_16_xor_inst0 ( + .in0(a), + .in1(Mux2xBits16_inst5_O), + .out(magma_Bits_16_xor_inst0_out) +); +PEGEN_coreir_eq #( + .width(1) +) magma_Bits_1_eq_inst0 ( + .in0(signed_), + .in1(const_1_1_out), + .out(magma_Bits_1_eq_inst0_out) +); +PEGEN_coreir_eq #( + .width(1) +) magma_Bits_1_eq_inst1 ( + .in0(signed_), + .in1(const_1_1_out), + .out(magma_Bits_1_eq_inst1_out) +); +PEGEN_coreir_eq #( + .width(1) +) magma_Bits_1_eq_inst2 ( + .in0(signed_), + .in1(const_1_1_out), + .out(magma_Bits_1_eq_inst2_out) +); +PEGEN_coreir_eq #( + .width(1) +) magma_Bits_1_eq_inst3 ( + .in0(signed_), + .in1(const_1_1_out), + .out(magma_Bits_1_eq_inst3_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst0 ( + .in0(alu), + .in1(const_18_5_out), + .out(magma_Bits_5_eq_inst0_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst1 ( + .in0(alu), + .in1(const_19_5_out), + .out(magma_Bits_5_eq_inst1_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst10 ( + .in0(alu), + .in1(const_15_5_out), + .out(magma_Bits_5_eq_inst10_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst11 ( + .in0(alu), + .in1(const_17_5_out), + .out(magma_Bits_5_eq_inst11_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst12 ( + .in0(alu), + .in1(const_0_5_out), + .out(magma_Bits_5_eq_inst12_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst13 ( + .in0(alu), + .in1(const_1_5_out), + .out(magma_Bits_5_eq_inst13_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst14 ( + .in0(alu), + .in1(const_4_5_out), + .out(magma_Bits_5_eq_inst14_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst15 ( + .in0(alu), + .in1(const_5_5_out), + .out(magma_Bits_5_eq_inst15_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst16 ( + .in0(alu), + .in1(const_6_5_out), + .out(magma_Bits_5_eq_inst16_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst17 ( + .in0(alu), + .in1(const_2_5_out), + .out(magma_Bits_5_eq_inst17_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst18 ( + .in0(alu), + .in1(const_3_5_out), + .out(magma_Bits_5_eq_inst18_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst19 ( + .in0(alu), + .in1(const_10_5_out), + .out(magma_Bits_5_eq_inst19_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst2 ( + .in0(alu), + .in1(const_1_5_out), + .out(magma_Bits_5_eq_inst2_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst20 ( + .in0(alu), + .in1(const_9_5_out), + .out(magma_Bits_5_eq_inst20_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst21 ( + .in0(alu), + .in1(const_11_5_out), + .out(magma_Bits_5_eq_inst21_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst22 ( + .in0(alu), + .in1(const_7_5_out), + .out(magma_Bits_5_eq_inst22_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst23 ( + .in0(alu), + .in1(const_8_5_out), + .out(magma_Bits_5_eq_inst23_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst24 ( + .in0(alu), + .in1(const_12_5_out), + .out(magma_Bits_5_eq_inst24_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst25 ( + .in0(alu), + .in1(const_13_5_out), + .out(magma_Bits_5_eq_inst25_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst26 ( + .in0(alu), + .in1(const_14_5_out), + .out(magma_Bits_5_eq_inst26_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst27 ( + .in0(alu), + .in1(const_16_5_out), + .out(magma_Bits_5_eq_inst27_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst28 ( + .in0(alu), + .in1(const_15_5_out), + .out(magma_Bits_5_eq_inst28_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst29 ( + .in0(alu), + .in1(const_17_5_out), + .out(magma_Bits_5_eq_inst29_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst3 ( + .in0(alu), + .in1(const_16_5_out), + .out(magma_Bits_5_eq_inst3_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst30 ( + .in0(alu), + .in1(const_18_5_out), + .out(magma_Bits_5_eq_inst30_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst4 ( + .in0(alu), + .in1(const_17_5_out), + .out(magma_Bits_5_eq_inst4_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst5 ( + .in0(alu), + .in1(const_14_5_out), + .out(magma_Bits_5_eq_inst5_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst6 ( + .in0(alu), + .in1(const_15_5_out), + .out(magma_Bits_5_eq_inst6_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst7 ( + .in0(alu), + .in1(const_16_5_out), + .out(magma_Bits_5_eq_inst7_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst8 ( + .in0(alu), + .in1(const_17_5_out), + .out(magma_Bits_5_eq_inst8_out) +); +PEGEN_coreir_eq #( + .width(5) +) magma_Bits_5_eq_inst9 ( + .in0(alu), + .in1(const_13_5_out), + .out(magma_Bits_5_eq_inst9_out) +); +PEGEN_coreir_ashr #( + .width(16) +) magma_SInt_16_ashr_inst0 ( + .in0(Mux2xBits16_inst3_O), + .in1(c), + .out(magma_SInt_16_ashr_inst0_out) +); +PEGEN_coreir_eq #( + .width(16) +) magma_SInt_16_eq_inst0 ( + .in0(const_0_16_out), + .in1(Mux2xBits16_inst21_O), + .out(magma_SInt_16_eq_inst0_out) +); +PEGEN_coreir_neg #( + .width(16) +) magma_SInt_16_neg_inst0 ( + .in(a), + .out(magma_SInt_16_neg_inst0_out) +); +PEGEN_coreir_sge #( + .width(16) +) magma_SInt_16_sge_inst0 ( + .in0(Mux2xBits16_inst1_O), + .in1(c), + .out(magma_SInt_16_sge_inst0_out) +); +PEGEN_coreir_sle #( + .width(16) +) magma_SInt_16_sle_inst0 ( + .in0(a), + .in1(b), + .out(magma_SInt_16_sle_inst0_out) +); +PEGEN_coreir_sle #( + .width(16) +) magma_SInt_16_sle_inst1 ( + .in0(const_0_16_out), + .in1(a), + .out(magma_SInt_16_sle_inst1_out) +); +PEGEN_coreir_lshr #( + .width(16) +) magma_UInt_16_lshr_inst0 ( + .in0(Mux2xBits16_inst3_O), + .in1(c), + .out(magma_UInt_16_lshr_inst0_out) +); +PEGEN_coreir_uge #( + .width(16) +) magma_UInt_16_uge_inst0 ( + .in0(Mux2xBits16_inst1_O), + .in1(c), + .out(magma_UInt_16_uge_inst0_out) +); +PEGEN_coreir_ule #( + .width(16) +) magma_UInt_16_ule_inst0 ( + .in0(a), + .in1(b), + .out(magma_UInt_16_ule_inst0_out) +); +wire [16:0] magma_UInt_17_add_inst0_in0; +assign magma_UInt_17_add_inst0_in0 = {bit_const_0_None_out,a}; +wire [16:0] magma_UInt_17_add_inst0_in1; +assign magma_UInt_17_add_inst0_in1 = {bit_const_0_None_out,Mux2xBits16_inst5_O}; +PEGEN_coreir_add #( + .width(17) +) magma_UInt_17_add_inst0 ( + .in0(magma_UInt_17_add_inst0_in0), + .in1(magma_UInt_17_add_inst0_in1), + .out(magma_UInt_17_add_inst0_out) +); +wire [16:0] magma_UInt_17_add_inst1_in1; +assign magma_UInt_17_add_inst1_in1 = {bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,d}; +PEGEN_coreir_add #( + .width(17) +) magma_UInt_17_add_inst1 ( + .in0(magma_UInt_17_add_inst0_out), + .in1(magma_UInt_17_add_inst1_in1), + .out(magma_UInt_17_add_inst1_out) +); +wire [16:0] magma_UInt_17_add_inst2_in0; +assign magma_UInt_17_add_inst2_in0 = {bit_const_0_None_out,Mux2xUInt16_inst0_O}; +wire [16:0] magma_UInt_17_add_inst2_in1; +assign magma_UInt_17_add_inst2_in1 = {bit_const_0_None_out,Mux2xBits16_inst6_O}; +PEGEN_coreir_add #( + .width(17) +) magma_UInt_17_add_inst2 ( + .in0(magma_UInt_17_add_inst2_in0), + .in1(magma_UInt_17_add_inst2_in1), + .out(magma_UInt_17_add_inst2_out) +); +wire [16:0] magma_UInt_17_add_inst3_in1; +assign magma_UInt_17_add_inst3_in1 = {bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,Mux2xBit_inst2_O}; +PEGEN_coreir_add #( + .width(17) +) magma_UInt_17_add_inst3 ( + .in0(magma_UInt_17_add_inst2_out), + .in1(magma_UInt_17_add_inst3_in1), + .out(magma_UInt_17_add_inst3_out) +); +PEGEN_coreir_mul #( + .width(32) +) magma_UInt_32_mul_inst0 ( + .in0(Mux2xUInt32_inst0_O), + .in1(Mux2xUInt32_inst1_O), + .out(magma_UInt_32_mul_inst0_out) +); +assign res = Mux2xBits16_inst21_O; +assign res_p = Mux2xBit_inst23_O; +assign Z = magma_SInt_16_eq_inst0_out; +assign N = Mux2xBits16_inst21_O[15]; +assign C = Mux2xBit_inst21_O; +assign V = Mux2xBit_inst22_O; +endmodule + +module PEGEN_PE ( + input [83:0] inst, + input [15:0] data0, + input [15:0] data1, + input [15:0] data2, + input bit0, + input bit1, + input bit2, + input clk_en, + output [15:0] O0, + output O1, + output [15:0] O2, + output [15:0] O3, + output [15:0] O4, + input CLK, + input ASYNCRESET +); +wire [15:0] ALU_inst0_res; +wire ALU_inst0_res_p; +wire ALU_inst0_Z; +wire ALU_inst0_N; +wire ALU_inst0_C; +wire ALU_inst0_V; +wire Cond_inst0_O; +wire [15:0] FPCustom_inst0_res; +wire FPCustom_inst0_res_p; +wire FPCustom_inst0_V; +wire [15:0] FPU_inst0_res; +wire FPU_inst0_N; +wire FPU_inst0_Z; +wire LUT_inst0_O; +wire Mux2xBit_inst0_O; +wire Mux2xBit_inst1_O; +wire Mux2xBit_inst2_O; +wire Mux2xBit_inst3_O; +wire Mux2xBit_inst4_O; +wire Mux2xBit_inst5_O; +wire Mux2xBit_inst6_O; +wire Mux2xBit_inst7_O; +wire [15:0] Mux2xBits16_inst0_O; +wire [15:0] Mux2xBits16_inst1_O; +wire [4:0] Mux2xMagmaADTALU_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst0_O; +wire [2:0] Mux2xMagmaADTFPCustom_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst0_O; +wire [2:0] Mux2xMagmaADTFPCustom_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst1_O; +wire [2:0] Mux2xMagmaADTFPU_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst0_O; +wire [2:0] Mux2xMagmaADTFPU_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst1_O; +wire [15:0] RegisterMode_inst0_O0; +wire [15:0] RegisterMode_inst0_O1; +wire [15:0] RegisterMode_inst1_O0; +wire [15:0] RegisterMode_inst1_O1; +wire [15:0] RegisterMode_inst2_O0; +wire [15:0] RegisterMode_inst2_O1; +wire RegisterMode_inst3_O0; +wire RegisterMode_inst3_O1; +wire RegisterMode_inst4_O0; +wire RegisterMode_inst4_O1; +wire RegisterMode_inst5_O0; +wire RegisterMode_inst5_O1; +wire bit_const_0_None_out; +wire [1:0] const_0_2_out; +wire [2:0] const_0_3_out; +wire [4:0] const_0_5_out; +wire [1:0] const_1_2_out; +wire [1:0] const_2_2_out; +wire magma_Bits_2_eq_inst0_out; +wire magma_Bits_2_eq_inst1_out; +wire magma_Bits_2_eq_inst2_out; +wire magma_Bits_2_eq_inst3_out; +wire magma_Bits_2_eq_inst4_out; +wire magma_Bits_2_eq_inst5_out; +wire magma_Bits_2_eq_inst6_out; +PEGEN_ALU ALU_inst0 ( + .alu(Mux2xMagmaADTALU_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst0_O), + .signed_(inst[7:7]), + .a(RegisterMode_inst0_O0), + .b(RegisterMode_inst1_O0), + .c(RegisterMode_inst2_O0), + .d(RegisterMode_inst3_O0), + .res(ALU_inst0_res), + .res_p(ALU_inst0_res_p), + .Z(ALU_inst0_Z), + .N(ALU_inst0_N), + .C(ALU_inst0_C), + .V(ALU_inst0_V), + .CLK(CLK), + .ASYNCRESET(ASYNCRESET) +); +PEGEN_Cond Cond_inst0 ( + .code(inst[20:16]), + .alu(Mux2xBit_inst7_O), + .lut(LUT_inst0_O), + .Z(Mux2xBit_inst6_O), + .N(Mux2xBit_inst4_O), + .C(ALU_inst0_C), + .V(Mux2xBit_inst5_O), + .O(Cond_inst0_O), + .CLK(CLK), + .ASYNCRESET(ASYNCRESET) +); +PEGEN_FPCustom FPCustom_inst0 ( + .op(Mux2xMagmaADTFPCustom_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst1_O), + .signed_(inst[7:7]), + .a(RegisterMode_inst0_O0), + .b(RegisterMode_inst1_O0), + .res(FPCustom_inst0_res), + .res_p(FPCustom_inst0_res_p), + .V(FPCustom_inst0_V), + .CLK(CLK), + .ASYNCRESET(ASYNCRESET) +); +PEGEN_FPU FPU_inst0 ( + .fpu_op(Mux2xMagmaADTFPU_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst1_O), + .a(RegisterMode_inst0_O0), + .b(RegisterMode_inst1_O0), + .res(FPU_inst0_res), + .N(FPU_inst0_N), + .Z(FPU_inst0_Z), + .CLK(CLK), + .ASYNCRESET(ASYNCRESET) +); +wire [7:0] LUT_inst0_lut; +assign LUT_inst0_lut = {inst[15],inst[14],inst[13],inst[12],inst[11],inst[10],inst[9],inst[8]}; +PEGEN_LUT LUT_inst0 ( + .lut(LUT_inst0_lut), + .bit0(RegisterMode_inst3_O0), + .bit1(RegisterMode_inst4_O0), + .bit2(RegisterMode_inst5_O0), + .O(LUT_inst0_O), + .CLK(CLK), + .ASYNCRESET(ASYNCRESET) +); +PEGEN_Mux2xBit Mux2xBit_inst0 ( + .I0(bit_const_0_None_out), + .I1(FPU_inst0_N), + .S(magma_Bits_2_eq_inst6_out), + .O(Mux2xBit_inst0_O) +); +PEGEN_Mux2xBit Mux2xBit_inst1 ( + .I0(FPCustom_inst0_V), + .I1(bit_const_0_None_out), + .S(magma_Bits_2_eq_inst6_out), + .O(Mux2xBit_inst1_O) +); +PEGEN_Mux2xBit Mux2xBit_inst2 ( + .I0(bit_const_0_None_out), + .I1(FPU_inst0_Z), + .S(magma_Bits_2_eq_inst6_out), + .O(Mux2xBit_inst2_O) +); +PEGEN_Mux2xBit Mux2xBit_inst3 ( + .I0(FPCustom_inst0_res_p), + .I1(bit_const_0_None_out), + .S(magma_Bits_2_eq_inst6_out), + .O(Mux2xBit_inst3_O) +); +PEGEN_Mux2xBit Mux2xBit_inst4 ( + .I0(Mux2xBit_inst0_O), + .I1(ALU_inst0_N), + .S(magma_Bits_2_eq_inst5_out), + .O(Mux2xBit_inst4_O) +); +PEGEN_Mux2xBit Mux2xBit_inst5 ( + .I0(Mux2xBit_inst1_O), + .I1(ALU_inst0_V), + .S(magma_Bits_2_eq_inst5_out), + .O(Mux2xBit_inst5_O) +); +PEGEN_Mux2xBit Mux2xBit_inst6 ( + .I0(Mux2xBit_inst2_O), + .I1(ALU_inst0_Z), + .S(magma_Bits_2_eq_inst5_out), + .O(Mux2xBit_inst6_O) +); +PEGEN_Mux2xBit Mux2xBit_inst7 ( + .I0(Mux2xBit_inst3_O), + .I1(ALU_inst0_res_p), + .S(magma_Bits_2_eq_inst5_out), + .O(Mux2xBit_inst7_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst0 ( + .I0(FPCustom_inst0_res), + .I1(FPU_inst0_res), + .S(magma_Bits_2_eq_inst6_out), + .O(Mux2xBits16_inst0_O) +); +PEGEN_Mux2xBits16 Mux2xBits16_inst1 ( + .I0(Mux2xBits16_inst0_O), + .I1(ALU_inst0_res), + .S(magma_Bits_2_eq_inst5_out), + .O(Mux2xBits16_inst1_O) +); +wire [4:0] Mux2xMagmaADTALU_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst0_I1; +assign Mux2xMagmaADTALU_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst0_I1 = {inst[6],inst[5],inst[4],inst[3],inst[2]}; +PEGEN_Mux2xMagmaADTALU_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3 Mux2xMagmaADTALU_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst0 ( + .I0(const_0_5_out), + .I1(Mux2xMagmaADTALU_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst0_I1), + .S(magma_Bits_2_eq_inst0_out), + .O(Mux2xMagmaADTALU_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst0_O) +); +wire [2:0] Mux2xMagmaADTFPCustom_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst0_I0; +assign Mux2xMagmaADTFPCustom_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst0_I0 = {inst[4],inst[3],inst[2]}; +PEGEN_Mux2xMagmaADTFPCustom_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3 Mux2xMagmaADTFPCustom_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst0 ( + .I0(Mux2xMagmaADTFPCustom_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst0_I0), + .I1(const_0_3_out), + .S(magma_Bits_2_eq_inst2_out), + .O(Mux2xMagmaADTFPCustom_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst0_O) +); +PEGEN_Mux2xMagmaADTFPCustom_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3 Mux2xMagmaADTFPCustom_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst1 ( + .I0(Mux2xMagmaADTFPCustom_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst0_O), + .I1(const_0_3_out), + .S(magma_Bits_2_eq_inst0_out), + .O(Mux2xMagmaADTFPCustom_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst1_O) +); +wire [2:0] Mux2xMagmaADTFPU_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst0_I1; +assign Mux2xMagmaADTFPU_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst0_I1 = {inst[4],inst[3],inst[2]}; +PEGEN_Mux2xMagmaADTFPU_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3 Mux2xMagmaADTFPU_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst0 ( + .I0(const_0_3_out), + .I1(Mux2xMagmaADTFPU_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst0_I1), + .S(magma_Bits_2_eq_inst2_out), + .O(Mux2xMagmaADTFPU_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst0_O) +); +PEGEN_Mux2xMagmaADTFPU_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3 Mux2xMagmaADTFPU_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst1 ( + .I0(Mux2xMagmaADTFPU_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst0_O), + .I1(const_0_3_out), + .S(magma_Bits_2_eq_inst0_out), + .O(Mux2xMagmaADTFPU_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst1_O) +); +wire [15:0] RegisterMode_inst0_const_; +assign RegisterMode_inst0_const_ = {inst[38],inst[37],inst[36],inst[35],inst[34],inst[33],inst[32],inst[31],inst[30],inst[29],inst[28],inst[27],inst[26],inst[25],inst[24],inst[23]}; +PEGEN_RegisterMode RegisterMode_inst0 ( + .mode(inst[22:21]), + .const_(RegisterMode_inst0_const_), + .value(data0), + .clk_en(clk_en), + .O0(RegisterMode_inst0_O0), + .O1(RegisterMode_inst0_O1), + .CLK(CLK), + .ASYNCRESET(ASYNCRESET) +); +wire [15:0] RegisterMode_inst1_const_; +assign RegisterMode_inst1_const_ = {inst[56],inst[55],inst[54],inst[53],inst[52],inst[51],inst[50],inst[49],inst[48],inst[47],inst[46],inst[45],inst[44],inst[43],inst[42],inst[41]}; +PEGEN_RegisterMode RegisterMode_inst1 ( + .mode(inst[40:39]), + .const_(RegisterMode_inst1_const_), + .value(data1), + .clk_en(clk_en), + .O0(RegisterMode_inst1_O0), + .O1(RegisterMode_inst1_O1), + .CLK(CLK), + .ASYNCRESET(ASYNCRESET) +); +wire [15:0] RegisterMode_inst2_const_; +assign RegisterMode_inst2_const_ = {inst[74],inst[73],inst[72],inst[71],inst[70],inst[69],inst[68],inst[67],inst[66],inst[65],inst[64],inst[63],inst[62],inst[61],inst[60],inst[59]}; +PEGEN_RegisterMode RegisterMode_inst2 ( + .mode(inst[58:57]), + .const_(RegisterMode_inst2_const_), + .value(data2), + .clk_en(clk_en), + .O0(RegisterMode_inst2_O0), + .O1(RegisterMode_inst2_O1), + .CLK(CLK), + .ASYNCRESET(ASYNCRESET) +); +PEGEN_RegisterMode_unq1 RegisterMode_inst3 ( + .mode(inst[76:75]), + .const_(inst[77]), + .value(bit0), + .clk_en(clk_en), + .O0(RegisterMode_inst3_O0), + .O1(RegisterMode_inst3_O1), + .CLK(CLK), + .ASYNCRESET(ASYNCRESET) +); +PEGEN_RegisterMode_unq1 RegisterMode_inst4 ( + .mode(inst[79:78]), + .const_(inst[80]), + .value(bit1), + .clk_en(clk_en), + .O0(RegisterMode_inst4_O0), + .O1(RegisterMode_inst4_O1), + .CLK(CLK), + .ASYNCRESET(ASYNCRESET) +); +PEGEN_RegisterMode_unq1 RegisterMode_inst5 ( + .mode(inst[82:81]), + .const_(inst[83]), + .value(bit2), + .clk_en(clk_en), + .O0(RegisterMode_inst5_O0), + .O1(RegisterMode_inst5_O1), + .CLK(CLK), + .ASYNCRESET(ASYNCRESET) +); +PEGEN_corebit_const #( + .value(1'b0) +) bit_const_0_None ( + .out(bit_const_0_None_out) +); +PEGEN_coreir_const #( + .value(2'h0), + .width(2) +) const_0_2 ( + .out(const_0_2_out) +); +PEGEN_coreir_const #( + .value(3'h0), + .width(3) +) const_0_3 ( + .out(const_0_3_out) +); +PEGEN_coreir_const #( + .value(5'h00), + .width(5) +) const_0_5 ( + .out(const_0_5_out) +); +PEGEN_coreir_const #( + .value(2'h1), + .width(2) +) const_1_2 ( + .out(const_1_2_out) +); +PEGEN_coreir_const #( + .value(2'h2), + .width(2) +) const_2_2 ( + .out(const_2_2_out) +); +wire [1:0] magma_Bits_2_eq_inst0_in0; +assign magma_Bits_2_eq_inst0_in0 = {inst[1],inst[0]}; +PEGEN_coreir_eq #( + .width(2) +) magma_Bits_2_eq_inst0 ( + .in0(magma_Bits_2_eq_inst0_in0), + .in1(const_0_2_out), + .out(magma_Bits_2_eq_inst0_out) +); +wire [1:0] magma_Bits_2_eq_inst1_in0; +assign magma_Bits_2_eq_inst1_in0 = {inst[1],inst[0]}; +PEGEN_coreir_eq #( + .width(2) +) magma_Bits_2_eq_inst1 ( + .in0(magma_Bits_2_eq_inst1_in0), + .in1(const_0_2_out), + .out(magma_Bits_2_eq_inst1_out) +); +wire [1:0] magma_Bits_2_eq_inst2_in0; +assign magma_Bits_2_eq_inst2_in0 = {inst[1],inst[0]}; +PEGEN_coreir_eq #( + .width(2) +) magma_Bits_2_eq_inst2 ( + .in0(magma_Bits_2_eq_inst2_in0), + .in1(const_2_2_out), + .out(magma_Bits_2_eq_inst2_out) +); +wire [1:0] magma_Bits_2_eq_inst3_in0; +assign magma_Bits_2_eq_inst3_in0 = {inst[1],inst[0]}; +PEGEN_coreir_eq #( + .width(2) +) magma_Bits_2_eq_inst3 ( + .in0(magma_Bits_2_eq_inst3_in0), + .in1(const_2_2_out), + .out(magma_Bits_2_eq_inst3_out) +); +wire [1:0] magma_Bits_2_eq_inst4_in0; +assign magma_Bits_2_eq_inst4_in0 = {inst[1],inst[0]}; +PEGEN_coreir_eq #( + .width(2) +) magma_Bits_2_eq_inst4 ( + .in0(magma_Bits_2_eq_inst4_in0), + .in1(const_1_2_out), + .out(magma_Bits_2_eq_inst4_out) +); +wire [1:0] magma_Bits_2_eq_inst5_in0; +assign magma_Bits_2_eq_inst5_in0 = {inst[1],inst[0]}; +PEGEN_coreir_eq #( + .width(2) +) magma_Bits_2_eq_inst5 ( + .in0(magma_Bits_2_eq_inst5_in0), + .in1(const_0_2_out), + .out(magma_Bits_2_eq_inst5_out) +); +wire [1:0] magma_Bits_2_eq_inst6_in0; +assign magma_Bits_2_eq_inst6_in0 = {inst[1],inst[0]}; +PEGEN_coreir_eq #( + .width(2) +) magma_Bits_2_eq_inst6 ( + .in0(magma_Bits_2_eq_inst6_in0), + .in1(const_2_2_out), + .out(magma_Bits_2_eq_inst6_out) +); +assign O0 = Mux2xBits16_inst1_O; +assign O1 = Cond_inst0_O; +assign O2 = RegisterMode_inst0_O1; +assign O3 = RegisterMode_inst1_O1; +assign O4 = RegisterMode_inst2_O1; +endmodule + diff --git a/sam/onyx/hw_nodes/compute_node.py b/sam/onyx/hw_nodes/compute_node.py index de147365..8a6b3329 100644 --- a/sam/onyx/hw_nodes/compute_node.py +++ b/sam/onyx/hw_nodes/compute_node.py @@ -7,7 +7,7 @@ class ComputeNode(HWNode): - def __init__(self, name=None, op=None, sam_graph_node_id=None) -> None: + def __init__(self, name=None, op=None, sam_graph_node_id=None, mapped_coreir_dir=None) -> None: super().__init__(name=name) self.num_inputs = 2 self.num_outputs = 1 @@ -16,8 +16,9 @@ def __init__(self, name=None, op=None, sam_graph_node_id=None) -> None: self.mapped_input_ports = [] self.op = op self.opcode = None + self.mapped_coreir_dir = mapped_coreir_dir # parse the mapped coreir file to get the input ports and opcode - self.parse_mapped_json("/aha/alu_mapped.json", sam_graph_node_id) + self.parse_mapped_json(self.mapped_coreir_dir + "/alu_coreir_spec_mapped.json", sam_graph_node_id) assert len(self.mapped_input_ports) > 0 assert self.opcode is not None diff --git a/sam/onyx/parse_dot.py b/sam/onyx/parse_dot.py index d4baf716..d6b80962 100644 --- a/sam/onyx/parse_dot.py +++ b/sam/onyx/parse_dot.py @@ -15,7 +15,7 @@ def __init__(self, *args: object) -> None: class SAMDotGraph(): def __init__(self, filename=None, local_mems=True, use_fork=False, - use_fa=False, unroll=1) -> None: + use_fa=False, unroll=1, collat_dir=None) -> None: assert filename is not None, "filename is None" self.graphs = pydot.graph_from_dot_file(filename) self.graph = self.graphs[0] @@ -27,6 +27,7 @@ def __init__(self, filename=None, local_mems=True, use_fork=False, self.use_fork = use_fork self.use_fa = use_fa self.fa_color = 0 + self.collat_dir = collat_dir self.alu_nodes = [] self.shared_writes = {} @@ -167,14 +168,15 @@ def map_alu(self): self.generate_coreir_spec(c, alu_node.get_attributes(), alu_node.get_name()) - c.save_to_file("/aha/alu.json") + c.save_to_file(self.collat_dir + "/alu_coreir_spec.json") # use metamapper to map it # set environment variable PIPELINED to zero to disable input buffering in the alu # in order to make sure the output comes out within the same cycle the input is given metamapper_env = os.environ.copy() metamapper_env["PIPELINED"] = "0" - subprocess.run(["python", "aha/MetaMapper/scripts/map_app.py", "/aha/alu.json"], env=metamapper_env) + subprocess.run(["python", "/aha/MetaMapper/scripts/map_app.py", self.collat_dir + "/alu_coreir_spec.json"], env=metamapper_env) + breakpoint() def get_next_seq(self): From 93a2846a319205d09746545ac9ec474987c93467 Mon Sep 17 00:00:00 2001 From: Bo Wun Cheng Date: Sun, 21 Jan 2024 21:58:54 -0800 Subject: [PATCH 06/18] remove unwanted file --- .../.ast_tools/__call__140020533737792.py | 7 - .../.ast_tools/__call__140020535566688.py | 149 - .../.ast_tools/__call__140020542680080.py | 40 - .../.ast_tools/__call__140020542812512.py | 7 - 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+0,0 @@ -@name_outputs(res=Data, res_p=Bit, Z=Bit, N=Bit, C=Bit, V=Bit) -def __call__( - self, - alu: Const(ALU_t), - signed_: Const(Signed_t), - a: DataPy, - b: DataPy, - c: DataPy, - d: BitPy, -) -> (DataPy, BitPy, BitPy, BitPy, BitPy, BitPy): - _cond_0 = signed_ == Signed_t.signed - mula_0 = UData32(SData(a).sext(16)) - mulb_0 = UData32(SData(b).sext(16)) - mula_1 = UData(a).zext(16) - mulb_1 = UData(b).zext(16) - mula_2 = __phi(_cond_0, mula_0, mula_1) - mulb_2 = __phi(_cond_0, mulb_0, mulb_1) - mul_0 = mula_2 * mulb_2 - _cond_1 = signed_ == Signed_t.signed - lte_pred_0 = SData(a) <= SData(b) - lte_pred_1 = UData(a) <= UData(b) - lte_pred_2 = __phi(_cond_1, lte_pred_0, lte_pred_1) - min_ab_0 = lte_pred_2.ite(a, b) - _cond_2 = alu == ALU_t.CROP - max_in0_0 = min_ab_0 - max_in0_1 = b - max_in0_2 = __phi(_cond_2, max_in0_0, max_in0_1) - _cond_3 = signed_ == Signed_t.signed - gte_pred_0 = SData(max_in0_2) >= SData(c) - gte_pred_1 = UData(max_in0_2) >= UData(c) - gte_pred_2 = __phi(_cond_3, gte_pred_0, gte_pred_1) - max_bc_0 = gte_pred_2.ite(max_in0_2, c) - _cond_4 = alu == ALU_t.MULSHR - shr_in0_0 = mul_0[:16] - shr_in0_1 = a - shr_in0_2 = __phi(_cond_4, shr_in0_0, shr_in0_1) - _cond_5 = signed_ == Signed_t.signed - shr_0 = Data(SData(shr_in0_2) >> SData(c)) - shr_1 = Data(UData(shr_in0_2) >> UData(c)) - shr_2 = __phi(_cond_5, shr_0, shr_1) - _cond_6 = (alu == ALU_t.Sbc) | (alu == ALU_t.TSA) | (alu == ALU_t.TSS) - b_0 = ~b - b_1 = __phi(_cond_6, b_0, b) - - Cin_0 = d - - # factor out comman add - adder_res_0, adder_C_0 = UData(a).adc(UData(b_1), Cin_0) - _cond_7 = ( - (alu == ALU_t.TAA) - | (alu == ALU_t.TAS) - | (alu == ALU_t.TSA) - | (alu == ALU_t.TSS) - ) - adder2_in0_0 = adder_res_0 - adder2_in0_1 = mul_0[:16] - adder2_in0_2 = __phi(_cond_7, adder2_in0_0, adder2_in0_1) - _cond_8 = (alu == ALU_t.MULSUB) | (alu == ALU_t.TAS) | (alu == ALU_t.TSS) - adder2_in1_0 = ~c - Cin2_0 = Bit(1) - adder2_in1_1 = c - Cin2_1 = Bit(0) - Cin2_2 = __phi(_cond_8, Cin2_0, Cin2_1) - adder2_in1_2 = __phi(_cond_8, adder2_in1_0, adder2_in1_1) - - adder2_res_0, adder2_C_0 = UData(adder2_in0_2).adc(adder2_in1_2, Cin2_2) - - C_0 = Bit(0) - V_0 = Bit(0) - _cond_21 = (alu == ALU_t.Adc) | (alu == ALU_t.Sbc) - res_0, C_1 = adder_res_0, adder_C_0 - V_1 = overflow(a, b_1, res_0) - res_p_0 = C_1 - _cond_20 = alu == ALU_t.Mult0 - res_1, C_2, V_2 = mul_0[:16], Bit(0), Bit(0) - res_p_1 = C_2 - _cond_19 = alu == ALU_t.Mult1 - res_2, C_3, V_3 = mul_0[8:24], Bit(0), Bit(0) - res_p_2 = C_3 - _cond_18 = alu == ALU_t.Mult2 - res_3, C_4, V_4 = mul_0[16:32], Bit(0), Bit(0) - res_p_3 = C_4 - _cond_17 = alu == ALU_t.Abs - abs_pred_0 = SData(a) >= SData(0) - res_4, res_p_4 = abs_pred_0.ite(a, UInt[16](-SInt[16](a))), Bit(a[-1]) - _cond_16 = alu == ALU_t.Sel - res_5, res_p_5 = d.ite(a, b_1), Bit(0) - _cond_15 = alu == ALU_t.And - res_6, res_p_6 = a & b_1, Bit(0) - _cond_14 = alu == ALU_t.Or - res_7, res_p_7 = a | b_1, Bit(0) - _cond_13 = alu == ALU_t.XOr - res_8, res_p_8 = a ^ b_1, Bit(0) - _cond_12 = alu == ALU_t.SHR - res_9, res_p_9 = shr_2, Bit(0) - _cond_11 = alu == ALU_t.SHL - res_10, res_p_10 = a << b_1, Bit(0) - _cond_10 = ( - (alu == ALU_t.MULADD) - | (alu == ALU_t.MULSUB) - | (alu == ALU_t.TAA) - | (alu == ALU_t.TSA) - | (alu == ALU_t.TAS) - | (alu == ALU_t.TSS) - ) - res_11, res_p_11 = adder2_res_0, Bit(0) - _cond_9 = alu == ALU_t.CROP - res_12, res_p_12 = max_bc_0, Bit(0) - res_13, res_p_13 = shr_2, Bit(0) - res_14 = __phi(_cond_9, res_12, res_13) - res_p_14 = __phi(_cond_9, res_p_12, res_p_13) - res_15 = __phi(_cond_10, res_11, res_14) - res_p_15 = __phi(_cond_10, res_p_11, res_p_14) - res_16 = __phi(_cond_11, res_10, res_15) - res_p_16 = __phi(_cond_11, res_p_10, res_p_15) - res_17 = __phi(_cond_12, res_9, res_16) - res_p_17 = __phi(_cond_12, res_p_9, res_p_16) - res_18 = __phi(_cond_13, res_8, res_17) - res_p_18 = __phi(_cond_13, res_p_8, res_p_17) - res_19 = __phi(_cond_14, res_7, res_18) - res_p_19 = __phi(_cond_14, res_p_7, res_p_18) - res_20 = __phi(_cond_15, res_6, res_19) - res_p_20 = __phi(_cond_15, res_p_6, res_p_19) - res_21 = __phi(_cond_16, res_5, res_20) - res_p_21 = __phi(_cond_16, res_p_5, res_p_20) - res_22 = __phi(_cond_17, res_4, res_21) - res_p_22 = __phi(_cond_17, res_p_4, res_p_21) - C_5 = __phi(_cond_18, C_4, C_0) - V_5 = __phi(_cond_18, V_4, V_0) - res_23 = __phi(_cond_18, res_3, res_22) - res_p_23 = __phi(_cond_18, res_p_3, res_p_22) - C_6 = __phi(_cond_19, C_3, C_5) - V_6 = __phi(_cond_19, V_3, V_5) - res_24 = __phi(_cond_19, res_2, res_23) - res_p_24 = __phi(_cond_19, res_p_2, res_p_23) - C_7 = __phi(_cond_20, C_2, C_6) - V_7 = __phi(_cond_20, V_2, V_6) - res_25 = __phi(_cond_20, res_1, res_24) - res_p_25 = __phi(_cond_20, res_p_1, res_p_24) - C_8 = __phi(_cond_21, C_1, C_7) - V_8 = __phi(_cond_21, V_1, V_7) - res_26 = __phi(_cond_21, res_0, res_25) - res_p_26 = __phi(_cond_21, res_p_0, res_p_25) - - N_0 = Bit(res_26[-1]) - Z_0 = res_26 == SData(0) - - __0_return_0 = res_26, res_p_26, Z_0, N_0, C_8, V_8 - return __0_return_0 diff --git a/sam/onyx/.ast_tools/__call__140020542680080.py b/sam/onyx/.ast_tools/__call__140020542680080.py deleted file mode 100644 index c159114e..00000000 --- a/sam/onyx/.ast_tools/__call__140020542680080.py +++ /dev/null @@ -1,40 +0,0 @@ -@name_outputs(res=Data, N=Bit, Z=Bit) -def __call__(self, fpu_op: Const(FPU_t), a: Data, b: Data) -> (Data, Bit, Bit): - - a_inf_0 = fp_is_inf(a) - b_inf_0 = fp_is_inf(b) - a_neg_0 = fp_is_neg(a) - b_neg_0 = fp_is_neg(b) - - old_b_0 = b - neg_b_0 = (fpu_op == FPU_t.FP_sub) | (fpu_op == FPU_t.FP_cmp) | (fpu_op == FPU_t.FP_max) - _cond_0 = neg_b_0 - b_0 = b ^ (2 ** (16 - 1)) - b_1 = __phi(_cond_0, b_0, b) - Add_val_0 = self.Add(a, b_1) - Mul_val_0 = self.Mul(a, b_1) - _cond_3 = ( - (fpu_op == FPU_t.FP_add) - | (fpu_op == FPU_t.FP_sub) - | (fpu_op == FPU_t.FP_cmp) - ) - res_0 = Add_val_0 - _cond_2 = (fpu_op == FPU_t.FP_max) - _cond_1 = family.Bit(Add_val_0[-1]) - res_1 = old_b_0 - res_2 = a - res_3 = __phi(_cond_1, res_1, res_2) - res_4 = Mul_val_0 - res_5 = __phi(_cond_2, res_3, res_4) - res_6 = __phi(_cond_3, res_0, res_5) - - Z_0 = fp_is_zero(res_6) - _cond_5 = fpu_op == FPU_t.FP_cmp - _cond_4 = (a_inf_0 & b_inf_0) & (a_neg_0 == b_neg_0) - Z_1 = family.Bit(1) - Z_2 = __phi(_cond_4, Z_1, Z_0) - Z_3 = __phi(_cond_5, Z_2, Z_0) - - N_0 = family.Bit(res_6[-1]) - __0_return_0 = res_6, N_0, Z_3 - return __0_return_0 diff --git a/sam/onyx/.ast_tools/__call__140020542812512.py b/sam/onyx/.ast_tools/__call__140020542812512.py deleted file mode 100644 index 678a8cde..00000000 --- a/sam/onyx/.ast_tools/__call__140020542812512.py +++ /dev/null @@ -1,7 +0,0 @@ -def __call__(self, in0: Data, in1: Data) -> Data: - in0_float_0 = cast(in0) - in1_float_0 = cast(in1) - out_float_0 = getattr(in0_float_0, op_name)(in1_float_0) - out_0 = out_float_0.reinterpret_as_bv() - __0_return_0 = out_0 - return __0_return_0 diff --git a/sam/onyx/.ast_tools/__call__140020545582560.py b/sam/onyx/.ast_tools/__call__140020545582560.py deleted file mode 100644 index c8f4fa5a..00000000 --- a/sam/onyx/.ast_tools/__call__140020545582560.py +++ /dev/null @@ -1,16 +0,0 @@ -def __call__( - self, mode: Mode_t, const_: T, value: T, clk_en: Bit -) -> (T, T): - _cond_0 = mode == Mode_t.DELAY - data_0, en_0 = value, clk_en - data_1, en_1 = value, Bit(0) - data_2 = __phi(_cond_0, data_0, data_1) - en_2 = __phi(_cond_0, en_0, en_1) - - reg_val_0 = self.register(data_2, en_2) - _cond_2 = mode == Mode_t.CONST - __0_return_0 = const_, reg_val_0 - _cond_1 = mode == Mode_t.BYPASS - __0_return_1 = value, reg_val_0 - __0_return_2 = reg_val_0, reg_val_0 - return __phi(_cond_2, __0_return_0, __phi(_cond_1, __0_return_1, __0_return_2)) diff --git a/sam/onyx/.ast_tools/__call__140020545725632.py b/sam/onyx/.ast_tools/__call__140020545725632.py deleted file mode 100644 index c8f4fa5a..00000000 --- a/sam/onyx/.ast_tools/__call__140020545725632.py +++ /dev/null @@ -1,16 +0,0 @@ -def __call__( - self, mode: Mode_t, const_: T, value: T, clk_en: Bit -) -> (T, T): - _cond_0 = mode == Mode_t.DELAY - data_0, en_0 = value, clk_en - data_1, en_1 = value, Bit(0) - data_2 = __phi(_cond_0, data_0, data_1) - en_2 = __phi(_cond_0, en_0, en_1) - - reg_val_0 = self.register(data_2, en_2) - _cond_2 = mode == Mode_t.CONST - __0_return_0 = const_, reg_val_0 - _cond_1 = mode == Mode_t.BYPASS - __0_return_1 = value, reg_val_0 - __0_return_2 = reg_val_0, reg_val_0 - return __phi(_cond_2, __0_return_0, __phi(_cond_1, __0_return_1, __0_return_2)) diff --git a/sam/onyx/.ast_tools/__call__140154664120672.py b/sam/onyx/.ast_tools/__call__140154664120672.py deleted file mode 100644 index 112693cc..00000000 --- a/sam/onyx/.ast_tools/__call__140154664120672.py +++ /dev/null @@ -1,6 +0,0 @@ -@name_outputs(lut_out=Bit) -def __call__(self, lut: LUT_t, bit0: Bit, bit1: Bit, bit2: Bit) -> Bit: - i_0 = IDX_t([bit0, bit1, bit2]) - i_1 = i_0.zext(5) - __0_return_0 = ((lut >> i_1) & 1)[0] - return __0_return_0 diff --git a/sam/onyx/.ast_tools/__call__140154664294576.py b/sam/onyx/.ast_tools/__call__140154664294576.py deleted file mode 100644 index 929fa036..00000000 --- a/sam/onyx/.ast_tools/__call__140154664294576.py +++ /dev/null @@ -1,91 +0,0 @@ -@name_outputs( - res=DataPy, - res_p=BitPy, - reg0_config_data=DataPy, - reg1_config_data=DataPy, - reg2_config_data=DataPy, -) -def __call__( - self, - inst: Const(Inst), - data0: DataPy = Data(0), - data1: DataPy = Data(0), - data2: DataPy = Data(0), - bit0: BitPy = Bit(0), - bit1: BitPy = Bit(0), - bit2: BitPy = Bit(0), - clk_en: Global(BitPy) = Bit(1), -) -> (DataPy, BitPy, DataPy, DataPy, DataPy): - - ra_0, ra_rdata_0 = self.rega(inst.rega, inst.data0, data0, clk_en) - rb_0, rb_rdata_0 = self.regb(inst.regb, inst.data1, data1, clk_en) - rc_0, rc_rdata_0 = self.regc(inst.regc, inst.data2, data2, clk_en) - - rd_0, rd_rdata_0 = self.regd(inst.regd, inst.bit0, bit0, clk_en) - re_0, re_rdata_0 = self.rege(inst.rege, inst.bit1, bit1, clk_en) - rf_0, rf_rdata_0 = self.regf(inst.regf, inst.bit2, bit2, clk_en) - - # set default values to each of the op kinds - alu_op_0 = ALU_t_c(ALU_t.Adc) - fpu_op_0 = FPU_t_c(FPU_t.FP_add) - fp_custom_op_0 = FPCustom_t_c(FPCustom_t.FGetMant) - _cond_1 = inst.op.alu.match - alu_op_1 = inst.op.alu.value - _cond_0 = inst.op.fpu.match - fpu_op_1 = inst.op.fpu.value - fp_custom_op_1 = inst.op.fp_custom.value - fp_custom_op_2 = __phi(_cond_0, fp_custom_op_0, fp_custom_op_1) - fpu_op_2 = __phi(_cond_0, fpu_op_1, fpu_op_0) - alu_op_2 = __phi(_cond_1, alu_op_1, alu_op_0) - fp_custom_op_3 = __phi(_cond_1, fp_custom_op_0, fp_custom_op_2) - fpu_op_3 = __phi(_cond_1, fpu_op_0, fpu_op_2) - - # calculate alu results - alu_res_0, alu_res_p_0, alu_Z_0, alu_N_0, C_0, alu_V_0 = self.alu( - alu_op_2, inst.signed, ra_0, rb_0, rc_0, rd_0 - ) - - fpu_res_0, fpu_N_0, fpu_Z_0 = self.fpu(fpu_op_3, ra_0, rb_0) - - fpc_res_0, fpc_res_p_0, fpc_V_0 = self.fp_custom( - fp_custom_op_3, inst.signed, ra_0, rb_0 - ) - - Z_0 = Bit(0) - N_0 = Bit(0) - V_0 = Bit(0) - res_p_0 = Bit(0) - res_0 = Data(0) - _cond_3 = inst.op.alu.match - Z_1 = alu_Z_0 - N_1 = alu_N_0 - V_1 = alu_V_0 - res_p_1 = alu_res_p_0 - res_1 = alu_res_0 - _cond_2 = inst.op.fpu.match - N_2 = fpu_N_0 - Z_2 = fpu_Z_0 - res_2 = fpu_res_0 - V_2 = fpc_V_0 - res_p_2 = fpc_res_p_0 - res_3 = fpc_res_0 - N_3 = __phi(_cond_2, N_2, N_0) - V_3 = __phi(_cond_2, V_0, V_2) - Z_3 = __phi(_cond_2, Z_2, Z_0) - res_4 = __phi(_cond_2, res_2, res_3) - res_p_3 = __phi(_cond_2, res_p_0, res_p_2) - N_4 = __phi(_cond_3, N_1, N_3) - V_4 = __phi(_cond_3, V_1, V_3) - Z_4 = __phi(_cond_3, Z_1, Z_3) - res_5 = __phi(_cond_3, res_1, res_4) - res_p_4 = __phi(_cond_3, res_p_1, res_p_3) - - # calculate lut results - lut_res_0 = self.lut(inst.lut, rd_0, re_0, rf_0) - - # calculate 1-bit result - cond_0 = self.cond(inst.cond, res_p_4, lut_res_0, Z_4, N_4, C_0, V_4) - - # return 16-bit result, 1-bit result - __0_return_0 = res_5, cond_0, ra_rdata_0, rb_rdata_0, rc_rdata_0 - return __0_return_0 diff --git a/sam/onyx/.ast_tools/__call__140154664427872.py b/sam/onyx/.ast_tools/__call__140154664427872.py deleted file mode 100644 index 2cbfdd97..00000000 --- a/sam/onyx/.ast_tools/__call__140154664427872.py +++ /dev/null @@ -1,149 +0,0 @@ -@name_outputs(res=Data, res_p=Bit, Z=Bit, N=Bit, C=Bit, V=Bit) -def __call__( - self, - alu: Const(ALU_t), - signed_: Const(Signed_t), - a: DataPy, - b: DataPy, - c: DataPy, - d: BitPy, -) -> (DataPy, BitPy, BitPy, BitPy, BitPy, BitPy): - _cond_0 = signed_ == Signed_t.signed - mula_0 = UData32(SData(a).sext(16)) - mulb_0 = UData32(SData(b).sext(16)) - mula_1 = UData(a).zext(16) - mulb_1 = UData(b).zext(16) - mula_2 = __phi(_cond_0, mula_0, mula_1) - mulb_2 = __phi(_cond_0, mulb_0, mulb_1) - mul_0 = mula_2 * mulb_2 - _cond_1 = signed_ == Signed_t.signed - lte_pred_0 = SData(a) <= SData(b) - lte_pred_1 = UData(a) <= UData(b) - lte_pred_2 = __phi(_cond_1, lte_pred_0, lte_pred_1) - min_ab_0 = lte_pred_2.ite(a, b) - _cond_2 = alu == ALU_t.CROP - max_in0_0 = min_ab_0 - max_in0_1 = b - max_in0_2 = __phi(_cond_2, max_in0_0, max_in0_1) - _cond_3 = signed_ == Signed_t.signed - gte_pred_0 = SData(max_in0_2) >= SData(c) - gte_pred_1 = UData(max_in0_2) >= UData(c) - gte_pred_2 = __phi(_cond_3, gte_pred_0, gte_pred_1) - max_bc_0 = gte_pred_2.ite(max_in0_2, c) - _cond_4 = alu == ALU_t.MULSHR - shr_in0_0 = mul_0[:16] - shr_in0_1 = a - shr_in0_2 = __phi(_cond_4, shr_in0_0, shr_in0_1) - _cond_5 = signed_ == Signed_t.signed - shr_0 = Data(SData(shr_in0_2) >> SData(c)) - shr_1 = Data(UData(shr_in0_2) >> UData(c)) - shr_2 = __phi(_cond_5, shr_0, shr_1) - _cond_6 = (alu == ALU_t.Sbc) | (alu == ALU_t.TSA) | (alu == ALU_t.TSS) - b_0 = ~b - b_1 = __phi(_cond_6, b_0, b) - - Cin_0 = d - - # factor out comman add - adder_res_0, adder_C_0 = UData(a).adc(UData(b_1), Cin_0) - _cond_7 = ( - (alu == ALU_t.TAA) - | (alu == ALU_t.TAS) - | (alu == ALU_t.TSA) - | (alu == ALU_t.TSS) - ) - adder2_in0_0 = adder_res_0 - adder2_in0_1 = mul_0[:16] - adder2_in0_2 = __phi(_cond_7, adder2_in0_0, adder2_in0_1) - _cond_8 = (alu == ALU_t.MULSUB) | (alu == ALU_t.TAS) | (alu == ALU_t.TSS) - adder2_in1_0 = ~c - Cin2_0 = Bit(1) - adder2_in1_1 = c - Cin2_1 = Bit(0) - Cin2_2 = __phi(_cond_8, Cin2_0, Cin2_1) - adder2_in1_2 = __phi(_cond_8, adder2_in1_0, adder2_in1_1) - - adder2_res_0, adder2_C_0 = UData(adder2_in0_2).adc(adder2_in1_2, Cin2_2) - - C_0 = Bit(0) - V_0 = Bit(0) - _cond_21 = (alu == ALU_t.Adc) | (alu == ALU_t.Sbc) - res_0, C_1 = adder_res_0, adder_C_0 - V_1 = overflow(a, b_1, res_0) - res_p_0 = C_1 - _cond_20 = alu == ALU_t.Mult0 - res_1, C_2, V_2 = mul_0[:16], Bit(0), Bit(0) - res_p_1 = C_2 - _cond_19 = alu == ALU_t.Mult1 - res_2, C_3, V_3 = mul_0[8:24], Bit(0), Bit(0) - res_p_2 = C_3 - _cond_18 = alu == ALU_t.Mult2 - res_3, C_4, V_4 = mul_0[16:32], Bit(0), Bit(0) - res_p_3 = C_4 - _cond_17 = alu == ALU_t.Abs - abs_pred_0 = SData(a) >= SData(0) - res_4, res_p_4 = abs_pred_0.ite(a, UInt[16](-SInt[16](a))), Bit(a[-1]) - _cond_16 = alu == ALU_t.Sel - res_5, res_p_5 = d.ite(a, b_1), Bit(0) - _cond_15 = alu == ALU_t.And - res_6, res_p_6 = a & b_1, Bit(0) - _cond_14 = alu == ALU_t.Or - res_7, res_p_7 = a | b_1, Bit(0) - _cond_13 = alu == ALU_t.XOr - res_8, res_p_8 = a ^ b_1, Bit(0) - _cond_12 = alu == ALU_t.SHR - res_9, res_p_9 = shr_2, Bit(0) - _cond_11 = alu == ALU_t.SHL - res_10, res_p_10 = a << b_1, Bit(0) - _cond_10 = ( - (alu == ALU_t.MULADD) - | (alu == ALU_t.MULSUB) - | (alu == ALU_t.TAA) - | (alu == ALU_t.TSA) - | (alu == ALU_t.TAS) - | (alu == ALU_t.TSS) - ) - res_11, res_p_11 = adder2_res_0, Bit(0) - _cond_9 = alu == ALU_t.CROP - res_12, res_p_12 = max_bc_0, Bit(0) - res_13, res_p_13 = shr_2, Bit(0) - res_14 = __phi(_cond_9, res_12, res_13) - res_p_14 = __phi(_cond_9, res_p_12, res_p_13) - res_15 = __phi(_cond_10, res_11, res_14) - res_p_15 = __phi(_cond_10, res_p_11, res_p_14) - res_16 = __phi(_cond_11, res_10, res_15) - res_p_16 = __phi(_cond_11, res_p_10, res_p_15) - res_17 = __phi(_cond_12, res_9, res_16) - res_p_17 = __phi(_cond_12, res_p_9, res_p_16) - res_18 = __phi(_cond_13, res_8, res_17) - res_p_18 = __phi(_cond_13, res_p_8, res_p_17) - res_19 = __phi(_cond_14, res_7, res_18) - res_p_19 = __phi(_cond_14, res_p_7, res_p_18) - res_20 = __phi(_cond_15, res_6, res_19) - res_p_20 = __phi(_cond_15, res_p_6, res_p_19) - res_21 = __phi(_cond_16, res_5, res_20) - res_p_21 = __phi(_cond_16, res_p_5, res_p_20) - res_22 = __phi(_cond_17, res_4, res_21) - res_p_22 = __phi(_cond_17, res_p_4, res_p_21) - C_5 = __phi(_cond_18, C_4, C_0) - V_5 = __phi(_cond_18, V_4, V_0) - res_23 = __phi(_cond_18, res_3, res_22) - res_p_23 = __phi(_cond_18, res_p_3, res_p_22) - C_6 = __phi(_cond_19, C_3, C_5) - V_6 = __phi(_cond_19, V_3, V_5) - res_24 = __phi(_cond_19, res_2, res_23) - res_p_24 = __phi(_cond_19, res_p_2, res_p_23) - C_7 = __phi(_cond_20, C_2, C_6) - V_7 = __phi(_cond_20, V_2, V_6) - res_25 = __phi(_cond_20, res_1, res_24) - res_p_25 = __phi(_cond_20, res_p_1, res_p_24) - C_8 = __phi(_cond_21, C_1, C_7) - V_8 = __phi(_cond_21, V_1, V_7) - res_26 = __phi(_cond_21, res_0, res_25) - res_p_26 = __phi(_cond_21, res_p_0, res_p_25) - - N_0 = Bit(res_26[-1]) - Z_0 = res_26 == SData(0) - - __0_return_0 = res_26, res_p_26, Z_0, N_0, C_8, V_8 - return __0_return_0 diff --git a/sam/onyx/.ast_tools/__call__140154666299744.py b/sam/onyx/.ast_tools/__call__140154666299744.py deleted file mode 100644 index 678a8cde..00000000 --- a/sam/onyx/.ast_tools/__call__140154666299744.py +++ /dev/null @@ -1,7 +0,0 @@ -def __call__(self, in0: Data, in1: Data) -> Data: - in0_float_0 = cast(in0) - in1_float_0 = cast(in1) - out_float_0 = getattr(in0_float_0, op_name)(in1_float_0) - out_0 = out_float_0.reinterpret_as_bv() - __0_return_0 = out_0 - return __0_return_0 diff --git a/sam/onyx/.ast_tools/__call__140154666347536.py b/sam/onyx/.ast_tools/__call__140154666347536.py deleted file mode 100644 index c159114e..00000000 --- a/sam/onyx/.ast_tools/__call__140154666347536.py +++ /dev/null @@ -1,40 +0,0 @@ -@name_outputs(res=Data, N=Bit, Z=Bit) -def __call__(self, fpu_op: Const(FPU_t), a: Data, b: Data) -> (Data, Bit, Bit): - - a_inf_0 = fp_is_inf(a) - b_inf_0 = fp_is_inf(b) - a_neg_0 = fp_is_neg(a) - b_neg_0 = fp_is_neg(b) - - old_b_0 = b - neg_b_0 = (fpu_op == FPU_t.FP_sub) | (fpu_op == FPU_t.FP_cmp) | (fpu_op == FPU_t.FP_max) - _cond_0 = neg_b_0 - b_0 = b ^ (2 ** (16 - 1)) - b_1 = __phi(_cond_0, b_0, b) - Add_val_0 = self.Add(a, b_1) - Mul_val_0 = self.Mul(a, b_1) - _cond_3 = ( - (fpu_op == FPU_t.FP_add) - | (fpu_op == FPU_t.FP_sub) - | (fpu_op == FPU_t.FP_cmp) - ) - res_0 = Add_val_0 - _cond_2 = (fpu_op == FPU_t.FP_max) - _cond_1 = family.Bit(Add_val_0[-1]) - res_1 = old_b_0 - res_2 = a - res_3 = __phi(_cond_1, res_1, res_2) - res_4 = Mul_val_0 - res_5 = __phi(_cond_2, res_3, res_4) - res_6 = __phi(_cond_3, res_0, res_5) - - Z_0 = fp_is_zero(res_6) - _cond_5 = fpu_op == FPU_t.FP_cmp - _cond_4 = (a_inf_0 & b_inf_0) & (a_neg_0 == b_neg_0) - Z_1 = family.Bit(1) - Z_2 = __phi(_cond_4, Z_1, Z_0) - Z_3 = __phi(_cond_5, Z_2, Z_0) - - N_0 = family.Bit(res_6[-1]) - __0_return_0 = res_6, N_0, Z_3 - return __0_return_0 diff --git a/sam/onyx/.ast_tools/__call__140154670632384.py b/sam/onyx/.ast_tools/__call__140154670632384.py deleted file mode 100644 index 215df2df..00000000 --- a/sam/onyx/.ast_tools/__call__140154670632384.py +++ /dev/null @@ -1,44 +0,0 @@ -@name_outputs(cond=Bit) -def __call__( - self, code: Cond_t, alu: Bit, lut: Bit, Z: Bit, N: Bit, C: Bit, V: Bit -) -> Bit: - _cond_18 = code == Cond_t.Z - __0_return_0 = Z - _cond_17 = code == Cond_t.Z_n - __0_return_1 = ~Z - _cond_16 = (code == Cond_t.C) | (code == Cond_t.UGE) - __0_return_2 = C - _cond_15 = (code == Cond_t.C_n) | (code == Cond_t.ULT) - __0_return_3 = ~C - _cond_14 = code == Cond_t._N - __0_return_4 = N - _cond_13 = code == Cond_t._N_n - __0_return_5 = ~N - _cond_12 = code == Cond_t.V - __0_return_6 = V - _cond_11 = code == Cond_t.V_n - __0_return_7 = ~V - _cond_10 = code == Cond_t.UGT - __0_return_8 = C & (~Z) - _cond_9 = code == Cond_t.ULE - __0_return_9 = (~C) | Z - _cond_8 = code == Cond_t.SGE - __0_return_10 = N == V - _cond_7 = code == Cond_t.SLT - __0_return_11 = N != V - _cond_6 = code == Cond_t.SGT - __0_return_12 = (~Z) & (N == V) - _cond_5 = code == Cond_t.SLE - __0_return_13 = Z | (N != V) - _cond_4 = code == Cond_t.ALU - __0_return_14 = alu - _cond_3 = code == Cond_t.LUT - __0_return_15 = lut - _cond_2 = code == Cond_t.FP_GE - __0_return_16 = ~N | Z - _cond_1 = code == Cond_t.FP_GT - __0_return_17 = ~N & ~Z - _cond_0 = code == Cond_t.FP_LE - __0_return_18 = N | Z - __0_return_19 = N & ~Z - return __phi(_cond_18, __0_return_0, __phi(_cond_17, __0_return_1, __phi(_cond_16, __0_return_2, __phi(_cond_15, __0_return_3, __phi(_cond_14, __0_return_4, __phi(_cond_13, __0_return_5, __phi(_cond_12, __0_return_6, __phi(_cond_11, __0_return_7, __phi(_cond_10, __0_return_8, __phi(_cond_9, __0_return_9, __phi(_cond_8, __0_return_10, __phi(_cond_7, __0_return_11, __phi(_cond_6, __0_return_12, __phi(_cond_5, __0_return_13, __phi(_cond_4, __0_return_14, __phi(_cond_3, __0_return_15, __phi(_cond_2, __0_return_16, __phi(_cond_1, __0_return_17, __phi(_cond_0, __0_return_18, __0_return_19))))))))))))))))))) diff --git a/sam/onyx/.ast_tools/__call__140154671532352.py b/sam/onyx/.ast_tools/__call__140154671532352.py deleted file mode 100644 index 678a8cde..00000000 --- a/sam/onyx/.ast_tools/__call__140154671532352.py +++ /dev/null @@ -1,7 +0,0 @@ -def __call__(self, in0: Data, in1: Data) -> Data: - in0_float_0 = cast(in0) - in1_float_0 = cast(in1) - out_float_0 = getattr(in0_float_0, op_name)(in1_float_0) - out_0 = out_float_0.reinterpret_as_bv() - __0_return_0 = out_0 - return __0_return_0 diff --git a/sam/onyx/.ast_tools/__call__140154674464224.py b/sam/onyx/.ast_tools/__call__140154674464224.py deleted file mode 100644 index c8f4fa5a..00000000 --- a/sam/onyx/.ast_tools/__call__140154674464224.py +++ /dev/null @@ -1,16 +0,0 @@ -def __call__( - self, mode: Mode_t, const_: T, value: T, clk_en: Bit -) -> (T, T): - _cond_0 = mode == Mode_t.DELAY - data_0, en_0 = value, clk_en - data_1, en_1 = value, Bit(0) - data_2 = __phi(_cond_0, data_0, data_1) - en_2 = __phi(_cond_0, en_0, en_1) - - reg_val_0 = self.register(data_2, en_2) - _cond_2 = mode == Mode_t.CONST - __0_return_0 = const_, reg_val_0 - _cond_1 = mode == Mode_t.BYPASS - __0_return_1 = value, reg_val_0 - __0_return_2 = reg_val_0, reg_val_0 - return __phi(_cond_2, __0_return_0, __phi(_cond_1, __0_return_1, __0_return_2)) diff --git a/sam/onyx/.ast_tools/__call__140154676057280.py b/sam/onyx/.ast_tools/__call__140154676057280.py deleted file mode 100644 index c8f4fa5a..00000000 --- a/sam/onyx/.ast_tools/__call__140154676057280.py +++ /dev/null @@ -1,16 +0,0 @@ -def __call__( - self, mode: Mode_t, const_: T, value: T, clk_en: Bit -) -> (T, T): - _cond_0 = mode == Mode_t.DELAY - data_0, en_0 = value, clk_en - data_1, en_1 = value, Bit(0) - data_2 = __phi(_cond_0, data_0, data_1) - en_2 = __phi(_cond_0, en_0, en_1) - - reg_val_0 = self.register(data_2, en_2) - _cond_2 = mode == Mode_t.CONST - __0_return_0 = const_, reg_val_0 - _cond_1 = mode == Mode_t.BYPASS - __0_return_1 = value, reg_val_0 - __0_return_2 = reg_val_0, reg_val_0 - return __phi(_cond_2, __0_return_0, __phi(_cond_1, __0_return_1, __0_return_2)) diff --git a/sam/onyx/.ast_tools/__call__140154676060016.py b/sam/onyx/.ast_tools/__call__140154676060016.py deleted file mode 100644 index 0e11d13a..00000000 --- a/sam/onyx/.ast_tools/__call__140154676060016.py +++ /dev/null @@ -1,236 +0,0 @@ -@name_outputs(res=Data, res_p=Bit, V=Bit) -def __call__( - self, op: Const(FPCustom_t), signed_: Const(Signed_t), a: Data, b: Data -) -> (Data, Bit, Bit): - _cond_27 = op == FPCustom_t.FCnvExp2F - expa0_0 = BitVector[8](a[7:15]) - biased_exp0_0 = SInt[9](expa0_0.zext(1)) - unbiased_exp0_0 = SInt[9](biased_exp0_0 - SInt[9](127)) - _cond_0 = unbiased_exp0_0 < 0 - sign_0 = BitVector[16](0x8000) - abs_exp0_0 = -unbiased_exp0_0 - sign_1 = BitVector[16](0x0000) - abs_exp0_1 = unbiased_exp0_0 - abs_exp0_2 = __phi(_cond_0, abs_exp0_0, abs_exp0_1) - sign_2 = __phi(_cond_0, sign_0, sign_1) - abs_exp_0 = BitVector[8](abs_exp0_2[0:8]) - scale_0 = SInt[16](-127) - _cond_1 = abs_exp_0[0] == Bit(1) - scale_1 = SInt[16](0) - scale_2 = __phi(_cond_1, scale_1, scale_0) - _cond_2 = abs_exp_0[1] == Bit(1) - scale_3 = SInt[16](1) - scale_4 = __phi(_cond_2, scale_3, scale_2) - _cond_3 = abs_exp_0[2] == Bit(1) - scale_5 = SInt[16](2) - scale_6 = __phi(_cond_3, scale_5, scale_4) - _cond_4 = abs_exp_0[3] == Bit(1) - scale_7 = SInt[16](3) - scale_8 = __phi(_cond_4, scale_7, scale_6) - _cond_5 = abs_exp_0[4] == Bit(1) - scale_9 = SInt[16](4) - scale_10 = __phi(_cond_5, scale_9, scale_8) - _cond_6 = abs_exp_0[5] == Bit(1) - scale_11 = SInt[16](5) - scale_12 = __phi(_cond_6, scale_11, scale_10) - _cond_7 = abs_exp_0[6] == Bit(1) - scale_13 = SInt[16](6) - scale_14 = __phi(_cond_7, scale_13, scale_12) - _cond_8 = abs_exp_0[7] == Bit(1) - scale_15 = SInt[16](7) - scale_16 = __phi(_cond_8, scale_15, scale_14) - normmant_mul_left_0 = SInt[16](abs_exp_0) - normmant_mul_right_0 = SInt[16](7) - scale_16 - normmant_mask_0 = SInt[16](0x7F) - _cond_9 = signed_ == Signed_t.signed - sign_3 = BitVector[16](a & 0x8000) - sign_4 = BitVector[16](0) - sign_5 = __phi(_cond_9, sign_3, sign_4) - _cond_10 = sign_5[15] == Bit(1) - abs_input_0 = BitVector[16](-SInt[16](a)) - abs_input_1 = BitVector[16](a) - abs_input_2 = __phi(_cond_10, abs_input_0, abs_input_1) - scale_17 = SInt[16](-127) - _cond_11 = abs_input_2[0] == Bit(1) - scale_18 = SInt[16](0) - scale_19 = __phi(_cond_11, scale_18, scale_17) - _cond_12 = abs_input_2[1] == Bit(1) - scale_20 = SInt[16](1) - scale_21 = __phi(_cond_12, scale_20, scale_19) - _cond_13 = abs_input_2[2] == Bit(1) - scale_22 = SInt[16](2) - scale_23 = __phi(_cond_13, scale_22, scale_21) - _cond_14 = abs_input_2[3] == Bit(1) - scale_24 = SInt[16](3) - scale_25 = __phi(_cond_14, scale_24, scale_23) - _cond_15 = abs_input_2[4] == Bit(1) - scale_26 = SInt[16](4) - scale_27 = __phi(_cond_15, scale_26, scale_25) - _cond_16 = abs_input_2[5] == Bit(1) - scale_28 = SInt[16](5) - scale_29 = __phi(_cond_16, scale_28, scale_27) - _cond_17 = abs_input_2[6] == Bit(1) - scale_30 = SInt[16](6) - scale_31 = __phi(_cond_17, scale_30, scale_29) - _cond_18 = abs_input_2[7] == Bit(1) - scale_32 = SInt[16](7) - scale_33 = __phi(_cond_18, scale_32, scale_31) - _cond_19 = abs_input_2[8] == Bit(1) - scale_34 = SInt[16](8) - scale_35 = __phi(_cond_19, scale_34, scale_33) - _cond_20 = abs_input_2[9] == Bit(1) - scale_36 = SInt[16](9) - scale_37 = __phi(_cond_20, scale_36, scale_35) - _cond_21 = abs_input_2[10] == Bit(1) - scale_38 = SInt[16](10) - scale_39 = __phi(_cond_21, scale_38, scale_37) - _cond_22 = abs_input_2[11] == Bit(1) - scale_40 = SInt[16](11) - scale_41 = __phi(_cond_22, scale_40, scale_39) - _cond_23 = abs_input_2[12] == Bit(1) - scale_42 = SInt[16](12) - scale_43 = __phi(_cond_23, scale_42, scale_41) - _cond_24 = abs_input_2[13] == Bit(1) - scale_44 = SInt[16](13) - scale_45 = __phi(_cond_24, scale_44, scale_43) - _cond_25 = abs_input_2[14] == Bit(1) - scale_46 = SInt[16](14) - scale_47 = __phi(_cond_25, scale_46, scale_45) - _cond_26 = abs_input_2[15] == Bit(1) - scale_48 = SInt[16](15) - scale_49 = __phi(_cond_26, scale_48, scale_47) - normmant_mul_left_1 = SInt[16](abs_input_2) - normmant_mul_right_1 = SInt[16](15) - scale_49 - normmant_mask_1 = SInt[16](0x7F00) - normmant_mask_2 = __phi(_cond_27, normmant_mask_0, normmant_mask_1) - normmant_mul_left_2 = __phi(_cond_27, normmant_mul_left_0, normmant_mul_left_1) - normmant_mul_right_2 = __phi(_cond_27, normmant_mul_right_0, normmant_mul_right_1) - scale_50 = __phi(_cond_27, scale_16, scale_49) - sign_6 = __phi(_cond_27, sign_2, sign_5) - _cond_28 = scale_50 >= 0 - normmant_0 = BitVector[16]( - (normmant_mul_left_2 << normmant_mul_right_2) & normmant_mask_2 - ) - normmant_1 = BitVector[16](0) - normmant_2 = __phi(_cond_28, normmant_0, normmant_1) - _cond_29 = op == FPCustom_t.FCnvInt2F - normmant_3 = BitVector[16](normmant_2) >> 8 - normmant_4 = __phi(_cond_29, normmant_3, normmant_2) - - biased_scale_0 = scale_50 + 127 - to_float_result_0 = ( - sign_6 | ((BitVector[16](biased_scale_0) << 7) & (0xFF << 7)) | normmant_4 - ) - - V_0 = Bit(0) - _cond_39 = op == FPCustom_t.FGetMant - res_0, res_p_0 = (a & 0x7F), Bit(0) - _cond_38 = op == FPCustom_t.FAddIExp - sign_7 = BitVector[16]((a & 0x8000)) - exp_0 = UData(a)[7:15] - exp_check_0 = exp_0.zext(1) - exp_1 = exp_0 + UData(b)[0:8] - exp_check_1 = exp_check_0 + UData(b)[0:9] - # Augassign not supported by magma yet - # exp += SInt[8](b[0:8]) - # exp_check += SInt[9](b[0:9]) - exp_shift_0 = BitVector[16](exp_1) - exp_shift_1 = exp_shift_0 << 7 - mant_0 = BitVector[16]((a & 0x7F)) - res_1, res_p_1 = (sign_7 | exp_shift_1 | mant_0), (exp_check_1 > 255) - _cond_37 = op == FPCustom_t.FSubExp - signa_0 = BitVector[16]((a & 0x8000)) - expa_0 = UData(a)[7:15] - signb_0 = BitVector[16]((b & 0x8000)) - expb_0 = UData(b)[7:15] - expa_1 = expa_0 - expb_0 + 127 - exp_shift_2 = BitVector[16](expa_1) - exp_shift_3 = exp_shift_2 << 7 - manta_0 = BitVector[16]((a & 0x7F)) - res_2, res_p_2 = ((signa_0 | signb_0) | exp_shift_3 | manta_0), Bit(0) - _cond_36 = op == FPCustom_t.FCnvExp2F - res_3, res_p_3 = to_float_result_0, Bit(0) - _cond_35 = op == FPCustom_t.FGetFInt - signa_1 = BitVector[16]((a & 0x8000)) - manta_1 = BitVector[16]((a & 0x7F)) | 0x80 - expa0_1 = UData(a)[7:15] - biased_exp0_1 = SInt[9](expa0_1.zext(1)) - unbiased_exp0_1 = SInt[9](biased_exp0_1 - SInt[9](127)) - _cond_30 = unbiased_exp0_1 < 0 - manta_shift0_0 = BitVector[23](0) - manta_shift0_1 = BitVector[23](manta_1) << BitVector[23](unbiased_exp0_1) - manta_shift0_2 = __phi(_cond_30, manta_shift0_0, manta_shift0_1) - unsigned_res0_0 = BitVector[23](manta_shift0_2 >> BitVector[23](7)) - unsigned_res_0 = BitVector[16](unsigned_res0_0[0:16]) - _cond_31 = signa_1 == 0x8000 - signed_res_0 = -SInt[16](unsigned_res_0) - signed_res_1 = SInt[16](unsigned_res_0) - signed_res_2 = __phi(_cond_31, signed_res_0, signed_res_1) - # We are not checking for overflow when converting to int - res_4, res_p_4, V_1 = signed_res_2, Bit(0), (expa0_1 > BitVector[8](142)) - _cond_34 = op == FPCustom_t.FGetFFrac - signa_2 = BitVector[16]((a & 0x8000)) - manta_2 = BitVector[16]((a & 0x7F)) | 0x80 - expa0_2 = BitVector[8](a[7:15]) - biased_exp0_2 = SInt[9](expa0_2.zext(1)) - unbiased_exp0_2 = SInt[9](biased_exp0_2 - SInt[9](127)) - _cond_32 = unbiased_exp0_2 < 0 - manta_shift1_0 = BitVector[16](manta_2) >> BitVector[16](-unbiased_exp0_2) - manta_shift1_1 = BitVector[16](manta_2) << BitVector[16](unbiased_exp0_2) - manta_shift1_2 = __phi(_cond_32, manta_shift1_0, manta_shift1_1) - unsigned_res_1 = BitVector[16]((manta_shift1_2 & 0x07F)) - _cond_33 = signa_2 == 0x8000 - signed_res_3 = -SInt[16](unsigned_res_1) - signed_res_4 = SInt[16](unsigned_res_1) - signed_res_5 = __phi(_cond_33, signed_res_3, signed_res_4) - - # We are not checking for overflow when converting to int - res_5, res_p_5 = signed_res_5, Bit(0) - res_6, res_p_6 = to_float_result_0, Bit(0) - biased_exp0_3 = __phi(_cond_34, biased_exp0_2, biased_exp0_0) - expa0_3 = __phi(_cond_34, expa0_2, expa0_0) - res_7 = __phi(_cond_34, res_5, res_6) - res_p_7 = __phi(_cond_34, res_p_5, res_p_6) - unbiased_exp0_3 = __phi(_cond_34, unbiased_exp0_2, unbiased_exp0_0) - V_2 = __phi(_cond_35, V_1, V_0) - biased_exp0_4 = __phi(_cond_35, biased_exp0_1, biased_exp0_3) - expa0_4 = __phi(_cond_35, expa0_1, expa0_3) - manta_3 = __phi(_cond_35, manta_1, manta_2) - res_8 = __phi(_cond_35, res_4, res_7) - res_p_8 = __phi(_cond_35, res_p_4, res_p_7) - signa_3 = __phi(_cond_35, signa_1, signa_2) - signed_res_6 = __phi(_cond_35, signed_res_2, signed_res_5) - unbiased_exp0_4 = __phi(_cond_35, unbiased_exp0_1, unbiased_exp0_3) - unsigned_res_2 = __phi(_cond_35, unsigned_res_0, unsigned_res_1) - V_3 = __phi(_cond_36, V_0, V_2) - biased_exp0_5 = __phi(_cond_36, biased_exp0_0, biased_exp0_4) - expa0_5 = __phi(_cond_36, expa0_0, expa0_4) - res_9 = __phi(_cond_36, res_3, res_8) - res_p_9 = __phi(_cond_36, res_p_3, res_p_8) - unbiased_exp0_5 = __phi(_cond_36, unbiased_exp0_0, unbiased_exp0_4) - V_4 = __phi(_cond_37, V_0, V_3) - biased_exp0_6 = __phi(_cond_37, biased_exp0_0, biased_exp0_5) - expa0_6 = __phi(_cond_37, expa0_0, expa0_5) - manta_4 = __phi(_cond_37, manta_0, manta_3) - res_10 = __phi(_cond_37, res_2, res_9) - res_p_10 = __phi(_cond_37, res_p_2, res_p_9) - signa_4 = __phi(_cond_37, signa_0, signa_3) - unbiased_exp0_6 = __phi(_cond_37, unbiased_exp0_0, unbiased_exp0_5) - V_5 = __phi(_cond_38, V_0, V_4) - biased_exp0_7 = __phi(_cond_38, biased_exp0_0, biased_exp0_6) - exp_shift_4 = __phi(_cond_38, exp_shift_1, exp_shift_3) - expa0_7 = __phi(_cond_38, expa0_0, expa0_6) - res_11 = __phi(_cond_38, res_1, res_10) - res_p_11 = __phi(_cond_38, res_p_1, res_p_10) - sign_8 = __phi(_cond_38, sign_7, sign_6) - unbiased_exp0_7 = __phi(_cond_38, unbiased_exp0_0, unbiased_exp0_6) - V_6 = __phi(_cond_39, V_0, V_5) - biased_exp0_8 = __phi(_cond_39, biased_exp0_0, biased_exp0_7) - expa0_8 = __phi(_cond_39, expa0_0, expa0_7) - res_12 = __phi(_cond_39, res_0, res_11) - res_p_12 = __phi(_cond_39, res_p_0, res_p_11) - sign_9 = __phi(_cond_39, sign_6, sign_8) - unbiased_exp0_8 = __phi(_cond_39, unbiased_exp0_0, unbiased_exp0_7) - - __0_return_0 = res_12, res_p_12, V_6 - return __0_return_0 diff --git a/sam/onyx/.ast_tools/__init__140020533738944.py b/sam/onyx/.ast_tools/__init__140020533738944.py deleted file mode 100644 index 5b8fa05f..00000000 --- a/sam/onyx/.ast_tools/__init__140020533738944.py +++ /dev/null @@ -1,3 +0,0 @@ -def __init__(self): - self._input_vals = None - self._output_vals = None diff --git a/sam/onyx/.ast_tools/__init__140020533770704.py b/sam/onyx/.ast_tools/__init__140020533770704.py deleted file mode 100644 index 5b8fa05f..00000000 --- a/sam/onyx/.ast_tools/__init__140020533770704.py +++ /dev/null @@ -1,3 +0,0 @@ -def __init__(self): - self._input_vals = None - self._output_vals = None diff --git a/sam/onyx/.ast_tools/__init__140020542815392.py b/sam/onyx/.ast_tools/__init__140020542815392.py deleted file mode 100644 index 64feacbc..00000000 --- a/sam/onyx/.ast_tools/__init__140020542815392.py +++ /dev/null @@ -1,3 +0,0 @@ -def __init__(self): - self.Add: FPAdd = FPAdd() - self.Mul: FPU_Mul_10_Bit_Rounding = FPU_Mul_10_Bit_Rounding() diff --git a/sam/onyx/.ast_tools/__init__140020546324656.py b/sam/onyx/.ast_tools/__init__140020546324656.py deleted file mode 100644 index b795dcb9..00000000 --- a/sam/onyx/.ast_tools/__init__140020546324656.py +++ /dev/null @@ -1,2 +0,0 @@ -def __init__(self): - self.register: Reg = Reg() diff --git a/sam/onyx/.ast_tools/__init__140020552380624.py b/sam/onyx/.ast_tools/__init__140020552380624.py deleted file mode 100644 index b795dcb9..00000000 --- a/sam/onyx/.ast_tools/__init__140020552380624.py +++ /dev/null @@ -1,2 +0,0 @@ -def __init__(self): - self.register: Reg = Reg() diff --git a/sam/onyx/.ast_tools/__init__140154664293712.py b/sam/onyx/.ast_tools/__init__140154664293712.py deleted file mode 100644 index d8f39601..00000000 --- a/sam/onyx/.ast_tools/__init__140154664293712.py +++ /dev/null @@ -1,22 +0,0 @@ -def __init__(self): - - # Data registers - self.rega: DataReg = DataReg() - self.regb: DataReg = DataReg() - self.regc: DataReg = DataReg() - - # Bit Registers - self.regd: BitReg = BitReg() - self.rege: BitReg = BitReg() - self.regf: BitReg = BitReg() - - # Execution - self.alu: ALU = ALU() - self.fpu: FPU = FPU() - self.fp_custom: FPCustom = FPCustom() - - # Lut - self.lut: LUT = LUT() - - # Condition code - self.cond: Cond = Cond() diff --git a/sam/onyx/.ast_tools/__init__140154666302624.py b/sam/onyx/.ast_tools/__init__140154666302624.py deleted file mode 100644 index 64feacbc..00000000 --- a/sam/onyx/.ast_tools/__init__140154666302624.py +++ /dev/null @@ -1,3 +0,0 @@ -def __init__(self): - self.Add: FPAdd = FPAdd() - self.Mul: FPU_Mul_10_Bit_Rounding = FPU_Mul_10_Bit_Rounding() diff --git a/sam/onyx/.ast_tools/__init__140154671533504.py b/sam/onyx/.ast_tools/__init__140154671533504.py deleted file mode 100644 index 5b8fa05f..00000000 --- a/sam/onyx/.ast_tools/__init__140154671533504.py +++ /dev/null @@ -1,3 +0,0 @@ -def __init__(self): - self._input_vals = None - self._output_vals = None diff --git a/sam/onyx/.ast_tools/__init__140154671569360.py b/sam/onyx/.ast_tools/__init__140154671569360.py deleted file mode 100644 index 5b8fa05f..00000000 --- a/sam/onyx/.ast_tools/__init__140154671569360.py +++ /dev/null @@ -1,3 +0,0 @@ -def __init__(self): - self._input_vals = None - self._output_vals = None diff --git a/sam/onyx/.ast_tools/__init__140154675218608.py b/sam/onyx/.ast_tools/__init__140154675218608.py deleted file mode 100644 index b795dcb9..00000000 --- a/sam/onyx/.ast_tools/__init__140154675218608.py +++ /dev/null @@ -1,2 +0,0 @@ -def __init__(self): - self.register: Reg = Reg() diff --git a/sam/onyx/.ast_tools/__init__140154681262288.py b/sam/onyx/.ast_tools/__init__140154681262288.py deleted file mode 100644 index b795dcb9..00000000 --- a/sam/onyx/.ast_tools/__init__140154681262288.py +++ /dev/null @@ -1,2 +0,0 @@ -def __init__(self): - self.register: Reg = Reg() diff --git a/sam/onyx/.magma/ExclusiveNodeFanout_H2-kratos.sv b/sam/onyx/.magma/ExclusiveNodeFanout_H2-kratos.sv deleted file mode 100644 index 6182f382..00000000 --- a/sam/onyx/.magma/ExclusiveNodeFanout_H2-kratos.sv +++ /dev/null @@ -1,9 +0,0 @@ -module ExclusiveNodeFanout_H2 ( - input logic [1:0] I, - input logic [1:0] S, - output logic O -); - -assign O = (I[0] & S[0]) | (I[1] & S[1]); -endmodule // ExclusiveNodeFanout_H2 - diff --git a/sam/onyx/.magma/FanoutHash_1130FCC7DFE98006-kratos.sv b/sam/onyx/.magma/FanoutHash_1130FCC7DFE98006-kratos.sv deleted file mode 100644 index 79e5bc79..00000000 --- a/sam/onyx/.magma/FanoutHash_1130FCC7DFE98006-kratos.sv +++ /dev/null @@ -1,37 +0,0 @@ -module FanoutHash_1130FCC7DFE98006 ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -assign sel0 = (~E0) | (~S0[1]) | I0; -assign sel1 = (~E1) | (~S1[2]) | I1; -assign sel2 = (~E2) | (~S2[0]) | I2; -assign sel3 = (~E3) | (~S3[6]) | I3; -assign sel4 = (~E4) | (~S4[6]) | I4; -assign sel5 = (~E5) | (~S5[6]) | I5; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5; -endmodule // FanoutHash_1130FCC7DFE98006 - diff --git a/sam/onyx/.magma/FanoutHash_11B554A18790BBBC-kratos.sv b/sam/onyx/.magma/FanoutHash_11B554A18790BBBC-kratos.sv deleted file mode 100644 index 9dfab7a9..00000000 --- a/sam/onyx/.magma/FanoutHash_11B554A18790BBBC-kratos.sv +++ /dev/null @@ -1,37 +0,0 @@ -module FanoutHash_11B554A18790BBBC ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -assign sel0 = (~E0) | (~S0[1]) | I0; -assign sel1 = (~E1) | (~S1[1]) | I1; -assign sel2 = (~E2) | (~S2[2]) | I2; -assign sel3 = (~E3) | (~S3[18]) | I3; -assign sel4 = (~E4) | (~S4[18]) | I4; -assign sel5 = (~E5) | (~S5[18]) | I5; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5; -endmodule // FanoutHash_11B554A18790BBBC - diff --git a/sam/onyx/.magma/FanoutHash_13B77C2790BDE4E2-kratos.sv b/sam/onyx/.magma/FanoutHash_13B77C2790BDE4E2-kratos.sv deleted file mode 100644 index 13cb393a..00000000 --- a/sam/onyx/.magma/FanoutHash_13B77C2790BDE4E2-kratos.sv +++ /dev/null @@ -1,37 +0,0 @@ -module FanoutHash_13B77C2790BDE4E2 ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -assign sel0 = (~E0) | (~S0[1]) | I0; -assign sel1 = (~E1) | (~S1[2]) | I1; -assign sel2 = (~E2) | (~S2[1]) | I2; -assign sel3 = (~E3) | (~S3[13]) | I3; -assign sel4 = (~E4) | (~S4[13]) | I4; -assign sel5 = (~E5) | (~S5[13]) | I5; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5; -endmodule // FanoutHash_13B77C2790BDE4E2 - diff --git a/sam/onyx/.magma/FanoutHash_14EBE1E8E49CA541-kratos.sv b/sam/onyx/.magma/FanoutHash_14EBE1E8E49CA541-kratos.sv deleted file mode 100644 index 2fdff0f7..00000000 --- a/sam/onyx/.magma/FanoutHash_14EBE1E8E49CA541-kratos.sv +++ /dev/null @@ -1,22 +0,0 @@ -module FanoutHash_14EBE1E8E49CA541 ( - input logic E0, - input logic E1, - input logic E2, - input logic I0, - input logic I1, - input logic I2, - input logic [31:0] S0, - input logic [31:0] S1, - input logic [31:0] S2, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -assign sel0 = (~E0) | (~S0[20]) | I0; -assign sel1 = (~E1) | (~S1[20]) | I1; -assign sel2 = (~E2) | (~S2[20]) | I2; -assign O = sel0 & sel1 & sel2; -endmodule // FanoutHash_14EBE1E8E49CA541 - diff --git a/sam/onyx/.magma/FanoutHash_1816466D6957000-kratos.sv b/sam/onyx/.magma/FanoutHash_1816466D6957000-kratos.sv deleted file mode 100644 index 8ea373f6..00000000 --- a/sam/onyx/.magma/FanoutHash_1816466D6957000-kratos.sv +++ /dev/null @@ -1,42 +0,0 @@ -module FanoutHash_1816466D6957000 ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic E6, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic I6, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - input logic [31:0] S6, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -logic sel6; -assign sel0 = (~E0) | (~S0[2]) | I0; -assign sel1 = (~E1) | (~S1[2]) | I1; -assign sel2 = (~E2) | (~S2[2]) | I2; -assign sel3 = (~E3) | (~S3[19]) | I3; -assign sel4 = (~E4) | (~S4[19]) | I4; -assign sel5 = (~E5) | (~S5[19]) | I5; -assign sel6 = (~E6) | (~S6[19]) | I6; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6; -endmodule // FanoutHash_1816466D6957000 - diff --git a/sam/onyx/.magma/FanoutHash_184DFC10DAF19BE9-kratos.sv b/sam/onyx/.magma/FanoutHash_184DFC10DAF19BE9-kratos.sv deleted file mode 100644 index 3bb0346f..00000000 --- a/sam/onyx/.magma/FanoutHash_184DFC10DAF19BE9-kratos.sv +++ /dev/null @@ -1,42 +0,0 @@ -module FanoutHash_184DFC10DAF19BE9 ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic E6, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic I6, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - input logic [31:0] S6, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -logic sel6; -assign sel0 = (~E0) | (~S0[0]) | I0; -assign sel1 = (~E1) | (~S1[2]) | I1; -assign sel2 = (~E2) | (~S2[2]) | I2; -assign sel3 = (~E3) | (~S3[16]) | I3; -assign sel4 = (~E4) | (~S4[16]) | I4; -assign sel5 = (~E5) | (~S5[16]) | I5; -assign sel6 = (~E6) | (~S6[16]) | I6; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6; -endmodule // FanoutHash_184DFC10DAF19BE9 - diff --git a/sam/onyx/.magma/FanoutHash_1A568579D8E9714B-kratos.sv b/sam/onyx/.magma/FanoutHash_1A568579D8E9714B-kratos.sv deleted file mode 100644 index 2360ad99..00000000 --- a/sam/onyx/.magma/FanoutHash_1A568579D8E9714B-kratos.sv +++ /dev/null @@ -1,37 +0,0 @@ -module FanoutHash_1A568579D8E9714B ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -assign sel0 = (~E0) | (~S0[0]) | I0; -assign sel1 = (~E1) | (~S1[2]) | I1; -assign sel2 = (~E2) | (~S2[1]) | I2; -assign sel3 = (~E3) | (~S3[7]) | I3; -assign sel4 = (~E4) | (~S4[7]) | I4; -assign sel5 = (~E5) | (~S5[7]) | I5; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5; -endmodule // FanoutHash_1A568579D8E9714B - diff --git a/sam/onyx/.magma/FanoutHash_1B10C32F008C11AC-kratos.sv b/sam/onyx/.magma/FanoutHash_1B10C32F008C11AC-kratos.sv deleted file mode 100644 index f1625866..00000000 --- a/sam/onyx/.magma/FanoutHash_1B10C32F008C11AC-kratos.sv +++ /dev/null @@ -1,37 +0,0 @@ -module FanoutHash_1B10C32F008C11AC ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -assign sel0 = (~E0) | (~S0[1]) | I0; -assign sel1 = (~E1) | (~S1[1]) | I1; -assign sel2 = (~E2) | (~S2[2]) | I2; -assign sel3 = (~E3) | (~S3[17]) | I3; -assign sel4 = (~E4) | (~S4[17]) | I4; -assign sel5 = (~E5) | (~S5[17]) | I5; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5; -endmodule // FanoutHash_1B10C32F008C11AC - diff --git a/sam/onyx/.magma/FanoutHash_1EBD0270673B29D7-kratos.sv b/sam/onyx/.magma/FanoutHash_1EBD0270673B29D7-kratos.sv deleted file mode 100644 index 40c9a795..00000000 --- a/sam/onyx/.magma/FanoutHash_1EBD0270673B29D7-kratos.sv +++ /dev/null @@ -1,108 +0,0 @@ -module FanoutHash_1EBD0270673B29D7 ( - input logic E0, - input logic E1, - input logic E10, - input logic E11, - input logic E12, - input logic E13, - input logic E14, - input logic E15, - input logic E16, - input logic E17, - input logic E18, - input logic E19, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic E6, - input logic E7, - input logic E8, - input logic E9, - input logic I0, - input logic I1, - input logic I10, - input logic I11, - input logic I12, - input logic I13, - input logic I14, - input logic I15, - input logic I16, - input logic I17, - input logic I18, - input logic I19, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic I6, - input logic I7, - input logic I8, - input logic I9, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S10, - input logic [7:0] S11, - input logic [7:0] S12, - input logic [7:0] S13, - input logic [7:0] S14, - input logic [7:0] S15, - input logic [7:0] S16, - input logic [7:0] S17, - input logic [7:0] S18, - input logic [7:0] S19, - input logic [7:0] S2, - input logic [7:0] S3, - input logic [7:0] S4, - input logic [7:0] S5, - input logic [7:0] S6, - input logic [7:0] S7, - input logic [7:0] S8, - input logic [7:0] S9, - output logic O -); - -logic sel0; -logic sel1; -logic sel10; -logic sel11; -logic sel12; -logic sel13; -logic sel14; -logic sel15; -logic sel16; -logic sel17; -logic sel18; -logic sel19; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -logic sel6; -logic sel7; -logic sel8; -logic sel9; -assign sel0 = (~E0) | (~S0[6]) | I0; -assign sel1 = (~E1) | (~S1[6]) | I1; -assign sel2 = (~E2) | (~S2[6]) | I2; -assign sel3 = (~E3) | (~S3[6]) | I3; -assign sel4 = (~E4) | (~S4[6]) | I4; -assign sel5 = (~E5) | (~S5[6]) | I5; -assign sel6 = (~E6) | (~S6[6]) | I6; -assign sel7 = (~E7) | (~S7[6]) | I7; -assign sel8 = (~E8) | (~S8[6]) | I8; -assign sel9 = (~E9) | (~S9[6]) | I9; -assign sel10 = (~E10) | (~S10[6]) | I10; -assign sel11 = (~E11) | (~S11[6]) | I11; -assign sel12 = (~E12) | (~S12[6]) | I12; -assign sel13 = (~E13) | (~S13[6]) | I13; -assign sel14 = (~E14) | (~S14[6]) | I14; -assign sel15 = (~E15) | (~S15[6]) | I15; -assign sel16 = (~E16) | (~S16[6]) | I16; -assign sel17 = (~E17) | (~S17[6]) | I17; -assign sel18 = (~E18) | (~S18[6]) | I18; -assign sel19 = (~E19) | (~S19[6]) | I19; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8 & sel9 & sel10 & - sel11 & sel12 & sel13 & sel14 & sel15 & sel16 & sel17 & sel18 & sel19; -endmodule // FanoutHash_1EBD0270673B29D7 - diff --git a/sam/onyx/.magma/FanoutHash_244497FCED8BEB80-kratos.sv b/sam/onyx/.magma/FanoutHash_244497FCED8BEB80-kratos.sv deleted file mode 100644 index 54a42b92..00000000 --- a/sam/onyx/.magma/FanoutHash_244497FCED8BEB80-kratos.sv +++ /dev/null @@ -1,52 +0,0 @@ -module FanoutHash_244497FCED8BEB80 ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic E6, - input logic E7, - input logic E8, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic I6, - input logic I7, - input logic I8, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - input logic [31:0] S6, - input logic [31:0] S7, - input logic [31:0] S8, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -logic sel6; -logic sel7; -logic sel8; -assign sel0 = (~E0) | (~S0[0]) | I0; -assign sel1 = (~E1) | (~S1[2]) | I1; -assign sel2 = (~E2) | (~S2[2]) | I2; -assign sel3 = (~E3) | (~S3[16]) | I3; -assign sel4 = (~E4) | (~S4[16]) | I4; -assign sel5 = (~E5) | (~S5[16]) | I5; -assign sel6 = (~E6) | (~S6[16]) | I6; -assign sel7 = (~E7) | (~S7[16]) | I7; -assign sel8 = (~E8) | (~S8[16]) | I8; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8; -endmodule // FanoutHash_244497FCED8BEB80 - diff --git a/sam/onyx/.magma/FanoutHash_245560850976C879-kratos.sv b/sam/onyx/.magma/FanoutHash_245560850976C879-kratos.sv deleted file mode 100644 index c65009f1..00000000 --- a/sam/onyx/.magma/FanoutHash_245560850976C879-kratos.sv +++ /dev/null @@ -1,52 +0,0 @@ -module FanoutHash_245560850976C879 ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic E6, - input logic E7, - input logic E8, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic I6, - input logic I7, - input logic I8, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - input logic [31:0] S6, - input logic [31:0] S7, - input logic [31:0] S8, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -logic sel6; -logic sel7; -logic sel8; -assign sel0 = (~E0) | (~S0[1]) | I0; -assign sel1 = (~E1) | (~S1[2]) | I1; -assign sel2 = (~E2) | (~S2[0]) | I2; -assign sel3 = (~E3) | (~S3[6]) | I3; -assign sel4 = (~E4) | (~S4[6]) | I4; -assign sel5 = (~E5) | (~S5[6]) | I5; -assign sel6 = (~E6) | (~S6[6]) | I6; -assign sel7 = (~E7) | (~S7[6]) | I7; -assign sel8 = (~E8) | (~S8[6]) | I8; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8; -endmodule // FanoutHash_245560850976C879 - diff --git a/sam/onyx/.magma/FanoutHash_26B6474864379B6A-kratos.sv b/sam/onyx/.magma/FanoutHash_26B6474864379B6A-kratos.sv deleted file mode 100644 index c381fb8b..00000000 --- a/sam/onyx/.magma/FanoutHash_26B6474864379B6A-kratos.sv +++ /dev/null @@ -1,42 +0,0 @@ -module FanoutHash_26B6474864379B6A ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic E6, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic I6, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - input logic [31:0] S6, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -logic sel6; -assign sel0 = (~E0) | (~S0[1]) | I0; -assign sel1 = (~E1) | (~S1[1]) | I1; -assign sel2 = (~E2) | (~S2[2]) | I2; -assign sel3 = (~E3) | (~S3[17]) | I3; -assign sel4 = (~E4) | (~S4[17]) | I4; -assign sel5 = (~E5) | (~S5[17]) | I5; -assign sel6 = (~E6) | (~S6[17]) | I6; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6; -endmodule // FanoutHash_26B6474864379B6A - diff --git a/sam/onyx/.magma/FanoutHash_276F8381CE025648-kratos.sv b/sam/onyx/.magma/FanoutHash_276F8381CE025648-kratos.sv deleted file mode 100644 index 4bc47134..00000000 --- a/sam/onyx/.magma/FanoutHash_276F8381CE025648-kratos.sv +++ /dev/null @@ -1,52 +0,0 @@ -module FanoutHash_276F8381CE025648 ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic E6, - input logic E7, - input logic E8, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic I6, - input logic I7, - input logic I8, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - input logic [31:0] S6, - input logic [31:0] S7, - input logic [31:0] S8, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -logic sel6; -logic sel7; -logic sel8; -assign sel0 = (~E0) | (~S0[0]) | I0; -assign sel1 = (~E1) | (~S1[0]) | I1; -assign sel2 = (~E2) | (~S2[2]) | I2; -assign sel3 = (~E3) | (~S3[14]) | I3; -assign sel4 = (~E4) | (~S4[14]) | I4; -assign sel5 = (~E5) | (~S5[14]) | I5; -assign sel6 = (~E6) | (~S6[14]) | I6; -assign sel7 = (~E7) | (~S7[14]) | I7; -assign sel8 = (~E8) | (~S8[14]) | I8; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8; -endmodule // FanoutHash_276F8381CE025648 - diff --git a/sam/onyx/.magma/FanoutHash_278348DB702230E6-kratos.sv b/sam/onyx/.magma/FanoutHash_278348DB702230E6-kratos.sv deleted file mode 100644 index ca9c496e..00000000 --- a/sam/onyx/.magma/FanoutHash_278348DB702230E6-kratos.sv +++ /dev/null @@ -1,37 +0,0 @@ -module FanoutHash_278348DB702230E6 ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -assign sel0 = (~E0) | (~S0[0]) | I0; -assign sel1 = (~E1) | (~S1[0]) | I1; -assign sel2 = (~E2) | (~S2[2]) | I2; -assign sel3 = (~E3) | (~S3[10]) | I3; -assign sel4 = (~E4) | (~S4[10]) | I4; -assign sel5 = (~E5) | (~S5[10]) | I5; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5; -endmodule // FanoutHash_278348DB702230E6 - diff --git a/sam/onyx/.magma/FanoutHash_2785CE916183C5C-kratos.sv b/sam/onyx/.magma/FanoutHash_2785CE916183C5C-kratos.sv deleted file mode 100644 index 5412996e..00000000 --- a/sam/onyx/.magma/FanoutHash_2785CE916183C5C-kratos.sv +++ /dev/null @@ -1,42 +0,0 @@ -module FanoutHash_2785CE916183C5C ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic E6, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic I6, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - input logic [31:0] S6, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -logic sel6; -assign sel0 = (~E0) | (~S0[0]) | I0; -assign sel1 = (~E1) | (~S1[2]) | I1; -assign sel2 = (~E2) | (~S2[1]) | I2; -assign sel3 = (~E3) | (~S3[1]) | I3; -assign sel4 = (~E4) | (~S4[1]) | I4; -assign sel5 = (~E5) | (~S5[1]) | I5; -assign sel6 = (~E6) | (~S6[1]) | I6; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6; -endmodule // FanoutHash_2785CE916183C5C - diff --git a/sam/onyx/.magma/FanoutHash_28125A548B305607-kratos.sv b/sam/onyx/.magma/FanoutHash_28125A548B305607-kratos.sv deleted file mode 100644 index 3460e627..00000000 --- a/sam/onyx/.magma/FanoutHash_28125A548B305607-kratos.sv +++ /dev/null @@ -1,42 +0,0 @@ -module FanoutHash_28125A548B305607 ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic E6, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic I6, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - input logic [31:0] S6, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -logic sel6; -assign sel0 = (~E0) | (~S0[2]) | I0; -assign sel1 = (~E1) | (~S1[1]) | I1; -assign sel2 = (~E2) | (~S2[1]) | I2; -assign sel3 = (~E3) | (~S3[9]) | I3; -assign sel4 = (~E4) | (~S4[9]) | I4; -assign sel5 = (~E5) | (~S5[9]) | I5; -assign sel6 = (~E6) | (~S6[9]) | I6; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6; -endmodule // FanoutHash_28125A548B305607 - diff --git a/sam/onyx/.magma/FanoutHash_2CE3041FDDDDEC1A-kratos.sv b/sam/onyx/.magma/FanoutHash_2CE3041FDDDDEC1A-kratos.sv deleted file mode 100644 index 6566169e..00000000 --- a/sam/onyx/.magma/FanoutHash_2CE3041FDDDDEC1A-kratos.sv +++ /dev/null @@ -1,52 +0,0 @@ -module FanoutHash_2CE3041FDDDDEC1A ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic E6, - input logic E7, - input logic E8, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic I6, - input logic I7, - input logic I8, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - input logic [31:0] S6, - input logic [31:0] S7, - input logic [31:0] S8, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -logic sel6; -logic sel7; -logic sel8; -assign sel0 = (~E0) | (~S0[2]) | I0; -assign sel1 = (~E1) | (~S1[1]) | I1; -assign sel2 = (~E2) | (~S2[1]) | I2; -assign sel3 = (~E3) | (~S3[9]) | I3; -assign sel4 = (~E4) | (~S4[9]) | I4; -assign sel5 = (~E5) | (~S5[9]) | I5; -assign sel6 = (~E6) | (~S6[9]) | I6; -assign sel7 = (~E7) | (~S7[9]) | I7; -assign sel8 = (~E8) | (~S8[9]) | I8; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8; -endmodule // FanoutHash_2CE3041FDDDDEC1A - diff --git a/sam/onyx/.magma/FanoutHash_2F92967E9F56D548-kratos.sv b/sam/onyx/.magma/FanoutHash_2F92967E9F56D548-kratos.sv deleted file mode 100644 index c5fbd2dd..00000000 --- a/sam/onyx/.magma/FanoutHash_2F92967E9F56D548-kratos.sv +++ /dev/null @@ -1,52 +0,0 @@ -module FanoutHash_2F92967E9F56D548 ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic E6, - input logic E7, - input logic E8, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic I6, - input logic I7, - input logic I8, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - input logic [31:0] S6, - input logic [31:0] S7, - input logic [31:0] S8, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -logic sel6; -logic sel7; -logic sel8; -assign sel0 = (~E0) | (~S0[1]) | I0; -assign sel1 = (~E1) | (~S1[1]) | I1; -assign sel2 = (~E2) | (~S2[1]) | I2; -assign sel3 = (~E3) | (~S3[5]) | I3; -assign sel4 = (~E4) | (~S4[5]) | I4; -assign sel5 = (~E5) | (~S5[5]) | I5; -assign sel6 = (~E6) | (~S6[5]) | I6; -assign sel7 = (~E7) | (~S7[5]) | I7; -assign sel8 = (~E8) | (~S8[5]) | I8; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8; -endmodule // FanoutHash_2F92967E9F56D548 - diff --git a/sam/onyx/.magma/FanoutHash_302974B49BE3F0C4-kratos.sv b/sam/onyx/.magma/FanoutHash_302974B49BE3F0C4-kratos.sv deleted file mode 100644 index db6670d6..00000000 --- a/sam/onyx/.magma/FanoutHash_302974B49BE3F0C4-kratos.sv +++ /dev/null @@ -1,42 +0,0 @@ -module FanoutHash_302974B49BE3F0C4 ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic E6, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic I6, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - input logic [31:0] S6, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -logic sel6; -assign sel0 = (~E0) | (~S0[2]) | I0; -assign sel1 = (~E1) | (~S1[0]) | I1; -assign sel2 = (~E2) | (~S2[1]) | I2; -assign sel3 = (~E3) | (~S3[2]) | I3; -assign sel4 = (~E4) | (~S4[2]) | I4; -assign sel5 = (~E5) | (~S5[2]) | I5; -assign sel6 = (~E6) | (~S6[2]) | I6; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6; -endmodule // FanoutHash_302974B49BE3F0C4 - diff --git a/sam/onyx/.magma/FanoutHash_308BAC760F688049-kratos.sv b/sam/onyx/.magma/FanoutHash_308BAC760F688049-kratos.sv deleted file mode 100644 index 6a58af8c..00000000 --- a/sam/onyx/.magma/FanoutHash_308BAC760F688049-kratos.sv +++ /dev/null @@ -1,37 +0,0 @@ -module FanoutHash_308BAC760F688049 ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -assign sel0 = (~E0) | (~S0[2]) | I0; -assign sel1 = (~E1) | (~S1[1]) | I1; -assign sel2 = (~E2) | (~S2[1]) | I2; -assign sel3 = (~E3) | (~S3[9]) | I3; -assign sel4 = (~E4) | (~S4[9]) | I4; -assign sel5 = (~E5) | (~S5[9]) | I5; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5; -endmodule // FanoutHash_308BAC760F688049 - diff --git a/sam/onyx/.magma/FanoutHash_31555E0CDC460B97-kratos.sv b/sam/onyx/.magma/FanoutHash_31555E0CDC460B97-kratos.sv deleted file mode 100644 index 2dc5ed1f..00000000 --- a/sam/onyx/.magma/FanoutHash_31555E0CDC460B97-kratos.sv +++ /dev/null @@ -1,37 +0,0 @@ -module FanoutHash_31555E0CDC460B97 ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -assign sel0 = (~E0) | (~S0[0]) | I0; -assign sel1 = (~E1) | (~S1[1]) | I1; -assign sel2 = (~E2) | (~S2[0]) | I2; -assign sel3 = (~E3) | (~S3[4]) | I3; -assign sel4 = (~E4) | (~S4[4]) | I4; -assign sel5 = (~E5) | (~S5[4]) | I5; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5; -endmodule // FanoutHash_31555E0CDC460B97 - diff --git a/sam/onyx/.magma/FanoutHash_31AE65CCDD94603-kratos.sv b/sam/onyx/.magma/FanoutHash_31AE65CCDD94603-kratos.sv deleted file mode 100644 index a03e54b5..00000000 --- a/sam/onyx/.magma/FanoutHash_31AE65CCDD94603-kratos.sv +++ /dev/null @@ -1,42 +0,0 @@ -module FanoutHash_31AE65CCDD94603 ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic E6, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic I6, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - input logic [31:0] S6, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -logic sel6; -assign sel0 = (~E0) | (~S0[2]) | I0; -assign sel1 = (~E1) | (~S1[2]) | I1; -assign sel2 = (~E2) | (~S2[2]) | I2; -assign sel3 = (~E3) | (~S3[15]) | I3; -assign sel4 = (~E4) | (~S4[15]) | I4; -assign sel5 = (~E5) | (~S5[15]) | I5; -assign sel6 = (~E6) | (~S6[15]) | I6; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6; -endmodule // FanoutHash_31AE65CCDD94603 - diff --git a/sam/onyx/.magma/FanoutHash_37B926A0CDF82FCC-kratos.sv b/sam/onyx/.magma/FanoutHash_37B926A0CDF82FCC-kratos.sv deleted file mode 100644 index 08be469a..00000000 --- a/sam/onyx/.magma/FanoutHash_37B926A0CDF82FCC-kratos.sv +++ /dev/null @@ -1,37 +0,0 @@ -module FanoutHash_37B926A0CDF82FCC ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -assign sel0 = (~E0) | (~S0[0]) | I0; -assign sel1 = (~E1) | (~S1[2]) | I1; -assign sel2 = (~E2) | (~S2[2]) | I2; -assign sel3 = (~E3) | (~S3[16]) | I3; -assign sel4 = (~E4) | (~S4[16]) | I4; -assign sel5 = (~E5) | (~S5[16]) | I5; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5; -endmodule // FanoutHash_37B926A0CDF82FCC - diff --git a/sam/onyx/.magma/FanoutHash_37E9FE88073C5BAC-kratos.sv b/sam/onyx/.magma/FanoutHash_37E9FE88073C5BAC-kratos.sv deleted file mode 100644 index a3be7859..00000000 --- a/sam/onyx/.magma/FanoutHash_37E9FE88073C5BAC-kratos.sv +++ /dev/null @@ -1,52 +0,0 @@ -module FanoutHash_37E9FE88073C5BAC ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic E6, - input logic E7, - input logic E8, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic I6, - input logic I7, - input logic I8, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - input logic [31:0] S6, - input logic [31:0] S7, - input logic [31:0] S8, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -logic sel6; -logic sel7; -logic sel8; -assign sel0 = (~E0) | (~S0[0]) | I0; -assign sel1 = (~E1) | (~S1[1]) | I1; -assign sel2 = (~E2) | (~S2[0]) | I2; -assign sel3 = (~E3) | (~S3[4]) | I3; -assign sel4 = (~E4) | (~S4[4]) | I4; -assign sel5 = (~E5) | (~S5[4]) | I5; -assign sel6 = (~E6) | (~S6[4]) | I6; -assign sel7 = (~E7) | (~S7[4]) | I7; -assign sel8 = (~E8) | (~S8[4]) | I8; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8; -endmodule // FanoutHash_37E9FE88073C5BAC - diff --git a/sam/onyx/.magma/FanoutHash_3A0064632A577CF5-kratos.sv b/sam/onyx/.magma/FanoutHash_3A0064632A577CF5-kratos.sv deleted file mode 100644 index 6437415b..00000000 --- a/sam/onyx/.magma/FanoutHash_3A0064632A577CF5-kratos.sv +++ /dev/null @@ -1,37 +0,0 @@ -module FanoutHash_3A0064632A577CF5 ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -assign sel0 = (~E0) | (~S0[0]) | I0; -assign sel1 = (~E1) | (~S1[0]) | I1; -assign sel2 = (~E2) | (~S2[0]) | I2; -assign sel3 = (~E3) | (~S3[3]) | I3; -assign sel4 = (~E4) | (~S4[3]) | I4; -assign sel5 = (~E5) | (~S5[3]) | I5; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5; -endmodule // FanoutHash_3A0064632A577CF5 - diff --git a/sam/onyx/.magma/FanoutHash_3A6A5822E84DCC71-kratos.sv b/sam/onyx/.magma/FanoutHash_3A6A5822E84DCC71-kratos.sv deleted file mode 100644 index 5e3a3b41..00000000 --- a/sam/onyx/.magma/FanoutHash_3A6A5822E84DCC71-kratos.sv +++ /dev/null @@ -1,52 +0,0 @@ -module FanoutHash_3A6A5822E84DCC71 ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic E6, - input logic E7, - input logic E8, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic I6, - input logic I7, - input logic I8, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - input logic [31:0] S6, - input logic [31:0] S7, - input logic [31:0] S8, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -logic sel6; -logic sel7; -logic sel8; -assign sel0 = (~E0) | (~S0[0]) | I0; -assign sel1 = (~E1) | (~S1[0]) | I1; -assign sel2 = (~E2) | (~S2[1]) | I2; -assign sel3 = (~E3) | (~S3[0]) | I3; -assign sel4 = (~E4) | (~S4[0]) | I4; -assign sel5 = (~E5) | (~S5[0]) | I5; -assign sel6 = (~E6) | (~S6[0]) | I6; -assign sel7 = (~E7) | (~S7[0]) | I7; -assign sel8 = (~E8) | (~S8[0]) | I8; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8; -endmodule // FanoutHash_3A6A5822E84DCC71 - diff --git a/sam/onyx/.magma/FanoutHash_3B67229CB02928BA-kratos.sv b/sam/onyx/.magma/FanoutHash_3B67229CB02928BA-kratos.sv deleted file mode 100644 index 73c47132..00000000 --- a/sam/onyx/.magma/FanoutHash_3B67229CB02928BA-kratos.sv +++ /dev/null @@ -1,42 +0,0 @@ -module FanoutHash_3B67229CB02928BA ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic E6, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic I6, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - input logic [31:0] S6, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -logic sel6; -assign sel0 = (~E0) | (~S0[1]) | I0; -assign sel1 = (~E1) | (~S1[1]) | I1; -assign sel2 = (~E2) | (~S2[0]) | I2; -assign sel3 = (~E3) | (~S3[8]) | I3; -assign sel4 = (~E4) | (~S4[8]) | I4; -assign sel5 = (~E5) | (~S5[8]) | I5; -assign sel6 = (~E6) | (~S6[8]) | I6; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6; -endmodule // FanoutHash_3B67229CB02928BA - diff --git a/sam/onyx/.magma/FanoutHash_3E05574A9CE9CA8A-kratos.sv b/sam/onyx/.magma/FanoutHash_3E05574A9CE9CA8A-kratos.sv deleted file mode 100644 index 94a70ac6..00000000 --- a/sam/onyx/.magma/FanoutHash_3E05574A9CE9CA8A-kratos.sv +++ /dev/null @@ -1,52 +0,0 @@ -module FanoutHash_3E05574A9CE9CA8A ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic E6, - input logic E7, - input logic E8, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic I6, - input logic I7, - input logic I8, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - input logic [31:0] S6, - input logic [31:0] S7, - input logic [31:0] S8, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -logic sel6; -logic sel7; -logic sel8; -assign sel0 = (~E0) | (~S0[0]) | I0; -assign sel1 = (~E1) | (~S1[2]) | I1; -assign sel2 = (~E2) | (~S2[1]) | I2; -assign sel3 = (~E3) | (~S3[1]) | I3; -assign sel4 = (~E4) | (~S4[1]) | I4; -assign sel5 = (~E5) | (~S5[1]) | I5; -assign sel6 = (~E6) | (~S6[1]) | I6; -assign sel7 = (~E7) | (~S7[1]) | I7; -assign sel8 = (~E8) | (~S8[1]) | I8; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8; -endmodule // FanoutHash_3E05574A9CE9CA8A - diff --git a/sam/onyx/.magma/FanoutHash_41D739158D58E184-kratos.sv b/sam/onyx/.magma/FanoutHash_41D739158D58E184-kratos.sv deleted file mode 100644 index cdbbf50c..00000000 --- a/sam/onyx/.magma/FanoutHash_41D739158D58E184-kratos.sv +++ /dev/null @@ -1,52 +0,0 @@ -module FanoutHash_41D739158D58E184 ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic E6, - input logic E7, - input logic E8, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic I6, - input logic I7, - input logic I8, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - input logic [31:0] S6, - input logic [31:0] S7, - input logic [31:0] S8, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -logic sel6; -logic sel7; -logic sel8; -assign sel0 = (~E0) | (~S0[2]) | I0; -assign sel1 = (~E1) | (~S1[2]) | I1; -assign sel2 = (~E2) | (~S2[2]) | I2; -assign sel3 = (~E3) | (~S3[15]) | I3; -assign sel4 = (~E4) | (~S4[15]) | I4; -assign sel5 = (~E5) | (~S5[15]) | I5; -assign sel6 = (~E6) | (~S6[15]) | I6; -assign sel7 = (~E7) | (~S7[15]) | I7; -assign sel8 = (~E8) | (~S8[15]) | I8; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8; -endmodule // FanoutHash_41D739158D58E184 - diff --git a/sam/onyx/.magma/FanoutHash_43D5C80ABD816837-kratos.sv b/sam/onyx/.magma/FanoutHash_43D5C80ABD816837-kratos.sv deleted file mode 100644 index 998358be..00000000 --- a/sam/onyx/.magma/FanoutHash_43D5C80ABD816837-kratos.sv +++ /dev/null @@ -1,42 +0,0 @@ -module FanoutHash_43D5C80ABD816837 ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic E6, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic I6, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - input logic [31:0] S6, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -logic sel6; -assign sel0 = (~E0) | (~S0[0]) | I0; -assign sel1 = (~E1) | (~S1[0]) | I1; -assign sel2 = (~E2) | (~S2[2]) | I2; -assign sel3 = (~E3) | (~S3[14]) | I3; -assign sel4 = (~E4) | (~S4[14]) | I4; -assign sel5 = (~E5) | (~S5[14]) | I5; -assign sel6 = (~E6) | (~S6[14]) | I6; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6; -endmodule // FanoutHash_43D5C80ABD816837 - diff --git a/sam/onyx/.magma/FanoutHash_466EB88CFD0CAD7B-kratos.sv b/sam/onyx/.magma/FanoutHash_466EB88CFD0CAD7B-kratos.sv deleted file mode 100644 index 3776548c..00000000 --- a/sam/onyx/.magma/FanoutHash_466EB88CFD0CAD7B-kratos.sv +++ /dev/null @@ -1,42 +0,0 @@ -module FanoutHash_466EB88CFD0CAD7B ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic E6, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic I6, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - input logic [31:0] S6, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -logic sel6; -assign sel0 = (~E0) | (~S0[1]) | I0; -assign sel1 = (~E1) | (~S1[1]) | I1; -assign sel2 = (~E2) | (~S2[1]) | I2; -assign sel3 = (~E3) | (~S3[5]) | I3; -assign sel4 = (~E4) | (~S4[5]) | I4; -assign sel5 = (~E5) | (~S5[5]) | I5; -assign sel6 = (~E6) | (~S6[5]) | I6; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6; -endmodule // FanoutHash_466EB88CFD0CAD7B - diff --git a/sam/onyx/.magma/FanoutHash_4678C6877F96240E-kratos.sv b/sam/onyx/.magma/FanoutHash_4678C6877F96240E-kratos.sv deleted file mode 100644 index 17a67836..00000000 --- a/sam/onyx/.magma/FanoutHash_4678C6877F96240E-kratos.sv +++ /dev/null @@ -1,37 +0,0 @@ -module FanoutHash_4678C6877F96240E ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -assign sel0 = (~E0) | (~S0[2]) | I0; -assign sel1 = (~E1) | (~S1[0]) | I1; -assign sel2 = (~E2) | (~S2[1]) | I2; -assign sel3 = (~E3) | (~S3[2]) | I3; -assign sel4 = (~E4) | (~S4[2]) | I4; -assign sel5 = (~E5) | (~S5[2]) | I5; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5; -endmodule // FanoutHash_4678C6877F96240E - diff --git a/sam/onyx/.magma/FanoutHash_47712AAC902ADA2-kratos.sv b/sam/onyx/.magma/FanoutHash_47712AAC902ADA2-kratos.sv deleted file mode 100644 index 93b6e8dd..00000000 --- a/sam/onyx/.magma/FanoutHash_47712AAC902ADA2-kratos.sv +++ /dev/null @@ -1,42 +0,0 @@ -module FanoutHash_47712AAC902ADA2 ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic E6, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic I6, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - input logic [31:0] S6, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -logic sel6; -assign sel0 = (~E0) | (~S0[0]) | I0; -assign sel1 = (~E1) | (~S1[0]) | I1; -assign sel2 = (~E2) | (~S2[1]) | I2; -assign sel3 = (~E3) | (~S3[0]) | I3; -assign sel4 = (~E4) | (~S4[0]) | I4; -assign sel5 = (~E5) | (~S5[0]) | I5; -assign sel6 = (~E6) | (~S6[0]) | I6; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6; -endmodule // FanoutHash_47712AAC902ADA2 - diff --git a/sam/onyx/.magma/FanoutHash_4A74B16B611BA7E4-kratos.sv b/sam/onyx/.magma/FanoutHash_4A74B16B611BA7E4-kratos.sv deleted file mode 100644 index f5a2c41c..00000000 --- a/sam/onyx/.magma/FanoutHash_4A74B16B611BA7E4-kratos.sv +++ /dev/null @@ -1,52 +0,0 @@ -module FanoutHash_4A74B16B611BA7E4 ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic E6, - input logic E7, - input logic E8, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic I6, - input logic I7, - input logic I8, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - input logic [31:0] S6, - input logic [31:0] S7, - input logic [31:0] S8, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -logic sel6; -logic sel7; -logic sel8; -assign sel0 = (~E0) | (~S0[0]) | I0; -assign sel1 = (~E1) | (~S1[2]) | I1; -assign sel2 = (~E2) | (~S2[2]) | I2; -assign sel3 = (~E3) | (~S3[11]) | I3; -assign sel4 = (~E4) | (~S4[11]) | I4; -assign sel5 = (~E5) | (~S5[11]) | I5; -assign sel6 = (~E6) | (~S6[11]) | I6; -assign sel7 = (~E7) | (~S7[11]) | I7; -assign sel8 = (~E8) | (~S8[11]) | I8; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8; -endmodule // FanoutHash_4A74B16B611BA7E4 - diff --git a/sam/onyx/.magma/FanoutHash_4F83851A40824F89-kratos.sv b/sam/onyx/.magma/FanoutHash_4F83851A40824F89-kratos.sv deleted file mode 100644 index 325464d3..00000000 --- a/sam/onyx/.magma/FanoutHash_4F83851A40824F89-kratos.sv +++ /dev/null @@ -1,42 +0,0 @@ -module FanoutHash_4F83851A40824F89 ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic E6, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic I6, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - input logic [31:0] S6, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -logic sel6; -assign sel0 = (~E0) | (~S0[1]) | I0; -assign sel1 = (~E1) | (~S1[2]) | I1; -assign sel2 = (~E2) | (~S2[0]) | I2; -assign sel3 = (~E3) | (~S3[6]) | I3; -assign sel4 = (~E4) | (~S4[6]) | I4; -assign sel5 = (~E5) | (~S5[6]) | I5; -assign sel6 = (~E6) | (~S6[6]) | I6; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6; -endmodule // FanoutHash_4F83851A40824F89 - diff --git a/sam/onyx/.magma/FanoutHash_4FADDC8F90390680-kratos.sv b/sam/onyx/.magma/FanoutHash_4FADDC8F90390680-kratos.sv deleted file mode 100644 index 1bc086bf..00000000 --- a/sam/onyx/.magma/FanoutHash_4FADDC8F90390680-kratos.sv +++ /dev/null @@ -1,42 +0,0 @@ -module FanoutHash_4FADDC8F90390680 ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic E6, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic I6, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - input logic [31:0] S6, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -logic sel6; -assign sel0 = (~E0) | (~S0[0]) | I0; -assign sel1 = (~E1) | (~S1[1]) | I1; -assign sel2 = (~E2) | (~S2[0]) | I2; -assign sel3 = (~E3) | (~S3[4]) | I3; -assign sel4 = (~E4) | (~S4[4]) | I4; -assign sel5 = (~E5) | (~S5[4]) | I5; -assign sel6 = (~E6) | (~S6[4]) | I6; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6; -endmodule // FanoutHash_4FADDC8F90390680 - diff --git a/sam/onyx/.magma/FanoutHash_4FF010386DB0B737-kratos.sv b/sam/onyx/.magma/FanoutHash_4FF010386DB0B737-kratos.sv deleted file mode 100644 index 73d09815..00000000 --- a/sam/onyx/.magma/FanoutHash_4FF010386DB0B737-kratos.sv +++ /dev/null @@ -1,37 +0,0 @@ -module FanoutHash_4FF010386DB0B737 ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -assign sel0 = (~E0) | (~S0[1]) | I0; -assign sel1 = (~E1) | (~S1[1]) | I1; -assign sel2 = (~E2) | (~S2[1]) | I2; -assign sel3 = (~E3) | (~S3[5]) | I3; -assign sel4 = (~E4) | (~S4[5]) | I4; -assign sel5 = (~E5) | (~S5[5]) | I5; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5; -endmodule // FanoutHash_4FF010386DB0B737 - diff --git a/sam/onyx/.magma/FanoutHash_55169EB19E10AA09-kratos.sv b/sam/onyx/.magma/FanoutHash_55169EB19E10AA09-kratos.sv deleted file mode 100644 index df5e881a..00000000 --- a/sam/onyx/.magma/FanoutHash_55169EB19E10AA09-kratos.sv +++ /dev/null @@ -1,52 +0,0 @@ -module FanoutHash_55169EB19E10AA09 ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic E6, - input logic E7, - input logic E8, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic I6, - input logic I7, - input logic I8, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - input logic [31:0] S6, - input logic [31:0] S7, - input logic [31:0] S8, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -logic sel6; -logic sel7; -logic sel8; -assign sel0 = (~E0) | (~S0[1]) | I0; -assign sel1 = (~E1) | (~S1[1]) | I1; -assign sel2 = (~E2) | (~S2[2]) | I2; -assign sel3 = (~E3) | (~S3[18]) | I3; -assign sel4 = (~E4) | (~S4[18]) | I4; -assign sel5 = (~E5) | (~S5[18]) | I5; -assign sel6 = (~E6) | (~S6[18]) | I6; -assign sel7 = (~E7) | (~S7[18]) | I7; -assign sel8 = (~E8) | (~S8[18]) | I8; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8; -endmodule // FanoutHash_55169EB19E10AA09 - diff --git a/sam/onyx/.magma/FanoutHash_55B00FA90A0098BB-kratos.sv b/sam/onyx/.magma/FanoutHash_55B00FA90A0098BB-kratos.sv deleted file mode 100644 index 21ec5a6f..00000000 --- a/sam/onyx/.magma/FanoutHash_55B00FA90A0098BB-kratos.sv +++ /dev/null @@ -1,52 +0,0 @@ -module FanoutHash_55B00FA90A0098BB ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic E6, - input logic E7, - input logic E8, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic I6, - input logic I7, - input logic I8, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - input logic [31:0] S6, - input logic [31:0] S7, - input logic [31:0] S8, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -logic sel6; -logic sel7; -logic sel8; -assign sel0 = (~E0) | (~S0[2]) | I0; -assign sel1 = (~E1) | (~S1[0]) | I1; -assign sel2 = (~E2) | (~S2[1]) | I2; -assign sel3 = (~E3) | (~S3[2]) | I3; -assign sel4 = (~E4) | (~S4[2]) | I4; -assign sel5 = (~E5) | (~S5[2]) | I5; -assign sel6 = (~E6) | (~S6[2]) | I6; -assign sel7 = (~E7) | (~S7[2]) | I7; -assign sel8 = (~E8) | (~S8[2]) | I8; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8; -endmodule // FanoutHash_55B00FA90A0098BB - diff --git a/sam/onyx/.magma/FanoutHash_59B7E37DAE2221E3-kratos.sv b/sam/onyx/.magma/FanoutHash_59B7E37DAE2221E3-kratos.sv deleted file mode 100644 index 155886cf..00000000 --- a/sam/onyx/.magma/FanoutHash_59B7E37DAE2221E3-kratos.sv +++ /dev/null @@ -1,52 +0,0 @@ -module FanoutHash_59B7E37DAE2221E3 ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic E6, - input logic E7, - input logic E8, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic I6, - input logic I7, - input logic I8, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - input logic [31:0] S6, - input logic [31:0] S7, - input logic [31:0] S8, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -logic sel6; -logic sel7; -logic sel8; -assign sel0 = (~E0) | (~S0[1]) | I0; -assign sel1 = (~E1) | (~S1[2]) | I1; -assign sel2 = (~E2) | (~S2[1]) | I2; -assign sel3 = (~E3) | (~S3[13]) | I3; -assign sel4 = (~E4) | (~S4[13]) | I4; -assign sel5 = (~E5) | (~S5[13]) | I5; -assign sel6 = (~E6) | (~S6[13]) | I6; -assign sel7 = (~E7) | (~S7[13]) | I7; -assign sel8 = (~E8) | (~S8[13]) | I8; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8; -endmodule // FanoutHash_59B7E37DAE2221E3 - diff --git a/sam/onyx/.magma/FanoutHash_5CD8077D054B887B-kratos.sv b/sam/onyx/.magma/FanoutHash_5CD8077D054B887B-kratos.sv deleted file mode 100644 index c0c73ff4..00000000 --- a/sam/onyx/.magma/FanoutHash_5CD8077D054B887B-kratos.sv +++ /dev/null @@ -1,52 +0,0 @@ -module FanoutHash_5CD8077D054B887B ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic E6, - input logic E7, - input logic E8, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic I6, - input logic I7, - input logic I8, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - input logic [31:0] S6, - input logic [31:0] S7, - input logic [31:0] S8, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -logic sel6; -logic sel7; -logic sel8; -assign sel0 = (~E0) | (~S0[0]) | I0; -assign sel1 = (~E1) | (~S1[0]) | I1; -assign sel2 = (~E2) | (~S2[2]) | I2; -assign sel3 = (~E3) | (~S3[10]) | I3; -assign sel4 = (~E4) | (~S4[10]) | I4; -assign sel5 = (~E5) | (~S5[10]) | I5; -assign sel6 = (~E6) | (~S6[10]) | I6; -assign sel7 = (~E7) | (~S7[10]) | I7; -assign sel8 = (~E8) | (~S8[10]) | I8; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8; -endmodule // FanoutHash_5CD8077D054B887B - diff --git a/sam/onyx/.magma/FanoutHash_5D7AEC1255CDC1CC-kratos.sv b/sam/onyx/.magma/FanoutHash_5D7AEC1255CDC1CC-kratos.sv deleted file mode 100644 index f8d9f2d3..00000000 --- a/sam/onyx/.magma/FanoutHash_5D7AEC1255CDC1CC-kratos.sv +++ /dev/null @@ -1,42 +0,0 @@ -module FanoutHash_5D7AEC1255CDC1CC ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic E6, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic I6, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - input logic [31:0] S6, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -logic sel6; -assign sel0 = (~E0) | (~S0[1]) | I0; -assign sel1 = (~E1) | (~S1[1]) | I1; -assign sel2 = (~E2) | (~S2[2]) | I2; -assign sel3 = (~E3) | (~S3[18]) | I3; -assign sel4 = (~E4) | (~S4[18]) | I4; -assign sel5 = (~E5) | (~S5[18]) | I5; -assign sel6 = (~E6) | (~S6[18]) | I6; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6; -endmodule // FanoutHash_5D7AEC1255CDC1CC - diff --git a/sam/onyx/.magma/FanoutHash_5DE101F5B6936D07-kratos.sv b/sam/onyx/.magma/FanoutHash_5DE101F5B6936D07-kratos.sv deleted file mode 100644 index 1763b796..00000000 --- a/sam/onyx/.magma/FanoutHash_5DE101F5B6936D07-kratos.sv +++ /dev/null @@ -1,37 +0,0 @@ -module FanoutHash_5DE101F5B6936D07 ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -assign sel0 = (~E0) | (~S0[0]) | I0; -assign sel1 = (~E1) | (~S1[0]) | I1; -assign sel2 = (~E2) | (~S2[1]) | I2; -assign sel3 = (~E3) | (~S3[12]) | I3; -assign sel4 = (~E4) | (~S4[12]) | I4; -assign sel5 = (~E5) | (~S5[12]) | I5; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5; -endmodule // FanoutHash_5DE101F5B6936D07 - diff --git a/sam/onyx/.magma/FanoutHash_6211982AB4467DB3-kratos.sv b/sam/onyx/.magma/FanoutHash_6211982AB4467DB3-kratos.sv deleted file mode 100644 index 136463d9..00000000 --- a/sam/onyx/.magma/FanoutHash_6211982AB4467DB3-kratos.sv +++ /dev/null @@ -1,119 +0,0 @@ -module FanoutHash_6211982AB4467DB3 ( - input logic E0, - input logic E1, - input logic E10, - input logic E11, - input logic E12, - input logic E13, - input logic E14, - input logic E15, - input logic E16, - input logic E17, - input logic E18, - input logic E19, - input logic E2, - input logic E20, - input logic E21, - input logic E3, - input logic E4, - input logic E5, - input logic E6, - input logic E7, - input logic E8, - input logic E9, - input logic I0, - input logic I1, - input logic I10, - input logic I11, - input logic I12, - input logic I13, - input logic I14, - input logic I15, - input logic I16, - input logic I17, - input logic I18, - input logic I19, - input logic I2, - input logic I20, - input logic I21, - input logic I3, - input logic I4, - input logic I5, - input logic I6, - input logic I7, - input logic I8, - input logic I9, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S10, - input logic [7:0] S11, - input logic [7:0] S12, - input logic [7:0] S13, - input logic [7:0] S14, - input logic [7:0] S15, - input logic [7:0] S16, - input logic [7:0] S17, - input logic [7:0] S18, - input logic [7:0] S19, - input logic [7:0] S2, - input logic [31:0] S20, - input logic [31:0] S21, - input logic [7:0] S3, - input logic [7:0] S4, - input logic [7:0] S5, - input logic [7:0] S6, - input logic [7:0] S7, - input logic [7:0] S8, - input logic [7:0] S9, - output logic O -); - -logic sel0; -logic sel1; -logic sel10; -logic sel11; -logic sel12; -logic sel13; -logic sel14; -logic sel15; -logic sel16; -logic sel17; -logic sel18; -logic sel19; -logic sel2; -logic sel20; -logic sel21; -logic sel3; -logic sel4; -logic sel5; -logic sel6; -logic sel7; -logic sel8; -logic sel9; -assign sel0 = (~E0) | (~S0[4]) | I0; -assign sel1 = (~E1) | (~S1[4]) | I1; -assign sel2 = (~E2) | (~S2[4]) | I2; -assign sel3 = (~E3) | (~S3[4]) | I3; -assign sel4 = (~E4) | (~S4[4]) | I4; -assign sel5 = (~E5) | (~S5[4]) | I5; -assign sel6 = (~E6) | (~S6[4]) | I6; -assign sel7 = (~E7) | (~S7[4]) | I7; -assign sel8 = (~E8) | (~S8[4]) | I8; -assign sel9 = (~E9) | (~S9[4]) | I9; -assign sel10 = (~E10) | (~S10[4]) | I10; -assign sel11 = (~E11) | (~S11[4]) | I11; -assign sel12 = (~E12) | (~S12[4]) | I12; -assign sel13 = (~E13) | (~S13[4]) | I13; -assign sel14 = (~E14) | (~S14[4]) | I14; -assign sel15 = (~E15) | (~S15[4]) | I15; -assign sel16 = (~E16) | (~S16[4]) | I16; -assign sel17 = (~E17) | (~S17[4]) | I17; -assign sel18 = (~E18) | (~S18[4]) | I18; -assign sel19 = (~E19) | (~S19[4]) | I19; -assign sel20 = (~E20) | (~S20[20]) | I20; -assign sel21 = (~E21) | (~S21[20]) | I21; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8 & sel9 & sel10 & - sel11 & sel12 & sel13 & sel14 & sel15 & sel16 & sel17 & sel18 & sel19 & sel20 & - sel21; -endmodule // FanoutHash_6211982AB4467DB3 - diff --git a/sam/onyx/.magma/FanoutHash_653384C8EF52B5E3-kratos.sv b/sam/onyx/.magma/FanoutHash_653384C8EF52B5E3-kratos.sv deleted file mode 100644 index af3a47a2..00000000 --- a/sam/onyx/.magma/FanoutHash_653384C8EF52B5E3-kratos.sv +++ /dev/null @@ -1,52 +0,0 @@ -module FanoutHash_653384C8EF52B5E3 ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic E6, - input logic E7, - input logic E8, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic I6, - input logic I7, - input logic I8, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - input logic [31:0] S6, - input logic [31:0] S7, - input logic [31:0] S8, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -logic sel6; -logic sel7; -logic sel8; -assign sel0 = (~E0) | (~S0[0]) | I0; -assign sel1 = (~E1) | (~S1[2]) | I1; -assign sel2 = (~E2) | (~S2[1]) | I2; -assign sel3 = (~E3) | (~S3[7]) | I3; -assign sel4 = (~E4) | (~S4[7]) | I4; -assign sel5 = (~E5) | (~S5[7]) | I5; -assign sel6 = (~E6) | (~S6[7]) | I6; -assign sel7 = (~E7) | (~S7[7]) | I7; -assign sel8 = (~E8) | (~S8[7]) | I8; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8; -endmodule // FanoutHash_653384C8EF52B5E3 - diff --git a/sam/onyx/.magma/FanoutHash_65A468071775C7BB-kratos.sv b/sam/onyx/.magma/FanoutHash_65A468071775C7BB-kratos.sv deleted file mode 100644 index 8935b861..00000000 --- a/sam/onyx/.magma/FanoutHash_65A468071775C7BB-kratos.sv +++ /dev/null @@ -1,42 +0,0 @@ -module FanoutHash_65A468071775C7BB ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic E6, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic I6, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - input logic [31:0] S6, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -logic sel6; -assign sel0 = (~E0) | (~S0[0]) | I0; -assign sel1 = (~E1) | (~S1[0]) | I1; -assign sel2 = (~E2) | (~S2[0]) | I2; -assign sel3 = (~E3) | (~S3[3]) | I3; -assign sel4 = (~E4) | (~S4[3]) | I4; -assign sel5 = (~E5) | (~S5[3]) | I5; -assign sel6 = (~E6) | (~S6[3]) | I6; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6; -endmodule // FanoutHash_65A468071775C7BB - diff --git a/sam/onyx/.magma/FanoutHash_660E59B0DDACF452-kratos.sv b/sam/onyx/.magma/FanoutHash_660E59B0DDACF452-kratos.sv deleted file mode 100644 index 9d4632a5..00000000 --- a/sam/onyx/.magma/FanoutHash_660E59B0DDACF452-kratos.sv +++ /dev/null @@ -1,37 +0,0 @@ -module FanoutHash_660E59B0DDACF452 ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -assign sel0 = (~E0) | (~S0[2]) | I0; -assign sel1 = (~E1) | (~S1[2]) | I1; -assign sel2 = (~E2) | (~S2[2]) | I2; -assign sel3 = (~E3) | (~S3[19]) | I3; -assign sel4 = (~E4) | (~S4[19]) | I4; -assign sel5 = (~E5) | (~S5[19]) | I5; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5; -endmodule // FanoutHash_660E59B0DDACF452 - diff --git a/sam/onyx/.magma/FanoutHash_66A75CC8494A4D6B-kratos.sv b/sam/onyx/.magma/FanoutHash_66A75CC8494A4D6B-kratos.sv deleted file mode 100644 index 08c15fdb..00000000 --- a/sam/onyx/.magma/FanoutHash_66A75CC8494A4D6B-kratos.sv +++ /dev/null @@ -1,42 +0,0 @@ -module FanoutHash_66A75CC8494A4D6B ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic E6, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic I6, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - input logic [31:0] S6, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -logic sel6; -assign sel0 = (~E0) | (~S0[1]) | I0; -assign sel1 = (~E1) | (~S1[2]) | I1; -assign sel2 = (~E2) | (~S2[1]) | I2; -assign sel3 = (~E3) | (~S3[13]) | I3; -assign sel4 = (~E4) | (~S4[13]) | I4; -assign sel5 = (~E5) | (~S5[13]) | I5; -assign sel6 = (~E6) | (~S6[13]) | I6; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6; -endmodule // FanoutHash_66A75CC8494A4D6B - diff --git a/sam/onyx/.magma/FanoutHash_69376833A2418E2-kratos.sv b/sam/onyx/.magma/FanoutHash_69376833A2418E2-kratos.sv deleted file mode 100644 index a7cbf111..00000000 --- a/sam/onyx/.magma/FanoutHash_69376833A2418E2-kratos.sv +++ /dev/null @@ -1,42 +0,0 @@ -module FanoutHash_69376833A2418E2 ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic E6, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic I6, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - input logic [31:0] S6, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -logic sel6; -assign sel0 = (~E0) | (~S0[0]) | I0; -assign sel1 = (~E1) | (~S1[0]) | I1; -assign sel2 = (~E2) | (~S2[1]) | I2; -assign sel3 = (~E3) | (~S3[12]) | I3; -assign sel4 = (~E4) | (~S4[12]) | I4; -assign sel5 = (~E5) | (~S5[12]) | I5; -assign sel6 = (~E6) | (~S6[12]) | I6; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6; -endmodule // FanoutHash_69376833A2418E2 - diff --git a/sam/onyx/.magma/FanoutHash_6E1094CE0D0F6DFA-kratos.sv b/sam/onyx/.magma/FanoutHash_6E1094CE0D0F6DFA-kratos.sv deleted file mode 100644 index 2a26a093..00000000 --- a/sam/onyx/.magma/FanoutHash_6E1094CE0D0F6DFA-kratos.sv +++ /dev/null @@ -1,52 +0,0 @@ -module FanoutHash_6E1094CE0D0F6DFA ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic E6, - input logic E7, - input logic E8, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic I6, - input logic I7, - input logic I8, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - input logic [31:0] S6, - input logic [31:0] S7, - input logic [31:0] S8, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -logic sel6; -logic sel7; -logic sel8; -assign sel0 = (~E0) | (~S0[2]) | I0; -assign sel1 = (~E1) | (~S1[2]) | I1; -assign sel2 = (~E2) | (~S2[2]) | I2; -assign sel3 = (~E3) | (~S3[19]) | I3; -assign sel4 = (~E4) | (~S4[19]) | I4; -assign sel5 = (~E5) | (~S5[19]) | I5; -assign sel6 = (~E6) | (~S6[19]) | I6; -assign sel7 = (~E7) | (~S7[19]) | I7; -assign sel8 = (~E8) | (~S8[19]) | I8; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8; -endmodule // FanoutHash_6E1094CE0D0F6DFA - diff --git a/sam/onyx/.magma/FanoutHash_6EB42FA08A9B7B5B-kratos.sv b/sam/onyx/.magma/FanoutHash_6EB42FA08A9B7B5B-kratos.sv deleted file mode 100644 index 13aa8c2b..00000000 --- a/sam/onyx/.magma/FanoutHash_6EB42FA08A9B7B5B-kratos.sv +++ /dev/null @@ -1,37 +0,0 @@ -module FanoutHash_6EB42FA08A9B7B5B ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -assign sel0 = (~E0) | (~S0[1]) | I0; -assign sel1 = (~E1) | (~S1[1]) | I1; -assign sel2 = (~E2) | (~S2[0]) | I2; -assign sel3 = (~E3) | (~S3[8]) | I3; -assign sel4 = (~E4) | (~S4[8]) | I4; -assign sel5 = (~E5) | (~S5[8]) | I5; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5; -endmodule // FanoutHash_6EB42FA08A9B7B5B - diff --git a/sam/onyx/.magma/FanoutHash_74A3E41836ECED62-kratos.sv b/sam/onyx/.magma/FanoutHash_74A3E41836ECED62-kratos.sv deleted file mode 100644 index 530215cb..00000000 --- a/sam/onyx/.magma/FanoutHash_74A3E41836ECED62-kratos.sv +++ /dev/null @@ -1,52 +0,0 @@ -module FanoutHash_74A3E41836ECED62 ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic E6, - input logic E7, - input logic E8, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic I6, - input logic I7, - input logic I8, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - input logic [31:0] S6, - input logic [31:0] S7, - input logic [31:0] S8, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -logic sel6; -logic sel7; -logic sel8; -assign sel0 = (~E0) | (~S0[1]) | I0; -assign sel1 = (~E1) | (~S1[1]) | I1; -assign sel2 = (~E2) | (~S2[0]) | I2; -assign sel3 = (~E3) | (~S3[8]) | I3; -assign sel4 = (~E4) | (~S4[8]) | I4; -assign sel5 = (~E5) | (~S5[8]) | I5; -assign sel6 = (~E6) | (~S6[8]) | I6; -assign sel7 = (~E7) | (~S7[8]) | I7; -assign sel8 = (~E8) | (~S8[8]) | I8; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8; -endmodule // FanoutHash_74A3E41836ECED62 - diff --git a/sam/onyx/.magma/FanoutHash_752C11B748DD905C-kratos.sv b/sam/onyx/.magma/FanoutHash_752C11B748DD905C-kratos.sv deleted file mode 100644 index 73473a1e..00000000 --- a/sam/onyx/.magma/FanoutHash_752C11B748DD905C-kratos.sv +++ /dev/null @@ -1,42 +0,0 @@ -module FanoutHash_752C11B748DD905C ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic E6, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic I6, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - input logic [31:0] S6, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -logic sel6; -assign sel0 = (~E0) | (~S0[0]) | I0; -assign sel1 = (~E1) | (~S1[2]) | I1; -assign sel2 = (~E2) | (~S2[2]) | I2; -assign sel3 = (~E3) | (~S3[11]) | I3; -assign sel4 = (~E4) | (~S4[11]) | I4; -assign sel5 = (~E5) | (~S5[11]) | I5; -assign sel6 = (~E6) | (~S6[11]) | I6; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6; -endmodule // FanoutHash_752C11B748DD905C - diff --git a/sam/onyx/.magma/FanoutHash_7E22D83B42537D1D-kratos.sv b/sam/onyx/.magma/FanoutHash_7E22D83B42537D1D-kratos.sv deleted file mode 100644 index 96ceac3e..00000000 --- a/sam/onyx/.magma/FanoutHash_7E22D83B42537D1D-kratos.sv +++ /dev/null @@ -1,52 +0,0 @@ -module FanoutHash_7E22D83B42537D1D ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic E6, - input logic E7, - input logic E8, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic I6, - input logic I7, - input logic I8, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - input logic [31:0] S6, - input logic [31:0] S7, - input logic [31:0] S8, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -logic sel6; -logic sel7; -logic sel8; -assign sel0 = (~E0) | (~S0[0]) | I0; -assign sel1 = (~E1) | (~S1[0]) | I1; -assign sel2 = (~E2) | (~S2[1]) | I2; -assign sel3 = (~E3) | (~S3[12]) | I3; -assign sel4 = (~E4) | (~S4[12]) | I4; -assign sel5 = (~E5) | (~S5[12]) | I5; -assign sel6 = (~E6) | (~S6[12]) | I6; -assign sel7 = (~E7) | (~S7[12]) | I7; -assign sel8 = (~E8) | (~S8[12]) | I8; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8; -endmodule // FanoutHash_7E22D83B42537D1D - diff --git a/sam/onyx/.magma/FanoutHash_7ED1C80229B84786-kratos.sv b/sam/onyx/.magma/FanoutHash_7ED1C80229B84786-kratos.sv deleted file mode 100644 index 5cfe0c93..00000000 --- a/sam/onyx/.magma/FanoutHash_7ED1C80229B84786-kratos.sv +++ /dev/null @@ -1,42 +0,0 @@ -module FanoutHash_7ED1C80229B84786 ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic E6, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic I6, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - input logic [31:0] S6, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -logic sel6; -assign sel0 = (~E0) | (~S0[0]) | I0; -assign sel1 = (~E1) | (~S1[2]) | I1; -assign sel2 = (~E2) | (~S2[1]) | I2; -assign sel3 = (~E3) | (~S3[7]) | I3; -assign sel4 = (~E4) | (~S4[7]) | I4; -assign sel5 = (~E5) | (~S5[7]) | I5; -assign sel6 = (~E6) | (~S6[7]) | I6; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6; -endmodule // FanoutHash_7ED1C80229B84786 - diff --git a/sam/onyx/.magma/FanoutHash_7F4660D1463D9234-kratos.sv b/sam/onyx/.magma/FanoutHash_7F4660D1463D9234-kratos.sv deleted file mode 100644 index 4170771e..00000000 --- a/sam/onyx/.magma/FanoutHash_7F4660D1463D9234-kratos.sv +++ /dev/null @@ -1,42 +0,0 @@ -module FanoutHash_7F4660D1463D9234 ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic E6, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic I6, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - input logic [31:0] S6, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -logic sel6; -assign sel0 = (~E0) | (~S0[0]) | I0; -assign sel1 = (~E1) | (~S1[0]) | I1; -assign sel2 = (~E2) | (~S2[2]) | I2; -assign sel3 = (~E3) | (~S3[10]) | I3; -assign sel4 = (~E4) | (~S4[10]) | I4; -assign sel5 = (~E5) | (~S5[10]) | I5; -assign sel6 = (~E6) | (~S6[10]) | I6; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6; -endmodule // FanoutHash_7F4660D1463D9234 - diff --git a/sam/onyx/.magma/FanoutHash_7FDF2D3240D4A947-kratos.sv b/sam/onyx/.magma/FanoutHash_7FDF2D3240D4A947-kratos.sv deleted file mode 100644 index 5745d42e..00000000 --- a/sam/onyx/.magma/FanoutHash_7FDF2D3240D4A947-kratos.sv +++ /dev/null @@ -1,37 +0,0 @@ -module FanoutHash_7FDF2D3240D4A947 ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -assign sel0 = (~E0) | (~S0[2]) | I0; -assign sel1 = (~E1) | (~S1[2]) | I1; -assign sel2 = (~E2) | (~S2[2]) | I2; -assign sel3 = (~E3) | (~S3[15]) | I3; -assign sel4 = (~E4) | (~S4[15]) | I4; -assign sel5 = (~E5) | (~S5[15]) | I5; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5; -endmodule // FanoutHash_7FDF2D3240D4A947 - diff --git a/sam/onyx/.magma/FanoutHash_82899D6851EDC11-kratos.sv b/sam/onyx/.magma/FanoutHash_82899D6851EDC11-kratos.sv deleted file mode 100644 index c9b8e44a..00000000 --- a/sam/onyx/.magma/FanoutHash_82899D6851EDC11-kratos.sv +++ /dev/null @@ -1,108 +0,0 @@ -module FanoutHash_82899D6851EDC11 ( - input logic E0, - input logic E1, - input logic E10, - input logic E11, - input logic E12, - input logic E13, - input logic E14, - input logic E15, - input logic E16, - input logic E17, - input logic E18, - input logic E19, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic E6, - input logic E7, - input logic E8, - input logic E9, - input logic I0, - input logic I1, - input logic I10, - input logic I11, - input logic I12, - input logic I13, - input logic I14, - input logic I15, - input logic I16, - input logic I17, - input logic I18, - input logic I19, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic I6, - input logic I7, - input logic I8, - input logic I9, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S10, - input logic [7:0] S11, - input logic [7:0] S12, - input logic [7:0] S13, - input logic [7:0] S14, - input logic [7:0] S15, - input logic [7:0] S16, - input logic [7:0] S17, - input logic [7:0] S18, - input logic [7:0] S19, - input logic [7:0] S2, - input logic [7:0] S3, - input logic [7:0] S4, - input logic [7:0] S5, - input logic [7:0] S6, - input logic [7:0] S7, - input logic [7:0] S8, - input logic [7:0] S9, - output logic O -); - -logic sel0; -logic sel1; -logic sel10; -logic sel11; -logic sel12; -logic sel13; -logic sel14; -logic sel15; -logic sel16; -logic sel17; -logic sel18; -logic sel19; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -logic sel6; -logic sel7; -logic sel8; -logic sel9; -assign sel0 = (~E0) | (~S0[4]) | I0; -assign sel1 = (~E1) | (~S1[4]) | I1; -assign sel2 = (~E2) | (~S2[4]) | I2; -assign sel3 = (~E3) | (~S3[4]) | I3; -assign sel4 = (~E4) | (~S4[4]) | I4; -assign sel5 = (~E5) | (~S5[4]) | I5; -assign sel6 = (~E6) | (~S6[4]) | I6; -assign sel7 = (~E7) | (~S7[4]) | I7; -assign sel8 = (~E8) | (~S8[4]) | I8; -assign sel9 = (~E9) | (~S9[4]) | I9; -assign sel10 = (~E10) | (~S10[4]) | I10; -assign sel11 = (~E11) | (~S11[4]) | I11; -assign sel12 = (~E12) | (~S12[4]) | I12; -assign sel13 = (~E13) | (~S13[4]) | I13; -assign sel14 = (~E14) | (~S14[4]) | I14; -assign sel15 = (~E15) | (~S15[4]) | I15; -assign sel16 = (~E16) | (~S16[4]) | I16; -assign sel17 = (~E17) | (~S17[4]) | I17; -assign sel18 = (~E18) | (~S18[4]) | I18; -assign sel19 = (~E19) | (~S19[4]) | I19; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8 & sel9 & sel10 & - sel11 & sel12 & sel13 & sel14 & sel15 & sel16 & sel17 & sel18 & sel19; -endmodule // FanoutHash_82899D6851EDC11 - diff --git a/sam/onyx/.magma/FanoutHash_87642A353688B49-kratos.sv b/sam/onyx/.magma/FanoutHash_87642A353688B49-kratos.sv deleted file mode 100644 index 393255a6..00000000 --- a/sam/onyx/.magma/FanoutHash_87642A353688B49-kratos.sv +++ /dev/null @@ -1,52 +0,0 @@ -module FanoutHash_87642A353688B49 ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic E6, - input logic E7, - input logic E8, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic I6, - input logic I7, - input logic I8, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - input logic [31:0] S6, - input logic [31:0] S7, - input logic [31:0] S8, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -logic sel6; -logic sel7; -logic sel8; -assign sel0 = (~E0) | (~S0[0]) | I0; -assign sel1 = (~E1) | (~S1[0]) | I1; -assign sel2 = (~E2) | (~S2[0]) | I2; -assign sel3 = (~E3) | (~S3[3]) | I3; -assign sel4 = (~E4) | (~S4[3]) | I4; -assign sel5 = (~E5) | (~S5[3]) | I5; -assign sel6 = (~E6) | (~S6[3]) | I6; -assign sel7 = (~E7) | (~S7[3]) | I7; -assign sel8 = (~E8) | (~S8[3]) | I8; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8; -endmodule // FanoutHash_87642A353688B49 - diff --git a/sam/onyx/.magma/FanoutHash_99D793215CEDDD5-kratos.sv b/sam/onyx/.magma/FanoutHash_99D793215CEDDD5-kratos.sv deleted file mode 100644 index f4d4ee5c..00000000 --- a/sam/onyx/.magma/FanoutHash_99D793215CEDDD5-kratos.sv +++ /dev/null @@ -1,37 +0,0 @@ -module FanoutHash_99D793215CEDDD5 ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -assign sel0 = (~E0) | (~S0[0]) | I0; -assign sel1 = (~E1) | (~S1[2]) | I1; -assign sel2 = (~E2) | (~S2[1]) | I2; -assign sel3 = (~E3) | (~S3[1]) | I3; -assign sel4 = (~E4) | (~S4[1]) | I4; -assign sel5 = (~E5) | (~S5[1]) | I5; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5; -endmodule // FanoutHash_99D793215CEDDD5 - diff --git a/sam/onyx/.magma/FanoutHash_AE7392256DF8B0F-kratos.sv b/sam/onyx/.magma/FanoutHash_AE7392256DF8B0F-kratos.sv deleted file mode 100644 index fc97cdfc..00000000 --- a/sam/onyx/.magma/FanoutHash_AE7392256DF8B0F-kratos.sv +++ /dev/null @@ -1,52 +0,0 @@ -module FanoutHash_AE7392256DF8B0F ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic E6, - input logic E7, - input logic E8, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic I6, - input logic I7, - input logic I8, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - input logic [31:0] S6, - input logic [31:0] S7, - input logic [31:0] S8, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -logic sel6; -logic sel7; -logic sel8; -assign sel0 = (~E0) | (~S0[1]) | I0; -assign sel1 = (~E1) | (~S1[1]) | I1; -assign sel2 = (~E2) | (~S2[2]) | I2; -assign sel3 = (~E3) | (~S3[17]) | I3; -assign sel4 = (~E4) | (~S4[17]) | I4; -assign sel5 = (~E5) | (~S5[17]) | I5; -assign sel6 = (~E6) | (~S6[17]) | I6; -assign sel7 = (~E7) | (~S7[17]) | I7; -assign sel8 = (~E8) | (~S8[17]) | I8; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8; -endmodule // FanoutHash_AE7392256DF8B0F - diff --git a/sam/onyx/.magma/FanoutHash_CE1AA874B742213-kratos.sv b/sam/onyx/.magma/FanoutHash_CE1AA874B742213-kratos.sv deleted file mode 100644 index c1dc7330..00000000 --- a/sam/onyx/.magma/FanoutHash_CE1AA874B742213-kratos.sv +++ /dev/null @@ -1,108 +0,0 @@ -module FanoutHash_CE1AA874B742213 ( - input logic E0, - input logic E1, - input logic E10, - input logic E11, - input logic E12, - input logic E13, - input logic E14, - input logic E15, - input logic E16, - input logic E17, - input logic E18, - input logic E19, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic E6, - input logic E7, - input logic E8, - input logic E9, - input logic I0, - input logic I1, - input logic I10, - input logic I11, - input logic I12, - input logic I13, - input logic I14, - input logic I15, - input logic I16, - input logic I17, - input logic I18, - input logic I19, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic I6, - input logic I7, - input logic I8, - input logic I9, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S10, - input logic [7:0] S11, - input logic [7:0] S12, - input logic [7:0] S13, - input logic [7:0] S14, - input logic [7:0] S15, - input logic [7:0] S16, - input logic [7:0] S17, - input logic [7:0] S18, - input logic [7:0] S19, - input logic [7:0] S2, - input logic [7:0] S3, - input logic [7:0] S4, - input logic [7:0] S5, - input logic [7:0] S6, - input logic [7:0] S7, - input logic [7:0] S8, - input logic [7:0] S9, - output logic O -); - -logic sel0; -logic sel1; -logic sel10; -logic sel11; -logic sel12; -logic sel13; -logic sel14; -logic sel15; -logic sel16; -logic sel17; -logic sel18; -logic sel19; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -logic sel6; -logic sel7; -logic sel8; -logic sel9; -assign sel0 = (~E0) | (~S0[5]) | I0; -assign sel1 = (~E1) | (~S1[5]) | I1; -assign sel2 = (~E2) | (~S2[5]) | I2; -assign sel3 = (~E3) | (~S3[5]) | I3; -assign sel4 = (~E4) | (~S4[5]) | I4; -assign sel5 = (~E5) | (~S5[5]) | I5; -assign sel6 = (~E6) | (~S6[5]) | I6; -assign sel7 = (~E7) | (~S7[5]) | I7; -assign sel8 = (~E8) | (~S8[5]) | I8; -assign sel9 = (~E9) | (~S9[5]) | I9; -assign sel10 = (~E10) | (~S10[5]) | I10; -assign sel11 = (~E11) | (~S11[5]) | I11; -assign sel12 = (~E12) | (~S12[5]) | I12; -assign sel13 = (~E13) | (~S13[5]) | I13; -assign sel14 = (~E14) | (~S14[5]) | I14; -assign sel15 = (~E15) | (~S15[5]) | I15; -assign sel16 = (~E16) | (~S16[5]) | I16; -assign sel17 = (~E17) | (~S17[5]) | I17; -assign sel18 = (~E18) | (~S18[5]) | I18; -assign sel19 = (~E19) | (~S19[5]) | I19; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8 & sel9 & sel10 & - sel11 & sel12 & sel13 & sel14 & sel15 & sel16 & sel17 & sel18 & sel19; -endmodule // FanoutHash_CE1AA874B742213 - diff --git a/sam/onyx/.magma/FanoutHash_D70CFBE8EA3CE7F-kratos.sv b/sam/onyx/.magma/FanoutHash_D70CFBE8EA3CE7F-kratos.sv deleted file mode 100644 index 359f72e9..00000000 --- a/sam/onyx/.magma/FanoutHash_D70CFBE8EA3CE7F-kratos.sv +++ /dev/null @@ -1,37 +0,0 @@ -module FanoutHash_D70CFBE8EA3CE7F ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -assign sel0 = (~E0) | (~S0[0]) | I0; -assign sel1 = (~E1) | (~S1[0]) | I1; -assign sel2 = (~E2) | (~S2[2]) | I2; -assign sel3 = (~E3) | (~S3[14]) | I3; -assign sel4 = (~E4) | (~S4[14]) | I4; -assign sel5 = (~E5) | (~S5[14]) | I5; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5; -endmodule // FanoutHash_D70CFBE8EA3CE7F - diff --git a/sam/onyx/.magma/FanoutHash_E70AF988E4250F5-kratos.sv b/sam/onyx/.magma/FanoutHash_E70AF988E4250F5-kratos.sv deleted file mode 100644 index 7ad618e8..00000000 --- a/sam/onyx/.magma/FanoutHash_E70AF988E4250F5-kratos.sv +++ /dev/null @@ -1,108 +0,0 @@ -module FanoutHash_E70AF988E4250F5 ( - input logic E0, - input logic E1, - input logic E10, - input logic E11, - input logic E12, - input logic E13, - input logic E14, - input logic E15, - input logic E16, - input logic E17, - input logic E18, - input logic E19, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic E6, - input logic E7, - input logic E8, - input logic E9, - input logic I0, - input logic I1, - input logic I10, - input logic I11, - input logic I12, - input logic I13, - input logic I14, - input logic I15, - input logic I16, - input logic I17, - input logic I18, - input logic I19, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic I6, - input logic I7, - input logic I8, - input logic I9, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S10, - input logic [7:0] S11, - input logic [7:0] S12, - input logic [7:0] S13, - input logic [7:0] S14, - input logic [7:0] S15, - input logic [7:0] S16, - input logic [7:0] S17, - input logic [7:0] S18, - input logic [7:0] S19, - input logic [7:0] S2, - input logic [7:0] S3, - input logic [7:0] S4, - input logic [7:0] S5, - input logic [7:0] S6, - input logic [7:0] S7, - input logic [7:0] S8, - input logic [7:0] S9, - output logic O -); - -logic sel0; -logic sel1; -logic sel10; -logic sel11; -logic sel12; -logic sel13; -logic sel14; -logic sel15; -logic sel16; -logic sel17; -logic sel18; -logic sel19; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -logic sel6; -logic sel7; -logic sel8; -logic sel9; -assign sel0 = (~E0) | (~S0[3]) | I0; -assign sel1 = (~E1) | (~S1[3]) | I1; -assign sel2 = (~E2) | (~S2[3]) | I2; -assign sel3 = (~E3) | (~S3[3]) | I3; -assign sel4 = (~E4) | (~S4[3]) | I4; -assign sel5 = (~E5) | (~S5[3]) | I5; -assign sel6 = (~E6) | (~S6[3]) | I6; -assign sel7 = (~E7) | (~S7[3]) | I7; -assign sel8 = (~E8) | (~S8[3]) | I8; -assign sel9 = (~E9) | (~S9[3]) | I9; -assign sel10 = (~E10) | (~S10[3]) | I10; -assign sel11 = (~E11) | (~S11[3]) | I11; -assign sel12 = (~E12) | (~S12[3]) | I12; -assign sel13 = (~E13) | (~S13[3]) | I13; -assign sel14 = (~E14) | (~S14[3]) | I14; -assign sel15 = (~E15) | (~S15[3]) | I15; -assign sel16 = (~E16) | (~S16[3]) | I16; -assign sel17 = (~E17) | (~S17[3]) | I17; -assign sel18 = (~E18) | (~S18[3]) | I18; -assign sel19 = (~E19) | (~S19[3]) | I19; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8 & sel9 & sel10 & - sel11 & sel12 & sel13 & sel14 & sel15 & sel16 & sel17 & sel18 & sel19; -endmodule // FanoutHash_E70AF988E4250F5 - diff --git a/sam/onyx/.magma/FanoutHash_F689C91787363AB-kratos.sv b/sam/onyx/.magma/FanoutHash_F689C91787363AB-kratos.sv deleted file mode 100644 index 99188fa0..00000000 --- a/sam/onyx/.magma/FanoutHash_F689C91787363AB-kratos.sv +++ /dev/null @@ -1,113 +0,0 @@ -module FanoutHash_F689C91787363AB ( - input logic E0, - input logic E1, - input logic E10, - input logic E11, - input logic E12, - input logic E13, - input logic E14, - input logic E15, - input logic E16, - input logic E17, - input logic E18, - input logic E19, - input logic E2, - input logic E20, - input logic E3, - input logic E4, - input logic E5, - input logic E6, - input logic E7, - input logic E8, - input logic E9, - input logic I0, - input logic I1, - input logic I10, - input logic I11, - input logic I12, - input logic I13, - input logic I14, - input logic I15, - input logic I16, - input logic I17, - input logic I18, - input logic I19, - input logic I2, - input logic I20, - input logic I3, - input logic I4, - input logic I5, - input logic I6, - input logic I7, - input logic I8, - input logic I9, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S10, - input logic [7:0] S11, - input logic [7:0] S12, - input logic [7:0] S13, - input logic [7:0] S14, - input logic [7:0] S15, - input logic [7:0] S16, - input logic [7:0] S17, - input logic [7:0] S18, - input logic [7:0] S19, - input logic [7:0] S2, - input logic [31:0] S20, - input logic [7:0] S3, - input logic [7:0] S4, - input logic [7:0] S5, - input logic [7:0] S6, - input logic [7:0] S7, - input logic [7:0] S8, - input logic [7:0] S9, - output logic O -); - -logic sel0; -logic sel1; -logic sel10; -logic sel11; -logic sel12; -logic sel13; -logic sel14; -logic sel15; -logic sel16; -logic sel17; -logic sel18; -logic sel19; -logic sel2; -logic sel20; -logic sel3; -logic sel4; -logic sel5; -logic sel6; -logic sel7; -logic sel8; -logic sel9; -assign sel0 = (~E0) | (~S0[4]) | I0; -assign sel1 = (~E1) | (~S1[4]) | I1; -assign sel2 = (~E2) | (~S2[4]) | I2; -assign sel3 = (~E3) | (~S3[4]) | I3; -assign sel4 = (~E4) | (~S4[4]) | I4; -assign sel5 = (~E5) | (~S5[4]) | I5; -assign sel6 = (~E6) | (~S6[4]) | I6; -assign sel7 = (~E7) | (~S7[4]) | I7; -assign sel8 = (~E8) | (~S8[4]) | I8; -assign sel9 = (~E9) | (~S9[4]) | I9; -assign sel10 = (~E10) | (~S10[4]) | I10; -assign sel11 = (~E11) | (~S11[4]) | I11; -assign sel12 = (~E12) | (~S12[4]) | I12; -assign sel13 = (~E13) | (~S13[4]) | I13; -assign sel14 = (~E14) | (~S14[4]) | I14; -assign sel15 = (~E15) | (~S15[4]) | I15; -assign sel16 = (~E16) | (~S16[4]) | I16; -assign sel17 = (~E17) | (~S17[4]) | I17; -assign sel18 = (~E18) | (~S18[4]) | I18; -assign sel19 = (~E19) | (~S19[4]) | I19; -assign sel20 = (~E20) | (~S20[20]) | I20; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5 & sel6 & sel7 & sel8 & sel9 & sel10 & - sel11 & sel12 & sel13 & sel14 & sel15 & sel16 & sel17 & sel18 & sel19 & sel20; -endmodule // FanoutHash_F689C91787363AB - diff --git a/sam/onyx/.magma/FanoutHash_F8E7A0823DC8CDD-kratos.sv b/sam/onyx/.magma/FanoutHash_F8E7A0823DC8CDD-kratos.sv deleted file mode 100644 index e519ead7..00000000 --- a/sam/onyx/.magma/FanoutHash_F8E7A0823DC8CDD-kratos.sv +++ /dev/null @@ -1,37 +0,0 @@ -module FanoutHash_F8E7A0823DC8CDD ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -assign sel0 = (~E0) | (~S0[0]) | I0; -assign sel1 = (~E1) | (~S1[2]) | I1; -assign sel2 = (~E2) | (~S2[2]) | I2; -assign sel3 = (~E3) | (~S3[11]) | I3; -assign sel4 = (~E4) | (~S4[11]) | I4; -assign sel5 = (~E5) | (~S5[11]) | I5; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5; -endmodule // FanoutHash_F8E7A0823DC8CDD - diff --git a/sam/onyx/.magma/FanoutHash_F95D10B01D02012-kratos.sv b/sam/onyx/.magma/FanoutHash_F95D10B01D02012-kratos.sv deleted file mode 100644 index 195a0d77..00000000 --- a/sam/onyx/.magma/FanoutHash_F95D10B01D02012-kratos.sv +++ /dev/null @@ -1,37 +0,0 @@ -module FanoutHash_F95D10B01D02012 ( - input logic E0, - input logic E1, - input logic E2, - input logic E3, - input logic E4, - input logic E5, - input logic I0, - input logic I1, - input logic I2, - input logic I3, - input logic I4, - input logic I5, - input logic [7:0] S0, - input logic [7:0] S1, - input logic [7:0] S2, - input logic [31:0] S3, - input logic [31:0] S4, - input logic [31:0] S5, - output logic O -); - -logic sel0; -logic sel1; -logic sel2; -logic sel3; -logic sel4; -logic sel5; -assign sel0 = (~E0) | (~S0[0]) | I0; -assign sel1 = (~E1) | (~S1[0]) | I1; -assign sel2 = (~E2) | (~S2[1]) | I2; -assign sel3 = (~E3) | (~S3[0]) | I3; -assign sel4 = (~E4) | (~S4[0]) | I4; -assign sel5 = (~E5) | (~S5[0]) | I5; -assign O = sel0 & sel1 & sel2 & sel3 & sel4 & sel5; -endmodule // FanoutHash_F95D10B01D02012 - diff --git a/sam/onyx/.magma/MemCore_inner_W-kratos.sv b/sam/onyx/.magma/MemCore_inner_W-kratos.sv deleted file mode 100644 index 80260613..00000000 --- a/sam/onyx/.magma/MemCore_inner_W-kratos.sv +++ /dev/null @@ -1,11527 +0,0 @@ -module Chain_2_16 ( - input logic [1:0] accessor_output, - input logic [1:0] [15:0] chain_data_in, - input logic chain_en, - input logic clk_en, - input logic [1:0] [15:0] curr_tile_data_out, - input logic flush, - output logic [1:0] [15:0] data_out_tile -); - -always_comb begin - if (accessor_output[0]) begin - data_out_tile[0] = curr_tile_data_out[0]; - end - else if (chain_en) begin - data_out_tile[0] = chain_data_in[0]; - end - else data_out_tile[0] = 16'h0; - if (accessor_output[1]) begin - data_out_tile[1] = curr_tile_data_out[1]; - end - else if (chain_en) begin - data_out_tile[1] = chain_data_in[1]; - end - else data_out_tile[1] = 16'h0; -end -endmodule // Chain_2_16 - -module MemCore_inner ( - input logic [31:0] CONFIG_SPACE_0, - input logic [31:0] CONFIG_SPACE_1, - input logic [31:0] CONFIG_SPACE_10, - input logic [31:0] CONFIG_SPACE_11, - input logic [31:0] CONFIG_SPACE_12, - input logic [31:0] CONFIG_SPACE_13, - input logic [31:0] CONFIG_SPACE_14, - input logic [31:0] CONFIG_SPACE_15, - input logic [31:0] CONFIG_SPACE_16, - input logic [31:0] CONFIG_SPACE_17, - input logic [31:0] CONFIG_SPACE_18, - input logic [31:0] CONFIG_SPACE_19, - input logic [31:0] CONFIG_SPACE_2, - input logic [31:0] CONFIG_SPACE_20, - input logic [31:0] CONFIG_SPACE_21, - input logic [31:0] CONFIG_SPACE_22, - input logic [31:0] CONFIG_SPACE_23, - input logic [31:0] CONFIG_SPACE_24, - input logic [31:0] CONFIG_SPACE_25, - input logic [31:0] CONFIG_SPACE_26, - input logic [31:0] CONFIG_SPACE_27, - input logic [31:0] CONFIG_SPACE_28, - input logic [31:0] CONFIG_SPACE_29, - input logic [31:0] CONFIG_SPACE_3, - input logic [31:0] CONFIG_SPACE_30, - input logic [31:0] CONFIG_SPACE_31, - input logic [31:0] CONFIG_SPACE_32, - input logic [31:0] CONFIG_SPACE_33, - input logic [31:0] CONFIG_SPACE_34, - input logic [31:0] CONFIG_SPACE_35, - input logic [31:0] CONFIG_SPACE_36, - input logic [31:0] CONFIG_SPACE_37, - input logic [31:0] CONFIG_SPACE_38, - input logic [31:0] CONFIG_SPACE_39, - input logic [31:0] CONFIG_SPACE_4, - input logic [31:0] CONFIG_SPACE_40, - input logic [31:0] CONFIG_SPACE_41, - input logic [31:0] CONFIG_SPACE_42, - input logic [31:0] CONFIG_SPACE_43, - input logic [31:0] CONFIG_SPACE_44, - input logic [18:0] CONFIG_SPACE_45, - input logic [31:0] CONFIG_SPACE_5, - input logic [31:0] CONFIG_SPACE_6, - input logic [31:0] CONFIG_SPACE_7, - input logic [31:0] CONFIG_SPACE_8, - input logic [31:0] CONFIG_SPACE_9, - input logic [0:0] [16:0] MEM_input_width_17_num_0, - input logic MEM_input_width_17_num_0_valid, - input logic [0:0] [16:0] MEM_input_width_17_num_1, - input logic MEM_input_width_17_num_1_valid, - input logic [0:0] [16:0] MEM_input_width_17_num_2, - input logic MEM_input_width_17_num_2_valid, - input logic [0:0] [16:0] MEM_input_width_17_num_3, - input logic MEM_input_width_17_num_3_valid, - input logic MEM_input_width_1_num_0, - input logic MEM_input_width_1_num_1, - input logic MEM_output_width_17_num_0_ready, - input logic MEM_output_width_17_num_1_ready, - input logic MEM_output_width_17_num_2_ready, - input logic clk, - input logic clk_en, - input logic [7:0] config_addr_in, - input logic [31:0] config_data_in, - input logic [1:0] config_en, - input logic config_read, - input logic config_write, - input logic flush, - input logic [1:0] mode, - input logic mode_excl, - input logic rst_n, - input logic tile_en, - output logic MEM_input_width_17_num_0_ready, - output logic MEM_input_width_17_num_1_ready, - output logic MEM_input_width_17_num_2_ready, - output logic MEM_input_width_17_num_3_ready, - output logic [0:0] [16:0] MEM_output_width_17_num_0, - output logic MEM_output_width_17_num_0_valid, - output logic [0:0] [16:0] MEM_output_width_17_num_1, - output logic MEM_output_width_17_num_1_valid, - output logic [0:0] [16:0] MEM_output_width_17_num_2, - output logic MEM_output_width_17_num_2_valid, - output logic MEM_output_width_1_num_0, - output logic MEM_output_width_1_num_1, - output logic MEM_output_width_1_num_2, - output logic [1:0] [31:0] config_data_out -); - -logic [1458:0] CONFIG_SPACE; -logic [15:0] config_data_in_shrt; -logic [1:0][15:0] config_data_out_shrt; -logic [8:0] config_seq_addr_out; -logic config_seq_clk_en; -logic [0:0][3:0][15:0] config_seq_rd_data_stg; -logic config_seq_ren_out; -logic config_seq_wen_out; -logic [3:0][15:0] config_seq_wr_data; -logic gclk; -logic [0:0][16:0] input_width_17_num_0_fifo_out; -logic input_width_17_num_0_fifo_out_ready; -logic input_width_17_num_0_fifo_out_valid; -logic input_width_17_num_0_input_fifo_empty; -logic input_width_17_num_0_input_fifo_full; -logic [0:0][16:0] input_width_17_num_1_fifo_out; -logic input_width_17_num_1_fifo_out_ready; -logic input_width_17_num_1_fifo_out_valid; -logic input_width_17_num_1_input_fifo_empty; -logic input_width_17_num_1_input_fifo_full; -logic [0:0][16:0] input_width_17_num_2_fifo_out; -logic input_width_17_num_2_fifo_out_ready; -logic input_width_17_num_2_fifo_out_valid; -logic input_width_17_num_2_input_fifo_empty; -logic input_width_17_num_2_input_fifo_full; -logic [0:0][16:0] input_width_17_num_3_fifo_out; -logic input_width_17_num_3_fifo_out_ready; -logic input_width_17_num_3_fifo_out_valid; -logic input_width_17_num_3_input_fifo_empty; -logic input_width_17_num_3_input_fifo_full; -logic mem_ctrl_fiber_access_16_flat_clk; -logic [8:0] mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_addr_to_mem_lifted_lifted; -logic [3:0] mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_buffet_capacity_log_0; -logic [3:0] mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_buffet_capacity_log_1; -logic [3:0][15:0] mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_data_from_mem_lifted_lifted; -logic [3:0][15:0] mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_data_to_mem_lifted_lifted; -logic mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_ren_to_mem_lifted_lifted; -logic mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_tile_en; -logic mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_wen_to_mem_lifted_lifted; -logic mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_block_mode; -logic mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_dense; -logic [15:0] mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_dim_size; -logic mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_do_repeat; -logic [15:0] mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_inner_dim_offset; -logic mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_lookup; -logic [15:0] mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_repeat_factor; -logic mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_repeat_outer_inner_n; -logic mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_root; -logic mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_tile_en; -logic mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_tile_en; -logic mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_vector_reduce_mode; -logic mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_write_scanner_block_mode; -logic mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_write_scanner_compressed; -logic mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_write_scanner_init_blank; -logic mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_write_scanner_lowest_level; -logic [15:0] mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_write_scanner_stop_lvl; -logic mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_write_scanner_tile_en; -logic [0:0][16:0] mem_ctrl_fiber_access_16_flat_read_scanner_block_rd_out_f_; -logic mem_ctrl_fiber_access_16_flat_read_scanner_block_rd_out_valid_f_; -logic [0:0][16:0] mem_ctrl_fiber_access_16_flat_read_scanner_coord_out_f_; -logic mem_ctrl_fiber_access_16_flat_read_scanner_coord_out_valid_f_; -logic [0:0][16:0] mem_ctrl_fiber_access_16_flat_read_scanner_pos_out_f_; -logic mem_ctrl_fiber_access_16_flat_read_scanner_pos_out_valid_f_; -logic mem_ctrl_fiber_access_16_flat_read_scanner_us_pos_in_ready_f_; -logic mem_ctrl_fiber_access_16_flat_write_scanner_addr_in_ready_f_; -logic mem_ctrl_fiber_access_16_flat_write_scanner_block_wr_in_ready_f_; -logic mem_ctrl_fiber_access_16_flat_write_scanner_data_in_ready_f_; -logic mem_ctrl_stencil_valid_flat_clk; -logic mem_ctrl_stencil_valid_flat_stencil_valid_f_; -logic [3:0] mem_ctrl_stencil_valid_flat_stencil_valid_inst_loops_stencil_valid_dimensionality; -logic [10:0] mem_ctrl_stencil_valid_flat_stencil_valid_inst_loops_stencil_valid_ranges_0; -logic [10:0] mem_ctrl_stencil_valid_flat_stencil_valid_inst_loops_stencil_valid_ranges_1; -logic [10:0] mem_ctrl_stencil_valid_flat_stencil_valid_inst_loops_stencil_valid_ranges_2; -logic [10:0] mem_ctrl_stencil_valid_flat_stencil_valid_inst_loops_stencil_valid_ranges_3; -logic [10:0] mem_ctrl_stencil_valid_flat_stencil_valid_inst_loops_stencil_valid_ranges_4; -logic [10:0] mem_ctrl_stencil_valid_flat_stencil_valid_inst_loops_stencil_valid_ranges_5; -logic mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_enable; -logic [15:0] mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_starting_addr; -logic [15:0] mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_0; -logic [15:0] mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_1; -logic [15:0] mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_2; -logic [15:0] mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_3; -logic [15:0] mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_4; -logic [15:0] mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_5; -logic mem_ctrl_strg_ram_64_512_delay1_flat_clk; -logic [0:0][16:0] mem_ctrl_strg_ram_64_512_delay1_flat_data_out_f_; -logic mem_ctrl_strg_ram_64_512_delay1_flat_ready_f_; -logic [0:0][8:0] mem_ctrl_strg_ram_64_512_delay1_flat_strg_ram_64_512_delay1_inst_addr_out_lifted; -logic [0:0][3:0][15:0] mem_ctrl_strg_ram_64_512_delay1_flat_strg_ram_64_512_delay1_inst_data_from_strg_lifted; -logic [0:0][3:0][15:0] mem_ctrl_strg_ram_64_512_delay1_flat_strg_ram_64_512_delay1_inst_data_to_strg_lifted; -logic mem_ctrl_strg_ram_64_512_delay1_flat_strg_ram_64_512_delay1_inst_ren_to_strg_lifted; -logic mem_ctrl_strg_ram_64_512_delay1_flat_strg_ram_64_512_delay1_inst_wen_to_strg_lifted; -logic mem_ctrl_strg_ram_64_512_delay1_flat_valid_out_f_; -logic mem_ctrl_strg_ub_vec_flat_accessor_output_f_b_0; -logic mem_ctrl_strg_ub_vec_flat_accessor_output_f_b_1; -logic mem_ctrl_strg_ub_vec_flat_clk; -logic [0:0][16:0] mem_ctrl_strg_ub_vec_flat_data_out_f_0; -logic [0:0][16:0] mem_ctrl_strg_ub_vec_flat_data_out_f_1; -logic [8:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_addr_out_lifted; -logic [2:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_starting_addr; -logic [2:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_strides_0; -logic [2:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_strides_1; -logic [2:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_strides_2; -logic [2:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_starting_addr; -logic [2:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_strides_0; -logic [2:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_strides_1; -logic [2:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_strides_2; -logic mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_enable; -logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_starting_addr; -logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_0; -logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_1; -logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_2; -logic mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_enable; -logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_starting_addr; -logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_0; -logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_1; -logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_2; -logic [2:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_0_dimensionality; -logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_0_ranges_0; -logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_0_ranges_1; -logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_0_ranges_2; -logic [2:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_1_dimensionality; -logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_1_ranges_0; -logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_1_ranges_1; -logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_1_ranges_2; -logic [7:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_sram_shared_agg_read_sched_gen_0_agg_read_padding; -logic [7:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_sram_shared_agg_read_sched_gen_1_agg_read_padding; -logic [8:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_sram_shared_agg_sram_shared_addr_gen_0_starting_addr; -logic [8:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_sram_shared_agg_sram_shared_addr_gen_1_starting_addr; -logic [1:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_sram_shared_mode_0; -logic [1:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_sram_shared_mode_1; -logic mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_chain_chain_en; -logic [3:0][15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_data_from_strg_lifted; -logic [3:0][15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_data_to_strg_lifted; -logic mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_ren_to_strg_lifted; -logic [8:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_0_starting_addr; -logic [8:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_0; -logic [8:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_1; -logic [8:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_2; -logic [8:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_3; -logic [8:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_4; -logic [8:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_5; -logic [8:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_1_starting_addr; -logic [8:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_0; -logic [8:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_1; -logic [8:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_2; -logic [8:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_3; -logic [8:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_4; -logic [8:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_5; -logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_dimensionality; -logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_0; -logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_1; -logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_2; -logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_3; -logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_4; -logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_5; -logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_dimensionality; -logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_0; -logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_1; -logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_2; -logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_3; -logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_4; -logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_5; -logic mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_enable; -logic [9:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_delay; -logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_starting_addr; -logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_0; -logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_1; -logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_2; -logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_3; -logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_4; -logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_5; -logic mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_enable; -logic [9:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_delay; -logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_starting_addr; -logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_0; -logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_1; -logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_2; -logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_3; -logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_4; -logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_5; -logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_0_dimensionality; -logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_0; -logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_1; -logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_2; -logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_3; -logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_4; -logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_5; -logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_1_dimensionality; -logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_0; -logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_1; -logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_2; -logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_3; -logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_4; -logic [10:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_5; -logic mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_shared_tb_0; -logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_starting_addr; -logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_0; -logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_1; -logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_2; -logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_3; -logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_4; -logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_5; -logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_starting_addr; -logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_0; -logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_1; -logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_2; -logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_3; -logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_4; -logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_5; -logic mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_enable; -logic [9:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_delay; -logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_starting_addr; -logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_0; -logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_1; -logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_2; -logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_3; -logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_4; -logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_5; -logic mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_enable; -logic [9:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_delay; -logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_starting_addr; -logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_0; -logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_1; -logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_2; -logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_3; -logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_4; -logic [15:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_5; -logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_starting_addr; -logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_0; -logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_1; -logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_2; -logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_3; -logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_4; -logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_5; -logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_starting_addr; -logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_0; -logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_1; -logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_2; -logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_3; -logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_4; -logic [3:0] mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_5; -logic mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_wen_to_strg_lifted; -logic memory_0_clk_en; -logic [63:0] memory_0_data_in_p0; -logic [63:0] memory_0_data_out_p0; -logic [8:0] memory_0_read_addr_p0; -logic memory_0_read_enable_p0; -logic [8:0] memory_0_write_addr_p0; -logic memory_0_write_enable_p0; -logic [0:0][16:0] output_width_17_num_0_fifo_in; -logic output_width_17_num_0_fifo_in_ready; -logic output_width_17_num_0_fifo_in_valid; -logic [0:0][16:0] output_width_17_num_0_output_fifo_data_out; -logic output_width_17_num_0_output_fifo_empty; -logic output_width_17_num_0_output_fifo_full; -logic [0:0][16:0] output_width_17_num_1_fifo_in; -logic output_width_17_num_1_fifo_in_ready; -logic output_width_17_num_1_fifo_in_valid; -logic [0:0][16:0] output_width_17_num_1_output_fifo_data_out; -logic output_width_17_num_1_output_fifo_empty; -logic output_width_17_num_1_output_fifo_full; -logic [0:0][16:0] output_width_17_num_2_fifo_in; -logic output_width_17_num_2_fifo_in_ready; -logic output_width_17_num_2_fifo_in_valid; -logic [0:0][16:0] output_width_17_num_2_output_fifo_data_out; -logic output_width_17_num_2_output_fifo_empty; -logic output_width_17_num_2_output_fifo_full; -assign gclk = clk & tile_en; -assign mem_ctrl_fiber_access_16_flat_clk = gclk & (mode == 2'h0); -assign mem_ctrl_strg_ub_vec_flat_clk = gclk & (mode == 2'h1); -assign mem_ctrl_strg_ram_64_512_delay1_flat_clk = gclk & (mode == 2'h2); -assign mem_ctrl_stencil_valid_flat_clk = gclk; -assign input_width_17_num_0_fifo_out_valid = ~input_width_17_num_0_input_fifo_empty; -always_comb begin - input_width_17_num_0_fifo_out_ready = 1'h1; - if (mode == 2'h0) begin - input_width_17_num_0_fifo_out_ready = mem_ctrl_fiber_access_16_flat_read_scanner_us_pos_in_ready_f_; - end - else input_width_17_num_0_fifo_out_ready = 1'h1; -end -always_comb begin - MEM_input_width_17_num_0_ready = 1'h1; - if (mode == 2'h0) begin - MEM_input_width_17_num_0_ready = ~input_width_17_num_0_input_fifo_full; - end - else if (mode == 2'h1) begin - MEM_input_width_17_num_0_ready = 1'h1; - end - else if (mode == 2'h2) begin - MEM_input_width_17_num_0_ready = 1'h1; - end -end -assign input_width_17_num_1_fifo_out_valid = ~input_width_17_num_1_input_fifo_empty; -always_comb begin - input_width_17_num_1_fifo_out_ready = 1'h1; - if (mode == 2'h0) begin - input_width_17_num_1_fifo_out_ready = mem_ctrl_fiber_access_16_flat_write_scanner_addr_in_ready_f_; - end - else input_width_17_num_1_fifo_out_ready = 1'h1; -end -always_comb begin - MEM_input_width_17_num_1_ready = 1'h1; - if (mode == 2'h0) begin - MEM_input_width_17_num_1_ready = ~input_width_17_num_1_input_fifo_full; - end - else if (mode == 2'h1) begin - MEM_input_width_17_num_1_ready = 1'h1; - end - else if (mode == 2'h2) begin - MEM_input_width_17_num_1_ready = 1'h1; - end -end -assign input_width_17_num_2_fifo_out_valid = ~input_width_17_num_2_input_fifo_empty; -always_comb begin - input_width_17_num_2_fifo_out_ready = 1'h1; - if (mode == 2'h0) begin - input_width_17_num_2_fifo_out_ready = mem_ctrl_fiber_access_16_flat_write_scanner_block_wr_in_ready_f_; - end - else input_width_17_num_2_fifo_out_ready = 1'h1; -end -always_comb begin - MEM_input_width_17_num_2_ready = 1'h1; - if (mode == 2'h0) begin - MEM_input_width_17_num_2_ready = ~input_width_17_num_2_input_fifo_full; - end - else if (mode == 2'h1) begin - MEM_input_width_17_num_2_ready = 1'h1; - end - else if (mode == 2'h2) begin - MEM_input_width_17_num_2_ready = 1'h1; - end -end -assign input_width_17_num_3_fifo_out_valid = ~input_width_17_num_3_input_fifo_empty; -always_comb begin - input_width_17_num_3_fifo_out_ready = 1'h1; - if (mode == 2'h0) begin - input_width_17_num_3_fifo_out_ready = mem_ctrl_fiber_access_16_flat_write_scanner_data_in_ready_f_; - end - else input_width_17_num_3_fifo_out_ready = 1'h1; -end -always_comb begin - MEM_input_width_17_num_3_ready = 1'h1; - if (mode == 2'h0) begin - MEM_input_width_17_num_3_ready = ~input_width_17_num_3_input_fifo_full; - end - else if (mode == 2'h1) begin - MEM_input_width_17_num_3_ready = 1'h1; - end -end -assign output_width_17_num_0_fifo_in_ready = ~output_width_17_num_0_output_fifo_full; -always_comb begin - output_width_17_num_0_fifo_in = 17'h0; - output_width_17_num_0_fifo_in_valid = 1'h0; - output_width_17_num_0_fifo_in = mem_ctrl_fiber_access_16_flat_read_scanner_block_rd_out_f_; - output_width_17_num_0_fifo_in_valid = mem_ctrl_fiber_access_16_flat_read_scanner_block_rd_out_valid_f_; -end -always_comb begin - MEM_output_width_17_num_0 = 17'h0; - if (mode == 2'h0) begin - MEM_output_width_17_num_0 = output_width_17_num_0_output_fifo_data_out; - end - else if (mode == 2'h1) begin - MEM_output_width_17_num_0 = mem_ctrl_strg_ub_vec_flat_data_out_f_0; - end - else if (mode == 2'h2) begin - MEM_output_width_17_num_0 = mem_ctrl_strg_ram_64_512_delay1_flat_data_out_f_; - end -end -always_comb begin - MEM_output_width_17_num_0_valid = 1'h0; - if (mode == 2'h0) begin - MEM_output_width_17_num_0_valid = ~output_width_17_num_0_output_fifo_empty; - end - else if (mode == 2'h1) begin - MEM_output_width_17_num_0_valid = 1'h1; - end - else if (mode == 2'h2) begin - MEM_output_width_17_num_0_valid = 1'h1; - end -end -assign output_width_17_num_1_fifo_in_ready = ~output_width_17_num_1_output_fifo_full; -always_comb begin - output_width_17_num_1_fifo_in = 17'h0; - output_width_17_num_1_fifo_in_valid = 1'h0; - output_width_17_num_1_fifo_in = mem_ctrl_fiber_access_16_flat_read_scanner_coord_out_f_; - output_width_17_num_1_fifo_in_valid = mem_ctrl_fiber_access_16_flat_read_scanner_coord_out_valid_f_; -end -always_comb begin - MEM_output_width_17_num_1 = 17'h0; - if (mode == 2'h0) begin - MEM_output_width_17_num_1 = output_width_17_num_1_output_fifo_data_out; - end - else if (mode == 2'h1) begin - MEM_output_width_17_num_1 = mem_ctrl_strg_ub_vec_flat_data_out_f_1; - end -end -always_comb begin - MEM_output_width_17_num_1_valid = 1'h0; - if (mode == 2'h0) begin - MEM_output_width_17_num_1_valid = ~output_width_17_num_1_output_fifo_empty; - end - else if (mode == 2'h1) begin - MEM_output_width_17_num_1_valid = 1'h1; - end -end -assign output_width_17_num_2_fifo_in_ready = ~output_width_17_num_2_output_fifo_full; -always_comb begin - output_width_17_num_2_fifo_in = 17'h0; - output_width_17_num_2_fifo_in_valid = 1'h0; - output_width_17_num_2_fifo_in = mem_ctrl_fiber_access_16_flat_read_scanner_pos_out_f_; - output_width_17_num_2_fifo_in_valid = mem_ctrl_fiber_access_16_flat_read_scanner_pos_out_valid_f_; -end -always_comb begin - MEM_output_width_17_num_2 = 17'h0; - if (mode == 2'h0) begin - MEM_output_width_17_num_2 = output_width_17_num_2_output_fifo_data_out; - end - else MEM_output_width_17_num_2 = 17'h0; -end -always_comb begin - MEM_output_width_17_num_2_valid = 1'h0; - if (mode == 2'h0) begin - MEM_output_width_17_num_2_valid = ~output_width_17_num_2_output_fifo_empty; - end - else MEM_output_width_17_num_2_valid = 1'h0; -end -always_comb begin - MEM_output_width_1_num_0 = 1'h0; - if (mode == 2'h1) begin - MEM_output_width_1_num_0 = mem_ctrl_strg_ub_vec_flat_accessor_output_f_b_0; - end - else if (mode == 2'h2) begin - MEM_output_width_1_num_0 = mem_ctrl_strg_ram_64_512_delay1_flat_ready_f_; - end -end -always_comb begin - MEM_output_width_1_num_1 = 1'h0; - if (mode == 2'h1) begin - MEM_output_width_1_num_1 = mem_ctrl_strg_ub_vec_flat_accessor_output_f_b_1; - end - else if (mode == 2'h2) begin - MEM_output_width_1_num_1 = mem_ctrl_strg_ram_64_512_delay1_flat_valid_out_f_; - end -end -always_comb begin - MEM_output_width_1_num_2 = 1'h0; - if (mode_excl == 1'h1) begin - MEM_output_width_1_num_2 = mem_ctrl_stencil_valid_flat_stencil_valid_f_; - end - else MEM_output_width_1_num_2 = 1'h0; -end -always_comb begin - memory_0_data_in_p0 = 64'h0; - memory_0_write_addr_p0 = 9'h0; - memory_0_write_enable_p0 = 1'h0; - memory_0_read_addr_p0 = 9'h0; - memory_0_read_enable_p0 = 1'h0; - if (|config_en) begin - memory_0_data_in_p0 = config_seq_wr_data; - memory_0_write_addr_p0 = config_seq_addr_out; - memory_0_write_enable_p0 = config_seq_wen_out; - memory_0_read_addr_p0 = config_seq_addr_out; - memory_0_read_enable_p0 = config_seq_ren_out; - end - else if (mode == 2'h0) begin - memory_0_data_in_p0 = mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_data_to_mem_lifted_lifted; - memory_0_write_addr_p0 = mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_addr_to_mem_lifted_lifted; - memory_0_write_enable_p0 = mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_wen_to_mem_lifted_lifted; - memory_0_read_addr_p0 = mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_addr_to_mem_lifted_lifted; - memory_0_read_enable_p0 = mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_ren_to_mem_lifted_lifted; - end - else if (mode == 2'h1) begin - memory_0_data_in_p0 = mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_data_to_strg_lifted; - memory_0_write_addr_p0 = mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_addr_out_lifted; - memory_0_write_enable_p0 = mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_wen_to_strg_lifted; - memory_0_read_addr_p0 = mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_addr_out_lifted; - memory_0_read_enable_p0 = mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_ren_to_strg_lifted; - end - else if (mode == 2'h2) begin - memory_0_data_in_p0 = mem_ctrl_strg_ram_64_512_delay1_flat_strg_ram_64_512_delay1_inst_data_to_strg_lifted; - memory_0_write_addr_p0 = mem_ctrl_strg_ram_64_512_delay1_flat_strg_ram_64_512_delay1_inst_addr_out_lifted; - memory_0_write_enable_p0 = mem_ctrl_strg_ram_64_512_delay1_flat_strg_ram_64_512_delay1_inst_wen_to_strg_lifted; - memory_0_read_addr_p0 = mem_ctrl_strg_ram_64_512_delay1_flat_strg_ram_64_512_delay1_inst_addr_out_lifted; - memory_0_read_enable_p0 = mem_ctrl_strg_ram_64_512_delay1_flat_strg_ram_64_512_delay1_inst_ren_to_strg_lifted; - end -end -always_comb begin - mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_data_from_mem_lifted_lifted = memory_0_data_out_p0; - mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_data_from_strg_lifted = memory_0_data_out_p0; - mem_ctrl_strg_ram_64_512_delay1_flat_strg_ram_64_512_delay1_inst_data_from_strg_lifted = memory_0_data_out_p0; - config_seq_rd_data_stg = memory_0_data_out_p0; -end -assign config_data_in_shrt = config_data_in[15:0]; -assign config_data_out[0] = 32'(config_data_out_shrt[0]); -assign config_data_out[1] = 32'(config_data_out_shrt[1]); -assign config_seq_clk_en = clk_en | (|config_en); -assign memory_0_clk_en = clk_en | (|config_en); -assign {mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_buffet_capacity_log_0, mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_buffet_capacity_log_1, mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_tile_en, mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_block_mode, mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_dense, mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_dim_size, mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_do_repeat, mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_inner_dim_offset, mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_lookup, mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_repeat_factor, mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_repeat_outer_inner_n, mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_root, mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_tile_en, mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_tile_en, mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_vector_reduce_mode, mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_write_scanner_block_mode, mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_write_scanner_compressed, mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_write_scanner_init_blank, mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_write_scanner_lowest_level, mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_write_scanner_stop_lvl, mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_write_scanner_tile_en} = CONFIG_SPACE[86:0]; -assign {mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_starting_addr, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_strides_0, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_strides_1, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_strides_2, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_starting_addr, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_strides_0, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_strides_1, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_strides_2, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_enable, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_starting_addr, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_0, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_1, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_2, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_enable, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_starting_addr, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_0, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_1, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_2, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_0_dimensionality, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_0_ranges_0, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_0_ranges_1, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_0_ranges_2, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_1_dimensionality, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_1_ranges_0, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_1_ranges_1, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_1_ranges_2, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_sram_shared_agg_read_sched_gen_0_agg_read_padding, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_sram_shared_agg_read_sched_gen_1_agg_read_padding, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_sram_shared_agg_sram_shared_addr_gen_0_starting_addr, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_sram_shared_agg_sram_shared_addr_gen_1_starting_addr, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_sram_shared_mode_0, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_sram_shared_mode_1, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_chain_chain_en, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_0_starting_addr, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_0, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_1, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_2, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_3, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_4, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_5, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_1_starting_addr, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_0, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_1, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_2, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_3, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_4, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_5, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_dimensionality, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_0, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_1, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_2, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_3, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_4, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_5, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_dimensionality, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_0, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_1, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_2, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_3, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_4, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_5, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_enable, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_delay, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_starting_addr, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_0, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_1, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_2, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_3, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_4, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_5, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_enable, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_delay, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_starting_addr, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_0, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_1, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_2, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_3, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_4, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_5, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_0_dimensionality, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_0, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_1, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_2, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_3, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_4, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_5, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_1_dimensionality, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_0, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_1, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_2, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_3, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_4, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_5, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_shared_tb_0, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_starting_addr, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_0, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_1, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_2, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_3, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_4, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_5, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_starting_addr, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_0, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_1, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_2, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_3, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_4, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_5, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_enable, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_delay, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_starting_addr, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_0, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_1, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_2, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_3, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_4, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_5, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_enable, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_delay, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_starting_addr, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_0, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_1, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_2, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_3, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_4, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_5, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_starting_addr, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_0, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_1, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_2, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_3, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_4, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_5, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_starting_addr, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_0, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_1, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_2, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_3, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_4, mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_5} = CONFIG_SPACE[1275:0]; -assign {mem_ctrl_stencil_valid_flat_stencil_valid_inst_loops_stencil_valid_dimensionality, mem_ctrl_stencil_valid_flat_stencil_valid_inst_loops_stencil_valid_ranges_0, mem_ctrl_stencil_valid_flat_stencil_valid_inst_loops_stencil_valid_ranges_1, mem_ctrl_stencil_valid_flat_stencil_valid_inst_loops_stencil_valid_ranges_2, mem_ctrl_stencil_valid_flat_stencil_valid_inst_loops_stencil_valid_ranges_3, mem_ctrl_stencil_valid_flat_stencil_valid_inst_loops_stencil_valid_ranges_4, mem_ctrl_stencil_valid_flat_stencil_valid_inst_loops_stencil_valid_ranges_5, mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_enable, mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_starting_addr, mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_0, mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_1, mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_2, mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_3, mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_4, mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_5} = CONFIG_SPACE[1458:1276]; -assign CONFIG_SPACE[31:0] = CONFIG_SPACE_0; -assign CONFIG_SPACE[63:32] = CONFIG_SPACE_1; -assign CONFIG_SPACE[95:64] = CONFIG_SPACE_2; -assign CONFIG_SPACE[127:96] = CONFIG_SPACE_3; -assign CONFIG_SPACE[159:128] = CONFIG_SPACE_4; -assign CONFIG_SPACE[191:160] = CONFIG_SPACE_5; -assign CONFIG_SPACE[223:192] = CONFIG_SPACE_6; -assign CONFIG_SPACE[255:224] = CONFIG_SPACE_7; -assign CONFIG_SPACE[287:256] = CONFIG_SPACE_8; -assign CONFIG_SPACE[319:288] = CONFIG_SPACE_9; -assign CONFIG_SPACE[351:320] = CONFIG_SPACE_10; -assign CONFIG_SPACE[383:352] = CONFIG_SPACE_11; -assign CONFIG_SPACE[415:384] = CONFIG_SPACE_12; -assign CONFIG_SPACE[447:416] = CONFIG_SPACE_13; -assign CONFIG_SPACE[479:448] = CONFIG_SPACE_14; -assign CONFIG_SPACE[511:480] = CONFIG_SPACE_15; -assign CONFIG_SPACE[543:512] = CONFIG_SPACE_16; -assign CONFIG_SPACE[575:544] = CONFIG_SPACE_17; -assign CONFIG_SPACE[607:576] = CONFIG_SPACE_18; -assign CONFIG_SPACE[639:608] = CONFIG_SPACE_19; -assign CONFIG_SPACE[671:640] = CONFIG_SPACE_20; -assign CONFIG_SPACE[703:672] = CONFIG_SPACE_21; -assign CONFIG_SPACE[735:704] = CONFIG_SPACE_22; -assign CONFIG_SPACE[767:736] = CONFIG_SPACE_23; -assign CONFIG_SPACE[799:768] = CONFIG_SPACE_24; -assign CONFIG_SPACE[831:800] = CONFIG_SPACE_25; -assign CONFIG_SPACE[863:832] = CONFIG_SPACE_26; -assign CONFIG_SPACE[895:864] = CONFIG_SPACE_27; -assign CONFIG_SPACE[927:896] = CONFIG_SPACE_28; -assign CONFIG_SPACE[959:928] = CONFIG_SPACE_29; -assign CONFIG_SPACE[991:960] = CONFIG_SPACE_30; -assign CONFIG_SPACE[1023:992] = CONFIG_SPACE_31; -assign CONFIG_SPACE[1055:1024] = CONFIG_SPACE_32; -assign CONFIG_SPACE[1087:1056] = CONFIG_SPACE_33; -assign CONFIG_SPACE[1119:1088] = CONFIG_SPACE_34; -assign CONFIG_SPACE[1151:1120] = CONFIG_SPACE_35; -assign CONFIG_SPACE[1183:1152] = CONFIG_SPACE_36; -assign CONFIG_SPACE[1215:1184] = CONFIG_SPACE_37; -assign CONFIG_SPACE[1247:1216] = CONFIG_SPACE_38; -assign CONFIG_SPACE[1279:1248] = CONFIG_SPACE_39; -assign CONFIG_SPACE[1311:1280] = CONFIG_SPACE_40; -assign CONFIG_SPACE[1343:1312] = CONFIG_SPACE_41; -assign CONFIG_SPACE[1375:1344] = CONFIG_SPACE_42; -assign CONFIG_SPACE[1407:1376] = CONFIG_SPACE_43; -assign CONFIG_SPACE[1439:1408] = CONFIG_SPACE_44; -assign CONFIG_SPACE[1458:1440] = CONFIG_SPACE_45; -fiber_access_16_flat mem_ctrl_fiber_access_16_flat ( - .clk(mem_ctrl_fiber_access_16_flat_clk), - .clk_en(clk_en), - .fiber_access_16_inst_buffet_buffet_capacity_log_0(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_buffet_capacity_log_0), - .fiber_access_16_inst_buffet_buffet_capacity_log_1(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_buffet_capacity_log_1), - .fiber_access_16_inst_buffet_data_from_mem_lifted_lifted(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_data_from_mem_lifted_lifted), - .fiber_access_16_inst_buffet_tile_en(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_tile_en), - .fiber_access_16_inst_read_scanner_block_mode(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_block_mode), - .fiber_access_16_inst_read_scanner_dense(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_dense), - .fiber_access_16_inst_read_scanner_dim_size(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_dim_size), - .fiber_access_16_inst_read_scanner_do_repeat(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_do_repeat), - .fiber_access_16_inst_read_scanner_inner_dim_offset(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_inner_dim_offset), - .fiber_access_16_inst_read_scanner_lookup(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_lookup), - .fiber_access_16_inst_read_scanner_repeat_factor(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_repeat_factor), - .fiber_access_16_inst_read_scanner_repeat_outer_inner_n(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_repeat_outer_inner_n), - .fiber_access_16_inst_read_scanner_root(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_root), - .fiber_access_16_inst_read_scanner_tile_en(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_read_scanner_tile_en), - .fiber_access_16_inst_tile_en(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_tile_en), - .fiber_access_16_inst_vector_reduce_mode(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_vector_reduce_mode), - .fiber_access_16_inst_write_scanner_block_mode(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_write_scanner_block_mode), - .fiber_access_16_inst_write_scanner_compressed(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_write_scanner_compressed), - .fiber_access_16_inst_write_scanner_init_blank(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_write_scanner_init_blank), - .fiber_access_16_inst_write_scanner_lowest_level(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_write_scanner_lowest_level), - .fiber_access_16_inst_write_scanner_stop_lvl(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_write_scanner_stop_lvl), - .fiber_access_16_inst_write_scanner_tile_en(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_write_scanner_tile_en), - .flush(flush), - .read_scanner_block_rd_out_ready_f_(output_width_17_num_0_fifo_in_ready), - .read_scanner_coord_out_ready_f_(output_width_17_num_1_fifo_in_ready), - .read_scanner_pos_out_ready_f_(output_width_17_num_2_fifo_in_ready), - .read_scanner_us_pos_in_f_(input_width_17_num_0_fifo_out), - .read_scanner_us_pos_in_valid_f_(input_width_17_num_0_fifo_out_valid), - .rst_n(rst_n), - .write_scanner_addr_in_f_(input_width_17_num_1_fifo_out), - .write_scanner_addr_in_valid_f_(input_width_17_num_1_fifo_out_valid), - .write_scanner_block_wr_in_f_(input_width_17_num_2_fifo_out), - .write_scanner_block_wr_in_valid_f_(input_width_17_num_2_fifo_out_valid), - .write_scanner_data_in_f_(input_width_17_num_3_fifo_out), - .write_scanner_data_in_valid_f_(input_width_17_num_3_fifo_out_valid), - .fiber_access_16_inst_buffet_addr_to_mem_lifted_lifted(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_addr_to_mem_lifted_lifted), - .fiber_access_16_inst_buffet_data_to_mem_lifted_lifted(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_data_to_mem_lifted_lifted), - .fiber_access_16_inst_buffet_ren_to_mem_lifted_lifted(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_ren_to_mem_lifted_lifted), - .fiber_access_16_inst_buffet_wen_to_mem_lifted_lifted(mem_ctrl_fiber_access_16_flat_fiber_access_16_inst_buffet_wen_to_mem_lifted_lifted), - .read_scanner_block_rd_out_f_(mem_ctrl_fiber_access_16_flat_read_scanner_block_rd_out_f_), - .read_scanner_block_rd_out_valid_f_(mem_ctrl_fiber_access_16_flat_read_scanner_block_rd_out_valid_f_), - .read_scanner_coord_out_f_(mem_ctrl_fiber_access_16_flat_read_scanner_coord_out_f_), - .read_scanner_coord_out_valid_f_(mem_ctrl_fiber_access_16_flat_read_scanner_coord_out_valid_f_), - .read_scanner_pos_out_f_(mem_ctrl_fiber_access_16_flat_read_scanner_pos_out_f_), - .read_scanner_pos_out_valid_f_(mem_ctrl_fiber_access_16_flat_read_scanner_pos_out_valid_f_), - .read_scanner_us_pos_in_ready_f_(mem_ctrl_fiber_access_16_flat_read_scanner_us_pos_in_ready_f_), - .write_scanner_addr_in_ready_f_(mem_ctrl_fiber_access_16_flat_write_scanner_addr_in_ready_f_), - .write_scanner_block_wr_in_ready_f_(mem_ctrl_fiber_access_16_flat_write_scanner_block_wr_in_ready_f_), - .write_scanner_data_in_ready_f_(mem_ctrl_fiber_access_16_flat_write_scanner_data_in_ready_f_) -); - -strg_ub_vec_flat mem_ctrl_strg_ub_vec_flat ( - .chain_data_in_f_0(MEM_input_width_17_num_0), - .chain_data_in_f_1(MEM_input_width_17_num_1), - .clk(mem_ctrl_strg_ub_vec_flat_clk), - .clk_en(clk_en), - .data_in_f_0(MEM_input_width_17_num_2), - .data_in_f_1(MEM_input_width_17_num_3), - .flush(flush), - .rst_n(rst_n), - .strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_starting_addr(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_starting_addr), - .strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_strides_0(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_strides_0), - .strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_strides_1(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_strides_1), - .strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_strides_2(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_strides_2), - .strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_starting_addr(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_starting_addr), - .strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_strides_0(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_strides_0), - .strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_strides_1(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_strides_1), - .strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_strides_2(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_strides_2), - .strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_enable(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_enable), - .strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_starting_addr(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_starting_addr), - .strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_0(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_0), - .strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_1(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_1), - .strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_2(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_2), - .strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_enable(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_enable), - .strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_starting_addr(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_starting_addr), - .strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_0(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_0), - .strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_1(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_1), - .strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_2(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_2), - .strg_ub_vec_inst_agg_only_loops_in2buf_0_dimensionality(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_0_dimensionality), - .strg_ub_vec_inst_agg_only_loops_in2buf_0_ranges_0(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_0_ranges_0), - .strg_ub_vec_inst_agg_only_loops_in2buf_0_ranges_1(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_0_ranges_1), - .strg_ub_vec_inst_agg_only_loops_in2buf_0_ranges_2(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_0_ranges_2), - .strg_ub_vec_inst_agg_only_loops_in2buf_1_dimensionality(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_1_dimensionality), - .strg_ub_vec_inst_agg_only_loops_in2buf_1_ranges_0(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_1_ranges_0), - .strg_ub_vec_inst_agg_only_loops_in2buf_1_ranges_1(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_1_ranges_1), - .strg_ub_vec_inst_agg_only_loops_in2buf_1_ranges_2(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_only_loops_in2buf_1_ranges_2), - .strg_ub_vec_inst_agg_sram_shared_agg_read_sched_gen_0_agg_read_padding(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_sram_shared_agg_read_sched_gen_0_agg_read_padding), - .strg_ub_vec_inst_agg_sram_shared_agg_read_sched_gen_1_agg_read_padding(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_sram_shared_agg_read_sched_gen_1_agg_read_padding), - .strg_ub_vec_inst_agg_sram_shared_agg_sram_shared_addr_gen_0_starting_addr(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_sram_shared_agg_sram_shared_addr_gen_0_starting_addr), - .strg_ub_vec_inst_agg_sram_shared_agg_sram_shared_addr_gen_1_starting_addr(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_sram_shared_agg_sram_shared_addr_gen_1_starting_addr), - .strg_ub_vec_inst_agg_sram_shared_mode_0(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_sram_shared_mode_0), - .strg_ub_vec_inst_agg_sram_shared_mode_1(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_agg_sram_shared_mode_1), - .strg_ub_vec_inst_chain_chain_en(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_chain_chain_en), - .strg_ub_vec_inst_data_from_strg_lifted(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_data_from_strg_lifted), - .strg_ub_vec_inst_sram_only_output_addr_gen_0_starting_addr(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_0_starting_addr), - .strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_0(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_0), - .strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_1(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_1), - .strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_2(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_2), - .strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_3(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_3), - .strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_4(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_4), - .strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_5(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_5), - .strg_ub_vec_inst_sram_only_output_addr_gen_1_starting_addr(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_1_starting_addr), - .strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_0(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_0), - .strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_1(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_1), - .strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_2(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_2), - .strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_3(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_3), - .strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_4(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_4), - .strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_5(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_5), - .strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_dimensionality(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_dimensionality), - .strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_0(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_0), - .strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_1(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_1), - .strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_2(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_2), - .strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_3(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_3), - .strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_4(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_4), - .strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_5(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_5), - .strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_dimensionality(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_dimensionality), - .strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_0(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_0), - .strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_1(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_1), - .strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_2(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_2), - .strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_3(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_3), - .strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_4(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_4), - .strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_5(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_5), - .strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_enable(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_enable), - .strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_delay(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_delay), - .strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_starting_addr(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_starting_addr), - .strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_0(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_0), - .strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_1(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_1), - .strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_2(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_2), - .strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_3(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_3), - .strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_4(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_4), - .strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_5(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_5), - .strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_enable(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_enable), - .strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_delay(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_delay), - .strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_starting_addr(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_starting_addr), - .strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_0(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_0), - .strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_1(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_1), - .strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_2(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_2), - .strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_3(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_3), - .strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_4(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_4), - .strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_5(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_5), - .strg_ub_vec_inst_tb_only_loops_buf2out_read_0_dimensionality(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_0_dimensionality), - .strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_0(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_0), - .strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_1(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_1), - .strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_2(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_2), - .strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_3(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_3), - .strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_4(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_4), - .strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_5(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_5), - .strg_ub_vec_inst_tb_only_loops_buf2out_read_1_dimensionality(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_1_dimensionality), - .strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_0(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_0), - .strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_1(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_1), - .strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_2(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_2), - .strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_3(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_3), - .strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_4(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_4), - .strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_5(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_5), - .strg_ub_vec_inst_tb_only_shared_tb_0(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_shared_tb_0), - .strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_starting_addr(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_starting_addr), - .strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_0(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_0), - .strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_1(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_1), - .strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_2(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_2), - .strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_3(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_3), - .strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_4(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_4), - .strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_5(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_5), - .strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_starting_addr(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_starting_addr), - .strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_0(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_0), - .strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_1(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_1), - .strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_2(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_2), - .strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_3(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_3), - .strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_4(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_4), - .strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_5(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_5), - .strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_enable(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_enable), - .strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_delay(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_delay), - .strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_starting_addr(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_starting_addr), - .strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_0(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_0), - .strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_1(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_1), - .strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_2(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_2), - .strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_3(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_3), - .strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_4(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_4), - .strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_5(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_5), - .strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_enable(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_enable), - .strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_delay(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_delay), - .strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_starting_addr(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_starting_addr), - .strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_0(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_0), - .strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_1(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_1), - .strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_2(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_2), - .strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_3(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_3), - .strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_4(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_4), - .strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_5(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_5), - .strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_starting_addr(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_starting_addr), - .strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_0(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_0), - .strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_1(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_1), - .strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_2(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_2), - .strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_3(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_3), - .strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_4(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_4), - .strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_5(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_5), - .strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_starting_addr(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_starting_addr), - .strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_0(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_0), - .strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_1(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_1), - .strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_2(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_2), - .strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_3(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_3), - .strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_4(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_4), - .strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_5(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_5), - .accessor_output_f_b_0(mem_ctrl_strg_ub_vec_flat_accessor_output_f_b_0), - .accessor_output_f_b_1(mem_ctrl_strg_ub_vec_flat_accessor_output_f_b_1), - .data_out_f_0(mem_ctrl_strg_ub_vec_flat_data_out_f_0), - .data_out_f_1(mem_ctrl_strg_ub_vec_flat_data_out_f_1), - .strg_ub_vec_inst_addr_out_lifted(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_addr_out_lifted), - .strg_ub_vec_inst_data_to_strg_lifted(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_data_to_strg_lifted), - .strg_ub_vec_inst_ren_to_strg_lifted(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_ren_to_strg_lifted), - .strg_ub_vec_inst_wen_to_strg_lifted(mem_ctrl_strg_ub_vec_flat_strg_ub_vec_inst_wen_to_strg_lifted) -); - -strg_ram_64_512_delay1_flat mem_ctrl_strg_ram_64_512_delay1_flat ( - .clk(mem_ctrl_strg_ram_64_512_delay1_flat_clk), - .clk_en(clk_en), - .data_in_f_(MEM_input_width_17_num_0), - .flush(flush), - .rd_addr_in_f_(MEM_input_width_17_num_1), - .ren_f_(MEM_input_width_1_num_0), - .rst_n(rst_n), - .strg_ram_64_512_delay1_inst_data_from_strg_lifted(mem_ctrl_strg_ram_64_512_delay1_flat_strg_ram_64_512_delay1_inst_data_from_strg_lifted), - .wen_f_(MEM_input_width_1_num_1), - .wr_addr_in_f_(MEM_input_width_17_num_2), - .data_out_f_(mem_ctrl_strg_ram_64_512_delay1_flat_data_out_f_), - .ready_f_(mem_ctrl_strg_ram_64_512_delay1_flat_ready_f_), - .strg_ram_64_512_delay1_inst_addr_out_lifted(mem_ctrl_strg_ram_64_512_delay1_flat_strg_ram_64_512_delay1_inst_addr_out_lifted), - .strg_ram_64_512_delay1_inst_data_to_strg_lifted(mem_ctrl_strg_ram_64_512_delay1_flat_strg_ram_64_512_delay1_inst_data_to_strg_lifted), - .strg_ram_64_512_delay1_inst_ren_to_strg_lifted(mem_ctrl_strg_ram_64_512_delay1_flat_strg_ram_64_512_delay1_inst_ren_to_strg_lifted), - .strg_ram_64_512_delay1_inst_wen_to_strg_lifted(mem_ctrl_strg_ram_64_512_delay1_flat_strg_ram_64_512_delay1_inst_wen_to_strg_lifted), - .valid_out_f_(mem_ctrl_strg_ram_64_512_delay1_flat_valid_out_f_) -); - -stencil_valid_flat mem_ctrl_stencil_valid_flat ( - .clk(mem_ctrl_stencil_valid_flat_clk), - .clk_en(clk_en), - .flush(flush), - .rst_n(rst_n), - .stencil_valid_inst_loops_stencil_valid_dimensionality(mem_ctrl_stencil_valid_flat_stencil_valid_inst_loops_stencil_valid_dimensionality), - .stencil_valid_inst_loops_stencil_valid_ranges_0(mem_ctrl_stencil_valid_flat_stencil_valid_inst_loops_stencil_valid_ranges_0), - .stencil_valid_inst_loops_stencil_valid_ranges_1(mem_ctrl_stencil_valid_flat_stencil_valid_inst_loops_stencil_valid_ranges_1), - .stencil_valid_inst_loops_stencil_valid_ranges_2(mem_ctrl_stencil_valid_flat_stencil_valid_inst_loops_stencil_valid_ranges_2), - .stencil_valid_inst_loops_stencil_valid_ranges_3(mem_ctrl_stencil_valid_flat_stencil_valid_inst_loops_stencil_valid_ranges_3), - .stencil_valid_inst_loops_stencil_valid_ranges_4(mem_ctrl_stencil_valid_flat_stencil_valid_inst_loops_stencil_valid_ranges_4), - .stencil_valid_inst_loops_stencil_valid_ranges_5(mem_ctrl_stencil_valid_flat_stencil_valid_inst_loops_stencil_valid_ranges_5), - .stencil_valid_inst_stencil_valid_sched_gen_enable(mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_enable), - .stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_starting_addr(mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_starting_addr), - .stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_0(mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_0), - .stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_1(mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_1), - .stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_2(mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_2), - .stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_3(mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_3), - .stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_4(mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_4), - .stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_5(mem_ctrl_stencil_valid_flat_stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_5), - .stencil_valid_f_(mem_ctrl_stencil_valid_flat_stencil_valid_f_) -); - -reg_fifo_depth_2_w_17_afd_2 input_width_17_num_0_input_fifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in(MEM_input_width_17_num_0), - .flush(flush), - .pop(input_width_17_num_0_fifo_out_ready), - .push(MEM_input_width_17_num_0_valid), - .rst_n(rst_n), - .data_out(input_width_17_num_0_fifo_out), - .empty(input_width_17_num_0_input_fifo_empty), - .full(input_width_17_num_0_input_fifo_full) -); - -reg_fifo_depth_2_w_17_afd_2 input_width_17_num_1_input_fifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in(MEM_input_width_17_num_1), - .flush(flush), - .pop(input_width_17_num_1_fifo_out_ready), - .push(MEM_input_width_17_num_1_valid), - .rst_n(rst_n), - .data_out(input_width_17_num_1_fifo_out), - .empty(input_width_17_num_1_input_fifo_empty), - .full(input_width_17_num_1_input_fifo_full) -); - -reg_fifo_depth_2_w_17_afd_2 input_width_17_num_2_input_fifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in(MEM_input_width_17_num_2), - .flush(flush), - .pop(input_width_17_num_2_fifo_out_ready), - .push(MEM_input_width_17_num_2_valid), - .rst_n(rst_n), - .data_out(input_width_17_num_2_fifo_out), - .empty(input_width_17_num_2_input_fifo_empty), - .full(input_width_17_num_2_input_fifo_full) -); - -reg_fifo_depth_2_w_17_afd_2 input_width_17_num_3_input_fifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in(MEM_input_width_17_num_3), - .flush(flush), - .pop(input_width_17_num_3_fifo_out_ready), - .push(MEM_input_width_17_num_3_valid), - .rst_n(rst_n), - .data_out(input_width_17_num_3_fifo_out), - .empty(input_width_17_num_3_input_fifo_empty), - .full(input_width_17_num_3_input_fifo_full) -); - -reg_fifo_depth_2_w_17_afd_2 output_width_17_num_0_output_fifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in(output_width_17_num_0_fifo_in), - .flush(flush), - .pop(MEM_output_width_17_num_0_ready), - .push(output_width_17_num_0_fifo_in_valid), - .rst_n(rst_n), - .data_out(output_width_17_num_0_output_fifo_data_out), - .empty(output_width_17_num_0_output_fifo_empty), - .full(output_width_17_num_0_output_fifo_full) -); - -reg_fifo_depth_2_w_17_afd_2 output_width_17_num_1_output_fifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in(output_width_17_num_1_fifo_in), - .flush(flush), - .pop(MEM_output_width_17_num_1_ready), - .push(output_width_17_num_1_fifo_in_valid), - .rst_n(rst_n), - .data_out(output_width_17_num_1_output_fifo_data_out), - .empty(output_width_17_num_1_output_fifo_empty), - .full(output_width_17_num_1_output_fifo_full) -); - -reg_fifo_depth_2_w_17_afd_2 output_width_17_num_2_output_fifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in(output_width_17_num_2_fifo_in), - .flush(flush), - .pop(MEM_output_width_17_num_2_ready), - .push(output_width_17_num_2_fifo_in_valid), - .rst_n(rst_n), - .data_out(output_width_17_num_2_output_fifo_data_out), - .empty(output_width_17_num_2_output_fifo_empty), - .full(output_width_17_num_2_output_fifo_full) -); - -sram_sp__0 memory_0 ( - .clk(gclk), - .clk_en(memory_0_clk_en), - .data_in_p0(memory_0_data_in_p0), - .flush(flush), - .read_addr_p0(memory_0_read_addr_p0), - .read_enable_p0(memory_0_read_enable_p0), - .write_addr_p0(memory_0_write_addr_p0), - .write_enable_p0(memory_0_write_enable_p0), - .data_out_p0(memory_0_data_out_p0) -); - -storage_config_seq_2_64_16 config_seq ( - .clk(gclk), - .clk_en(config_seq_clk_en), - .config_addr_in(config_addr_in), - .config_data_in(config_data_in_shrt), - .config_en(config_en), - .config_rd(config_read), - .config_wr(config_write), - .flush(flush), - .rd_data_stg(config_seq_rd_data_stg), - .rst_n(rst_n), - .addr_out(config_seq_addr_out), - .rd_data_out(config_data_out_shrt), - .ren_out(config_seq_ren_out), - .wen_out(config_seq_wen_out), - .wr_data(config_seq_wr_data) -); - -endmodule // MemCore_inner - -module MemCore_inner_W ( - input logic [31:0] CONFIG_SPACE_0, - input logic [31:0] CONFIG_SPACE_1, - input logic [31:0] CONFIG_SPACE_10, - input logic [31:0] CONFIG_SPACE_11, - input logic [31:0] CONFIG_SPACE_12, - input logic [31:0] CONFIG_SPACE_13, - input logic [31:0] CONFIG_SPACE_14, - input logic [31:0] CONFIG_SPACE_15, - input logic [31:0] CONFIG_SPACE_16, - input logic [31:0] CONFIG_SPACE_17, - input logic [31:0] CONFIG_SPACE_18, - input logic [31:0] CONFIG_SPACE_19, - input logic [31:0] CONFIG_SPACE_2, - input logic [31:0] CONFIG_SPACE_20, - input logic [31:0] CONFIG_SPACE_21, - input logic [31:0] CONFIG_SPACE_22, - input logic [31:0] CONFIG_SPACE_23, - input logic [31:0] CONFIG_SPACE_24, - input logic [31:0] CONFIG_SPACE_25, - input logic [31:0] CONFIG_SPACE_26, - input logic [31:0] CONFIG_SPACE_27, - input logic [31:0] CONFIG_SPACE_28, - input logic [31:0] CONFIG_SPACE_29, - input logic [31:0] CONFIG_SPACE_3, - input logic [31:0] CONFIG_SPACE_30, - input logic [31:0] CONFIG_SPACE_31, - input logic [31:0] CONFIG_SPACE_32, - input logic [31:0] CONFIG_SPACE_33, - input logic [31:0] CONFIG_SPACE_34, - input logic [31:0] CONFIG_SPACE_35, - input logic [31:0] CONFIG_SPACE_36, - input logic [31:0] CONFIG_SPACE_37, - input logic [31:0] CONFIG_SPACE_38, - input logic [31:0] CONFIG_SPACE_39, - input logic [31:0] CONFIG_SPACE_4, - input logic [31:0] CONFIG_SPACE_40, - input logic [31:0] CONFIG_SPACE_41, - input logic [31:0] CONFIG_SPACE_42, - input logic [31:0] CONFIG_SPACE_43, - input logic [31:0] CONFIG_SPACE_44, - input logic [18:0] CONFIG_SPACE_45, - input logic [31:0] CONFIG_SPACE_5, - input logic [31:0] CONFIG_SPACE_6, - input logic [31:0] CONFIG_SPACE_7, - input logic [31:0] CONFIG_SPACE_8, - input logic [31:0] CONFIG_SPACE_9, - input logic [0:0] [16:0] MEM_input_width_17_num_0, - input logic MEM_input_width_17_num_0_valid, - input logic [0:0] [16:0] MEM_input_width_17_num_1, - input logic MEM_input_width_17_num_1_valid, - input logic [0:0] [16:0] MEM_input_width_17_num_2, - input logic MEM_input_width_17_num_2_valid, - input logic [0:0] [16:0] MEM_input_width_17_num_3, - input logic MEM_input_width_17_num_3_valid, - input logic MEM_input_width_1_num_0, - input logic MEM_input_width_1_num_1, - input logic MEM_output_width_17_num_0_ready, - input logic MEM_output_width_17_num_1_ready, - input logic MEM_output_width_17_num_2_ready, - input logic clk, - input logic clk_en, - input logic [7:0] config_addr_in, - input logic [31:0] config_data_in, - input logic [1:0] config_en, - input logic config_read, - input logic config_write, - input logic flush, - input logic [1:0] mode, - input logic mode_excl, - input logic rst_n, - input logic tile_en, - output logic MEM_input_width_17_num_0_ready, - output logic MEM_input_width_17_num_1_ready, - output logic MEM_input_width_17_num_2_ready, - output logic MEM_input_width_17_num_3_ready, - output logic [0:0] [16:0] MEM_output_width_17_num_0, - output logic MEM_output_width_17_num_0_valid, - output logic [0:0] [16:0] MEM_output_width_17_num_1, - output logic MEM_output_width_17_num_1_valid, - output logic [0:0] [16:0] MEM_output_width_17_num_2, - output logic MEM_output_width_17_num_2_valid, - output logic MEM_output_width_1_num_0, - output logic MEM_output_width_1_num_1, - output logic MEM_output_width_1_num_2, - output logic [31:0] config_data_out_0, - output logic [31:0] config_data_out_1 -); - -logic [1:0][31:0] MemCore_inner_config_data_out; -assign config_data_out_0 = MemCore_inner_config_data_out[0]; -assign config_data_out_1 = MemCore_inner_config_data_out[1]; -MemCore_inner MemCore_inner ( - .CONFIG_SPACE_0(CONFIG_SPACE_0), - .CONFIG_SPACE_1(CONFIG_SPACE_1), - .CONFIG_SPACE_10(CONFIG_SPACE_10), - .CONFIG_SPACE_11(CONFIG_SPACE_11), - .CONFIG_SPACE_12(CONFIG_SPACE_12), - .CONFIG_SPACE_13(CONFIG_SPACE_13), - .CONFIG_SPACE_14(CONFIG_SPACE_14), - .CONFIG_SPACE_15(CONFIG_SPACE_15), - .CONFIG_SPACE_16(CONFIG_SPACE_16), - .CONFIG_SPACE_17(CONFIG_SPACE_17), - .CONFIG_SPACE_18(CONFIG_SPACE_18), - .CONFIG_SPACE_19(CONFIG_SPACE_19), - .CONFIG_SPACE_2(CONFIG_SPACE_2), - .CONFIG_SPACE_20(CONFIG_SPACE_20), - .CONFIG_SPACE_21(CONFIG_SPACE_21), - .CONFIG_SPACE_22(CONFIG_SPACE_22), - .CONFIG_SPACE_23(CONFIG_SPACE_23), - .CONFIG_SPACE_24(CONFIG_SPACE_24), - .CONFIG_SPACE_25(CONFIG_SPACE_25), - .CONFIG_SPACE_26(CONFIG_SPACE_26), - .CONFIG_SPACE_27(CONFIG_SPACE_27), - .CONFIG_SPACE_28(CONFIG_SPACE_28), - .CONFIG_SPACE_29(CONFIG_SPACE_29), - .CONFIG_SPACE_3(CONFIG_SPACE_3), - .CONFIG_SPACE_30(CONFIG_SPACE_30), - .CONFIG_SPACE_31(CONFIG_SPACE_31), - .CONFIG_SPACE_32(CONFIG_SPACE_32), - .CONFIG_SPACE_33(CONFIG_SPACE_33), - .CONFIG_SPACE_34(CONFIG_SPACE_34), - .CONFIG_SPACE_35(CONFIG_SPACE_35), - .CONFIG_SPACE_36(CONFIG_SPACE_36), - .CONFIG_SPACE_37(CONFIG_SPACE_37), - .CONFIG_SPACE_38(CONFIG_SPACE_38), - .CONFIG_SPACE_39(CONFIG_SPACE_39), - .CONFIG_SPACE_4(CONFIG_SPACE_4), - .CONFIG_SPACE_40(CONFIG_SPACE_40), - .CONFIG_SPACE_41(CONFIG_SPACE_41), - .CONFIG_SPACE_42(CONFIG_SPACE_42), - .CONFIG_SPACE_43(CONFIG_SPACE_43), - .CONFIG_SPACE_44(CONFIG_SPACE_44), - .CONFIG_SPACE_45(CONFIG_SPACE_45), - .CONFIG_SPACE_5(CONFIG_SPACE_5), - .CONFIG_SPACE_6(CONFIG_SPACE_6), - .CONFIG_SPACE_7(CONFIG_SPACE_7), - .CONFIG_SPACE_8(CONFIG_SPACE_8), - .CONFIG_SPACE_9(CONFIG_SPACE_9), - .MEM_input_width_17_num_0(MEM_input_width_17_num_0), - .MEM_input_width_17_num_0_valid(MEM_input_width_17_num_0_valid), - .MEM_input_width_17_num_1(MEM_input_width_17_num_1), - .MEM_input_width_17_num_1_valid(MEM_input_width_17_num_1_valid), - .MEM_input_width_17_num_2(MEM_input_width_17_num_2), - .MEM_input_width_17_num_2_valid(MEM_input_width_17_num_2_valid), - .MEM_input_width_17_num_3(MEM_input_width_17_num_3), - .MEM_input_width_17_num_3_valid(MEM_input_width_17_num_3_valid), - .MEM_input_width_1_num_0(MEM_input_width_1_num_0), - .MEM_input_width_1_num_1(MEM_input_width_1_num_1), - .MEM_output_width_17_num_0_ready(MEM_output_width_17_num_0_ready), - .MEM_output_width_17_num_1_ready(MEM_output_width_17_num_1_ready), - .MEM_output_width_17_num_2_ready(MEM_output_width_17_num_2_ready), - .clk(clk), - .clk_en(clk_en), - .config_addr_in(config_addr_in), - .config_data_in(config_data_in), - .config_en(config_en), - .config_read(config_read), - .config_write(config_write), - .flush(flush), - .mode(mode), - .mode_excl(mode_excl), - .rst_n(rst_n), - .tile_en(tile_en), - .MEM_input_width_17_num_0_ready(MEM_input_width_17_num_0_ready), - .MEM_input_width_17_num_1_ready(MEM_input_width_17_num_1_ready), - .MEM_input_width_17_num_2_ready(MEM_input_width_17_num_2_ready), - .MEM_input_width_17_num_3_ready(MEM_input_width_17_num_3_ready), - .MEM_output_width_17_num_0(MEM_output_width_17_num_0), - .MEM_output_width_17_num_0_valid(MEM_output_width_17_num_0_valid), - .MEM_output_width_17_num_1(MEM_output_width_17_num_1), - .MEM_output_width_17_num_1_valid(MEM_output_width_17_num_1_valid), - .MEM_output_width_17_num_2(MEM_output_width_17_num_2), - .MEM_output_width_17_num_2_valid(MEM_output_width_17_num_2_valid), - .MEM_output_width_1_num_0(MEM_output_width_1_num_0), - .MEM_output_width_1_num_1(MEM_output_width_1_num_1), - .MEM_output_width_1_num_2(MEM_output_width_1_num_2), - .config_data_out(MemCore_inner_config_data_out) -); - -endmodule // MemCore_inner_W - -module addr_gen_3_16 ( - input logic clk, - input logic clk_en, - input logic flush, - input logic [1:0] mux_sel, - input logic restart, - input logic rst_n, - input logic [15:0] starting_addr, - input logic step, - input logic [2:0] [15:0] strides, - output logic [15:0] addr_out -); - -logic [15:0] calc_addr; -logic [15:0] current_addr; -logic [15:0] strt_addr; -assign strt_addr = starting_addr; -assign addr_out = calc_addr; -assign calc_addr = current_addr; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - current_addr <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - current_addr <= strt_addr; - end - else if (step) begin - if (restart) begin - current_addr <= strt_addr; - end - else current_addr <= current_addr + strides[mux_sel]; - end - end -end -endmodule // addr_gen_3_16 - -module addr_gen_3_3 ( - input logic clk, - input logic clk_en, - input logic flush, - input logic [1:0] mux_sel, - input logic restart, - input logic rst_n, - input logic [2:0] starting_addr, - input logic step, - input logic [2:0] [2:0] strides, - output logic [2:0] addr_out -); - -logic [2:0] calc_addr; -logic [2:0] current_addr; -logic [2:0] strt_addr; -assign strt_addr = starting_addr; -assign addr_out = calc_addr; -assign calc_addr = current_addr; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - current_addr <= 3'h0; - end - else if (clk_en) begin - if (flush) begin - current_addr <= strt_addr; - end - else if (step) begin - if (restart) begin - current_addr <= strt_addr; - end - else current_addr <= current_addr + strides[mux_sel]; - end - end -end -endmodule // addr_gen_3_3 - -module addr_gen_6_16 ( - input logic clk, - input logic clk_en, - input logic flush, - input logic [2:0] mux_sel, - input logic restart, - input logic rst_n, - input logic [15:0] starting_addr, - input logic step, - input logic [5:0] [15:0] strides, - output logic [15:0] addr_out -); - -logic [15:0] calc_addr; -logic [15:0] current_addr; -logic [15:0] strt_addr; -assign strt_addr = starting_addr; -assign addr_out = calc_addr; -assign calc_addr = current_addr; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - current_addr <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - current_addr <= strt_addr; - end - else if (step) begin - if (restart) begin - current_addr <= strt_addr; - end - else current_addr <= current_addr + strides[mux_sel]; - end - end -end -endmodule // addr_gen_6_16 - -module addr_gen_6_16_delay_addr_10 ( - input logic clk, - input logic clk_en, - input logic [9:0] delay, - input logic flush, - input logic [2:0] mux_sel, - input logic restart, - input logic rst_n, - input logic [15:0] starting_addr, - input logic step, - input logic [5:0] [15:0] strides, - output logic [15:0] addr_out, - output logic [9:0] delay_out, - output logic [15:0] delayed_addr_out -); - -logic [15:0] calc_addr; -logic [15:0] current_addr; -logic [15:0] strt_addr; -assign delay_out = delay; -assign strt_addr = starting_addr; -assign addr_out = calc_addr; -assign calc_addr = current_addr; -assign delayed_addr_out = current_addr + 16'(delay); - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - current_addr <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - current_addr <= strt_addr; - end - else if (step) begin - if (restart) begin - current_addr <= strt_addr; - end - else current_addr <= current_addr + strides[mux_sel]; - end - end -end -endmodule // addr_gen_6_16_delay_addr_10 - -module addr_gen_6_4 ( - input logic clk, - input logic clk_en, - input logic flush, - input logic [2:0] mux_sel, - input logic restart, - input logic rst_n, - input logic [3:0] starting_addr, - input logic step, - input logic [5:0] [3:0] strides, - output logic [3:0] addr_out -); - -logic [3:0] calc_addr; -logic [3:0] current_addr; -logic [3:0] strt_addr; -assign strt_addr = starting_addr; -assign addr_out = calc_addr; -assign calc_addr = current_addr; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - current_addr <= 4'h0; - end - else if (clk_en) begin - if (flush) begin - current_addr <= strt_addr; - end - else if (step) begin - if (restart) begin - current_addr <= strt_addr; - end - else current_addr <= current_addr + strides[mux_sel]; - end - end -end -endmodule // addr_gen_6_4 - -module addr_gen_6_9 ( - input logic clk, - input logic clk_en, - input logic flush, - input logic [2:0] mux_sel, - input logic restart, - input logic rst_n, - input logic [8:0] starting_addr, - input logic step, - input logic [5:0] [8:0] strides, - output logic [8:0] addr_out -); - -logic [8:0] calc_addr; -logic [8:0] current_addr; -logic [8:0] strt_addr; -assign strt_addr = starting_addr; -assign addr_out = calc_addr; -assign calc_addr = current_addr; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - current_addr <= 9'h0; - end - else if (clk_en) begin - if (flush) begin - current_addr <= strt_addr; - end - else if (step) begin - if (restart) begin - current_addr <= strt_addr; - end - else current_addr <= current_addr + strides[mux_sel]; - end - end -end -endmodule // addr_gen_6_9 - -module agg_sram_shared_addr_gen ( - input logic clk, - input logic clk_en, - input logic flush, - input logic [1:0] mode, - input logic rst_n, - input logic [1:0] sram_read, - input logic [1:0] [8:0] sram_read_addr, - input logic [8:0] starting_addr, - input logic step, - output logic [8:0] addr_out -); - -logic [3:0][8:0] addr_fifo; -logic [8:0] addr_fifo_in; -logic [8:0] addr_fifo_out; -logic addr_fifo_wr_en; -logic [8:0] lin_addr_cnter; -logic [1:0] rd_ptr; -logic [1:0] wr_ptr; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - lin_addr_cnter <= 9'h0; - end - else if (clk_en) begin - if (flush) begin - lin_addr_cnter <= 9'h0; - end - else if (mode[1] == 1'h0) begin - if (step) begin - if (lin_addr_cnter == 9'h1FF) begin - lin_addr_cnter <= 9'h0; - end - else lin_addr_cnter <= lin_addr_cnter + 9'h1; - end - end - end -end -assign addr_fifo_wr_en = mode[0] ? sram_read[1]: sram_read[0]; -assign addr_fifo_in = mode[0] ? sram_read_addr[1]: sram_read_addr[0]; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - wr_ptr <= 2'h0; - rd_ptr <= 2'h0; - addr_fifo <= 36'h0; - addr_fifo_out <= 9'h0; - end - else if (clk_en) begin - if (flush) begin - wr_ptr <= 2'h0; - rd_ptr <= 2'h0; - addr_fifo <= 36'h0; - addr_fifo_out <= 9'h0; - end - else if (mode[1] == 1'h1) begin - if (addr_fifo_wr_en) begin - wr_ptr <= wr_ptr + 2'h1; - addr_fifo[wr_ptr] <= addr_fifo_in; - end - if (step) begin - rd_ptr <= rd_ptr + 2'h1; - end - addr_fifo_out <= addr_fifo[rd_ptr]; - end - end -end -assign addr_out = mode[1] ? addr_fifo_out: lin_addr_cnter + starting_addr; -endmodule // agg_sram_shared_addr_gen - -module agg_sram_shared_sched_gen ( - input logic [7:0] agg_read_padding, - input logic agg_write, - input logic [1:0] agg_write_addr_l2b, - input logic [2:0] agg_write_mux_sel, - input logic agg_write_restart, - input logic clk, - input logic clk_en, - input logic flush, - input logic [1:0] mode, - input logic rst_n, - input logic [1:0] sram_read_d, - output logic valid_output -); - -logic agg_write_4_r; -logic [7:0] pad_cnt; -logic pad_cnt_en; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - agg_write_4_r <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - agg_write_4_r <= 1'h0; - end - else if (mode[1] == 1'h0) begin - agg_write_4_r <= agg_write & (&agg_write_addr_l2b); - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - pad_cnt_en <= 1'h0; - pad_cnt <= 8'h0; - end - else if (clk_en) begin - if (flush) begin - pad_cnt_en <= 1'h0; - pad_cnt <= 8'h0; - end - else if ((mode[1] == 1'h0) & (agg_read_padding != 8'h0)) begin - if (agg_write & ((agg_write_mux_sel != 3'h0) | agg_write_restart)) begin - pad_cnt_en <= 1'h1; - end - else if (pad_cnt == agg_read_padding) begin - pad_cnt_en <= 1'h0; - end - if (pad_cnt == agg_read_padding) begin - pad_cnt <= 8'h0; - end - else if (pad_cnt_en | (agg_write & ((agg_write_mux_sel != 3'h0) | agg_write_restart))) begin - pad_cnt <= pad_cnt + 8'h1; - end - end - end -end -always_comb begin - if (mode[1] == 1'h0) begin - if (agg_read_padding != 8'h0) begin - valid_output = (agg_read_padding == pad_cnt) | agg_write_4_r; - end - else valid_output = agg_write_4_r; - end - else valid_output = mode[0] ? sram_read_d[1]: sram_read_d[0]; -end -endmodule // agg_sram_shared_sched_gen - -module arbiter_2_in_PRIO_algo ( - input logic clk, - input logic clk_en, - input logic flush, - input logic [1:0] request_in, - input logic resource_ready, - input logic rst_n, - output logic [1:0] grant_out -); - -logic [1:0] grant_line; -logic [1:0] grant_line_ready; -logic [1:0] grant_out_consolation; -logic [1:0] grant_out_priority; -logic tmp_done; -logic tmp_out_first; -always_comb begin - grant_line = request_in[1] ? 2'h2: 2'h1; -end -assign grant_line_ready[0] = grant_line[0] & resource_ready; -assign grant_out_priority[0] = grant_line_ready[0] & request_in[0]; -assign grant_line_ready[1] = grant_line[1] & resource_ready; -assign grant_out_priority[1] = grant_line_ready[1] & request_in[1]; -always_comb begin - tmp_done = 1'h0; - tmp_out_first = 1'h0; - if (~tmp_done) begin - if (request_in[0]) begin - tmp_out_first = 1'h0; - tmp_done = 1'h1; - end - end - if (~tmp_done) begin - if (request_in[1]) begin - tmp_out_first = 1'h1; - tmp_done = 1'h1; - end - end -end -assign grant_out_consolation[0] = resource_ready & request_in[0] & (tmp_out_first == 1'h0); -assign grant_out[0] = (|grant_out_priority) ? grant_out_priority[0]: grant_out_consolation[0]; -assign grant_out_consolation[1] = resource_ready & request_in[1] & (tmp_out_first == 1'h1); -assign grant_out[1] = (|grant_out_priority) ? grant_out_priority[1]: grant_out_consolation[1]; -endmodule // arbiter_2_in_PRIO_algo - -module arbiter_4_in_RR_algo ( - input logic clk, - input logic clk_en, - input logic flush, - input logic [3:0] request_in, - input logic resource_ready, - input logic rst_n, - output logic [3:0] grant_out -); - -logic [3:0] grant_line; -logic [3:0] grant_line_ready; -logic [3:0] grant_out_consolation; -logic [3:0] grant_out_priority; -logic tmp_done; -logic [1:0] tmp_out_first; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - grant_line <= 4'h1; - end - else if (clk_en) begin - if (flush) begin - grant_line <= 4'h1; - end - else grant_line <= {grant_line[2:0], grant_line[3]}; - end -end -assign grant_line_ready[0] = grant_line[0] & resource_ready; -assign grant_out_priority[0] = grant_line_ready[0] & request_in[0]; -assign grant_line_ready[1] = grant_line[1] & resource_ready; -assign grant_out_priority[1] = grant_line_ready[1] & request_in[1]; -assign grant_line_ready[2] = grant_line[2] & resource_ready; -assign grant_out_priority[2] = grant_line_ready[2] & request_in[2]; -assign grant_line_ready[3] = grant_line[3] & resource_ready; -assign grant_out_priority[3] = grant_line_ready[3] & request_in[3]; -always_comb begin - tmp_done = 1'h0; - tmp_out_first = 2'h0; - if (~tmp_done) begin - if (request_in[0]) begin - tmp_out_first = 2'h0; - tmp_done = 1'h1; - end - end - if (~tmp_done) begin - if (request_in[1]) begin - tmp_out_first = 2'h1; - tmp_done = 1'h1; - end - end - if (~tmp_done) begin - if (request_in[2]) begin - tmp_out_first = 2'h2; - tmp_done = 1'h1; - end - end - if (~tmp_done) begin - if (request_in[3]) begin - tmp_out_first = 2'h3; - tmp_done = 1'h1; - end - end -end -assign grant_out_consolation[0] = resource_ready & request_in[0] & (tmp_out_first == 2'h0); -assign grant_out[0] = (|grant_out_priority) ? grant_out_priority[0]: grant_out_consolation[0]; -assign grant_out_consolation[1] = resource_ready & request_in[1] & (tmp_out_first == 2'h1); -assign grant_out[1] = (|grant_out_priority) ? grant_out_priority[1]: grant_out_consolation[1]; -assign grant_out_consolation[2] = resource_ready & request_in[2] & (tmp_out_first == 2'h2); -assign grant_out[2] = (|grant_out_priority) ? grant_out_priority[2]: grant_out_consolation[2]; -assign grant_out_consolation[3] = resource_ready & request_in[3] & (tmp_out_first == 2'h3); -assign grant_out[3] = (|grant_out_priority) ? grant_out_priority[3]: grant_out_consolation[3]; -endmodule // arbiter_4_in_RR_algo - -module buffet_like_16 ( - input logic [1:0] [3:0] buffet_capacity_log, - input logic clk, - input logic clk_en, - input logic [3:0] [15:0] data_from_mem, - input logic flush, - input logic [0:0] [16:0] rd_addr_0, - input logic rd_addr_0_valid, - input logic [0:0] [16:0] rd_addr_1, - input logic rd_addr_1_valid, - input logic [0:0] [16:0] rd_op_0, - input logic rd_op_0_valid, - input logic [0:0] [16:0] rd_op_1, - input logic rd_op_1_valid, - input logic rd_rsp_data_0_ready, - input logic rd_rsp_data_1_ready, - input logic rst_n, - input logic tile_en, - input logic [0:0] [16:0] wr_ID, - input logic wr_ID_valid, - input logic [0:0] [16:0] wr_addr, - input logic wr_addr_valid, - input logic [0:0] [16:0] wr_data, - input logic wr_data_valid, - output logic [8:0] addr_to_mem, - output logic [3:0] [15:0] data_to_mem, - output logic rd_addr_0_ready, - output logic rd_addr_1_ready, - output logic rd_op_0_ready, - output logic rd_op_1_ready, - output logic [0:0] [16:0] rd_rsp_data_0, - output logic rd_rsp_data_0_valid, - output logic [0:0] [16:0] rd_rsp_data_1, - output logic rd_rsp_data_1_valid, - output logic ren_to_mem, - output logic wen_to_mem, - output logic wr_ID_ready, - output logic wr_addr_ready, - output logic wr_data_ready -); - -typedef enum logic[1:0] { - RD_PAUSE_0 = 2'h0, - RD_PAUSE_T_0 = 2'h1, - RD_START_0 = 2'h2 -} read_fsm_0_state; -typedef enum logic[1:0] { - RD_PAUSE_1 = 2'h0, - RD_PAUSE_T_1 = 2'h1, - RD_START_1 = 2'h2 -} read_fsm_1_state; -typedef enum logic[1:0] { - MODIFY_0 = 2'h0, - WRITING_0 = 2'h1, - WR_START_0 = 2'h2 -} write_fsm_0_state; -typedef enum logic[1:0] { - MODIFY_1 = 2'h0, - WRITING_1 = 2'h1, - WR_START_1 = 2'h2 -} write_fsm_1_state; -logic PREVIOUS_WR_OP; -logic [15:0] addr_to_mem_local; -logic any_sram_lock; -logic [3:0] base_rr; -logic [1:0][15:0] blk_base; -logic [1:0][15:0] blk_bounds; -logic [7:0] blk_count_0; -logic [7:0] blk_count_1; -logic [0:0][31:0] blk_fifo_0_data_in; -logic [0:0][31:0] blk_fifo_0_data_out; -logic blk_fifo_0_empty; -logic blk_fifo_0_full; -logic [0:0][31:0] blk_fifo_1_data_in; -logic [0:0][31:0] blk_fifo_1_data_out; -logic blk_fifo_1_empty; -logic blk_fifo_1_full; -logic [1:0] blk_full; -logic [1:0] blk_valid; -logic [1:0][15:0] buffet_base; -logic [1:0][15:0] buffet_capacity; -logic [1:0][15:0] buffet_capacity_mask; -logic [15:0] cached_read_word_addr_0; -logic [15:0] cached_read_word_addr_1; -logic [15:0] chosen_read_0; -logic [15:0] chosen_read_1; -logic clr_cached_read_0; -logic clr_cached_read_1; -logic clr_write_wide_word_0; -logic clr_write_wide_word_1; -logic [15:0] curr_base_0; -logic [15:0] curr_base_1; -logic [15:0] curr_base_pre_0; -logic [15:0] curr_base_pre_1; -logic [15:0] curr_bounds_0; -logic [15:0] curr_bounds_1; -logic [1:0][15:0] curr_capacity_pre; -logic [15:0] decode_ret_size_request_full_blk_bounds; -logic decode_sel_done_size_request_full_blk_bounds; -logic [1:0] en_curr_base; -logic [1:0] en_curr_bounds; -logic first_base_set_0_sticky; -logic first_base_set_0_was_high; -logic first_base_set_1_sticky; -logic first_base_set_1_was_high; -logic from_cached_read_0; -logic from_cached_read_1; -logic gclk; -logic joined_in_fifo; -logic [1:0] last_read_addr_0; -logic [1:0] last_read_addr_1; -logic [15:0] last_read_addr_wide_0; -logic [15:0] last_read_addr_wide_1; -logic [3:0] mem_acq; -logic [2:0] num_bits_valid_mask_0_sum; -logic [2:0] num_bits_valid_mask_1_sum; -logic [1:0] pop_blk; -logic pop_in_fifos; -logic [1:0] pop_in_full; -logic [1:0] push_blk; -logic rd_acq_0; -logic rd_acq_1; -logic rd_addr_fifo_0_empty; -logic rd_addr_fifo_0_full; -logic rd_addr_fifo_1_empty; -logic rd_addr_fifo_1_full; -logic [15:0] rd_addr_fifo_out_addr_0; -logic [15:0] rd_addr_fifo_out_addr_1; -logic rd_addr_fifo_pop_0; -logic rd_addr_fifo_pop_1; -logic rd_addr_fifo_valid_0; -logic rd_addr_fifo_valid_1; -logic rd_op_fifo_0_empty; -logic rd_op_fifo_0_full; -logic rd_op_fifo_1_empty; -logic rd_op_fifo_1_full; -logic [15:0] rd_op_fifo_out_op_0; -logic [15:0] rd_op_fifo_out_op_1; -logic rd_op_fifo_pop_0; -logic rd_op_fifo_pop_1; -logic rd_op_fifo_valid_0; -logic rd_op_fifo_valid_1; -logic rd_rsp_fifo_0_almost_full; -logic rd_rsp_fifo_0_empty; -logic rd_rsp_fifo_0_full; -logic [16:0] rd_rsp_fifo_0_in_data; -logic rd_rsp_fifo_0_push; -logic rd_rsp_fifo_1_almost_full; -logic rd_rsp_fifo_1_empty; -logic rd_rsp_fifo_1_full; -logic [16:0] rd_rsp_fifo_1_in_data; -logic rd_rsp_fifo_1_push; -logic [15:0] read_addr_delayed_0; -logic [15:0] read_addr_delayed_1; -logic read_d1; -logic read_from_sram_write_side_0; -logic read_from_sram_write_side_1; -read_fsm_0_state read_fsm_0_current_state; -read_fsm_0_state read_fsm_0_next_state; -read_fsm_1_state read_fsm_1_current_state; -read_fsm_1_state read_fsm_1_next_state; -logic read_joined_0; -logic read_joined_1; -logic read_joined_d1_0; -logic read_joined_d1_1; -logic read_pop_0; -logic read_pop_1; -logic [1:0] read_pop_full; -logic [3:0][15:0] read_wide_word_0; -logic [3:0][15:0] read_wide_word_1; -logic read_wide_word_valid_sticky_0_sticky; -logic read_wide_word_valid_sticky_0_was_high; -logic read_wide_word_valid_sticky_1_sticky; -logic read_wide_word_valid_sticky_1_was_high; -logic [1:0] ren_full; -logic ren_full_delayed_0; -logic ren_full_delayed_1; -logic rr_arbiter_resource_ready; -logic set_cached_read_0; -logic set_cached_read_1; -logic set_read_word_addr_0; -logic set_read_word_addr_1; -logic set_wide_word_addr_0; -logic set_wide_word_addr_1; -logic set_write_wide_word_0; -logic set_write_wide_word_1; -logic [1:0] size_request_full; -logic sram_lock_0; -logic sram_lock_1; -logic [15:0] tmp_addr_0; -logic [15:0] tmp_addr_1; -logic [15:0] tmp_rd_base; -logic [15:0] tmp_wr_base; -logic use_cached_read_0; -logic use_cached_read_1; -logic valid_from_mem; -logic [1:0] wen_full; -logic wr_ID_fifo_empty; -logic wr_ID_fifo_full; -logic [15:0] wr_ID_fifo_out_data; -logic wr_ID_fifo_pop; -logic wr_ID_fifo_valid; -logic wr_acq_0; -logic wr_acq_1; -logic wr_addr_fifo_empty; -logic wr_addr_fifo_full; -logic [15:0] wr_addr_fifo_out_data; -logic wr_addr_fifo_pop; -logic wr_addr_fifo_valid; -logic [0:0][16:0] wr_data_fifo_data_out; -logic wr_data_fifo_empty; -logic wr_data_fifo_full; -logic [15:0] wr_data_fifo_out_data; -logic wr_data_fifo_out_op; -logic wr_data_fifo_pop; -logic wr_data_fifo_valid; -write_fsm_0_state write_fsm_0_current_state; -write_fsm_0_state write_fsm_0_next_state; -write_fsm_1_state write_fsm_1_current_state; -write_fsm_1_state write_fsm_1_next_state; -logic write_full_word_0; -logic write_full_word_1; -logic write_to_sram_0; -logic write_to_sram_1; -logic [3:0][15:0] write_wide_word_comb_in_0; -logic [3:0][15:0] write_wide_word_comb_in_1; -logic [3:0][15:0] write_wide_word_comb_out_0; -logic [3:0][15:0] write_wide_word_comb_out_1; -logic [3:0] write_wide_word_mask_comb_0; -logic [3:0] write_wide_word_mask_comb_1; -logic [3:0] write_wide_word_mask_reg_in_0; -logic [3:0] write_wide_word_mask_reg_in_1; -logic [3:0] write_wide_word_mask_reg_out_0; -logic [3:0] write_wide_word_mask_reg_out_1; -logic [3:0] write_wide_word_mask_reg_strg_0; -logic [3:0] write_wide_word_mask_reg_strg_1; -logic [3:0][15:0] write_wide_word_modified_0; -logic [3:0][15:0] write_wide_word_modified_1; -logic [3:0][15:0] write_wide_word_reg_0; -logic [3:0][15:0] write_wide_word_reg_1; -logic [15:0] write_word_addr_reg_0; -logic [15:0] write_word_addr_reg_1; -logic write_word_addr_valid_sticky_0_sticky; -logic write_word_addr_valid_sticky_0_was_high; -logic write_word_addr_valid_sticky_1_sticky; -logic write_word_addr_valid_sticky_1_was_high; -assign gclk = clk & tile_en; -assign buffet_capacity_mask[0][0] = (buffet_capacity_log[0] > 4'h0) & (buffet_capacity_log[0] != 4'h0); -assign buffet_capacity_mask[0][1] = (buffet_capacity_log[0] > 4'h1) & (buffet_capacity_log[0] != 4'h0); -assign buffet_capacity_mask[0][2] = (buffet_capacity_log[0] > 4'h2) & (buffet_capacity_log[0] != 4'h0); -assign buffet_capacity_mask[0][3] = (buffet_capacity_log[0] > 4'h3) & (buffet_capacity_log[0] != 4'h0); -assign buffet_capacity_mask[0][4] = (buffet_capacity_log[0] > 4'h4) & (buffet_capacity_log[0] != 4'h0); -assign buffet_capacity_mask[0][5] = (buffet_capacity_log[0] > 4'h5) & (buffet_capacity_log[0] != 4'h0); -assign buffet_capacity_mask[0][6] = (buffet_capacity_log[0] > 4'h6) & (buffet_capacity_log[0] != 4'h0); -assign buffet_capacity_mask[0][7] = (buffet_capacity_log[0] > 4'h7) & (buffet_capacity_log[0] != 4'h0); -assign buffet_capacity_mask[0][8] = (buffet_capacity_log[0] > 4'h8) & (buffet_capacity_log[0] != 4'h0); -assign buffet_capacity_mask[0][9] = (buffet_capacity_log[0] > 4'h9) & (buffet_capacity_log[0] != 4'h0); -assign buffet_capacity_mask[0][10] = (buffet_capacity_log[0] > 4'hA) & (buffet_capacity_log[0] != 4'h0); -assign buffet_capacity_mask[0][11] = (buffet_capacity_log[0] > 4'hB) & (buffet_capacity_log[0] != 4'h0); -assign buffet_capacity_mask[0][12] = (buffet_capacity_log[0] > 4'hC) & (buffet_capacity_log[0] != 4'h0); -assign buffet_capacity_mask[0][13] = (buffet_capacity_log[0] > 4'hD) & (buffet_capacity_log[0] != 4'h0); -assign buffet_capacity_mask[0][14] = (buffet_capacity_log[0] > 4'hE) & (buffet_capacity_log[0] != 4'h0); -assign buffet_capacity_mask[0][15] = (buffet_capacity_log[0] > 4'hF) & (buffet_capacity_log[0] != 4'h0); -assign buffet_capacity_mask[1][0] = (buffet_capacity_log[1] > 4'h0) & (buffet_capacity_log[1] != 4'h0); -assign buffet_capacity_mask[1][1] = (buffet_capacity_log[1] > 4'h1) & (buffet_capacity_log[1] != 4'h0); -assign buffet_capacity_mask[1][2] = (buffet_capacity_log[1] > 4'h2) & (buffet_capacity_log[1] != 4'h0); -assign buffet_capacity_mask[1][3] = (buffet_capacity_log[1] > 4'h3) & (buffet_capacity_log[1] != 4'h0); -assign buffet_capacity_mask[1][4] = (buffet_capacity_log[1] > 4'h4) & (buffet_capacity_log[1] != 4'h0); -assign buffet_capacity_mask[1][5] = (buffet_capacity_log[1] > 4'h5) & (buffet_capacity_log[1] != 4'h0); -assign buffet_capacity_mask[1][6] = (buffet_capacity_log[1] > 4'h6) & (buffet_capacity_log[1] != 4'h0); -assign buffet_capacity_mask[1][7] = (buffet_capacity_log[1] > 4'h7) & (buffet_capacity_log[1] != 4'h0); -assign buffet_capacity_mask[1][8] = (buffet_capacity_log[1] > 4'h8) & (buffet_capacity_log[1] != 4'h0); -assign buffet_capacity_mask[1][9] = (buffet_capacity_log[1] > 4'h9) & (buffet_capacity_log[1] != 4'h0); -assign buffet_capacity_mask[1][10] = (buffet_capacity_log[1] > 4'hA) & (buffet_capacity_log[1] != 4'h0); -assign buffet_capacity_mask[1][11] = (buffet_capacity_log[1] > 4'hB) & (buffet_capacity_log[1] != 4'h0); -assign buffet_capacity_mask[1][12] = (buffet_capacity_log[1] > 4'hC) & (buffet_capacity_log[1] != 4'h0); -assign buffet_capacity_mask[1][13] = (buffet_capacity_log[1] > 4'hD) & (buffet_capacity_log[1] != 4'h0); -assign buffet_capacity_mask[1][14] = (buffet_capacity_log[1] > 4'hE) & (buffet_capacity_log[1] != 4'h0); -assign buffet_capacity_mask[1][15] = (buffet_capacity_log[1] > 4'hF) & (buffet_capacity_log[1] != 4'h0); -assign buffet_capacity[0] = (buffet_capacity_log[0] == 4'h0) ? 16'h0: 16'h1 << 16'(buffet_capacity_log[0] + - 4'h2); -assign buffet_capacity[1] = (buffet_capacity_log[1] == 4'h0) ? 16'h0: 16'h1 << 16'(buffet_capacity_log[1] + - 4'h2); -assign buffet_base[0] = 16'h0; -assign buffet_base[1] = 16'h100; -assign {wr_data_fifo_out_op, wr_data_fifo_out_data} = wr_data_fifo_data_out; -assign wr_data_ready = ~wr_data_fifo_full; -assign wr_data_fifo_valid = ~wr_data_fifo_empty; -assign wr_addr_ready = ~wr_addr_fifo_full; -assign wr_addr_fifo_valid = ~wr_addr_fifo_empty; -assign wr_ID_ready = ~wr_ID_fifo_full; -assign wr_ID_fifo_valid = ~wr_ID_fifo_empty; -assign rd_op_0_ready = ~rd_op_fifo_0_full; -assign rd_op_1_ready = ~rd_op_fifo_1_full; -assign rd_op_fifo_valid_0 = ~rd_op_fifo_0_empty; -assign rd_op_fifo_valid_1 = ~rd_op_fifo_1_empty; -assign rd_addr_0_ready = ~rd_addr_fifo_0_full; -assign rd_addr_1_ready = ~rd_addr_fifo_1_full; -assign rd_addr_fifo_valid_0 = ~rd_addr_fifo_0_empty; -assign rd_addr_fifo_valid_1 = ~rd_addr_fifo_1_empty; -assign read_joined_0 = rd_op_fifo_valid_0 & rd_addr_fifo_valid_0; -assign read_joined_1 = rd_op_fifo_valid_1 & rd_addr_fifo_valid_1; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - curr_bounds_0 <= 16'hFFFF; - end - else if (clk_en) begin - if (flush) begin - curr_bounds_0 <= 16'hFFFF; - end - else if (1'h0) begin - curr_bounds_0 <= 16'h0; - end - else if (en_curr_bounds[0]) begin - curr_bounds_0 <= wr_addr_fifo_out_data; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - curr_bounds_1 <= 16'hFFFF; - end - else if (clk_en) begin - if (flush) begin - curr_bounds_1 <= 16'hFFFF; - end - else if (1'h0) begin - curr_bounds_1 <= 16'h0; - end - else if (en_curr_bounds[1]) begin - curr_bounds_1 <= wr_addr_fifo_out_data; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - first_base_set_0_was_high <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - first_base_set_0_was_high <= 1'h0; - end - else if (1'h0) begin - first_base_set_0_was_high <= 1'h0; - end - else if (en_curr_base[0]) begin - first_base_set_0_was_high <= 1'h1; - end - end -end -assign first_base_set_0_sticky = first_base_set_0_was_high; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - first_base_set_1_was_high <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - first_base_set_1_was_high <= 1'h0; - end - else if (1'h0) begin - first_base_set_1_was_high <= 1'h0; - end - else if (en_curr_base[1]) begin - first_base_set_1_was_high <= 1'h1; - end - end -end -assign first_base_set_1_sticky = first_base_set_1_was_high; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - curr_base_0 <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - curr_base_0 <= 16'h0; - end - else if (1'h0) begin - curr_base_0 <= 16'h0; - end - else if (en_curr_base[0]) begin - curr_base_0 <= curr_base_pre_0; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - curr_base_1 <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - curr_base_1 <= 16'h0; - end - else if (1'h0) begin - curr_base_1 <= 16'h0; - end - else if (en_curr_base[1]) begin - curr_base_1 <= curr_base_pre_1; - end - end -end -assign curr_base_pre_0 = 1'h1 ? (curr_bounds_0 >> 16'h2) + 16'h1 + curr_base_0: 16'h0; -assign curr_base_pre_1 = 1'h1 ? (curr_bounds_1 >> 16'h2) + 16'h1 + curr_base_1: 16'h0; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - read_joined_d1_0 <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - read_joined_d1_0 <= 1'h0; - end - else if (1'h0) begin - read_joined_d1_0 <= 1'h0; - end - else if (1'h1) begin - read_joined_d1_0 <= read_joined_0 & read_pop_0; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - read_joined_d1_1 <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - read_joined_d1_1 <= 1'h0; - end - else if (1'h0) begin - read_joined_d1_1 <= 1'h0; - end - else if (1'h1) begin - read_joined_d1_1 <= read_joined_1 & read_pop_1; - end - end -end -assign rd_acq_0 = mem_acq[1] & ren_full[0]; -assign rd_acq_1 = mem_acq[3] & ren_full[1]; -assign wr_acq_0 = mem_acq[0] & write_to_sram_0; -assign wr_acq_1 = mem_acq[2] & write_to_sram_1; -assign addr_to_mem = addr_to_mem_local[8:0]; -assign tmp_addr_0 = ((16'(wr_addr_fifo_out_data[15:2]) + curr_base_0) & buffet_capacity_mask[0]) + - buffet_base[0]; -assign tmp_addr_1 = ((16'(wr_addr_fifo_out_data[15:2]) + curr_base_1) & buffet_capacity_mask[1]) + - buffet_base[1]; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - write_word_addr_reg_0 <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - write_word_addr_reg_0 <= 16'h0; - end - else if (1'h0) begin - write_word_addr_reg_0 <= 16'h0; - end - else if (set_wide_word_addr_0) begin - write_word_addr_reg_0 <= tmp_addr_0; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - write_word_addr_reg_1 <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - write_word_addr_reg_1 <= 16'h0; - end - else if (1'h0) begin - write_word_addr_reg_1 <= 16'h0; - end - else if (set_wide_word_addr_1) begin - write_word_addr_reg_1 <= tmp_addr_1; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - write_word_addr_valid_sticky_0_was_high <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - write_word_addr_valid_sticky_0_was_high <= 1'h0; - end - else if (1'h0) begin - write_word_addr_valid_sticky_0_was_high <= 1'h0; - end - else if (set_wide_word_addr_0) begin - write_word_addr_valid_sticky_0_was_high <= 1'h1; - end - end -end -assign write_word_addr_valid_sticky_0_sticky = write_word_addr_valid_sticky_0_was_high; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - write_word_addr_valid_sticky_1_was_high <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - write_word_addr_valid_sticky_1_was_high <= 1'h0; - end - else if (1'h0) begin - write_word_addr_valid_sticky_1_was_high <= 1'h0; - end - else if (set_wide_word_addr_1) begin - write_word_addr_valid_sticky_1_was_high <= 1'h1; - end - end -end -assign write_word_addr_valid_sticky_1_sticky = write_word_addr_valid_sticky_1_was_high; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - write_wide_word_mask_reg_strg_0 <= 4'h0; - end - else if (clk_en) begin - if (flush) begin - write_wide_word_mask_reg_strg_0 <= 4'h0; - end - else if (1'h0) begin - write_wide_word_mask_reg_strg_0 <= 4'h0; - end - else if (set_write_wide_word_0 | clr_write_wide_word_0) begin - write_wide_word_mask_reg_strg_0 <= write_wide_word_mask_reg_in_0; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - write_wide_word_mask_reg_strg_1 <= 4'h0; - end - else if (clk_en) begin - if (flush) begin - write_wide_word_mask_reg_strg_1 <= 4'h0; - end - else if (1'h0) begin - write_wide_word_mask_reg_strg_1 <= 4'h0; - end - else if (set_write_wide_word_1 | clr_write_wide_word_1) begin - write_wide_word_mask_reg_strg_1 <= write_wide_word_mask_reg_in_1; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - write_wide_word_reg_0 <= 64'h0; - end - else if (clk_en) begin - if (flush) begin - write_wide_word_reg_0 <= 64'h0; - end - else if (1'h0) begin - write_wide_word_reg_0 <= 64'h0; - end - else if (set_write_wide_word_0 | clr_write_wide_word_0) begin - write_wide_word_reg_0 <= write_wide_word_comb_in_0; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - write_wide_word_reg_1 <= 64'h0; - end - else if (clk_en) begin - if (flush) begin - write_wide_word_reg_1 <= 64'h0; - end - else if (1'h0) begin - write_wide_word_reg_1 <= 64'h0; - end - else if (set_write_wide_word_1 | clr_write_wide_word_1) begin - write_wide_word_reg_1 <= write_wide_word_comb_in_1; - end - end -end -assign write_wide_word_comb_out_0[0] = write_wide_word_mask_reg_out_0[0] ? write_wide_word_reg_0[0]: - wr_data_fifo_out_data; -assign write_wide_word_comb_out_0[1] = write_wide_word_mask_reg_out_0[1] ? write_wide_word_reg_0[1]: - wr_data_fifo_out_data; -assign write_wide_word_comb_out_0[2] = write_wide_word_mask_reg_out_0[2] ? write_wide_word_reg_0[2]: - wr_data_fifo_out_data; -assign write_wide_word_comb_out_0[3] = write_wide_word_mask_reg_out_0[3] ? write_wide_word_reg_0[3]: - wr_data_fifo_out_data; -assign write_wide_word_comb_out_1[0] = write_wide_word_mask_reg_out_1[0] ? write_wide_word_reg_1[0]: - wr_data_fifo_out_data; -assign write_wide_word_comb_out_1[1] = write_wide_word_mask_reg_out_1[1] ? write_wide_word_reg_1[1]: - wr_data_fifo_out_data; -assign write_wide_word_comb_out_1[2] = write_wide_word_mask_reg_out_1[2] ? write_wide_word_reg_1[2]: - wr_data_fifo_out_data; -assign write_wide_word_comb_out_1[3] = write_wide_word_mask_reg_out_1[3] ? write_wide_word_reg_1[3]: - wr_data_fifo_out_data; -assign write_wide_word_comb_in_0[0] = (write_wide_word_mask_reg_out_0[0] & (~clr_write_wide_word_0)) ? - write_wide_word_reg_0[0]: wr_data_fifo_out_data; -assign write_wide_word_comb_in_0[1] = (write_wide_word_mask_reg_out_0[1] & (~clr_write_wide_word_0)) ? - write_wide_word_reg_0[1]: wr_data_fifo_out_data; -assign write_wide_word_comb_in_0[2] = (write_wide_word_mask_reg_out_0[2] & (~clr_write_wide_word_0)) ? - write_wide_word_reg_0[2]: wr_data_fifo_out_data; -assign write_wide_word_comb_in_0[3] = (write_wide_word_mask_reg_out_0[3] & (~clr_write_wide_word_0)) ? - write_wide_word_reg_0[3]: wr_data_fifo_out_data; -assign write_wide_word_comb_in_1[0] = (write_wide_word_mask_reg_out_1[0] & (~clr_write_wide_word_1)) ? - write_wide_word_reg_1[0]: wr_data_fifo_out_data; -assign write_wide_word_comb_in_1[1] = (write_wide_word_mask_reg_out_1[1] & (~clr_write_wide_word_1)) ? - write_wide_word_reg_1[1]: wr_data_fifo_out_data; -assign write_wide_word_comb_in_1[2] = (write_wide_word_mask_reg_out_1[2] & (~clr_write_wide_word_1)) ? - write_wide_word_reg_1[2]: wr_data_fifo_out_data; -assign write_wide_word_comb_in_1[3] = (write_wide_word_mask_reg_out_1[3] & (~clr_write_wide_word_1)) ? - write_wide_word_reg_1[3]: wr_data_fifo_out_data; -assign write_wide_word_modified_0[0] = write_wide_word_mask_reg_out_0[0] ? write_wide_word_reg_0[0]: data_from_mem[0]; -assign write_wide_word_modified_0[1] = write_wide_word_mask_reg_out_0[1] ? write_wide_word_reg_0[1]: data_from_mem[1]; -assign write_wide_word_modified_0[2] = write_wide_word_mask_reg_out_0[2] ? write_wide_word_reg_0[2]: data_from_mem[2]; -assign write_wide_word_modified_0[3] = write_wide_word_mask_reg_out_0[3] ? write_wide_word_reg_0[3]: data_from_mem[3]; -assign write_wide_word_modified_1[0] = write_wide_word_mask_reg_out_1[0] ? write_wide_word_reg_1[0]: data_from_mem[0]; -assign write_wide_word_modified_1[1] = write_wide_word_mask_reg_out_1[1] ? write_wide_word_reg_1[1]: data_from_mem[1]; -assign write_wide_word_modified_1[2] = write_wide_word_mask_reg_out_1[2] ? write_wide_word_reg_1[2]: data_from_mem[2]; -assign write_wide_word_modified_1[3] = write_wide_word_mask_reg_out_1[3] ? write_wide_word_reg_1[3]: data_from_mem[3]; -assign write_wide_word_mask_reg_out_0 = write_wide_word_mask_reg_strg_0; -assign write_wide_word_mask_reg_out_1 = write_wide_word_mask_reg_strg_1; -assign write_wide_word_mask_comb_0 = write_wide_word_mask_reg_out_0 | 4'(2'(((tmp_addr_0 == write_word_addr_reg_0) & - joined_in_fifo & (1'h1 == wr_data_fifo_out_op) & (16'h0 == wr_ID_fifo_out_data)) - ? 1'h1: 1'h0) << wr_addr_fifo_out_data[1:0]); -assign write_wide_word_mask_comb_1 = write_wide_word_mask_reg_out_1 | 4'(2'(((tmp_addr_1 == write_word_addr_reg_1) & - joined_in_fifo & (1'h1 == wr_data_fifo_out_op) & (16'h1 == wr_ID_fifo_out_data)) - ? 1'h1: 1'h0) << wr_addr_fifo_out_data[1:0]); -assign write_wide_word_mask_reg_in_0 = (clr_write_wide_word_0 ? 4'h0: write_wide_word_mask_reg_out_0) | - (((((clr_write_wide_word_0 & (tmp_addr_0 != write_word_addr_reg_0)) | - ((tmp_addr_0 == write_word_addr_reg_0) & ((~write_full_word_0) | - (write_full_word_0 & (~mem_acq[0]))))) & (1'h1 == wr_data_fifo_out_op) & (16'h0 - == wr_ID_fifo_out_data)) ? {3'h0, joined_in_fifo}: 4'h0) << - 4'(wr_addr_fifo_out_data[1:0])); -assign write_wide_word_mask_reg_in_1 = (clr_write_wide_word_1 ? 4'h0: write_wide_word_mask_reg_out_1) | - (((((clr_write_wide_word_1 & (tmp_addr_1 != write_word_addr_reg_1)) | - ((tmp_addr_1 == write_word_addr_reg_1) & ((~write_full_word_1) | - (write_full_word_1 & (~mem_acq[2]))))) & (1'h1 == wr_data_fifo_out_op) & (16'h1 - == wr_ID_fifo_out_data)) ? {3'h0, joined_in_fifo}: 4'h0) << - 4'(wr_addr_fifo_out_data[1:0])); -always_comb begin - num_bits_valid_mask_0_sum = 3'h0; - num_bits_valid_mask_0_sum = num_bits_valid_mask_0_sum + 3'(write_wide_word_mask_comb_0[0]); - num_bits_valid_mask_0_sum = num_bits_valid_mask_0_sum + 3'(write_wide_word_mask_comb_0[1]); - num_bits_valid_mask_0_sum = num_bits_valid_mask_0_sum + 3'(write_wide_word_mask_comb_0[2]); - num_bits_valid_mask_0_sum = num_bits_valid_mask_0_sum + 3'(write_wide_word_mask_comb_0[3]); -end -always_comb begin - num_bits_valid_mask_1_sum = 3'h0; - num_bits_valid_mask_1_sum = num_bits_valid_mask_1_sum + 3'(write_wide_word_mask_comb_1[0]); - num_bits_valid_mask_1_sum = num_bits_valid_mask_1_sum + 3'(write_wide_word_mask_comb_1[1]); - num_bits_valid_mask_1_sum = num_bits_valid_mask_1_sum + 3'(write_wide_word_mask_comb_1[2]); - num_bits_valid_mask_1_sum = num_bits_valid_mask_1_sum + 3'(write_wide_word_mask_comb_1[3]); -end -assign write_full_word_0 = 3'h4 == num_bits_valid_mask_0_sum; -assign write_full_word_1 = 3'h4 == num_bits_valid_mask_1_sum; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - read_wide_word_0 <= 64'h0; - end - else if (clk_en) begin - if (flush) begin - read_wide_word_0 <= 64'h0; - end - else if (1'h0) begin - read_wide_word_0 <= 64'h0; - end - else if (set_cached_read_0) begin - read_wide_word_0 <= data_from_mem; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - read_wide_word_1 <= 64'h0; - end - else if (clk_en) begin - if (flush) begin - read_wide_word_1 <= 64'h0; - end - else if (1'h0) begin - read_wide_word_1 <= 64'h0; - end - else if (set_cached_read_1) begin - read_wide_word_1 <= data_from_mem; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - read_wide_word_valid_sticky_0_was_high <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - read_wide_word_valid_sticky_0_was_high <= 1'h0; - end - else if (clr_cached_read_0) begin - read_wide_word_valid_sticky_0_was_high <= 1'h0; - end - else if (set_cached_read_0) begin - read_wide_word_valid_sticky_0_was_high <= 1'h1; - end - end -end -assign read_wide_word_valid_sticky_0_sticky = set_cached_read_0 | read_wide_word_valid_sticky_0_was_high; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - read_wide_word_valid_sticky_1_was_high <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - read_wide_word_valid_sticky_1_was_high <= 1'h0; - end - else if (clr_cached_read_1) begin - read_wide_word_valid_sticky_1_was_high <= 1'h0; - end - else if (set_cached_read_1) begin - read_wide_word_valid_sticky_1_was_high <= 1'h1; - end - end -end -assign read_wide_word_valid_sticky_1_sticky = set_cached_read_1 | read_wide_word_valid_sticky_1_was_high; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - last_read_addr_0 <= 2'h0; - end - else if (clk_en) begin - if (flush) begin - last_read_addr_0 <= 2'h0; - end - else if (1'h0) begin - last_read_addr_0 <= 2'h0; - end - else if (rd_acq_0) begin - last_read_addr_0 <= rd_addr_fifo_out_addr_0[1:0]; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - last_read_addr_1 <= 2'h0; - end - else if (clk_en) begin - if (flush) begin - last_read_addr_1 <= 2'h0; - end - else if (1'h0) begin - last_read_addr_1 <= 2'h0; - end - else if (rd_acq_1) begin - last_read_addr_1 <= rd_addr_fifo_out_addr_1[1:0]; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - last_read_addr_wide_0 <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - last_read_addr_wide_0 <= 16'h0; - end - else if (1'h0) begin - last_read_addr_wide_0 <= 16'h0; - end - else if (rd_acq_0) begin - last_read_addr_wide_0 <= addr_to_mem_local; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - last_read_addr_wide_1 <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - last_read_addr_wide_1 <= 16'h0; - end - else if (1'h0) begin - last_read_addr_wide_1 <= 16'h0; - end - else if (rd_acq_1) begin - last_read_addr_wide_1 <= addr_to_mem_local; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - read_addr_delayed_0 <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - read_addr_delayed_0 <= 16'h0; - end - else if (1'h0) begin - read_addr_delayed_0 <= 16'h0; - end - else if (rd_addr_fifo_pop_0 & rd_addr_fifo_valid_0) begin - read_addr_delayed_0 <= rd_addr_fifo_out_addr_0; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - read_addr_delayed_1 <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - read_addr_delayed_1 <= 16'h0; - end - else if (1'h0) begin - read_addr_delayed_1 <= 16'h0; - end - else if (rd_addr_fifo_pop_1 & rd_addr_fifo_valid_1) begin - read_addr_delayed_1 <= rd_addr_fifo_out_addr_1; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - cached_read_word_addr_0 <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - cached_read_word_addr_0 <= 16'h0; - end - else if (1'h0) begin - cached_read_word_addr_0 <= 16'h0; - end - else if (set_read_word_addr_0) begin - cached_read_word_addr_0 <= addr_to_mem_local; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - cached_read_word_addr_1 <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - cached_read_word_addr_1 <= 16'h0; - end - else if (1'h0) begin - cached_read_word_addr_1 <= 16'h0; - end - else if (set_read_word_addr_1) begin - cached_read_word_addr_1 <= addr_to_mem_local; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - ren_full_delayed_0 <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - ren_full_delayed_0 <= 1'h0; - end - else if (1'h0) begin - ren_full_delayed_0 <= 1'h0; - end - else if (1'h1) begin - ren_full_delayed_0 <= ren_full[0] & rd_acq_0; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - ren_full_delayed_1 <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - ren_full_delayed_1 <= 1'h0; - end - else if (1'h0) begin - ren_full_delayed_1 <= 1'h0; - end - else if (1'h1) begin - ren_full_delayed_1 <= ren_full[1] & rd_acq_1; - end - end -end -assign use_cached_read_0 = read_wide_word_valid_sticky_0_sticky & ((((16'(rd_addr_fifo_out_addr_0[15:2]) + - blk_base[0]) & buffet_capacity_mask[0]) + buffet_base[0]) == - cached_read_word_addr_0) & (16'h1 == rd_op_fifo_out_op_0) & read_joined_0; -assign use_cached_read_1 = read_wide_word_valid_sticky_1_sticky & ((((16'(rd_addr_fifo_out_addr_1[15:2]) + - blk_base[1]) & buffet_capacity_mask[1]) + buffet_base[1]) == - cached_read_word_addr_1) & (16'h1 == rd_op_fifo_out_op_1) & read_joined_1; -assign from_cached_read_0 = read_wide_word_valid_sticky_0_sticky & ((((16'(read_addr_delayed_0[15:2]) + - blk_base[0]) & buffet_capacity_mask[0]) + buffet_base[0]) == - cached_read_word_addr_0) & read_joined_d1_0; -assign from_cached_read_1 = read_wide_word_valid_sticky_1_sticky & ((((16'(read_addr_delayed_1[15:2]) + - blk_base[1]) & buffet_capacity_mask[1]) + buffet_base[1]) == - cached_read_word_addr_1) & read_joined_d1_1; -assign chosen_read_0 = (~ren_full_delayed_0) ? read_wide_word_0[read_addr_delayed_0[1:0]]: - data_from_mem[last_read_addr_0[1:0]]; -assign chosen_read_1 = (~ren_full_delayed_1) ? read_wide_word_1[read_addr_delayed_1[1:0]]: - data_from_mem[last_read_addr_1[1:0]]; -assign any_sram_lock = |{sram_lock_0, sram_lock_1}; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - read_d1 <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - read_d1 <= 1'h0; - end - else if (1'h0) begin - read_d1 <= 1'h0; - end - else if (1'h1) begin - read_d1 <= |{mem_acq[1], mem_acq[3]}; - end - end -end -assign valid_from_mem = read_d1; -assign rd_rsp_data_0_valid = ~rd_rsp_fifo_0_empty; -assign rd_rsp_data_1_valid = ~rd_rsp_fifo_1_empty; -always_comb begin - decode_sel_done_size_request_full_blk_bounds = 1'h0; - decode_ret_size_request_full_blk_bounds = 16'h0; - if ((~decode_sel_done_size_request_full_blk_bounds) & size_request_full[0]) begin - decode_ret_size_request_full_blk_bounds = blk_bounds[0]; - decode_sel_done_size_request_full_blk_bounds = 1'h1; - end - if ((~decode_sel_done_size_request_full_blk_bounds) & size_request_full[1]) begin - decode_ret_size_request_full_blk_bounds = blk_bounds[1]; - decode_sel_done_size_request_full_blk_bounds = 1'h1; - end -end -assign rd_rsp_fifo_0_in_data[15:0] = (from_cached_read_0 & read_wide_word_valid_sticky_0_sticky) ? chosen_read_0: - decode_ret_size_request_full_blk_bounds + 16'h1; -assign rd_rsp_fifo_1_in_data[15:0] = (from_cached_read_1 & read_wide_word_valid_sticky_1_sticky) ? chosen_read_1: - decode_ret_size_request_full_blk_bounds + 16'h1; -assign rd_rsp_fifo_0_in_data[16] = from_cached_read_0 ? 1'h0: 1'h1; -assign rd_rsp_fifo_1_in_data[16] = from_cached_read_1 ? 1'h0: 1'h1; -assign rd_rsp_fifo_0_push = from_cached_read_0 | size_request_full[0]; -assign rd_rsp_fifo_1_push = from_cached_read_1 | size_request_full[1]; -assign joined_in_fifo = wr_data_fifo_valid & wr_addr_fifo_valid & wr_ID_fifo_valid; -assign {wr_addr_fifo_pop, wr_data_fifo_pop, wr_ID_fifo_pop} = {pop_in_fifos, pop_in_fifos, pop_in_fifos}; -assign pop_in_fifos = |pop_in_full; -assign {rd_op_fifo_pop_0, rd_addr_fifo_pop_0} = {read_pop_0, read_pop_0}; -assign {rd_op_fifo_pop_1, rd_addr_fifo_pop_1} = {read_pop_1, read_pop_1}; -assign read_pop_0 = read_pop_full[0]; -assign read_pop_1 = read_pop_full[1]; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - blk_count_0 <= 8'h0; - end - else if (clk_en) begin - if (flush) begin - blk_count_0 <= 8'h0; - end - else if (push_blk[0]) begin - blk_count_0 <= blk_count_0 + 8'h1; - end - else if (pop_blk[0]) begin - blk_count_0 <= blk_count_0 - 8'h1; - end - else blk_count_0 <= blk_count_0; - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - blk_count_1 <= 8'h0; - end - else if (clk_en) begin - if (flush) begin - blk_count_1 <= 8'h0; - end - else if (push_blk[1]) begin - blk_count_1 <= blk_count_1 + 8'h1; - end - else if (pop_blk[1]) begin - blk_count_1 <= blk_count_1 - 8'h1; - end - else blk_count_1 <= blk_count_1; - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - curr_capacity_pre[0] <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - curr_capacity_pre[0] <= 16'h0; - end - else if (push_blk[0] || pop_blk[0]) begin - curr_capacity_pre[0] <= (curr_capacity_pre[0] + (push_blk[0] ? blk_bounds[0]: 16'h0)) - (pop_blk[0] ? - blk_bounds[0]: 16'h0); - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - curr_capacity_pre[1] <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - curr_capacity_pre[1] <= 16'h0; - end - else if (push_blk[1] || pop_blk[1]) begin - curr_capacity_pre[1] <= (curr_capacity_pre[1] + (push_blk[1] ? blk_bounds[1]: 16'h0)) - (pop_blk[1] ? - blk_bounds[1]: 16'h0); - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - PREVIOUS_WR_OP <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - PREVIOUS_WR_OP <= 1'h0; - end - else if (1'h0) begin - PREVIOUS_WR_OP <= 1'h0; - end - else if (1'h1) begin - PREVIOUS_WR_OP <= wr_data_fifo_out_op; - end - end -end -assign blk_fifo_0_data_in = {curr_base_0, curr_bounds_0}; -assign {blk_base[0], blk_bounds[0]} = blk_fifo_0_data_out; -assign blk_full[0] = blk_fifo_0_full; -assign blk_valid[0] = ~blk_fifo_0_empty; -assign blk_fifo_1_data_in = {curr_base_1, curr_bounds_1}; -assign {blk_base[1], blk_bounds[1]} = blk_fifo_1_data_out; -assign blk_full[1] = blk_fifo_1_full; -assign blk_valid[1] = ~blk_fifo_1_empty; - -always_ff @(posedge clk, negedge rst_n) begin - if (!rst_n) begin - read_fsm_0_current_state <= RD_START_0; - end - else if (clk_en) begin - if (flush) begin - read_fsm_0_current_state <= RD_START_0; - end - else read_fsm_0_current_state <= read_fsm_0_next_state; - end -end -always_comb begin - read_fsm_0_next_state = read_fsm_0_current_state; - unique case (read_fsm_0_current_state) - RD_PAUSE_0: begin - if (push_blk[0]) begin - read_fsm_0_next_state = RD_PAUSE_T_0; - end - else read_fsm_0_next_state = RD_PAUSE_0; - end - RD_PAUSE_T_0: read_fsm_0_next_state = RD_START_0; - RD_START_0: begin - if ((blk_count_0 == 8'h0) & (rd_op_fifo_out_op_0 == 16'h0) & read_joined_0 & 1'h1) begin - read_fsm_0_next_state = RD_PAUSE_0; - end - else read_fsm_0_next_state = RD_START_0; - end - default: read_fsm_0_next_state = read_fsm_0_current_state; - endcase -end -always_comb begin - unique case (read_fsm_0_current_state) - RD_PAUSE_0: begin :read_fsm_0_RD_PAUSE_0_Output - pop_blk[0] = 1'h0; - ren_full[0] = 1'h0; - read_pop_full[0] = 1'h0; - size_request_full[0] = 1'h0; - set_cached_read_0 = 1'h0; - clr_cached_read_0 = 1'h0; - set_read_word_addr_0 = 1'h0; - end :read_fsm_0_RD_PAUSE_0_Output - RD_PAUSE_T_0: begin :read_fsm_0_RD_PAUSE_T_0_Output - pop_blk[0] = 1'h1; - ren_full[0] = 1'h0; - read_pop_full[0] = 1'h0; - size_request_full[0] = 1'h0; - set_cached_read_0 = 1'h0; - clr_cached_read_0 = 1'h0; - set_read_word_addr_0 = 1'h0; - end :read_fsm_0_RD_PAUSE_T_0_Output - RD_START_0: begin :read_fsm_0_RD_START_0_Output - pop_blk[0] = (rd_op_fifo_out_op_0 == 16'h0) & read_joined_0 & 1'h1 & (blk_count_0 > 8'h0); - ren_full[0] = (rd_op_fifo_out_op_0 == 16'h1) & (~use_cached_read_0) & read_joined_0 & - (~rd_rsp_fifo_0_almost_full) & blk_valid[0] & - (((16'(rd_addr_fifo_out_addr_0[15:2]) + blk_base[0] + buffet_base[0]) != - cached_read_word_addr_0) | (~read_wide_word_valid_sticky_0_sticky)) & 1'h1; - read_pop_full[0] = ((rd_op_fifo_out_op_0 == 16'h2) ? (~ren_full_delayed_0) & blk_valid[0]: - (rd_op_fifo_out_op_0 == 16'h1) ? (mem_acq[1] | use_cached_read_0) & - (~rd_rsp_fifo_0_full): 1'h1) & read_joined_0 & 1'h1; - size_request_full[0] = blk_valid[0] & (rd_op_fifo_out_op_0 == 16'h2) & read_joined_0 & 1'h1; - set_cached_read_0 = ren_full_delayed_0 & 1'h1; - clr_cached_read_0 = (rd_op_fifo_out_op_0 == 16'h0) & read_joined_0 & 1'h1; - set_read_word_addr_0 = ren_full[0] & mem_acq[1] & (addr_to_mem_local != cached_read_word_addr_0) & 1'h1; - end :read_fsm_0_RD_START_0_Output - default: begin :read_fsm_0_default_Output - pop_blk[0] = (rd_op_fifo_out_op_0 == 16'h0) & read_joined_0 & 1'h1 & (blk_count_0 > 8'h0); - ren_full[0] = (rd_op_fifo_out_op_0 == 16'h1) & (~use_cached_read_0) & read_joined_0 & - (~rd_rsp_fifo_0_almost_full) & blk_valid[0] & - (((16'(rd_addr_fifo_out_addr_0[15:2]) + blk_base[0] + buffet_base[0]) != - cached_read_word_addr_0) | (~read_wide_word_valid_sticky_0_sticky)) & 1'h1; - read_pop_full[0] = ((rd_op_fifo_out_op_0 == 16'h2) ? (~ren_full_delayed_0) & blk_valid[0]: - (rd_op_fifo_out_op_0 == 16'h1) ? (mem_acq[1] | use_cached_read_0) & - (~rd_rsp_fifo_0_full): 1'h1) & read_joined_0 & 1'h1; - size_request_full[0] = blk_valid[0] & (rd_op_fifo_out_op_0 == 16'h2) & read_joined_0 & 1'h1; - set_cached_read_0 = ren_full_delayed_0 & 1'h1; - clr_cached_read_0 = (rd_op_fifo_out_op_0 == 16'h0) & read_joined_0 & 1'h1; - set_read_word_addr_0 = ren_full[0] & mem_acq[1] & (addr_to_mem_local != cached_read_word_addr_0) & 1'h1; - end :read_fsm_0_default_Output - endcase -end - -always_ff @(posedge clk, negedge rst_n) begin - if (!rst_n) begin - read_fsm_1_current_state <= RD_START_1; - end - else if (clk_en) begin - if (flush) begin - read_fsm_1_current_state <= RD_START_1; - end - else read_fsm_1_current_state <= read_fsm_1_next_state; - end -end -always_comb begin - read_fsm_1_next_state = read_fsm_1_current_state; - unique case (read_fsm_1_current_state) - RD_PAUSE_1: begin - if (push_blk[1]) begin - read_fsm_1_next_state = RD_PAUSE_T_1; - end - else read_fsm_1_next_state = RD_PAUSE_1; - end - RD_PAUSE_T_1: read_fsm_1_next_state = RD_START_1; - RD_START_1: begin - if ((blk_count_1 == 8'h0) & (rd_op_fifo_out_op_1 == 16'h0) & read_joined_1 & 1'h1) begin - read_fsm_1_next_state = RD_PAUSE_1; - end - else read_fsm_1_next_state = RD_START_1; - end - default: read_fsm_1_next_state = read_fsm_1_current_state; - endcase -end -always_comb begin - unique case (read_fsm_1_current_state) - RD_PAUSE_1: begin :read_fsm_1_RD_PAUSE_1_Output - pop_blk[1] = 1'h0; - ren_full[1] = 1'h0; - read_pop_full[1] = 1'h0; - size_request_full[1] = 1'h0; - set_cached_read_1 = 1'h0; - clr_cached_read_1 = 1'h0; - set_read_word_addr_1 = 1'h0; - end :read_fsm_1_RD_PAUSE_1_Output - RD_PAUSE_T_1: begin :read_fsm_1_RD_PAUSE_T_1_Output - pop_blk[1] = 1'h1; - ren_full[1] = 1'h0; - read_pop_full[1] = 1'h0; - size_request_full[1] = 1'h0; - set_cached_read_1 = 1'h0; - clr_cached_read_1 = 1'h0; - set_read_word_addr_1 = 1'h0; - end :read_fsm_1_RD_PAUSE_T_1_Output - RD_START_1: begin :read_fsm_1_RD_START_1_Output - pop_blk[1] = (rd_op_fifo_out_op_1 == 16'h0) & read_joined_1 & 1'h1 & (blk_count_1 > 8'h0); - ren_full[1] = (rd_op_fifo_out_op_1 == 16'h1) & (~use_cached_read_1) & read_joined_1 & - (~rd_rsp_fifo_1_almost_full) & blk_valid[1] & - (((16'(rd_addr_fifo_out_addr_1[15:2]) + blk_base[1] + buffet_base[1]) != - cached_read_word_addr_1) | (~read_wide_word_valid_sticky_1_sticky)) & 1'h1; - read_pop_full[1] = ((rd_op_fifo_out_op_1 == 16'h2) ? (~ren_full_delayed_1) & blk_valid[1]: - (rd_op_fifo_out_op_1 == 16'h1) ? (mem_acq[3] | use_cached_read_1) & - (~rd_rsp_fifo_1_full): 1'h1) & read_joined_1 & 1'h1; - size_request_full[1] = blk_valid[1] & (rd_op_fifo_out_op_1 == 16'h2) & read_joined_1 & 1'h1; - set_cached_read_1 = ren_full_delayed_1 & 1'h1; - clr_cached_read_1 = (rd_op_fifo_out_op_1 == 16'h0) & read_joined_1 & 1'h1; - set_read_word_addr_1 = ren_full[1] & mem_acq[3] & (addr_to_mem_local != cached_read_word_addr_1) & 1'h1; - end :read_fsm_1_RD_START_1_Output - default: begin :read_fsm_1_default_Output - pop_blk[1] = (rd_op_fifo_out_op_1 == 16'h0) & read_joined_1 & 1'h1 & (blk_count_1 > 8'h0); - ren_full[1] = (rd_op_fifo_out_op_1 == 16'h1) & (~use_cached_read_1) & read_joined_1 & - (~rd_rsp_fifo_1_almost_full) & blk_valid[1] & - (((16'(rd_addr_fifo_out_addr_1[15:2]) + blk_base[1] + buffet_base[1]) != - cached_read_word_addr_1) | (~read_wide_word_valid_sticky_1_sticky)) & 1'h1; - read_pop_full[1] = ((rd_op_fifo_out_op_1 == 16'h2) ? (~ren_full_delayed_1) & blk_valid[1]: - (rd_op_fifo_out_op_1 == 16'h1) ? (mem_acq[3] | use_cached_read_1) & - (~rd_rsp_fifo_1_full): 1'h1) & read_joined_1 & 1'h1; - size_request_full[1] = blk_valid[1] & (rd_op_fifo_out_op_1 == 16'h2) & read_joined_1 & 1'h1; - set_cached_read_1 = ren_full_delayed_1 & 1'h1; - clr_cached_read_1 = (rd_op_fifo_out_op_1 == 16'h0) & read_joined_1 & 1'h1; - set_read_word_addr_1 = ren_full[1] & mem_acq[3] & (addr_to_mem_local != cached_read_word_addr_1) & 1'h1; - end :read_fsm_1_default_Output - endcase -end - -always_ff @(posedge clk, negedge rst_n) begin - if (!rst_n) begin - write_fsm_0_current_state <= WR_START_0; - end - else if (clk_en) begin - if (flush) begin - write_fsm_0_current_state <= WR_START_0; - end - else write_fsm_0_current_state <= write_fsm_0_next_state; - end -end -always_comb begin - write_fsm_0_next_state = write_fsm_0_current_state; - unique case (write_fsm_0_current_state) - MODIFY_0: begin - if (1'h1 == PREVIOUS_WR_OP) begin - write_fsm_0_next_state = WRITING_0; - end - else if ((1'h0 == PREVIOUS_WR_OP) & (~blk_full[0])) begin - write_fsm_0_next_state = WR_START_0; - end - else write_fsm_0_next_state = MODIFY_0; - end - WRITING_0: begin - if (joined_in_fifo & (wr_data_fifo_out_op == 1'h0) & (~blk_full[0]) & ((write_full_word_0 & mem_acq[0]) | (num_bits_valid_mask_0_sum == 3'h0)) & (16'h0 == wr_ID_fifo_out_data)) begin - write_fsm_0_next_state = WR_START_0; - end - else if (joined_in_fifo & (16'h0 == wr_ID_fifo_out_data) & mem_acq[0] & ((1'h0 == wr_data_fifo_out_op) | ((tmp_addr_0 != write_word_addr_reg_0) & write_word_addr_valid_sticky_0_sticky & (1'h1 == wr_data_fifo_out_op))) & (num_bits_valid_mask_0_sum > 3'h0) & (~write_full_word_0)) begin - write_fsm_0_next_state = MODIFY_0; - end - else write_fsm_0_next_state = WRITING_0; - end - WR_START_0: begin - if (joined_in_fifo & (wr_data_fifo_out_op == 1'h0) & (16'h0 == wr_ID_fifo_out_data) & tile_en) begin - write_fsm_0_next_state = WRITING_0; - end - else write_fsm_0_next_state = WR_START_0; - end - default: write_fsm_0_next_state = write_fsm_0_current_state; - endcase -end -always_comb begin - unique case (write_fsm_0_current_state) - MODIFY_0: begin :write_fsm_0_MODIFY_0_Output - push_blk[0] = (1'h0 == PREVIOUS_WR_OP) & (~blk_full[0]); - en_curr_base[0] = (1'h0 == PREVIOUS_WR_OP) & (~blk_full[0]); - en_curr_bounds[0] = 1'h0; - wen_full[0] = ~blk_full[0]; - pop_in_full[0] = ~blk_full[0]; - set_write_wide_word_0 = 1'h0; - clr_write_wide_word_0 = ~blk_full[0]; - write_to_sram_0 = ~blk_full[0]; - read_from_sram_write_side_0 = 1'h0; - set_wide_word_addr_0 = 1'h0; - sram_lock_0 = ~blk_full[0]; - end :write_fsm_0_MODIFY_0_Output - WRITING_0: begin :write_fsm_0_WRITING_0_Output - push_blk[0] = joined_in_fifo & (wr_data_fifo_out_op == 1'h0) & (~blk_full[0]) & - ((write_full_word_0 & mem_acq[0]) | (num_bits_valid_mask_0_sum == 3'h0)) & - (16'h0 == wr_ID_fifo_out_data); - en_curr_base[0] = joined_in_fifo & (wr_data_fifo_out_op == 1'h0) & (~blk_full[0]) & - ((write_full_word_0 & mem_acq[0]) | (num_bits_valid_mask_0_sum == 3'h0)) & - (16'h0 == wr_ID_fifo_out_data); - set_write_wide_word_0 = (tmp_addr_0 == write_word_addr_reg_0) & write_word_addr_valid_sticky_0_sticky & - joined_in_fifo & (wr_data_fifo_out_op == 1'h1) & (16'h0 == wr_ID_fifo_out_data); - en_curr_bounds[0] = (mem_acq[0] | set_write_wide_word_0) & joined_in_fifo & (wr_data_fifo_out_op == - 1'h1) & (16'h0 == wr_ID_fifo_out_data); - wen_full[0] = joined_in_fifo & (wr_data_fifo_out_op == 1'h1) & ((buffet_capacity[0] - - curr_capacity_pre[0]) > wr_addr_fifo_out_data) & (16'h0 == wr_ID_fifo_out_data); - clr_write_wide_word_0 = ((tmp_addr_0 != write_word_addr_reg_0) | - (~write_word_addr_valid_sticky_0_sticky) | ((tmp_addr_0 == - write_word_addr_reg_0) & write_word_addr_valid_sticky_0_sticky & - write_full_word_0)) & joined_in_fifo & (wr_data_fifo_out_op == 1'h1) & - mem_acq[0] & (16'h0 == wr_ID_fifo_out_data); - write_to_sram_0 = write_full_word_0 & joined_in_fifo & ((buffet_capacity[0] - - curr_capacity_pre[0]) > wr_addr_fifo_out_data) & (16'h0 == wr_ID_fifo_out_data); - set_wide_word_addr_0 = ((tmp_addr_0 != write_word_addr_reg_0) | - (~write_word_addr_valid_sticky_0_sticky)) & joined_in_fifo & - (wr_data_fifo_out_op == 1'h1) & ((|write_wide_word_mask_reg_out_0) ? mem_acq[0]: - 1'h1) & (16'h0 == wr_ID_fifo_out_data); - sram_lock_0 = 1'h0; - read_from_sram_write_side_0 = joined_in_fifo & (16'h0 == wr_ID_fifo_out_data) & (~any_sram_lock) & - ((buffet_capacity[0] - curr_capacity_pre[0]) > wr_addr_fifo_out_data) & ((1'h0 - == wr_data_fifo_out_op) | ((tmp_addr_0 != write_word_addr_reg_0) & - write_word_addr_valid_sticky_0_sticky & (1'h1 == wr_data_fifo_out_op))) & - (num_bits_valid_mask_0_sum > 3'h0) & (~write_full_word_0); - pop_in_full[0] = ((mem_acq[0] | set_write_wide_word_0) & joined_in_fifo & (wr_data_fifo_out_op == - 1'h1) & ((buffet_capacity[0] - curr_capacity_pre[0]) > wr_addr_fifo_out_data) & - (16'h0 == wr_ID_fifo_out_data)) | (joined_in_fifo & (wr_data_fifo_out_op == - 1'h0) & (~blk_full[0]) & ((write_full_word_0 & mem_acq[0]) | - (num_bits_valid_mask_0_sum == 3'h0)) & (16'h0 == wr_ID_fifo_out_data)); - end :write_fsm_0_WRITING_0_Output - WR_START_0: begin :write_fsm_0_WR_START_0_Output - push_blk[0] = 1'h0; - en_curr_base[0] = 1'h0; - en_curr_bounds[0] = 1'h0; - wen_full[0] = 1'h0; - pop_in_full[0] = (wr_data_fifo_out_op == 1'h0) & (16'h0 == wr_ID_fifo_out_data); - set_write_wide_word_0 = 1'h0; - clr_write_wide_word_0 = 1'h0; - write_to_sram_0 = 1'h0; - set_wide_word_addr_0 = 1'h0; - sram_lock_0 = 1'h0; - read_from_sram_write_side_0 = 1'h0; - end :write_fsm_0_WR_START_0_Output - default: begin :write_fsm_0_default_Output - push_blk[0] = 1'h0; - en_curr_base[0] = 1'h0; - en_curr_bounds[0] = 1'h0; - wen_full[0] = 1'h0; - pop_in_full[0] = (wr_data_fifo_out_op == 1'h0) & (16'h0 == wr_ID_fifo_out_data); - set_write_wide_word_0 = 1'h0; - clr_write_wide_word_0 = 1'h0; - write_to_sram_0 = 1'h0; - set_wide_word_addr_0 = 1'h0; - sram_lock_0 = 1'h0; - read_from_sram_write_side_0 = 1'h0; - end :write_fsm_0_default_Output - endcase -end - -always_ff @(posedge clk, negedge rst_n) begin - if (!rst_n) begin - write_fsm_1_current_state <= WR_START_1; - end - else if (clk_en) begin - if (flush) begin - write_fsm_1_current_state <= WR_START_1; - end - else write_fsm_1_current_state <= write_fsm_1_next_state; - end -end -always_comb begin - write_fsm_1_next_state = write_fsm_1_current_state; - unique case (write_fsm_1_current_state) - MODIFY_1: begin - if (1'h1 == PREVIOUS_WR_OP) begin - write_fsm_1_next_state = WRITING_1; - end - else if ((1'h0 == PREVIOUS_WR_OP) & (~blk_full[1])) begin - write_fsm_1_next_state = WR_START_1; - end - else write_fsm_1_next_state = MODIFY_1; - end - WRITING_1: begin - if (joined_in_fifo & (wr_data_fifo_out_op == 1'h0) & (~blk_full[1]) & ((write_full_word_1 & mem_acq[2]) | (num_bits_valid_mask_1_sum == 3'h0)) & (16'h1 == wr_ID_fifo_out_data)) begin - write_fsm_1_next_state = WR_START_1; - end - else if (joined_in_fifo & (16'h1 == wr_ID_fifo_out_data) & mem_acq[2] & ((1'h0 == wr_data_fifo_out_op) | ((tmp_addr_1 != write_word_addr_reg_1) & write_word_addr_valid_sticky_1_sticky & (1'h1 == wr_data_fifo_out_op))) & (num_bits_valid_mask_1_sum > 3'h0) & (~write_full_word_1)) begin - write_fsm_1_next_state = MODIFY_1; - end - else write_fsm_1_next_state = WRITING_1; - end - WR_START_1: begin - if (joined_in_fifo & (wr_data_fifo_out_op == 1'h0) & (16'h1 == wr_ID_fifo_out_data) & tile_en) begin - write_fsm_1_next_state = WRITING_1; - end - else write_fsm_1_next_state = WR_START_1; - end - default: write_fsm_1_next_state = write_fsm_1_current_state; - endcase -end -always_comb begin - unique case (write_fsm_1_current_state) - MODIFY_1: begin :write_fsm_1_MODIFY_1_Output - push_blk[1] = (1'h0 == PREVIOUS_WR_OP) & (~blk_full[1]); - en_curr_base[1] = (1'h0 == PREVIOUS_WR_OP) & (~blk_full[1]); - en_curr_bounds[1] = 1'h0; - wen_full[1] = ~blk_full[1]; - pop_in_full[1] = ~blk_full[1]; - set_write_wide_word_1 = 1'h0; - clr_write_wide_word_1 = ~blk_full[1]; - write_to_sram_1 = ~blk_full[1]; - read_from_sram_write_side_1 = 1'h0; - set_wide_word_addr_1 = 1'h0; - sram_lock_1 = ~blk_full[1]; - end :write_fsm_1_MODIFY_1_Output - WRITING_1: begin :write_fsm_1_WRITING_1_Output - push_blk[1] = joined_in_fifo & (wr_data_fifo_out_op == 1'h0) & (~blk_full[1]) & - ((write_full_word_1 & mem_acq[2]) | (num_bits_valid_mask_1_sum == 3'h0)) & - (16'h1 == wr_ID_fifo_out_data); - en_curr_base[1] = joined_in_fifo & (wr_data_fifo_out_op == 1'h0) & (~blk_full[1]) & - ((write_full_word_1 & mem_acq[2]) | (num_bits_valid_mask_1_sum == 3'h0)) & - (16'h1 == wr_ID_fifo_out_data); - set_write_wide_word_1 = (tmp_addr_1 == write_word_addr_reg_1) & write_word_addr_valid_sticky_1_sticky & - joined_in_fifo & (wr_data_fifo_out_op == 1'h1) & (16'h1 == wr_ID_fifo_out_data); - en_curr_bounds[1] = (mem_acq[2] | set_write_wide_word_1) & joined_in_fifo & (wr_data_fifo_out_op == - 1'h1) & (16'h1 == wr_ID_fifo_out_data); - wen_full[1] = joined_in_fifo & (wr_data_fifo_out_op == 1'h1) & ((buffet_capacity[1] - - curr_capacity_pre[1]) > wr_addr_fifo_out_data) & (16'h1 == wr_ID_fifo_out_data); - clr_write_wide_word_1 = ((tmp_addr_1 != write_word_addr_reg_1) | - (~write_word_addr_valid_sticky_1_sticky) | ((tmp_addr_1 == - write_word_addr_reg_1) & write_word_addr_valid_sticky_1_sticky & - write_full_word_1)) & joined_in_fifo & (wr_data_fifo_out_op == 1'h1) & - mem_acq[2] & (16'h1 == wr_ID_fifo_out_data); - write_to_sram_1 = write_full_word_1 & joined_in_fifo & ((buffet_capacity[1] - - curr_capacity_pre[1]) > wr_addr_fifo_out_data) & (16'h1 == wr_ID_fifo_out_data); - set_wide_word_addr_1 = ((tmp_addr_1 != write_word_addr_reg_1) | - (~write_word_addr_valid_sticky_1_sticky)) & joined_in_fifo & - (wr_data_fifo_out_op == 1'h1) & ((|write_wide_word_mask_reg_out_1) ? mem_acq[2]: - 1'h1) & (16'h1 == wr_ID_fifo_out_data); - sram_lock_1 = 1'h0; - read_from_sram_write_side_1 = joined_in_fifo & (16'h1 == wr_ID_fifo_out_data) & (~any_sram_lock) & - ((buffet_capacity[1] - curr_capacity_pre[1]) > wr_addr_fifo_out_data) & ((1'h0 - == wr_data_fifo_out_op) | ((tmp_addr_1 != write_word_addr_reg_1) & - write_word_addr_valid_sticky_1_sticky & (1'h1 == wr_data_fifo_out_op))) & - (num_bits_valid_mask_1_sum > 3'h0) & (~write_full_word_1); - pop_in_full[1] = ((mem_acq[2] | set_write_wide_word_1) & joined_in_fifo & (wr_data_fifo_out_op == - 1'h1) & ((buffet_capacity[1] - curr_capacity_pre[1]) > wr_addr_fifo_out_data) & - (16'h1 == wr_ID_fifo_out_data)) | (joined_in_fifo & (wr_data_fifo_out_op == - 1'h0) & (~blk_full[1]) & ((write_full_word_1 & mem_acq[2]) | - (num_bits_valid_mask_1_sum == 3'h0)) & (16'h1 == wr_ID_fifo_out_data)); - end :write_fsm_1_WRITING_1_Output - WR_START_1: begin :write_fsm_1_WR_START_1_Output - push_blk[1] = 1'h0; - en_curr_base[1] = 1'h0; - en_curr_bounds[1] = 1'h0; - wen_full[1] = 1'h0; - pop_in_full[1] = (wr_data_fifo_out_op == 1'h0) & (16'h1 == wr_ID_fifo_out_data); - set_write_wide_word_1 = 1'h0; - clr_write_wide_word_1 = 1'h0; - write_to_sram_1 = 1'h0; - set_wide_word_addr_1 = 1'h0; - sram_lock_1 = 1'h0; - read_from_sram_write_side_1 = 1'h0; - end :write_fsm_1_WR_START_1_Output - default: begin :write_fsm_1_default_Output - push_blk[1] = 1'h0; - en_curr_base[1] = 1'h0; - en_curr_bounds[1] = 1'h0; - wen_full[1] = 1'h0; - pop_in_full[1] = (wr_data_fifo_out_op == 1'h0) & (16'h1 == wr_ID_fifo_out_data); - set_write_wide_word_1 = 1'h0; - clr_write_wide_word_1 = 1'h0; - write_to_sram_1 = 1'h0; - set_wide_word_addr_1 = 1'h0; - sram_lock_1 = 1'h0; - read_from_sram_write_side_1 = 1'h0; - end :write_fsm_1_default_Output - endcase -end -assign base_rr = {ren_full[1], write_to_sram_1 | read_from_sram_write_side_1, {ren_full[0], - write_to_sram_0 | read_from_sram_write_side_0}}; -assign rr_arbiter_resource_ready = ~any_sram_lock; -assign ren_to_mem = (|{mem_acq[1] & ren_full[0], mem_acq[3] & ren_full[1]}) | - (|{read_from_sram_write_side_0, read_from_sram_write_side_1}); -assign wen_to_mem = |({mem_acq[0] & write_to_sram_0, mem_acq[2] & write_to_sram_1} | {sram_lock_0, - sram_lock_1}); -assign tmp_wr_base = (mem_acq[2] & write_to_sram_1) ? curr_base_1 + buffet_base[1]: (mem_acq[0] & - write_to_sram_0) ? curr_base_0 + buffet_base[0]: 16'h0; -assign tmp_rd_base = (mem_acq[3] & ren_full[1]) ? blk_base[1] + buffet_base[1]: (mem_acq[1] & - ren_full[0]) ? blk_base[0] + buffet_base[0]: 16'h0; -assign data_to_mem = (mem_acq[0] & write_to_sram_0) ? write_wide_word_comb_out_0: (mem_acq[2] & - write_to_sram_1) ? write_wide_word_comb_out_1: sram_lock_0 ? - write_wide_word_modified_0: sram_lock_1 ? write_wide_word_modified_1: 64'h0; -assign addr_to_mem_local = (wen_to_mem | mem_acq[0] | mem_acq[2]) ? (mem_acq[0] | sram_lock_0) ? - write_word_addr_reg_0: write_word_addr_reg_1: (mem_acq[1] & ren_full[0]) ? - ((16'(rd_addr_fifo_out_addr_0[15:2]) + blk_base[0]) & buffet_capacity_mask[0]) + - buffet_base[0]: ((16'(rd_addr_fifo_out_addr_1[15:2]) + blk_base[1]) & - buffet_capacity_mask[1]) + buffet_base[1]; -reg_fifo_depth_2_w_17_afd_2 wr_data_fifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in(wr_data), - .flush(flush), - .pop(wr_data_fifo_pop), - .push(wr_data_valid), - .rst_n(rst_n), - .data_out(wr_data_fifo_data_out), - .empty(wr_data_fifo_empty), - .full(wr_data_fifo_full) -); - -reg_fifo_depth_2_w_16_afd_2 wr_addr_fifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in(wr_addr[0][15:0]), - .flush(flush), - .pop(wr_addr_fifo_pop), - .push(wr_addr_valid), - .rst_n(rst_n), - .data_out(wr_addr_fifo_out_data), - .empty(wr_addr_fifo_empty), - .full(wr_addr_fifo_full) -); - -reg_fifo_depth_2_w_16_afd_2 wr_ID_fifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in(wr_ID[0][15:0]), - .flush(flush), - .pop(wr_ID_fifo_pop), - .push(wr_ID_valid), - .rst_n(rst_n), - .data_out(wr_ID_fifo_out_data), - .empty(wr_ID_fifo_empty), - .full(wr_ID_fifo_full) -); - -reg_fifo_depth_2_w_16_afd_2 rd_op_fifo_0 ( - .clk(gclk), - .clk_en(clk_en), - .data_in(rd_op_0[0][15:0]), - .flush(flush), - .pop(rd_op_fifo_pop_0), - .push(rd_op_0_valid), - .rst_n(rst_n), - .data_out(rd_op_fifo_out_op_0), - .empty(rd_op_fifo_0_empty), - .full(rd_op_fifo_0_full) -); - -reg_fifo_depth_2_w_16_afd_2 rd_op_fifo_1 ( - .clk(gclk), - .clk_en(clk_en), - .data_in(rd_op_1[0][15:0]), - .flush(flush), - .pop(rd_op_fifo_pop_1), - .push(rd_op_1_valid), - .rst_n(rst_n), - .data_out(rd_op_fifo_out_op_1), - .empty(rd_op_fifo_1_empty), - .full(rd_op_fifo_1_full) -); - -reg_fifo_depth_2_w_16_afd_2 rd_addr_fifo_0 ( - .clk(gclk), - .clk_en(clk_en), - .data_in(rd_addr_0[0][15:0]), - .flush(flush), - .pop(rd_addr_fifo_pop_0), - .push(rd_addr_0_valid), - .rst_n(rst_n), - .data_out(rd_addr_fifo_out_addr_0), - .empty(rd_addr_fifo_0_empty), - .full(rd_addr_fifo_0_full) -); - -reg_fifo_depth_2_w_16_afd_2 rd_addr_fifo_1 ( - .clk(gclk), - .clk_en(clk_en), - .data_in(rd_addr_1[0][15:0]), - .flush(flush), - .pop(rd_addr_fifo_pop_1), - .push(rd_addr_1_valid), - .rst_n(rst_n), - .data_out(rd_addr_fifo_out_addr_1), - .empty(rd_addr_fifo_1_empty), - .full(rd_addr_fifo_1_full) -); - -reg_fifo_depth_2_w_17_afd_0 rd_rsp_fifo_0 ( - .clk(gclk), - .clk_en(clk_en), - .data_in(rd_rsp_fifo_0_in_data), - .flush(flush), - .pop(rd_rsp_data_0_ready), - .push(rd_rsp_fifo_0_push), - .rst_n(rst_n), - .almost_full(rd_rsp_fifo_0_almost_full), - .data_out(rd_rsp_data_0), - .empty(rd_rsp_fifo_0_empty), - .full(rd_rsp_fifo_0_full) -); - -reg_fifo_depth_2_w_17_afd_0 rd_rsp_fifo_1 ( - .clk(gclk), - .clk_en(clk_en), - .data_in(rd_rsp_fifo_1_in_data), - .flush(flush), - .pop(rd_rsp_data_1_ready), - .push(rd_rsp_fifo_1_push), - .rst_n(rst_n), - .almost_full(rd_rsp_fifo_1_almost_full), - .data_out(rd_rsp_data_1), - .empty(rd_rsp_fifo_1_empty), - .full(rd_rsp_fifo_1_full) -); - -reg_fifo_depth_2_w_32_afd_2 blk_fifo_0 ( - .clk(gclk), - .clk_en(clk_en), - .data_in(blk_fifo_0_data_in), - .flush(flush), - .pop(pop_blk[0]), - .push(push_blk[0]), - .rst_n(rst_n), - .data_out(blk_fifo_0_data_out), - .empty(blk_fifo_0_empty), - .full(blk_fifo_0_full) -); - -reg_fifo_depth_2_w_32_afd_2 blk_fifo_1 ( - .clk(gclk), - .clk_en(clk_en), - .data_in(blk_fifo_1_data_in), - .flush(flush), - .pop(pop_blk[1]), - .push(push_blk[1]), - .rst_n(rst_n), - .data_out(blk_fifo_1_data_out), - .empty(blk_fifo_1_empty), - .full(blk_fifo_1_full) -); - -arbiter_4_in_RR_algo rr_arbiter ( - .clk(gclk), - .clk_en(clk_en), - .flush(flush), - .request_in(base_rr), - .resource_ready(rr_arbiter_resource_ready), - .rst_n(rst_n), - .grant_out(mem_acq) -); - -endmodule // buffet_like_16 - -module fiber_access_16 ( - input logic [1:0] [3:0] buffet_buffet_capacity_log, - input logic [3:0] [15:0] buffet_data_from_mem_lifted, - input logic buffet_tile_en, - input logic clk, - input logic clk_en, - input logic flush, - input logic read_scanner_block_mode, - input logic read_scanner_block_rd_out_ready, - input logic read_scanner_coord_out_ready, - input logic read_scanner_dense, - input logic [15:0] read_scanner_dim_size, - input logic read_scanner_do_repeat, - input logic [15:0] read_scanner_inner_dim_offset, - input logic read_scanner_lookup, - input logic read_scanner_pos_out_ready, - input logic [15:0] read_scanner_repeat_factor, - input logic read_scanner_repeat_outer_inner_n, - input logic read_scanner_root, - input logic read_scanner_tile_en, - input logic [16:0] read_scanner_us_pos_in, - input logic read_scanner_us_pos_in_valid, - input logic rst_n, - input logic tile_en, - input logic vector_reduce_mode, - input logic [16:0] write_scanner_addr_in, - input logic write_scanner_addr_in_valid, - input logic write_scanner_block_mode, - input logic [16:0] write_scanner_block_wr_in, - input logic write_scanner_block_wr_in_valid, - input logic write_scanner_compressed, - input logic [16:0] write_scanner_data_in, - input logic write_scanner_data_in_valid, - input logic write_scanner_init_blank, - input logic write_scanner_lowest_level, - input logic [15:0] write_scanner_stop_lvl, - input logic write_scanner_tile_en, - output logic [8:0] buffet_addr_to_mem_lifted, - output logic [3:0] [15:0] buffet_data_to_mem_lifted, - output logic buffet_ren_to_mem_lifted, - output logic buffet_wen_to_mem_lifted, - output logic [16:0] read_scanner_block_rd_out, - output logic read_scanner_block_rd_out_valid, - output logic [16:0] read_scanner_coord_out, - output logic read_scanner_coord_out_valid, - output logic [16:0] read_scanner_pos_out, - output logic read_scanner_pos_out_valid, - output logic read_scanner_us_pos_in_ready, - output logic write_scanner_addr_in_ready, - output logic write_scanner_block_wr_in_ready, - output logic write_scanner_data_in_ready -); - -typedef enum logic[2:0] { - DS_READ_ROW = 3'h0, - INIT_BLANK_SEND_DONE = 3'h1, - INIT_BLANK_SEND_S0 = 3'h2, - ISSUE_READ_SEND_DONE = 3'h3, - ISSUE_READ_SEND_REF_CNT = 3'h4, - ISSUE_READ_SEND_S0 = 3'h5, - PROCESS_ROW = 3'h6, - START = 3'h7 -} vr_seq_state; -logic [16:0] S_level_0; -logic [16:0] S_level_1; -logic [16:0] S_level_2; -logic [0:0][16:0] buffet_wr_ID; -logic buffet_wr_ID_ready; -logic buffet_wr_ID_valid; -logic [0:0][16:0] buffet_wr_addr; -logic buffet_wr_addr_ready; -logic buffet_wr_addr_valid; -logic [0:0][16:0] buffet_wr_data; -logic buffet_wr_data_ready; -logic buffet_wr_data_valid; -logic done_sent_to_ds; -logic done_sent_to_ds_d1; -logic [16:0] done_token; -logic gclk; -logic [2:0] highest_seen_stoken; -logic input_row_fully_processed; -logic input_row_fully_processed_sticky_sticky; -logic input_row_fully_processed_sticky_was_high; -logic is_stop_token; -logic new_highest_stoken_seen; -logic output_matrix_fully_accumulated; -logic output_matrix_fully_accumulated_sticky_sticky; -logic output_matrix_fully_accumulated_sticky_was_high; -logic output_row_fully_accumulated; -logic output_row_fully_accumulated_sticky_sticky; -logic output_row_fully_accumulated_sticky_was_high; -logic [0:0][16:0] read_scanner_addr_out_0; -logic read_scanner_addr_out_0_ready; -logic read_scanner_addr_out_0_valid; -logic [0:0][16:0] read_scanner_addr_out_1; -logic read_scanner_addr_out_1_ready; -logic read_scanner_addr_out_1_valid; -logic [0:0][16:0] read_scanner_op_out_0; -logic read_scanner_op_out_0_ready; -logic read_scanner_op_out_0_valid; -logic [0:0][16:0] read_scanner_op_out_1; -logic read_scanner_op_out_1_ready; -logic read_scanner_op_out_1_valid; -logic [16:0] read_scanner_pos_out_0; -logic read_scanner_pos_out_valid_0; -logic [0:0][16:0] read_scanner_rd_rsp_data_in_0; -logic read_scanner_rd_rsp_data_in_0_ready; -logic read_scanner_rd_rsp_data_in_0_valid; -logic [0:0][16:0] read_scanner_rd_rsp_data_in_1; -logic read_scanner_rd_rsp_data_in_1_ready; -logic read_scanner_rd_rsp_data_in_1_valid; -logic [16:0] read_scanner_us_pos_in_0; -logic read_scanner_us_pos_in_valid_0; -logic rs_has_prepped_ds_row; -logic [16:0] semi_done_token; -logic vr_fsm_init_blank_DONE; -logic vr_fsm_init_blank_S0; -logic [16:0] vr_fsm_pos_to_read_scanner; -logic vr_fsm_pos_valid_to_read_scanner; -vr_seq_state vr_seq_current_state; -vr_seq_state vr_seq_next_state; -assign gclk = clk & tile_en; -assign S_level_0 = {1'h1, 16'h0}; -assign S_level_1 = {1'h1, 15'h0, 1'h1}; -assign S_level_2 = {1'h1, 14'h0, 1'h1, 1'h0}; -assign done_token = {1'h1, 7'h0, 1'h1, 8'h0}; -assign semi_done_token = {1'h1, 11'h0, 1'h1, 4'h0}; -assign done_sent_to_ds = (read_scanner_pos_out_0 == done_token) & read_scanner_pos_out_valid_0 & - read_scanner_pos_out_ready; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - done_sent_to_ds_d1 <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - done_sent_to_ds_d1 <= 1'h0; - end - else done_sent_to_ds_d1 <= done_sent_to_ds; - end -end -assign is_stop_token = (write_scanner_data_in[16] == 1'h1) & (~(write_scanner_data_in == done_token)) & - (~(write_scanner_data_in == semi_done_token)); -assign new_highest_stoken_seen = is_stop_token & (write_scanner_data_in[2:0] > highest_seen_stoken) & - write_scanner_data_in_valid & write_scanner_data_in_ready; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - highest_seen_stoken <= S_level_0[2:0]; - end - else if (clk_en) begin - if (flush) begin - highest_seen_stoken <= S_level_0[2:0]; - end - else if (done_sent_to_ds) begin - highest_seen_stoken <= S_level_0[2:0]; - end - else if (new_highest_stoken_seen) begin - highest_seen_stoken <= write_scanner_data_in[2:0]; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (!rst_n) begin - vr_seq_current_state <= START; - end - else if (clk_en) begin - if (flush) begin - vr_seq_current_state <= START; - end - else vr_seq_current_state <= vr_seq_next_state; - end -end -always_comb begin - vr_seq_next_state = vr_seq_current_state; - unique case (vr_seq_current_state) - DS_READ_ROW: begin - if (rs_has_prepped_ds_row) begin - vr_seq_next_state = INIT_BLANK_SEND_S0; - end - else vr_seq_next_state = DS_READ_ROW; - end - INIT_BLANK_SEND_DONE: begin - if (read_scanner_coord_out_ready) begin - vr_seq_next_state = PROCESS_ROW; - end - else vr_seq_next_state = INIT_BLANK_SEND_DONE; - end - INIT_BLANK_SEND_S0: begin - if (read_scanner_coord_out_ready) begin - vr_seq_next_state = INIT_BLANK_SEND_DONE; - end - else vr_seq_next_state = INIT_BLANK_SEND_S0; - end - ISSUE_READ_SEND_DONE: begin - if (read_scanner_us_pos_in_ready & (~output_row_fully_accumulated)) begin - vr_seq_next_state = PROCESS_ROW; - end - else if (read_scanner_us_pos_in_ready & output_row_fully_accumulated) begin - vr_seq_next_state = DS_READ_ROW; - end - else vr_seq_next_state = ISSUE_READ_SEND_DONE; - end - ISSUE_READ_SEND_REF_CNT: begin - if (read_scanner_us_pos_in_ready & ((~output_matrix_fully_accumulated) | (output_matrix_fully_accumulated & (~(S_level_1[2:0] < highest_seen_stoken))))) begin - vr_seq_next_state = ISSUE_READ_SEND_DONE; - end - else if (read_scanner_us_pos_in_ready & output_matrix_fully_accumulated & (S_level_1[2:0] < highest_seen_stoken)) begin - vr_seq_next_state = ISSUE_READ_SEND_S0; - end - else vr_seq_next_state = ISSUE_READ_SEND_REF_CNT; - end - ISSUE_READ_SEND_S0: begin - if (read_scanner_us_pos_in_ready) begin - vr_seq_next_state = ISSUE_READ_SEND_DONE; - end - else vr_seq_next_state = ISSUE_READ_SEND_S0; - end - PROCESS_ROW: begin - if (input_row_fully_processed) begin - vr_seq_next_state = ISSUE_READ_SEND_REF_CNT; - end - else vr_seq_next_state = PROCESS_ROW; - end - START: begin - if (vector_reduce_mode) begin - vr_seq_next_state = INIT_BLANK_SEND_S0; - end - else vr_seq_next_state = START; - end - default: begin end - endcase -end -always_comb begin - unique case (vr_seq_current_state) - DS_READ_ROW: begin :vr_seq_DS_READ_ROW_Output - vr_fsm_pos_to_read_scanner = 17'h0; - vr_fsm_pos_valid_to_read_scanner = 1'h0; - vr_fsm_init_blank_S0 = 1'h0; - vr_fsm_init_blank_DONE = 1'h0; - end :vr_seq_DS_READ_ROW_Output - INIT_BLANK_SEND_DONE: begin :vr_seq_INIT_BLANK_SEND_DONE_Output - vr_fsm_pos_to_read_scanner = 17'h0; - vr_fsm_pos_valid_to_read_scanner = 1'h0; - vr_fsm_init_blank_S0 = 1'h0; - vr_fsm_init_blank_DONE = 1'h1; - end :vr_seq_INIT_BLANK_SEND_DONE_Output - INIT_BLANK_SEND_S0: begin :vr_seq_INIT_BLANK_SEND_S0_Output - vr_fsm_pos_to_read_scanner = 17'h0; - vr_fsm_pos_valid_to_read_scanner = 1'h0; - vr_fsm_init_blank_S0 = 1'h1; - vr_fsm_init_blank_DONE = 1'h0; - end :vr_seq_INIT_BLANK_SEND_S0_Output - ISSUE_READ_SEND_DONE: begin :vr_seq_ISSUE_READ_SEND_DONE_Output - vr_fsm_pos_to_read_scanner = done_token; - vr_fsm_pos_valid_to_read_scanner = 1'h1; - vr_fsm_init_blank_S0 = 1'h0; - vr_fsm_init_blank_DONE = 1'h0; - end :vr_seq_ISSUE_READ_SEND_DONE_Output - ISSUE_READ_SEND_REF_CNT: begin :vr_seq_ISSUE_READ_SEND_REF_CNT_Output - vr_fsm_pos_to_read_scanner = 17'h0; - vr_fsm_pos_valid_to_read_scanner = 1'h1; - vr_fsm_init_blank_S0 = 1'h0; - vr_fsm_init_blank_DONE = 1'h0; - end :vr_seq_ISSUE_READ_SEND_REF_CNT_Output - ISSUE_READ_SEND_S0: begin :vr_seq_ISSUE_READ_SEND_S0_Output - vr_fsm_pos_to_read_scanner = S_level_0; - vr_fsm_pos_valid_to_read_scanner = 1'h1; - vr_fsm_init_blank_S0 = 1'h0; - vr_fsm_init_blank_DONE = 1'h0; - end :vr_seq_ISSUE_READ_SEND_S0_Output - PROCESS_ROW: begin :vr_seq_PROCESS_ROW_Output - vr_fsm_pos_to_read_scanner = 17'h0; - vr_fsm_pos_valid_to_read_scanner = 1'h0; - vr_fsm_init_blank_S0 = 1'h0; - vr_fsm_init_blank_DONE = 1'h0; - end :vr_seq_PROCESS_ROW_Output - START: begin :vr_seq_START_Output - vr_fsm_pos_to_read_scanner = 17'h0; - vr_fsm_pos_valid_to_read_scanner = 1'h0; - vr_fsm_init_blank_S0 = 1'h0; - vr_fsm_init_blank_DONE = 1'h0; - end :vr_seq_START_Output - default: begin end - endcase -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - input_row_fully_processed_sticky_was_high <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - input_row_fully_processed_sticky_was_high <= 1'h0; - end - else if (vr_seq_current_state == ISSUE_READ_SEND_DONE) begin - input_row_fully_processed_sticky_was_high <= 1'h0; - end - else if (((write_scanner_data_in == S_level_0) | (write_scanner_data_in == S_level_1) | (write_scanner_data_in == S_level_2)) & write_scanner_data_in_valid & write_scanner_data_in_ready) begin - input_row_fully_processed_sticky_was_high <= 1'h1; - end - end -end -assign input_row_fully_processed_sticky_sticky = (((write_scanner_data_in == S_level_0) | (write_scanner_data_in == S_level_1) | - (write_scanner_data_in == S_level_2)) & write_scanner_data_in_valid & - write_scanner_data_in_ready) | input_row_fully_processed_sticky_was_high; -assign input_row_fully_processed = input_row_fully_processed_sticky_sticky; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - output_row_fully_accumulated_sticky_was_high <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - output_row_fully_accumulated_sticky_was_high <= 1'h0; - end - else if (vr_seq_current_state == INIT_BLANK_SEND_S0) begin - output_row_fully_accumulated_sticky_was_high <= 1'h0; - end - else if (((write_scanner_data_in == S_level_1) | (write_scanner_data_in == S_level_2)) & write_scanner_data_in_valid & write_scanner_data_in_ready) begin - output_row_fully_accumulated_sticky_was_high <= 1'h1; - end - end -end -assign output_row_fully_accumulated_sticky_sticky = (((write_scanner_data_in == S_level_1) | (write_scanner_data_in == S_level_2)) & - write_scanner_data_in_valid & write_scanner_data_in_ready) | - output_row_fully_accumulated_sticky_was_high; -assign output_row_fully_accumulated = output_row_fully_accumulated_sticky_sticky; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - output_matrix_fully_accumulated_sticky_was_high <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - output_matrix_fully_accumulated_sticky_was_high <= 1'h0; - end - else if (done_sent_to_ds_d1) begin - output_matrix_fully_accumulated_sticky_was_high <= 1'h0; - end - else if ((write_scanner_data_in == done_token) & write_scanner_data_in_valid & write_scanner_data_in_ready) begin - output_matrix_fully_accumulated_sticky_was_high <= 1'h1; - end - end -end -assign output_matrix_fully_accumulated_sticky_sticky = ((write_scanner_data_in == done_token) & write_scanner_data_in_valid & - write_scanner_data_in_ready) | output_matrix_fully_accumulated_sticky_was_high; -assign output_matrix_fully_accumulated = output_matrix_fully_accumulated_sticky_sticky; -assign read_scanner_pos_out = read_scanner_pos_out_0; -assign read_scanner_pos_out_valid = read_scanner_pos_out_valid_0; -assign read_scanner_us_pos_in_0 = vector_reduce_mode ? vr_fsm_pos_to_read_scanner: read_scanner_us_pos_in; -assign read_scanner_us_pos_in_valid_0 = vector_reduce_mode ? vr_fsm_pos_valid_to_read_scanner: - read_scanner_us_pos_in_valid; -scanner_pipe read_scanner ( - .addr_out_0_ready(read_scanner_addr_out_0_ready), - .addr_out_1_ready(read_scanner_addr_out_1_ready), - .block_mode(read_scanner_block_mode), - .block_rd_out_ready(read_scanner_block_rd_out_ready), - .clk(gclk), - .clk_en(clk_en), - .coord_out_ready(read_scanner_coord_out_ready), - .dense(read_scanner_dense), - .dim_size(read_scanner_dim_size), - .do_repeat(read_scanner_do_repeat), - .flush(flush), - .inner_dim_offset(read_scanner_inner_dim_offset), - .lookup(read_scanner_lookup), - .op_out_0_ready(read_scanner_op_out_0_ready), - .op_out_1_ready(read_scanner_op_out_1_ready), - .output_matrix_fully_accumulated(output_matrix_fully_accumulated), - .output_row_fully_accumulated(output_row_fully_accumulated), - .pos_out_ready(read_scanner_pos_out_ready), - .pos_to_read_scanner_from_vr_fsm(vr_fsm_pos_to_read_scanner), - .rd_rsp_data_in_0(read_scanner_rd_rsp_data_in_0), - .rd_rsp_data_in_0_valid(read_scanner_rd_rsp_data_in_0_valid), - .rd_rsp_data_in_1(read_scanner_rd_rsp_data_in_1), - .rd_rsp_data_in_1_valid(read_scanner_rd_rsp_data_in_1_valid), - .repeat_factor(read_scanner_repeat_factor), - .repeat_outer_inner_n(read_scanner_repeat_outer_inner_n), - .root(read_scanner_root), - .rst_n(rst_n), - .tile_en(read_scanner_tile_en), - .us_pos_in(read_scanner_us_pos_in_0), - .us_pos_in_valid(read_scanner_us_pos_in_valid_0), - .vector_reduce_mode(vector_reduce_mode), - .vr_fsm_state_init_blank_DONE(vr_fsm_init_blank_DONE), - .vr_fsm_state_init_blank_S0(vr_fsm_init_blank_S0), - .addr_out_0(read_scanner_addr_out_0), - .addr_out_0_valid(read_scanner_addr_out_0_valid), - .addr_out_1(read_scanner_addr_out_1), - .addr_out_1_valid(read_scanner_addr_out_1_valid), - .block_rd_out(read_scanner_block_rd_out), - .block_rd_out_valid(read_scanner_block_rd_out_valid), - .coord_out(read_scanner_coord_out), - .coord_out_valid(read_scanner_coord_out_valid), - .op_out_0(read_scanner_op_out_0), - .op_out_0_valid(read_scanner_op_out_0_valid), - .op_out_1(read_scanner_op_out_1), - .op_out_1_valid(read_scanner_op_out_1_valid), - .pos_out(read_scanner_pos_out_0), - .pos_out_valid(read_scanner_pos_out_valid_0), - .rd_rsp_data_in_0_ready(read_scanner_rd_rsp_data_in_0_ready), - .rd_rsp_data_in_1_ready(read_scanner_rd_rsp_data_in_1_ready), - .rs_has_prepped_ds_row(rs_has_prepped_ds_row), - .us_pos_in_ready(read_scanner_us_pos_in_ready) -); - -buffet_like_16 buffet ( - .buffet_capacity_log(buffet_buffet_capacity_log), - .clk(gclk), - .clk_en(clk_en), - .data_from_mem(buffet_data_from_mem_lifted), - .flush(flush), - .rd_addr_0(read_scanner_addr_out_0), - .rd_addr_0_valid(read_scanner_addr_out_0_valid), - .rd_addr_1(read_scanner_addr_out_1), - .rd_addr_1_valid(read_scanner_addr_out_1_valid), - .rd_op_0(read_scanner_op_out_0), - .rd_op_0_valid(read_scanner_op_out_0_valid), - .rd_op_1(read_scanner_op_out_1), - .rd_op_1_valid(read_scanner_op_out_1_valid), - .rd_rsp_data_0_ready(read_scanner_rd_rsp_data_in_0_ready), - .rd_rsp_data_1_ready(read_scanner_rd_rsp_data_in_1_ready), - .rst_n(rst_n), - .tile_en(buffet_tile_en), - .wr_ID(buffet_wr_ID), - .wr_ID_valid(buffet_wr_ID_valid), - .wr_addr(buffet_wr_addr), - .wr_addr_valid(buffet_wr_addr_valid), - .wr_data(buffet_wr_data), - .wr_data_valid(buffet_wr_data_valid), - .addr_to_mem(buffet_addr_to_mem_lifted), - .data_to_mem(buffet_data_to_mem_lifted), - .rd_addr_0_ready(read_scanner_addr_out_0_ready), - .rd_addr_1_ready(read_scanner_addr_out_1_ready), - .rd_op_0_ready(read_scanner_op_out_0_ready), - .rd_op_1_ready(read_scanner_op_out_1_ready), - .rd_rsp_data_0(read_scanner_rd_rsp_data_in_0), - .rd_rsp_data_0_valid(read_scanner_rd_rsp_data_in_0_valid), - .rd_rsp_data_1(read_scanner_rd_rsp_data_in_1), - .rd_rsp_data_1_valid(read_scanner_rd_rsp_data_in_1_valid), - .ren_to_mem(buffet_ren_to_mem_lifted), - .wen_to_mem(buffet_wen_to_mem_lifted), - .wr_ID_ready(buffet_wr_ID_ready), - .wr_addr_ready(buffet_wr_addr_ready), - .wr_data_ready(buffet_wr_data_ready) -); - -write_scanner write_scanner ( - .ID_out_ready(buffet_wr_ID_ready), - .addr_in(write_scanner_addr_in), - .addr_in_valid(write_scanner_addr_in_valid), - .addr_out_ready(buffet_wr_addr_ready), - .block_mode(write_scanner_block_mode), - .block_wr_in(write_scanner_block_wr_in), - .block_wr_in_valid(write_scanner_block_wr_in_valid), - .clk(gclk), - .clk_en(clk_en), - .compressed(write_scanner_compressed), - .data_in(write_scanner_data_in), - .data_in_valid(write_scanner_data_in_valid), - .data_out_ready(buffet_wr_data_ready), - .flush(flush), - .init_blank(write_scanner_init_blank), - .lowest_level(write_scanner_lowest_level), - .rst_n(rst_n), - .stop_lvl(write_scanner_stop_lvl), - .tile_en(write_scanner_tile_en), - .vector_reduce_mode(vector_reduce_mode), - .ID_out(buffet_wr_ID), - .ID_out_valid(buffet_wr_ID_valid), - .addr_in_ready(write_scanner_addr_in_ready), - .addr_out(buffet_wr_addr), - .addr_out_valid(buffet_wr_addr_valid), - .block_wr_in_ready(write_scanner_block_wr_in_ready), - .data_in_ready(write_scanner_data_in_ready), - .data_out(buffet_wr_data), - .data_out_valid(buffet_wr_data_valid) -); - -endmodule // fiber_access_16 - -module fiber_access_16_flat ( - input logic clk, - input logic clk_en, - input logic [3:0] fiber_access_16_inst_buffet_buffet_capacity_log_0, - input logic [3:0] fiber_access_16_inst_buffet_buffet_capacity_log_1, - input logic [3:0] [15:0] fiber_access_16_inst_buffet_data_from_mem_lifted_lifted, - input logic fiber_access_16_inst_buffet_tile_en, - input logic fiber_access_16_inst_read_scanner_block_mode, - input logic fiber_access_16_inst_read_scanner_dense, - input logic [15:0] fiber_access_16_inst_read_scanner_dim_size, - input logic fiber_access_16_inst_read_scanner_do_repeat, - input logic [15:0] fiber_access_16_inst_read_scanner_inner_dim_offset, - input logic fiber_access_16_inst_read_scanner_lookup, - input logic [15:0] fiber_access_16_inst_read_scanner_repeat_factor, - input logic fiber_access_16_inst_read_scanner_repeat_outer_inner_n, - input logic fiber_access_16_inst_read_scanner_root, - input logic fiber_access_16_inst_read_scanner_tile_en, - input logic fiber_access_16_inst_tile_en, - input logic fiber_access_16_inst_vector_reduce_mode, - input logic fiber_access_16_inst_write_scanner_block_mode, - input logic fiber_access_16_inst_write_scanner_compressed, - input logic fiber_access_16_inst_write_scanner_init_blank, - input logic fiber_access_16_inst_write_scanner_lowest_level, - input logic [15:0] fiber_access_16_inst_write_scanner_stop_lvl, - input logic fiber_access_16_inst_write_scanner_tile_en, - input logic flush, - input logic read_scanner_block_rd_out_ready_f_, - input logic read_scanner_coord_out_ready_f_, - input logic read_scanner_pos_out_ready_f_, - input logic [0:0] [16:0] read_scanner_us_pos_in_f_, - input logic read_scanner_us_pos_in_valid_f_, - input logic rst_n, - input logic [0:0] [16:0] write_scanner_addr_in_f_, - input logic write_scanner_addr_in_valid_f_, - input logic [0:0] [16:0] write_scanner_block_wr_in_f_, - input logic write_scanner_block_wr_in_valid_f_, - input logic [0:0] [16:0] write_scanner_data_in_f_, - input logic write_scanner_data_in_valid_f_, - output logic [8:0] fiber_access_16_inst_buffet_addr_to_mem_lifted_lifted, - output logic [3:0] [15:0] fiber_access_16_inst_buffet_data_to_mem_lifted_lifted, - output logic fiber_access_16_inst_buffet_ren_to_mem_lifted_lifted, - output logic fiber_access_16_inst_buffet_wen_to_mem_lifted_lifted, - output logic [0:0] [16:0] read_scanner_block_rd_out_f_, - output logic read_scanner_block_rd_out_valid_f_, - output logic [0:0] [16:0] read_scanner_coord_out_f_, - output logic read_scanner_coord_out_valid_f_, - output logic [0:0] [16:0] read_scanner_pos_out_f_, - output logic read_scanner_pos_out_valid_f_, - output logic read_scanner_us_pos_in_ready_f_, - output logic write_scanner_addr_in_ready_f_, - output logic write_scanner_block_wr_in_ready_f_, - output logic write_scanner_data_in_ready_f_ -); - -logic [1:0][3:0] fiber_access_16_inst_buffet_buffet_capacity_log; -assign fiber_access_16_inst_buffet_buffet_capacity_log[0] = fiber_access_16_inst_buffet_buffet_capacity_log_0; -assign fiber_access_16_inst_buffet_buffet_capacity_log[1] = fiber_access_16_inst_buffet_buffet_capacity_log_1; -fiber_access_16 fiber_access_16_inst ( - .buffet_buffet_capacity_log(fiber_access_16_inst_buffet_buffet_capacity_log), - .buffet_data_from_mem_lifted(fiber_access_16_inst_buffet_data_from_mem_lifted_lifted), - .buffet_tile_en(fiber_access_16_inst_buffet_tile_en), - .clk(clk), - .clk_en(clk_en), - .flush(flush), - .read_scanner_block_mode(fiber_access_16_inst_read_scanner_block_mode), - .read_scanner_block_rd_out_ready(read_scanner_block_rd_out_ready_f_), - .read_scanner_coord_out_ready(read_scanner_coord_out_ready_f_), - .read_scanner_dense(fiber_access_16_inst_read_scanner_dense), - .read_scanner_dim_size(fiber_access_16_inst_read_scanner_dim_size), - .read_scanner_do_repeat(fiber_access_16_inst_read_scanner_do_repeat), - .read_scanner_inner_dim_offset(fiber_access_16_inst_read_scanner_inner_dim_offset), - .read_scanner_lookup(fiber_access_16_inst_read_scanner_lookup), - .read_scanner_pos_out_ready(read_scanner_pos_out_ready_f_), - .read_scanner_repeat_factor(fiber_access_16_inst_read_scanner_repeat_factor), - .read_scanner_repeat_outer_inner_n(fiber_access_16_inst_read_scanner_repeat_outer_inner_n), - .read_scanner_root(fiber_access_16_inst_read_scanner_root), - .read_scanner_tile_en(fiber_access_16_inst_read_scanner_tile_en), - .read_scanner_us_pos_in(read_scanner_us_pos_in_f_), - .read_scanner_us_pos_in_valid(read_scanner_us_pos_in_valid_f_), - .rst_n(rst_n), - .tile_en(fiber_access_16_inst_tile_en), - .vector_reduce_mode(fiber_access_16_inst_vector_reduce_mode), - .write_scanner_addr_in(write_scanner_addr_in_f_), - .write_scanner_addr_in_valid(write_scanner_addr_in_valid_f_), - .write_scanner_block_mode(fiber_access_16_inst_write_scanner_block_mode), - .write_scanner_block_wr_in(write_scanner_block_wr_in_f_), - .write_scanner_block_wr_in_valid(write_scanner_block_wr_in_valid_f_), - .write_scanner_compressed(fiber_access_16_inst_write_scanner_compressed), - .write_scanner_data_in(write_scanner_data_in_f_), - .write_scanner_data_in_valid(write_scanner_data_in_valid_f_), - .write_scanner_init_blank(fiber_access_16_inst_write_scanner_init_blank), - .write_scanner_lowest_level(fiber_access_16_inst_write_scanner_lowest_level), - .write_scanner_stop_lvl(fiber_access_16_inst_write_scanner_stop_lvl), - .write_scanner_tile_en(fiber_access_16_inst_write_scanner_tile_en), - .buffet_addr_to_mem_lifted(fiber_access_16_inst_buffet_addr_to_mem_lifted_lifted), - .buffet_data_to_mem_lifted(fiber_access_16_inst_buffet_data_to_mem_lifted_lifted), - .buffet_ren_to_mem_lifted(fiber_access_16_inst_buffet_ren_to_mem_lifted_lifted), - .buffet_wen_to_mem_lifted(fiber_access_16_inst_buffet_wen_to_mem_lifted_lifted), - .read_scanner_block_rd_out(read_scanner_block_rd_out_f_), - .read_scanner_block_rd_out_valid(read_scanner_block_rd_out_valid_f_), - .read_scanner_coord_out(read_scanner_coord_out_f_), - .read_scanner_coord_out_valid(read_scanner_coord_out_valid_f_), - .read_scanner_pos_out(read_scanner_pos_out_f_), - .read_scanner_pos_out_valid(read_scanner_pos_out_valid_f_), - .read_scanner_us_pos_in_ready(read_scanner_us_pos_in_ready_f_), - .write_scanner_addr_in_ready(write_scanner_addr_in_ready_f_), - .write_scanner_block_wr_in_ready(write_scanner_block_wr_in_ready_f_), - .write_scanner_data_in_ready(write_scanner_data_in_ready_f_) -); - -endmodule // fiber_access_16_flat - -module for_loop_3_11 #( - parameter CONFIG_WIDTH = 5'hB, - parameter ITERATOR_SUPPORT = 3'h3, - parameter ITERATOR_SUPPORT2 = 2'h2 -) -( - input logic clk, - input logic clk_en, - input logic [2:0] dimensionality, - input logic flush, - input logic [2:0] [10:0] ranges, - input logic rst_n, - input logic step, - output logic [1:0] mux_sel_out, - output logic restart -); - -logic [2:0] clear; -logic [2:0][10:0] dim_counter; -logic done; -logic [2:0] inc; -logic [10:0] inced_cnt; -logic [2:0] max_value; -logic maxed_value; -logic [1:0] mux_sel; -assign mux_sel_out = mux_sel; -assign inced_cnt = dim_counter[mux_sel] + 11'h1; -assign maxed_value = (dim_counter[mux_sel] == ranges[mux_sel]) & inc[mux_sel]; -always_comb begin - mux_sel = 2'h0; - done = 1'h0; - if (~done) begin - if ((~max_value[0]) & (dimensionality > 3'h0)) begin - mux_sel = 2'h0; - done = 1'h1; - end - end - if (~done) begin - if ((~max_value[1]) & (dimensionality > 3'h1)) begin - mux_sel = 2'h1; - done = 1'h1; - end - end - if (~done) begin - if ((~max_value[2]) & (dimensionality > 3'h2)) begin - mux_sel = 2'h2; - done = 1'h1; - end - end -end -always_comb begin - clear[0] = 1'h0; - if (((mux_sel > 2'h0) | (~done)) & step) begin - clear[0] = 1'h1; - end -end -always_comb begin - inc[0] = 1'h0; - if ((5'h0 == 5'h0) & step & (dimensionality > 3'h0)) begin - inc[0] = 1'h1; - end - else if ((mux_sel == 2'h0) & step & (dimensionality > 3'h0)) begin - inc[0] = 1'h1; - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - dim_counter[0] <= 11'h0; - end - else if (clk_en) begin - if (flush) begin - dim_counter[0] <= 11'h0; - end - else if (clear[0]) begin - dim_counter[0] <= 11'h0; - end - else if (inc[0]) begin - dim_counter[0] <= inced_cnt; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - max_value[0] <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - max_value[0] <= 1'h0; - end - else if (clear[0]) begin - max_value[0] <= 1'h0; - end - else if (inc[0]) begin - max_value[0] <= maxed_value; - end - end -end -always_comb begin - clear[1] = 1'h0; - if (((mux_sel > 2'h1) | (~done)) & step) begin - clear[1] = 1'h1; - end -end -always_comb begin - inc[1] = 1'h0; - if ((5'h1 == 5'h0) & step & (dimensionality > 3'h1)) begin - inc[1] = 1'h1; - end - else if ((mux_sel == 2'h1) & step & (dimensionality > 3'h1)) begin - inc[1] = 1'h1; - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - dim_counter[1] <= 11'h0; - end - else if (clk_en) begin - if (flush) begin - dim_counter[1] <= 11'h0; - end - else if (clear[1]) begin - dim_counter[1] <= 11'h0; - end - else if (inc[1]) begin - dim_counter[1] <= inced_cnt; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - max_value[1] <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - max_value[1] <= 1'h0; - end - else if (clear[1]) begin - max_value[1] <= 1'h0; - end - else if (inc[1]) begin - max_value[1] <= maxed_value; - end - end -end -always_comb begin - clear[2] = 1'h0; - if (((mux_sel > 2'h2) | (~done)) & step) begin - clear[2] = 1'h1; - end -end -always_comb begin - inc[2] = 1'h0; - if ((5'h2 == 5'h0) & step & (dimensionality > 3'h2)) begin - inc[2] = 1'h1; - end - else if ((mux_sel == 2'h2) & step & (dimensionality > 3'h2)) begin - inc[2] = 1'h1; - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - dim_counter[2] <= 11'h0; - end - else if (clk_en) begin - if (flush) begin - dim_counter[2] <= 11'h0; - end - else if (clear[2]) begin - dim_counter[2] <= 11'h0; - end - else if (inc[2]) begin - dim_counter[2] <= inced_cnt; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - max_value[2] <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - max_value[2] <= 1'h0; - end - else if (clear[2]) begin - max_value[2] <= 1'h0; - end - else if (inc[2]) begin - max_value[2] <= maxed_value; - end - end -end -assign restart = step & (~done); -endmodule // for_loop_3_11 - -module for_loop_6_11 #( - parameter CONFIG_WIDTH = 5'hB, - parameter ITERATOR_SUPPORT = 4'h6, - parameter ITERATOR_SUPPORT2 = 2'h2 -) -( - input logic clk, - input logic clk_en, - input logic [3:0] dimensionality, - input logic flush, - input logic [5:0] [10:0] ranges, - input logic rst_n, - input logic step, - output logic [2:0] mux_sel_out, - output logic restart -); - -logic [5:0] clear; -logic [5:0][10:0] dim_counter; -logic done; -logic [5:0] inc; -logic [10:0] inced_cnt; -logic [5:0] max_value; -logic maxed_value; -logic [2:0] mux_sel; -assign mux_sel_out = mux_sel; -assign inced_cnt = dim_counter[mux_sel] + 11'h1; -assign maxed_value = (dim_counter[mux_sel] == ranges[mux_sel]) & inc[mux_sel]; -always_comb begin - mux_sel = 3'h0; - done = 1'h0; - if (~done) begin - if ((~max_value[0]) & (dimensionality > 4'h0)) begin - mux_sel = 3'h0; - done = 1'h1; - end - end - if (~done) begin - if ((~max_value[1]) & (dimensionality > 4'h1)) begin - mux_sel = 3'h1; - done = 1'h1; - end - end - if (~done) begin - if ((~max_value[2]) & (dimensionality > 4'h2)) begin - mux_sel = 3'h2; - done = 1'h1; - end - end - if (~done) begin - if ((~max_value[3]) & (dimensionality > 4'h3)) begin - mux_sel = 3'h3; - done = 1'h1; - end - end - if (~done) begin - if ((~max_value[4]) & (dimensionality > 4'h4)) begin - mux_sel = 3'h4; - done = 1'h1; - end - end - if (~done) begin - if ((~max_value[5]) & (dimensionality > 4'h5)) begin - mux_sel = 3'h5; - done = 1'h1; - end - end -end -always_comb begin - clear[0] = 1'h0; - if (((mux_sel > 3'h0) | (~done)) & step) begin - clear[0] = 1'h1; - end -end -always_comb begin - inc[0] = 1'h0; - if ((5'h0 == 5'h0) & step & (dimensionality > 4'h0)) begin - inc[0] = 1'h1; - end - else if ((mux_sel == 3'h0) & step & (dimensionality > 4'h0)) begin - inc[0] = 1'h1; - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - dim_counter[0] <= 11'h0; - end - else if (clk_en) begin - if (flush) begin - dim_counter[0] <= 11'h0; - end - else if (clear[0]) begin - dim_counter[0] <= 11'h0; - end - else if (inc[0]) begin - dim_counter[0] <= inced_cnt; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - max_value[0] <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - max_value[0] <= 1'h0; - end - else if (clear[0]) begin - max_value[0] <= 1'h0; - end - else if (inc[0]) begin - max_value[0] <= maxed_value; - end - end -end -always_comb begin - clear[1] = 1'h0; - if (((mux_sel > 3'h1) | (~done)) & step) begin - clear[1] = 1'h1; - end -end -always_comb begin - inc[1] = 1'h0; - if ((5'h1 == 5'h0) & step & (dimensionality > 4'h1)) begin - inc[1] = 1'h1; - end - else if ((mux_sel == 3'h1) & step & (dimensionality > 4'h1)) begin - inc[1] = 1'h1; - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - dim_counter[1] <= 11'h0; - end - else if (clk_en) begin - if (flush) begin - dim_counter[1] <= 11'h0; - end - else if (clear[1]) begin - dim_counter[1] <= 11'h0; - end - else if (inc[1]) begin - dim_counter[1] <= inced_cnt; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - max_value[1] <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - max_value[1] <= 1'h0; - end - else if (clear[1]) begin - max_value[1] <= 1'h0; - end - else if (inc[1]) begin - max_value[1] <= maxed_value; - end - end -end -always_comb begin - clear[2] = 1'h0; - if (((mux_sel > 3'h2) | (~done)) & step) begin - clear[2] = 1'h1; - end -end -always_comb begin - inc[2] = 1'h0; - if ((5'h2 == 5'h0) & step & (dimensionality > 4'h2)) begin - inc[2] = 1'h1; - end - else if ((mux_sel == 3'h2) & step & (dimensionality > 4'h2)) begin - inc[2] = 1'h1; - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - dim_counter[2] <= 11'h0; - end - else if (clk_en) begin - if (flush) begin - dim_counter[2] <= 11'h0; - end - else if (clear[2]) begin - dim_counter[2] <= 11'h0; - end - else if (inc[2]) begin - dim_counter[2] <= inced_cnt; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - max_value[2] <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - max_value[2] <= 1'h0; - end - else if (clear[2]) begin - max_value[2] <= 1'h0; - end - else if (inc[2]) begin - max_value[2] <= maxed_value; - end - end -end -always_comb begin - clear[3] = 1'h0; - if (((mux_sel > 3'h3) | (~done)) & step) begin - clear[3] = 1'h1; - end -end -always_comb begin - inc[3] = 1'h0; - if ((5'h3 == 5'h0) & step & (dimensionality > 4'h3)) begin - inc[3] = 1'h1; - end - else if ((mux_sel == 3'h3) & step & (dimensionality > 4'h3)) begin - inc[3] = 1'h1; - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - dim_counter[3] <= 11'h0; - end - else if (clk_en) begin - if (flush) begin - dim_counter[3] <= 11'h0; - end - else if (clear[3]) begin - dim_counter[3] <= 11'h0; - end - else if (inc[3]) begin - dim_counter[3] <= inced_cnt; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - max_value[3] <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - max_value[3] <= 1'h0; - end - else if (clear[3]) begin - max_value[3] <= 1'h0; - end - else if (inc[3]) begin - max_value[3] <= maxed_value; - end - end -end -always_comb begin - clear[4] = 1'h0; - if (((mux_sel > 3'h4) | (~done)) & step) begin - clear[4] = 1'h1; - end -end -always_comb begin - inc[4] = 1'h0; - if ((5'h4 == 5'h0) & step & (dimensionality > 4'h4)) begin - inc[4] = 1'h1; - end - else if ((mux_sel == 3'h4) & step & (dimensionality > 4'h4)) begin - inc[4] = 1'h1; - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - dim_counter[4] <= 11'h0; - end - else if (clk_en) begin - if (flush) begin - dim_counter[4] <= 11'h0; - end - else if (clear[4]) begin - dim_counter[4] <= 11'h0; - end - else if (inc[4]) begin - dim_counter[4] <= inced_cnt; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - max_value[4] <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - max_value[4] <= 1'h0; - end - else if (clear[4]) begin - max_value[4] <= 1'h0; - end - else if (inc[4]) begin - max_value[4] <= maxed_value; - end - end -end -always_comb begin - clear[5] = 1'h0; - if (((mux_sel > 3'h5) | (~done)) & step) begin - clear[5] = 1'h1; - end -end -always_comb begin - inc[5] = 1'h0; - if ((5'h5 == 5'h0) & step & (dimensionality > 4'h5)) begin - inc[5] = 1'h1; - end - else if ((mux_sel == 3'h5) & step & (dimensionality > 4'h5)) begin - inc[5] = 1'h1; - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - dim_counter[5] <= 11'h0; - end - else if (clk_en) begin - if (flush) begin - dim_counter[5] <= 11'h0; - end - else if (clear[5]) begin - dim_counter[5] <= 11'h0; - end - else if (inc[5]) begin - dim_counter[5] <= inced_cnt; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - max_value[5] <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - max_value[5] <= 1'h0; - end - else if (clear[5]) begin - max_value[5] <= 1'h0; - end - else if (inc[5]) begin - max_value[5] <= maxed_value; - end - end -end -assign restart = step & (~done); -endmodule // for_loop_6_11 - -module reg_fifo_depth_0_w_16_afd_2 ( - input logic clk, - input logic clk_en, - input logic [0:0] [15:0] data_in, - input logic flush, - input logic pop, - input logic push, - input logic rst_n, - output logic almost_full, - output logic [0:0] [15:0] data_out, - output logic empty, - output logic full, - output logic valid -); - -assign data_out = data_in; -assign valid = push; -assign empty = ~push; -assign full = ~pop; -assign almost_full = ~pop; -endmodule // reg_fifo_depth_0_w_16_afd_2 - -module reg_fifo_depth_2_w_16_afd_2 ( - input logic clk, - input logic clk_en, - input logic [0:0] [15:0] data_in, - input logic flush, - input logic pop, - input logic push, - input logic rst_n, - output logic almost_full, - output logic [0:0] [15:0] data_out, - output logic empty, - output logic full, - output logic valid -); - -logic [1:0] num_items; -logic passthru; -logic rd_ptr; -logic read; -logic [1:0][0:0][15:0] reg_array; -logic wr_ptr; -logic write; -assign full = num_items == 2'h2; -assign almost_full = num_items >= 2'h0; -assign empty = num_items == 2'h0; -assign read = pop & (~passthru) & (~empty); -assign passthru = 1'h0; -assign write = push & (~passthru) & (~full); - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - num_items <= 2'h0; - end - else if (flush) begin - num_items <= 2'h0; - end - else if (clk_en) begin - if (write & (~read)) begin - num_items <= num_items + 2'h1; - end - else if ((~write) & read) begin - num_items <= num_items - 2'h1; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - reg_array <= 32'h0; - end - else if (flush) begin - reg_array <= 32'h0; - end - else if (clk_en) begin - if (write) begin - reg_array[wr_ptr] <= data_in; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - wr_ptr <= 1'h0; - end - else if (flush) begin - wr_ptr <= 1'h0; - end - else if (clk_en) begin - if (write) begin - if (wr_ptr == 1'h1) begin - wr_ptr <= 1'h0; - end - else wr_ptr <= wr_ptr + 1'h1; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - rd_ptr <= 1'h0; - end - else if (flush) begin - rd_ptr <= 1'h0; - end - else if (clk_en) begin - if (read) begin - rd_ptr <= rd_ptr + 1'h1; - end - end -end -always_comb begin - if (passthru) begin - data_out = data_in; - end - else data_out = reg_array[rd_ptr]; -end -always_comb begin - valid = (~empty) | passthru; -end -endmodule // reg_fifo_depth_2_w_16_afd_2 - -module reg_fifo_depth_2_w_17_afd_0 ( - input logic clk, - input logic clk_en, - input logic [0:0] [16:0] data_in, - input logic flush, - input logic pop, - input logic push, - input logic rst_n, - output logic almost_full, - output logic [0:0] [16:0] data_out, - output logic empty, - output logic full, - output logic valid -); - -logic [1:0] num_items; -logic passthru; -logic rd_ptr; -logic read; -logic [1:0][0:0][16:0] reg_array; -logic wr_ptr; -logic write; -assign full = num_items == 2'h2; -assign almost_full = num_items >= 2'h2; -assign empty = num_items == 2'h0; -assign read = pop & (~passthru) & (~empty); -assign passthru = 1'h0; -assign write = push & (~passthru) & (~full); - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - num_items <= 2'h0; - end - else if (flush) begin - num_items <= 2'h0; - end - else if (clk_en) begin - if (write & (~read)) begin - num_items <= num_items + 2'h1; - end - else if ((~write) & read) begin - num_items <= num_items - 2'h1; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - reg_array <= 34'h0; - end - else if (flush) begin - reg_array <= 34'h0; - end - else if (clk_en) begin - if (write) begin - reg_array[wr_ptr] <= data_in; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - wr_ptr <= 1'h0; - end - else if (flush) begin - wr_ptr <= 1'h0; - end - else if (clk_en) begin - if (write) begin - if (wr_ptr == 1'h1) begin - wr_ptr <= 1'h0; - end - else wr_ptr <= wr_ptr + 1'h1; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - rd_ptr <= 1'h0; - end - else if (flush) begin - rd_ptr <= 1'h0; - end - else if (clk_en) begin - if (read) begin - rd_ptr <= rd_ptr + 1'h1; - end - end -end -always_comb begin - if (passthru) begin - data_out = data_in; - end - else data_out = reg_array[rd_ptr]; -end -always_comb begin - valid = (~empty) | passthru; -end -endmodule // reg_fifo_depth_2_w_17_afd_0 - -module reg_fifo_depth_2_w_32_afd_2 ( - input logic clk, - input logic clk_en, - input logic [0:0] [31:0] data_in, - input logic flush, - input logic pop, - input logic push, - input logic rst_n, - output logic almost_full, - output logic [0:0] [31:0] data_out, - output logic empty, - output logic full, - output logic valid -); - -logic [1:0] num_items; -logic passthru; -logic rd_ptr; -logic read; -logic [1:0][0:0][31:0] reg_array; -logic wr_ptr; -logic write; -assign full = num_items == 2'h2; -assign almost_full = num_items >= 2'h0; -assign empty = num_items == 2'h0; -assign read = pop & (~passthru) & (~empty); -assign passthru = 1'h0; -assign write = push & (~passthru) & (~full); - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - num_items <= 2'h0; - end - else if (flush) begin - num_items <= 2'h0; - end - else if (clk_en) begin - if (clk_en) begin - if (clk_en) begin - if (write & (~read)) begin - num_items <= num_items + 2'h1; - end - else if ((~write) & read) begin - num_items <= num_items - 2'h1; - end - end - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - reg_array <= 64'h0; - end - else if (flush) begin - reg_array <= 64'h0; - end - else if (clk_en) begin - if (clk_en) begin - if (clk_en) begin - if (write) begin - reg_array[wr_ptr] <= data_in; - end - end - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - wr_ptr <= 1'h0; - end - else if (flush) begin - wr_ptr <= 1'h0; - end - else if (clk_en) begin - if (clk_en) begin - if (clk_en) begin - if (write) begin - if (wr_ptr == 1'h1) begin - wr_ptr <= 1'h0; - end - else wr_ptr <= wr_ptr + 1'h1; - end - end - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - rd_ptr <= 1'h0; - end - else if (flush) begin - rd_ptr <= 1'h0; - end - else if (clk_en) begin - if (clk_en) begin - if (clk_en) begin - if (read) begin - rd_ptr <= rd_ptr + 1'h1; - end - end - end - end -end -always_comb begin - if (passthru) begin - data_out = data_in; - end - else data_out = reg_array[rd_ptr]; -end -always_comb begin - valid = (~empty) | passthru; -end -endmodule // reg_fifo_depth_2_w_32_afd_2 - -module reservation_fifo_depth_32_w_17_num_per_1 ( - input logic clk, - input logic clk_en, - input logic [16:0] data_in_0, - input logic [16:0] fill_data_in, - input logic flush, - input logic pop, - input logic push_alloc, - input logic push_fill, - input logic push_reserve, - input logic rst_n, - output logic [16:0] data_out_0, - output logic empty, - output logic full, - output logic valid -); - -logic clr_item_ptr; -logic clr_read_ptr; -logic clr_write_ptr; -logic [0:0][16:0] data_in_packed; -logic [0:0][16:0] data_out; -logic enable_reserve_ptr; -logic inc_item_ptr; -logic inc_read_ptr; -logic inc_reserve_count; -logic inc_write_ptr; -logic item_ptr; -logic jump_next_0; -logic [4:0] next_0_valid; -logic [4:0] next_0_valid_d1; -logic [4:0] next_0_valid_high; -logic next_0_valid_high_done; -logic next_0_valid_high_found; -logic [4:0] next_0_valid_low; -logic next_0_valid_low_done; -logic next_0_valid_low_found; -logic [5:0] num_items; -logic read; -logic [4:0] read_ptr_addr; -logic [31:0][0:0][16:0] reg_array; -logic [15:0] reserve_count; -logic [4:0] reserve_ptr_val; -logic [31:0] valid_mask; -logic write_alloc; -logic write_fill; -logic [4:0] write_ptr_addr; -logic write_reserve; -logic write_reserve_final; -assign data_in_packed[0] = data_in_0; -assign data_out_0 = data_out[0]; -assign item_ptr = 1'h0; -assign inc_item_ptr = push_reserve; -assign clr_item_ptr = push_reserve & (item_ptr == 1'h0); - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - read_ptr_addr <= 5'h0; - end - else if (flush) begin - read_ptr_addr <= 5'h0; - end - else if (clk_en) begin - if (clk_en) begin - if (clr_read_ptr) begin - read_ptr_addr <= 5'h0; - end - else if (inc_read_ptr) begin - read_ptr_addr <= read_ptr_addr + 5'h1; - end - end - end -end -assign inc_read_ptr = read; -assign clr_read_ptr = 1'h0; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - write_ptr_addr <= 5'h0; - end - else if (flush) begin - write_ptr_addr <= 5'h0; - end - else if (clk_en) begin - if (clk_en) begin - if (clr_write_ptr) begin - write_ptr_addr <= 5'h0; - end - else if (inc_write_ptr) begin - write_ptr_addr <= write_ptr_addr + 5'h1; - end - end - end -end -assign inc_write_ptr = write_alloc | write_fill; -assign clr_write_ptr = 1'h0; -assign jump_next_0 = next_0_valid_high_found | next_0_valid_low_found; -assign enable_reserve_ptr = write_reserve_final | (write_fill & (reserve_ptr_val == write_ptr_addr)); - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - next_0_valid_d1 <= 5'h0; - end - else if (flush) begin - next_0_valid_d1 <= 5'h0; - end - else if (clk_en) begin - if (clk_en) begin - if (1'h0) begin - next_0_valid_d1 <= 5'h0; - end - else if (enable_reserve_ptr) begin - next_0_valid_d1 <= next_0_valid; - end - end - end -end -assign reserve_ptr_val = next_0_valid_d1; -assign next_0_valid = (write_fill & ((next_0_valid_d1 == write_ptr_addr) | ((~next_0_valid_high_found) - & (~next_0_valid_low_found)) | (next_0_valid_high_found ? next_0_valid_high == - write_ptr_addr: next_0_valid_low == write_ptr_addr))) ? write_ptr_addr + 5'h1: - ((~next_0_valid_high_found) & (~next_0_valid_low_found)) ? write_ptr_addr: - next_0_valid_high_found ? next_0_valid_high: next_0_valid_low; -assign full = num_items == 6'h20; -assign empty = num_items == 6'h0; -assign write_fill = push_fill & push_alloc & (~full); -assign write_alloc = push_alloc & (~full); -assign write_reserve = inc_item_ptr; -assign write_reserve_final = clr_item_ptr; -assign read = pop & valid_mask[read_ptr_addr]; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - num_items <= 6'h0; - end - else if (flush) begin - num_items <= 6'h0; - end - else if (clk_en) begin - if (clk_en) begin - if (write_alloc & (~read)) begin - num_items <= num_items + 6'h1; - end - else if ((~write_alloc) & read) begin - num_items <= num_items - 6'h1; - end - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - reg_array <= 544'h0; - end - else if (flush) begin - reg_array <= 544'h0; - end - else if (clk_en) begin - if (clk_en) begin - if (write_fill) begin - reg_array[write_ptr_addr] <= fill_data_in; - end - if (write_reserve) begin - reg_array[next_0_valid_d1] <= data_in_packed; - end - end - end -end -always_comb begin - data_out = reg_array[read_ptr_addr]; -end -always_comb begin - valid = valid_mask[read_ptr_addr]; -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - valid_mask <= 32'h0; - end - else if (flush) begin - valid_mask <= 32'h0; - end - else if (clk_en) begin - if (clk_en) begin - if (write_fill) begin - valid_mask[write_ptr_addr] <= 1'h1; - end - if (write_reserve_final) begin - valid_mask[next_0_valid_d1] <= 1'h1; - end - if (read) begin - valid_mask[read_ptr_addr] <= 1'h0; - end - end - end -end -always_comb begin - next_0_valid_high_found = 1'h0; - next_0_valid_high = 5'h0; - next_0_valid_high_done = 1'h0; - if (~next_0_valid_high_done) begin - if (next_0_valid_d1 < 5'h0) begin - if (valid_mask[0] == 1'h0) begin - next_0_valid_high_found = 1'h1; - next_0_valid_high = 5'h0; - next_0_valid_high_done = 1'h1; - end - end - end - if (~next_0_valid_high_done) begin - if (next_0_valid_d1 < 5'h1) begin - if (valid_mask[1] == 1'h0) begin - next_0_valid_high_found = 1'h1; - next_0_valid_high = 5'h1; - next_0_valid_high_done = 1'h1; - end - end - end - if (~next_0_valid_high_done) begin - if (next_0_valid_d1 < 5'h2) begin - if (valid_mask[2] == 1'h0) begin - next_0_valid_high_found = 1'h1; - next_0_valid_high = 5'h2; - next_0_valid_high_done = 1'h1; - end - end - end - if (~next_0_valid_high_done) begin - if (next_0_valid_d1 < 5'h3) begin - if (valid_mask[3] == 1'h0) begin - next_0_valid_high_found = 1'h1; - next_0_valid_high = 5'h3; - next_0_valid_high_done = 1'h1; - end - end - end - if (~next_0_valid_high_done) begin - if (next_0_valid_d1 < 5'h4) begin - if (valid_mask[4] == 1'h0) begin - next_0_valid_high_found = 1'h1; - next_0_valid_high = 5'h4; - next_0_valid_high_done = 1'h1; - end - end - end - if (~next_0_valid_high_done) begin - if (next_0_valid_d1 < 5'h5) begin - if (valid_mask[5] == 1'h0) begin - next_0_valid_high_found = 1'h1; - next_0_valid_high = 5'h5; - next_0_valid_high_done = 1'h1; - end - end - end - if (~next_0_valid_high_done) begin - if (next_0_valid_d1 < 5'h6) begin - if (valid_mask[6] == 1'h0) begin - next_0_valid_high_found = 1'h1; - next_0_valid_high = 5'h6; - next_0_valid_high_done = 1'h1; - end - end - end - if (~next_0_valid_high_done) begin - if (next_0_valid_d1 < 5'h7) begin - if (valid_mask[7] == 1'h0) begin - next_0_valid_high_found = 1'h1; - next_0_valid_high = 5'h7; - next_0_valid_high_done = 1'h1; - end - end - end - if (~next_0_valid_high_done) begin - if (next_0_valid_d1 < 5'h8) begin - if (valid_mask[8] == 1'h0) begin - next_0_valid_high_found = 1'h1; - next_0_valid_high = 5'h8; - next_0_valid_high_done = 1'h1; - end - end - end - if (~next_0_valid_high_done) begin - if (next_0_valid_d1 < 5'h9) begin - if (valid_mask[9] == 1'h0) begin - next_0_valid_high_found = 1'h1; - next_0_valid_high = 5'h9; - next_0_valid_high_done = 1'h1; - end - end - end - if (~next_0_valid_high_done) begin - if (next_0_valid_d1 < 5'hA) begin - if (valid_mask[10] == 1'h0) begin - next_0_valid_high_found = 1'h1; - next_0_valid_high = 5'hA; - next_0_valid_high_done = 1'h1; - end - end - end - if (~next_0_valid_high_done) begin - if (next_0_valid_d1 < 5'hB) begin - if (valid_mask[11] == 1'h0) begin - next_0_valid_high_found = 1'h1; - next_0_valid_high = 5'hB; - next_0_valid_high_done = 1'h1; - end - end - end - if (~next_0_valid_high_done) begin - if (next_0_valid_d1 < 5'hC) begin - if (valid_mask[12] == 1'h0) begin - next_0_valid_high_found = 1'h1; - next_0_valid_high = 5'hC; - next_0_valid_high_done = 1'h1; - end - end - end - if (~next_0_valid_high_done) begin - if (next_0_valid_d1 < 5'hD) begin - if (valid_mask[13] == 1'h0) begin - next_0_valid_high_found = 1'h1; - next_0_valid_high = 5'hD; - next_0_valid_high_done = 1'h1; - end - end - end - if (~next_0_valid_high_done) begin - if (next_0_valid_d1 < 5'hE) begin - if (valid_mask[14] == 1'h0) begin - next_0_valid_high_found = 1'h1; - next_0_valid_high = 5'hE; - next_0_valid_high_done = 1'h1; - end - end - end - if (~next_0_valid_high_done) begin - if (next_0_valid_d1 < 5'hF) begin - if (valid_mask[15] == 1'h0) begin - next_0_valid_high_found = 1'h1; - next_0_valid_high = 5'hF; - next_0_valid_high_done = 1'h1; - end - end - end - if (~next_0_valid_high_done) begin - if (next_0_valid_d1 < 5'h10) begin - if (valid_mask[16] == 1'h0) begin - next_0_valid_high_found = 1'h1; - next_0_valid_high = 5'h10; - next_0_valid_high_done = 1'h1; - end - end - end - if (~next_0_valid_high_done) begin - if (next_0_valid_d1 < 5'h11) begin - if (valid_mask[17] == 1'h0) begin - next_0_valid_high_found = 1'h1; - next_0_valid_high = 5'h11; - next_0_valid_high_done = 1'h1; - end - end - end - if (~next_0_valid_high_done) begin - if (next_0_valid_d1 < 5'h12) begin - if (valid_mask[18] == 1'h0) begin - next_0_valid_high_found = 1'h1; - next_0_valid_high = 5'h12; - next_0_valid_high_done = 1'h1; - end - end - end - if (~next_0_valid_high_done) begin - if (next_0_valid_d1 < 5'h13) begin - if (valid_mask[19] == 1'h0) begin - next_0_valid_high_found = 1'h1; - next_0_valid_high = 5'h13; - next_0_valid_high_done = 1'h1; - end - end - end - if (~next_0_valid_high_done) begin - if (next_0_valid_d1 < 5'h14) begin - if (valid_mask[20] == 1'h0) begin - next_0_valid_high_found = 1'h1; - next_0_valid_high = 5'h14; - next_0_valid_high_done = 1'h1; - end - end - end - if (~next_0_valid_high_done) begin - if (next_0_valid_d1 < 5'h15) begin - if (valid_mask[21] == 1'h0) begin - next_0_valid_high_found = 1'h1; - next_0_valid_high = 5'h15; - next_0_valid_high_done = 1'h1; - end - end - end - if (~next_0_valid_high_done) begin - if (next_0_valid_d1 < 5'h16) begin - if (valid_mask[22] == 1'h0) begin - next_0_valid_high_found = 1'h1; - next_0_valid_high = 5'h16; - next_0_valid_high_done = 1'h1; - end - end - end - if (~next_0_valid_high_done) begin - if (next_0_valid_d1 < 5'h17) begin - if (valid_mask[23] == 1'h0) begin - next_0_valid_high_found = 1'h1; - next_0_valid_high = 5'h17; - next_0_valid_high_done = 1'h1; - end - end - end - if (~next_0_valid_high_done) begin - if (next_0_valid_d1 < 5'h18) begin - if (valid_mask[24] == 1'h0) begin - next_0_valid_high_found = 1'h1; - next_0_valid_high = 5'h18; - next_0_valid_high_done = 1'h1; - end - end - end - if (~next_0_valid_high_done) begin - if (next_0_valid_d1 < 5'h19) begin - if (valid_mask[25] == 1'h0) begin - next_0_valid_high_found = 1'h1; - next_0_valid_high = 5'h19; - next_0_valid_high_done = 1'h1; - end - end - end - if (~next_0_valid_high_done) begin - if (next_0_valid_d1 < 5'h1A) begin - if (valid_mask[26] == 1'h0) begin - next_0_valid_high_found = 1'h1; - next_0_valid_high = 5'h1A; - next_0_valid_high_done = 1'h1; - end - end - end - if (~next_0_valid_high_done) begin - if (next_0_valid_d1 < 5'h1B) begin - if (valid_mask[27] == 1'h0) begin - next_0_valid_high_found = 1'h1; - next_0_valid_high = 5'h1B; - next_0_valid_high_done = 1'h1; - end - end - end - if (~next_0_valid_high_done) begin - if (next_0_valid_d1 < 5'h1C) begin - if (valid_mask[28] == 1'h0) begin - next_0_valid_high_found = 1'h1; - next_0_valid_high = 5'h1C; - next_0_valid_high_done = 1'h1; - end - end - end - if (~next_0_valid_high_done) begin - if (next_0_valid_d1 < 5'h1D) begin - if (valid_mask[29] == 1'h0) begin - next_0_valid_high_found = 1'h1; - next_0_valid_high = 5'h1D; - next_0_valid_high_done = 1'h1; - end - end - end - if (~next_0_valid_high_done) begin - if (next_0_valid_d1 < 5'h1E) begin - if (valid_mask[30] == 1'h0) begin - next_0_valid_high_found = 1'h1; - next_0_valid_high = 5'h1E; - next_0_valid_high_done = 1'h1; - end - end - end - if (~next_0_valid_high_done) begin - if (next_0_valid_d1 < 5'h1F) begin - if (valid_mask[31] == 1'h0) begin - next_0_valid_high_found = 1'h1; - next_0_valid_high = 5'h1F; - next_0_valid_high_done = 1'h1; - end - end - end -end -always_comb begin - next_0_valid_low_found = 1'h0; - next_0_valid_low = 5'h0; - next_0_valid_low_done = 1'h0; - if (~next_0_valid_low_done) begin - if (next_0_valid_d1 > 5'h0) begin - if (valid_mask[0] == 1'h0) begin - next_0_valid_low_found = 1'h1; - next_0_valid_low = 5'h0; - next_0_valid_low_done = 1'h1; - end - end - end - if (~next_0_valid_low_done) begin - if (next_0_valid_d1 > 5'h1) begin - if (valid_mask[1] == 1'h0) begin - next_0_valid_low_found = 1'h1; - next_0_valid_low = 5'h1; - next_0_valid_low_done = 1'h1; - end - end - end - if (~next_0_valid_low_done) begin - if (next_0_valid_d1 > 5'h2) begin - if (valid_mask[2] == 1'h0) begin - next_0_valid_low_found = 1'h1; - next_0_valid_low = 5'h2; - next_0_valid_low_done = 1'h1; - end - end - end - if (~next_0_valid_low_done) begin - if (next_0_valid_d1 > 5'h3) begin - if (valid_mask[3] == 1'h0) begin - next_0_valid_low_found = 1'h1; - next_0_valid_low = 5'h3; - next_0_valid_low_done = 1'h1; - end - end - end - if (~next_0_valid_low_done) begin - if (next_0_valid_d1 > 5'h4) begin - if (valid_mask[4] == 1'h0) begin - next_0_valid_low_found = 1'h1; - next_0_valid_low = 5'h4; - next_0_valid_low_done = 1'h1; - end - end - end - if (~next_0_valid_low_done) begin - if (next_0_valid_d1 > 5'h5) begin - if (valid_mask[5] == 1'h0) begin - next_0_valid_low_found = 1'h1; - next_0_valid_low = 5'h5; - next_0_valid_low_done = 1'h1; - end - end - end - if (~next_0_valid_low_done) begin - if (next_0_valid_d1 > 5'h6) begin - if (valid_mask[6] == 1'h0) begin - next_0_valid_low_found = 1'h1; - next_0_valid_low = 5'h6; - next_0_valid_low_done = 1'h1; - end - end - end - if (~next_0_valid_low_done) begin - if (next_0_valid_d1 > 5'h7) begin - if (valid_mask[7] == 1'h0) begin - next_0_valid_low_found = 1'h1; - next_0_valid_low = 5'h7; - next_0_valid_low_done = 1'h1; - end - end - end - if (~next_0_valid_low_done) begin - if (next_0_valid_d1 > 5'h8) begin - if (valid_mask[8] == 1'h0) begin - next_0_valid_low_found = 1'h1; - next_0_valid_low = 5'h8; - next_0_valid_low_done = 1'h1; - end - end - end - if (~next_0_valid_low_done) begin - if (next_0_valid_d1 > 5'h9) begin - if (valid_mask[9] == 1'h0) begin - next_0_valid_low_found = 1'h1; - next_0_valid_low = 5'h9; - next_0_valid_low_done = 1'h1; - end - end - end - if (~next_0_valid_low_done) begin - if (next_0_valid_d1 > 5'hA) begin - if (valid_mask[10] == 1'h0) begin - next_0_valid_low_found = 1'h1; - next_0_valid_low = 5'hA; - next_0_valid_low_done = 1'h1; - end - end - end - if (~next_0_valid_low_done) begin - if (next_0_valid_d1 > 5'hB) begin - if (valid_mask[11] == 1'h0) begin - next_0_valid_low_found = 1'h1; - next_0_valid_low = 5'hB; - next_0_valid_low_done = 1'h1; - end - end - end - if (~next_0_valid_low_done) begin - if (next_0_valid_d1 > 5'hC) begin - if (valid_mask[12] == 1'h0) begin - next_0_valid_low_found = 1'h1; - next_0_valid_low = 5'hC; - next_0_valid_low_done = 1'h1; - end - end - end - if (~next_0_valid_low_done) begin - if (next_0_valid_d1 > 5'hD) begin - if (valid_mask[13] == 1'h0) begin - next_0_valid_low_found = 1'h1; - next_0_valid_low = 5'hD; - next_0_valid_low_done = 1'h1; - end - end - end - if (~next_0_valid_low_done) begin - if (next_0_valid_d1 > 5'hE) begin - if (valid_mask[14] == 1'h0) begin - next_0_valid_low_found = 1'h1; - next_0_valid_low = 5'hE; - next_0_valid_low_done = 1'h1; - end - end - end - if (~next_0_valid_low_done) begin - if (next_0_valid_d1 > 5'hF) begin - if (valid_mask[15] == 1'h0) begin - next_0_valid_low_found = 1'h1; - next_0_valid_low = 5'hF; - next_0_valid_low_done = 1'h1; - end - end - end - if (~next_0_valid_low_done) begin - if (next_0_valid_d1 > 5'h10) begin - if (valid_mask[16] == 1'h0) begin - next_0_valid_low_found = 1'h1; - next_0_valid_low = 5'h10; - next_0_valid_low_done = 1'h1; - end - end - end - if (~next_0_valid_low_done) begin - if (next_0_valid_d1 > 5'h11) begin - if (valid_mask[17] == 1'h0) begin - next_0_valid_low_found = 1'h1; - next_0_valid_low = 5'h11; - next_0_valid_low_done = 1'h1; - end - end - end - if (~next_0_valid_low_done) begin - if (next_0_valid_d1 > 5'h12) begin - if (valid_mask[18] == 1'h0) begin - next_0_valid_low_found = 1'h1; - next_0_valid_low = 5'h12; - next_0_valid_low_done = 1'h1; - end - end - end - if (~next_0_valid_low_done) begin - if (next_0_valid_d1 > 5'h13) begin - if (valid_mask[19] == 1'h0) begin - next_0_valid_low_found = 1'h1; - next_0_valid_low = 5'h13; - next_0_valid_low_done = 1'h1; - end - end - end - if (~next_0_valid_low_done) begin - if (next_0_valid_d1 > 5'h14) begin - if (valid_mask[20] == 1'h0) begin - next_0_valid_low_found = 1'h1; - next_0_valid_low = 5'h14; - next_0_valid_low_done = 1'h1; - end - end - end - if (~next_0_valid_low_done) begin - if (next_0_valid_d1 > 5'h15) begin - if (valid_mask[21] == 1'h0) begin - next_0_valid_low_found = 1'h1; - next_0_valid_low = 5'h15; - next_0_valid_low_done = 1'h1; - end - end - end - if (~next_0_valid_low_done) begin - if (next_0_valid_d1 > 5'h16) begin - if (valid_mask[22] == 1'h0) begin - next_0_valid_low_found = 1'h1; - next_0_valid_low = 5'h16; - next_0_valid_low_done = 1'h1; - end - end - end - if (~next_0_valid_low_done) begin - if (next_0_valid_d1 > 5'h17) begin - if (valid_mask[23] == 1'h0) begin - next_0_valid_low_found = 1'h1; - next_0_valid_low = 5'h17; - next_0_valid_low_done = 1'h1; - end - end - end - if (~next_0_valid_low_done) begin - if (next_0_valid_d1 > 5'h18) begin - if (valid_mask[24] == 1'h0) begin - next_0_valid_low_found = 1'h1; - next_0_valid_low = 5'h18; - next_0_valid_low_done = 1'h1; - end - end - end - if (~next_0_valid_low_done) begin - if (next_0_valid_d1 > 5'h19) begin - if (valid_mask[25] == 1'h0) begin - next_0_valid_low_found = 1'h1; - next_0_valid_low = 5'h19; - next_0_valid_low_done = 1'h1; - end - end - end - if (~next_0_valid_low_done) begin - if (next_0_valid_d1 > 5'h1A) begin - if (valid_mask[26] == 1'h0) begin - next_0_valid_low_found = 1'h1; - next_0_valid_low = 5'h1A; - next_0_valid_low_done = 1'h1; - end - end - end - if (~next_0_valid_low_done) begin - if (next_0_valid_d1 > 5'h1B) begin - if (valid_mask[27] == 1'h0) begin - next_0_valid_low_found = 1'h1; - next_0_valid_low = 5'h1B; - next_0_valid_low_done = 1'h1; - end - end - end - if (~next_0_valid_low_done) begin - if (next_0_valid_d1 > 5'h1C) begin - if (valid_mask[28] == 1'h0) begin - next_0_valid_low_found = 1'h1; - next_0_valid_low = 5'h1C; - next_0_valid_low_done = 1'h1; - end - end - end - if (~next_0_valid_low_done) begin - if (next_0_valid_d1 > 5'h1D) begin - if (valid_mask[29] == 1'h0) begin - next_0_valid_low_found = 1'h1; - next_0_valid_low = 5'h1D; - next_0_valid_low_done = 1'h1; - end - end - end - if (~next_0_valid_low_done) begin - if (next_0_valid_d1 > 5'h1E) begin - if (valid_mask[30] == 1'h0) begin - next_0_valid_low_found = 1'h1; - next_0_valid_low = 5'h1E; - next_0_valid_low_done = 1'h1; - end - end - end - if (~next_0_valid_low_done) begin - if (next_0_valid_d1 > 5'h1F) begin - if (valid_mask[31] == 1'h0) begin - next_0_valid_low_found = 1'h1; - next_0_valid_low = 5'h1F; - next_0_valid_low_done = 1'h1; - end - end - end -end -assign inc_reserve_count = write_alloc & (~write_fill); - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - reserve_count <= 16'h0; - end - else if (flush) begin - reserve_count <= 16'h0; - end - else if (clk_en) begin - if (clk_en) begin - if (inc_reserve_count) begin - reserve_count <= reserve_count + 16'h1; - end - end - end -end -endmodule // reservation_fifo_depth_32_w_17_num_per_1 - -module reservation_fifo_depth_8_w_17_num_per_2 ( - input logic clk, - input logic clk_en, - input logic [16:0] data_in_0, - input logic [16:0] data_in_1, - input logic [16:0] fill_data_in, - input logic flush, - input logic pop, - input logic push_alloc, - input logic push_fill, - input logic push_reserve, - input logic rst_n, - output logic [16:0] data_out_0, - output logic [16:0] data_out_1, - output logic empty, - output logic full, - output logic valid -); - -logic clr_item_ptr; -logic clr_read_ptr; -logic clr_write_ptr; -logic [1:0][16:0] data_in_packed; -logic [1:0][16:0] data_out; -logic enable_reserve_ptr; -logic inc_item_ptr; -logic inc_read_ptr; -logic inc_reserve_count; -logic inc_write_ptr; -logic item_ptr_addr; -logic jump_next_0; -logic [2:0] next_0_valid; -logic [2:0] next_0_valid_d1; -logic [2:0] next_0_valid_high; -logic next_0_valid_high_done; -logic next_0_valid_high_found; -logic [2:0] next_0_valid_low; -logic next_0_valid_low_done; -logic next_0_valid_low_found; -logic [3:0] num_items; -logic read; -logic [2:0] read_ptr_addr; -logic [7:0][1:0][16:0] reg_array; -logic [15:0] reserve_count; -logic [2:0] reserve_ptr_val; -logic [7:0] valid_mask; -logic write_alloc; -logic write_fill; -logic [2:0] write_ptr_addr; -logic write_reserve; -logic write_reserve_final; -assign data_in_packed[0] = data_in_0; -assign data_in_packed[1] = data_in_1; -assign data_out_0 = data_out[0]; -assign data_out_1 = data_out[1]; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - item_ptr_addr <= 1'h0; - end - else if (flush) begin - item_ptr_addr <= 1'h0; - end - else if (clk_en) begin - if (clk_en) begin - if (clr_item_ptr) begin - item_ptr_addr <= 1'h0; - end - else if (inc_item_ptr) begin - item_ptr_addr <= item_ptr_addr + 1'h1; - end - end - end -end -assign inc_item_ptr = push_reserve; -assign clr_item_ptr = push_reserve & (item_ptr_addr == 1'h1); - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - read_ptr_addr <= 3'h0; - end - else if (flush) begin - read_ptr_addr <= 3'h0; - end - else if (clk_en) begin - if (clk_en) begin - if (clr_read_ptr) begin - read_ptr_addr <= 3'h0; - end - else if (inc_read_ptr) begin - read_ptr_addr <= read_ptr_addr + 3'h1; - end - end - end -end -assign inc_read_ptr = read; -assign clr_read_ptr = 1'h0; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - write_ptr_addr <= 3'h0; - end - else if (flush) begin - write_ptr_addr <= 3'h0; - end - else if (clk_en) begin - if (clk_en) begin - if (clr_write_ptr) begin - write_ptr_addr <= 3'h0; - end - else if (inc_write_ptr) begin - write_ptr_addr <= write_ptr_addr + 3'h1; - end - end - end -end -assign inc_write_ptr = write_alloc | write_fill; -assign clr_write_ptr = 1'h0; -assign jump_next_0 = next_0_valid_high_found | next_0_valid_low_found; -assign enable_reserve_ptr = write_reserve_final | (write_fill & (reserve_ptr_val == write_ptr_addr)); - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - next_0_valid_d1 <= 3'h0; - end - else if (flush) begin - next_0_valid_d1 <= 3'h0; - end - else if (clk_en) begin - if (clk_en) begin - if (1'h0) begin - next_0_valid_d1 <= 3'h0; - end - else if (enable_reserve_ptr) begin - next_0_valid_d1 <= next_0_valid; - end - end - end -end -assign reserve_ptr_val = next_0_valid_d1; -assign next_0_valid = (write_fill & ((next_0_valid_d1 == write_ptr_addr) | ((~next_0_valid_high_found) - & (~next_0_valid_low_found)) | (next_0_valid_high_found ? next_0_valid_high == - write_ptr_addr: next_0_valid_low == write_ptr_addr))) ? write_ptr_addr + 3'h1: - ((~next_0_valid_high_found) & (~next_0_valid_low_found)) ? write_ptr_addr: - next_0_valid_high_found ? next_0_valid_high: next_0_valid_low; -assign full = num_items == 4'h8; -assign empty = num_items == 4'h0; -assign write_fill = push_fill & push_alloc & (~full); -assign write_alloc = push_alloc & (~full); -assign write_reserve = inc_item_ptr; -assign write_reserve_final = clr_item_ptr; -assign read = pop & valid_mask[read_ptr_addr]; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - num_items <= 4'h0; - end - else if (flush) begin - num_items <= 4'h0; - end - else if (clk_en) begin - if (clk_en) begin - if (write_alloc & (~read)) begin - num_items <= num_items + 4'h1; - end - else if ((~write_alloc) & read) begin - num_items <= num_items - 4'h1; - end - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - reg_array <= 272'h0; - end - else if (flush) begin - reg_array <= 272'h0; - end - else if (clk_en) begin - if (clk_en) begin - if (write_fill) begin - reg_array[write_ptr_addr][0] <= fill_data_in; - end - if (write_reserve) begin - reg_array[next_0_valid_d1][item_ptr_addr] <= data_in_packed[item_ptr_addr]; - end - end - end -end -always_comb begin - data_out = reg_array[read_ptr_addr]; -end -always_comb begin - valid = valid_mask[read_ptr_addr]; -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - valid_mask <= 8'h0; - end - else if (flush) begin - valid_mask <= 8'h0; - end - else if (clk_en) begin - if (clk_en) begin - if (write_fill) begin - valid_mask[write_ptr_addr] <= 1'h1; - end - if (write_reserve_final) begin - valid_mask[next_0_valid_d1] <= 1'h1; - end - if (read) begin - valid_mask[read_ptr_addr] <= 1'h0; - end - end - end -end -always_comb begin - next_0_valid_high_found = 1'h0; - next_0_valid_high = 3'h0; - next_0_valid_high_done = 1'h0; - if (~next_0_valid_high_done) begin - if (next_0_valid_d1 < 3'h0) begin - if (valid_mask[0] == 1'h0) begin - next_0_valid_high_found = 1'h1; - next_0_valid_high = 3'h0; - next_0_valid_high_done = 1'h1; - end - end - end - if (~next_0_valid_high_done) begin - if (next_0_valid_d1 < 3'h1) begin - if (valid_mask[1] == 1'h0) begin - next_0_valid_high_found = 1'h1; - next_0_valid_high = 3'h1; - next_0_valid_high_done = 1'h1; - end - end - end - if (~next_0_valid_high_done) begin - if (next_0_valid_d1 < 3'h2) begin - if (valid_mask[2] == 1'h0) begin - next_0_valid_high_found = 1'h1; - next_0_valid_high = 3'h2; - next_0_valid_high_done = 1'h1; - end - end - end - if (~next_0_valid_high_done) begin - if (next_0_valid_d1 < 3'h3) begin - if (valid_mask[3] == 1'h0) begin - next_0_valid_high_found = 1'h1; - next_0_valid_high = 3'h3; - next_0_valid_high_done = 1'h1; - end - end - end - if (~next_0_valid_high_done) begin - if (next_0_valid_d1 < 3'h4) begin - if (valid_mask[4] == 1'h0) begin - next_0_valid_high_found = 1'h1; - next_0_valid_high = 3'h4; - next_0_valid_high_done = 1'h1; - end - end - end - if (~next_0_valid_high_done) begin - if (next_0_valid_d1 < 3'h5) begin - if (valid_mask[5] == 1'h0) begin - next_0_valid_high_found = 1'h1; - next_0_valid_high = 3'h5; - next_0_valid_high_done = 1'h1; - end - end - end - if (~next_0_valid_high_done) begin - if (next_0_valid_d1 < 3'h6) begin - if (valid_mask[6] == 1'h0) begin - next_0_valid_high_found = 1'h1; - next_0_valid_high = 3'h6; - next_0_valid_high_done = 1'h1; - end - end - end - if (~next_0_valid_high_done) begin - if (next_0_valid_d1 < 3'h7) begin - if (valid_mask[7] == 1'h0) begin - next_0_valid_high_found = 1'h1; - next_0_valid_high = 3'h7; - next_0_valid_high_done = 1'h1; - end - end - end -end -always_comb begin - next_0_valid_low_found = 1'h0; - next_0_valid_low = 3'h0; - next_0_valid_low_done = 1'h0; - if (~next_0_valid_low_done) begin - if (next_0_valid_d1 > 3'h0) begin - if (valid_mask[0] == 1'h0) begin - next_0_valid_low_found = 1'h1; - next_0_valid_low = 3'h0; - next_0_valid_low_done = 1'h1; - end - end - end - if (~next_0_valid_low_done) begin - if (next_0_valid_d1 > 3'h1) begin - if (valid_mask[1] == 1'h0) begin - next_0_valid_low_found = 1'h1; - next_0_valid_low = 3'h1; - next_0_valid_low_done = 1'h1; - end - end - end - if (~next_0_valid_low_done) begin - if (next_0_valid_d1 > 3'h2) begin - if (valid_mask[2] == 1'h0) begin - next_0_valid_low_found = 1'h1; - next_0_valid_low = 3'h2; - next_0_valid_low_done = 1'h1; - end - end - end - if (~next_0_valid_low_done) begin - if (next_0_valid_d1 > 3'h3) begin - if (valid_mask[3] == 1'h0) begin - next_0_valid_low_found = 1'h1; - next_0_valid_low = 3'h3; - next_0_valid_low_done = 1'h1; - end - end - end - if (~next_0_valid_low_done) begin - if (next_0_valid_d1 > 3'h4) begin - if (valid_mask[4] == 1'h0) begin - next_0_valid_low_found = 1'h1; - next_0_valid_low = 3'h4; - next_0_valid_low_done = 1'h1; - end - end - end - if (~next_0_valid_low_done) begin - if (next_0_valid_d1 > 3'h5) begin - if (valid_mask[5] == 1'h0) begin - next_0_valid_low_found = 1'h1; - next_0_valid_low = 3'h5; - next_0_valid_low_done = 1'h1; - end - end - end - if (~next_0_valid_low_done) begin - if (next_0_valid_d1 > 3'h6) begin - if (valid_mask[6] == 1'h0) begin - next_0_valid_low_found = 1'h1; - next_0_valid_low = 3'h6; - next_0_valid_low_done = 1'h1; - end - end - end - if (~next_0_valid_low_done) begin - if (next_0_valid_d1 > 3'h7) begin - if (valid_mask[7] == 1'h0) begin - next_0_valid_low_found = 1'h1; - next_0_valid_low = 3'h7; - next_0_valid_low_done = 1'h1; - end - end - end -end -assign inc_reserve_count = write_alloc & (~write_fill); - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - reserve_count <= 16'h0; - end - else if (flush) begin - reserve_count <= 16'h0; - end - else if (clk_en) begin - if (clk_en) begin - if (inc_reserve_count) begin - reserve_count <= reserve_count + 16'h1; - end - end - end -end -endmodule // reservation_fifo_depth_8_w_17_num_per_2 - -module scanner_pipe ( - input logic addr_out_0_ready, - input logic addr_out_1_ready, - input logic block_mode, - input logic block_rd_out_ready, - input logic clk, - input logic clk_en, - input logic coord_out_ready, - input logic dense, - input logic [15:0] dim_size, - input logic do_repeat, - input logic flush, - input logic [15:0] inner_dim_offset, - input logic lookup, - input logic op_out_0_ready, - input logic op_out_1_ready, - input logic output_matrix_fully_accumulated, - input logic output_row_fully_accumulated, - input logic pos_out_ready, - input logic [16:0] pos_to_read_scanner_from_vr_fsm, - input logic [0:0] [16:0] rd_rsp_data_in_0, - input logic rd_rsp_data_in_0_valid, - input logic [0:0] [16:0] rd_rsp_data_in_1, - input logic rd_rsp_data_in_1_valid, - input logic [15:0] repeat_factor, - input logic repeat_outer_inner_n, - input logic root, - input logic rst_n, - input logic tile_en, - input logic [16:0] us_pos_in, - input logic us_pos_in_valid, - input logic vector_reduce_mode, - input logic vr_fsm_state_init_blank_DONE, - input logic vr_fsm_state_init_blank_S0, - output logic [0:0] [16:0] addr_out_0, - output logic addr_out_0_valid, - output logic [0:0] [16:0] addr_out_1, - output logic addr_out_1_valid, - output logic [16:0] block_rd_out, - output logic block_rd_out_valid, - output logic [16:0] coord_out, - output logic coord_out_valid, - output logic [0:0] [16:0] op_out_0, - output logic op_out_0_valid, - output logic [0:0] [16:0] op_out_1, - output logic op_out_1_valid, - output logic [16:0] pos_out, - output logic pos_out_valid, - output logic rd_rsp_data_in_0_ready, - output logic rd_rsp_data_in_1_ready, - output logic rs_has_prepped_ds_row, - output logic us_pos_in_ready -); - -typedef enum logic[3:0] { - BLOCK_1_RD = 4'h0, - BLOCK_1_SIZE_REC = 4'h1, - BLOCK_1_SIZE_REQ = 4'h2, - BLOCK_2_RD = 4'h3, - BLOCK_2_SIZE_REC = 4'h4, - BLOCK_2_SIZE_REQ = 4'h5, - DENSE_STRM = 4'h6, - DONE_CRD = 4'h7, - FREE_CRD = 4'h8, - FREE_CRD2 = 4'h9, - PASS_DONE_CRD = 4'hA, - READOUT_SYNC_LOCK = 4'hB, - SEQ_STRM = 4'hC, - START_CRD = 4'hD -} scan_seq_crd_state; -typedef enum logic[3:0] { - DONE_SEG = 4'h0, - FREE_SEG = 4'h1, - INJECT_0 = 4'h2, - INJECT_DONE = 4'h3, - INJECT_ROUTING = 4'h4, - LOOKUP = 4'h5, - PASS_DONE_SEG = 4'h6, - PASS_STOP_SEG = 4'h7, - READ = 4'h8, - READ_ALT = 4'h9, - START_SEG = 4'hA -} scan_seq_seg_state; -logic [15:0] READS_MADE; -logic [15:0] READS_REC_CRD_READ; -logic [16:0] S_level_0; -logic [0:0][16:0] addr_out_fifo_0_data_in; -logic addr_out_fifo_0_empty; -logic addr_out_fifo_0_full; -logic addr_out_fifo_0_push; -logic [0:0][16:0] addr_out_fifo_1_data_in; -logic addr_out_fifo_1_empty; -logic addr_out_fifo_1_full; -logic addr_out_fifo_1_push; -logic [0:0][15:0] addr_out_to_fifo_0; -logic [0:0][15:0] addr_out_to_fifo_1; -logic [1:0] base_rr_0; -logic [1:0] base_rr_1; -logic block_rd_fifo_empty; -logic block_rd_fifo_full; -logic block_rd_fifo_push; -logic clr_fiber_addr; -logic clr_final_pushed_done; -logic clr_pop_infifo_sticky; -logic clr_pushed_done_crd; -logic clr_pushed_done_seg; -logic clr_readout_loop_crd; -logic clr_readout_loop_seg; -logic clr_rep; -logic clr_req_made_crd; -logic clr_req_made_seg; -logic clr_req_rec_crd; -logic clr_req_rec_seg; -logic clr_seen_root_eos; -logic clr_used_data; -logic [16:0] coord_fifo_in_packed; -logic [16:0] coord_fifo_out_packed; -logic coord_fifo_push; -logic coordinate_fifo_empty; -logic coordinate_fifo_full; -logic [0:0][15:0] crd_ID_out_to_fifo; -logic [0:0][15:0] crd_addr_out_to_fifo; -logic crd_grant_push_0; -logic crd_grant_push_1; -logic crd_in_done_state; -logic [0:0][15:0] crd_op_out_to_fifo; -logic [16:0] crd_out_to_fifo; -logic crd_pop_infifo; -logic crd_rd_rsp_fifo_pop; -logic crd_req_push; -logic [16:0] crd_res_fifo_data_in_0; -logic [16:0] crd_res_fifo_data_out; -logic [16:0] crd_res_fifo_fill_data_in; -logic crd_res_fifo_full; -logic crd_res_fifo_pop; -logic crd_res_fifo_push_alloc; -logic crd_res_fifo_push_alloc_0; -logic crd_res_fifo_push_fill; -logic crd_res_fifo_push_fill_0; -logic crd_res_fifo_push_reserve_0; -logic crd_res_fifo_valid; -logic done_in; -logic [16:0] done_token; -logic en_reg_data_in; -logic eos_in; -logic [15:0] fiber_addr; -logic [15:0] fiber_addr_pre; -logic [15:0] fiber_addr_pre_d1; -logic [15:0] fiber_addr_pre_d1_d1; -logic fifo_full; -logic [1:0] fifo_full_pre; -logic [16:0] fifo_out_us_packed; -logic fifo_us_full; -logic [16:0] fifo_us_in_packed; -logic final_pushed_done_sticky_sticky; -logic final_pushed_done_sticky_was_high; -logic gclk; -logic inc_fiber_addr; -logic inc_rep; -logic inc_req_made_crd; -logic inc_req_made_seg; -logic inc_req_rec_crd; -logic inc_req_rec_seg; -logic inc_requests_REC_CRD_READ; -logic inc_requests_made_CRDDD_READ; -logic infifo_eos_in; -logic [15:0] infifo_pos_in; -logic [15:0] infifo_pos_in_d1; -logic infifo_pos_in_d1_en; -logic infifo_valid_in; -logic [0:0][16:0] input_fifo_data_out; -logic input_fifo_empty; -logic iter_finish_sticky; -logic iter_finish_was_high; -logic [16:0] last_stop_token; -logic last_valid_accepting; -logic maybe_in; -logic [15:0] next_seq_addr; -logic [15:0] next_seq_length; -logic no_outfifo_full_0; -logic no_outfifo_full_1; -logic non_vr_coord_fifo_push; -logic non_vr_pos_out_fifo_push; -logic [15:0] num_reps; -logic [15:0] num_req_made_crd; -logic [15:0] num_req_made_seg; -logic [15:0] num_req_rec_crd; -logic [15:0] num_req_rec_seg; -logic [0:0][16:0] op_out_fifo_0_data_in; -logic op_out_fifo_0_empty; -logic op_out_fifo_0_full; -logic op_out_fifo_0_push; -logic [0:0][16:0] op_out_fifo_1_data_in; -logic op_out_fifo_1_empty; -logic op_out_fifo_1_full; -logic op_out_fifo_1_push; -logic [0:0][15:0] op_out_to_fifo_0; -logic [0:0][15:0] op_out_to_fifo_1; -logic [15:0] payload_ptr; -logic pop_infifo; -logic pop_infifo_sticky_sticky; -logic pop_infifo_sticky_was_high; -logic [15:0] pos_addr; -logic pos_fifo_empty; -logic pos_fifo_full; -logic [16:0] pos_fifo_in_packed; -logic [16:0] pos_fifo_out_packed; -logic pos_out_fifo_push; -logic [16:0] pos_out_to_fifo; -logic pos_out_valid_mux_sel; -logic [15:0] ptr_in; -logic [15:0] ptr_in_d1; -logic ptr_reg_en; -logic pushed_done_sticky_sticky; -logic pushed_done_sticky_was_high; -logic rd_rsp_fifo_0_empty; -logic rd_rsp_fifo_0_full; -logic [16:0] rd_rsp_fifo_0_out_data; -logic [16:0] rd_rsp_fifo_0_out_data_d1; -logic rd_rsp_fifo_0_valid; -logic rd_rsp_fifo_1_empty; -logic rd_rsp_fifo_1_full; -logic [16:0] rd_rsp_fifo_1_out_data; -logic rd_rsp_fifo_1_valid; -logic readout_dst_crd; -logic readout_dst_seg; -logic readout_loop_sticky_sticky; -logic readout_loop_sticky_was_high; -logic rep_finish_sticky; -logic rep_finish_was_high; -logic [1:0] rr_arbiter_0_grant_out; -logic [1:0] rr_arbiter_1_grant_out; -logic rs_has_prepped_ds_row_sticky_sticky; -logic rs_has_prepped_ds_row_sticky_was_high; -scan_seq_crd_state scan_seq_crd_current_state; -scan_seq_crd_state scan_seq_crd_next_state; -scan_seq_seg_state scan_seq_seg_current_state; -scan_seq_seg_state scan_seq_seg_next_state; -logic seen_root_eos_sticky; -logic seen_root_eos_was_high; -logic [0:0][15:0] seg_ID_out_to_fifo; -logic [0:0][15:0] seg_addr_out_to_fifo; -logic seg_grant_push_0; -logic seg_grant_push_1; -logic seg_in_done_state; -logic seg_in_start_state; -logic [0:0][15:0] seg_op_out_to_fifo; -logic seg_pop_infifo; -logic seg_rd_rsp_fifo_pop; -logic seg_req_push; -logic [16:0] seg_res_fifo_data_out_0; -logic [16:0] seg_res_fifo_data_out_1; -logic seg_res_fifo_done_out; -logic [16:0] seg_res_fifo_fill_data_in; -logic seg_res_fifo_full; -logic seg_res_fifo_pop; -logic seg_res_fifo_pop_0; -logic seg_res_fifo_push_alloc; -logic seg_res_fifo_push_alloc_0; -logic seg_res_fifo_push_fill; -logic seg_res_fifo_push_fill_0; -logic seg_res_fifo_push_reserve_0; -logic seg_res_fifo_valid; -logic [15:0] seq_addr; -logic [15:0] seq_length; -logic [15:0] seq_length_ptr_math; -logic set_final_pushed_done; -logic set_pushed_done_crd; -logic set_pushed_done_seg; -logic set_readout_loop_crd; -logic set_readout_loop_seg; -logic update_seq_state; -logic [15:0] us_fifo_inject_data; -logic us_fifo_inject_eos; -logic us_fifo_inject_push; -logic us_fifo_push; -logic use_data_sticky_sticky; -logic use_data_sticky_was_high; -logic [15:0] valid_cnt; -logic valid_inc; -logic valid_rst; -assign gclk = clk & tile_en; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - fiber_addr_pre <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - fiber_addr_pre <= 16'h0; - end - else if (clr_fiber_addr) begin - fiber_addr_pre <= 16'h0; - end - else if (inc_fiber_addr) begin - fiber_addr_pre <= fiber_addr_pre + 16'h1; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - num_reps <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - num_reps <= 16'h0; - end - else if (clr_rep) begin - num_reps <= 16'h0; - end - else if (inc_rep) begin - num_reps <= num_reps + 16'h1; - end - end -end -assign fifo_us_in_packed[16] = root ? us_fifo_inject_eos: us_pos_in[16]; -assign fifo_us_in_packed[15:0] = root ? us_fifo_inject_data: us_pos_in[15:0]; -assign us_fifo_push = root ? us_fifo_inject_push: us_pos_in_valid; -assign infifo_eos_in = fifo_out_us_packed[16]; -assign infifo_pos_in = fifo_out_us_packed[15:0]; -assign pop_infifo = seg_pop_infifo | crd_pop_infifo; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - pop_infifo_sticky_was_high <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - pop_infifo_sticky_was_high <= 1'h0; - end - else if (clr_pop_infifo_sticky) begin - pop_infifo_sticky_was_high <= 1'h0; - end - else if (pop_infifo) begin - pop_infifo_sticky_was_high <= 1'h1; - end - end -end -assign pop_infifo_sticky_sticky = pop_infifo_sticky_was_high; -assign fifo_out_us_packed = input_fifo_data_out; -assign us_pos_in_ready = ~fifo_us_full; -assign infifo_valid_in = ~input_fifo_empty; -assign rd_rsp_data_in_0_ready = ~rd_rsp_fifo_0_full; -assign rd_rsp_data_in_1_ready = ~rd_rsp_fifo_1_full; -assign rd_rsp_fifo_0_valid = ~rd_rsp_fifo_0_empty; -assign rd_rsp_fifo_1_valid = ~rd_rsp_fifo_1_empty; -assign no_outfifo_full_0 = ~(op_out_fifo_0_full | addr_out_fifo_0_full); -assign no_outfifo_full_1 = ~(op_out_fifo_1_full | addr_out_fifo_1_full); -assign base_rr_0 = {crd_req_push & (16'h0 == crd_ID_out_to_fifo), seg_req_push & (16'h0 == - seg_ID_out_to_fifo)}; -assign base_rr_1 = {crd_req_push & (16'h1 == crd_ID_out_to_fifo), seg_req_push & (16'h1 == - seg_ID_out_to_fifo)}; -assign {crd_grant_push_0, seg_grant_push_0} = rr_arbiter_0_grant_out; -assign {crd_grant_push_1, seg_grant_push_1} = rr_arbiter_1_grant_out; -assign addr_out_to_fifo_0 = crd_grant_push_0 ? crd_addr_out_to_fifo: seg_addr_out_to_fifo; -assign addr_out_to_fifo_1 = crd_grant_push_1 ? crd_addr_out_to_fifo: seg_addr_out_to_fifo; -assign op_out_to_fifo_0 = crd_grant_push_0 ? crd_op_out_to_fifo: seg_op_out_to_fifo; -assign op_out_to_fifo_1 = crd_grant_push_1 ? crd_op_out_to_fifo: seg_op_out_to_fifo; -assign addr_out_fifo_0_push = seg_grant_push_0 | crd_grant_push_0; -assign addr_out_fifo_1_push = seg_grant_push_1 | crd_grant_push_1; -assign op_out_fifo_0_push = seg_grant_push_0 | crd_grant_push_0; -assign op_out_fifo_1_push = seg_grant_push_1 | crd_grant_push_1; -assign addr_out_fifo_0_data_in = {1'h0, addr_out_to_fifo_0}; -assign addr_out_fifo_1_data_in = {1'h0, addr_out_to_fifo_1}; -assign addr_out_0_valid = ~addr_out_fifo_0_empty; -assign addr_out_1_valid = ~addr_out_fifo_1_empty; -assign op_out_fifo_0_data_in = {1'h0, op_out_to_fifo_0}; -assign op_out_fifo_1_data_in = {1'h0, op_out_to_fifo_1}; -assign op_out_0_valid = ~op_out_fifo_0_empty; -assign op_out_1_valid = ~op_out_fifo_1_empty; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - pushed_done_sticky_was_high <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - pushed_done_sticky_was_high <= 1'h0; - end - else if (clr_pushed_done_seg | clr_pushed_done_crd) begin - pushed_done_sticky_was_high <= 1'h0; - end - else if (set_pushed_done_seg | set_pushed_done_crd) begin - pushed_done_sticky_was_high <= 1'h1; - end - end -end -assign pushed_done_sticky_sticky = pushed_done_sticky_was_high; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - readout_loop_sticky_was_high <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - readout_loop_sticky_was_high <= 1'h0; - end - else if (clr_readout_loop_seg | clr_readout_loop_crd) begin - readout_loop_sticky_was_high <= 1'h0; - end - else if (set_readout_loop_seg | set_readout_loop_crd) begin - readout_loop_sticky_was_high <= 1'h1; - end - end -end -assign readout_loop_sticky_sticky = readout_loop_sticky_was_high; -assign seg_res_fifo_push_alloc_0 = seg_res_fifo_push_alloc & (~lookup); -assign seg_res_fifo_push_reserve_0 = rd_rsp_fifo_0_valid & (rd_rsp_fifo_0_out_data[16] == 1'h0) & (~block_mode) & - (~lookup); -assign seg_res_fifo_push_fill_0 = seg_res_fifo_push_fill & (~lookup); -assign seg_res_fifo_pop_0 = seg_res_fifo_pop & (~lookup); -assign crd_res_fifo_data_in_0 = lookup ? {1'h0, rd_rsp_fifo_0_out_data[15:0]}: block_mode ? rd_rsp_fifo_0_valid - ? {1'h0, rd_rsp_fifo_0_out_data[15:0]}: {1'h0, rd_rsp_fifo_1_out_data[15:0]}: - {1'h0, rd_rsp_fifo_1_out_data[15:0]}; -assign crd_res_fifo_fill_data_in = lookup ? seg_res_fifo_fill_data_in: dense ? crd_out_to_fifo: - seg_res_fifo_data_out_0; -assign crd_res_fifo_push_alloc_0 = lookup ? seg_res_fifo_push_alloc: crd_res_fifo_push_alloc; -assign crd_res_fifo_push_reserve_0 = rd_rsp_fifo_1_valid | (rd_rsp_fifo_0_valid & (block_mode | lookup)); -assign crd_res_fifo_push_fill_0 = lookup ? seg_res_fifo_push_fill: crd_res_fifo_push_fill; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - last_stop_token <= 17'h0; - end - else if (clk_en) begin - if (flush) begin - last_stop_token <= 17'h0; - end - else if (1'h0) begin - last_stop_token <= 17'h0; - end - else if (seg_in_start_state ? 1'h0: seg_res_fifo_push_fill & seg_res_fifo_push_alloc & (lookup ? ~crd_res_fifo_full: ~seg_res_fifo_full) & seg_res_fifo_fill_data_in[16] & (seg_res_fifo_fill_data_in[9:8] == 2'h0)) begin - last_stop_token <= seg_in_start_state ? input_fifo_data_out + 17'h1: seg_res_fifo_fill_data_in; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - use_data_sticky_was_high <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - use_data_sticky_was_high <= 1'h0; - end - else if (clr_used_data) begin - use_data_sticky_was_high <= 1'h0; - end - else if (infifo_valid_in & (~infifo_eos_in)) begin - use_data_sticky_was_high <= 1'h1; - end - end -end -assign use_data_sticky_sticky = use_data_sticky_was_high; -assign clr_used_data = 1'h0; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - valid_cnt <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - valid_cnt <= 16'h0; - end - else if (valid_rst) begin - valid_cnt <= 16'h0; - end - else if (valid_inc) begin - valid_cnt <= valid_cnt + 16'h1; - end - end -end -assign ptr_in = block_mode ? rd_rsp_fifo_0_valid ? rd_rsp_fifo_0_out_data[15:0]: - rd_rsp_fifo_1_out_data[15:0]: rd_rsp_fifo_0_out_data[15:0]; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - ptr_in_d1 <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - ptr_in_d1 <= 16'h0; - end - else if (1'h0) begin - ptr_in_d1 <= 16'h0; - end - else if (ptr_reg_en) begin - ptr_in_d1 <= ptr_in; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - fiber_addr_pre_d1 <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - fiber_addr_pre_d1 <= 16'h0; - end - else if (1'h0) begin - fiber_addr_pre_d1 <= 16'h0; - end - else if (1'h1) begin - fiber_addr_pre_d1 <= fiber_addr_pre; - end - end -end -assign seq_length_ptr_math = seg_res_fifo_data_out_1 - seg_res_fifo_data_out_0[15:0]; -assign pos_addr = root ? 16'h0: infifo_pos_in; -assign next_seq_addr = ptr_in_d1 + inner_dim_offset; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - seq_length <= 16'h0; - seq_addr <= 16'h0; - payload_ptr <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - seq_length <= 16'h0; - seq_addr <= 16'h0; - payload_ptr <= 16'h0; - end - else if (update_seq_state) begin - seq_length <= next_seq_length; - seq_addr <= next_seq_addr; - payload_ptr <= ptr_in_d1; - end - end -end -assign fiber_addr = fiber_addr_pre + seq_addr; -assign fifo_full = |fifo_full_pre; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - iter_finish_was_high <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - iter_finish_was_high <= 1'h0; - end - else if (clr_fiber_addr) begin - iter_finish_was_high <= 1'h0; - end - else if (last_valid_accepting) begin - iter_finish_was_high <= 1'h1; - end - end -end -assign iter_finish_sticky = last_valid_accepting | iter_finish_was_high; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - rep_finish_was_high <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - rep_finish_was_high <= 1'h0; - end - else if (clr_rep) begin - rep_finish_was_high <= 1'h0; - end - else if (((repeat_factor - 16'h1) == num_reps) & inc_rep) begin - rep_finish_was_high <= 1'h1; - end - end -end -assign rep_finish_sticky = (((repeat_factor - 16'h1) == num_reps) & inc_rep) | rep_finish_was_high; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - seen_root_eos_was_high <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - seen_root_eos_was_high <= 1'h0; - end - else if (clr_seen_root_eos) begin - seen_root_eos_was_high <= 1'h0; - end - else if (infifo_eos_in & (infifo_pos_in == 16'h0)) begin - seen_root_eos_was_high <= 1'h1; - end - end -end -assign seen_root_eos_sticky = (infifo_eos_in & (infifo_pos_in == 16'h0)) | seen_root_eos_was_high; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - rd_rsp_fifo_0_out_data_d1 <= 17'h0; - end - else if (clk_en) begin - if (flush) begin - rd_rsp_fifo_0_out_data_d1 <= 17'h0; - end - else if (1'h0) begin - rd_rsp_fifo_0_out_data_d1 <= 17'h0; - end - else if (en_reg_data_in) begin - rd_rsp_fifo_0_out_data_d1 <= rd_rsp_fifo_0_out_data; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - fiber_addr_pre_d1_d1 <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - fiber_addr_pre_d1_d1 <= 16'h0; - end - else if (1'h0) begin - fiber_addr_pre_d1_d1 <= 16'h0; - end - else if (en_reg_data_in) begin - fiber_addr_pre_d1_d1 <= fiber_addr_pre_d1; - end - end -end -assign done_in = infifo_eos_in & infifo_valid_in & (infifo_pos_in[9:8] == 2'h1); -assign eos_in = infifo_eos_in & infifo_valid_in & (infifo_pos_in[9:8] == 2'h0); -assign maybe_in = infifo_eos_in & infifo_valid_in & (infifo_pos_in[9:8] == 2'h2); - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - infifo_pos_in_d1 <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - infifo_pos_in_d1 <= 16'h0; - end - else if (1'h0) begin - infifo_pos_in_d1 <= 16'h0; - end - else if (infifo_pos_in_d1_en) begin - infifo_pos_in_d1 <= infifo_pos_in; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - num_req_made_seg <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - num_req_made_seg <= 16'h0; - end - else if (clr_req_made_seg) begin - num_req_made_seg <= 16'h0; - end - else if (inc_req_made_seg) begin - num_req_made_seg <= num_req_made_seg + 16'h1; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - num_req_rec_seg <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - num_req_rec_seg <= 16'h0; - end - else if (clr_req_rec_seg) begin - num_req_rec_seg <= 16'h0; - end - else if (inc_req_rec_seg) begin - num_req_rec_seg <= num_req_rec_seg + 16'h1; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - num_req_made_crd <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - num_req_made_crd <= 16'h0; - end - else if (clr_req_made_crd) begin - num_req_made_crd <= 16'h0; - end - else if (inc_req_made_crd) begin - num_req_made_crd <= num_req_made_crd + 16'h1; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - num_req_rec_crd <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - num_req_rec_crd <= 16'h0; - end - else if (clr_req_rec_crd) begin - num_req_rec_crd <= 16'h0; - end - else if (inc_req_rec_crd) begin - num_req_rec_crd <= num_req_rec_crd + 16'h1; - end - end -end -assign seg_res_fifo_done_out = seg_res_fifo_valid & seg_res_fifo_data_out_0[16] & (seg_res_fifo_data_out_0[9:8] - == 2'h1); -assign readout_dst_crd = readout_loop_sticky_sticky; -assign readout_dst_seg = readout_loop_sticky_sticky; -assign inc_requests_made_CRDDD_READ = |{crd_grant_push_0, crd_grant_push_1}; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - READS_MADE <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - READS_MADE <= 16'h0; - end - else if (inc_requests_made_CRDDD_READ) begin - READS_MADE <= READS_MADE + 16'h1; - end - end -end -assign inc_requests_REC_CRD_READ = rd_rsp_fifo_1_valid & (rd_rsp_fifo_1_out_data[16] == 1'h1); - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - READS_REC_CRD_READ <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - READS_REC_CRD_READ <= 16'h0; - end - else if (inc_requests_REC_CRD_READ) begin - READS_REC_CRD_READ <= READS_REC_CRD_READ + 16'h1; - end - end -end -assign coord_fifo_in_packed = crd_res_fifo_data_out; -assign S_level_0 = {1'h1, 16'h0}; -assign done_token = {1'h1, 7'h0, 1'h1, 8'h0}; -assign coord_out[16] = vr_fsm_state_init_blank_DONE ? done_token[16]: vr_fsm_state_init_blank_S0 ? - S_level_0[16]: coord_fifo_out_packed[16]; -assign coord_out[15:0] = vr_fsm_state_init_blank_DONE ? done_token[15:0]: vr_fsm_state_init_blank_S0 ? - S_level_0[15:0]: coord_fifo_out_packed[15:0]; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - final_pushed_done_sticky_was_high <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - final_pushed_done_sticky_was_high <= 1'h0; - end - else if (clr_final_pushed_done) begin - final_pushed_done_sticky_was_high <= 1'h0; - end - else if (set_final_pushed_done) begin - final_pushed_done_sticky_was_high <= 1'h1; - end - end -end -assign final_pushed_done_sticky_sticky = final_pushed_done_sticky_was_high; -assign set_final_pushed_done = 1'h0; -assign clr_final_pushed_done = 1'h0; -assign non_vr_coord_fifo_push = crd_res_fifo_valid & (~block_mode) & (~(crd_res_fifo_data_out[16] & - crd_res_fifo_valid & (crd_res_fifo_data_out[9:8] == 2'h3))); -assign coord_fifo_push = vector_reduce_mode ? non_vr_coord_fifo_push & (~output_row_fully_accumulated): - non_vr_coord_fifo_push; -assign coord_out_valid = vr_fsm_state_init_blank_S0 | vr_fsm_state_init_blank_DONE | - (~coordinate_fifo_empty); -assign fifo_full_pre[0] = coordinate_fifo_full; -assign crd_res_fifo_pop = (vector_reduce_mode & output_row_fully_accumulated) ? ~pos_fifo_full: block_mode - ? ~block_rd_fifo_full: ~coordinate_fifo_full; -assign pos_fifo_in_packed = vector_reduce_mode ? coord_fifo_in_packed: pos_out_to_fifo; -assign pos_out_fifo_push = vector_reduce_mode ? non_vr_coord_fifo_push & output_row_fully_accumulated: - non_vr_pos_out_fifo_push; -assign pos_out[16] = pos_fifo_out_packed[16]; -assign pos_out[15:0] = pos_fifo_out_packed[15:0]; -assign pos_out_valid_mux_sel = vector_reduce_mode & (pos_out == done_token); -assign pos_out_valid = ((~pos_out_valid_mux_sel) & (~pos_fifo_empty)) | (pos_out_valid_mux_sel & - output_matrix_fully_accumulated & (~pos_fifo_empty)); -assign fifo_full_pre[1] = pos_fifo_full; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - rs_has_prepped_ds_row_sticky_was_high <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - rs_has_prepped_ds_row_sticky_was_high <= 1'h0; - end - else if (vr_fsm_state_init_blank_S0) begin - rs_has_prepped_ds_row_sticky_was_high <= 1'h0; - end - else if ((pos_fifo_in_packed == done_token) & pos_out_fifo_push & (~fifo_full_pre[1])) begin - rs_has_prepped_ds_row_sticky_was_high <= 1'h1; - end - end -end -assign rs_has_prepped_ds_row_sticky_sticky = ((pos_fifo_in_packed == done_token) & pos_out_fifo_push & (~fifo_full_pre[1])) | - rs_has_prepped_ds_row_sticky_was_high; -assign rs_has_prepped_ds_row = rs_has_prepped_ds_row_sticky_sticky; -assign block_rd_fifo_push = crd_res_fifo_valid & block_mode & (~(crd_res_fifo_data_out[16] & - crd_res_fifo_valid & (crd_res_fifo_data_out[9:8] == 2'h3))); -assign block_rd_out_valid = ~block_rd_fifo_empty; - -always_ff @(posedge clk, negedge rst_n) begin - if (!rst_n) begin - scan_seq_crd_current_state <= START_CRD; - end - else if (clk_en) begin - if (flush) begin - scan_seq_crd_current_state <= START_CRD; - end - else scan_seq_crd_current_state <= scan_seq_crd_next_state; - end -end -always_comb begin - scan_seq_crd_next_state = scan_seq_crd_current_state; - unique case (scan_seq_crd_current_state) - BLOCK_1_RD: begin - if ((num_req_rec_crd == ptr_in_d1) & (~lookup)) begin - scan_seq_crd_next_state = BLOCK_2_SIZE_REQ; - end - else if ((num_req_rec_crd == ptr_in_d1) & lookup) begin - scan_seq_crd_next_state = FREE_CRD; - end - else scan_seq_crd_next_state = BLOCK_1_RD; - end - BLOCK_1_SIZE_REC: begin - if (rd_rsp_fifo_0_valid) begin - scan_seq_crd_next_state = BLOCK_1_RD; - end - else scan_seq_crd_next_state = BLOCK_1_SIZE_REC; - end - BLOCK_1_SIZE_REQ: begin - if (|{crd_grant_push_0, crd_grant_push_1}) begin - scan_seq_crd_next_state = BLOCK_1_SIZE_REC; - end - else scan_seq_crd_next_state = BLOCK_1_SIZE_REQ; - end - BLOCK_2_RD: begin - if (num_req_rec_crd == ptr_in_d1) begin - scan_seq_crd_next_state = FREE_CRD; - end - else scan_seq_crd_next_state = BLOCK_2_RD; - end - BLOCK_2_SIZE_REC: begin - if (rd_rsp_fifo_1_valid) begin - scan_seq_crd_next_state = BLOCK_2_RD; - end - else scan_seq_crd_next_state = BLOCK_2_SIZE_REC; - end - BLOCK_2_SIZE_REQ: begin - if (|{crd_grant_push_0, crd_grant_push_1}) begin - scan_seq_crd_next_state = BLOCK_2_SIZE_REC; - end - else scan_seq_crd_next_state = BLOCK_2_SIZE_REQ; - end - DENSE_STRM: scan_seq_crd_next_state = DENSE_STRM; - DONE_CRD: scan_seq_crd_next_state = START_CRD; - FREE_CRD: begin - if ((|{crd_grant_push_0, crd_grant_push_1}) & block_mode & (~lookup)) begin - scan_seq_crd_next_state = FREE_CRD2; - end - else if (|{crd_grant_push_0, crd_grant_push_1}) begin - scan_seq_crd_next_state = DONE_CRD; - end - else scan_seq_crd_next_state = FREE_CRD; - end - FREE_CRD2: begin - if (|{crd_grant_push_0, crd_grant_push_1}) begin - scan_seq_crd_next_state = DONE_CRD; - end - else scan_seq_crd_next_state = FREE_CRD2; - end - PASS_DONE_CRD: begin - if ((~crd_res_fifo_full) & (~pos_fifo_full)) begin - scan_seq_crd_next_state = DONE_CRD; - end - end - READOUT_SYNC_LOCK: scan_seq_crd_next_state = DONE_CRD; - SEQ_STRM: begin - if (seg_res_fifo_done_out & (~crd_res_fifo_full) & (~pos_fifo_full)) begin - scan_seq_crd_next_state = FREE_CRD; - end - end - START_CRD: begin - if (block_mode & tile_en) begin - scan_seq_crd_next_state = BLOCK_1_SIZE_REQ; - end - else if (dense & (~lookup) & tile_en) begin - scan_seq_crd_next_state = DENSE_STRM; - end - else if ((~dense) & (~lookup) & tile_en) begin - scan_seq_crd_next_state = SEQ_STRM; - end - end - default: scan_seq_crd_next_state = scan_seq_crd_current_state; - endcase -end -always_comb begin - unique case (scan_seq_crd_current_state) - BLOCK_1_RD: begin :scan_seq_crd_BLOCK_1_RD_Output - crd_addr_out_to_fifo = num_req_made_crd; - crd_op_out_to_fifo = 16'h1; - crd_ID_out_to_fifo = 16'h0; - crd_req_push = (num_req_made_crd < ptr_in_d1) & (~crd_res_fifo_full); - crd_rd_rsp_fifo_pop = num_req_rec_crd < ptr_in_d1; - non_vr_pos_out_fifo_push = 1'h0; - crd_pop_infifo = 1'h0; - en_reg_data_in = 1'h0; - pos_out_to_fifo = 17'h0; - crd_out_to_fifo = 17'h0; - inc_req_made_crd = (num_req_made_crd < ptr_in_d1) & (|{crd_grant_push_0, crd_grant_push_1}) & - (~crd_res_fifo_full); - clr_req_made_crd = 1'h0; - inc_req_rec_crd = (num_req_rec_crd < ptr_in_d1) & rd_rsp_fifo_0_valid; - clr_req_rec_crd = 1'h0; - crd_res_fifo_push_alloc = (num_req_made_crd < ptr_in_d1) & (|{crd_grant_push_0, crd_grant_push_1}) & - (~crd_res_fifo_full); - crd_res_fifo_push_fill = 1'h0; - ptr_reg_en = 1'h0; - seg_res_fifo_pop = 1'h0; - set_readout_loop_crd = 1'h0; - set_pushed_done_crd = 1'h0; - clr_readout_loop_crd = 1'h0; - crd_in_done_state = 1'h0; - clr_pushed_done_crd = 1'h0; - end :scan_seq_crd_BLOCK_1_RD_Output - BLOCK_1_SIZE_REC: begin :scan_seq_crd_BLOCK_1_SIZE_REC_Output - crd_addr_out_to_fifo = 16'h0; - crd_op_out_to_fifo = 16'h0; - crd_ID_out_to_fifo = 16'h0; - crd_req_push = 1'h0; - crd_rd_rsp_fifo_pop = 1'h1; - non_vr_pos_out_fifo_push = 1'h0; - crd_pop_infifo = 1'h0; - en_reg_data_in = 1'h0; - pos_out_to_fifo = 17'h0; - crd_out_to_fifo = 17'h0; - inc_req_made_crd = 1'h0; - clr_req_made_crd = 1'h1; - inc_req_rec_crd = 1'h0; - clr_req_rec_crd = 1'h0; - crd_res_fifo_push_alloc = 1'h0; - crd_res_fifo_push_fill = 1'h0; - ptr_reg_en = rd_rsp_fifo_0_valid; - seg_res_fifo_pop = 1'h0; - set_readout_loop_crd = 1'h0; - set_pushed_done_crd = 1'h0; - clr_readout_loop_crd = 1'h0; - crd_in_done_state = 1'h0; - clr_pushed_done_crd = 1'h0; - end :scan_seq_crd_BLOCK_1_SIZE_REC_Output - BLOCK_1_SIZE_REQ: begin :scan_seq_crd_BLOCK_1_SIZE_REQ_Output - crd_addr_out_to_fifo = 16'h0; - crd_op_out_to_fifo = 16'h2; - crd_ID_out_to_fifo = 16'h0; - crd_req_push = ~crd_res_fifo_full; - crd_rd_rsp_fifo_pop = 1'h0; - non_vr_pos_out_fifo_push = 1'h0; - crd_pop_infifo = 1'h0; - en_reg_data_in = 1'h0; - pos_out_to_fifo = 17'h0; - crd_out_to_fifo = 17'h0; - inc_req_made_crd = 1'h0; - clr_req_made_crd = 1'h0; - inc_req_rec_crd = 1'h0; - clr_req_rec_crd = 1'h0; - crd_res_fifo_push_alloc = (~crd_res_fifo_full) & (|{crd_grant_push_0, crd_grant_push_1}); - crd_res_fifo_push_fill = 1'h0; - ptr_reg_en = 1'h0; - seg_res_fifo_pop = 1'h0; - set_readout_loop_crd = 1'h0; - set_pushed_done_crd = 1'h0; - clr_readout_loop_crd = 1'h0; - crd_in_done_state = 1'h0; - clr_pushed_done_crd = 1'h0; - end :scan_seq_crd_BLOCK_1_SIZE_REQ_Output - BLOCK_2_RD: begin :scan_seq_crd_BLOCK_2_RD_Output - crd_addr_out_to_fifo = num_req_made_crd; - crd_op_out_to_fifo = 16'h1; - crd_ID_out_to_fifo = 16'h1; - crd_req_push = (num_req_made_crd < ptr_in_d1) & (~crd_res_fifo_full); - crd_rd_rsp_fifo_pop = num_req_rec_crd < ptr_in_d1; - non_vr_pos_out_fifo_push = 1'h0; - crd_pop_infifo = 1'h0; - en_reg_data_in = 1'h0; - pos_out_to_fifo = 17'h0; - crd_out_to_fifo = 17'h0; - inc_req_made_crd = (num_req_made_crd < ptr_in_d1) & (|{crd_grant_push_0, crd_grant_push_1}) & - (~crd_res_fifo_full); - clr_req_made_crd = 1'h0; - inc_req_rec_crd = (num_req_rec_crd < ptr_in_d1) & rd_rsp_fifo_1_valid; - clr_req_rec_crd = 1'h0; - crd_res_fifo_push_alloc = (num_req_made_crd < ptr_in_d1) & (|{crd_grant_push_0, crd_grant_push_1}) & - (~crd_res_fifo_full); - crd_res_fifo_push_fill = 1'h0; - ptr_reg_en = 1'h0; - seg_res_fifo_pop = 1'h0; - set_readout_loop_crd = 1'h0; - set_pushed_done_crd = 1'h0; - clr_readout_loop_crd = 1'h0; - crd_in_done_state = 1'h0; - clr_pushed_done_crd = 1'h0; - end :scan_seq_crd_BLOCK_2_RD_Output - BLOCK_2_SIZE_REC: begin :scan_seq_crd_BLOCK_2_SIZE_REC_Output - crd_addr_out_to_fifo = 16'h0; - crd_op_out_to_fifo = 16'h0; - crd_ID_out_to_fifo = 16'h0; - crd_req_push = 1'h0; - crd_rd_rsp_fifo_pop = 1'h1; - non_vr_pos_out_fifo_push = 1'h0; - crd_pop_infifo = 1'h0; - en_reg_data_in = 1'h0; - pos_out_to_fifo = 17'h0; - crd_out_to_fifo = 17'h0; - inc_req_made_crd = 1'h0; - clr_req_made_crd = 1'h1; - inc_req_rec_crd = 1'h0; - clr_req_rec_crd = 1'h1; - crd_res_fifo_push_alloc = 1'h0; - crd_res_fifo_push_fill = 1'h0; - ptr_reg_en = rd_rsp_fifo_1_valid; - seg_res_fifo_pop = 1'h0; - set_readout_loop_crd = 1'h0; - set_pushed_done_crd = 1'h0; - clr_readout_loop_crd = 1'h0; - crd_in_done_state = 1'h0; - clr_pushed_done_crd = 1'h0; - end :scan_seq_crd_BLOCK_2_SIZE_REC_Output - BLOCK_2_SIZE_REQ: begin :scan_seq_crd_BLOCK_2_SIZE_REQ_Output - crd_addr_out_to_fifo = 16'h0; - crd_op_out_to_fifo = 16'h2; - crd_ID_out_to_fifo = 16'h1; - crd_req_push = ~crd_res_fifo_full; - crd_rd_rsp_fifo_pop = 1'h0; - non_vr_pos_out_fifo_push = 1'h0; - crd_pop_infifo = 1'h0; - en_reg_data_in = 1'h0; - pos_out_to_fifo = 17'h0; - crd_out_to_fifo = 17'h0; - inc_req_made_crd = 1'h0; - clr_req_made_crd = 1'h0; - inc_req_rec_crd = 1'h0; - clr_req_rec_crd = 1'h0; - crd_res_fifo_push_alloc = (~crd_res_fifo_full) & (|{crd_grant_push_0, crd_grant_push_1}); - crd_res_fifo_push_fill = 1'h0; - ptr_reg_en = 1'h0; - seg_res_fifo_pop = 1'h0; - set_readout_loop_crd = 1'h0; - set_pushed_done_crd = 1'h0; - clr_readout_loop_crd = 1'h0; - crd_in_done_state = 1'h0; - clr_pushed_done_crd = 1'h0; - end :scan_seq_crd_BLOCK_2_SIZE_REQ_Output - DENSE_STRM: begin :scan_seq_crd_DENSE_STRM_Output - crd_addr_out_to_fifo = 16'h0; - crd_op_out_to_fifo = 16'h0; - crd_ID_out_to_fifo = 16'h0; - crd_req_push = 1'h0; - crd_rd_rsp_fifo_pop = 1'h0; - non_vr_pos_out_fifo_push = seg_res_fifo_valid & (~pos_fifo_full) & (~crd_res_fifo_full) & - (seg_res_fifo_data_out_0[16] ? 1'h1: dim_size > num_req_made_crd); - crd_pop_infifo = 1'h0; - en_reg_data_in = 1'h0; - pos_out_to_fifo = seg_res_fifo_data_out_0[16] ? seg_res_fifo_data_out_0: - 17'((seg_res_fifo_data_out_0[15:0] * dim_size) + num_req_made_crd); - crd_out_to_fifo = seg_res_fifo_data_out_0[16] ? seg_res_fifo_data_out_0: 17'(num_req_made_crd); - inc_req_made_crd = seg_res_fifo_valid & (dim_size > num_req_made_crd) & - (~seg_res_fifo_data_out_0[16]) & (~pos_fifo_full) & (~crd_res_fifo_full); - clr_req_made_crd = seg_res_fifo_valid & seg_res_fifo_data_out_0[16]; - inc_req_rec_crd = 1'h0; - clr_req_rec_crd = 1'h0; - crd_res_fifo_push_alloc = seg_res_fifo_valid & (~pos_fifo_full) & (~crd_res_fifo_full) & - (seg_res_fifo_data_out_0[16] ? 1'h1: dim_size > num_req_made_crd); - crd_res_fifo_push_fill = seg_res_fifo_valid & (~pos_fifo_full) & (~crd_res_fifo_full) & - (seg_res_fifo_data_out_0[16] ? 1'h1: dim_size > num_req_made_crd); - ptr_reg_en = 1'h0; - seg_res_fifo_pop = seg_res_fifo_valid & (~pos_fifo_full) & (~crd_res_fifo_full) & - (seg_res_fifo_data_out_0[16] ? 1'h1: ((dim_size - 16'h1) == num_req_made_crd) & - inc_req_made_crd); - set_readout_loop_crd = 1'h0; - set_pushed_done_crd = 1'h0; - clr_readout_loop_crd = 1'h0; - crd_in_done_state = 1'h0; - clr_pushed_done_crd = 1'h0; - end :scan_seq_crd_DENSE_STRM_Output - DONE_CRD: begin :scan_seq_crd_DONE_CRD_Output - crd_addr_out_to_fifo = 16'h0; - crd_op_out_to_fifo = 16'h0; - crd_ID_out_to_fifo = 16'h0; - crd_req_push = 1'h0; - crd_rd_rsp_fifo_pop = 1'h0; - non_vr_pos_out_fifo_push = 1'h0; - crd_pop_infifo = 1'h0; - en_reg_data_in = 1'h0; - pos_out_to_fifo = 17'h0; - crd_out_to_fifo = 17'h0; - inc_req_made_crd = 1'h0; - clr_req_made_crd = 1'h1; - inc_req_rec_crd = 1'h0; - clr_req_rec_crd = 1'h1; - crd_res_fifo_push_alloc = 1'h0; - crd_res_fifo_push_fill = 1'h0; - ptr_reg_en = 1'h0; - seg_res_fifo_pop = 1'h0; - crd_in_done_state = 1'h1; - set_readout_loop_crd = 1'h0; - set_pushed_done_crd = 1'h0; - clr_readout_loop_crd = 1'h0; - clr_pushed_done_crd = 1'h0; - end :scan_seq_crd_DONE_CRD_Output - FREE_CRD: begin :scan_seq_crd_FREE_CRD_Output - crd_addr_out_to_fifo = 16'h0; - crd_op_out_to_fifo = 16'h0; - crd_ID_out_to_fifo = block_mode ? 16'h0: 16'h1; - crd_req_push = 1'h1; - crd_rd_rsp_fifo_pop = 1'h0; - non_vr_pos_out_fifo_push = 1'h0; - crd_pop_infifo = 1'h0; - en_reg_data_in = 1'h0; - pos_out_to_fifo = 17'h0; - crd_out_to_fifo = 17'h0; - inc_req_made_crd = 1'h0; - clr_req_made_crd = 1'h1; - inc_req_rec_crd = 1'h0; - clr_req_rec_crd = 1'h1; - crd_res_fifo_push_alloc = 1'h0; - crd_res_fifo_push_fill = 1'h0; - ptr_reg_en = 1'h0; - seg_res_fifo_pop = 1'h0; - set_readout_loop_crd = 1'h0; - set_pushed_done_crd = 1'h0; - clr_readout_loop_crd = 1'h0; - crd_in_done_state = 1'h0; - clr_pushed_done_crd = 1'h0; - end :scan_seq_crd_FREE_CRD_Output - FREE_CRD2: begin :scan_seq_crd_FREE_CRD2_Output - crd_addr_out_to_fifo = 16'h0; - crd_op_out_to_fifo = 16'h0; - crd_ID_out_to_fifo = 16'h1; - crd_req_push = 1'h1; - crd_rd_rsp_fifo_pop = 1'h0; - non_vr_pos_out_fifo_push = 1'h0; - crd_pop_infifo = 1'h0; - en_reg_data_in = 1'h0; - pos_out_to_fifo = 17'h0; - crd_out_to_fifo = 17'h0; - inc_req_made_crd = 1'h0; - clr_req_made_crd = 1'h1; - inc_req_rec_crd = 1'h0; - clr_req_rec_crd = 1'h1; - crd_res_fifo_push_alloc = 1'h0; - crd_res_fifo_push_fill = 1'h0; - ptr_reg_en = 1'h0; - seg_res_fifo_pop = 1'h0; - set_readout_loop_crd = 1'h0; - set_pushed_done_crd = 1'h0; - clr_readout_loop_crd = 1'h0; - crd_in_done_state = 1'h0; - clr_pushed_done_crd = 1'h0; - end :scan_seq_crd_FREE_CRD2_Output - PASS_DONE_CRD: begin :scan_seq_crd_PASS_DONE_CRD_Output - crd_addr_out_to_fifo = 16'h0; - crd_op_out_to_fifo = 16'h0; - crd_ID_out_to_fifo = 16'h0; - crd_req_push = 1'h0; - crd_rd_rsp_fifo_pop = 1'h0; - non_vr_pos_out_fifo_push = (~pos_fifo_full) & (~crd_res_fifo_full) & seg_res_fifo_done_out & - seg_res_fifo_valid; - crd_pop_infifo = 1'h0; - en_reg_data_in = 1'h0; - pos_out_to_fifo = {1'h1, 6'h0, 2'h1, 8'h0}; - crd_out_to_fifo = 17'h0; - inc_req_made_crd = 1'h0; - clr_req_made_crd = 1'h0; - inc_req_rec_crd = 1'h0; - clr_req_rec_crd = 1'h0; - crd_res_fifo_push_alloc = (~pos_fifo_full) & (~crd_res_fifo_full) & seg_res_fifo_done_out & - seg_res_fifo_valid; - crd_res_fifo_push_fill = (~pos_fifo_full) & (~crd_res_fifo_full) & seg_res_fifo_done_out & - seg_res_fifo_valid; - ptr_reg_en = 1'h0; - seg_res_fifo_pop = (~pos_fifo_full) & (~crd_res_fifo_full) & seg_res_fifo_done_out & - seg_res_fifo_valid; - clr_pushed_done_crd = 1'h0; - clr_readout_loop_crd = 1'h0; - set_readout_loop_crd = 1'h0; - set_pushed_done_crd = 1'h0; - crd_in_done_state = 1'h0; - end :scan_seq_crd_PASS_DONE_CRD_Output - READOUT_SYNC_LOCK: begin :scan_seq_crd_READOUT_SYNC_LOCK_Output - crd_addr_out_to_fifo = 16'h0; - crd_op_out_to_fifo = 16'h0; - crd_ID_out_to_fifo = 16'h0; - crd_req_push = 1'h0; - crd_rd_rsp_fifo_pop = 1'h0; - non_vr_pos_out_fifo_push = 1'h0; - crd_pop_infifo = 1'h0; - en_reg_data_in = 1'h0; - pos_out_to_fifo = 17'h0; - crd_out_to_fifo = 17'h0; - inc_req_made_crd = 1'h0; - clr_req_made_crd = 1'h0; - inc_req_rec_crd = 1'h0; - clr_req_rec_crd = 1'h0; - crd_res_fifo_push_alloc = 1'h0; - crd_res_fifo_push_fill = 1'h0; - ptr_reg_en = 1'h0; - seg_res_fifo_pop = 1'h0; - clr_pushed_done_crd = 1'h1; - clr_readout_loop_crd = 1'h1; - set_readout_loop_crd = 1'h0; - set_pushed_done_crd = 1'h0; - crd_in_done_state = 1'h0; - end :scan_seq_crd_READOUT_SYNC_LOCK_Output - SEQ_STRM: begin :scan_seq_crd_SEQ_STRM_Output - crd_addr_out_to_fifo = num_req_made_crd + seg_res_fifo_data_out_0[15:0]; - crd_op_out_to_fifo = 16'h1; - crd_ID_out_to_fifo = 16'h1; - crd_req_push = seg_res_fifo_valid & (~seg_res_fifo_data_out_0[16]) & (~crd_res_fifo_full) & - (num_req_made_crd < seq_length_ptr_math) & (~pos_fifo_full); - crd_rd_rsp_fifo_pop = 1'h1; - non_vr_pos_out_fifo_push = seg_res_fifo_data_out_0[16] ? (~pos_fifo_full) & (~crd_res_fifo_full) & - seg_res_fifo_valid: (|{crd_grant_push_0, crd_grant_push_1}) & (num_req_made_crd - < seq_length_ptr_math) & (~pos_fifo_full) & (~crd_res_fifo_full) & - seg_res_fifo_valid; - crd_pop_infifo = 1'h0; - en_reg_data_in = 1'h0; - pos_out_to_fifo = seg_res_fifo_data_out_0[16] ? seg_res_fifo_data_out_0: {1'h0, num_req_made_crd + - seg_res_fifo_data_out_0[15:0]}; - crd_out_to_fifo = 17'h0; - inc_req_made_crd = (|{crd_grant_push_0, crd_grant_push_1}) & (num_req_made_crd < - seq_length_ptr_math) & (~pos_fifo_full) & (~crd_res_fifo_full) & - seg_res_fifo_valid; - clr_req_made_crd = (((|{crd_grant_push_0, crd_grant_push_1}) & ((seq_length_ptr_math - 16'h1) == - num_req_made_crd)) | (seq_length_ptr_math == 16'h0)) & (~pos_fifo_full) & - (~crd_res_fifo_full) & seg_res_fifo_valid; - inc_req_rec_crd = 1'h0; - clr_req_rec_crd = 1'h0; - crd_res_fifo_push_alloc = seg_res_fifo_data_out_0[16] ? (~pos_fifo_full) & (~crd_res_fifo_full) & - seg_res_fifo_valid: (|{crd_grant_push_0, crd_grant_push_1}) & (num_req_made_crd - < seq_length_ptr_math) & (~pos_fifo_full) & (~crd_res_fifo_full) & - seg_res_fifo_valid; - crd_res_fifo_push_fill = seg_res_fifo_valid & seg_res_fifo_data_out_0[16] & (~pos_fifo_full) & - (~crd_res_fifo_full); - ptr_reg_en = 1'h0; - seg_res_fifo_pop = clr_req_made_crd | (seg_res_fifo_valid & seg_res_fifo_data_out_0[16] & - (~pos_fifo_full) & (~crd_res_fifo_full)); - set_readout_loop_crd = 1'h0; - set_pushed_done_crd = 1'h0; - clr_readout_loop_crd = 1'h0; - crd_in_done_state = 1'h0; - clr_pushed_done_crd = 1'h0; - end :scan_seq_crd_SEQ_STRM_Output - START_CRD: begin :scan_seq_crd_START_CRD_Output - crd_addr_out_to_fifo = 16'h0; - crd_op_out_to_fifo = 16'h0; - crd_ID_out_to_fifo = 16'h0; - crd_req_push = 1'h0; - crd_rd_rsp_fifo_pop = 1'h0; - non_vr_pos_out_fifo_push = 1'h0; - crd_pop_infifo = 1'h0; - en_reg_data_in = 1'h0; - pos_out_to_fifo = 17'h0; - crd_out_to_fifo = 17'h0; - inc_req_made_crd = 1'h0; - clr_req_made_crd = 1'h0; - inc_req_rec_crd = 1'h0; - clr_req_rec_crd = 1'h0; - crd_res_fifo_push_alloc = 1'h0; - crd_res_fifo_push_fill = 1'h0; - ptr_reg_en = 1'h0; - seg_res_fifo_pop = 1'h0; - set_readout_loop_crd = 1'h0; - set_pushed_done_crd = 1'h0; - clr_readout_loop_crd = 1'h0; - crd_in_done_state = 1'h0; - clr_pushed_done_crd = 1'h0; - end :scan_seq_crd_START_CRD_Output - default: begin :scan_seq_crd_default_Output - crd_addr_out_to_fifo = 16'h0; - crd_op_out_to_fifo = 16'h0; - crd_ID_out_to_fifo = 16'h0; - crd_req_push = 1'h0; - crd_rd_rsp_fifo_pop = 1'h0; - non_vr_pos_out_fifo_push = 1'h0; - crd_pop_infifo = 1'h0; - en_reg_data_in = 1'h0; - pos_out_to_fifo = 17'h0; - crd_out_to_fifo = 17'h0; - inc_req_made_crd = 1'h0; - clr_req_made_crd = 1'h0; - inc_req_rec_crd = 1'h0; - clr_req_rec_crd = 1'h0; - crd_res_fifo_push_alloc = 1'h0; - crd_res_fifo_push_fill = 1'h0; - ptr_reg_en = 1'h0; - seg_res_fifo_pop = 1'h0; - set_readout_loop_crd = 1'h0; - set_pushed_done_crd = 1'h0; - clr_readout_loop_crd = 1'h0; - crd_in_done_state = 1'h0; - clr_pushed_done_crd = 1'h0; - end :scan_seq_crd_default_Output - endcase -end - -always_ff @(posedge clk, negedge rst_n) begin - if (!rst_n) begin - scan_seq_seg_current_state <= START_SEG; - end - else if (clk_en) begin - if (flush) begin - scan_seq_seg_current_state <= START_SEG; - end - else scan_seq_seg_current_state <= scan_seq_seg_next_state; - end -end -always_comb begin - scan_seq_seg_next_state = scan_seq_seg_current_state; - unique case (scan_seq_seg_current_state) - DONE_SEG: begin - if (lookup ? 1'h1: (~dense) & crd_in_done_state) begin - scan_seq_seg_next_state = START_SEG; - end - end - FREE_SEG: begin - if (|{seg_grant_push_0, seg_grant_push_1}) begin - scan_seq_seg_next_state = DONE_SEG; - end - end - INJECT_0: scan_seq_seg_next_state = INJECT_DONE; - INJECT_DONE: scan_seq_seg_next_state = READ; - INJECT_ROUTING: begin - if (~seg_res_fifo_full) begin - scan_seq_seg_next_state = READ; - end - end - LOOKUP: begin - if (done_in & (~crd_res_fifo_full)) begin - scan_seq_seg_next_state = FREE_SEG; - end - else scan_seq_seg_next_state = LOOKUP; - end - PASS_DONE_SEG: scan_seq_seg_next_state = FREE_SEG; - PASS_STOP_SEG: begin - if (readout_loop_sticky_sticky & (~seg_res_fifo_full)) begin - scan_seq_seg_next_state = PASS_DONE_SEG; - end - else if (infifo_valid_in & (~lookup) & (~seg_res_fifo_full)) begin - scan_seq_seg_next_state = READ; - end - else scan_seq_seg_next_state = PASS_STOP_SEG; - end - READ: begin - if (maybe_in | (dense & (~done_in) & (~seg_res_fifo_full) & infifo_valid_in) | ((~dense) & eos_in)) begin - scan_seq_seg_next_state = PASS_STOP_SEG; - end - else if ((|{seg_grant_push_0, seg_grant_push_1}) & (~seg_res_fifo_full)) begin - scan_seq_seg_next_state = READ_ALT; - end - else if (done_in & (~seg_res_fifo_full)) begin - scan_seq_seg_next_state = FREE_SEG; - end - else scan_seq_seg_next_state = READ; - end - READ_ALT: begin - if ((|{seg_grant_push_0, seg_grant_push_1}) & (~seg_res_fifo_full) & infifo_valid_in) begin - scan_seq_seg_next_state = READ; - end - else if ((|{seg_grant_push_0, seg_grant_push_1}) & (~seg_res_fifo_full)) begin - scan_seq_seg_next_state = PASS_STOP_SEG; - end - else scan_seq_seg_next_state = READ_ALT; - end - START_SEG: begin - if (block_mode) begin - scan_seq_seg_next_state = START_SEG; - end - else if ((~root) & (~lookup) & (~block_mode) & tile_en) begin - scan_seq_seg_next_state = READ; - end - else if (root & (~lookup) & (~block_mode) & tile_en) begin - scan_seq_seg_next_state = INJECT_0; - end - else if ((~root) & lookup & (~block_mode) & tile_en) begin - scan_seq_seg_next_state = LOOKUP; - end - end - default: scan_seq_seg_next_state = scan_seq_seg_current_state; - endcase -end -always_comb begin - unique case (scan_seq_seg_current_state) - DONE_SEG: begin :scan_seq_seg_DONE_SEG_Output - seg_addr_out_to_fifo = 16'h0; - seg_op_out_to_fifo = 16'h0; - seg_ID_out_to_fifo = 16'h0; - seg_req_push = 1'h0; - seg_rd_rsp_fifo_pop = 1'h1; - seg_pop_infifo = 1'h0; - inc_req_made_seg = 1'h0; - clr_req_made_seg = 1'h0; - inc_req_rec_seg = 1'h0; - clr_req_rec_seg = 1'h0; - us_fifo_inject_data = 16'h0; - us_fifo_inject_eos = 1'h0; - us_fifo_inject_push = 1'h0; - seg_res_fifo_push_alloc = 1'h0; - seg_res_fifo_push_fill = 1'h0; - seg_res_fifo_fill_data_in = 17'h0; - set_readout_loop_seg = 1'h0; - clr_readout_loop_seg = 1'h0; - seg_in_done_state = 1'h1; - infifo_pos_in_d1_en = 1'h0; - clr_pushed_done_seg = 1'h0; - set_pushed_done_seg = 1'h0; - seg_in_start_state = 1'h0; - end :scan_seq_seg_DONE_SEG_Output - FREE_SEG: begin :scan_seq_seg_FREE_SEG_Output - seg_addr_out_to_fifo = 16'h0; - seg_op_out_to_fifo = 16'h0; - seg_ID_out_to_fifo = 16'h0; - seg_req_push = 1'h1; - seg_rd_rsp_fifo_pop = 1'h1; - seg_pop_infifo = 1'h0; - inc_req_made_seg = 1'h0; - clr_req_made_seg = 1'h0; - inc_req_rec_seg = 1'h0; - clr_req_rec_seg = 1'h0; - us_fifo_inject_data = 16'h0; - us_fifo_inject_eos = 1'h0; - us_fifo_inject_push = 1'h0; - seg_res_fifo_push_alloc = 1'h0; - seg_res_fifo_push_fill = 1'h0; - seg_res_fifo_fill_data_in = 17'h0; - infifo_pos_in_d1_en = 1'h0; - clr_pushed_done_seg = 1'h0; - set_pushed_done_seg = 1'h0; - seg_in_done_state = 1'h0; - seg_in_start_state = 1'h0; - set_readout_loop_seg = 1'h0; - clr_readout_loop_seg = 1'h0; - end :scan_seq_seg_FREE_SEG_Output - INJECT_0: begin :scan_seq_seg_INJECT_0_Output - seg_addr_out_to_fifo = 16'h0; - seg_op_out_to_fifo = 16'h0; - seg_ID_out_to_fifo = 16'h0; - seg_req_push = 1'h0; - seg_rd_rsp_fifo_pop = 1'h0; - seg_pop_infifo = 1'h0; - inc_req_made_seg = 1'h0; - clr_req_made_seg = 1'h0; - inc_req_rec_seg = 1'h0; - clr_req_rec_seg = 1'h0; - us_fifo_inject_data = 16'h0; - us_fifo_inject_eos = 1'h0; - us_fifo_inject_push = 1'h1; - seg_res_fifo_push_alloc = 1'h0; - seg_res_fifo_push_fill = 1'h0; - seg_res_fifo_fill_data_in = 17'h0; - infifo_pos_in_d1_en = 1'h0; - clr_pushed_done_seg = 1'h0; - set_pushed_done_seg = 1'h0; - seg_in_done_state = 1'h0; - seg_in_start_state = 1'h0; - set_readout_loop_seg = 1'h0; - clr_readout_loop_seg = 1'h0; - end :scan_seq_seg_INJECT_0_Output - INJECT_DONE: begin :scan_seq_seg_INJECT_DONE_Output - seg_addr_out_to_fifo = 16'h0; - seg_op_out_to_fifo = 16'h0; - seg_ID_out_to_fifo = 16'h0; - seg_req_push = 1'h0; - seg_rd_rsp_fifo_pop = 1'h0; - seg_pop_infifo = 1'h0; - inc_req_made_seg = 1'h0; - clr_req_made_seg = 1'h0; - inc_req_rec_seg = 1'h0; - clr_req_rec_seg = 1'h0; - us_fifo_inject_data = 16'h100; - us_fifo_inject_eos = 1'h1; - us_fifo_inject_push = 1'h1; - seg_res_fifo_push_alloc = 1'h0; - seg_res_fifo_push_fill = 1'h0; - seg_res_fifo_fill_data_in = 17'h0; - infifo_pos_in_d1_en = 1'h0; - clr_pushed_done_seg = 1'h0; - set_pushed_done_seg = 1'h0; - seg_in_done_state = 1'h0; - seg_in_start_state = 1'h0; - set_readout_loop_seg = 1'h0; - clr_readout_loop_seg = 1'h0; - end :scan_seq_seg_INJECT_DONE_Output - INJECT_ROUTING: begin :scan_seq_seg_INJECT_ROUTING_Output - seg_addr_out_to_fifo = 16'h0; - seg_op_out_to_fifo = 16'h0; - seg_ID_out_to_fifo = 16'h0; - seg_req_push = 1'h0; - seg_rd_rsp_fifo_pop = 1'h0; - seg_pop_infifo = 1'h0; - inc_req_made_seg = 1'h0; - clr_req_made_seg = 1'h0; - inc_req_rec_seg = 1'h0; - clr_req_rec_seg = 1'h0; - us_fifo_inject_data = 16'h0; - us_fifo_inject_eos = 1'h0; - us_fifo_inject_push = 1'h1; - seg_res_fifo_push_alloc = ~seg_res_fifo_full; - seg_res_fifo_push_fill = ~seg_res_fifo_full; - seg_res_fifo_fill_data_in = {1'h1, 6'h0, 2'h3, 7'h0, readout_loop_sticky_sticky}; - infifo_pos_in_d1_en = 1'h0; - clr_pushed_done_seg = 1'h0; - set_pushed_done_seg = 1'h0; - seg_in_done_state = 1'h0; - seg_in_start_state = 1'h0; - set_readout_loop_seg = 1'h0; - clr_readout_loop_seg = 1'h0; - end :scan_seq_seg_INJECT_ROUTING_Output - LOOKUP: begin :scan_seq_seg_LOOKUP_Output - seg_addr_out_to_fifo = infifo_pos_in; - seg_op_out_to_fifo = 16'h1; - seg_ID_out_to_fifo = 16'h0; - seg_req_push = infifo_valid_in & (~infifo_eos_in) & (~crd_res_fifo_full); - seg_rd_rsp_fifo_pop = 1'h1; - seg_pop_infifo = infifo_valid_in & (~crd_res_fifo_full) & (infifo_eos_in ? 1'h1: - |{seg_grant_push_0, seg_grant_push_1}); - inc_req_made_seg = 1'h0; - clr_req_made_seg = 1'h1; - inc_req_rec_seg = 1'h0; - clr_req_rec_seg = 1'h1; - us_fifo_inject_data = 16'h0; - us_fifo_inject_eos = 1'h0; - us_fifo_inject_push = 1'h0; - seg_res_fifo_push_alloc = (~crd_res_fifo_full) & ((|{seg_grant_push_0, seg_grant_push_1}) | - (infifo_valid_in & infifo_eos_in)); - seg_res_fifo_push_fill = infifo_valid_in & infifo_eos_in & (~crd_res_fifo_full); - seg_res_fifo_fill_data_in = (infifo_eos_in & (infifo_pos_in[9:8] == 2'h2)) ? 17'h0: {infifo_eos_in, - infifo_pos_in}; - set_pushed_done_seg = 1'h0; - set_readout_loop_seg = 1'h0; - infifo_pos_in_d1_en = 1'h0; - clr_pushed_done_seg = 1'h0; - seg_in_done_state = 1'h0; - seg_in_start_state = 1'h0; - clr_readout_loop_seg = 1'h0; - end :scan_seq_seg_LOOKUP_Output - PASS_DONE_SEG: begin :scan_seq_seg_PASS_DONE_SEG_Output - seg_addr_out_to_fifo = 16'h0; - seg_op_out_to_fifo = 16'h0; - seg_ID_out_to_fifo = 16'h0; - seg_req_push = 1'h0; - seg_rd_rsp_fifo_pop = 1'h1; - seg_pop_infifo = (~readout_loop_sticky_sticky) & done_in & (~seg_res_fifo_full); - inc_req_made_seg = 1'h0; - clr_req_made_seg = 1'h0; - inc_req_rec_seg = 1'h0; - clr_req_rec_seg = 1'h0; - us_fifo_inject_data = 16'h0; - us_fifo_inject_eos = 1'h0; - us_fifo_inject_push = 1'h0; - seg_res_fifo_push_alloc = readout_loop_sticky_sticky & pushed_done_sticky_sticky & (~seg_res_fifo_full); - seg_res_fifo_push_fill = readout_loop_sticky_sticky & pushed_done_sticky_sticky & (~seg_res_fifo_full); - seg_res_fifo_fill_data_in = {1'h1, 6'h0, 2'h1, 8'h0}; - set_pushed_done_seg = 1'h0; - infifo_pos_in_d1_en = 1'h0; - clr_pushed_done_seg = 1'h0; - seg_in_done_state = 1'h0; - seg_in_start_state = 1'h0; - set_readout_loop_seg = 1'h0; - clr_readout_loop_seg = 1'h0; - end :scan_seq_seg_PASS_DONE_SEG_Output - PASS_STOP_SEG: begin :scan_seq_seg_PASS_STOP_SEG_Output - seg_addr_out_to_fifo = 16'h0; - seg_op_out_to_fifo = 16'h0; - seg_ID_out_to_fifo = 16'h0; - seg_req_push = 1'h0; - seg_rd_rsp_fifo_pop = 1'h1; - seg_pop_infifo = (~seg_res_fifo_full) & eos_in & (~readout_loop_sticky_sticky); - inc_req_made_seg = 1'h0; - clr_req_made_seg = 1'h1; - inc_req_rec_seg = 1'h0; - clr_req_rec_seg = 1'h1; - us_fifo_inject_data = 16'h0; - us_fifo_inject_eos = 1'h0; - us_fifo_inject_push = 1'h0; - seg_res_fifo_push_alloc = (infifo_valid_in | readout_loop_sticky_sticky) & (~seg_res_fifo_full); - seg_res_fifo_push_fill = (infifo_valid_in | readout_loop_sticky_sticky) & (~seg_res_fifo_full); - seg_res_fifo_fill_data_in = readout_loop_sticky_sticky ? last_stop_token - 17'h1: eos_in ? {1'h1, - infifo_pos_in + 16'h1}: {1'h1, 16'h0}; - infifo_pos_in_d1_en = 1'h0; - clr_pushed_done_seg = 1'h0; - set_pushed_done_seg = 1'h0; - seg_in_done_state = 1'h0; - seg_in_start_state = 1'h0; - set_readout_loop_seg = 1'h0; - clr_readout_loop_seg = 1'h0; - end :scan_seq_seg_PASS_STOP_SEG_Output - READ: begin :scan_seq_seg_READ_Output - seg_addr_out_to_fifo = readout_loop_sticky_sticky ? 16'h0: infifo_pos_in; - seg_op_out_to_fifo = 16'h1; - seg_ID_out_to_fifo = 16'h0; - seg_req_push = ((infifo_valid_in & (~infifo_eos_in) & (~dense)) | readout_loop_sticky_sticky) & - (~seg_res_fifo_full); - seg_rd_rsp_fifo_pop = 1'h1; - seg_pop_infifo = (((done_in | (infifo_valid_in & (~eos_in) & (dense | (|{seg_grant_push_0, - seg_grant_push_1})))) & (~seg_res_fifo_full)) | maybe_in) & - (~readout_loop_sticky_sticky); - inc_req_made_seg = 1'h0; - clr_req_made_seg = 1'h0; - inc_req_rec_seg = 1'h0; - clr_req_rec_seg = 1'h0; - us_fifo_inject_data = 16'h0; - us_fifo_inject_eos = 1'h0; - us_fifo_inject_push = 1'h0; - seg_res_fifo_push_alloc = (done_in | dense) ? (~seg_res_fifo_full) & infifo_valid_in & (~eos_in): - (~seg_res_fifo_full) & (|{seg_grant_push_0, seg_grant_push_1}) & (~maybe_in); - seg_res_fifo_push_fill = (done_in | (dense & infifo_valid_in & (~eos_in))) & (~seg_res_fifo_full); - seg_res_fifo_fill_data_in = {infifo_eos_in, infifo_pos_in}; - infifo_pos_in_d1_en = (|{seg_grant_push_0, seg_grant_push_1}) & (~seg_res_fifo_full); - clr_pushed_done_seg = 1'h0; - set_pushed_done_seg = 1'h0; - seg_in_done_state = 1'h0; - seg_in_start_state = 1'h0; - set_readout_loop_seg = 1'h0; - clr_readout_loop_seg = 1'h0; - end :scan_seq_seg_READ_Output - READ_ALT: begin :scan_seq_seg_READ_ALT_Output - seg_addr_out_to_fifo = readout_loop_sticky_sticky ? 16'h1: infifo_pos_in_d1 + 16'h1; - seg_op_out_to_fifo = 16'h1; - seg_ID_out_to_fifo = 16'h0; - seg_req_push = ~seg_res_fifo_full; - seg_rd_rsp_fifo_pop = 1'h1; - seg_pop_infifo = eos_in & (~done_in) & (|{seg_grant_push_0, seg_grant_push_1}) & - (~seg_res_fifo_full) & (~readout_loop_sticky_sticky); - inc_req_made_seg = 1'h0; - clr_req_made_seg = 1'h0; - inc_req_rec_seg = 1'h0; - clr_req_rec_seg = 1'h0; - us_fifo_inject_data = 16'h0; - us_fifo_inject_eos = 1'h0; - us_fifo_inject_push = 1'h0; - seg_res_fifo_push_alloc = infifo_valid_in & (|{seg_grant_push_0, seg_grant_push_1}) & (~seg_res_fifo_full) - & (~readout_loop_sticky_sticky); - seg_res_fifo_push_fill = infifo_valid_in & (|{seg_grant_push_0, seg_grant_push_1}) & (~seg_res_fifo_full) - & (~readout_loop_sticky_sticky); - seg_res_fifo_fill_data_in = eos_in ? {1'h1, infifo_pos_in + 16'h1}: {1'h1, 16'h0}; - infifo_pos_in_d1_en = 1'h0; - clr_pushed_done_seg = 1'h0; - set_pushed_done_seg = 1'h0; - seg_in_done_state = 1'h0; - seg_in_start_state = 1'h0; - set_readout_loop_seg = 1'h0; - clr_readout_loop_seg = 1'h0; - end :scan_seq_seg_READ_ALT_Output - START_SEG: begin :scan_seq_seg_START_SEG_Output - seg_addr_out_to_fifo = 16'h0; - seg_op_out_to_fifo = 16'h0; - seg_ID_out_to_fifo = 16'h0; - seg_req_push = 1'h0; - seg_rd_rsp_fifo_pop = 1'h0; - seg_pop_infifo = 1'h0; - inc_req_made_seg = 1'h0; - clr_req_made_seg = 1'h0; - inc_req_rec_seg = 1'h0; - clr_req_rec_seg = 1'h0; - us_fifo_inject_data = 16'h0; - us_fifo_inject_eos = 1'h0; - us_fifo_inject_push = 1'h0; - seg_res_fifo_push_alloc = 1'h0; - seg_res_fifo_push_fill = 1'h0; - seg_res_fifo_fill_data_in = 17'h0; - set_readout_loop_seg = 1'h0; - seg_in_start_state = 1'h1; - infifo_pos_in_d1_en = 1'h0; - clr_pushed_done_seg = 1'h0; - set_pushed_done_seg = 1'h0; - seg_in_done_state = 1'h0; - clr_readout_loop_seg = 1'h0; - end :scan_seq_seg_START_SEG_Output - default: begin :scan_seq_seg_default_Output - seg_addr_out_to_fifo = 16'h0; - seg_op_out_to_fifo = 16'h0; - seg_ID_out_to_fifo = 16'h0; - seg_req_push = 1'h0; - seg_rd_rsp_fifo_pop = 1'h0; - seg_pop_infifo = 1'h0; - inc_req_made_seg = 1'h0; - clr_req_made_seg = 1'h0; - inc_req_rec_seg = 1'h0; - clr_req_rec_seg = 1'h0; - us_fifo_inject_data = 16'h0; - us_fifo_inject_eos = 1'h0; - us_fifo_inject_push = 1'h0; - seg_res_fifo_push_alloc = 1'h0; - seg_res_fifo_push_fill = 1'h0; - seg_res_fifo_fill_data_in = 17'h0; - set_readout_loop_seg = 1'h0; - seg_in_start_state = 1'h1; - infifo_pos_in_d1_en = 1'h0; - clr_pushed_done_seg = 1'h0; - set_pushed_done_seg = 1'h0; - seg_in_done_state = 1'h0; - clr_readout_loop_seg = 1'h0; - end :scan_seq_seg_default_Output - endcase -end -reg_fifo_depth_2_w_17_afd_2 input_fifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in(fifo_us_in_packed), - .flush(flush), - .pop(pop_infifo), - .push(us_fifo_push), - .rst_n(rst_n), - .data_out(input_fifo_data_out), - .empty(input_fifo_empty), - .full(fifo_us_full) -); - -reg_fifo_depth_2_w_17_afd_2 rd_rsp_fifo_0 ( - .clk(gclk), - .clk_en(clk_en), - .data_in(rd_rsp_data_in_0), - .flush(flush), - .pop(1'h1), - .push(rd_rsp_data_in_0_valid), - .rst_n(rst_n), - .data_out(rd_rsp_fifo_0_out_data), - .empty(rd_rsp_fifo_0_empty), - .full(rd_rsp_fifo_0_full) -); - -reg_fifo_depth_2_w_17_afd_2 rd_rsp_fifo_1 ( - .clk(gclk), - .clk_en(clk_en), - .data_in(rd_rsp_data_in_1), - .flush(flush), - .pop(1'h1), - .push(rd_rsp_data_in_1_valid), - .rst_n(rst_n), - .data_out(rd_rsp_fifo_1_out_data), - .empty(rd_rsp_fifo_1_empty), - .full(rd_rsp_fifo_1_full) -); - -arbiter_2_in_PRIO_algo rr_arbiter_0 ( - .clk(gclk), - .clk_en(clk_en), - .flush(flush), - .request_in(base_rr_0), - .resource_ready(no_outfifo_full_0), - .rst_n(rst_n), - .grant_out(rr_arbiter_0_grant_out) -); - -arbiter_2_in_PRIO_algo rr_arbiter_1 ( - .clk(gclk), - .clk_en(clk_en), - .flush(flush), - .request_in(base_rr_1), - .resource_ready(no_outfifo_full_1), - .rst_n(rst_n), - .grant_out(rr_arbiter_1_grant_out) -); - -reg_fifo_depth_2_w_17_afd_2 addr_out_fifo_0 ( - .clk(gclk), - .clk_en(clk_en), - .data_in(addr_out_fifo_0_data_in), - .flush(flush), - .pop(addr_out_0_ready), - .push(addr_out_fifo_0_push), - .rst_n(rst_n), - .data_out(addr_out_0), - .empty(addr_out_fifo_0_empty), - .full(addr_out_fifo_0_full) -); - -reg_fifo_depth_2_w_17_afd_2 addr_out_fifo_1 ( - .clk(gclk), - .clk_en(clk_en), - .data_in(addr_out_fifo_1_data_in), - .flush(flush), - .pop(addr_out_1_ready), - .push(addr_out_fifo_1_push), - .rst_n(rst_n), - .data_out(addr_out_1), - .empty(addr_out_fifo_1_empty), - .full(addr_out_fifo_1_full) -); - -reg_fifo_depth_2_w_17_afd_2 op_out_fifo_0 ( - .clk(gclk), - .clk_en(clk_en), - .data_in(op_out_fifo_0_data_in), - .flush(flush), - .pop(op_out_0_ready), - .push(op_out_fifo_0_push), - .rst_n(rst_n), - .data_out(op_out_0), - .empty(op_out_fifo_0_empty), - .full(op_out_fifo_0_full) -); - -reg_fifo_depth_2_w_17_afd_2 op_out_fifo_1 ( - .clk(gclk), - .clk_en(clk_en), - .data_in(op_out_fifo_1_data_in), - .flush(flush), - .pop(op_out_1_ready), - .push(op_out_fifo_1_push), - .rst_n(rst_n), - .data_out(op_out_1), - .empty(op_out_fifo_1_empty), - .full(op_out_fifo_1_full) -); - -reservation_fifo_depth_8_w_17_num_per_2 seg_res_fifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in_0(rd_rsp_fifo_0_out_data), - .data_in_1(rd_rsp_fifo_0_out_data), - .fill_data_in(seg_res_fifo_fill_data_in), - .flush(flush), - .pop(seg_res_fifo_pop_0), - .push_alloc(seg_res_fifo_push_alloc_0), - .push_fill(seg_res_fifo_push_fill_0), - .push_reserve(seg_res_fifo_push_reserve_0), - .rst_n(rst_n), - .data_out_0(seg_res_fifo_data_out_0), - .data_out_1(seg_res_fifo_data_out_1), - .full(seg_res_fifo_full), - .valid(seg_res_fifo_valid) -); - -reservation_fifo_depth_32_w_17_num_per_1 crd_res_fifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in_0(crd_res_fifo_data_in_0), - .fill_data_in(crd_res_fifo_fill_data_in), - .flush(flush), - .pop(crd_res_fifo_pop), - .push_alloc(crd_res_fifo_push_alloc_0), - .push_fill(crd_res_fifo_push_fill_0), - .push_reserve(crd_res_fifo_push_reserve_0), - .rst_n(rst_n), - .data_out_0(crd_res_fifo_data_out), - .full(crd_res_fifo_full), - .valid(crd_res_fifo_valid) -); - -reg_fifo_depth_0_w_17_afd_2 coordinate_fifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in(coord_fifo_in_packed), - .flush(flush), - .pop(coord_out_ready), - .push(coord_fifo_push), - .rst_n(rst_n), - .data_out(coord_fifo_out_packed), - .empty(coordinate_fifo_empty), - .full(coordinate_fifo_full) -); - -reg_fifo_depth_0_w_17_afd_2 pos_fifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in(pos_fifo_in_packed), - .flush(flush), - .pop(pos_out_ready), - .push(pos_out_fifo_push), - .rst_n(rst_n), - .data_out(pos_fifo_out_packed), - .empty(pos_fifo_empty), - .full(pos_fifo_full) -); - -reg_fifo_depth_0_w_17_afd_2 block_rd_fifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in(crd_res_fifo_data_out), - .flush(flush), - .pop(block_rd_out_ready), - .push(block_rd_fifo_push), - .rst_n(rst_n), - .data_out(block_rd_out), - .empty(block_rd_fifo_empty), - .full(block_rd_fifo_full) -); - -endmodule // scanner_pipe - -module sched_gen_3_16 ( - input logic clk, - input logic clk_en, - input logic [15:0] cycle_count, - input logic enable, - input logic finished, - input logic flush, - input logic [1:0] mux_sel, - input logic rst_n, - input logic [15:0] sched_addr_gen_starting_addr, - input logic [15:0] sched_addr_gen_strides_0, - input logic [15:0] sched_addr_gen_strides_1, - input logic [15:0] sched_addr_gen_strides_2, - output logic valid_output -); - -logic [15:0] addr_out; -logic [2:0][15:0] sched_addr_gen_strides; -logic valid_gate; -logic valid_gate_inv; -logic valid_out; -assign valid_gate = ~valid_gate_inv; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - valid_gate_inv <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - valid_gate_inv <= 1'h0; - end - else if (finished) begin - valid_gate_inv <= 1'h1; - end - end -end -always_comb begin - valid_out = (cycle_count == addr_out) & valid_gate & enable; -end -always_comb begin - valid_output = valid_out; -end -assign sched_addr_gen_strides[0] = sched_addr_gen_strides_0; -assign sched_addr_gen_strides[1] = sched_addr_gen_strides_1; -assign sched_addr_gen_strides[2] = sched_addr_gen_strides_2; -addr_gen_3_16 sched_addr_gen ( - .clk(clk), - .clk_en(clk_en), - .flush(flush), - .mux_sel(mux_sel), - .restart(finished), - .rst_n(rst_n), - .starting_addr(sched_addr_gen_starting_addr), - .step(valid_out), - .strides(sched_addr_gen_strides), - .addr_out(addr_out) -); - -endmodule // sched_gen_3_16 - -module sched_gen_6_16 ( - input logic clk, - input logic clk_en, - input logic [15:0] cycle_count, - input logic enable, - input logic finished, - input logic flush, - input logic [2:0] mux_sel, - input logic rst_n, - input logic [15:0] sched_addr_gen_starting_addr, - input logic [15:0] sched_addr_gen_strides_0, - input logic [15:0] sched_addr_gen_strides_1, - input logic [15:0] sched_addr_gen_strides_2, - input logic [15:0] sched_addr_gen_strides_3, - input logic [15:0] sched_addr_gen_strides_4, - input logic [15:0] sched_addr_gen_strides_5, - output logic valid_output -); - -logic [15:0] addr_out; -logic [5:0][15:0] sched_addr_gen_strides; -logic valid_gate; -logic valid_gate_inv; -logic valid_out; -assign valid_gate = ~valid_gate_inv; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - valid_gate_inv <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - valid_gate_inv <= 1'h0; - end - else if (finished) begin - valid_gate_inv <= 1'h1; - end - end -end -always_comb begin - valid_out = (cycle_count == addr_out) & valid_gate & enable; -end -always_comb begin - valid_output = valid_out; -end -assign sched_addr_gen_strides[0] = sched_addr_gen_strides_0; -assign sched_addr_gen_strides[1] = sched_addr_gen_strides_1; -assign sched_addr_gen_strides[2] = sched_addr_gen_strides_2; -assign sched_addr_gen_strides[3] = sched_addr_gen_strides_3; -assign sched_addr_gen_strides[4] = sched_addr_gen_strides_4; -assign sched_addr_gen_strides[5] = sched_addr_gen_strides_5; -addr_gen_6_16 sched_addr_gen ( - .clk(clk), - .clk_en(clk_en), - .flush(flush), - .mux_sel(mux_sel), - .restart(finished), - .rst_n(rst_n), - .starting_addr(sched_addr_gen_starting_addr), - .step(valid_out), - .strides(sched_addr_gen_strides), - .addr_out(addr_out) -); - -endmodule // sched_gen_6_16 - -module sched_gen_6_16_delay_addr_10_4 ( - input logic clk, - input logic clk_en, - input logic [15:0] cycle_count, - input logic enable, - input logic finished, - input logic flush, - input logic [2:0] mux_sel, - input logic rst_n, - input logic [9:0] sched_addr_gen_delay, - input logic [15:0] sched_addr_gen_starting_addr, - input logic [15:0] sched_addr_gen_strides_0, - input logic [15:0] sched_addr_gen_strides_1, - input logic [15:0] sched_addr_gen_strides_2, - input logic [15:0] sched_addr_gen_strides_3, - input logic [15:0] sched_addr_gen_strides_4, - input logic [15:0] sched_addr_gen_strides_5, - output logic delay_en_out, - output logic valid_output, - output logic valid_output_d -); - -logic [3:0][10:0] addr_fifo; -logic addr_fifo_empty_n; -logic [10:0] addr_fifo_in; -logic [10:0] addr_fifo_out; -logic addr_fifo_wr_en; -logic [15:0] addr_out; -logic [15:0] addr_out_d; -logic delay_en; -logic [1:0] next_rd_ptr; -logic [1:0] rd_ptr; -logic [9:0] sched_addr_gen_delay_out; -logic [5:0][15:0] sched_addr_gen_strides; -logic valid_gate; -logic valid_gate_inv; -logic valid_out; -logic valid_out_d; -logic [1:0] wr_ptr; -assign valid_gate = ~valid_gate_inv; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - valid_gate_inv <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - valid_gate_inv <= 1'h0; - end - else if (finished) begin - valid_gate_inv <= 1'h1; - end - end -end -assign delay_en_out = delay_en; -assign delay_en = sched_addr_gen_delay_out > 10'h0; -assign next_rd_ptr = rd_ptr + 2'h1; -assign addr_fifo_wr_en = valid_out; -assign addr_fifo_in = addr_out_d[10:0]; -assign addr_fifo_out = addr_fifo[rd_ptr]; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - wr_ptr <= 2'h0; - rd_ptr <= 2'h0; - addr_fifo <= 44'h0; - addr_fifo_empty_n <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - wr_ptr <= 2'h0; - rd_ptr <= 2'h0; - addr_fifo <= 44'h0; - addr_fifo_empty_n <= 1'h0; - end - else if (delay_en) begin - if (addr_fifo_wr_en) begin - wr_ptr <= wr_ptr + 2'h1; - addr_fifo[wr_ptr] <= addr_fifo_in; - end - if (valid_out_d) begin - rd_ptr <= next_rd_ptr; - end - if (addr_fifo_wr_en) begin - addr_fifo_empty_n <= 1'h1; - end - else if (valid_out_d) begin - addr_fifo_empty_n <= ~(next_rd_ptr == wr_ptr); - end - else addr_fifo_empty_n <= addr_fifo_empty_n; - end - end -end -always_comb begin - valid_out_d = (cycle_count[10:0] == addr_fifo_out) & addr_fifo_empty_n & enable; - valid_output_d = valid_out_d; -end -always_comb begin - valid_out = (cycle_count == addr_out) & valid_gate & enable; -end -always_comb begin - valid_output = valid_out; -end -assign sched_addr_gen_strides[0] = sched_addr_gen_strides_0; -assign sched_addr_gen_strides[1] = sched_addr_gen_strides_1; -assign sched_addr_gen_strides[2] = sched_addr_gen_strides_2; -assign sched_addr_gen_strides[3] = sched_addr_gen_strides_3; -assign sched_addr_gen_strides[4] = sched_addr_gen_strides_4; -assign sched_addr_gen_strides[5] = sched_addr_gen_strides_5; -addr_gen_6_16_delay_addr_10 sched_addr_gen ( - .clk(clk), - .clk_en(clk_en), - .delay(sched_addr_gen_delay), - .flush(flush), - .mux_sel(mux_sel), - .restart(finished), - .rst_n(rst_n), - .starting_addr(sched_addr_gen_starting_addr), - .step(valid_out), - .strides(sched_addr_gen_strides), - .addr_out(addr_out), - .delay_out(sched_addr_gen_delay_out), - .delayed_addr_out(addr_out_d) -); - -endmodule // sched_gen_6_16_delay_addr_10_4 - -module sched_gen_6_16_delay_addr_10_8 ( - input logic clk, - input logic clk_en, - input logic [15:0] cycle_count, - input logic enable, - input logic finished, - input logic flush, - input logic [2:0] mux_sel, - input logic rst_n, - input logic [9:0] sched_addr_gen_delay, - input logic [15:0] sched_addr_gen_starting_addr, - input logic [15:0] sched_addr_gen_strides_0, - input logic [15:0] sched_addr_gen_strides_1, - input logic [15:0] sched_addr_gen_strides_2, - input logic [15:0] sched_addr_gen_strides_3, - input logic [15:0] sched_addr_gen_strides_4, - input logic [15:0] sched_addr_gen_strides_5, - output logic delay_en_out, - output logic valid_output, - output logic valid_output_d -); - -logic [7:0][10:0] addr_fifo; -logic addr_fifo_empty_n; -logic [10:0] addr_fifo_in; -logic [10:0] addr_fifo_out; -logic addr_fifo_wr_en; -logic [15:0] addr_out; -logic [15:0] addr_out_d; -logic delay_en; -logic [2:0] next_rd_ptr; -logic [2:0] rd_ptr; -logic [9:0] sched_addr_gen_delay_out; -logic [5:0][15:0] sched_addr_gen_strides; -logic valid_gate; -logic valid_gate_inv; -logic valid_out; -logic valid_out_d; -logic [2:0] wr_ptr; -assign valid_gate = ~valid_gate_inv; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - valid_gate_inv <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - valid_gate_inv <= 1'h0; - end - else if (finished) begin - valid_gate_inv <= 1'h1; - end - end -end -assign delay_en_out = delay_en; -assign delay_en = sched_addr_gen_delay_out > 10'h0; -assign next_rd_ptr = rd_ptr + 3'h1; -assign addr_fifo_wr_en = valid_out; -assign addr_fifo_in = addr_out_d[10:0]; -assign addr_fifo_out = addr_fifo[rd_ptr]; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - wr_ptr <= 3'h0; - rd_ptr <= 3'h0; - addr_fifo <= 88'h0; - addr_fifo_empty_n <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - wr_ptr <= 3'h0; - rd_ptr <= 3'h0; - addr_fifo <= 88'h0; - addr_fifo_empty_n <= 1'h0; - end - else if (delay_en) begin - if (addr_fifo_wr_en) begin - wr_ptr <= wr_ptr + 3'h1; - addr_fifo[wr_ptr] <= addr_fifo_in; - end - if (valid_out_d) begin - rd_ptr <= next_rd_ptr; - end - if (addr_fifo_wr_en) begin - addr_fifo_empty_n <= 1'h1; - end - else if (valid_out_d) begin - addr_fifo_empty_n <= ~(next_rd_ptr == wr_ptr); - end - else addr_fifo_empty_n <= addr_fifo_empty_n; - end - end -end -always_comb begin - valid_out_d = (cycle_count[10:0] == addr_fifo_out) & addr_fifo_empty_n & enable; - valid_output_d = valid_out_d; -end -always_comb begin - valid_out = (cycle_count == addr_out) & valid_gate & enable; -end -always_comb begin - valid_output = valid_out; -end -assign sched_addr_gen_strides[0] = sched_addr_gen_strides_0; -assign sched_addr_gen_strides[1] = sched_addr_gen_strides_1; -assign sched_addr_gen_strides[2] = sched_addr_gen_strides_2; -assign sched_addr_gen_strides[3] = sched_addr_gen_strides_3; -assign sched_addr_gen_strides[4] = sched_addr_gen_strides_4; -assign sched_addr_gen_strides[5] = sched_addr_gen_strides_5; -addr_gen_6_16_delay_addr_10 sched_addr_gen ( - .clk(clk), - .clk_en(clk_en), - .delay(sched_addr_gen_delay), - .flush(flush), - .mux_sel(mux_sel), - .restart(finished), - .rst_n(rst_n), - .starting_addr(sched_addr_gen_starting_addr), - .step(valid_out), - .strides(sched_addr_gen_strides), - .addr_out(addr_out), - .delay_out(sched_addr_gen_delay_out), - .delayed_addr_out(addr_out_d) -); - -endmodule // sched_gen_6_16_delay_addr_10_8 - -module sram_sp__0 ( - input logic clk, - input logic clk_en, - input logic [63:0] data_in_p0, - input logic flush, - input logic [8:0] read_addr_p0, - input logic read_enable_p0, - input logic [8:0] write_addr_p0, - input logic write_enable_p0, - output logic [63:0] data_out_p0 -); - -logic [63:0] data_array [511:0]; - -always_ff @(posedge clk) begin - if (clk_en) begin - if (write_enable_p0 == 1'h1) begin - data_array[write_addr_p0] <= data_in_p0; - end - else if (read_enable_p0) begin - data_out_p0 <= data_array[read_addr_p0]; - end - end -end -endmodule // sram_sp__0 - -module stencil_valid ( - input logic clk, - input logic clk_en, - input logic flush, - input logic [3:0] loops_stencil_valid_dimensionality, - input logic [10:0] loops_stencil_valid_ranges_0, - input logic [10:0] loops_stencil_valid_ranges_1, - input logic [10:0] loops_stencil_valid_ranges_2, - input logic [10:0] loops_stencil_valid_ranges_3, - input logic [10:0] loops_stencil_valid_ranges_4, - input logic [10:0] loops_stencil_valid_ranges_5, - input logic rst_n, - input logic stencil_valid_sched_gen_enable, - input logic [15:0] stencil_valid_sched_gen_sched_addr_gen_starting_addr, - input logic [15:0] stencil_valid_sched_gen_sched_addr_gen_strides_0, - input logic [15:0] stencil_valid_sched_gen_sched_addr_gen_strides_1, - input logic [15:0] stencil_valid_sched_gen_sched_addr_gen_strides_2, - input logic [15:0] stencil_valid_sched_gen_sched_addr_gen_strides_3, - input logic [15:0] stencil_valid_sched_gen_sched_addr_gen_strides_4, - input logic [15:0] stencil_valid_sched_gen_sched_addr_gen_strides_5, - output logic stencil_valid -); - -logic [15:0] cycle_count; -logic flushed; -logic [2:0] loops_stencil_valid_mux_sel_out; -logic [5:0][10:0] loops_stencil_valid_ranges; -logic loops_stencil_valid_restart; -logic stencil_valid_internal; -assign stencil_valid = stencil_valid_internal & flushed; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - cycle_count <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - cycle_count <= 16'h0; - end - else if (flushed) begin - cycle_count <= cycle_count + 16'h1; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - flushed <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - flushed <= 1'h1; - end - end -end -assign loops_stencil_valid_ranges[0] = loops_stencil_valid_ranges_0; -assign loops_stencil_valid_ranges[1] = loops_stencil_valid_ranges_1; -assign loops_stencil_valid_ranges[2] = loops_stencil_valid_ranges_2; -assign loops_stencil_valid_ranges[3] = loops_stencil_valid_ranges_3; -assign loops_stencil_valid_ranges[4] = loops_stencil_valid_ranges_4; -assign loops_stencil_valid_ranges[5] = loops_stencil_valid_ranges_5; -for_loop_6_11 loops_stencil_valid ( - .clk(clk), - .clk_en(clk_en), - .dimensionality(loops_stencil_valid_dimensionality), - .flush(flush), - .ranges(loops_stencil_valid_ranges), - .rst_n(rst_n), - .step(stencil_valid_internal), - .mux_sel_out(loops_stencil_valid_mux_sel_out), - .restart(loops_stencil_valid_restart) -); - -sched_gen_6_16 stencil_valid_sched_gen ( - .clk(clk), - .clk_en(clk_en), - .cycle_count(cycle_count), - .enable(stencil_valid_sched_gen_enable), - .finished(loops_stencil_valid_restart), - .flush(flush), - .mux_sel(loops_stencil_valid_mux_sel_out), - .rst_n(rst_n), - .sched_addr_gen_starting_addr(stencil_valid_sched_gen_sched_addr_gen_starting_addr), - .sched_addr_gen_strides_0(stencil_valid_sched_gen_sched_addr_gen_strides_0), - .sched_addr_gen_strides_1(stencil_valid_sched_gen_sched_addr_gen_strides_1), - .sched_addr_gen_strides_2(stencil_valid_sched_gen_sched_addr_gen_strides_2), - .sched_addr_gen_strides_3(stencil_valid_sched_gen_sched_addr_gen_strides_3), - .sched_addr_gen_strides_4(stencil_valid_sched_gen_sched_addr_gen_strides_4), - .sched_addr_gen_strides_5(stencil_valid_sched_gen_sched_addr_gen_strides_5), - .valid_output(stencil_valid_internal) -); - -endmodule // stencil_valid - -module stencil_valid_flat ( - input logic clk, - input logic clk_en, - input logic flush, - input logic rst_n, - input logic [3:0] stencil_valid_inst_loops_stencil_valid_dimensionality, - input logic [10:0] stencil_valid_inst_loops_stencil_valid_ranges_0, - input logic [10:0] stencil_valid_inst_loops_stencil_valid_ranges_1, - input logic [10:0] stencil_valid_inst_loops_stencil_valid_ranges_2, - input logic [10:0] stencil_valid_inst_loops_stencil_valid_ranges_3, - input logic [10:0] stencil_valid_inst_loops_stencil_valid_ranges_4, - input logic [10:0] stencil_valid_inst_loops_stencil_valid_ranges_5, - input logic stencil_valid_inst_stencil_valid_sched_gen_enable, - input logic [15:0] stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_starting_addr, - input logic [15:0] stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_0, - input logic [15:0] stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_1, - input logic [15:0] stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_2, - input logic [15:0] stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_3, - input logic [15:0] stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_4, - input logic [15:0] stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_5, - output logic stencil_valid_f_ -); - -stencil_valid stencil_valid_inst ( - .clk(clk), - .clk_en(clk_en), - .flush(flush), - .loops_stencil_valid_dimensionality(stencil_valid_inst_loops_stencil_valid_dimensionality), - .loops_stencil_valid_ranges_0(stencil_valid_inst_loops_stencil_valid_ranges_0), - .loops_stencil_valid_ranges_1(stencil_valid_inst_loops_stencil_valid_ranges_1), - .loops_stencil_valid_ranges_2(stencil_valid_inst_loops_stencil_valid_ranges_2), - .loops_stencil_valid_ranges_3(stencil_valid_inst_loops_stencil_valid_ranges_3), - .loops_stencil_valid_ranges_4(stencil_valid_inst_loops_stencil_valid_ranges_4), - .loops_stencil_valid_ranges_5(stencil_valid_inst_loops_stencil_valid_ranges_5), - .rst_n(rst_n), - .stencil_valid_sched_gen_enable(stencil_valid_inst_stencil_valid_sched_gen_enable), - .stencil_valid_sched_gen_sched_addr_gen_starting_addr(stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_starting_addr), - .stencil_valid_sched_gen_sched_addr_gen_strides_0(stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_0), - .stencil_valid_sched_gen_sched_addr_gen_strides_1(stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_1), - .stencil_valid_sched_gen_sched_addr_gen_strides_2(stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_2), - .stencil_valid_sched_gen_sched_addr_gen_strides_3(stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_3), - .stencil_valid_sched_gen_sched_addr_gen_strides_4(stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_4), - .stencil_valid_sched_gen_sched_addr_gen_strides_5(stencil_valid_inst_stencil_valid_sched_gen_sched_addr_gen_strides_5), - .stencil_valid(stencil_valid_f_) -); - -endmodule // stencil_valid_flat - -module storage_config_seq_2_64_16 ( - input logic clk, - input logic clk_en, - input logic [7:0] config_addr_in, - input logic [15:0] config_data_in, - input logic [1:0] config_en, - input logic config_rd, - input logic config_wr, - input logic flush, - input logic [0:0][3:0] [15:0] rd_data_stg, - input logic rst_n, - output logic [8:0] addr_out, - output logic [1:0] [15:0] rd_data_out, - output logic ren_out, - output logic wen_out, - output logic [3:0] [15:0] wr_data -); - -logic [1:0] cnt; -logic [2:0][15:0] data_wr_reg; -logic [1:0] rd_cnt; -logic rd_valid; -logic [1:0] reduce_en; -logic set_to_addr; -assign reduce_en[0] = |config_en[0]; -assign reduce_en[1] = |config_en[1]; -always_comb begin - set_to_addr = 1'h0; - for (int unsigned i = 0; i < 2; i += 1) begin - if (reduce_en[1'(i)]) begin - set_to_addr = 1'(i); - end - end -end -assign addr_out = {set_to_addr, config_addr_in}; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - cnt <= 2'h0; - end - else if (flush) begin - cnt <= 2'h0; - end - else if (config_wr & (|config_en)) begin - cnt <= cnt + 2'h1; - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - rd_valid <= 1'h0; - end - else if (flush) begin - rd_valid <= 1'h0; - end - else rd_valid <= config_rd & (|config_en); -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - rd_cnt <= 2'h0; - end - else if (flush) begin - rd_cnt <= 2'h0; - end - else if (rd_valid & (~(config_rd & (|config_en)))) begin - rd_cnt <= rd_cnt + 2'h1; - end -end -assign rd_data_out[0] = rd_data_stg[0][rd_cnt]; -assign rd_data_out[1] = rd_data_stg[0][rd_cnt]; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - data_wr_reg <= 48'h0; - end - else if (flush) begin - data_wr_reg <= 48'h0; - end - else if (config_wr & (cnt < 2'h3)) begin - data_wr_reg[cnt] <= config_data_in; - end -end -assign wr_data[0] = data_wr_reg[0]; -assign wr_data[1] = data_wr_reg[1]; -assign wr_data[2] = data_wr_reg[2]; -assign wr_data[3] = config_data_in; -assign wen_out = config_wr & (cnt == 2'h3); -assign ren_out = config_rd; -endmodule // storage_config_seq_2_64_16 - -module strg_ram_64_512_delay1 ( - input logic clk, - input logic clk_en, - input logic [0:0][3:0] [15:0] data_from_strg, - input logic [16:0] data_in, - input logic flush, - input logic [16:0] rd_addr_in, - input logic ren, - input logic rst_n, - input logic wen, - input logic [16:0] wr_addr_in, - output logic [0:0] [8:0] addr_out, - output logic [16:0] data_out, - output logic [0:0][3:0] [15:0] data_to_strg, - output logic ready, - output logic ren_to_strg, - output logic valid_out, - output logic wen_to_strg -); - -typedef enum logic[1:0] { - IDLE = 2'h0, - MODIFY = 2'h1, - READ = 2'h2, - _DEFAULT = 2'h3 -} r_w_seq_state; -logic [15:0] addr_to_write; -logic [3:0][15:0] data_combined; -logic [15:0] data_to_write; -r_w_seq_state r_w_seq_current_state; -r_w_seq_state r_w_seq_next_state; -logic [15:0] rd_addr; -logic rd_bank; -logic read_gate; -logic [15:0] wr_addr; -logic write_gate; -assign wr_addr = wr_addr_in[15:0]; -assign rd_addr = wr_addr_in[15:0]; -assign rd_bank = 1'h0; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - data_to_write <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - data_to_write <= 16'h0; - end - else data_to_write <= data_in[15:0]; - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - addr_to_write <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - addr_to_write <= 16'h0; - end - else addr_to_write <= wr_addr; - end -end -assign data_to_strg[0] = data_combined; -assign ren_to_strg = (wen | ren) & read_gate; -assign wen_to_strg = write_gate; -always_comb begin - addr_out[0] = rd_addr[10:2]; - if (wen & (~write_gate)) begin - addr_out[0] = wr_addr[10:2]; - end - else if (write_gate) begin - addr_out[0] = addr_to_write[10:2]; - end -end -always_comb begin - if (addr_to_write[1:0] == 2'h0) begin - data_combined[0] = data_to_write; - end - else data_combined[0] = data_from_strg[rd_bank][0]; -end -always_comb begin - if (addr_to_write[1:0] == 2'h1) begin - data_combined[1] = data_to_write; - end - else data_combined[1] = data_from_strg[rd_bank][1]; -end -always_comb begin - if (addr_to_write[1:0] == 2'h2) begin - data_combined[2] = data_to_write; - end - else data_combined[2] = data_from_strg[rd_bank][2]; -end -always_comb begin - if (addr_to_write[1:0] == 2'h3) begin - data_combined[3] = data_to_write; - end - else data_combined[3] = data_from_strg[rd_bank][3]; -end - -always_ff @(posedge clk, negedge rst_n) begin - if (!rst_n) begin - r_w_seq_current_state <= IDLE; - end - else r_w_seq_current_state <= r_w_seq_next_state; -end -always_comb begin - r_w_seq_next_state = r_w_seq_current_state; - unique case (r_w_seq_current_state) - IDLE: begin - if ((~wen) & (~ren)) begin - r_w_seq_next_state = IDLE; - end - else if (ren & (~wen)) begin - r_w_seq_next_state = READ; - end - else if (wen) begin - r_w_seq_next_state = MODIFY; - end - end - MODIFY: begin - if (1'h1) begin - r_w_seq_next_state = IDLE; - end - end - READ: begin - if ((~wen) & (~ren)) begin - r_w_seq_next_state = IDLE; - end - else if (ren & (~wen)) begin - r_w_seq_next_state = READ; - end - else if (wen) begin - r_w_seq_next_state = MODIFY; - end - end - _DEFAULT: begin - if (1'h1) begin - r_w_seq_next_state = _DEFAULT; - end - end - default: begin end - endcase -end -always_comb begin - unique case (r_w_seq_current_state) - IDLE: begin :r_w_seq_IDLE_Output - ready = 1'h1; - valid_out = 1'h0; - data_out[15:0] = 16'h0; - data_out[16] = 1'h0; - write_gate = 1'h0; - read_gate = 1'h1; - end :r_w_seq_IDLE_Output - MODIFY: begin :r_w_seq_MODIFY_Output - ready = 1'h0; - valid_out = 1'h0; - data_out[15:0] = 16'h0; - data_out[16] = 1'h0; - write_gate = 1'h1; - read_gate = 1'h0; - end :r_w_seq_MODIFY_Output - READ: begin :r_w_seq_READ_Output - ready = 1'h1; - valid_out = 1'h1; - data_out[15:0] = data_from_strg[rd_bank][addr_to_write[1:0]]; - data_out[16] = 1'h0; - write_gate = 1'h0; - read_gate = 1'h1; - end :r_w_seq_READ_Output - _DEFAULT: begin :r_w_seq__DEFAULT_Output - ready = 1'h0; - valid_out = 1'h0; - data_out[15:0] = 16'h0; - data_out[16] = 1'h0; - write_gate = 1'h0; - read_gate = 1'h0; - end :r_w_seq__DEFAULT_Output - default: begin end - endcase -end -endmodule // strg_ram_64_512_delay1 - -module strg_ram_64_512_delay1_flat ( - input logic clk, - input logic clk_en, - input logic [0:0] [16:0] data_in_f_, - input logic flush, - input logic [0:0] [16:0] rd_addr_in_f_, - input logic ren_f_, - input logic rst_n, - input logic [0:0][3:0] [15:0] strg_ram_64_512_delay1_inst_data_from_strg_lifted, - input logic wen_f_, - input logic [0:0] [16:0] wr_addr_in_f_, - output logic [0:0] [16:0] data_out_f_, - output logic ready_f_, - output logic [0:0] [8:0] strg_ram_64_512_delay1_inst_addr_out_lifted, - output logic [0:0][3:0] [15:0] strg_ram_64_512_delay1_inst_data_to_strg_lifted, - output logic strg_ram_64_512_delay1_inst_ren_to_strg_lifted, - output logic strg_ram_64_512_delay1_inst_wen_to_strg_lifted, - output logic valid_out_f_ -); - -strg_ram_64_512_delay1 strg_ram_64_512_delay1_inst ( - .clk(clk), - .clk_en(clk_en), - .data_from_strg(strg_ram_64_512_delay1_inst_data_from_strg_lifted), - .data_in(data_in_f_), - .flush(flush), - .rd_addr_in(rd_addr_in_f_), - .ren(ren_f_), - .rst_n(rst_n), - .wen(wen_f_), - .wr_addr_in(wr_addr_in_f_), - .addr_out(strg_ram_64_512_delay1_inst_addr_out_lifted), - .data_out(data_out_f_), - .data_to_strg(strg_ram_64_512_delay1_inst_data_to_strg_lifted), - .ready(ready_f_), - .ren_to_strg(strg_ram_64_512_delay1_inst_ren_to_strg_lifted), - .valid_out(valid_out_f_), - .wen_to_strg(strg_ram_64_512_delay1_inst_wen_to_strg_lifted) -); - -endmodule // strg_ram_64_512_delay1_flat - -module strg_ub_agg_only ( - input logic [1:0] agg_read, - input logic [2:0] agg_write_addr_gen_0_starting_addr, - input logic [2:0] agg_write_addr_gen_0_strides_0, - input logic [2:0] agg_write_addr_gen_0_strides_1, - input logic [2:0] agg_write_addr_gen_0_strides_2, - input logic [2:0] agg_write_addr_gen_1_starting_addr, - input logic [2:0] agg_write_addr_gen_1_strides_0, - input logic [2:0] agg_write_addr_gen_1_strides_1, - input logic [2:0] agg_write_addr_gen_1_strides_2, - input logic agg_write_sched_gen_0_enable, - input logic [15:0] agg_write_sched_gen_0_sched_addr_gen_starting_addr, - input logic [15:0] agg_write_sched_gen_0_sched_addr_gen_strides_0, - input logic [15:0] agg_write_sched_gen_0_sched_addr_gen_strides_1, - input logic [15:0] agg_write_sched_gen_0_sched_addr_gen_strides_2, - input logic agg_write_sched_gen_1_enable, - input logic [15:0] agg_write_sched_gen_1_sched_addr_gen_starting_addr, - input logic [15:0] agg_write_sched_gen_1_sched_addr_gen_strides_0, - input logic [15:0] agg_write_sched_gen_1_sched_addr_gen_strides_1, - input logic [15:0] agg_write_sched_gen_1_sched_addr_gen_strides_2, - input logic clk, - input logic clk_en, - input logic [15:0] cycle_count, - input logic [1:0] [15:0] data_in, - input logic flush, - input logic [2:0] loops_in2buf_0_dimensionality, - input logic [10:0] loops_in2buf_0_ranges_0, - input logic [10:0] loops_in2buf_0_ranges_1, - input logic [10:0] loops_in2buf_0_ranges_2, - input logic [2:0] loops_in2buf_1_dimensionality, - input logic [10:0] loops_in2buf_1_ranges_0, - input logic [10:0] loops_in2buf_1_ranges_1, - input logic [10:0] loops_in2buf_1_ranges_2, - input logic rst_n, - input logic [1:0] [8:0] sram_read_addr_in, - input logic [1:0] [2:0] tb_read_addr_d_in, - input logic [1:0] tb_read_d_in, - input logic [1:0] [1:0] update_mode_in, - output logic [1:0][3:0] [15:0] agg_data_out, - output logic [1:0] [1:0] agg_write_addr_l2b_out, - output logic [1:0] [2:0] agg_write_mux_sel_out, - output logic [1:0] agg_write_out, - output logic [1:0] agg_write_restart_out -); - -logic [1:0][1:0][3:0][15:0] agg; -logic [1:0] agg_read_addr; -logic [1:0][7:0] agg_read_addr_gen_out; -logic [1:0] agg_read_addr_in; -logic [1:0] agg_write; -logic [1:0][2:0] agg_write_addr; -logic [2:0] agg_write_addr_gen_0_addr_out; -logic [2:0][2:0] agg_write_addr_gen_0_strides; -logic [2:0] agg_write_addr_gen_1_addr_out; -logic [2:0][2:0] agg_write_addr_gen_1_strides; -logic agg_write_sched_gen_0_valid_output; -logic agg_write_sched_gen_1_valid_output; -logic [2:0] fl_mux_sel_0; -logic [2:0] fl_mux_sel_1; -logic [1:0] loops_in2buf_0_mux_sel_out; -logic [2:0][10:0] loops_in2buf_0_ranges; -logic loops_in2buf_0_restart; -logic [1:0] loops_in2buf_1_mux_sel_out; -logic [2:0][10:0] loops_in2buf_1_ranges; -logic loops_in2buf_1_restart; -logic [1:0] mode_0; -logic [1:0] mode_1; -logic [2:0] tb_addr_0; -logic [2:0] tb_addr_1; -logic tb_read_0; -logic tb_read_1; -assign agg_write_out = agg_write; -assign mode_0 = update_mode_in[0]; -assign agg_write_addr_l2b_out[0] = agg_write_addr[0][1:0]; -assign tb_read_0 = mode_0[0] ? tb_read_d_in[1]: tb_read_d_in[0]; -assign tb_addr_0 = mode_0[0] ? tb_read_addr_d_in[1]: tb_read_addr_d_in[0]; -assign fl_mux_sel_0[1:0] = loops_in2buf_0_mux_sel_out; -assign fl_mux_sel_0[2] = 1'h0; -assign agg_write_mux_sel_out[0] = fl_mux_sel_0; -assign agg_write_restart_out[0] = loops_in2buf_0_restart; -assign agg_write_addr[0] = mode_0[1] ? tb_addr_0: agg_write_addr_gen_0_addr_out; -assign agg_write[0] = mode_0[1] ? tb_read_0: agg_write_sched_gen_0_valid_output; - -always_ff @(posedge clk) begin - if (clk_en) begin - if (agg_write[0]) begin - agg[0][agg_write_addr[0][2]][agg_write_addr[0][1:0]] <= data_in[0]; - end - end -end -assign agg_read_addr_in[0] = sram_read_addr_in[0][0]; -assign agg_read_addr_gen_out[0][0] = agg_read_addr_in[0]; -assign agg_read_addr_gen_out[0][7:1] = 7'h0; -assign agg_read_addr[0] = agg_read_addr_gen_out[0][0]; -always_comb begin - agg_data_out[0] = agg[0][agg_read_addr[0]]; -end -assign mode_1 = update_mode_in[1]; -assign agg_write_addr_l2b_out[1] = agg_write_addr[1][1:0]; -assign tb_read_1 = mode_1[0] ? tb_read_d_in[1]: tb_read_d_in[0]; -assign tb_addr_1 = mode_1[0] ? tb_read_addr_d_in[1]: tb_read_addr_d_in[0]; -assign fl_mux_sel_1[1:0] = loops_in2buf_1_mux_sel_out; -assign fl_mux_sel_1[2] = 1'h0; -assign agg_write_mux_sel_out[1] = fl_mux_sel_1; -assign agg_write_restart_out[1] = loops_in2buf_1_restart; -assign agg_write_addr[1] = mode_1[1] ? tb_addr_1: agg_write_addr_gen_1_addr_out; -assign agg_write[1] = mode_1[1] ? tb_read_1: agg_write_sched_gen_1_valid_output; - -always_ff @(posedge clk) begin - if (clk_en) begin - if (agg_write[1]) begin - agg[1][agg_write_addr[1][2]][agg_write_addr[1][1:0]] <= data_in[1]; - end - end -end -assign agg_read_addr_in[1] = sram_read_addr_in[1][0]; -assign agg_read_addr_gen_out[1][0] = agg_read_addr_in[1]; -assign agg_read_addr_gen_out[1][7:1] = 7'h0; -assign agg_read_addr[1] = agg_read_addr_gen_out[1][0]; -always_comb begin - agg_data_out[1] = agg[1][agg_read_addr[1]]; -end -assign loops_in2buf_0_ranges[0] = loops_in2buf_0_ranges_0; -assign loops_in2buf_0_ranges[1] = loops_in2buf_0_ranges_1; -assign loops_in2buf_0_ranges[2] = loops_in2buf_0_ranges_2; -assign agg_write_addr_gen_0_strides[0] = agg_write_addr_gen_0_strides_0; -assign agg_write_addr_gen_0_strides[1] = agg_write_addr_gen_0_strides_1; -assign agg_write_addr_gen_0_strides[2] = agg_write_addr_gen_0_strides_2; -assign loops_in2buf_1_ranges[0] = loops_in2buf_1_ranges_0; -assign loops_in2buf_1_ranges[1] = loops_in2buf_1_ranges_1; -assign loops_in2buf_1_ranges[2] = loops_in2buf_1_ranges_2; -assign agg_write_addr_gen_1_strides[0] = agg_write_addr_gen_1_strides_0; -assign agg_write_addr_gen_1_strides[1] = agg_write_addr_gen_1_strides_1; -assign agg_write_addr_gen_1_strides[2] = agg_write_addr_gen_1_strides_2; -for_loop_3_11 loops_in2buf_0 ( - .clk(clk), - .clk_en(clk_en), - .dimensionality(loops_in2buf_0_dimensionality), - .flush(flush), - .ranges(loops_in2buf_0_ranges), - .rst_n(rst_n), - .step(agg_write[0]), - .mux_sel_out(loops_in2buf_0_mux_sel_out), - .restart(loops_in2buf_0_restart) -); - -addr_gen_3_3 agg_write_addr_gen_0 ( - .clk(clk), - .clk_en(clk_en), - .flush(flush), - .mux_sel(loops_in2buf_0_mux_sel_out), - .restart(loops_in2buf_0_restart), - .rst_n(rst_n), - .starting_addr(agg_write_addr_gen_0_starting_addr), - .step(agg_write[0]), - .strides(agg_write_addr_gen_0_strides), - .addr_out(agg_write_addr_gen_0_addr_out) -); - -sched_gen_3_16 agg_write_sched_gen_0 ( - .clk(clk), - .clk_en(clk_en), - .cycle_count(cycle_count), - .enable(agg_write_sched_gen_0_enable), - .finished(loops_in2buf_0_restart), - .flush(flush), - .mux_sel(loops_in2buf_0_mux_sel_out), - .rst_n(rst_n), - .sched_addr_gen_starting_addr(agg_write_sched_gen_0_sched_addr_gen_starting_addr), - .sched_addr_gen_strides_0(agg_write_sched_gen_0_sched_addr_gen_strides_0), - .sched_addr_gen_strides_1(agg_write_sched_gen_0_sched_addr_gen_strides_1), - .sched_addr_gen_strides_2(agg_write_sched_gen_0_sched_addr_gen_strides_2), - .valid_output(agg_write_sched_gen_0_valid_output) -); - -for_loop_3_11 loops_in2buf_1 ( - .clk(clk), - .clk_en(clk_en), - .dimensionality(loops_in2buf_1_dimensionality), - .flush(flush), - .ranges(loops_in2buf_1_ranges), - .rst_n(rst_n), - .step(agg_write[1]), - .mux_sel_out(loops_in2buf_1_mux_sel_out), - .restart(loops_in2buf_1_restart) -); - -addr_gen_3_3 agg_write_addr_gen_1 ( - .clk(clk), - .clk_en(clk_en), - .flush(flush), - .mux_sel(loops_in2buf_1_mux_sel_out), - .restart(loops_in2buf_1_restart), - .rst_n(rst_n), - .starting_addr(agg_write_addr_gen_1_starting_addr), - .step(agg_write[1]), - .strides(agg_write_addr_gen_1_strides), - .addr_out(agg_write_addr_gen_1_addr_out) -); - -sched_gen_3_16 agg_write_sched_gen_1 ( - .clk(clk), - .clk_en(clk_en), - .cycle_count(cycle_count), - .enable(agg_write_sched_gen_1_enable), - .finished(loops_in2buf_1_restart), - .flush(flush), - .mux_sel(loops_in2buf_1_mux_sel_out), - .rst_n(rst_n), - .sched_addr_gen_starting_addr(agg_write_sched_gen_1_sched_addr_gen_starting_addr), - .sched_addr_gen_strides_0(agg_write_sched_gen_1_sched_addr_gen_strides_0), - .sched_addr_gen_strides_1(agg_write_sched_gen_1_sched_addr_gen_strides_1), - .sched_addr_gen_strides_2(agg_write_sched_gen_1_sched_addr_gen_strides_2), - .valid_output(agg_write_sched_gen_1_valid_output) -); - -endmodule // strg_ub_agg_only - -module strg_ub_agg_sram_shared ( - input logic [7:0] agg_read_sched_gen_0_agg_read_padding, - input logic [7:0] agg_read_sched_gen_1_agg_read_padding, - input logic [8:0] agg_sram_shared_addr_gen_0_starting_addr, - input logic [8:0] agg_sram_shared_addr_gen_1_starting_addr, - input logic [1:0] [1:0] agg_write_addr_l2b_in, - input logic [1:0] agg_write_in, - input logic [1:0] [2:0] agg_write_mux_sel_in, - input logic [1:0] agg_write_restart_in, - input logic clk, - input logic clk_en, - input logic flush, - input logic [1:0] mode_0, - input logic [1:0] mode_1, - input logic rst_n, - input logic [1:0] [8:0] sram_read_addr_in, - input logic [1:0] sram_read_d_in, - input logic [1:0] sram_read_in, - output logic [1:0] agg_read_out, - output logic [1:0] [8:0] agg_sram_shared_addr_out, - output logic [1:0] [1:0] update_mode_out -); - -logic [1:0] agg_read; -logic agg_read_sched_gen_0_valid_output; -logic agg_read_sched_gen_1_valid_output; -logic [8:0] agg_sram_shared_addr_gen_0_addr_out; -logic [8:0] agg_sram_shared_addr_gen_1_addr_out; -assign agg_read_out = agg_read; -assign update_mode_out[0] = mode_0; -assign agg_read[0] = agg_read_sched_gen_0_valid_output; -assign agg_sram_shared_addr_out[0] = agg_sram_shared_addr_gen_0_addr_out; -assign update_mode_out[1] = mode_1; -assign agg_read[1] = agg_read_sched_gen_1_valid_output; -assign agg_sram_shared_addr_out[1] = agg_sram_shared_addr_gen_1_addr_out; -agg_sram_shared_sched_gen agg_read_sched_gen_0 ( - .agg_read_padding(agg_read_sched_gen_0_agg_read_padding), - .agg_write(agg_write_in[0]), - .agg_write_addr_l2b(agg_write_addr_l2b_in[0]), - .agg_write_mux_sel(agg_write_mux_sel_in[0]), - .agg_write_restart(agg_write_restart_in[0]), - .clk(clk), - .clk_en(clk_en), - .flush(flush), - .mode(mode_0), - .rst_n(rst_n), - .sram_read_d(sram_read_d_in), - .valid_output(agg_read_sched_gen_0_valid_output) -); - -agg_sram_shared_addr_gen agg_sram_shared_addr_gen_0 ( - .clk(clk), - .clk_en(clk_en), - .flush(flush), - .mode(mode_0), - .rst_n(rst_n), - .sram_read(sram_read_in), - .sram_read_addr(sram_read_addr_in), - .starting_addr(agg_sram_shared_addr_gen_0_starting_addr), - .step(agg_read[0]), - .addr_out(agg_sram_shared_addr_gen_0_addr_out) -); - -agg_sram_shared_sched_gen agg_read_sched_gen_1 ( - .agg_read_padding(agg_read_sched_gen_1_agg_read_padding), - .agg_write(agg_write_in[1]), - .agg_write_addr_l2b(agg_write_addr_l2b_in[1]), - .agg_write_mux_sel(agg_write_mux_sel_in[1]), - .agg_write_restart(agg_write_restart_in[1]), - .clk(clk), - .clk_en(clk_en), - .flush(flush), - .mode(mode_1), - .rst_n(rst_n), - .sram_read_d(sram_read_d_in), - .valid_output(agg_read_sched_gen_1_valid_output) -); - -agg_sram_shared_addr_gen agg_sram_shared_addr_gen_1 ( - .clk(clk), - .clk_en(clk_en), - .flush(flush), - .mode(mode_1), - .rst_n(rst_n), - .sram_read(sram_read_in), - .sram_read_addr(sram_read_addr_in), - .starting_addr(agg_sram_shared_addr_gen_1_starting_addr), - .step(agg_read[1]), - .addr_out(agg_sram_shared_addr_gen_1_addr_out) -); - -endmodule // strg_ub_agg_sram_shared - -module strg_ub_sram_only ( - input logic [1:0][3:0] [15:0] agg_data_out, - input logic [1:0] agg_read, - input logic clk, - input logic clk_en, - input logic [15:0] cycle_count, - input logic flush, - input logic [1:0] [2:0] loops_sram2tb_mux_sel, - input logic [1:0] loops_sram2tb_restart, - input logic [8:0] output_addr_gen_0_starting_addr, - input logic [8:0] output_addr_gen_0_strides_0, - input logic [8:0] output_addr_gen_0_strides_1, - input logic [8:0] output_addr_gen_0_strides_2, - input logic [8:0] output_addr_gen_0_strides_3, - input logic [8:0] output_addr_gen_0_strides_4, - input logic [8:0] output_addr_gen_0_strides_5, - input logic [8:0] output_addr_gen_1_starting_addr, - input logic [8:0] output_addr_gen_1_strides_0, - input logic [8:0] output_addr_gen_1_strides_1, - input logic [8:0] output_addr_gen_1_strides_2, - input logic [8:0] output_addr_gen_1_strides_3, - input logic [8:0] output_addr_gen_1_strides_4, - input logic [8:0] output_addr_gen_1_strides_5, - input logic rst_n, - input logic [1:0] [8:0] sram_read_addr_in, - input logic [1:0] t_read, - output logic [8:0] addr_to_sram, - output logic cen_to_sram, - output logic [3:0] [15:0] data_to_sram, - output logic [1:0] [8:0] sram_read_addr_out, - output logic wen_to_sram -); - -logic [8:0] addr; -logic [3:0][15:0] decode_ret_agg_read_agg_data_out; -logic [15:0] decode_ret_agg_read_s_write_addr; -logic [15:0] decode_ret_t_read_s_read_addr; -logic decode_sel_done_agg_read_agg_data_out; -logic decode_sel_done_agg_read_s_write_addr; -logic decode_sel_done_t_read_s_read_addr; -logic [8:0] output_addr_gen_0_addr_out; -logic [5:0][8:0] output_addr_gen_0_strides; -logic [8:0] output_addr_gen_1_addr_out; -logic [5:0][8:0] output_addr_gen_1_strides; -logic read; -logic [1:0][15:0] s_read_addr; -logic [1:0][15:0] s_write_addr; -logic [3:0][15:0] sram_write_data; -logic write; -assign s_write_addr[0][8:0] = sram_read_addr_in[0]; -assign s_write_addr[0][15:9] = 7'h0; -assign s_write_addr[1][8:0] = sram_read_addr_in[1]; -assign s_write_addr[1][15:9] = 7'h0; -assign s_read_addr[0][8:0] = output_addr_gen_0_addr_out; -assign s_read_addr[0][15:9] = 7'h0; -assign sram_read_addr_out[0] = output_addr_gen_0_addr_out; -assign s_read_addr[1][8:0] = output_addr_gen_1_addr_out; -assign s_read_addr[1][15:9] = 7'h0; -assign sram_read_addr_out[1] = output_addr_gen_1_addr_out; -assign data_to_sram = sram_write_data; -assign wen_to_sram = write; -always_comb begin - decode_sel_done_agg_read_s_write_addr = 1'h0; - decode_ret_agg_read_s_write_addr = 16'h0; - for (int unsigned i = 0; i < 2; i += 1) begin - if ((~decode_sel_done_agg_read_s_write_addr) & agg_read[1'(i)]) begin - decode_ret_agg_read_s_write_addr = s_write_addr[1'(i)]; - decode_sel_done_agg_read_s_write_addr = 1'h1; - end - end -end -always_comb begin - decode_sel_done_t_read_s_read_addr = 1'h0; - decode_ret_t_read_s_read_addr = 16'h0; - for (int unsigned i = 0; i < 2; i += 1) begin - if ((~decode_sel_done_t_read_s_read_addr) & t_read[1'(i)]) begin - decode_ret_t_read_s_read_addr = s_read_addr[1'(i)]; - decode_sel_done_t_read_s_read_addr = 1'h1; - end - end -end -assign cen_to_sram = write | read; -assign addr_to_sram = addr; -always_comb begin - if (write) begin - addr = decode_ret_agg_read_s_write_addr[8:0]; - end - else addr = decode_ret_t_read_s_read_addr[8:0]; -end -assign write = |agg_read; -assign read = |t_read; -always_comb begin - decode_sel_done_agg_read_agg_data_out = 1'h0; - decode_ret_agg_read_agg_data_out = 64'h0; - for (int unsigned i = 0; i < 2; i += 1) begin - if ((~decode_sel_done_agg_read_agg_data_out) & agg_read[1'(i)]) begin - decode_ret_agg_read_agg_data_out = agg_data_out[1'(i)]; - decode_sel_done_agg_read_agg_data_out = 1'h1; - end - end -end -assign sram_write_data = decode_ret_agg_read_agg_data_out; -assign output_addr_gen_0_strides[0] = output_addr_gen_0_strides_0; -assign output_addr_gen_0_strides[1] = output_addr_gen_0_strides_1; -assign output_addr_gen_0_strides[2] = output_addr_gen_0_strides_2; -assign output_addr_gen_0_strides[3] = output_addr_gen_0_strides_3; -assign output_addr_gen_0_strides[4] = output_addr_gen_0_strides_4; -assign output_addr_gen_0_strides[5] = output_addr_gen_0_strides_5; -assign output_addr_gen_1_strides[0] = output_addr_gen_1_strides_0; -assign output_addr_gen_1_strides[1] = output_addr_gen_1_strides_1; -assign output_addr_gen_1_strides[2] = output_addr_gen_1_strides_2; -assign output_addr_gen_1_strides[3] = output_addr_gen_1_strides_3; -assign output_addr_gen_1_strides[4] = output_addr_gen_1_strides_4; -assign output_addr_gen_1_strides[5] = output_addr_gen_1_strides_5; -addr_gen_6_9 output_addr_gen_0 ( - .clk(clk), - .clk_en(clk_en), - .flush(flush), - .mux_sel(loops_sram2tb_mux_sel[0]), - .restart(loops_sram2tb_restart[0]), - .rst_n(rst_n), - .starting_addr(output_addr_gen_0_starting_addr), - .step(t_read[0]), - .strides(output_addr_gen_0_strides), - .addr_out(output_addr_gen_0_addr_out) -); - -addr_gen_6_9 output_addr_gen_1 ( - .clk(clk), - .clk_en(clk_en), - .flush(flush), - .mux_sel(loops_sram2tb_mux_sel[1]), - .restart(loops_sram2tb_restart[1]), - .rst_n(rst_n), - .starting_addr(output_addr_gen_1_starting_addr), - .step(t_read[1]), - .strides(output_addr_gen_1_strides), - .addr_out(output_addr_gen_1_addr_out) -); - -endmodule // strg_ub_sram_only - -module strg_ub_sram_tb_shared ( - input logic clk, - input logic clk_en, - input logic [15:0] cycle_count, - input logic flush, - input logic [3:0] loops_buf2out_autovec_read_0_dimensionality, - input logic [10:0] loops_buf2out_autovec_read_0_ranges_0, - input logic [10:0] loops_buf2out_autovec_read_0_ranges_1, - input logic [10:0] loops_buf2out_autovec_read_0_ranges_2, - input logic [10:0] loops_buf2out_autovec_read_0_ranges_3, - input logic [10:0] loops_buf2out_autovec_read_0_ranges_4, - input logic [10:0] loops_buf2out_autovec_read_0_ranges_5, - input logic [3:0] loops_buf2out_autovec_read_1_dimensionality, - input logic [10:0] loops_buf2out_autovec_read_1_ranges_0, - input logic [10:0] loops_buf2out_autovec_read_1_ranges_1, - input logic [10:0] loops_buf2out_autovec_read_1_ranges_2, - input logic [10:0] loops_buf2out_autovec_read_1_ranges_3, - input logic [10:0] loops_buf2out_autovec_read_1_ranges_4, - input logic [10:0] loops_buf2out_autovec_read_1_ranges_5, - input logic output_sched_gen_0_enable, - input logic [9:0] output_sched_gen_0_sched_addr_gen_delay, - input logic [15:0] output_sched_gen_0_sched_addr_gen_starting_addr, - input logic [15:0] output_sched_gen_0_sched_addr_gen_strides_0, - input logic [15:0] output_sched_gen_0_sched_addr_gen_strides_1, - input logic [15:0] output_sched_gen_0_sched_addr_gen_strides_2, - input logic [15:0] output_sched_gen_0_sched_addr_gen_strides_3, - input logic [15:0] output_sched_gen_0_sched_addr_gen_strides_4, - input logic [15:0] output_sched_gen_0_sched_addr_gen_strides_5, - input logic output_sched_gen_1_enable, - input logic [9:0] output_sched_gen_1_sched_addr_gen_delay, - input logic [15:0] output_sched_gen_1_sched_addr_gen_starting_addr, - input logic [15:0] output_sched_gen_1_sched_addr_gen_strides_0, - input logic [15:0] output_sched_gen_1_sched_addr_gen_strides_1, - input logic [15:0] output_sched_gen_1_sched_addr_gen_strides_2, - input logic [15:0] output_sched_gen_1_sched_addr_gen_strides_3, - input logic [15:0] output_sched_gen_1_sched_addr_gen_strides_4, - input logic [15:0] output_sched_gen_1_sched_addr_gen_strides_5, - input logic rst_n, - output logic [1:0] [2:0] loops_sram2tb_mux_sel, - output logic [1:0] loops_sram2tb_restart, - output logic [1:0] sram_read_d, - output logic [1:0] t_read_out -); - -logic [2:0] loops_buf2out_autovec_read_0_mux_sel_out; -logic [5:0][10:0] loops_buf2out_autovec_read_0_ranges; -logic loops_buf2out_autovec_read_0_restart; -logic [2:0] loops_buf2out_autovec_read_1_mux_sel_out; -logic [5:0][10:0] loops_buf2out_autovec_read_1_ranges; -logic loops_buf2out_autovec_read_1_restart; -logic output_sched_gen_0_valid_output; -logic output_sched_gen_0_valid_output_d; -logic output_sched_gen_1_valid_output; -logic output_sched_gen_1_valid_output_d; -logic [1:0] t_read; -assign t_read_out = t_read; -assign loops_sram2tb_mux_sel[0] = loops_buf2out_autovec_read_0_mux_sel_out; -assign loops_sram2tb_restart[0] = loops_buf2out_autovec_read_0_restart; -assign t_read[0] = output_sched_gen_0_valid_output; -assign sram_read_d[0] = output_sched_gen_0_valid_output_d; -assign loops_sram2tb_mux_sel[1] = loops_buf2out_autovec_read_1_mux_sel_out; -assign loops_sram2tb_restart[1] = loops_buf2out_autovec_read_1_restart; -assign t_read[1] = output_sched_gen_1_valid_output; -assign sram_read_d[1] = output_sched_gen_1_valid_output_d; -assign loops_buf2out_autovec_read_0_ranges[0] = loops_buf2out_autovec_read_0_ranges_0; -assign loops_buf2out_autovec_read_0_ranges[1] = loops_buf2out_autovec_read_0_ranges_1; -assign loops_buf2out_autovec_read_0_ranges[2] = loops_buf2out_autovec_read_0_ranges_2; -assign loops_buf2out_autovec_read_0_ranges[3] = loops_buf2out_autovec_read_0_ranges_3; -assign loops_buf2out_autovec_read_0_ranges[4] = loops_buf2out_autovec_read_0_ranges_4; -assign loops_buf2out_autovec_read_0_ranges[5] = loops_buf2out_autovec_read_0_ranges_5; -assign loops_buf2out_autovec_read_1_ranges[0] = loops_buf2out_autovec_read_1_ranges_0; -assign loops_buf2out_autovec_read_1_ranges[1] = loops_buf2out_autovec_read_1_ranges_1; -assign loops_buf2out_autovec_read_1_ranges[2] = loops_buf2out_autovec_read_1_ranges_2; -assign loops_buf2out_autovec_read_1_ranges[3] = loops_buf2out_autovec_read_1_ranges_3; -assign loops_buf2out_autovec_read_1_ranges[4] = loops_buf2out_autovec_read_1_ranges_4; -assign loops_buf2out_autovec_read_1_ranges[5] = loops_buf2out_autovec_read_1_ranges_5; -for_loop_6_11 loops_buf2out_autovec_read_0 ( - .clk(clk), - .clk_en(clk_en), - .dimensionality(loops_buf2out_autovec_read_0_dimensionality), - .flush(flush), - .ranges(loops_buf2out_autovec_read_0_ranges), - .rst_n(rst_n), - .step(t_read[0]), - .mux_sel_out(loops_buf2out_autovec_read_0_mux_sel_out), - .restart(loops_buf2out_autovec_read_0_restart) -); - -sched_gen_6_16_delay_addr_10_4 output_sched_gen_0 ( - .clk(clk), - .clk_en(clk_en), - .cycle_count(cycle_count), - .enable(output_sched_gen_0_enable), - .finished(loops_buf2out_autovec_read_0_restart), - .flush(flush), - .mux_sel(loops_buf2out_autovec_read_0_mux_sel_out), - .rst_n(rst_n), - .sched_addr_gen_delay(output_sched_gen_0_sched_addr_gen_delay), - .sched_addr_gen_starting_addr(output_sched_gen_0_sched_addr_gen_starting_addr), - .sched_addr_gen_strides_0(output_sched_gen_0_sched_addr_gen_strides_0), - .sched_addr_gen_strides_1(output_sched_gen_0_sched_addr_gen_strides_1), - .sched_addr_gen_strides_2(output_sched_gen_0_sched_addr_gen_strides_2), - .sched_addr_gen_strides_3(output_sched_gen_0_sched_addr_gen_strides_3), - .sched_addr_gen_strides_4(output_sched_gen_0_sched_addr_gen_strides_4), - .sched_addr_gen_strides_5(output_sched_gen_0_sched_addr_gen_strides_5), - .valid_output(output_sched_gen_0_valid_output), - .valid_output_d(output_sched_gen_0_valid_output_d) -); - -for_loop_6_11 loops_buf2out_autovec_read_1 ( - .clk(clk), - .clk_en(clk_en), - .dimensionality(loops_buf2out_autovec_read_1_dimensionality), - .flush(flush), - .ranges(loops_buf2out_autovec_read_1_ranges), - .rst_n(rst_n), - .step(t_read[1]), - .mux_sel_out(loops_buf2out_autovec_read_1_mux_sel_out), - .restart(loops_buf2out_autovec_read_1_restart) -); - -sched_gen_6_16_delay_addr_10_4 output_sched_gen_1 ( - .clk(clk), - .clk_en(clk_en), - .cycle_count(cycle_count), - .enable(output_sched_gen_1_enable), - .finished(loops_buf2out_autovec_read_1_restart), - .flush(flush), - .mux_sel(loops_buf2out_autovec_read_1_mux_sel_out), - .rst_n(rst_n), - .sched_addr_gen_delay(output_sched_gen_1_sched_addr_gen_delay), - .sched_addr_gen_starting_addr(output_sched_gen_1_sched_addr_gen_starting_addr), - .sched_addr_gen_strides_0(output_sched_gen_1_sched_addr_gen_strides_0), - .sched_addr_gen_strides_1(output_sched_gen_1_sched_addr_gen_strides_1), - .sched_addr_gen_strides_2(output_sched_gen_1_sched_addr_gen_strides_2), - .sched_addr_gen_strides_3(output_sched_gen_1_sched_addr_gen_strides_3), - .sched_addr_gen_strides_4(output_sched_gen_1_sched_addr_gen_strides_4), - .sched_addr_gen_strides_5(output_sched_gen_1_sched_addr_gen_strides_5), - .valid_output(output_sched_gen_1_valid_output), - .valid_output_d(output_sched_gen_1_valid_output_d) -); - -endmodule // strg_ub_sram_tb_shared - -module strg_ub_tb_only ( - input logic clk, - input logic clk_en, - input logic [15:0] cycle_count, - input logic flush, - input logic [3:0] loops_buf2out_read_0_dimensionality, - input logic [10:0] loops_buf2out_read_0_ranges_0, - input logic [10:0] loops_buf2out_read_0_ranges_1, - input logic [10:0] loops_buf2out_read_0_ranges_2, - input logic [10:0] loops_buf2out_read_0_ranges_3, - input logic [10:0] loops_buf2out_read_0_ranges_4, - input logic [10:0] loops_buf2out_read_0_ranges_5, - input logic [3:0] loops_buf2out_read_1_dimensionality, - input logic [10:0] loops_buf2out_read_1_ranges_0, - input logic [10:0] loops_buf2out_read_1_ranges_1, - input logic [10:0] loops_buf2out_read_1_ranges_2, - input logic [10:0] loops_buf2out_read_1_ranges_3, - input logic [10:0] loops_buf2out_read_1_ranges_4, - input logic [10:0] loops_buf2out_read_1_ranges_5, - input logic [1:0] [2:0] loops_sram2tb_mux_sel, - input logic [1:0] loops_sram2tb_restart, - input logic rst_n, - input logic shared_tb_0, - input logic [3:0] [15:0] sram_read_data, - input logic [1:0] t_read, - input logic [3:0] tb_read_addr_gen_0_starting_addr, - input logic [3:0] tb_read_addr_gen_0_strides_0, - input logic [3:0] tb_read_addr_gen_0_strides_1, - input logic [3:0] tb_read_addr_gen_0_strides_2, - input logic [3:0] tb_read_addr_gen_0_strides_3, - input logic [3:0] tb_read_addr_gen_0_strides_4, - input logic [3:0] tb_read_addr_gen_0_strides_5, - input logic [3:0] tb_read_addr_gen_1_starting_addr, - input logic [3:0] tb_read_addr_gen_1_strides_0, - input logic [3:0] tb_read_addr_gen_1_strides_1, - input logic [3:0] tb_read_addr_gen_1_strides_2, - input logic [3:0] tb_read_addr_gen_1_strides_3, - input logic [3:0] tb_read_addr_gen_1_strides_4, - input logic [3:0] tb_read_addr_gen_1_strides_5, - input logic tb_read_sched_gen_0_enable, - input logic [9:0] tb_read_sched_gen_0_sched_addr_gen_delay, - input logic [15:0] tb_read_sched_gen_0_sched_addr_gen_starting_addr, - input logic [15:0] tb_read_sched_gen_0_sched_addr_gen_strides_0, - input logic [15:0] tb_read_sched_gen_0_sched_addr_gen_strides_1, - input logic [15:0] tb_read_sched_gen_0_sched_addr_gen_strides_2, - input logic [15:0] tb_read_sched_gen_0_sched_addr_gen_strides_3, - input logic [15:0] tb_read_sched_gen_0_sched_addr_gen_strides_4, - input logic [15:0] tb_read_sched_gen_0_sched_addr_gen_strides_5, - input logic tb_read_sched_gen_1_enable, - input logic [9:0] tb_read_sched_gen_1_sched_addr_gen_delay, - input logic [15:0] tb_read_sched_gen_1_sched_addr_gen_starting_addr, - input logic [15:0] tb_read_sched_gen_1_sched_addr_gen_strides_0, - input logic [15:0] tb_read_sched_gen_1_sched_addr_gen_strides_1, - input logic [15:0] tb_read_sched_gen_1_sched_addr_gen_strides_2, - input logic [15:0] tb_read_sched_gen_1_sched_addr_gen_strides_3, - input logic [15:0] tb_read_sched_gen_1_sched_addr_gen_strides_4, - input logic [15:0] tb_read_sched_gen_1_sched_addr_gen_strides_5, - input logic [3:0] tb_write_addr_gen_0_starting_addr, - input logic [3:0] tb_write_addr_gen_0_strides_0, - input logic [3:0] tb_write_addr_gen_0_strides_1, - input logic [3:0] tb_write_addr_gen_0_strides_2, - input logic [3:0] tb_write_addr_gen_0_strides_3, - input logic [3:0] tb_write_addr_gen_0_strides_4, - input logic [3:0] tb_write_addr_gen_0_strides_5, - input logic [3:0] tb_write_addr_gen_1_starting_addr, - input logic [3:0] tb_write_addr_gen_1_strides_0, - input logic [3:0] tb_write_addr_gen_1_strides_1, - input logic [3:0] tb_write_addr_gen_1_strides_2, - input logic [3:0] tb_write_addr_gen_1_strides_3, - input logic [3:0] tb_write_addr_gen_1_strides_4, - input logic [3:0] tb_write_addr_gen_1_strides_5, - output logic [1:0] accessor_output, - output logic [1:0] [15:0] data_out, - output logic [1:0] [2:0] tb_read_addr_d_out, - output logic [1:0] tb_read_d_out -); - -logic [2:0] addr_fifo_in_0; -logic [2:0] addr_fifo_in_1; -logic delay_en_0; -logic delay_en_1; -logic [2:0] loops_buf2out_read_0_mux_sel_out; -logic [5:0][10:0] loops_buf2out_read_0_ranges; -logic loops_buf2out_read_0_restart; -logic [2:0] loops_buf2out_read_1_mux_sel_out; -logic [5:0][10:0] loops_buf2out_read_1_ranges; -logic loops_buf2out_read_1_restart; -logic [1:0][2:0] mux_sel_d1; -logic [2:0] rd_ptr_0; -logic [2:0] rd_ptr_1; -logic [1:0] restart_d1; -logic [1:0] t_read_d1; -logic [1:0][1:0][3:0][15:0] tb; -logic [7:0][2:0] tb_addr_fifo_0; -logic [7:0][2:0] tb_addr_fifo_1; -logic [1:0] tb_read; -logic [1:0][3:0] tb_read_addr; -logic [3:0] tb_read_addr_gen_0_addr_out; -logic [5:0][3:0] tb_read_addr_gen_0_strides; -logic [3:0] tb_read_addr_gen_1_addr_out; -logic [5:0][3:0] tb_read_addr_gen_1_strides; -logic tb_read_d_0; -logic tb_read_d_1; -logic tb_read_sched_gen_0_valid_output; -logic tb_read_sched_gen_1_valid_output; -logic tb_read_sel_0; -logic [1:0][2:0] tb_write_addr; -logic [3:0] tb_write_addr_gen_0_addr_out; -logic [5:0][3:0] tb_write_addr_gen_0_strides; -logic [3:0] tb_write_addr_gen_1_addr_out; -logic [5:0][3:0] tb_write_addr_gen_1_strides; -logic tb_write_sel_0; -logic [2:0] wr_ptr_0; -logic [2:0] wr_ptr_1; -assign accessor_output = tb_read; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - t_read_d1[0] <= 1'h0; - mux_sel_d1[0] <= 3'h0; - restart_d1[0] <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - t_read_d1[0] <= 1'h0; - mux_sel_d1[0] <= 3'h0; - restart_d1[0] <= 1'h0; - end - else begin - t_read_d1[0] <= t_read[0]; - mux_sel_d1[0] <= loops_sram2tb_mux_sel[0]; - restart_d1[0] <= loops_sram2tb_restart[0]; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - t_read_d1[1] <= 1'h0; - mux_sel_d1[1] <= 3'h0; - restart_d1[1] <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - t_read_d1[1] <= 1'h0; - mux_sel_d1[1] <= 3'h0; - restart_d1[1] <= 1'h0; - end - else begin - t_read_d1[1] <= t_read[1]; - mux_sel_d1[1] <= loops_sram2tb_mux_sel[1]; - restart_d1[1] <= loops_sram2tb_restart[1]; - end - end -end -assign tb_write_sel_0 = shared_tb_0 ? tb_write_addr[0][1]: 1'h0; -assign tb_read_sel_0 = shared_tb_0 ? tb_read_addr[0][3]: 1'h0; -assign tb_write_addr[0] = tb_write_addr_gen_0_addr_out[2:0]; -assign tb_read_addr[0] = tb_read_addr_gen_0_addr_out; -assign tb_read[0] = tb_read_sched_gen_0_valid_output; -assign addr_fifo_in_0 = tb_read_addr_gen_0_addr_out[2:0]; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - wr_ptr_0 <= 3'h0; - rd_ptr_0 <= 3'h0; - tb_addr_fifo_0 <= 24'h0; - end - else if (clk_en) begin - if (flush) begin - wr_ptr_0 <= 3'h0; - rd_ptr_0 <= 3'h0; - tb_addr_fifo_0 <= 24'h0; - end - else if (delay_en_0) begin - if (tb_read[0]) begin - tb_addr_fifo_0[wr_ptr_0] <= addr_fifo_in_0; - wr_ptr_0 <= wr_ptr_0 + 3'h1; - end - if (tb_read_d_0) begin - rd_ptr_0 <= rd_ptr_0 + 3'h1; - end - end - end -end -assign tb_read_d_out[0] = delay_en_0 ? tb_read_d_0: tb_read[0]; -assign tb_read_addr_d_out[0] = delay_en_0 ? tb_addr_fifo_0[rd_ptr_0]: addr_fifo_in_0; -always_comb begin - data_out[0] = tb[tb_read_sel_0][tb_read_addr[0][2]][tb_read_addr[0][1:0]]; -end -assign tb_write_addr[1] = tb_write_addr_gen_1_addr_out[2:0]; -assign tb_read_addr[1] = tb_read_addr_gen_1_addr_out; -assign tb_read[1] = tb_read_sched_gen_1_valid_output; -assign addr_fifo_in_1 = tb_read_addr_gen_1_addr_out[2:0]; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - wr_ptr_1 <= 3'h0; - rd_ptr_1 <= 3'h0; - tb_addr_fifo_1 <= 24'h0; - end - else if (clk_en) begin - if (flush) begin - wr_ptr_1 <= 3'h0; - rd_ptr_1 <= 3'h0; - tb_addr_fifo_1 <= 24'h0; - end - else if (delay_en_1) begin - if (tb_read[1]) begin - tb_addr_fifo_1[wr_ptr_1] <= addr_fifo_in_1; - wr_ptr_1 <= wr_ptr_1 + 3'h1; - end - if (tb_read_d_1) begin - rd_ptr_1 <= rd_ptr_1 + 3'h1; - end - end - end -end -assign tb_read_d_out[1] = delay_en_1 ? tb_read_d_1: tb_read[1]; -assign tb_read_addr_d_out[1] = delay_en_1 ? tb_addr_fifo_1[rd_ptr_1]: addr_fifo_in_1; -always_comb begin - data_out[1] = tb[1][tb_read_addr[1][2]][tb_read_addr[1][1:0]]; -end - -always_ff @(posedge clk) begin - if (clk_en) begin - for (int unsigned i = 0; i < 2; i += 1) begin - if (t_read_d1[1'(i)]) begin - if (i == 32'h0) begin - tb[tb_write_sel_0][tb_write_addr[1'(i)][0]] <= sram_read_data; - end - else tb[1'(i)][tb_write_addr[1'(i)][0]] <= sram_read_data; - end - end - end -end -assign tb_write_addr_gen_0_strides[0] = tb_write_addr_gen_0_strides_0; -assign tb_write_addr_gen_0_strides[1] = tb_write_addr_gen_0_strides_1; -assign tb_write_addr_gen_0_strides[2] = tb_write_addr_gen_0_strides_2; -assign tb_write_addr_gen_0_strides[3] = tb_write_addr_gen_0_strides_3; -assign tb_write_addr_gen_0_strides[4] = tb_write_addr_gen_0_strides_4; -assign tb_write_addr_gen_0_strides[5] = tb_write_addr_gen_0_strides_5; -assign loops_buf2out_read_0_ranges[0] = loops_buf2out_read_0_ranges_0; -assign loops_buf2out_read_0_ranges[1] = loops_buf2out_read_0_ranges_1; -assign loops_buf2out_read_0_ranges[2] = loops_buf2out_read_0_ranges_2; -assign loops_buf2out_read_0_ranges[3] = loops_buf2out_read_0_ranges_3; -assign loops_buf2out_read_0_ranges[4] = loops_buf2out_read_0_ranges_4; -assign loops_buf2out_read_0_ranges[5] = loops_buf2out_read_0_ranges_5; -assign tb_read_addr_gen_0_strides[0] = tb_read_addr_gen_0_strides_0; -assign tb_read_addr_gen_0_strides[1] = tb_read_addr_gen_0_strides_1; -assign tb_read_addr_gen_0_strides[2] = tb_read_addr_gen_0_strides_2; -assign tb_read_addr_gen_0_strides[3] = tb_read_addr_gen_0_strides_3; -assign tb_read_addr_gen_0_strides[4] = tb_read_addr_gen_0_strides_4; -assign tb_read_addr_gen_0_strides[5] = tb_read_addr_gen_0_strides_5; -assign tb_write_addr_gen_1_strides[0] = tb_write_addr_gen_1_strides_0; -assign tb_write_addr_gen_1_strides[1] = tb_write_addr_gen_1_strides_1; -assign tb_write_addr_gen_1_strides[2] = tb_write_addr_gen_1_strides_2; -assign tb_write_addr_gen_1_strides[3] = tb_write_addr_gen_1_strides_3; -assign tb_write_addr_gen_1_strides[4] = tb_write_addr_gen_1_strides_4; -assign tb_write_addr_gen_1_strides[5] = tb_write_addr_gen_1_strides_5; -assign loops_buf2out_read_1_ranges[0] = loops_buf2out_read_1_ranges_0; -assign loops_buf2out_read_1_ranges[1] = loops_buf2out_read_1_ranges_1; -assign loops_buf2out_read_1_ranges[2] = loops_buf2out_read_1_ranges_2; -assign loops_buf2out_read_1_ranges[3] = loops_buf2out_read_1_ranges_3; -assign loops_buf2out_read_1_ranges[4] = loops_buf2out_read_1_ranges_4; -assign loops_buf2out_read_1_ranges[5] = loops_buf2out_read_1_ranges_5; -assign tb_read_addr_gen_1_strides[0] = tb_read_addr_gen_1_strides_0; -assign tb_read_addr_gen_1_strides[1] = tb_read_addr_gen_1_strides_1; -assign tb_read_addr_gen_1_strides[2] = tb_read_addr_gen_1_strides_2; -assign tb_read_addr_gen_1_strides[3] = tb_read_addr_gen_1_strides_3; -assign tb_read_addr_gen_1_strides[4] = tb_read_addr_gen_1_strides_4; -assign tb_read_addr_gen_1_strides[5] = tb_read_addr_gen_1_strides_5; -addr_gen_6_4 tb_write_addr_gen_0 ( - .clk(clk), - .clk_en(clk_en), - .flush(flush), - .mux_sel(mux_sel_d1[0]), - .restart(restart_d1[0]), - .rst_n(rst_n), - .starting_addr(tb_write_addr_gen_0_starting_addr), - .step(t_read_d1[0]), - .strides(tb_write_addr_gen_0_strides), - .addr_out(tb_write_addr_gen_0_addr_out) -); - -for_loop_6_11 loops_buf2out_read_0 ( - .clk(clk), - .clk_en(clk_en), - .dimensionality(loops_buf2out_read_0_dimensionality), - .flush(flush), - .ranges(loops_buf2out_read_0_ranges), - .rst_n(rst_n), - .step(tb_read[0]), - .mux_sel_out(loops_buf2out_read_0_mux_sel_out), - .restart(loops_buf2out_read_0_restart) -); - -addr_gen_6_4 tb_read_addr_gen_0 ( - .clk(clk), - .clk_en(clk_en), - .flush(flush), - .mux_sel(loops_buf2out_read_0_mux_sel_out), - .restart(loops_buf2out_read_0_restart), - .rst_n(rst_n), - .starting_addr(tb_read_addr_gen_0_starting_addr), - .step(tb_read[0]), - .strides(tb_read_addr_gen_0_strides), - .addr_out(tb_read_addr_gen_0_addr_out) -); - -sched_gen_6_16_delay_addr_10_8 tb_read_sched_gen_0 ( - .clk(clk), - .clk_en(clk_en), - .cycle_count(cycle_count), - .enable(tb_read_sched_gen_0_enable), - .finished(loops_buf2out_read_0_restart), - .flush(flush), - .mux_sel(loops_buf2out_read_0_mux_sel_out), - .rst_n(rst_n), - .sched_addr_gen_delay(tb_read_sched_gen_0_sched_addr_gen_delay), - .sched_addr_gen_starting_addr(tb_read_sched_gen_0_sched_addr_gen_starting_addr), - .sched_addr_gen_strides_0(tb_read_sched_gen_0_sched_addr_gen_strides_0), - .sched_addr_gen_strides_1(tb_read_sched_gen_0_sched_addr_gen_strides_1), - .sched_addr_gen_strides_2(tb_read_sched_gen_0_sched_addr_gen_strides_2), - .sched_addr_gen_strides_3(tb_read_sched_gen_0_sched_addr_gen_strides_3), - .sched_addr_gen_strides_4(tb_read_sched_gen_0_sched_addr_gen_strides_4), - .sched_addr_gen_strides_5(tb_read_sched_gen_0_sched_addr_gen_strides_5), - .delay_en_out(delay_en_0), - .valid_output(tb_read_sched_gen_0_valid_output), - .valid_output_d(tb_read_d_0) -); - -addr_gen_6_4 tb_write_addr_gen_1 ( - .clk(clk), - .clk_en(clk_en), - .flush(flush), - .mux_sel(mux_sel_d1[1]), - .restart(restart_d1[1]), - .rst_n(rst_n), - .starting_addr(tb_write_addr_gen_1_starting_addr), - .step(t_read_d1[1]), - .strides(tb_write_addr_gen_1_strides), - .addr_out(tb_write_addr_gen_1_addr_out) -); - -for_loop_6_11 loops_buf2out_read_1 ( - .clk(clk), - .clk_en(clk_en), - .dimensionality(loops_buf2out_read_1_dimensionality), - .flush(flush), - .ranges(loops_buf2out_read_1_ranges), - .rst_n(rst_n), - .step(tb_read[1]), - .mux_sel_out(loops_buf2out_read_1_mux_sel_out), - .restart(loops_buf2out_read_1_restart) -); - -addr_gen_6_4 tb_read_addr_gen_1 ( - .clk(clk), - .clk_en(clk_en), - .flush(flush), - .mux_sel(loops_buf2out_read_1_mux_sel_out), - .restart(loops_buf2out_read_1_restart), - .rst_n(rst_n), - .starting_addr(tb_read_addr_gen_1_starting_addr), - .step(tb_read[1]), - .strides(tb_read_addr_gen_1_strides), - .addr_out(tb_read_addr_gen_1_addr_out) -); - -sched_gen_6_16_delay_addr_10_8 tb_read_sched_gen_1 ( - .clk(clk), - .clk_en(clk_en), - .cycle_count(cycle_count), - .enable(tb_read_sched_gen_1_enable), - .finished(loops_buf2out_read_1_restart), - .flush(flush), - .mux_sel(loops_buf2out_read_1_mux_sel_out), - .rst_n(rst_n), - .sched_addr_gen_delay(tb_read_sched_gen_1_sched_addr_gen_delay), - .sched_addr_gen_starting_addr(tb_read_sched_gen_1_sched_addr_gen_starting_addr), - .sched_addr_gen_strides_0(tb_read_sched_gen_1_sched_addr_gen_strides_0), - .sched_addr_gen_strides_1(tb_read_sched_gen_1_sched_addr_gen_strides_1), - .sched_addr_gen_strides_2(tb_read_sched_gen_1_sched_addr_gen_strides_2), - .sched_addr_gen_strides_3(tb_read_sched_gen_1_sched_addr_gen_strides_3), - .sched_addr_gen_strides_4(tb_read_sched_gen_1_sched_addr_gen_strides_4), - .sched_addr_gen_strides_5(tb_read_sched_gen_1_sched_addr_gen_strides_5), - .delay_en_out(delay_en_1), - .valid_output(tb_read_sched_gen_1_valid_output), - .valid_output_d(tb_read_d_1) -); - -endmodule // strg_ub_tb_only - -module strg_ub_vec ( - input logic [2:0] agg_only_agg_write_addr_gen_0_starting_addr, - input logic [2:0] agg_only_agg_write_addr_gen_0_strides_0, - input logic [2:0] agg_only_agg_write_addr_gen_0_strides_1, - input logic [2:0] agg_only_agg_write_addr_gen_0_strides_2, - input logic [2:0] agg_only_agg_write_addr_gen_1_starting_addr, - input logic [2:0] agg_only_agg_write_addr_gen_1_strides_0, - input logic [2:0] agg_only_agg_write_addr_gen_1_strides_1, - input logic [2:0] agg_only_agg_write_addr_gen_1_strides_2, - input logic agg_only_agg_write_sched_gen_0_enable, - input logic [15:0] agg_only_agg_write_sched_gen_0_sched_addr_gen_starting_addr, - input logic [15:0] agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_0, - input logic [15:0] agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_1, - input logic [15:0] agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_2, - input logic agg_only_agg_write_sched_gen_1_enable, - input logic [15:0] agg_only_agg_write_sched_gen_1_sched_addr_gen_starting_addr, - input logic [15:0] agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_0, - input logic [15:0] agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_1, - input logic [15:0] agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_2, - input logic [2:0] agg_only_loops_in2buf_0_dimensionality, - input logic [10:0] agg_only_loops_in2buf_0_ranges_0, - input logic [10:0] agg_only_loops_in2buf_0_ranges_1, - input logic [10:0] agg_only_loops_in2buf_0_ranges_2, - input logic [2:0] agg_only_loops_in2buf_1_dimensionality, - input logic [10:0] agg_only_loops_in2buf_1_ranges_0, - input logic [10:0] agg_only_loops_in2buf_1_ranges_1, - input logic [10:0] agg_only_loops_in2buf_1_ranges_2, - input logic [7:0] agg_sram_shared_agg_read_sched_gen_0_agg_read_padding, - input logic [7:0] agg_sram_shared_agg_read_sched_gen_1_agg_read_padding, - input logic [8:0] agg_sram_shared_agg_sram_shared_addr_gen_0_starting_addr, - input logic [8:0] agg_sram_shared_agg_sram_shared_addr_gen_1_starting_addr, - input logic [1:0] agg_sram_shared_mode_0, - input logic [1:0] agg_sram_shared_mode_1, - input logic chain_chain_en, - input logic [1:0] [16:0] chain_data_in, - input logic clk, - input logic clk_en, - input logic [3:0] [15:0] data_from_strg, - input logic [1:0] [16:0] data_in, - input logic flush, - input logic rst_n, - input logic [8:0] sram_only_output_addr_gen_0_starting_addr, - input logic [8:0] sram_only_output_addr_gen_0_strides_0, - input logic [8:0] sram_only_output_addr_gen_0_strides_1, - input logic [8:0] sram_only_output_addr_gen_0_strides_2, - input logic [8:0] sram_only_output_addr_gen_0_strides_3, - input logic [8:0] sram_only_output_addr_gen_0_strides_4, - input logic [8:0] sram_only_output_addr_gen_0_strides_5, - input logic [8:0] sram_only_output_addr_gen_1_starting_addr, - input logic [8:0] sram_only_output_addr_gen_1_strides_0, - input logic [8:0] sram_only_output_addr_gen_1_strides_1, - input logic [8:0] sram_only_output_addr_gen_1_strides_2, - input logic [8:0] sram_only_output_addr_gen_1_strides_3, - input logic [8:0] sram_only_output_addr_gen_1_strides_4, - input logic [8:0] sram_only_output_addr_gen_1_strides_5, - input logic [3:0] sram_tb_shared_loops_buf2out_autovec_read_0_dimensionality, - input logic [10:0] sram_tb_shared_loops_buf2out_autovec_read_0_ranges_0, - input logic [10:0] sram_tb_shared_loops_buf2out_autovec_read_0_ranges_1, - input logic [10:0] sram_tb_shared_loops_buf2out_autovec_read_0_ranges_2, - input logic [10:0] sram_tb_shared_loops_buf2out_autovec_read_0_ranges_3, - input logic [10:0] sram_tb_shared_loops_buf2out_autovec_read_0_ranges_4, - input logic [10:0] sram_tb_shared_loops_buf2out_autovec_read_0_ranges_5, - input logic [3:0] sram_tb_shared_loops_buf2out_autovec_read_1_dimensionality, - input logic [10:0] sram_tb_shared_loops_buf2out_autovec_read_1_ranges_0, - input logic [10:0] sram_tb_shared_loops_buf2out_autovec_read_1_ranges_1, - input logic [10:0] sram_tb_shared_loops_buf2out_autovec_read_1_ranges_2, - input logic [10:0] sram_tb_shared_loops_buf2out_autovec_read_1_ranges_3, - input logic [10:0] sram_tb_shared_loops_buf2out_autovec_read_1_ranges_4, - input logic [10:0] sram_tb_shared_loops_buf2out_autovec_read_1_ranges_5, - input logic sram_tb_shared_output_sched_gen_0_enable, - input logic [9:0] sram_tb_shared_output_sched_gen_0_sched_addr_gen_delay, - input logic [15:0] sram_tb_shared_output_sched_gen_0_sched_addr_gen_starting_addr, - input logic [15:0] sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_0, - input logic [15:0] sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_1, - input logic [15:0] sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_2, - input logic [15:0] sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_3, - input logic [15:0] sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_4, - input logic [15:0] sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_5, - input logic sram_tb_shared_output_sched_gen_1_enable, - input logic [9:0] sram_tb_shared_output_sched_gen_1_sched_addr_gen_delay, - input logic [15:0] sram_tb_shared_output_sched_gen_1_sched_addr_gen_starting_addr, - input logic [15:0] sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_0, - input logic [15:0] sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_1, - input logic [15:0] sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_2, - input logic [15:0] sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_3, - input logic [15:0] sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_4, - input logic [15:0] sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_5, - input logic [3:0] tb_only_loops_buf2out_read_0_dimensionality, - input logic [10:0] tb_only_loops_buf2out_read_0_ranges_0, - input logic [10:0] tb_only_loops_buf2out_read_0_ranges_1, - input logic [10:0] tb_only_loops_buf2out_read_0_ranges_2, - input logic [10:0] tb_only_loops_buf2out_read_0_ranges_3, - input logic [10:0] tb_only_loops_buf2out_read_0_ranges_4, - input logic [10:0] tb_only_loops_buf2out_read_0_ranges_5, - input logic [3:0] tb_only_loops_buf2out_read_1_dimensionality, - input logic [10:0] tb_only_loops_buf2out_read_1_ranges_0, - input logic [10:0] tb_only_loops_buf2out_read_1_ranges_1, - input logic [10:0] tb_only_loops_buf2out_read_1_ranges_2, - input logic [10:0] tb_only_loops_buf2out_read_1_ranges_3, - input logic [10:0] tb_only_loops_buf2out_read_1_ranges_4, - input logic [10:0] tb_only_loops_buf2out_read_1_ranges_5, - input logic tb_only_shared_tb_0, - input logic [3:0] tb_only_tb_read_addr_gen_0_starting_addr, - input logic [3:0] tb_only_tb_read_addr_gen_0_strides_0, - input logic [3:0] tb_only_tb_read_addr_gen_0_strides_1, - input logic [3:0] tb_only_tb_read_addr_gen_0_strides_2, - input logic [3:0] tb_only_tb_read_addr_gen_0_strides_3, - input logic [3:0] tb_only_tb_read_addr_gen_0_strides_4, - input logic [3:0] tb_only_tb_read_addr_gen_0_strides_5, - input logic [3:0] tb_only_tb_read_addr_gen_1_starting_addr, - input logic [3:0] tb_only_tb_read_addr_gen_1_strides_0, - input logic [3:0] tb_only_tb_read_addr_gen_1_strides_1, - input logic [3:0] tb_only_tb_read_addr_gen_1_strides_2, - input logic [3:0] tb_only_tb_read_addr_gen_1_strides_3, - input logic [3:0] tb_only_tb_read_addr_gen_1_strides_4, - input logic [3:0] tb_only_tb_read_addr_gen_1_strides_5, - input logic tb_only_tb_read_sched_gen_0_enable, - input logic [9:0] tb_only_tb_read_sched_gen_0_sched_addr_gen_delay, - input logic [15:0] tb_only_tb_read_sched_gen_0_sched_addr_gen_starting_addr, - input logic [15:0] tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_0, - input logic [15:0] tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_1, - input logic [15:0] tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_2, - input logic [15:0] tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_3, - input logic [15:0] tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_4, - input logic [15:0] tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_5, - input logic tb_only_tb_read_sched_gen_1_enable, - input logic [9:0] tb_only_tb_read_sched_gen_1_sched_addr_gen_delay, - input logic [15:0] tb_only_tb_read_sched_gen_1_sched_addr_gen_starting_addr, - input logic [15:0] tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_0, - input logic [15:0] tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_1, - input logic [15:0] tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_2, - input logic [15:0] tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_3, - input logic [15:0] tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_4, - input logic [15:0] tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_5, - input logic [3:0] tb_only_tb_write_addr_gen_0_starting_addr, - input logic [3:0] tb_only_tb_write_addr_gen_0_strides_0, - input logic [3:0] tb_only_tb_write_addr_gen_0_strides_1, - input logic [3:0] tb_only_tb_write_addr_gen_0_strides_2, - input logic [3:0] tb_only_tb_write_addr_gen_0_strides_3, - input logic [3:0] tb_only_tb_write_addr_gen_0_strides_4, - input logic [3:0] tb_only_tb_write_addr_gen_0_strides_5, - input logic [3:0] tb_only_tb_write_addr_gen_1_starting_addr, - input logic [3:0] tb_only_tb_write_addr_gen_1_strides_0, - input logic [3:0] tb_only_tb_write_addr_gen_1_strides_1, - input logic [3:0] tb_only_tb_write_addr_gen_1_strides_2, - input logic [3:0] tb_only_tb_write_addr_gen_1_strides_3, - input logic [3:0] tb_only_tb_write_addr_gen_1_strides_4, - input logic [3:0] tb_only_tb_write_addr_gen_1_strides_5, - output logic [1:0] accessor_output, - output logic [8:0] addr_out, - output logic [1:0] [16:0] data_out, - output logic [3:0] [15:0] data_to_strg, - output logic ren_to_strg, - output logic wen_to_strg -); - -logic [1:0] accessor_output_int; -logic [1:0][3:0][15:0] agg_only_agg_data_out; -logic [1:0] agg_only_agg_read; -logic [1:0][1:0] agg_only_agg_write_addr_l2b_out; -logic [1:0][2:0] agg_only_agg_write_mux_sel_out; -logic [1:0] agg_only_agg_write_out; -logic [1:0] agg_only_agg_write_restart_out; -logic [1:0][8:0] agg_only_sram_read_addr_in; -logic [1:0][2:0] agg_only_tb_read_addr_d_in; -logic [1:0] agg_only_tb_read_d_in; -logic [1:0][1:0] agg_only_update_mode_in; -logic [1:0] agg_sram_shared_agg_read_out; -logic [1:0][8:0] agg_sram_shared_agg_sram_shared_addr_out; -logic [1:0][8:0] agg_sram_shared_sram_read_addr_in; -logic [1:0] agg_sram_shared_sram_read_d_in; -logic [1:0] agg_sram_shared_sram_read_in; -logic [1:0][15:0] chain_data_in_thin; -logic [15:0] cycle_count; -logic [1:0][15:0] data_in_thin; -logic [1:0][15:0] data_out_int; -logic [1:0][15:0] data_out_int_thin; -logic [1:0][2:0] sram_only_loops_sram2tb_mux_sel; -logic [1:0] sram_only_loops_sram2tb_restart; -logic [1:0] sram_only_t_read; -logic [1:0][2:0] sram_tb_shared_loops_sram2tb_mux_sel; -logic [1:0] sram_tb_shared_loops_sram2tb_restart; -logic [1:0] sram_tb_shared_t_read_out; -assign data_in_thin[0] = data_in[0][15:0]; -assign data_in_thin[1] = data_in[1][15:0]; -assign data_out[0][15:0] = data_out_int_thin[0]; -assign data_out[0][16] = 1'h0; -assign data_out[1][15:0] = data_out_int_thin[1]; -assign data_out[1][16] = 1'h0; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - cycle_count <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - cycle_count <= 16'h0; - end - else if (1'h1) begin - cycle_count <= cycle_count + 16'h1; - end - end -end -assign agg_only_sram_read_addr_in = agg_sram_shared_agg_sram_shared_addr_out; -assign agg_sram_shared_sram_read_in = sram_tb_shared_t_read_out; -assign agg_only_agg_read = agg_sram_shared_agg_read_out; -assign sram_only_loops_sram2tb_mux_sel = sram_tb_shared_loops_sram2tb_mux_sel; -assign sram_only_loops_sram2tb_restart = sram_tb_shared_loops_sram2tb_restart; -assign sram_only_t_read = sram_tb_shared_t_read_out; -assign ren_to_strg = |sram_tb_shared_t_read_out; -assign chain_data_in_thin[0] = chain_data_in[0][15:0]; -assign chain_data_in_thin[1] = chain_data_in[1][15:0]; -assign accessor_output = accessor_output_int; -strg_ub_agg_only agg_only ( - .agg_read(agg_only_agg_read), - .agg_write_addr_gen_0_starting_addr(agg_only_agg_write_addr_gen_0_starting_addr), - .agg_write_addr_gen_0_strides_0(agg_only_agg_write_addr_gen_0_strides_0), - .agg_write_addr_gen_0_strides_1(agg_only_agg_write_addr_gen_0_strides_1), - .agg_write_addr_gen_0_strides_2(agg_only_agg_write_addr_gen_0_strides_2), - .agg_write_addr_gen_1_starting_addr(agg_only_agg_write_addr_gen_1_starting_addr), - .agg_write_addr_gen_1_strides_0(agg_only_agg_write_addr_gen_1_strides_0), - .agg_write_addr_gen_1_strides_1(agg_only_agg_write_addr_gen_1_strides_1), - .agg_write_addr_gen_1_strides_2(agg_only_agg_write_addr_gen_1_strides_2), - .agg_write_sched_gen_0_enable(agg_only_agg_write_sched_gen_0_enable), - .agg_write_sched_gen_0_sched_addr_gen_starting_addr(agg_only_agg_write_sched_gen_0_sched_addr_gen_starting_addr), - .agg_write_sched_gen_0_sched_addr_gen_strides_0(agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_0), - .agg_write_sched_gen_0_sched_addr_gen_strides_1(agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_1), - .agg_write_sched_gen_0_sched_addr_gen_strides_2(agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_2), - .agg_write_sched_gen_1_enable(agg_only_agg_write_sched_gen_1_enable), - .agg_write_sched_gen_1_sched_addr_gen_starting_addr(agg_only_agg_write_sched_gen_1_sched_addr_gen_starting_addr), - .agg_write_sched_gen_1_sched_addr_gen_strides_0(agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_0), - .agg_write_sched_gen_1_sched_addr_gen_strides_1(agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_1), - .agg_write_sched_gen_1_sched_addr_gen_strides_2(agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_2), - .clk(clk), - .clk_en(clk_en), - .cycle_count(cycle_count), - .data_in(data_in_thin), - .flush(flush), - .loops_in2buf_0_dimensionality(agg_only_loops_in2buf_0_dimensionality), - .loops_in2buf_0_ranges_0(agg_only_loops_in2buf_0_ranges_0), - .loops_in2buf_0_ranges_1(agg_only_loops_in2buf_0_ranges_1), - .loops_in2buf_0_ranges_2(agg_only_loops_in2buf_0_ranges_2), - .loops_in2buf_1_dimensionality(agg_only_loops_in2buf_1_dimensionality), - .loops_in2buf_1_ranges_0(agg_only_loops_in2buf_1_ranges_0), - .loops_in2buf_1_ranges_1(agg_only_loops_in2buf_1_ranges_1), - .loops_in2buf_1_ranges_2(agg_only_loops_in2buf_1_ranges_2), - .rst_n(rst_n), - .sram_read_addr_in(agg_only_sram_read_addr_in), - .tb_read_addr_d_in(agg_only_tb_read_addr_d_in), - .tb_read_d_in(agg_only_tb_read_d_in), - .update_mode_in(agg_only_update_mode_in), - .agg_data_out(agg_only_agg_data_out), - .agg_write_addr_l2b_out(agg_only_agg_write_addr_l2b_out), - .agg_write_mux_sel_out(agg_only_agg_write_mux_sel_out), - .agg_write_out(agg_only_agg_write_out), - .agg_write_restart_out(agg_only_agg_write_restart_out) -); - -strg_ub_agg_sram_shared agg_sram_shared ( - .agg_read_sched_gen_0_agg_read_padding(agg_sram_shared_agg_read_sched_gen_0_agg_read_padding), - .agg_read_sched_gen_1_agg_read_padding(agg_sram_shared_agg_read_sched_gen_1_agg_read_padding), - .agg_sram_shared_addr_gen_0_starting_addr(agg_sram_shared_agg_sram_shared_addr_gen_0_starting_addr), - .agg_sram_shared_addr_gen_1_starting_addr(agg_sram_shared_agg_sram_shared_addr_gen_1_starting_addr), - .agg_write_addr_l2b_in(agg_only_agg_write_addr_l2b_out), - .agg_write_in(agg_only_agg_write_out), - .agg_write_mux_sel_in(agg_only_agg_write_mux_sel_out), - .agg_write_restart_in(agg_only_agg_write_restart_out), - .clk(clk), - .clk_en(clk_en), - .flush(flush), - .mode_0(agg_sram_shared_mode_0), - .mode_1(agg_sram_shared_mode_1), - .rst_n(rst_n), - .sram_read_addr_in(agg_sram_shared_sram_read_addr_in), - .sram_read_d_in(agg_sram_shared_sram_read_d_in), - .sram_read_in(agg_sram_shared_sram_read_in), - .agg_read_out(agg_sram_shared_agg_read_out), - .agg_sram_shared_addr_out(agg_sram_shared_agg_sram_shared_addr_out), - .update_mode_out(agg_only_update_mode_in) -); - -strg_ub_sram_only sram_only ( - .agg_data_out(agg_only_agg_data_out), - .agg_read(agg_sram_shared_agg_read_out), - .clk(clk), - .clk_en(clk_en), - .cycle_count(cycle_count), - .flush(flush), - .loops_sram2tb_mux_sel(sram_only_loops_sram2tb_mux_sel), - .loops_sram2tb_restart(sram_only_loops_sram2tb_restart), - .output_addr_gen_0_starting_addr(sram_only_output_addr_gen_0_starting_addr), - .output_addr_gen_0_strides_0(sram_only_output_addr_gen_0_strides_0), - .output_addr_gen_0_strides_1(sram_only_output_addr_gen_0_strides_1), - .output_addr_gen_0_strides_2(sram_only_output_addr_gen_0_strides_2), - .output_addr_gen_0_strides_3(sram_only_output_addr_gen_0_strides_3), - .output_addr_gen_0_strides_4(sram_only_output_addr_gen_0_strides_4), - .output_addr_gen_0_strides_5(sram_only_output_addr_gen_0_strides_5), - .output_addr_gen_1_starting_addr(sram_only_output_addr_gen_1_starting_addr), - .output_addr_gen_1_strides_0(sram_only_output_addr_gen_1_strides_0), - .output_addr_gen_1_strides_1(sram_only_output_addr_gen_1_strides_1), - .output_addr_gen_1_strides_2(sram_only_output_addr_gen_1_strides_2), - .output_addr_gen_1_strides_3(sram_only_output_addr_gen_1_strides_3), - .output_addr_gen_1_strides_4(sram_only_output_addr_gen_1_strides_4), - .output_addr_gen_1_strides_5(sram_only_output_addr_gen_1_strides_5), - .rst_n(rst_n), - .sram_read_addr_in(agg_sram_shared_agg_sram_shared_addr_out), - .t_read(sram_only_t_read), - .addr_to_sram(addr_out), - .data_to_sram(data_to_strg), - .sram_read_addr_out(agg_sram_shared_sram_read_addr_in), - .wen_to_sram(wen_to_strg) -); - -strg_ub_sram_tb_shared sram_tb_shared ( - .clk(clk), - .clk_en(clk_en), - .cycle_count(cycle_count), - .flush(flush), - .loops_buf2out_autovec_read_0_dimensionality(sram_tb_shared_loops_buf2out_autovec_read_0_dimensionality), - .loops_buf2out_autovec_read_0_ranges_0(sram_tb_shared_loops_buf2out_autovec_read_0_ranges_0), - .loops_buf2out_autovec_read_0_ranges_1(sram_tb_shared_loops_buf2out_autovec_read_0_ranges_1), - .loops_buf2out_autovec_read_0_ranges_2(sram_tb_shared_loops_buf2out_autovec_read_0_ranges_2), - .loops_buf2out_autovec_read_0_ranges_3(sram_tb_shared_loops_buf2out_autovec_read_0_ranges_3), - .loops_buf2out_autovec_read_0_ranges_4(sram_tb_shared_loops_buf2out_autovec_read_0_ranges_4), - .loops_buf2out_autovec_read_0_ranges_5(sram_tb_shared_loops_buf2out_autovec_read_0_ranges_5), - .loops_buf2out_autovec_read_1_dimensionality(sram_tb_shared_loops_buf2out_autovec_read_1_dimensionality), - .loops_buf2out_autovec_read_1_ranges_0(sram_tb_shared_loops_buf2out_autovec_read_1_ranges_0), - .loops_buf2out_autovec_read_1_ranges_1(sram_tb_shared_loops_buf2out_autovec_read_1_ranges_1), - .loops_buf2out_autovec_read_1_ranges_2(sram_tb_shared_loops_buf2out_autovec_read_1_ranges_2), - .loops_buf2out_autovec_read_1_ranges_3(sram_tb_shared_loops_buf2out_autovec_read_1_ranges_3), - .loops_buf2out_autovec_read_1_ranges_4(sram_tb_shared_loops_buf2out_autovec_read_1_ranges_4), - .loops_buf2out_autovec_read_1_ranges_5(sram_tb_shared_loops_buf2out_autovec_read_1_ranges_5), - .output_sched_gen_0_enable(sram_tb_shared_output_sched_gen_0_enable), - .output_sched_gen_0_sched_addr_gen_delay(sram_tb_shared_output_sched_gen_0_sched_addr_gen_delay), - .output_sched_gen_0_sched_addr_gen_starting_addr(sram_tb_shared_output_sched_gen_0_sched_addr_gen_starting_addr), - .output_sched_gen_0_sched_addr_gen_strides_0(sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_0), - .output_sched_gen_0_sched_addr_gen_strides_1(sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_1), - .output_sched_gen_0_sched_addr_gen_strides_2(sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_2), - .output_sched_gen_0_sched_addr_gen_strides_3(sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_3), - .output_sched_gen_0_sched_addr_gen_strides_4(sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_4), - .output_sched_gen_0_sched_addr_gen_strides_5(sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_5), - .output_sched_gen_1_enable(sram_tb_shared_output_sched_gen_1_enable), - .output_sched_gen_1_sched_addr_gen_delay(sram_tb_shared_output_sched_gen_1_sched_addr_gen_delay), - .output_sched_gen_1_sched_addr_gen_starting_addr(sram_tb_shared_output_sched_gen_1_sched_addr_gen_starting_addr), - .output_sched_gen_1_sched_addr_gen_strides_0(sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_0), - .output_sched_gen_1_sched_addr_gen_strides_1(sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_1), - .output_sched_gen_1_sched_addr_gen_strides_2(sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_2), - .output_sched_gen_1_sched_addr_gen_strides_3(sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_3), - .output_sched_gen_1_sched_addr_gen_strides_4(sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_4), - .output_sched_gen_1_sched_addr_gen_strides_5(sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_5), - .rst_n(rst_n), - .loops_sram2tb_mux_sel(sram_tb_shared_loops_sram2tb_mux_sel), - .loops_sram2tb_restart(sram_tb_shared_loops_sram2tb_restart), - .sram_read_d(agg_sram_shared_sram_read_d_in), - .t_read_out(sram_tb_shared_t_read_out) -); - -strg_ub_tb_only tb_only ( - .clk(clk), - .clk_en(clk_en), - .cycle_count(cycle_count), - .flush(flush), - .loops_buf2out_read_0_dimensionality(tb_only_loops_buf2out_read_0_dimensionality), - .loops_buf2out_read_0_ranges_0(tb_only_loops_buf2out_read_0_ranges_0), - .loops_buf2out_read_0_ranges_1(tb_only_loops_buf2out_read_0_ranges_1), - .loops_buf2out_read_0_ranges_2(tb_only_loops_buf2out_read_0_ranges_2), - .loops_buf2out_read_0_ranges_3(tb_only_loops_buf2out_read_0_ranges_3), - .loops_buf2out_read_0_ranges_4(tb_only_loops_buf2out_read_0_ranges_4), - .loops_buf2out_read_0_ranges_5(tb_only_loops_buf2out_read_0_ranges_5), - .loops_buf2out_read_1_dimensionality(tb_only_loops_buf2out_read_1_dimensionality), - .loops_buf2out_read_1_ranges_0(tb_only_loops_buf2out_read_1_ranges_0), - .loops_buf2out_read_1_ranges_1(tb_only_loops_buf2out_read_1_ranges_1), - .loops_buf2out_read_1_ranges_2(tb_only_loops_buf2out_read_1_ranges_2), - .loops_buf2out_read_1_ranges_3(tb_only_loops_buf2out_read_1_ranges_3), - .loops_buf2out_read_1_ranges_4(tb_only_loops_buf2out_read_1_ranges_4), - .loops_buf2out_read_1_ranges_5(tb_only_loops_buf2out_read_1_ranges_5), - .loops_sram2tb_mux_sel(sram_tb_shared_loops_sram2tb_mux_sel), - .loops_sram2tb_restart(sram_tb_shared_loops_sram2tb_restart), - .rst_n(rst_n), - .shared_tb_0(tb_only_shared_tb_0), - .sram_read_data(data_from_strg), - .t_read(sram_tb_shared_t_read_out), - .tb_read_addr_gen_0_starting_addr(tb_only_tb_read_addr_gen_0_starting_addr), - .tb_read_addr_gen_0_strides_0(tb_only_tb_read_addr_gen_0_strides_0), - .tb_read_addr_gen_0_strides_1(tb_only_tb_read_addr_gen_0_strides_1), - .tb_read_addr_gen_0_strides_2(tb_only_tb_read_addr_gen_0_strides_2), - .tb_read_addr_gen_0_strides_3(tb_only_tb_read_addr_gen_0_strides_3), - .tb_read_addr_gen_0_strides_4(tb_only_tb_read_addr_gen_0_strides_4), - .tb_read_addr_gen_0_strides_5(tb_only_tb_read_addr_gen_0_strides_5), - .tb_read_addr_gen_1_starting_addr(tb_only_tb_read_addr_gen_1_starting_addr), - .tb_read_addr_gen_1_strides_0(tb_only_tb_read_addr_gen_1_strides_0), - .tb_read_addr_gen_1_strides_1(tb_only_tb_read_addr_gen_1_strides_1), - .tb_read_addr_gen_1_strides_2(tb_only_tb_read_addr_gen_1_strides_2), - .tb_read_addr_gen_1_strides_3(tb_only_tb_read_addr_gen_1_strides_3), - .tb_read_addr_gen_1_strides_4(tb_only_tb_read_addr_gen_1_strides_4), - .tb_read_addr_gen_1_strides_5(tb_only_tb_read_addr_gen_1_strides_5), - .tb_read_sched_gen_0_enable(tb_only_tb_read_sched_gen_0_enable), - .tb_read_sched_gen_0_sched_addr_gen_delay(tb_only_tb_read_sched_gen_0_sched_addr_gen_delay), - .tb_read_sched_gen_0_sched_addr_gen_starting_addr(tb_only_tb_read_sched_gen_0_sched_addr_gen_starting_addr), - .tb_read_sched_gen_0_sched_addr_gen_strides_0(tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_0), - .tb_read_sched_gen_0_sched_addr_gen_strides_1(tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_1), - .tb_read_sched_gen_0_sched_addr_gen_strides_2(tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_2), - .tb_read_sched_gen_0_sched_addr_gen_strides_3(tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_3), - .tb_read_sched_gen_0_sched_addr_gen_strides_4(tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_4), - .tb_read_sched_gen_0_sched_addr_gen_strides_5(tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_5), - .tb_read_sched_gen_1_enable(tb_only_tb_read_sched_gen_1_enable), - .tb_read_sched_gen_1_sched_addr_gen_delay(tb_only_tb_read_sched_gen_1_sched_addr_gen_delay), - .tb_read_sched_gen_1_sched_addr_gen_starting_addr(tb_only_tb_read_sched_gen_1_sched_addr_gen_starting_addr), - .tb_read_sched_gen_1_sched_addr_gen_strides_0(tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_0), - .tb_read_sched_gen_1_sched_addr_gen_strides_1(tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_1), - .tb_read_sched_gen_1_sched_addr_gen_strides_2(tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_2), - .tb_read_sched_gen_1_sched_addr_gen_strides_3(tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_3), - .tb_read_sched_gen_1_sched_addr_gen_strides_4(tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_4), - .tb_read_sched_gen_1_sched_addr_gen_strides_5(tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_5), - .tb_write_addr_gen_0_starting_addr(tb_only_tb_write_addr_gen_0_starting_addr), - .tb_write_addr_gen_0_strides_0(tb_only_tb_write_addr_gen_0_strides_0), - .tb_write_addr_gen_0_strides_1(tb_only_tb_write_addr_gen_0_strides_1), - .tb_write_addr_gen_0_strides_2(tb_only_tb_write_addr_gen_0_strides_2), - .tb_write_addr_gen_0_strides_3(tb_only_tb_write_addr_gen_0_strides_3), - .tb_write_addr_gen_0_strides_4(tb_only_tb_write_addr_gen_0_strides_4), - .tb_write_addr_gen_0_strides_5(tb_only_tb_write_addr_gen_0_strides_5), - .tb_write_addr_gen_1_starting_addr(tb_only_tb_write_addr_gen_1_starting_addr), - .tb_write_addr_gen_1_strides_0(tb_only_tb_write_addr_gen_1_strides_0), - .tb_write_addr_gen_1_strides_1(tb_only_tb_write_addr_gen_1_strides_1), - .tb_write_addr_gen_1_strides_2(tb_only_tb_write_addr_gen_1_strides_2), - .tb_write_addr_gen_1_strides_3(tb_only_tb_write_addr_gen_1_strides_3), - .tb_write_addr_gen_1_strides_4(tb_only_tb_write_addr_gen_1_strides_4), - .tb_write_addr_gen_1_strides_5(tb_only_tb_write_addr_gen_1_strides_5), - .accessor_output(accessor_output_int), - .data_out(data_out_int), - .tb_read_addr_d_out(agg_only_tb_read_addr_d_in), - .tb_read_d_out(agg_only_tb_read_d_in) -); - -Chain_2_16 chain ( - .accessor_output(accessor_output_int), - .chain_data_in(chain_data_in_thin), - .chain_en(chain_chain_en), - .clk_en(clk_en), - .curr_tile_data_out(data_out_int), - .flush(flush), - .data_out_tile(data_out_int_thin) -); - -endmodule // strg_ub_vec - -module strg_ub_vec_flat ( - input logic [0:0] [16:0] chain_data_in_f_0, - input logic [0:0] [16:0] chain_data_in_f_1, - input logic clk, - input logic clk_en, - input logic [0:0] [16:0] data_in_f_0, - input logic [0:0] [16:0] data_in_f_1, - input logic flush, - input logic rst_n, - input logic [2:0] strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_starting_addr, - input logic [2:0] strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_strides_0, - input logic [2:0] strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_strides_1, - input logic [2:0] strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_strides_2, - input logic [2:0] strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_starting_addr, - input logic [2:0] strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_strides_0, - input logic [2:0] strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_strides_1, - input logic [2:0] strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_strides_2, - input logic strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_enable, - input logic [15:0] strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_starting_addr, - input logic [15:0] strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_0, - input logic [15:0] strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_1, - input logic [15:0] strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_2, - input logic strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_enable, - input logic [15:0] strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_starting_addr, - input logic [15:0] strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_0, - input logic [15:0] strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_1, - input logic [15:0] strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_2, - input logic [2:0] strg_ub_vec_inst_agg_only_loops_in2buf_0_dimensionality, - input logic [10:0] strg_ub_vec_inst_agg_only_loops_in2buf_0_ranges_0, - input logic [10:0] strg_ub_vec_inst_agg_only_loops_in2buf_0_ranges_1, - input logic [10:0] strg_ub_vec_inst_agg_only_loops_in2buf_0_ranges_2, - input logic [2:0] strg_ub_vec_inst_agg_only_loops_in2buf_1_dimensionality, - input logic [10:0] strg_ub_vec_inst_agg_only_loops_in2buf_1_ranges_0, - input logic [10:0] strg_ub_vec_inst_agg_only_loops_in2buf_1_ranges_1, - input logic [10:0] strg_ub_vec_inst_agg_only_loops_in2buf_1_ranges_2, - input logic [7:0] strg_ub_vec_inst_agg_sram_shared_agg_read_sched_gen_0_agg_read_padding, - input logic [7:0] strg_ub_vec_inst_agg_sram_shared_agg_read_sched_gen_1_agg_read_padding, - input logic [8:0] strg_ub_vec_inst_agg_sram_shared_agg_sram_shared_addr_gen_0_starting_addr, - input logic [8:0] strg_ub_vec_inst_agg_sram_shared_agg_sram_shared_addr_gen_1_starting_addr, - input logic [1:0] strg_ub_vec_inst_agg_sram_shared_mode_0, - input logic [1:0] strg_ub_vec_inst_agg_sram_shared_mode_1, - input logic strg_ub_vec_inst_chain_chain_en, - input logic [3:0] [15:0] strg_ub_vec_inst_data_from_strg_lifted, - input logic [8:0] strg_ub_vec_inst_sram_only_output_addr_gen_0_starting_addr, - input logic [8:0] strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_0, - input logic [8:0] strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_1, - input logic [8:0] strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_2, - input logic [8:0] strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_3, - input logic [8:0] strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_4, - input logic [8:0] strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_5, - input logic [8:0] strg_ub_vec_inst_sram_only_output_addr_gen_1_starting_addr, - input logic [8:0] strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_0, - input logic [8:0] strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_1, - input logic [8:0] strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_2, - input logic [8:0] strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_3, - input logic [8:0] strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_4, - input logic [8:0] strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_5, - input logic [3:0] strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_dimensionality, - input logic [10:0] strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_0, - input logic [10:0] strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_1, - input logic [10:0] strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_2, - input logic [10:0] strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_3, - input logic [10:0] strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_4, - input logic [10:0] strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_5, - input logic [3:0] strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_dimensionality, - input logic [10:0] strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_0, - input logic [10:0] strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_1, - input logic [10:0] strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_2, - input logic [10:0] strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_3, - input logic [10:0] strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_4, - input logic [10:0] strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_5, - input logic strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_enable, - input logic [9:0] strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_delay, - input logic [15:0] strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_starting_addr, - input logic [15:0] strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_0, - input logic [15:0] strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_1, - input logic [15:0] strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_2, - input logic [15:0] strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_3, - input logic [15:0] strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_4, - input logic [15:0] strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_5, - input logic strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_enable, - input logic [9:0] strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_delay, - input logic [15:0] strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_starting_addr, - input logic [15:0] strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_0, - input logic [15:0] strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_1, - input logic [15:0] strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_2, - input logic [15:0] strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_3, - input logic [15:0] strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_4, - input logic [15:0] strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_5, - input logic [3:0] strg_ub_vec_inst_tb_only_loops_buf2out_read_0_dimensionality, - input logic [10:0] strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_0, - input logic [10:0] strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_1, - input logic [10:0] strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_2, - input logic [10:0] strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_3, - input logic [10:0] strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_4, - input logic [10:0] strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_5, - input logic [3:0] strg_ub_vec_inst_tb_only_loops_buf2out_read_1_dimensionality, - input logic [10:0] strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_0, - input logic [10:0] strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_1, - input logic [10:0] strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_2, - input logic [10:0] strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_3, - input logic [10:0] strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_4, - input logic [10:0] strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_5, - input logic strg_ub_vec_inst_tb_only_shared_tb_0, - input logic [3:0] strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_starting_addr, - input logic [3:0] strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_0, - input logic [3:0] strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_1, - input logic [3:0] strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_2, - input logic [3:0] strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_3, - input logic [3:0] strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_4, - input logic [3:0] strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_5, - input logic [3:0] strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_starting_addr, - input logic [3:0] strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_0, - input logic [3:0] strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_1, - input logic [3:0] strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_2, - input logic [3:0] strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_3, - input logic [3:0] strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_4, - input logic [3:0] strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_5, - input logic strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_enable, - input logic [9:0] strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_delay, - input logic [15:0] strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_starting_addr, - input logic [15:0] strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_0, - input logic [15:0] strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_1, - input logic [15:0] strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_2, - input logic [15:0] strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_3, - input logic [15:0] strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_4, - input logic [15:0] strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_5, - input logic strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_enable, - input logic [9:0] strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_delay, - input logic [15:0] strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_starting_addr, - input logic [15:0] strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_0, - input logic [15:0] strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_1, - input logic [15:0] strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_2, - input logic [15:0] strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_3, - input logic [15:0] strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_4, - input logic [15:0] strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_5, - input logic [3:0] strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_starting_addr, - input logic [3:0] strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_0, - input logic [3:0] strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_1, - input logic [3:0] strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_2, - input logic [3:0] strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_3, - input logic [3:0] strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_4, - input logic [3:0] strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_5, - input logic [3:0] strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_starting_addr, - input logic [3:0] strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_0, - input logic [3:0] strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_1, - input logic [3:0] strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_2, - input logic [3:0] strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_3, - input logic [3:0] strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_4, - input logic [3:0] strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_5, - output logic accessor_output_f_b_0, - output logic accessor_output_f_b_1, - output logic [0:0] [16:0] data_out_f_0, - output logic [0:0] [16:0] data_out_f_1, - output logic [8:0] strg_ub_vec_inst_addr_out_lifted, - output logic [3:0] [15:0] strg_ub_vec_inst_data_to_strg_lifted, - output logic strg_ub_vec_inst_ren_to_strg_lifted, - output logic strg_ub_vec_inst_wen_to_strg_lifted -); - -logic [1:0] strg_ub_vec_inst_accessor_output; -logic [1:0][16:0] strg_ub_vec_inst_chain_data_in; -logic [1:0][16:0] strg_ub_vec_inst_data_in; -logic [1:0][16:0] strg_ub_vec_inst_data_out; -assign strg_ub_vec_inst_data_in[0] = data_in_f_0; -assign strg_ub_vec_inst_data_in[1] = data_in_f_1; -assign strg_ub_vec_inst_chain_data_in[0] = chain_data_in_f_0; -assign strg_ub_vec_inst_chain_data_in[1] = chain_data_in_f_1; -assign data_out_f_0 = strg_ub_vec_inst_data_out[0]; -assign data_out_f_1 = strg_ub_vec_inst_data_out[1]; -assign accessor_output_f_b_0 = strg_ub_vec_inst_accessor_output[0]; -assign accessor_output_f_b_1 = strg_ub_vec_inst_accessor_output[1]; -strg_ub_vec strg_ub_vec_inst ( - .agg_only_agg_write_addr_gen_0_starting_addr(strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_starting_addr), - .agg_only_agg_write_addr_gen_0_strides_0(strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_strides_0), - .agg_only_agg_write_addr_gen_0_strides_1(strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_strides_1), - .agg_only_agg_write_addr_gen_0_strides_2(strg_ub_vec_inst_agg_only_agg_write_addr_gen_0_strides_2), - .agg_only_agg_write_addr_gen_1_starting_addr(strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_starting_addr), - .agg_only_agg_write_addr_gen_1_strides_0(strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_strides_0), - .agg_only_agg_write_addr_gen_1_strides_1(strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_strides_1), - .agg_only_agg_write_addr_gen_1_strides_2(strg_ub_vec_inst_agg_only_agg_write_addr_gen_1_strides_2), - .agg_only_agg_write_sched_gen_0_enable(strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_enable), - .agg_only_agg_write_sched_gen_0_sched_addr_gen_starting_addr(strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_starting_addr), - .agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_0(strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_0), - .agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_1(strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_1), - .agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_2(strg_ub_vec_inst_agg_only_agg_write_sched_gen_0_sched_addr_gen_strides_2), - .agg_only_agg_write_sched_gen_1_enable(strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_enable), - .agg_only_agg_write_sched_gen_1_sched_addr_gen_starting_addr(strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_starting_addr), - .agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_0(strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_0), - .agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_1(strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_1), - .agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_2(strg_ub_vec_inst_agg_only_agg_write_sched_gen_1_sched_addr_gen_strides_2), - .agg_only_loops_in2buf_0_dimensionality(strg_ub_vec_inst_agg_only_loops_in2buf_0_dimensionality), - .agg_only_loops_in2buf_0_ranges_0(strg_ub_vec_inst_agg_only_loops_in2buf_0_ranges_0), - .agg_only_loops_in2buf_0_ranges_1(strg_ub_vec_inst_agg_only_loops_in2buf_0_ranges_1), - .agg_only_loops_in2buf_0_ranges_2(strg_ub_vec_inst_agg_only_loops_in2buf_0_ranges_2), - .agg_only_loops_in2buf_1_dimensionality(strg_ub_vec_inst_agg_only_loops_in2buf_1_dimensionality), - .agg_only_loops_in2buf_1_ranges_0(strg_ub_vec_inst_agg_only_loops_in2buf_1_ranges_0), - .agg_only_loops_in2buf_1_ranges_1(strg_ub_vec_inst_agg_only_loops_in2buf_1_ranges_1), - .agg_only_loops_in2buf_1_ranges_2(strg_ub_vec_inst_agg_only_loops_in2buf_1_ranges_2), - .agg_sram_shared_agg_read_sched_gen_0_agg_read_padding(strg_ub_vec_inst_agg_sram_shared_agg_read_sched_gen_0_agg_read_padding), - .agg_sram_shared_agg_read_sched_gen_1_agg_read_padding(strg_ub_vec_inst_agg_sram_shared_agg_read_sched_gen_1_agg_read_padding), - .agg_sram_shared_agg_sram_shared_addr_gen_0_starting_addr(strg_ub_vec_inst_agg_sram_shared_agg_sram_shared_addr_gen_0_starting_addr), - .agg_sram_shared_agg_sram_shared_addr_gen_1_starting_addr(strg_ub_vec_inst_agg_sram_shared_agg_sram_shared_addr_gen_1_starting_addr), - .agg_sram_shared_mode_0(strg_ub_vec_inst_agg_sram_shared_mode_0), - .agg_sram_shared_mode_1(strg_ub_vec_inst_agg_sram_shared_mode_1), - .chain_chain_en(strg_ub_vec_inst_chain_chain_en), - .chain_data_in(strg_ub_vec_inst_chain_data_in), - .clk(clk), - .clk_en(clk_en), - .data_from_strg(strg_ub_vec_inst_data_from_strg_lifted), - .data_in(strg_ub_vec_inst_data_in), - .flush(flush), - .rst_n(rst_n), - .sram_only_output_addr_gen_0_starting_addr(strg_ub_vec_inst_sram_only_output_addr_gen_0_starting_addr), - .sram_only_output_addr_gen_0_strides_0(strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_0), - .sram_only_output_addr_gen_0_strides_1(strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_1), - .sram_only_output_addr_gen_0_strides_2(strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_2), - .sram_only_output_addr_gen_0_strides_3(strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_3), - .sram_only_output_addr_gen_0_strides_4(strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_4), - .sram_only_output_addr_gen_0_strides_5(strg_ub_vec_inst_sram_only_output_addr_gen_0_strides_5), - .sram_only_output_addr_gen_1_starting_addr(strg_ub_vec_inst_sram_only_output_addr_gen_1_starting_addr), - .sram_only_output_addr_gen_1_strides_0(strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_0), - .sram_only_output_addr_gen_1_strides_1(strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_1), - .sram_only_output_addr_gen_1_strides_2(strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_2), - .sram_only_output_addr_gen_1_strides_3(strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_3), - .sram_only_output_addr_gen_1_strides_4(strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_4), - .sram_only_output_addr_gen_1_strides_5(strg_ub_vec_inst_sram_only_output_addr_gen_1_strides_5), - .sram_tb_shared_loops_buf2out_autovec_read_0_dimensionality(strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_dimensionality), - .sram_tb_shared_loops_buf2out_autovec_read_0_ranges_0(strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_0), - .sram_tb_shared_loops_buf2out_autovec_read_0_ranges_1(strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_1), - .sram_tb_shared_loops_buf2out_autovec_read_0_ranges_2(strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_2), - .sram_tb_shared_loops_buf2out_autovec_read_0_ranges_3(strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_3), - .sram_tb_shared_loops_buf2out_autovec_read_0_ranges_4(strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_4), - .sram_tb_shared_loops_buf2out_autovec_read_0_ranges_5(strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_0_ranges_5), - .sram_tb_shared_loops_buf2out_autovec_read_1_dimensionality(strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_dimensionality), - .sram_tb_shared_loops_buf2out_autovec_read_1_ranges_0(strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_0), - .sram_tb_shared_loops_buf2out_autovec_read_1_ranges_1(strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_1), - .sram_tb_shared_loops_buf2out_autovec_read_1_ranges_2(strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_2), - .sram_tb_shared_loops_buf2out_autovec_read_1_ranges_3(strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_3), - .sram_tb_shared_loops_buf2out_autovec_read_1_ranges_4(strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_4), - .sram_tb_shared_loops_buf2out_autovec_read_1_ranges_5(strg_ub_vec_inst_sram_tb_shared_loops_buf2out_autovec_read_1_ranges_5), - .sram_tb_shared_output_sched_gen_0_enable(strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_enable), - .sram_tb_shared_output_sched_gen_0_sched_addr_gen_delay(strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_delay), - .sram_tb_shared_output_sched_gen_0_sched_addr_gen_starting_addr(strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_starting_addr), - .sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_0(strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_0), - .sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_1(strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_1), - .sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_2(strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_2), - .sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_3(strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_3), - .sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_4(strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_4), - .sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_5(strg_ub_vec_inst_sram_tb_shared_output_sched_gen_0_sched_addr_gen_strides_5), - .sram_tb_shared_output_sched_gen_1_enable(strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_enable), - .sram_tb_shared_output_sched_gen_1_sched_addr_gen_delay(strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_delay), - .sram_tb_shared_output_sched_gen_1_sched_addr_gen_starting_addr(strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_starting_addr), - .sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_0(strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_0), - .sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_1(strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_1), - .sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_2(strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_2), - .sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_3(strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_3), - .sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_4(strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_4), - .sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_5(strg_ub_vec_inst_sram_tb_shared_output_sched_gen_1_sched_addr_gen_strides_5), - .tb_only_loops_buf2out_read_0_dimensionality(strg_ub_vec_inst_tb_only_loops_buf2out_read_0_dimensionality), - .tb_only_loops_buf2out_read_0_ranges_0(strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_0), - .tb_only_loops_buf2out_read_0_ranges_1(strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_1), - .tb_only_loops_buf2out_read_0_ranges_2(strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_2), - .tb_only_loops_buf2out_read_0_ranges_3(strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_3), - .tb_only_loops_buf2out_read_0_ranges_4(strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_4), - .tb_only_loops_buf2out_read_0_ranges_5(strg_ub_vec_inst_tb_only_loops_buf2out_read_0_ranges_5), - .tb_only_loops_buf2out_read_1_dimensionality(strg_ub_vec_inst_tb_only_loops_buf2out_read_1_dimensionality), - .tb_only_loops_buf2out_read_1_ranges_0(strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_0), - .tb_only_loops_buf2out_read_1_ranges_1(strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_1), - .tb_only_loops_buf2out_read_1_ranges_2(strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_2), - .tb_only_loops_buf2out_read_1_ranges_3(strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_3), - .tb_only_loops_buf2out_read_1_ranges_4(strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_4), - .tb_only_loops_buf2out_read_1_ranges_5(strg_ub_vec_inst_tb_only_loops_buf2out_read_1_ranges_5), - .tb_only_shared_tb_0(strg_ub_vec_inst_tb_only_shared_tb_0), - .tb_only_tb_read_addr_gen_0_starting_addr(strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_starting_addr), - .tb_only_tb_read_addr_gen_0_strides_0(strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_0), - .tb_only_tb_read_addr_gen_0_strides_1(strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_1), - .tb_only_tb_read_addr_gen_0_strides_2(strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_2), - .tb_only_tb_read_addr_gen_0_strides_3(strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_3), - .tb_only_tb_read_addr_gen_0_strides_4(strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_4), - .tb_only_tb_read_addr_gen_0_strides_5(strg_ub_vec_inst_tb_only_tb_read_addr_gen_0_strides_5), - .tb_only_tb_read_addr_gen_1_starting_addr(strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_starting_addr), - .tb_only_tb_read_addr_gen_1_strides_0(strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_0), - .tb_only_tb_read_addr_gen_1_strides_1(strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_1), - .tb_only_tb_read_addr_gen_1_strides_2(strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_2), - .tb_only_tb_read_addr_gen_1_strides_3(strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_3), - .tb_only_tb_read_addr_gen_1_strides_4(strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_4), - .tb_only_tb_read_addr_gen_1_strides_5(strg_ub_vec_inst_tb_only_tb_read_addr_gen_1_strides_5), - .tb_only_tb_read_sched_gen_0_enable(strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_enable), - .tb_only_tb_read_sched_gen_0_sched_addr_gen_delay(strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_delay), - .tb_only_tb_read_sched_gen_0_sched_addr_gen_starting_addr(strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_starting_addr), - .tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_0(strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_0), - .tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_1(strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_1), - .tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_2(strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_2), - .tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_3(strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_3), - .tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_4(strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_4), - .tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_5(strg_ub_vec_inst_tb_only_tb_read_sched_gen_0_sched_addr_gen_strides_5), - .tb_only_tb_read_sched_gen_1_enable(strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_enable), - .tb_only_tb_read_sched_gen_1_sched_addr_gen_delay(strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_delay), - .tb_only_tb_read_sched_gen_1_sched_addr_gen_starting_addr(strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_starting_addr), - .tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_0(strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_0), - .tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_1(strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_1), - .tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_2(strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_2), - .tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_3(strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_3), - .tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_4(strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_4), - .tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_5(strg_ub_vec_inst_tb_only_tb_read_sched_gen_1_sched_addr_gen_strides_5), - .tb_only_tb_write_addr_gen_0_starting_addr(strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_starting_addr), - .tb_only_tb_write_addr_gen_0_strides_0(strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_0), - .tb_only_tb_write_addr_gen_0_strides_1(strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_1), - .tb_only_tb_write_addr_gen_0_strides_2(strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_2), - .tb_only_tb_write_addr_gen_0_strides_3(strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_3), - .tb_only_tb_write_addr_gen_0_strides_4(strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_4), - .tb_only_tb_write_addr_gen_0_strides_5(strg_ub_vec_inst_tb_only_tb_write_addr_gen_0_strides_5), - .tb_only_tb_write_addr_gen_1_starting_addr(strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_starting_addr), - .tb_only_tb_write_addr_gen_1_strides_0(strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_0), - .tb_only_tb_write_addr_gen_1_strides_1(strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_1), - .tb_only_tb_write_addr_gen_1_strides_2(strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_2), - .tb_only_tb_write_addr_gen_1_strides_3(strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_3), - .tb_only_tb_write_addr_gen_1_strides_4(strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_4), - .tb_only_tb_write_addr_gen_1_strides_5(strg_ub_vec_inst_tb_only_tb_write_addr_gen_1_strides_5), - .accessor_output(strg_ub_vec_inst_accessor_output), - .addr_out(strg_ub_vec_inst_addr_out_lifted), - .data_out(strg_ub_vec_inst_data_out), - .data_to_strg(strg_ub_vec_inst_data_to_strg_lifted), - .ren_to_strg(strg_ub_vec_inst_ren_to_strg_lifted), - .wen_to_strg(strg_ub_vec_inst_wen_to_strg_lifted) -); - -endmodule // strg_ub_vec_flat - -module write_scanner ( - input logic ID_out_ready, - input logic [16:0] addr_in, - input logic addr_in_valid, - input logic addr_out_ready, - input logic block_mode, - input logic [16:0] block_wr_in, - input logic block_wr_in_valid, - input logic clk, - input logic clk_en, - input logic compressed, - input logic [16:0] data_in, - input logic data_in_valid, - input logic data_out_ready, - input logic flush, - input logic init_blank, - input logic lowest_level, - input logic rst_n, - input logic [15:0] stop_lvl, - input logic tile_en, - input logic vector_reduce_mode, - output logic [16:0] ID_out, - output logic ID_out_valid, - output logic addr_in_ready, - output logic [16:0] addr_out, - output logic addr_out_valid, - output logic block_wr_in_ready, - output logic data_in_ready, - output logic [16:0] data_out, - output logic data_out_valid -); - -typedef enum logic[3:0] { - ALLOCATE1 = 4'h0, - ALLOCATE2 = 4'h1, - BLOCK_1_SZ = 4'h2, - BLOCK_1_WR = 4'h3, - BLOCK_2_SZ = 4'h4, - BLOCK_2_WR = 4'h5, - ComLL = 4'h6, - DONE = 4'h7, - FINALIZE1 = 4'h8, - FINALIZE2 = 4'h9, - LL = 4'hA, - START = 4'hB, - UL = 4'hC, - UL_EMIT = 4'hD, - UL_WZ = 4'hE, - UnLL = 4'hF -} scan_seq_state; -logic [0:0][16:0] ID_out_fifo_data_in; -logic ID_out_fifo_empty; -logic ID_out_fifo_full; -logic ID_out_fifo_push; -logic [15:0] ID_to_fifo; -logic IN_DONE; -logic addr_done_in; -logic [15:0] addr_infifo_data_in; -logic addr_infifo_eos_in; -logic [16:0] addr_infifo_in_packed; -logic [16:0] addr_infifo_out_packed; -logic addr_infifo_valid_in; -logic addr_input_fifo_empty; -logic addr_input_fifo_full; -logic [0:0][16:0] addr_out_fifo_data_in; -logic addr_out_fifo_empty; -logic addr_out_fifo_full; -logic addr_out_fifo_push; -logic [15:0] addr_to_fifo; -logic blank_done_stick_sticky; -logic blank_done_stick_was_high; -logic [15:0] block_size; -logic block_wr_fifo_valid; -logic [0:0][15:0] block_wr_input_fifo_data_out; -logic block_wr_input_fifo_empty; -logic block_wr_input_fifo_full; -logic [15:0] block_write_count; -logic clr_blank_done; -logic clr_block_write; -logic clr_coord_addr; -logic clr_curr_coord; -logic clr_seg_addr; -logic clr_seg_ctr; -logic clr_wen_made; -logic [15:0] coord_addr; -logic data_done_in; -logic [15:0] data_infifo_data_in; -logic [15:0] data_infifo_data_in_d1; -logic data_infifo_eos_in; -logic [16:0] data_infifo_in_packed; -logic [16:0] data_infifo_out_packed; -logic data_infifo_valid_in; -logic data_input_fifo_empty; -logic data_input_fifo_full; -logic [0:0][16:0] data_out_fifo_data_in; -logic data_out_fifo_empty; -logic data_out_fifo_full; -logic data_out_fifo_push; -logic [15:0] data_to_fifo; -logic [16:0] done_token; -logic gclk; -logic inc_block_write; -logic inc_coord_addr; -logic inc_seg_addr; -logic inc_seg_ctr; -logic [1:0] infifo_pop; -logic new_coord; -logic op_to_fifo; -logic pop_block_wr; -logic push_to_outs; -scan_seq_state scan_seq_current_state; -scan_seq_state scan_seq_next_state; -logic [15:0] segment_addr; -logic [15:0] segment_counter; -logic [16:0] semi_done_token; -logic set_blank_done; -logic set_block_size; -logic set_curr_coord; -logic stop_in; -logic valid_coord_sticky_sticky; -logic valid_coord_sticky_was_high; -logic [16:0] vr_fsm_wr_scan_data_in; -logic wen_made_sticky; -logic wen_made_was_high; -assign gclk = clk & tile_en; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - blank_done_stick_was_high <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - blank_done_stick_was_high <= 1'h0; - end - else if (clr_blank_done) begin - blank_done_stick_was_high <= 1'h0; - end - else if (set_blank_done) begin - blank_done_stick_was_high <= 1'h1; - end - end -end -assign blank_done_stick_sticky = blank_done_stick_was_high; -assign done_token = {1'h1, 7'h0, 1'h1, 8'h0}; -assign semi_done_token = {1'h1, 11'h0, 1'h1, 4'h0}; -assign vr_fsm_wr_scan_data_in = (data_in == semi_done_token) ? done_token: data_in; -assign data_infifo_in_packed = vector_reduce_mode ? vr_fsm_wr_scan_data_in: data_in; -assign data_infifo_eos_in = data_infifo_out_packed[16]; -assign data_infifo_data_in = data_infifo_out_packed[15:0]; -assign data_in_ready = ~data_input_fifo_full; -assign data_infifo_valid_in = ~data_input_fifo_empty; -assign addr_infifo_in_packed[16] = addr_in[16]; -assign addr_infifo_in_packed[15:0] = addr_in[15:0]; -assign addr_infifo_eos_in = addr_infifo_out_packed[16]; -assign addr_infifo_data_in = addr_infifo_out_packed[15:0]; -assign addr_in_ready = ~addr_input_fifo_full; -assign addr_infifo_valid_in = ~addr_input_fifo_empty; -assign block_wr_in_ready = ~block_wr_input_fifo_full; -assign block_wr_fifo_valid = ~block_wr_input_fifo_empty; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - block_size <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - block_size <= 16'h0; - end - else if (1'h0) begin - block_size <= 16'h0; - end - else if (set_block_size) begin - block_size <= block_wr_input_fifo_data_out; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - block_write_count <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - block_write_count <= 16'h0; - end - else if (clr_block_write) begin - block_write_count <= 16'h0; - end - else if (inc_block_write) begin - block_write_count <= block_write_count + 16'h1; - end - end -end -assign data_out_fifo_data_in = {op_to_fifo, data_to_fifo}; -assign data_out_valid = ~data_out_fifo_empty; -assign addr_out_fifo_data_in = {1'h0, addr_to_fifo}; -assign addr_out_valid = ~addr_out_fifo_empty; -assign ID_out_fifo_data_in = {1'h0, ID_to_fifo}; -assign ID_out_valid = ~ID_out_fifo_empty; -assign {data_out_fifo_push, addr_out_fifo_push, ID_out_fifo_push} = {push_to_outs, push_to_outs, push_to_outs}; -assign data_done_in = data_infifo_valid_in & data_infifo_eos_in & (data_infifo_data_in[9:8] == 2'h1); -assign addr_done_in = addr_infifo_valid_in & addr_infifo_eos_in & (addr_infifo_data_in[9:8] == 2'h1); - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - segment_addr <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - segment_addr <= 16'h0; - end - else if (clr_seg_addr) begin - segment_addr <= 16'h0; - end - else if (inc_seg_addr) begin - segment_addr <= segment_addr + 16'h1; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - coord_addr <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - coord_addr <= 16'h0; - end - else if (clr_coord_addr) begin - coord_addr <= 16'h0; - end - else if (inc_coord_addr) begin - coord_addr <= coord_addr + 16'h1; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - segment_counter <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - segment_counter <= 16'h0; - end - else if (clr_seg_ctr) begin - segment_counter <= 16'h0; - end - else if (inc_seg_ctr) begin - segment_counter <= segment_counter + 16'h1; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - data_infifo_data_in_d1 <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - data_infifo_data_in_d1 <= 16'h0; - end - else if (1'h0) begin - data_infifo_data_in_d1 <= 16'h0; - end - else if (set_curr_coord) begin - data_infifo_data_in_d1 <= data_infifo_data_in; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - valid_coord_sticky_was_high <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - valid_coord_sticky_was_high <= 1'h0; - end - else if (clr_curr_coord) begin - valid_coord_sticky_was_high <= 1'h0; - end - else if (set_curr_coord) begin - valid_coord_sticky_was_high <= 1'h1; - end - end -end -assign valid_coord_sticky_sticky = valid_coord_sticky_was_high; -assign new_coord = data_infifo_valid_in & (~data_infifo_eos_in) & ((~valid_coord_sticky_sticky) | - (data_infifo_data_in != data_infifo_data_in_d1)); -assign stop_in = data_infifo_valid_in & data_infifo_eos_in; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - wen_made_was_high <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - wen_made_was_high <= 1'h0; - end - else if (clr_wen_made) begin - wen_made_was_high <= 1'h0; - end - else if (push_to_outs) begin - wen_made_was_high <= 1'h1; - end - end -end -assign wen_made_sticky = wen_made_was_high; - -always_ff @(posedge clk, negedge rst_n) begin - if (!rst_n) begin - scan_seq_current_state <= START; - end - else if (clk_en) begin - if (flush) begin - scan_seq_current_state <= START; - end - else scan_seq_current_state <= scan_seq_next_state; - end -end -always_comb begin - scan_seq_next_state = scan_seq_current_state; - unique case (scan_seq_current_state) - ALLOCATE1: begin - if (~(&(~{data_out_fifo_full, addr_out_fifo_full, ID_out_fifo_full}))) begin - scan_seq_next_state = ALLOCATE1; - end - else if ((~lowest_level) & (&(~{data_out_fifo_full, addr_out_fifo_full, ID_out_fifo_full}))) begin - scan_seq_next_state = ALLOCATE2; - end - else if (lowest_level & block_mode & (&(~{data_out_fifo_full, addr_out_fifo_full, ID_out_fifo_full}))) begin - scan_seq_next_state = BLOCK_1_SZ; - end - else if (lowest_level & (~block_mode) & (&(~{data_out_fifo_full, addr_out_fifo_full, ID_out_fifo_full}))) begin - scan_seq_next_state = LL; - end - end - ALLOCATE2: begin - if (~(&(~{data_out_fifo_full, addr_out_fifo_full, ID_out_fifo_full}))) begin - scan_seq_next_state = ALLOCATE2; - end - else if (block_mode & (&(~{data_out_fifo_full, addr_out_fifo_full, ID_out_fifo_full}))) begin - scan_seq_next_state = BLOCK_1_SZ; - end - else if ((~block_mode) & (&(~{data_out_fifo_full, addr_out_fifo_full, ID_out_fifo_full}))) begin - scan_seq_next_state = UL_WZ; - end - end - BLOCK_1_SZ: begin - if (block_wr_fifo_valid) begin - scan_seq_next_state = BLOCK_1_WR; - end - else scan_seq_next_state = BLOCK_1_SZ; - end - BLOCK_1_WR: begin - if ((block_write_count == block_size) & (~lowest_level)) begin - scan_seq_next_state = BLOCK_2_SZ; - end - else if ((block_write_count == block_size) & lowest_level) begin - scan_seq_next_state = FINALIZE2; - end - else scan_seq_next_state = BLOCK_1_WR; - end - BLOCK_2_SZ: begin - if (block_wr_fifo_valid) begin - scan_seq_next_state = BLOCK_2_WR; - end - else scan_seq_next_state = BLOCK_2_SZ; - end - BLOCK_2_WR: begin - if (block_write_count == block_size) begin - scan_seq_next_state = FINALIZE1; - end - else scan_seq_next_state = BLOCK_2_WR; - end - ComLL: begin - if (data_done_in) begin - scan_seq_next_state = FINALIZE2; - end - else scan_seq_next_state = ComLL; - end - DONE: scan_seq_next_state = START; - FINALIZE1: begin - if (&(~{data_out_fifo_full, addr_out_fifo_full, ID_out_fifo_full})) begin - scan_seq_next_state = FINALIZE2; - end - else scan_seq_next_state = FINALIZE1; - end - FINALIZE2: begin - if (&(~{data_out_fifo_full, addr_out_fifo_full, ID_out_fifo_full})) begin - scan_seq_next_state = DONE; - end - else scan_seq_next_state = FINALIZE2; - end - LL: begin - if (init_blank & (~blank_done_stick_sticky)) begin - scan_seq_next_state = FINALIZE2; - end - else if (compressed & ((~init_blank) | blank_done_stick_sticky)) begin - scan_seq_next_state = ComLL; - end - else if ((~compressed) & ((~init_blank) | blank_done_stick_sticky)) begin - scan_seq_next_state = UnLL; - end - end - START: begin - if (tile_en) begin - scan_seq_next_state = ALLOCATE1; - end - else scan_seq_next_state = START; - end - UL: begin - if (data_infifo_valid_in) begin - scan_seq_next_state = UL_EMIT; - end - else scan_seq_next_state = UL; - end - UL_EMIT: begin - if (data_done_in) begin - scan_seq_next_state = FINALIZE1; - end - else scan_seq_next_state = UL_EMIT; - end - UL_WZ: begin - if (&(~{data_out_fifo_full, addr_out_fifo_full, ID_out_fifo_full})) begin - scan_seq_next_state = UL; - end - else if (~(&(~{data_out_fifo_full, addr_out_fifo_full, ID_out_fifo_full}))) begin - scan_seq_next_state = UL_WZ; - end - end - UnLL: begin - if (data_done_in & addr_done_in) begin - scan_seq_next_state = FINALIZE2; - end - else scan_seq_next_state = UnLL; - end - default: begin end - endcase -end -always_comb begin - unique case (scan_seq_current_state) - ALLOCATE1: begin :scan_seq_ALLOCATE1_Output - data_to_fifo = 16'h0; - op_to_fifo = 1'h0; - addr_to_fifo = 16'h0; - ID_to_fifo = 16'h0; - push_to_outs = 1'h1; - inc_seg_addr = 1'h0; - clr_seg_addr = 1'h0; - inc_coord_addr = 1'h0; - clr_coord_addr = 1'h0; - inc_seg_ctr = 1'h0; - clr_seg_ctr = 1'h0; - set_curr_coord = 1'h0; - clr_curr_coord = 1'h0; - infifo_pop[0] = 1'h0; - infifo_pop[1] = 1'h0; - clr_wen_made = 1'h0; - set_block_size = 1'h0; - inc_block_write = 1'h0; - clr_block_write = 1'h0; - IN_DONE = 1'h0; - pop_block_wr = 1'h0; - set_blank_done = 1'h0; - clr_blank_done = 1'h0; - end :scan_seq_ALLOCATE1_Output - ALLOCATE2: begin :scan_seq_ALLOCATE2_Output - data_to_fifo = 16'h0; - op_to_fifo = 1'h0; - addr_to_fifo = 16'h0; - ID_to_fifo = 16'h1; - push_to_outs = 1'h1; - inc_seg_addr = 1'h0; - clr_seg_addr = 1'h0; - inc_coord_addr = 1'h0; - clr_coord_addr = 1'h0; - inc_seg_ctr = 1'h0; - clr_seg_ctr = 1'h0; - set_curr_coord = 1'h0; - clr_curr_coord = 1'h0; - infifo_pop[0] = 1'h0; - infifo_pop[1] = 1'h0; - clr_wen_made = 1'h0; - set_block_size = 1'h0; - inc_block_write = 1'h0; - clr_block_write = 1'h0; - IN_DONE = 1'h0; - pop_block_wr = 1'h0; - set_blank_done = 1'h0; - clr_blank_done = 1'h0; - end :scan_seq_ALLOCATE2_Output - BLOCK_1_SZ: begin :scan_seq_BLOCK_1_SZ_Output - data_to_fifo = 16'h0; - op_to_fifo = 1'h0; - addr_to_fifo = 16'h0; - ID_to_fifo = 16'h1; - push_to_outs = 1'h0; - inc_seg_addr = 1'h0; - clr_seg_addr = 1'h0; - inc_coord_addr = 1'h0; - clr_coord_addr = 1'h0; - inc_seg_ctr = 1'h0; - clr_seg_ctr = 1'h0; - set_curr_coord = 1'h0; - clr_curr_coord = 1'h0; - infifo_pop[0] = 1'h0; - infifo_pop[1] = 1'h0; - clr_wen_made = 1'h0; - set_block_size = block_wr_fifo_valid; - inc_block_write = 1'h0; - clr_block_write = 1'h1; - pop_block_wr = block_wr_fifo_valid; - IN_DONE = 1'h0; - set_blank_done = 1'h0; - clr_blank_done = 1'h0; - end :scan_seq_BLOCK_1_SZ_Output - BLOCK_1_WR: begin :scan_seq_BLOCK_1_WR_Output - data_to_fifo = block_wr_input_fifo_data_out; - op_to_fifo = 1'h1; - addr_to_fifo = block_write_count; - ID_to_fifo = 16'h0; - push_to_outs = block_wr_fifo_valid & (block_write_count < block_size); - inc_seg_addr = 1'h0; - clr_seg_addr = 1'h0; - inc_coord_addr = 1'h0; - clr_coord_addr = 1'h0; - inc_seg_ctr = 1'h0; - clr_seg_ctr = 1'h0; - set_curr_coord = 1'h0; - clr_curr_coord = 1'h0; - infifo_pop[0] = 1'h0; - infifo_pop[1] = 1'h0; - clr_wen_made = 1'h0; - set_block_size = 1'h0; - inc_block_write = block_wr_fifo_valid & (block_write_count < block_size) & - (&(~{data_out_fifo_full, addr_out_fifo_full, ID_out_fifo_full})); - clr_block_write = 1'h0; - pop_block_wr = block_wr_fifo_valid & (block_write_count < block_size) & - (&(~{data_out_fifo_full, addr_out_fifo_full, ID_out_fifo_full})); - IN_DONE = 1'h0; - set_blank_done = 1'h0; - clr_blank_done = 1'h0; - end :scan_seq_BLOCK_1_WR_Output - BLOCK_2_SZ: begin :scan_seq_BLOCK_2_SZ_Output - data_to_fifo = 16'h0; - op_to_fifo = 1'h0; - addr_to_fifo = 16'h0; - ID_to_fifo = 16'h0; - push_to_outs = 1'h0; - inc_seg_addr = 1'h0; - clr_seg_addr = 1'h0; - inc_coord_addr = 1'h0; - clr_coord_addr = 1'h0; - inc_seg_ctr = 1'h0; - clr_seg_ctr = 1'h0; - set_curr_coord = 1'h0; - clr_curr_coord = 1'h0; - infifo_pop[0] = 1'h0; - infifo_pop[1] = 1'h0; - clr_wen_made = 1'h0; - set_block_size = block_wr_fifo_valid; - inc_block_write = 1'h0; - clr_block_write = 1'h1; - pop_block_wr = block_wr_fifo_valid; - IN_DONE = 1'h0; - set_blank_done = 1'h0; - clr_blank_done = 1'h0; - end :scan_seq_BLOCK_2_SZ_Output - BLOCK_2_WR: begin :scan_seq_BLOCK_2_WR_Output - data_to_fifo = block_wr_input_fifo_data_out; - op_to_fifo = 1'h1; - addr_to_fifo = block_write_count; - ID_to_fifo = 16'h1; - push_to_outs = block_wr_fifo_valid & (block_write_count < block_size); - inc_seg_addr = 1'h0; - clr_seg_addr = 1'h0; - inc_coord_addr = 1'h0; - clr_coord_addr = 1'h0; - inc_seg_ctr = 1'h0; - clr_seg_ctr = 1'h0; - set_curr_coord = 1'h0; - clr_curr_coord = 1'h0; - infifo_pop[0] = 1'h0; - infifo_pop[1] = 1'h0; - clr_wen_made = 1'h0; - set_block_size = 1'h0; - inc_block_write = block_wr_fifo_valid & (block_write_count < block_size) & - (&(~{data_out_fifo_full, addr_out_fifo_full, ID_out_fifo_full})); - clr_block_write = 1'h0; - pop_block_wr = block_wr_fifo_valid & (block_write_count < block_size) & - (&(~{data_out_fifo_full, addr_out_fifo_full, ID_out_fifo_full})); - IN_DONE = 1'h0; - set_blank_done = 1'h0; - clr_blank_done = 1'h0; - end :scan_seq_BLOCK_2_WR_Output - ComLL: begin :scan_seq_ComLL_Output - data_to_fifo = data_infifo_data_in; - op_to_fifo = 1'h1; - addr_to_fifo = segment_addr; - ID_to_fifo = 16'h0; - push_to_outs = data_infifo_valid_in & (~data_infifo_eos_in); - inc_seg_addr = data_infifo_valid_in & (~data_infifo_eos_in) & (&(~{data_out_fifo_full, - addr_out_fifo_full, ID_out_fifo_full})); - clr_seg_addr = 1'h0; - inc_coord_addr = 1'h0; - clr_coord_addr = 1'h0; - inc_seg_ctr = 1'h0; - clr_seg_ctr = 1'h0; - set_curr_coord = 1'h0; - clr_curr_coord = 1'h0; - infifo_pop[0] = data_infifo_valid_in & (data_infifo_eos_in | (&(~{data_out_fifo_full, - addr_out_fifo_full, ID_out_fifo_full}))); - infifo_pop[1] = 1'h0; - clr_wen_made = 1'h0; - set_block_size = 1'h0; - inc_block_write = 1'h0; - clr_block_write = 1'h0; - IN_DONE = 1'h0; - pop_block_wr = 1'h0; - set_blank_done = 1'h0; - clr_blank_done = 1'h0; - end :scan_seq_ComLL_Output - DONE: begin :scan_seq_DONE_Output - data_to_fifo = 16'h0; - op_to_fifo = 1'h0; - addr_to_fifo = 16'h0; - ID_to_fifo = 16'h0; - push_to_outs = 1'h0; - inc_seg_addr = 1'h0; - clr_seg_addr = 1'h0; - inc_coord_addr = 1'h0; - clr_coord_addr = 1'h0; - inc_seg_ctr = 1'h0; - clr_seg_ctr = 1'h0; - set_curr_coord = 1'h0; - clr_curr_coord = 1'h0; - infifo_pop[0] = data_done_in; - infifo_pop[1] = 1'h0; - clr_wen_made = 1'h0; - set_block_size = 1'h0; - inc_block_write = 1'h0; - clr_block_write = 1'h0; - set_blank_done = 1'h0; - clr_blank_done = 1'h0; - IN_DONE = 1'h1; - pop_block_wr = 1'h0; - end :scan_seq_DONE_Output - FINALIZE1: begin :scan_seq_FINALIZE1_Output - data_to_fifo = 16'h0; - op_to_fifo = 1'h0; - addr_to_fifo = 16'h0; - ID_to_fifo = 16'h1; - push_to_outs = 1'h1; - inc_seg_addr = 1'h0; - clr_seg_addr = 1'h0; - inc_coord_addr = 1'h0; - clr_coord_addr = 1'h0; - inc_seg_ctr = 1'h0; - clr_seg_ctr = 1'h0; - set_curr_coord = 1'h0; - clr_curr_coord = 1'h0; - infifo_pop[0] = 1'h0; - infifo_pop[1] = 1'h0; - clr_wen_made = 1'h0; - set_block_size = 1'h0; - inc_block_write = 1'h0; - clr_block_write = 1'h0; - IN_DONE = 1'h0; - pop_block_wr = 1'h0; - set_blank_done = 1'h0; - clr_blank_done = 1'h0; - end :scan_seq_FINALIZE1_Output - FINALIZE2: begin :scan_seq_FINALIZE2_Output - data_to_fifo = 16'h0; - op_to_fifo = 1'h0; - addr_to_fifo = 16'h0; - ID_to_fifo = 16'h0; - push_to_outs = 1'h1; - inc_seg_addr = 1'h0; - clr_seg_addr = 1'h0; - inc_coord_addr = 1'h0; - clr_coord_addr = 1'h0; - inc_seg_ctr = 1'h0; - clr_seg_ctr = 1'h0; - set_curr_coord = 1'h0; - clr_curr_coord = 1'h0; - infifo_pop[0] = 1'h0; - infifo_pop[1] = 1'h0; - clr_wen_made = 1'h0; - set_block_size = 1'h0; - inc_block_write = 1'h0; - clr_block_write = 1'h0; - IN_DONE = 1'h0; - pop_block_wr = 1'h0; - set_blank_done = 1'h0; - clr_blank_done = 1'h0; - end :scan_seq_FINALIZE2_Output - LL: begin :scan_seq_LL_Output - data_to_fifo = 16'h0; - op_to_fifo = 1'h0; - addr_to_fifo = 16'h0; - ID_to_fifo = 16'h0; - push_to_outs = 1'h0; - inc_seg_addr = 1'h0; - clr_seg_addr = 1'h0; - inc_coord_addr = 1'h0; - clr_coord_addr = 1'h0; - inc_seg_ctr = 1'h0; - clr_seg_ctr = 1'h0; - set_curr_coord = 1'h0; - clr_curr_coord = 1'h0; - infifo_pop[0] = 1'h0; - infifo_pop[1] = 1'h0; - clr_wen_made = 1'h0; - set_block_size = 1'h0; - inc_block_write = 1'h0; - clr_block_write = 1'h0; - IN_DONE = 1'h0; - pop_block_wr = 1'h0; - set_blank_done = 1'h0; - clr_blank_done = 1'h0; - end :scan_seq_LL_Output - START: begin :scan_seq_START_Output - data_to_fifo = 16'h0; - op_to_fifo = 1'h0; - addr_to_fifo = 16'h0; - ID_to_fifo = 16'h0; - push_to_outs = 1'h0; - inc_seg_addr = 1'h0; - clr_seg_addr = 1'h1; - inc_coord_addr = 1'h0; - clr_coord_addr = 1'h1; - inc_seg_ctr = 1'h0; - clr_seg_ctr = 1'h1; - set_curr_coord = 1'h0; - clr_curr_coord = 1'h1; - infifo_pop[0] = 1'h0; - infifo_pop[1] = 1'h0; - clr_wen_made = 1'h1; - set_block_size = 1'h0; - inc_block_write = 1'h0; - clr_block_write = 1'h1; - IN_DONE = 1'h0; - pop_block_wr = 1'h0; - set_blank_done = 1'h0; - clr_blank_done = 1'h0; - end :scan_seq_START_Output - UL: begin :scan_seq_UL_Output - data_to_fifo = 16'h0; - op_to_fifo = 1'h1; - addr_to_fifo = 16'h0; - ID_to_fifo = 16'h0; - push_to_outs = 1'h0; - inc_seg_addr = 1'h0; - clr_seg_addr = 1'h0; - inc_coord_addr = 1'h0; - clr_coord_addr = 1'h0; - inc_seg_ctr = 1'h0; - clr_seg_ctr = 1'h0; - set_curr_coord = new_coord; - clr_curr_coord = 1'h0; - infifo_pop[0] = 1'h0; - infifo_pop[1] = 1'h0; - clr_wen_made = 1'h1; - set_block_size = 1'h0; - inc_block_write = 1'h0; - clr_block_write = 1'h0; - IN_DONE = 1'h0; - pop_block_wr = 1'h0; - set_blank_done = 1'h0; - clr_blank_done = 1'h0; - end :scan_seq_UL_Output - UL_EMIT: begin :scan_seq_UL_EMIT_Output - data_to_fifo = stop_in ? segment_counter: data_infifo_data_in; - op_to_fifo = 1'h1; - addr_to_fifo = stop_in ? segment_addr: coord_addr; - ID_to_fifo = stop_in ? 16'h0: 16'h1; - push_to_outs = data_infifo_valid_in & (&(~{data_out_fifo_full, addr_out_fifo_full, - ID_out_fifo_full})) & (~data_done_in); - inc_seg_addr = stop_in & (&(~{data_out_fifo_full, addr_out_fifo_full, ID_out_fifo_full})) & - (~data_done_in); - clr_seg_addr = 1'h0; - inc_coord_addr = (~data_infifo_eos_in) & data_infifo_valid_in & (&(~{data_out_fifo_full, - addr_out_fifo_full, ID_out_fifo_full})); - clr_coord_addr = 1'h0; - inc_seg_ctr = (~data_infifo_eos_in) & data_infifo_valid_in & (&(~{data_out_fifo_full, - addr_out_fifo_full, ID_out_fifo_full})); - clr_seg_ctr = 1'h0; - set_curr_coord = new_coord; - clr_curr_coord = ~wen_made_sticky; - infifo_pop[0] = data_infifo_valid_in & (&(~{data_out_fifo_full, addr_out_fifo_full, - ID_out_fifo_full})) & (~data_done_in); - infifo_pop[1] = 1'h0; - clr_wen_made = wen_made_sticky & data_infifo_valid_in; - set_block_size = 1'h0; - inc_block_write = 1'h0; - clr_block_write = 1'h0; - IN_DONE = 1'h0; - pop_block_wr = 1'h0; - set_blank_done = 1'h0; - clr_blank_done = 1'h0; - end :scan_seq_UL_EMIT_Output - UL_WZ: begin :scan_seq_UL_WZ_Output - data_to_fifo = 16'h0; - op_to_fifo = 1'h1; - addr_to_fifo = segment_addr; - ID_to_fifo = 16'h0; - push_to_outs = 1'h1; - inc_seg_addr = &(~{data_out_fifo_full, addr_out_fifo_full, ID_out_fifo_full}); - clr_seg_addr = 1'h0; - inc_coord_addr = 1'h0; - clr_coord_addr = 1'h0; - inc_seg_ctr = 1'h0; - clr_seg_ctr = 1'h0; - set_curr_coord = 1'h0; - clr_curr_coord = 1'h0; - infifo_pop[0] = 1'h0; - infifo_pop[1] = 1'h0; - clr_wen_made = 1'h0; - set_block_size = 1'h0; - inc_block_write = 1'h0; - clr_block_write = 1'h0; - IN_DONE = 1'h0; - pop_block_wr = 1'h0; - set_blank_done = 1'h0; - clr_blank_done = 1'h0; - end :scan_seq_UL_WZ_Output - UnLL: begin :scan_seq_UnLL_Output - data_to_fifo = data_infifo_data_in; - op_to_fifo = 1'h1; - addr_to_fifo = addr_infifo_data_in; - ID_to_fifo = 16'h0; - push_to_outs = data_infifo_valid_in & addr_infifo_valid_in & (~(data_infifo_eos_in | - addr_infifo_eos_in)); - inc_seg_addr = 1'h0; - clr_seg_addr = 1'h0; - inc_coord_addr = 1'h0; - clr_coord_addr = 1'h0; - inc_seg_ctr = 1'h0; - clr_seg_ctr = 1'h0; - set_curr_coord = 1'h0; - clr_curr_coord = 1'h0; - infifo_pop[0] = data_infifo_valid_in & addr_infifo_valid_in & ((data_infifo_eos_in & - addr_infifo_eos_in) | (&(~{data_out_fifo_full, addr_out_fifo_full, - ID_out_fifo_full}))); - infifo_pop[1] = data_infifo_valid_in & addr_infifo_valid_in & ((data_infifo_eos_in & - addr_infifo_eos_in) | (&(~{data_out_fifo_full, addr_out_fifo_full, - ID_out_fifo_full}))); - clr_wen_made = 1'h0; - set_block_size = 1'h0; - inc_block_write = 1'h0; - clr_block_write = 1'h0; - IN_DONE = 1'h0; - pop_block_wr = 1'h0; - set_blank_done = 1'h0; - clr_blank_done = 1'h0; - end :scan_seq_UnLL_Output - default: begin end - endcase -end -reg_fifo_depth_2_w_17_afd_2 data_input_fifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in(data_infifo_in_packed), - .flush(flush), - .pop(infifo_pop[0]), - .push(data_in_valid), - .rst_n(rst_n), - .data_out(data_infifo_out_packed), - .empty(data_input_fifo_empty), - .full(data_input_fifo_full) -); - -reg_fifo_depth_0_w_17_afd_2 addr_input_fifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in(addr_infifo_in_packed), - .flush(flush), - .pop(infifo_pop[1]), - .push(addr_in_valid), - .rst_n(rst_n), - .data_out(addr_infifo_out_packed), - .empty(addr_input_fifo_empty), - .full(addr_input_fifo_full) -); - -reg_fifo_depth_0_w_16_afd_2 block_wr_input_fifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in(block_wr_in[15:0]), - .flush(flush), - .pop(pop_block_wr), - .push(block_wr_in_valid), - .rst_n(rst_n), - .data_out(block_wr_input_fifo_data_out), - .empty(block_wr_input_fifo_empty), - .full(block_wr_input_fifo_full) -); - -reg_fifo_depth_2_w_17_afd_2 data_out_fifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in(data_out_fifo_data_in), - .flush(flush), - .pop(data_out_ready), - .push(data_out_fifo_push), - .rst_n(rst_n), - .data_out(data_out), - .empty(data_out_fifo_empty), - .full(data_out_fifo_full) -); - -reg_fifo_depth_2_w_17_afd_2 addr_out_fifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in(addr_out_fifo_data_in), - .flush(flush), - .pop(addr_out_ready), - .push(addr_out_fifo_push), - .rst_n(rst_n), - .data_out(addr_out), - .empty(addr_out_fifo_empty), - .full(addr_out_fifo_full) -); - -reg_fifo_depth_2_w_17_afd_2 ID_out_fifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in(ID_out_fifo_data_in), - .flush(flush), - .pop(ID_out_ready), - .push(ID_out_fifo_push), - .rst_n(rst_n), - .data_out(ID_out), - .empty(ID_out_fifo_empty), - .full(ID_out_fifo_full) -); - -endmodule // write_scanner - diff --git a/sam/onyx/.magma/PE_inner_W-kratos.sv b/sam/onyx/.magma/PE_inner_W-kratos.sv deleted file mode 100644 index 23e35031..00000000 --- a/sam/onyx/.magma/PE_inner_W-kratos.sv +++ /dev/null @@ -1,3389 +0,0 @@ -module PE_inner ( - input logic [31:0] CONFIG_SPACE_0, - input logic [31:0] CONFIG_SPACE_1, - input logic [31:0] CONFIG_SPACE_2, - input logic [27:0] CONFIG_SPACE_3, - input logic [0:0] [16:0] PE_input_width_17_num_0, - input logic PE_input_width_17_num_0_dense, - input logic PE_input_width_17_num_0_valid, - input logic [0:0] [16:0] PE_input_width_17_num_1, - input logic PE_input_width_17_num_1_dense, - input logic PE_input_width_17_num_1_valid, - input logic [0:0] [16:0] PE_input_width_17_num_2, - input logic PE_input_width_17_num_2_dense, - input logic PE_input_width_17_num_2_valid, - input logic [0:0] [16:0] PE_input_width_17_num_3, - input logic PE_input_width_17_num_3_valid, - input logic PE_input_width_1_num_0, - input logic PE_input_width_1_num_1, - input logic PE_input_width_1_num_2, - input logic PE_output_width_17_num_0_ready, - input logic PE_output_width_17_num_1_dense, - input logic PE_output_width_17_num_1_ready, - input logic PE_output_width_17_num_2_ready, - input logic clk, - input logic clk_en, - input logic flush, - input logic [2:0] mode, - input logic rst_n, - input logic tile_en, - output logic PE_input_width_17_num_0_ready, - output logic PE_input_width_17_num_1_ready, - output logic PE_input_width_17_num_2_ready, - output logic PE_input_width_17_num_3_ready, - output logic [0:0] [16:0] PE_output_width_17_num_0, - output logic PE_output_width_17_num_0_valid, - output logic [0:0] [16:0] PE_output_width_17_num_1, - output logic PE_output_width_17_num_1_valid, - output logic [0:0] [16:0] PE_output_width_17_num_2, - output logic PE_output_width_17_num_2_valid, - output logic PE_output_width_1_num_0, - output logic [15:0] reduce_pe_cluster_inst_pe_onyxpeintf_O2, - output logic [15:0] reduce_pe_cluster_inst_pe_onyxpeintf_O3, - output logic [15:0] reduce_pe_cluster_inst_pe_onyxpeintf_O4 -); - -logic [123:0] CONFIG_SPACE; -logic gclk; -logic [0:0][16:0] input_width_17_num_0_fifo_out; -logic input_width_17_num_0_fifo_out_ready; -logic input_width_17_num_0_fifo_out_valid; -logic input_width_17_num_0_input_fifo_empty; -logic input_width_17_num_0_input_fifo_full; -logic [0:0][16:0] input_width_17_num_1_fifo_out; -logic input_width_17_num_1_fifo_out_ready; -logic input_width_17_num_1_fifo_out_valid; -logic input_width_17_num_1_input_fifo_empty; -logic input_width_17_num_1_input_fifo_full; -logic [0:0][16:0] input_width_17_num_2_fifo_out; -logic input_width_17_num_2_fifo_out_ready; -logic input_width_17_num_2_fifo_out_valid; -logic input_width_17_num_2_input_fifo_empty; -logic input_width_17_num_2_input_fifo_full; -logic [0:0][16:0] input_width_17_num_3_fifo_out; -logic input_width_17_num_3_fifo_out_ready; -logic input_width_17_num_3_fifo_out_valid; -logic input_width_17_num_3_input_fifo_empty; -logic input_width_17_num_3_input_fifo_full; -logic [15:0] mem_ctrl_RepeatSignalGenerator_flat_RepeatSignalGenerator_inst_stop_lvl; -logic mem_ctrl_RepeatSignalGenerator_flat_RepeatSignalGenerator_inst_tile_en; -logic mem_ctrl_RepeatSignalGenerator_flat_base_data_in_ready_f_; -logic mem_ctrl_RepeatSignalGenerator_flat_clk; -logic [0:0][16:0] mem_ctrl_RepeatSignalGenerator_flat_repsig_data_out_f_; -logic mem_ctrl_RepeatSignalGenerator_flat_repsig_data_out_valid_f_; -logic mem_ctrl_Repeat_flat_Repeat_inst_root; -logic mem_ctrl_Repeat_flat_Repeat_inst_spacc_mode; -logic [15:0] mem_ctrl_Repeat_flat_Repeat_inst_stop_lvl; -logic mem_ctrl_Repeat_flat_Repeat_inst_tile_en; -logic mem_ctrl_Repeat_flat_clk; -logic mem_ctrl_Repeat_flat_proc_data_in_ready_f_; -logic [0:0][16:0] mem_ctrl_Repeat_flat_ref_data_out_f_; -logic mem_ctrl_Repeat_flat_ref_data_out_valid_f_; -logic mem_ctrl_Repeat_flat_repsig_data_in_ready_f_; -logic mem_ctrl_crddrop_flat_clk; -logic mem_ctrl_crddrop_flat_cmrg_coord_in_0_ready_f_; -logic mem_ctrl_crddrop_flat_cmrg_coord_in_1_ready_f_; -logic [0:0][16:0] mem_ctrl_crddrop_flat_cmrg_coord_out_0_f_; -logic mem_ctrl_crddrop_flat_cmrg_coord_out_0_valid_f_; -logic [0:0][16:0] mem_ctrl_crddrop_flat_cmrg_coord_out_1_f_; -logic mem_ctrl_crddrop_flat_cmrg_coord_out_1_valid_f_; -logic mem_ctrl_crddrop_flat_crddrop_inst_cmrg_enable; -logic mem_ctrl_crddrop_flat_crddrop_inst_cmrg_mode; -logic [15:0] mem_ctrl_crddrop_flat_crddrop_inst_cmrg_stop_lvl; -logic mem_ctrl_crddrop_flat_crddrop_inst_tile_en; -logic mem_ctrl_crdhold_flat_clk; -logic mem_ctrl_crdhold_flat_cmrg_coord_in_0_ready_f_; -logic mem_ctrl_crdhold_flat_cmrg_coord_in_1_ready_f_; -logic [0:0][16:0] mem_ctrl_crdhold_flat_cmrg_coord_out_0_f_; -logic mem_ctrl_crdhold_flat_cmrg_coord_out_0_valid_f_; -logic [0:0][16:0] mem_ctrl_crdhold_flat_cmrg_coord_out_1_f_; -logic mem_ctrl_crdhold_flat_cmrg_coord_out_1_valid_f_; -logic mem_ctrl_crdhold_flat_crdhold_inst_cmrg_enable; -logic [15:0] mem_ctrl_crdhold_flat_crdhold_inst_cmrg_stop_lvl; -logic mem_ctrl_crdhold_flat_crdhold_inst_tile_en; -logic mem_ctrl_intersect_unit_flat_clk; -logic mem_ctrl_intersect_unit_flat_coord_in_0_ready_f_; -logic mem_ctrl_intersect_unit_flat_coord_in_1_ready_f_; -logic [0:0][16:0] mem_ctrl_intersect_unit_flat_coord_out_f_; -logic mem_ctrl_intersect_unit_flat_coord_out_valid_f_; -logic mem_ctrl_intersect_unit_flat_intersect_unit_inst_joiner_op; -logic mem_ctrl_intersect_unit_flat_intersect_unit_inst_tile_en; -logic mem_ctrl_intersect_unit_flat_intersect_unit_inst_vector_reduce_mode; -logic mem_ctrl_intersect_unit_flat_pos_in_0_ready_f_; -logic mem_ctrl_intersect_unit_flat_pos_in_1_ready_f_; -logic [0:0][16:0] mem_ctrl_intersect_unit_flat_pos_out_0_f_; -logic mem_ctrl_intersect_unit_flat_pos_out_0_valid_f_; -logic [0:0][16:0] mem_ctrl_intersect_unit_flat_pos_out_1_f_; -logic mem_ctrl_intersect_unit_flat_pos_out_1_valid_f_; -logic mem_ctrl_reduce_pe_cluster_flat_clk; -logic [0:0][16:0] mem_ctrl_reduce_pe_cluster_flat_data0_f_; -logic mem_ctrl_reduce_pe_cluster_flat_data0_ready_f_; -logic mem_ctrl_reduce_pe_cluster_flat_data0_valid_f_; -logic [0:0][16:0] mem_ctrl_reduce_pe_cluster_flat_data1_f_; -logic mem_ctrl_reduce_pe_cluster_flat_data1_ready_f_; -logic mem_ctrl_reduce_pe_cluster_flat_data1_valid_f_; -logic [0:0][16:0] mem_ctrl_reduce_pe_cluster_flat_data2_f_; -logic mem_ctrl_reduce_pe_cluster_flat_data2_ready_f_; -logic mem_ctrl_reduce_pe_cluster_flat_data2_valid_f_; -logic mem_ctrl_reduce_pe_cluster_flat_reduce_data_in_ready_f_; -logic [0:0][16:0] mem_ctrl_reduce_pe_cluster_flat_reduce_data_out_f_; -logic mem_ctrl_reduce_pe_cluster_flat_reduce_data_out_valid_f_; -logic mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_pe_dense_mode; -logic mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_pe_in_external; -logic [83:0] mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_pe_onyxpeintf_inst; -logic [2:0] mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_pe_sparse_num_inputs; -logic mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_pe_tile_en; -logic [15:0] mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_reduce_default_value; -logic [15:0] mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_reduce_stop_lvl; -logic mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_reduce_tile_en; -logic mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_tile_en; -logic [0:0][16:0] mem_ctrl_reduce_pe_cluster_flat_res_f_; -logic mem_ctrl_reduce_pe_cluster_flat_res_p_f_; -logic mem_ctrl_reduce_pe_cluster_flat_res_ready_f_; -logic mem_ctrl_reduce_pe_cluster_flat_res_valid_f_; -logic [0:0][16:0] output_width_17_num_0_fifo_in; -logic output_width_17_num_0_fifo_in_ready; -logic output_width_17_num_0_fifo_in_valid; -logic [0:0][16:0] output_width_17_num_0_output_fifo_data_out; -logic output_width_17_num_0_output_fifo_empty; -logic output_width_17_num_0_output_fifo_full; -logic [0:0][16:0] output_width_17_num_1_fifo_in; -logic output_width_17_num_1_fifo_in_ready; -logic output_width_17_num_1_fifo_in_valid; -logic [0:0][16:0] output_width_17_num_1_output_fifo_data_out; -logic output_width_17_num_1_output_fifo_empty; -logic output_width_17_num_1_output_fifo_full; -logic [0:0][16:0] output_width_17_num_2_fifo_in; -logic output_width_17_num_2_fifo_in_ready; -logic output_width_17_num_2_fifo_in_valid; -logic [0:0][16:0] output_width_17_num_2_output_fifo_data_out; -logic output_width_17_num_2_output_fifo_empty; -logic output_width_17_num_2_output_fifo_full; -assign gclk = clk & tile_en; -assign mem_ctrl_intersect_unit_flat_clk = gclk & (mode == 3'h0); -assign mem_ctrl_crddrop_flat_clk = gclk & (mode == 3'h1); -assign mem_ctrl_crdhold_flat_clk = gclk & (mode == 3'h2); -assign mem_ctrl_Repeat_flat_clk = gclk & (mode == 3'h3); -assign mem_ctrl_RepeatSignalGenerator_flat_clk = gclk & (mode == 3'h4); -assign mem_ctrl_reduce_pe_cluster_flat_clk = gclk & (mode == 3'h5); -assign input_width_17_num_0_fifo_out_valid = ~input_width_17_num_0_input_fifo_empty; -always_comb begin - input_width_17_num_0_fifo_out_ready = 1'h1; - if (mode == 3'h0) begin - input_width_17_num_0_fifo_out_ready = mem_ctrl_intersect_unit_flat_coord_in_0_ready_f_; - end - else if (mode == 3'h1) begin - input_width_17_num_0_fifo_out_ready = mem_ctrl_crddrop_flat_cmrg_coord_in_0_ready_f_; - end - else if (mode == 3'h2) begin - input_width_17_num_0_fifo_out_ready = mem_ctrl_crdhold_flat_cmrg_coord_in_0_ready_f_; - end - else if (mode == 3'h3) begin - input_width_17_num_0_fifo_out_ready = mem_ctrl_Repeat_flat_proc_data_in_ready_f_; - end - else if (mode == 3'h4) begin - input_width_17_num_0_fifo_out_ready = mem_ctrl_RepeatSignalGenerator_flat_base_data_in_ready_f_; - end - else if (mode == 3'h5) begin - input_width_17_num_0_fifo_out_ready = mem_ctrl_reduce_pe_cluster_flat_data0_ready_f_; - end -end -assign mem_ctrl_reduce_pe_cluster_flat_data0_f_ = PE_input_width_17_num_0_dense ? PE_input_width_17_num_0: - input_width_17_num_0_fifo_out; -assign mem_ctrl_reduce_pe_cluster_flat_data0_valid_f_ = PE_input_width_17_num_0_dense ? 1'h1: input_width_17_num_0_fifo_out_valid; -always_comb begin - PE_input_width_17_num_0_ready = 1'h1; - if (mode == 3'h0) begin - PE_input_width_17_num_0_ready = ~input_width_17_num_0_input_fifo_full; - end - else if (mode == 3'h1) begin - PE_input_width_17_num_0_ready = ~input_width_17_num_0_input_fifo_full; - end - else if (mode == 3'h2) begin - PE_input_width_17_num_0_ready = ~input_width_17_num_0_input_fifo_full; - end - else if (mode == 3'h3) begin - PE_input_width_17_num_0_ready = ~input_width_17_num_0_input_fifo_full; - end - else if (mode == 3'h4) begin - PE_input_width_17_num_0_ready = ~input_width_17_num_0_input_fifo_full; - end - else if (mode == 3'h5) begin - PE_input_width_17_num_0_ready = PE_input_width_17_num_0_dense ? 1'h1: ~input_width_17_num_0_input_fifo_full; - end -end -assign input_width_17_num_1_fifo_out_valid = ~input_width_17_num_1_input_fifo_empty; -always_comb begin - input_width_17_num_1_fifo_out_ready = 1'h1; - if (mode == 3'h0) begin - input_width_17_num_1_fifo_out_ready = mem_ctrl_intersect_unit_flat_coord_in_1_ready_f_; - end - else if (mode == 3'h1) begin - input_width_17_num_1_fifo_out_ready = mem_ctrl_crddrop_flat_cmrg_coord_in_1_ready_f_; - end - else if (mode == 3'h2) begin - input_width_17_num_1_fifo_out_ready = mem_ctrl_crdhold_flat_cmrg_coord_in_1_ready_f_; - end - else if (mode == 3'h3) begin - input_width_17_num_1_fifo_out_ready = mem_ctrl_Repeat_flat_repsig_data_in_ready_f_; - end - else if (mode == 3'h5) begin - input_width_17_num_1_fifo_out_ready = mem_ctrl_reduce_pe_cluster_flat_data1_ready_f_; - end -end -assign mem_ctrl_reduce_pe_cluster_flat_data1_f_ = PE_input_width_17_num_1_dense ? PE_input_width_17_num_1: - input_width_17_num_1_fifo_out; -assign mem_ctrl_reduce_pe_cluster_flat_data1_valid_f_ = PE_input_width_17_num_1_dense ? 1'h1: input_width_17_num_1_fifo_out_valid; -always_comb begin - PE_input_width_17_num_1_ready = 1'h1; - if (mode == 3'h0) begin - PE_input_width_17_num_1_ready = ~input_width_17_num_1_input_fifo_full; - end - else if (mode == 3'h1) begin - PE_input_width_17_num_1_ready = ~input_width_17_num_1_input_fifo_full; - end - else if (mode == 3'h2) begin - PE_input_width_17_num_1_ready = ~input_width_17_num_1_input_fifo_full; - end - else if (mode == 3'h3) begin - PE_input_width_17_num_1_ready = ~input_width_17_num_1_input_fifo_full; - end - else if (mode == 3'h5) begin - PE_input_width_17_num_1_ready = PE_input_width_17_num_1_dense ? 1'h1: ~input_width_17_num_1_input_fifo_full; - end -end -assign input_width_17_num_2_fifo_out_valid = ~input_width_17_num_2_input_fifo_empty; -always_comb begin - input_width_17_num_2_fifo_out_ready = 1'h1; - if (mode == 3'h0) begin - input_width_17_num_2_fifo_out_ready = mem_ctrl_intersect_unit_flat_pos_in_0_ready_f_; - end - else if (mode == 3'h5) begin - input_width_17_num_2_fifo_out_ready = mem_ctrl_reduce_pe_cluster_flat_data2_ready_f_; - end -end -assign mem_ctrl_reduce_pe_cluster_flat_data2_f_ = PE_input_width_17_num_2_dense ? PE_input_width_17_num_2: - input_width_17_num_2_fifo_out; -assign mem_ctrl_reduce_pe_cluster_flat_data2_valid_f_ = PE_input_width_17_num_2_dense ? 1'h1: input_width_17_num_2_fifo_out_valid; -always_comb begin - PE_input_width_17_num_2_ready = 1'h1; - if (mode == 3'h0) begin - PE_input_width_17_num_2_ready = ~input_width_17_num_2_input_fifo_full; - end - else if (mode == 3'h5) begin - PE_input_width_17_num_2_ready = PE_input_width_17_num_2_dense ? 1'h1: ~input_width_17_num_2_input_fifo_full; - end -end -assign input_width_17_num_3_fifo_out_valid = ~input_width_17_num_3_input_fifo_empty; -always_comb begin - input_width_17_num_3_fifo_out_ready = 1'h1; - if (mode == 3'h0) begin - input_width_17_num_3_fifo_out_ready = mem_ctrl_intersect_unit_flat_pos_in_1_ready_f_; - end - else if (mode == 3'h5) begin - input_width_17_num_3_fifo_out_ready = mem_ctrl_reduce_pe_cluster_flat_reduce_data_in_ready_f_; - end -end -always_comb begin - PE_input_width_17_num_3_ready = 1'h1; - if (mode == 3'h0) begin - PE_input_width_17_num_3_ready = ~input_width_17_num_3_input_fifo_full; - end - else if (mode == 3'h5) begin - PE_input_width_17_num_3_ready = ~input_width_17_num_3_input_fifo_full; - end -end -assign output_width_17_num_0_fifo_in_ready = ~output_width_17_num_0_output_fifo_full; -always_comb begin - output_width_17_num_0_fifo_in = 17'h0; - output_width_17_num_0_fifo_in_valid = 1'h0; - if (mode == 3'h0) begin - output_width_17_num_0_fifo_in = mem_ctrl_intersect_unit_flat_coord_out_f_; - output_width_17_num_0_fifo_in_valid = mem_ctrl_intersect_unit_flat_coord_out_valid_f_; - end - else if (mode == 3'h1) begin - output_width_17_num_0_fifo_in = mem_ctrl_crddrop_flat_cmrg_coord_out_0_f_; - output_width_17_num_0_fifo_in_valid = mem_ctrl_crddrop_flat_cmrg_coord_out_0_valid_f_; - end - else if (mode == 3'h2) begin - output_width_17_num_0_fifo_in = mem_ctrl_crdhold_flat_cmrg_coord_out_0_f_; - output_width_17_num_0_fifo_in_valid = mem_ctrl_crdhold_flat_cmrg_coord_out_0_valid_f_; - end - else if (mode == 3'h3) begin - output_width_17_num_0_fifo_in = mem_ctrl_Repeat_flat_ref_data_out_f_; - output_width_17_num_0_fifo_in_valid = mem_ctrl_Repeat_flat_ref_data_out_valid_f_; - end - else if (mode == 3'h4) begin - output_width_17_num_0_fifo_in = mem_ctrl_RepeatSignalGenerator_flat_repsig_data_out_f_; - output_width_17_num_0_fifo_in_valid = mem_ctrl_RepeatSignalGenerator_flat_repsig_data_out_valid_f_; - end - else if (mode == 3'h5) begin - output_width_17_num_0_fifo_in = mem_ctrl_reduce_pe_cluster_flat_reduce_data_out_f_; - output_width_17_num_0_fifo_in_valid = mem_ctrl_reduce_pe_cluster_flat_reduce_data_out_valid_f_; - end -end -always_comb begin - PE_output_width_17_num_0 = 17'h0; - if (mode == 3'h0) begin - PE_output_width_17_num_0 = output_width_17_num_0_output_fifo_data_out; - end - else if (mode == 3'h1) begin - PE_output_width_17_num_0 = output_width_17_num_0_output_fifo_data_out; - end - else if (mode == 3'h2) begin - PE_output_width_17_num_0 = output_width_17_num_0_output_fifo_data_out; - end - else if (mode == 3'h3) begin - PE_output_width_17_num_0 = output_width_17_num_0_output_fifo_data_out; - end - else if (mode == 3'h4) begin - PE_output_width_17_num_0 = output_width_17_num_0_output_fifo_data_out; - end - else if (mode == 3'h5) begin - PE_output_width_17_num_0 = output_width_17_num_0_output_fifo_data_out; - end -end -always_comb begin - PE_output_width_17_num_0_valid = 1'h0; - if (mode == 3'h0) begin - PE_output_width_17_num_0_valid = ~output_width_17_num_0_output_fifo_empty; - end - else if (mode == 3'h1) begin - PE_output_width_17_num_0_valid = ~output_width_17_num_0_output_fifo_empty; - end - else if (mode == 3'h2) begin - PE_output_width_17_num_0_valid = ~output_width_17_num_0_output_fifo_empty; - end - else if (mode == 3'h3) begin - PE_output_width_17_num_0_valid = ~output_width_17_num_0_output_fifo_empty; - end - else if (mode == 3'h4) begin - PE_output_width_17_num_0_valid = ~output_width_17_num_0_output_fifo_empty; - end - else if (mode == 3'h5) begin - PE_output_width_17_num_0_valid = ~output_width_17_num_0_output_fifo_empty; - end -end -assign output_width_17_num_1_fifo_in_ready = ~output_width_17_num_1_output_fifo_full; -always_comb begin - output_width_17_num_1_fifo_in = 17'h0; - output_width_17_num_1_fifo_in_valid = 1'h0; - if (mode == 3'h0) begin - output_width_17_num_1_fifo_in = mem_ctrl_intersect_unit_flat_pos_out_0_f_; - output_width_17_num_1_fifo_in_valid = mem_ctrl_intersect_unit_flat_pos_out_0_valid_f_; - end - else if (mode == 3'h1) begin - output_width_17_num_1_fifo_in = mem_ctrl_crddrop_flat_cmrg_coord_out_1_f_; - output_width_17_num_1_fifo_in_valid = mem_ctrl_crddrop_flat_cmrg_coord_out_1_valid_f_; - end - else if (mode == 3'h2) begin - output_width_17_num_1_fifo_in = mem_ctrl_crdhold_flat_cmrg_coord_out_1_f_; - output_width_17_num_1_fifo_in_valid = mem_ctrl_crdhold_flat_cmrg_coord_out_1_valid_f_; - end - else if (mode == 3'h5) begin - output_width_17_num_1_fifo_in = mem_ctrl_reduce_pe_cluster_flat_res_f_; - output_width_17_num_1_fifo_in_valid = mem_ctrl_reduce_pe_cluster_flat_res_valid_f_; - end -end -assign mem_ctrl_reduce_pe_cluster_flat_res_ready_f_ = PE_output_width_17_num_1_dense ? 1'h1: output_width_17_num_1_fifo_in_ready; -always_comb begin - PE_output_width_17_num_1 = 17'h0; - if (mode == 3'h0) begin - PE_output_width_17_num_1 = output_width_17_num_1_output_fifo_data_out; - end - else if (mode == 3'h1) begin - PE_output_width_17_num_1 = output_width_17_num_1_output_fifo_data_out; - end - else if (mode == 3'h2) begin - PE_output_width_17_num_1 = output_width_17_num_1_output_fifo_data_out; - end - else if (mode == 3'h5) begin - PE_output_width_17_num_1 = PE_output_width_17_num_1_dense ? mem_ctrl_reduce_pe_cluster_flat_res_f_: - output_width_17_num_1_output_fifo_data_out; - end -end -always_comb begin - PE_output_width_17_num_1_valid = 1'h0; - if (mode == 3'h0) begin - PE_output_width_17_num_1_valid = ~output_width_17_num_1_output_fifo_empty; - end - else if (mode == 3'h1) begin - PE_output_width_17_num_1_valid = ~output_width_17_num_1_output_fifo_empty; - end - else if (mode == 3'h2) begin - PE_output_width_17_num_1_valid = ~output_width_17_num_1_output_fifo_empty; - end - else if (mode == 3'h5) begin - PE_output_width_17_num_1_valid = PE_output_width_17_num_1_dense ? 1'h1: ~output_width_17_num_1_output_fifo_empty; - end -end -assign output_width_17_num_2_fifo_in_ready = ~output_width_17_num_2_output_fifo_full; -always_comb begin - output_width_17_num_2_fifo_in = 17'h0; - output_width_17_num_2_fifo_in_valid = 1'h0; - output_width_17_num_2_fifo_in = mem_ctrl_intersect_unit_flat_pos_out_1_f_; - output_width_17_num_2_fifo_in_valid = mem_ctrl_intersect_unit_flat_pos_out_1_valid_f_; -end -always_comb begin - PE_output_width_17_num_2 = 17'h0; - if (mode == 3'h0) begin - PE_output_width_17_num_2 = output_width_17_num_2_output_fifo_data_out; - end - else PE_output_width_17_num_2 = 17'h0; -end -always_comb begin - PE_output_width_17_num_2_valid = 1'h0; - if (mode == 3'h0) begin - PE_output_width_17_num_2_valid = ~output_width_17_num_2_output_fifo_empty; - end - else PE_output_width_17_num_2_valid = 1'h0; -end -always_comb begin - PE_output_width_1_num_0 = 1'h0; - if (mode == 3'h5) begin - PE_output_width_1_num_0 = mem_ctrl_reduce_pe_cluster_flat_res_p_f_; - end - else PE_output_width_1_num_0 = 1'h0; -end -assign {mem_ctrl_intersect_unit_flat_intersect_unit_inst_joiner_op, mem_ctrl_intersect_unit_flat_intersect_unit_inst_tile_en, mem_ctrl_intersect_unit_flat_intersect_unit_inst_vector_reduce_mode} = CONFIG_SPACE[2:0]; -assign {mem_ctrl_crddrop_flat_crddrop_inst_cmrg_enable, mem_ctrl_crddrop_flat_crddrop_inst_cmrg_mode, mem_ctrl_crddrop_flat_crddrop_inst_cmrg_stop_lvl, mem_ctrl_crddrop_flat_crddrop_inst_tile_en} = CONFIG_SPACE[18:0]; -assign {mem_ctrl_crdhold_flat_crdhold_inst_cmrg_enable, mem_ctrl_crdhold_flat_crdhold_inst_cmrg_stop_lvl, mem_ctrl_crdhold_flat_crdhold_inst_tile_en} = CONFIG_SPACE[17:0]; -assign {mem_ctrl_Repeat_flat_Repeat_inst_root, mem_ctrl_Repeat_flat_Repeat_inst_spacc_mode, mem_ctrl_Repeat_flat_Repeat_inst_stop_lvl, mem_ctrl_Repeat_flat_Repeat_inst_tile_en} = CONFIG_SPACE[18:0]; -assign {mem_ctrl_RepeatSignalGenerator_flat_RepeatSignalGenerator_inst_stop_lvl, mem_ctrl_RepeatSignalGenerator_flat_RepeatSignalGenerator_inst_tile_en} = CONFIG_SPACE[16:0]; -assign {mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_pe_dense_mode, mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_pe_in_external, mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_pe_onyxpeintf_inst, mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_pe_sparse_num_inputs, mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_pe_tile_en, mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_reduce_default_value, mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_reduce_stop_lvl, mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_reduce_tile_en, mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_tile_en} = CONFIG_SPACE[123:0]; -assign CONFIG_SPACE[31:0] = CONFIG_SPACE_0; -assign CONFIG_SPACE[63:32] = CONFIG_SPACE_1; -assign CONFIG_SPACE[95:64] = CONFIG_SPACE_2; -assign CONFIG_SPACE[123:96] = CONFIG_SPACE_3; -intersect_unit_flat mem_ctrl_intersect_unit_flat ( - .clk(mem_ctrl_intersect_unit_flat_clk), - .clk_en(clk_en), - .coord_in_0_f_(input_width_17_num_0_fifo_out), - .coord_in_0_valid_f_(input_width_17_num_0_fifo_out_valid), - .coord_in_1_f_(input_width_17_num_1_fifo_out), - .coord_in_1_valid_f_(input_width_17_num_1_fifo_out_valid), - .coord_out_ready_f_(output_width_17_num_0_fifo_in_ready), - .flush(flush), - .intersect_unit_inst_joiner_op(mem_ctrl_intersect_unit_flat_intersect_unit_inst_joiner_op), - .intersect_unit_inst_tile_en(mem_ctrl_intersect_unit_flat_intersect_unit_inst_tile_en), - .intersect_unit_inst_vector_reduce_mode(mem_ctrl_intersect_unit_flat_intersect_unit_inst_vector_reduce_mode), - .pos_in_0_f_(input_width_17_num_2_fifo_out), - .pos_in_0_valid_f_(input_width_17_num_2_fifo_out_valid), - .pos_in_1_f_(input_width_17_num_3_fifo_out), - .pos_in_1_valid_f_(input_width_17_num_3_fifo_out_valid), - .pos_out_0_ready_f_(output_width_17_num_1_fifo_in_ready), - .pos_out_1_ready_f_(output_width_17_num_2_fifo_in_ready), - .rst_n(rst_n), - .coord_in_0_ready_f_(mem_ctrl_intersect_unit_flat_coord_in_0_ready_f_), - .coord_in_1_ready_f_(mem_ctrl_intersect_unit_flat_coord_in_1_ready_f_), - .coord_out_f_(mem_ctrl_intersect_unit_flat_coord_out_f_), - .coord_out_valid_f_(mem_ctrl_intersect_unit_flat_coord_out_valid_f_), - .pos_in_0_ready_f_(mem_ctrl_intersect_unit_flat_pos_in_0_ready_f_), - .pos_in_1_ready_f_(mem_ctrl_intersect_unit_flat_pos_in_1_ready_f_), - .pos_out_0_f_(mem_ctrl_intersect_unit_flat_pos_out_0_f_), - .pos_out_0_valid_f_(mem_ctrl_intersect_unit_flat_pos_out_0_valid_f_), - .pos_out_1_f_(mem_ctrl_intersect_unit_flat_pos_out_1_f_), - .pos_out_1_valid_f_(mem_ctrl_intersect_unit_flat_pos_out_1_valid_f_) -); - -crddrop_flat mem_ctrl_crddrop_flat ( - .clk(mem_ctrl_crddrop_flat_clk), - .clk_en(clk_en), - .cmrg_coord_in_0_f_(input_width_17_num_0_fifo_out), - .cmrg_coord_in_0_valid_f_(input_width_17_num_0_fifo_out_valid), - .cmrg_coord_in_1_f_(input_width_17_num_1_fifo_out), - .cmrg_coord_in_1_valid_f_(input_width_17_num_1_fifo_out_valid), - .cmrg_coord_out_0_ready_f_(output_width_17_num_0_fifo_in_ready), - .cmrg_coord_out_1_ready_f_(output_width_17_num_1_fifo_in_ready), - .crddrop_inst_cmrg_enable(mem_ctrl_crddrop_flat_crddrop_inst_cmrg_enable), - .crddrop_inst_cmrg_mode(mem_ctrl_crddrop_flat_crddrop_inst_cmrg_mode), - .crddrop_inst_cmrg_stop_lvl(mem_ctrl_crddrop_flat_crddrop_inst_cmrg_stop_lvl), - .crddrop_inst_tile_en(mem_ctrl_crddrop_flat_crddrop_inst_tile_en), - .flush(flush), - .rst_n(rst_n), - .cmrg_coord_in_0_ready_f_(mem_ctrl_crddrop_flat_cmrg_coord_in_0_ready_f_), - .cmrg_coord_in_1_ready_f_(mem_ctrl_crddrop_flat_cmrg_coord_in_1_ready_f_), - .cmrg_coord_out_0_f_(mem_ctrl_crddrop_flat_cmrg_coord_out_0_f_), - .cmrg_coord_out_0_valid_f_(mem_ctrl_crddrop_flat_cmrg_coord_out_0_valid_f_), - .cmrg_coord_out_1_f_(mem_ctrl_crddrop_flat_cmrg_coord_out_1_f_), - .cmrg_coord_out_1_valid_f_(mem_ctrl_crddrop_flat_cmrg_coord_out_1_valid_f_) -); - -crdhold_flat mem_ctrl_crdhold_flat ( - .clk(mem_ctrl_crdhold_flat_clk), - .clk_en(clk_en), - .cmrg_coord_in_0_f_(input_width_17_num_0_fifo_out), - .cmrg_coord_in_0_valid_f_(input_width_17_num_0_fifo_out_valid), - .cmrg_coord_in_1_f_(input_width_17_num_1_fifo_out), - .cmrg_coord_in_1_valid_f_(input_width_17_num_1_fifo_out_valid), - .cmrg_coord_out_0_ready_f_(output_width_17_num_0_fifo_in_ready), - .cmrg_coord_out_1_ready_f_(output_width_17_num_1_fifo_in_ready), - .crdhold_inst_cmrg_enable(mem_ctrl_crdhold_flat_crdhold_inst_cmrg_enable), - .crdhold_inst_cmrg_stop_lvl(mem_ctrl_crdhold_flat_crdhold_inst_cmrg_stop_lvl), - .crdhold_inst_tile_en(mem_ctrl_crdhold_flat_crdhold_inst_tile_en), - .flush(flush), - .rst_n(rst_n), - .cmrg_coord_in_0_ready_f_(mem_ctrl_crdhold_flat_cmrg_coord_in_0_ready_f_), - .cmrg_coord_in_1_ready_f_(mem_ctrl_crdhold_flat_cmrg_coord_in_1_ready_f_), - .cmrg_coord_out_0_f_(mem_ctrl_crdhold_flat_cmrg_coord_out_0_f_), - .cmrg_coord_out_0_valid_f_(mem_ctrl_crdhold_flat_cmrg_coord_out_0_valid_f_), - .cmrg_coord_out_1_f_(mem_ctrl_crdhold_flat_cmrg_coord_out_1_f_), - .cmrg_coord_out_1_valid_f_(mem_ctrl_crdhold_flat_cmrg_coord_out_1_valid_f_) -); - -Repeat_flat mem_ctrl_Repeat_flat ( - .Repeat_inst_root(mem_ctrl_Repeat_flat_Repeat_inst_root), - .Repeat_inst_spacc_mode(mem_ctrl_Repeat_flat_Repeat_inst_spacc_mode), - .Repeat_inst_stop_lvl(mem_ctrl_Repeat_flat_Repeat_inst_stop_lvl), - .Repeat_inst_tile_en(mem_ctrl_Repeat_flat_Repeat_inst_tile_en), - .clk(mem_ctrl_Repeat_flat_clk), - .clk_en(clk_en), - .flush(flush), - .proc_data_in_f_(input_width_17_num_0_fifo_out), - .proc_data_in_valid_f_(input_width_17_num_0_fifo_out_valid), - .ref_data_out_ready_f_(output_width_17_num_0_fifo_in_ready), - .repsig_data_in_f_(input_width_17_num_1_fifo_out), - .repsig_data_in_valid_f_(input_width_17_num_1_fifo_out_valid), - .rst_n(rst_n), - .proc_data_in_ready_f_(mem_ctrl_Repeat_flat_proc_data_in_ready_f_), - .ref_data_out_f_(mem_ctrl_Repeat_flat_ref_data_out_f_), - .ref_data_out_valid_f_(mem_ctrl_Repeat_flat_ref_data_out_valid_f_), - .repsig_data_in_ready_f_(mem_ctrl_Repeat_flat_repsig_data_in_ready_f_) -); - -RepeatSignalGenerator_flat mem_ctrl_RepeatSignalGenerator_flat ( - .RepeatSignalGenerator_inst_stop_lvl(mem_ctrl_RepeatSignalGenerator_flat_RepeatSignalGenerator_inst_stop_lvl), - .RepeatSignalGenerator_inst_tile_en(mem_ctrl_RepeatSignalGenerator_flat_RepeatSignalGenerator_inst_tile_en), - .base_data_in_f_(input_width_17_num_0_fifo_out), - .base_data_in_valid_f_(input_width_17_num_0_fifo_out_valid), - .clk(mem_ctrl_RepeatSignalGenerator_flat_clk), - .clk_en(clk_en), - .flush(flush), - .repsig_data_out_ready_f_(output_width_17_num_0_fifo_in_ready), - .rst_n(rst_n), - .base_data_in_ready_f_(mem_ctrl_RepeatSignalGenerator_flat_base_data_in_ready_f_), - .repsig_data_out_f_(mem_ctrl_RepeatSignalGenerator_flat_repsig_data_out_f_), - .repsig_data_out_valid_f_(mem_ctrl_RepeatSignalGenerator_flat_repsig_data_out_valid_f_) -); - -reduce_pe_cluster_flat mem_ctrl_reduce_pe_cluster_flat ( - .bit0_f_(PE_input_width_1_num_0), - .bit1_f_(PE_input_width_1_num_1), - .bit2_f_(PE_input_width_1_num_2), - .clk(mem_ctrl_reduce_pe_cluster_flat_clk), - .clk_en(clk_en), - .data0_f_(mem_ctrl_reduce_pe_cluster_flat_data0_f_), - .data0_valid_f_(mem_ctrl_reduce_pe_cluster_flat_data0_valid_f_), - .data1_f_(mem_ctrl_reduce_pe_cluster_flat_data1_f_), - .data1_valid_f_(mem_ctrl_reduce_pe_cluster_flat_data1_valid_f_), - .data2_f_(mem_ctrl_reduce_pe_cluster_flat_data2_f_), - .data2_valid_f_(mem_ctrl_reduce_pe_cluster_flat_data2_valid_f_), - .flush(flush), - .reduce_data_in_f_(input_width_17_num_3_fifo_out), - .reduce_data_in_valid_f_(input_width_17_num_3_fifo_out_valid), - .reduce_data_out_ready_f_(output_width_17_num_0_fifo_in_ready), - .reduce_pe_cluster_inst_pe_dense_mode(mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_pe_dense_mode), - .reduce_pe_cluster_inst_pe_in_external(mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_pe_in_external), - .reduce_pe_cluster_inst_pe_onyxpeintf_inst(mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_pe_onyxpeintf_inst), - .reduce_pe_cluster_inst_pe_sparse_num_inputs(mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_pe_sparse_num_inputs), - .reduce_pe_cluster_inst_pe_tile_en(mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_pe_tile_en), - .reduce_pe_cluster_inst_reduce_default_value(mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_reduce_default_value), - .reduce_pe_cluster_inst_reduce_stop_lvl(mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_reduce_stop_lvl), - .reduce_pe_cluster_inst_reduce_tile_en(mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_reduce_tile_en), - .reduce_pe_cluster_inst_tile_en(mem_ctrl_reduce_pe_cluster_flat_reduce_pe_cluster_inst_tile_en), - .res_ready_f_(mem_ctrl_reduce_pe_cluster_flat_res_ready_f_), - .rst_n(rst_n), - .data0_ready_f_(mem_ctrl_reduce_pe_cluster_flat_data0_ready_f_), - .data1_ready_f_(mem_ctrl_reduce_pe_cluster_flat_data1_ready_f_), - .data2_ready_f_(mem_ctrl_reduce_pe_cluster_flat_data2_ready_f_), - .reduce_data_in_ready_f_(mem_ctrl_reduce_pe_cluster_flat_reduce_data_in_ready_f_), - .reduce_data_out_f_(mem_ctrl_reduce_pe_cluster_flat_reduce_data_out_f_), - .reduce_data_out_valid_f_(mem_ctrl_reduce_pe_cluster_flat_reduce_data_out_valid_f_), - .reduce_pe_cluster_inst_pe_onyxpeintf_O2(reduce_pe_cluster_inst_pe_onyxpeintf_O2), - .reduce_pe_cluster_inst_pe_onyxpeintf_O3(reduce_pe_cluster_inst_pe_onyxpeintf_O3), - .reduce_pe_cluster_inst_pe_onyxpeintf_O4(reduce_pe_cluster_inst_pe_onyxpeintf_O4), - .res_f_(mem_ctrl_reduce_pe_cluster_flat_res_f_), - .res_p_f_(mem_ctrl_reduce_pe_cluster_flat_res_p_f_), - .res_valid_f_(mem_ctrl_reduce_pe_cluster_flat_res_valid_f_) -); - -reg_fifo_depth_2_w_17_afd_2 input_width_17_num_0_input_fifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in(PE_input_width_17_num_0), - .flush(flush), - .pop(input_width_17_num_0_fifo_out_ready), - .push(PE_input_width_17_num_0_valid), - .rst_n(rst_n), - .data_out(input_width_17_num_0_fifo_out), - .empty(input_width_17_num_0_input_fifo_empty), - .full(input_width_17_num_0_input_fifo_full) -); - -reg_fifo_depth_2_w_17_afd_2 input_width_17_num_1_input_fifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in(PE_input_width_17_num_1), - .flush(flush), - .pop(input_width_17_num_1_fifo_out_ready), - .push(PE_input_width_17_num_1_valid), - .rst_n(rst_n), - .data_out(input_width_17_num_1_fifo_out), - .empty(input_width_17_num_1_input_fifo_empty), - .full(input_width_17_num_1_input_fifo_full) -); - -reg_fifo_depth_2_w_17_afd_2 input_width_17_num_2_input_fifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in(PE_input_width_17_num_2), - .flush(flush), - .pop(input_width_17_num_2_fifo_out_ready), - .push(PE_input_width_17_num_2_valid), - .rst_n(rst_n), - .data_out(input_width_17_num_2_fifo_out), - .empty(input_width_17_num_2_input_fifo_empty), - .full(input_width_17_num_2_input_fifo_full) -); - -reg_fifo_depth_2_w_17_afd_2 input_width_17_num_3_input_fifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in(PE_input_width_17_num_3), - .flush(flush), - .pop(input_width_17_num_3_fifo_out_ready), - .push(PE_input_width_17_num_3_valid), - .rst_n(rst_n), - .data_out(input_width_17_num_3_fifo_out), - .empty(input_width_17_num_3_input_fifo_empty), - .full(input_width_17_num_3_input_fifo_full) -); - -reg_fifo_depth_2_w_17_afd_2 output_width_17_num_0_output_fifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in(output_width_17_num_0_fifo_in), - .flush(flush), - .pop(PE_output_width_17_num_0_ready), - .push(output_width_17_num_0_fifo_in_valid), - .rst_n(rst_n), - .data_out(output_width_17_num_0_output_fifo_data_out), - .empty(output_width_17_num_0_output_fifo_empty), - .full(output_width_17_num_0_output_fifo_full) -); - -reg_fifo_depth_2_w_17_afd_2 output_width_17_num_1_output_fifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in(output_width_17_num_1_fifo_in), - .flush(flush), - .pop(PE_output_width_17_num_1_ready), - .push(output_width_17_num_1_fifo_in_valid), - .rst_n(rst_n), - .data_out(output_width_17_num_1_output_fifo_data_out), - .empty(output_width_17_num_1_output_fifo_empty), - .full(output_width_17_num_1_output_fifo_full) -); - -reg_fifo_depth_2_w_17_afd_2 output_width_17_num_2_output_fifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in(output_width_17_num_2_fifo_in), - .flush(flush), - .pop(PE_output_width_17_num_2_ready), - .push(output_width_17_num_2_fifo_in_valid), - .rst_n(rst_n), - .data_out(output_width_17_num_2_output_fifo_data_out), - .empty(output_width_17_num_2_output_fifo_empty), - .full(output_width_17_num_2_output_fifo_full) -); - -endmodule // PE_inner - -module PE_inner_W ( - input logic [31:0] CONFIG_SPACE_0, - input logic [31:0] CONFIG_SPACE_1, - input logic [31:0] CONFIG_SPACE_2, - input logic [27:0] CONFIG_SPACE_3, - input logic [0:0] [16:0] PE_input_width_17_num_0, - input logic PE_input_width_17_num_0_dense, - input logic PE_input_width_17_num_0_valid, - input logic [0:0] [16:0] PE_input_width_17_num_1, - input logic PE_input_width_17_num_1_dense, - input logic PE_input_width_17_num_1_valid, - input logic [0:0] [16:0] PE_input_width_17_num_2, - input logic PE_input_width_17_num_2_dense, - input logic PE_input_width_17_num_2_valid, - input logic [0:0] [16:0] PE_input_width_17_num_3, - input logic PE_input_width_17_num_3_valid, - input logic PE_input_width_1_num_0, - input logic PE_input_width_1_num_1, - input logic PE_input_width_1_num_2, - input logic PE_output_width_17_num_0_ready, - input logic PE_output_width_17_num_1_dense, - input logic PE_output_width_17_num_1_ready, - input logic PE_output_width_17_num_2_ready, - input logic clk, - input logic clk_en, - input logic flush, - input logic [2:0] mode, - input logic rst_n, - input logic tile_en, - output logic PE_input_width_17_num_0_ready, - output logic PE_input_width_17_num_1_ready, - output logic PE_input_width_17_num_2_ready, - output logic PE_input_width_17_num_3_ready, - output logic [0:0] [16:0] PE_output_width_17_num_0, - output logic PE_output_width_17_num_0_valid, - output logic [0:0] [16:0] PE_output_width_17_num_1, - output logic PE_output_width_17_num_1_valid, - output logic [0:0] [16:0] PE_output_width_17_num_2, - output logic PE_output_width_17_num_2_valid, - output logic PE_output_width_1_num_0, - output logic [15:0] reduce_pe_cluster_inst_pe_onyxpeintf_O2, - output logic [15:0] reduce_pe_cluster_inst_pe_onyxpeintf_O3, - output logic [15:0] reduce_pe_cluster_inst_pe_onyxpeintf_O4 -); - -PE_inner PE_inner ( - .CONFIG_SPACE_0(CONFIG_SPACE_0), - .CONFIG_SPACE_1(CONFIG_SPACE_1), - .CONFIG_SPACE_2(CONFIG_SPACE_2), - .CONFIG_SPACE_3(CONFIG_SPACE_3), - .PE_input_width_17_num_0(PE_input_width_17_num_0), - .PE_input_width_17_num_0_dense(PE_input_width_17_num_0_dense), - .PE_input_width_17_num_0_valid(PE_input_width_17_num_0_valid), - .PE_input_width_17_num_1(PE_input_width_17_num_1), - .PE_input_width_17_num_1_dense(PE_input_width_17_num_1_dense), - .PE_input_width_17_num_1_valid(PE_input_width_17_num_1_valid), - .PE_input_width_17_num_2(PE_input_width_17_num_2), - .PE_input_width_17_num_2_dense(PE_input_width_17_num_2_dense), - .PE_input_width_17_num_2_valid(PE_input_width_17_num_2_valid), - .PE_input_width_17_num_3(PE_input_width_17_num_3), - .PE_input_width_17_num_3_valid(PE_input_width_17_num_3_valid), - .PE_input_width_1_num_0(PE_input_width_1_num_0), - .PE_input_width_1_num_1(PE_input_width_1_num_1), - .PE_input_width_1_num_2(PE_input_width_1_num_2), - .PE_output_width_17_num_0_ready(PE_output_width_17_num_0_ready), - .PE_output_width_17_num_1_dense(PE_output_width_17_num_1_dense), - .PE_output_width_17_num_1_ready(PE_output_width_17_num_1_ready), - .PE_output_width_17_num_2_ready(PE_output_width_17_num_2_ready), - .clk(clk), - .clk_en(clk_en), - .flush(flush), - .mode(mode), - .rst_n(rst_n), - .tile_en(tile_en), - .PE_input_width_17_num_0_ready(PE_input_width_17_num_0_ready), - .PE_input_width_17_num_1_ready(PE_input_width_17_num_1_ready), - .PE_input_width_17_num_2_ready(PE_input_width_17_num_2_ready), - .PE_input_width_17_num_3_ready(PE_input_width_17_num_3_ready), - .PE_output_width_17_num_0(PE_output_width_17_num_0), - .PE_output_width_17_num_0_valid(PE_output_width_17_num_0_valid), - .PE_output_width_17_num_1(PE_output_width_17_num_1), - .PE_output_width_17_num_1_valid(PE_output_width_17_num_1_valid), - .PE_output_width_17_num_2(PE_output_width_17_num_2), - .PE_output_width_17_num_2_valid(PE_output_width_17_num_2_valid), - .PE_output_width_1_num_0(PE_output_width_1_num_0), - .reduce_pe_cluster_inst_pe_onyxpeintf_O2(reduce_pe_cluster_inst_pe_onyxpeintf_O2), - .reduce_pe_cluster_inst_pe_onyxpeintf_O3(reduce_pe_cluster_inst_pe_onyxpeintf_O3), - .reduce_pe_cluster_inst_pe_onyxpeintf_O4(reduce_pe_cluster_inst_pe_onyxpeintf_O4) -); - -endmodule // PE_inner_W - -module PE_onyx ( - input logic bit0, - input logic bit1, - input logic bit2, - input logic clk, - input logic clk_en, - input logic [16:0] data0, - input logic data0_valid, - input logic [16:0] data1, - input logic data1_valid, - input logic [16:0] data2, - input logic data2_valid, - input logic dense_mode, - input logic flush, - input logic [83:0] onyxpeintf_inst, - input logic res_ready, - input logic rst_n, - input logic [2:0] sparse_num_inputs, - input logic tile_en, - output logic data0_ready, - output logic data1_ready, - output logic data2_ready, - output logic [15:0] onyxpeintf_O2, - output logic [15:0] onyxpeintf_O3, - output logic [15:0] onyxpeintf_O4, - output logic [16:0] res, - output logic res_p, - output logic res_valid -); - -logic [15:0] data_to_fifo; -logic gclk; -logic [2:0][16:0] infifo_in_packed; -logic [2:0][15:0] infifo_out_data; -logic [2:0] infifo_out_eos; -logic infifo_out_maybe_0; -logic infifo_out_maybe_1; -logic infifo_out_maybe_2; -logic [2:0][16:0] infifo_out_packed; -logic [2:0] infifo_out_valid; -logic [2:0] infifo_pop; -logic infifo_push_0; -logic infifo_push_1; -logic infifo_push_2; -logic [0:0][16:0] input_fifo_0_data_out; -logic input_fifo_0_empty; -logic input_fifo_0_full; -logic [0:0][16:0] input_fifo_1_data_out; -logic input_fifo_1_empty; -logic input_fifo_1_full; -logic [0:0][16:0] input_fifo_2_data_out; -logic input_fifo_2_empty; -logic input_fifo_2_full; -logic onyxpeintf_ASYNCRESET; -logic [15:0] onyxpeintf_data0; -logic [15:0] onyxpeintf_data1; -logic [15:0] onyxpeintf_data2; -logic outfifo_full; -logic outfifo_in_eos; -logic [16:0] outfifo_in_packed; -logic [16:0] outfifo_out_packed; -logic outfifo_pop; -logic outfifo_push; -logic output_fifo_empty; -logic [15:0] pe_output; -assign gclk = clk & tile_en; -assign data0_ready = dense_mode ? 1'h1: ~input_fifo_0_full; -assign data1_ready = dense_mode ? 1'h1: ~input_fifo_1_full; -assign data2_ready = dense_mode ? 1'h1: ~input_fifo_2_full; -assign infifo_in_packed[0] = data0; -assign infifo_out_eos[0] = infifo_out_packed[0][16]; -assign infifo_out_data[0] = infifo_out_packed[0][15:0]; -assign infifo_in_packed[1] = data1; -assign infifo_out_eos[1] = infifo_out_packed[1][16]; -assign infifo_out_data[1] = infifo_out_packed[1][15:0]; -assign infifo_in_packed[2] = data2; -assign infifo_out_eos[2] = infifo_out_packed[2][16]; -assign infifo_out_data[2] = infifo_out_packed[2][15:0]; -assign infifo_push_0 = data0_valid; -assign infifo_push_1 = data1_valid; -assign infifo_push_2 = data2_valid; -assign infifo_out_packed[0] = input_fifo_0_data_out; -assign infifo_out_packed[1] = input_fifo_1_data_out; -assign infifo_out_packed[2] = input_fifo_2_data_out; -assign infifo_out_valid[0] = ~input_fifo_0_empty; -assign infifo_out_valid[1] = ~input_fifo_1_empty; -assign infifo_out_valid[2] = ~input_fifo_2_empty; -assign outfifo_in_packed[16] = outfifo_in_eos; -assign outfifo_in_packed[15:0] = data_to_fifo; -assign res = dense_mode ? 17'(pe_output): outfifo_out_packed; -assign res_valid = dense_mode ? 1'h1: ~output_fifo_empty; -assign outfifo_pop = res_ready; -assign infifo_out_maybe_0 = infifo_out_eos[0] & infifo_out_valid[0] & (infifo_out_data[0][9:8] == 2'h2); -assign infifo_out_maybe_1 = infifo_out_eos[1] & infifo_out_valid[1] & (infifo_out_data[1][9:8] == 2'h2); -assign infifo_out_maybe_2 = infifo_out_eos[2] & infifo_out_valid[2] & (infifo_out_data[2][9:8] == 2'h2); -assign onyxpeintf_ASYNCRESET = ~rst_n; -assign onyxpeintf_data0 = dense_mode ? data0[15:0]: infifo_out_maybe_0 ? 16'h0: infifo_out_data[0]; -assign onyxpeintf_data1 = dense_mode ? data1[15:0]: infifo_out_maybe_1 ? 16'h0: infifo_out_data[1]; -assign onyxpeintf_data2 = dense_mode ? data2[15:0]: infifo_out_maybe_2 ? 16'h0: infifo_out_data[2]; -always_comb begin - outfifo_push = 1'h0; - outfifo_in_eos = 1'h0; - data_to_fifo = 16'h0; - infifo_pop[0] = 1'h0; - infifo_pop[1] = 1'h0; - infifo_pop[2] = 1'h0; - if (((infifo_out_valid & sparse_num_inputs) == sparse_num_inputs) & (~outfifo_full) & (~dense_mode)) begin - if (~((infifo_out_eos & sparse_num_inputs) == sparse_num_inputs)) begin - outfifo_push = 1'h1; - outfifo_in_eos = 1'h0; - data_to_fifo = pe_output; - infifo_pop[0] = infifo_out_valid[0] & sparse_num_inputs[0]; - infifo_pop[1] = infifo_out_valid[1] & sparse_num_inputs[1]; - infifo_pop[2] = infifo_out_valid[2] & sparse_num_inputs[2]; - end - else begin - outfifo_push = 1'h1; - outfifo_in_eos = 1'h1; - data_to_fifo = sparse_num_inputs[0] ? infifo_out_data[0]: sparse_num_inputs[1] ? - infifo_out_data[1]: infifo_out_data[2]; - infifo_pop[0] = infifo_out_valid[0] & sparse_num_inputs[0]; - infifo_pop[1] = infifo_out_valid[1] & sparse_num_inputs[1]; - infifo_pop[2] = infifo_out_valid[2] & sparse_num_inputs[2]; - end - end -end -reg_fifo_depth_0_w_17_afd_2 input_fifo_0 ( - .clk(gclk), - .clk_en(clk_en), - .data_in(infifo_in_packed[0]), - .flush(flush), - .pop(infifo_pop[0]), - .push(infifo_push_0), - .rst_n(rst_n), - .data_out(input_fifo_0_data_out), - .empty(input_fifo_0_empty), - .full(input_fifo_0_full) -); - -reg_fifo_depth_0_w_17_afd_2 input_fifo_1 ( - .clk(gclk), - .clk_en(clk_en), - .data_in(infifo_in_packed[1]), - .flush(flush), - .pop(infifo_pop[1]), - .push(infifo_push_1), - .rst_n(rst_n), - .data_out(input_fifo_1_data_out), - .empty(input_fifo_1_empty), - .full(input_fifo_1_full) -); - -reg_fifo_depth_0_w_17_afd_2 input_fifo_2 ( - .clk(gclk), - .clk_en(clk_en), - .data_in(infifo_in_packed[2]), - .flush(flush), - .pop(infifo_pop[2]), - .push(infifo_push_2), - .rst_n(rst_n), - .data_out(input_fifo_2_data_out), - .empty(input_fifo_2_empty), - .full(input_fifo_2_full) -); - -reg_fifo_depth_2_w_17_afd_2 output_fifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in(outfifo_in_packed), - .flush(flush), - .pop(outfifo_pop), - .push(outfifo_push), - .rst_n(rst_n), - .data_out(outfifo_out_packed), - .empty(output_fifo_empty), - .full(outfifo_full) -); - -PEGEN_PE onyxpeintf ( - .ASYNCRESET(onyxpeintf_ASYNCRESET), - .CLK(gclk), - .bit0(bit0), - .bit1(bit1), - .bit2(bit2), - .clk_en(clk_en), - .data0(onyxpeintf_data0), - .data1(onyxpeintf_data1), - .data2(onyxpeintf_data2), - .inst(onyxpeintf_inst), - .O0(pe_output), - .O1(res_p), - .O2(onyxpeintf_O2), - .O3(onyxpeintf_O3), - .O4(onyxpeintf_O4) -); - -endmodule // PE_onyx - -module Repeat ( - input logic clk, - input logic clk_en, - input logic flush, - input logic [16:0] proc_data_in, - input logic proc_data_in_valid, - input logic ref_data_out_ready, - input logic [16:0] repsig_data_in, - input logic repsig_data_in_valid, - input logic root, - input logic rst_n, - input logic spacc_mode, - input logic [15:0] stop_lvl, - input logic tile_en, - output logic proc_data_in_ready, - output logic [16:0] ref_data_out, - output logic ref_data_out_valid, - output logic repsig_data_in_ready -); - -typedef enum logic[1:0] { - INJECT0 = 2'h0, - INJECT1 = 2'h1, - PASS_REPEAT = 2'h2, - START = 2'h3 -} repeat_fsm_state; -logic blank_repeat; -logic blank_repeat_stop; -logic clr_last_pushed_data; -logic gclk; -logic proc_data; -logic proc_done; -logic proc_fifo_full; -logic [15:0] proc_fifo_inject_data; -logic proc_fifo_inject_eos; -logic proc_fifo_inject_push; -logic [15:0] proc_fifo_out_data; -logic proc_fifo_out_eos; -logic proc_fifo_pop; -logic proc_fifo_push; -logic proc_fifo_valid; -logic [0:0][16:0] proc_in_fifo_data_in; -logic [0:0][16:0] proc_in_fifo_data_out; -logic proc_in_fifo_empty; -logic proc_in_fifo_full; -logic proc_stop; -logic pushed_data_sticky_sticky; -logic pushed_data_sticky_was_high; -logic ref_fifo_full; -logic [15:0] ref_fifo_in_data; -logic ref_fifo_in_eos; -logic ref_fifo_push; -logic ref_maybe; -logic [0:0][16:0] ref_out_fifo_data_in; -logic ref_out_fifo_empty; -repeat_fsm_state repeat_fsm_current_state; -repeat_fsm_state repeat_fsm_next_state; -logic repsig_done; -logic [15:0] repsig_fifo_out_data; -logic repsig_fifo_out_eos; -logic repsig_fifo_pop; -logic repsig_fifo_valid; -logic [0:0][16:0] repsig_in_fifo_data_out; -logic repsig_in_fifo_empty; -logic repsig_in_fifo_full; -logic repsig_sig; -logic repsig_stop; -logic seen_root_eos_sticky; -logic seen_root_eos_was_high; -logic set_last_pushed_data; -assign gclk = clk & tile_en; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - pushed_data_sticky_was_high <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - pushed_data_sticky_was_high <= 1'h0; - end - else if (clr_last_pushed_data) begin - pushed_data_sticky_was_high <= 1'h0; - end - else if (set_last_pushed_data) begin - pushed_data_sticky_was_high <= 1'h1; - end - end -end -assign pushed_data_sticky_sticky = pushed_data_sticky_was_high; -assign {repsig_fifo_out_eos, repsig_fifo_out_data} = repsig_in_fifo_data_out; -assign repsig_data_in_ready = ~repsig_in_fifo_full; -assign repsig_fifo_valid = ~repsig_in_fifo_empty; -assign proc_fifo_push = root ? proc_fifo_inject_push: proc_data_in_valid; -assign proc_in_fifo_data_in = root ? {proc_fifo_inject_eos, proc_fifo_inject_data}: proc_data_in; -assign {proc_fifo_out_eos, proc_fifo_out_data} = proc_in_fifo_data_out; -assign proc_data_in_ready = ~proc_in_fifo_full; -assign proc_fifo_full = proc_in_fifo_full; -assign proc_fifo_valid = ~proc_in_fifo_empty; -assign ref_out_fifo_data_in = {ref_fifo_in_eos, ref_fifo_in_data}; -assign ref_data_out_valid = ~ref_out_fifo_empty; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - seen_root_eos_was_high <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - seen_root_eos_was_high <= 1'h0; - end - else if (1'h0) begin - seen_root_eos_was_high <= 1'h0; - end - else if ((proc_fifo_out_data == 16'h0) & proc_fifo_out_eos & proc_fifo_valid) begin - seen_root_eos_was_high <= 1'h1; - end - end -end -assign seen_root_eos_sticky = ((proc_fifo_out_data == 16'h0) & proc_fifo_out_eos & proc_fifo_valid) | - seen_root_eos_was_high; -assign ref_maybe = proc_fifo_valid & proc_fifo_out_eos & (proc_fifo_out_data[9:8] == 2'h2); -assign proc_data = ((~proc_fifo_out_eos) | ref_maybe) & proc_fifo_valid; -assign proc_stop = (proc_fifo_out_data[9:8] == 2'h0) & proc_fifo_out_eos & proc_fifo_valid; -assign proc_done = (proc_fifo_out_data[9:8] == 2'h1) & proc_fifo_out_eos & proc_fifo_valid; -assign repsig_stop = (repsig_fifo_out_data[9:8] == 2'h0) & repsig_fifo_out_eos & repsig_fifo_valid; -assign repsig_sig = (~repsig_fifo_out_eos) & repsig_fifo_valid; -assign repsig_done = (repsig_fifo_out_data[9:8] == 2'h1) & repsig_fifo_out_eos & repsig_fifo_valid; -assign blank_repeat = proc_stop & (~repsig_stop) & repsig_fifo_valid; -assign blank_repeat_stop = proc_stop & repsig_stop & pushed_data_sticky_sticky; - -always_ff @(posedge clk, negedge rst_n) begin - if (!rst_n) begin - repeat_fsm_current_state <= START; - end - else if (clk_en) begin - if (flush) begin - repeat_fsm_current_state <= START; - end - else repeat_fsm_current_state <= repeat_fsm_next_state; - end -end -always_comb begin - repeat_fsm_next_state = repeat_fsm_current_state; - unique case (repeat_fsm_current_state) - INJECT0: begin - if (~proc_fifo_full) begin - repeat_fsm_next_state = INJECT1; - end - else repeat_fsm_next_state = INJECT0; - end - INJECT1: begin - if (~proc_fifo_full) begin - repeat_fsm_next_state = PASS_REPEAT; - end - else repeat_fsm_next_state = INJECT1; - end - PASS_REPEAT: begin - if (proc_done & repsig_done & (~ref_fifo_full)) begin - repeat_fsm_next_state = START; - end - else repeat_fsm_next_state = PASS_REPEAT; - end - START: begin - if (root & tile_en) begin - repeat_fsm_next_state = INJECT0; - end - else if ((~root) & tile_en) begin - repeat_fsm_next_state = PASS_REPEAT; - end - else repeat_fsm_next_state = START; - end - default: begin end - endcase -end -always_comb begin - unique case (repeat_fsm_current_state) - INJECT0: begin :repeat_fsm_INJECT0_Output - ref_fifo_in_data = 16'h0; - ref_fifo_in_eos = 1'h0; - ref_fifo_push = 1'h0; - proc_fifo_pop = 1'h0; - repsig_fifo_pop = 1'h0; - proc_fifo_inject_push = 1'h1; - proc_fifo_inject_data = 16'h0; - proc_fifo_inject_eos = 1'h0; - set_last_pushed_data = 1'h0; - clr_last_pushed_data = 1'h0; - end :repeat_fsm_INJECT0_Output - INJECT1: begin :repeat_fsm_INJECT1_Output - ref_fifo_in_data = 16'h0; - ref_fifo_in_eos = 1'h0; - ref_fifo_push = 1'h0; - proc_fifo_pop = 1'h0; - repsig_fifo_pop = 1'h0; - proc_fifo_inject_push = 1'h1; - proc_fifo_inject_data = 16'h100; - proc_fifo_inject_eos = 1'h1; - set_last_pushed_data = 1'h0; - clr_last_pushed_data = 1'h0; - end :repeat_fsm_INJECT1_Output - PASS_REPEAT: begin :repeat_fsm_PASS_REPEAT_Output - ref_fifo_in_data = repsig_stop ? repsig_fifo_out_data: proc_fifo_out_data; - ref_fifo_in_eos = ref_maybe | repsig_done | repsig_stop; - ref_fifo_push = (~ref_fifo_full) & ((proc_done & repsig_done) | (proc_data & repsig_fifo_valid) - | (proc_stop & (~pushed_data_sticky_sticky) & repsig_stop)); - proc_fifo_pop = proc_done ? repsig_done & (~ref_fifo_full): proc_stop ? - pushed_data_sticky_sticky | (repsig_stop & (~ref_fifo_full) & - (~pushed_data_sticky_sticky)): repsig_stop & (~ref_fifo_full); - repsig_fifo_pop = repsig_done ? proc_done & (~ref_fifo_full): repsig_stop ? (proc_data | - (proc_stop & (~pushed_data_sticky_sticky))) & (~ref_fifo_full): (proc_data & - (~ref_fifo_full)) | (proc_stop & (~pushed_data_sticky_sticky)); - proc_fifo_inject_push = 1'h0; - proc_fifo_inject_data = 16'h0; - proc_fifo_inject_eos = 1'h0; - set_last_pushed_data = proc_data; - clr_last_pushed_data = proc_stop | (proc_done & repsig_done & (~ref_fifo_full)); - end :repeat_fsm_PASS_REPEAT_Output - START: begin :repeat_fsm_START_Output - ref_fifo_in_data = 16'h0; - ref_fifo_in_eos = 1'h0; - ref_fifo_push = 1'h0; - proc_fifo_pop = 1'h0; - repsig_fifo_pop = 1'h0; - proc_fifo_inject_push = 1'h0; - proc_fifo_inject_data = 16'h0; - proc_fifo_inject_eos = 1'h0; - set_last_pushed_data = 1'h0; - clr_last_pushed_data = 1'h0; - end :repeat_fsm_START_Output - default: begin end - endcase -end -reg_fifo_depth_0_w_17_afd_2 repsig_in_fifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in(repsig_data_in), - .flush(flush), - .pop(repsig_fifo_pop), - .push(repsig_data_in_valid), - .rst_n(rst_n), - .data_out(repsig_in_fifo_data_out), - .empty(repsig_in_fifo_empty), - .full(repsig_in_fifo_full) -); - -reg_fifo_depth_2_w_17_afd_2 proc_in_fifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in(proc_in_fifo_data_in), - .flush(flush), - .pop(proc_fifo_pop), - .push(proc_fifo_push), - .rst_n(rst_n), - .data_out(proc_in_fifo_data_out), - .empty(proc_in_fifo_empty), - .full(proc_in_fifo_full) -); - -reg_fifo_depth_0_w_17_afd_2 ref_out_fifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in(ref_out_fifo_data_in), - .flush(flush), - .pop(ref_data_out_ready), - .push(ref_fifo_push), - .rst_n(rst_n), - .data_out(ref_data_out), - .empty(ref_out_fifo_empty), - .full(ref_fifo_full) -); - -endmodule // Repeat - -module RepeatSignalGenerator ( - input logic [16:0] base_data_in, - input logic base_data_in_valid, - input logic clk, - input logic clk_en, - input logic flush, - input logic repsig_data_out_ready, - input logic rst_n, - input logic [15:0] stop_lvl, - input logic tile_en, - output logic base_data_in_ready, - output logic [16:0] repsig_data_out, - output logic repsig_data_out_valid -); - -typedef enum logic[1:0] { - DONE = 2'h0, - PASS_REPEAT = 2'h1, - PASS_STOP = 2'h2, - START = 2'h3 -} rsg_fsm_state; -logic already_pushed_repsig_eos_sticky; -logic already_pushed_repsig_eos_was_high; -logic [15:0] base_fifo_out_data; -logic base_fifo_out_eos; -logic base_fifo_pop; -logic base_fifo_valid; -logic [0:0][16:0] base_in_fifo_data_out; -logic base_in_fifo_empty; -logic base_in_fifo_full; -logic clr_already_pushed_repsig_eos; -logic gclk; -logic repsig_fifo_full; -logic [15:0] repsig_fifo_in_data; -logic repsig_fifo_in_eos; -logic repsig_fifo_push; -logic [0:0][16:0] repsig_out_fifo_data_in; -logic repsig_out_fifo_empty; -rsg_fsm_state rsg_fsm_current_state; -rsg_fsm_state rsg_fsm_next_state; -logic seen_root_eos_sticky; -logic seen_root_eos_was_high; -assign gclk = clk & tile_en; -assign {base_fifo_out_eos, base_fifo_out_data} = base_in_fifo_data_out; -assign base_data_in_ready = ~base_in_fifo_full; -assign base_fifo_valid = ~base_in_fifo_empty; -assign repsig_out_fifo_data_in = {repsig_fifo_in_eos, repsig_fifo_in_data}; -assign repsig_data_out_valid = ~repsig_out_fifo_empty; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - seen_root_eos_was_high <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - seen_root_eos_was_high <= 1'h0; - end - else if (1'h0) begin - seen_root_eos_was_high <= 1'h0; - end - else if ((base_fifo_out_data[9:8] == 2'h1) & base_fifo_out_eos & base_fifo_valid) begin - seen_root_eos_was_high <= 1'h1; - end - end -end -assign seen_root_eos_sticky = ((base_fifo_out_data[9:8] == 2'h1) & base_fifo_out_eos & base_fifo_valid) | - seen_root_eos_was_high; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - already_pushed_repsig_eos_was_high <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - already_pushed_repsig_eos_was_high <= 1'h0; - end - else if (clr_already_pushed_repsig_eos) begin - already_pushed_repsig_eos_was_high <= 1'h0; - end - else if (repsig_fifo_push & (~repsig_fifo_full)) begin - already_pushed_repsig_eos_was_high <= 1'h1; - end - end -end -assign already_pushed_repsig_eos_sticky = already_pushed_repsig_eos_was_high; - -always_ff @(posedge clk, negedge rst_n) begin - if (!rst_n) begin - rsg_fsm_current_state <= START; - end - else if (clk_en) begin - if (flush) begin - rsg_fsm_current_state <= START; - end - else rsg_fsm_current_state <= rsg_fsm_next_state; - end -end -always_comb begin - rsg_fsm_next_state = rsg_fsm_current_state; - unique case (rsg_fsm_current_state) - DONE: rsg_fsm_next_state = START; - PASS_REPEAT: begin - if (base_fifo_out_eos & base_fifo_valid) begin - rsg_fsm_next_state = PASS_STOP; - end - else rsg_fsm_next_state = PASS_REPEAT; - end - PASS_STOP: begin - if (base_fifo_valid & base_fifo_out_eos & (base_fifo_out_data[9:8] == 2'h1) & (~repsig_fifo_full)) begin - rsg_fsm_next_state = DONE; - end - else if (base_fifo_valid & (~base_fifo_out_eos)) begin - rsg_fsm_next_state = PASS_REPEAT; - end - else rsg_fsm_next_state = PASS_STOP; - end - START: begin - if (tile_en) begin - rsg_fsm_next_state = PASS_REPEAT; - end - else rsg_fsm_next_state = START; - end - default: begin end - endcase -end -always_comb begin - unique case (rsg_fsm_current_state) - DONE: begin :rsg_fsm_DONE_Output - repsig_fifo_in_data = 16'h0; - repsig_fifo_in_eos = 1'h0; - repsig_fifo_push = 1'h0; - base_fifo_pop = 1'h0; - clr_already_pushed_repsig_eos = 1'h0; - end :rsg_fsm_DONE_Output - PASS_REPEAT: begin :rsg_fsm_PASS_REPEAT_Output - repsig_fifo_in_data = 16'h1; - repsig_fifo_in_eos = 1'h0; - repsig_fifo_push = (~base_fifo_out_eos) & base_fifo_valid; - clr_already_pushed_repsig_eos = 1'h1; - base_fifo_pop = (~base_fifo_out_eos) & base_fifo_valid & (~repsig_fifo_full); - end :rsg_fsm_PASS_REPEAT_Output - PASS_STOP: begin :rsg_fsm_PASS_STOP_Output - repsig_fifo_in_data = (base_fifo_out_data[9:8] == 2'h1) ? base_fifo_out_data: base_fifo_out_data; - repsig_fifo_in_eos = 1'h1; - repsig_fifo_push = base_fifo_out_eos & base_fifo_valid; - clr_already_pushed_repsig_eos = 1'h0; - base_fifo_pop = base_fifo_out_eos & base_fifo_valid & (~repsig_fifo_full); - end :rsg_fsm_PASS_STOP_Output - START: begin :rsg_fsm_START_Output - repsig_fifo_in_data = 16'h0; - repsig_fifo_in_eos = 1'h0; - repsig_fifo_push = 1'h0; - base_fifo_pop = 1'h0; - clr_already_pushed_repsig_eos = 1'h0; - end :rsg_fsm_START_Output - default: begin end - endcase -end -reg_fifo_depth_0_w_17_afd_2 base_in_fifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in(base_data_in), - .flush(flush), - .pop(base_fifo_pop), - .push(base_data_in_valid), - .rst_n(rst_n), - .data_out(base_in_fifo_data_out), - .empty(base_in_fifo_empty), - .full(base_in_fifo_full) -); - -reg_fifo_depth_0_w_17_afd_2 repsig_out_fifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in(repsig_out_fifo_data_in), - .flush(flush), - .pop(repsig_data_out_ready), - .push(repsig_fifo_push), - .rst_n(rst_n), - .data_out(repsig_data_out), - .empty(repsig_out_fifo_empty), - .full(repsig_fifo_full) -); - -endmodule // RepeatSignalGenerator - -module RepeatSignalGenerator_flat ( - input logic [15:0] RepeatSignalGenerator_inst_stop_lvl, - input logic RepeatSignalGenerator_inst_tile_en, - input logic [0:0] [16:0] base_data_in_f_, - input logic base_data_in_valid_f_, - input logic clk, - input logic clk_en, - input logic flush, - input logic repsig_data_out_ready_f_, - input logic rst_n, - output logic base_data_in_ready_f_, - output logic [0:0] [16:0] repsig_data_out_f_, - output logic repsig_data_out_valid_f_ -); - -RepeatSignalGenerator RepeatSignalGenerator_inst ( - .base_data_in(base_data_in_f_), - .base_data_in_valid(base_data_in_valid_f_), - .clk(clk), - .clk_en(clk_en), - .flush(flush), - .repsig_data_out_ready(repsig_data_out_ready_f_), - .rst_n(rst_n), - .stop_lvl(RepeatSignalGenerator_inst_stop_lvl), - .tile_en(RepeatSignalGenerator_inst_tile_en), - .base_data_in_ready(base_data_in_ready_f_), - .repsig_data_out(repsig_data_out_f_), - .repsig_data_out_valid(repsig_data_out_valid_f_) -); - -endmodule // RepeatSignalGenerator_flat - -module Repeat_flat ( - input logic Repeat_inst_root, - input logic Repeat_inst_spacc_mode, - input logic [15:0] Repeat_inst_stop_lvl, - input logic Repeat_inst_tile_en, - input logic clk, - input logic clk_en, - input logic flush, - input logic [0:0] [16:0] proc_data_in_f_, - input logic proc_data_in_valid_f_, - input logic ref_data_out_ready_f_, - input logic [0:0] [16:0] repsig_data_in_f_, - input logic repsig_data_in_valid_f_, - input logic rst_n, - output logic proc_data_in_ready_f_, - output logic [0:0] [16:0] ref_data_out_f_, - output logic ref_data_out_valid_f_, - output logic repsig_data_in_ready_f_ -); - -Repeat Repeat_inst ( - .clk(clk), - .clk_en(clk_en), - .flush(flush), - .proc_data_in(proc_data_in_f_), - .proc_data_in_valid(proc_data_in_valid_f_), - .ref_data_out_ready(ref_data_out_ready_f_), - .repsig_data_in(repsig_data_in_f_), - .repsig_data_in_valid(repsig_data_in_valid_f_), - .root(Repeat_inst_root), - .rst_n(rst_n), - .spacc_mode(Repeat_inst_spacc_mode), - .stop_lvl(Repeat_inst_stop_lvl), - .tile_en(Repeat_inst_tile_en), - .proc_data_in_ready(proc_data_in_ready_f_), - .ref_data_out(ref_data_out_f_), - .ref_data_out_valid(ref_data_out_valid_f_), - .repsig_data_in_ready(repsig_data_in_ready_f_) -); - -endmodule // Repeat_flat - -module crddrop ( - input logic clk, - input logic clk_en, - input logic [16:0] cmrg_coord_in_0, - input logic cmrg_coord_in_0_valid, - input logic [16:0] cmrg_coord_in_1, - input logic cmrg_coord_in_1_valid, - input logic cmrg_coord_out_0_ready, - input logic cmrg_coord_out_1_ready, - input logic cmrg_enable, - input logic cmrg_mode, - input logic [15:0] cmrg_stop_lvl, - input logic flush, - input logic rst_n, - input logic tile_en, - output logic cmrg_coord_in_0_ready, - output logic cmrg_coord_in_1_ready, - output logic [16:0] cmrg_coord_out_0, - output logic cmrg_coord_out_0_valid, - output logic [16:0] cmrg_coord_out_1, - output logic cmrg_coord_out_1_valid -); - -typedef enum logic[1:0] { - DROPZERO = 2'h0, - PROCESS = 2'h1, - START = 2'h2 -} proc_seq_state; -logic base_data_seen; -logic [16:0] base_delay; -logic base_done; -logic base_done_seen; -logic base_eos_seen; -logic base_infifo_empty; -logic base_infifo_full; -logic [15:0] base_infifo_in_data; -logic base_infifo_in_eos; -logic [16:0] base_infifo_in_packed; -logic base_infifo_in_valid; -logic [16:0] base_infifo_out_packed; -logic base_infifo_true_pop; -logic base_outfifo_empty; -logic base_outfifo_full; -logic [16:0] base_outfifo_in_packed; -logic base_outfifo_in_ready; -logic [16:0] base_outfifo_out_packed; -logic base_valid_delay; -logic both_done; -logic clr_pushed_data_lower; -logic clr_pushed_proc; -logic clr_pushed_stop_lvl; -logic cmrg_base_fifo_pop; -logic cmrg_base_fifo_push; -logic cmrg_coord_in_0_eos; -logic cmrg_coord_in_1_eos; -logic [1:0] cmrg_fifo_pop; -logic [1:0] cmrg_fifo_push; -logic cmrg_proc_fifo_pop; -logic cmrg_proc_fifo_push; -logic delay_data; -logic delay_done; -logic delay_eos; -logic delay_stop; -logic gclk; -logic proc_data_seen; -logic proc_done; -logic proc_infifo_empty; -logic proc_infifo_full; -logic [15:0] proc_infifo_in_data; -logic proc_infifo_in_eos; -logic [16:0] proc_infifo_in_packed; -logic proc_infifo_in_valid; -logic [16:0] proc_infifo_out_packed; -logic proc_outfifo_empty; -logic proc_outfifo_full; -logic [16:0] proc_outfifo_in_packed; -logic proc_outfifo_in_ready; -logic [16:0] proc_outfifo_out_packed; -proc_seq_state proc_seq_current_state; -proc_seq_state proc_seq_next_state; -logic pushed_data_sticky_sticky; -logic pushed_data_sticky_was_high; -logic pushed_proc_sticky; -logic pushed_proc_was_high; -logic pushed_stop_lvl_sticky; -logic pushed_stop_lvl_was_high; -logic pushing_done; -logic set_pushed_data_lower; -assign gclk = clk & tile_en; -assign cmrg_coord_in_0_eos = cmrg_coord_in_0[16]; -assign cmrg_coord_in_1_eos = cmrg_coord_in_1[16]; -assign delay_eos = base_valid_delay & base_delay[16]; -assign delay_data = base_valid_delay & (~delay_eos); -assign delay_done = delay_eos & (base_delay[9:8] == 2'h1); -assign delay_stop = delay_eos & (base_delay[9:8] == 2'h0); -assign base_infifo_in_packed[16] = cmrg_coord_in_0_eos; -assign base_infifo_in_packed[15:0] = cmrg_coord_in_0[15:0]; -assign base_infifo_in_eos = base_infifo_out_packed[16]; -assign base_infifo_in_data = base_infifo_out_packed[15:0]; -assign base_infifo_in_valid = ~base_infifo_empty; -assign cmrg_coord_in_0_ready = ~base_infifo_full; -assign proc_infifo_in_packed[16] = cmrg_coord_in_1_eos; -assign proc_infifo_in_packed[15:0] = cmrg_coord_in_1[15:0]; -assign proc_infifo_in_eos = proc_infifo_out_packed[16]; -assign proc_infifo_in_data = proc_infifo_out_packed[15:0]; -assign proc_infifo_in_valid = ~proc_infifo_empty; -assign cmrg_coord_in_1_ready = ~proc_infifo_full; -assign base_data_seen = base_infifo_in_valid & (~base_infifo_in_eos); -assign proc_data_seen = proc_infifo_in_valid & (~proc_infifo_in_eos); - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - pushed_data_sticky_was_high <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - pushed_data_sticky_was_high <= 1'h0; - end - else if (clr_pushed_data_lower) begin - pushed_data_sticky_was_high <= 1'h0; - end - else if (set_pushed_data_lower) begin - pushed_data_sticky_was_high <= 1'h1; - end - end -end -assign pushed_data_sticky_sticky = pushed_data_sticky_was_high; -assign base_eos_seen = base_infifo_in_valid & base_infifo_in_eos & (base_infifo_in_data[9:8] == 2'h0); -assign base_done_seen = base_infifo_in_valid & base_infifo_in_eos & (base_infifo_in_data[9:8] == 2'h1); -assign base_done = base_infifo_in_valid & base_infifo_in_eos & (base_infifo_in_data[9:8] == 2'h1); -assign proc_done = proc_infifo_in_valid & proc_infifo_in_eos & (proc_infifo_in_data[9:8] == 2'h1); - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - pushed_proc_was_high <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - pushed_proc_was_high <= 1'h0; - end - else if (clr_pushed_proc) begin - pushed_proc_was_high <= 1'h0; - end - else if (cmrg_fifo_push[1]) begin - pushed_proc_was_high <= 1'h1; - end - end -end -assign pushed_proc_sticky = pushed_proc_was_high; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - pushed_stop_lvl_was_high <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - pushed_stop_lvl_was_high <= 1'h0; - end - else if (clr_pushed_stop_lvl) begin - pushed_stop_lvl_was_high <= 1'h0; - end - else if (cmrg_fifo_push[0] & base_infifo_in_valid & base_infifo_in_eos) begin - pushed_stop_lvl_was_high <= 1'h1; - end - end -end -assign pushed_stop_lvl_sticky = pushed_stop_lvl_was_high; -assign both_done = base_infifo_in_valid & base_infifo_in_eos & proc_infifo_in_valid & - proc_infifo_in_eos & (base_infifo_in_data[9:8] == 2'h1) & - (proc_infifo_in_data[9:8] == 2'h1); -assign pushing_done = base_infifo_in_valid & base_infifo_in_eos & proc_infifo_in_valid & - proc_infifo_in_eos & (base_infifo_in_data[9:8] == 2'h1) & - (proc_infifo_in_data[9:8] == 2'h1) & (~base_outfifo_full) & (~proc_outfifo_full); -assign base_infifo_true_pop = cmrg_mode ? cmrg_fifo_pop[0] & (~(delay_stop & base_done_seen)): - cmrg_fifo_pop[0]; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - base_delay <= 17'h0; - base_valid_delay <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - base_delay <= 17'h0; - base_valid_delay <= 1'h0; - end - else if (cmrg_fifo_pop[0] & (~(delay_done & base_done_seen))) begin - base_delay <= ((~base_valid_delay) | base_data_seen | base_done_seen | delay_data) ? - base_infifo_out_packed: (base_infifo_out_packed < base_delay) ? base_delay: - base_infifo_out_packed; - base_valid_delay <= base_infifo_in_valid; - end - else if (cmrg_fifo_pop[0] & delay_done & base_done_seen) begin - base_delay <= 17'h0; - base_valid_delay <= 1'h0; - end - else begin - base_delay <= base_delay; - base_valid_delay <= base_valid_delay; - end - end -end -assign base_outfifo_in_packed[16] = cmrg_mode ? base_delay[16]: base_infifo_in_eos; -assign base_outfifo_in_packed[15:0] = cmrg_mode ? base_delay[15:0]: base_infifo_in_data; -assign cmrg_coord_out_0[16] = base_outfifo_out_packed[16]; -assign cmrg_coord_out_0[15:0] = base_outfifo_out_packed[15:0]; -assign cmrg_coord_out_0_valid = ~base_outfifo_empty; -assign base_outfifo_in_ready = ~base_outfifo_full; -assign proc_outfifo_in_packed[16] = proc_infifo_in_eos; -assign proc_outfifo_in_packed[15:0] = proc_infifo_in_data; -assign cmrg_coord_out_1[16] = proc_outfifo_out_packed[16]; -assign cmrg_coord_out_1[15:0] = proc_outfifo_out_packed[15:0]; -assign cmrg_coord_out_1_valid = ~proc_outfifo_empty; -assign proc_outfifo_in_ready = ~proc_outfifo_full; -always_comb begin - if (base_infifo_in_valid & proc_infifo_in_valid) begin - if ((base_infifo_in_data == 16'h0) & (~base_eos_seen) & (~base_done)) begin - cmrg_base_fifo_pop = 1'h1; - cmrg_proc_fifo_pop = 1'h1; - cmrg_base_fifo_push = 1'h0; - cmrg_proc_fifo_push = 1'h0; - end - else if (base_outfifo_in_ready & proc_outfifo_in_ready) begin - cmrg_base_fifo_pop = 1'h1; - cmrg_proc_fifo_pop = 1'h1; - cmrg_base_fifo_push = 1'h1; - cmrg_proc_fifo_push = 1'h1; - end - else begin - cmrg_base_fifo_pop = 1'h0; - cmrg_proc_fifo_pop = 1'h0; - cmrg_base_fifo_push = 1'h0; - cmrg_proc_fifo_push = 1'h0; - end - end - else begin - cmrg_base_fifo_pop = 1'h0; - cmrg_proc_fifo_pop = 1'h0; - cmrg_base_fifo_push = 1'h0; - cmrg_proc_fifo_push = 1'h0; - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (!rst_n) begin - proc_seq_current_state <= START; - end - else if (clk_en) begin - if (flush) begin - proc_seq_current_state <= START; - end - else proc_seq_current_state <= proc_seq_next_state; - end -end -always_comb begin - proc_seq_next_state = proc_seq_current_state; - unique case (proc_seq_current_state) - DROPZERO: proc_seq_next_state = DROPZERO; - PROCESS: proc_seq_next_state = PROCESS; - START: begin - if (tile_en & cmrg_mode) begin - proc_seq_next_state = PROCESS; - end - else if (tile_en & (~cmrg_mode)) begin - proc_seq_next_state = DROPZERO; - end - else proc_seq_next_state = START; - end - default: proc_seq_next_state = proc_seq_current_state; - endcase -end -always_comb begin - unique case (proc_seq_current_state) - DROPZERO: begin :proc_seq_DROPZERO_Output - cmrg_fifo_pop[0] = cmrg_base_fifo_pop; - cmrg_fifo_pop[1] = cmrg_proc_fifo_pop; - cmrg_fifo_push[0] = cmrg_base_fifo_push; - cmrg_fifo_push[1] = cmrg_proc_fifo_push; - clr_pushed_proc = 1'h1; - clr_pushed_stop_lvl = 1'h1; - set_pushed_data_lower = 1'h0; - clr_pushed_data_lower = 1'h1; - end :proc_seq_DROPZERO_Output - PROCESS: begin :proc_seq_PROCESS_Output - cmrg_fifo_pop[0] = (~base_valid_delay) | (delay_done ? proc_done & (~base_outfifo_full) & - (~proc_outfifo_full): delay_data ? (~base_outfifo_full) & base_infifo_in_valid & - (base_data_seen | (base_eos_seen & proc_infifo_in_valid & (~proc_infifo_in_eos) - & (~proc_outfifo_full))): delay_eos ? base_infifo_in_valid & - ((proc_infifo_in_valid & (~proc_infifo_in_eos)) | proc_done) & (((base_data_seen - | base_done) & ((pushed_data_sticky_sticky & (~base_outfifo_full)) | - (~pushed_data_sticky_sticky))) | base_eos_seen): 1'h0); - cmrg_fifo_pop[1] = proc_done ? delay_done & (~base_outfifo_full) & (~proc_outfifo_full): - (proc_infifo_in_valid & (~proc_infifo_in_eos)) ? base_eos_seen & - (((~proc_outfifo_full) & delay_data & (~base_outfifo_full)) | delay_eos | - (~base_valid_delay)): (proc_infifo_in_valid & proc_infifo_in_eos) ? - ~proc_outfifo_full: 1'h0; - cmrg_fifo_push[0] = delay_done ? proc_done & (~base_outfifo_full) & (~proc_outfifo_full): delay_data - ? (~base_outfifo_full) & base_infifo_in_valid & (base_data_seen | (base_eos_seen - & proc_infifo_in_valid & (~proc_infifo_in_eos) & (~proc_outfifo_full))): - delay_eos ? base_infifo_in_valid & ((proc_infifo_in_valid & - (~proc_infifo_in_eos)) | proc_done) & (base_data_seen | base_done) & - pushed_data_sticky_sticky & (~base_outfifo_full): 1'h0; - cmrg_fifo_push[1] = proc_done ? delay_done & (~base_outfifo_full) & (~proc_outfifo_full): - (proc_infifo_in_valid & (~proc_infifo_in_eos)) ? base_eos_seen & - (~proc_outfifo_full) & delay_data & (~base_outfifo_full): (proc_infifo_in_valid - & proc_infifo_in_eos) ? ~proc_outfifo_full: 1'h0; - clr_pushed_proc = 1'h0; - clr_pushed_stop_lvl = 1'h0; - set_pushed_data_lower = delay_data & (~base_outfifo_full) & base_infifo_in_valid & (base_data_seen | - (base_eos_seen & proc_infifo_in_valid & (~proc_infifo_in_eos) & - (~proc_outfifo_full))); - clr_pushed_data_lower = delay_done | (delay_eos & base_infifo_in_valid & ((proc_infifo_in_valid & - (~proc_infifo_in_eos)) | proc_done) & (base_data_seen | base_done) & - pushed_data_sticky_sticky & (~base_outfifo_full)); - end :proc_seq_PROCESS_Output - START: begin :proc_seq_START_Output - cmrg_fifo_pop[0] = 1'h0; - cmrg_fifo_pop[1] = 1'h0; - cmrg_fifo_push[0] = 1'h0; - cmrg_fifo_push[1] = 1'h0; - clr_pushed_proc = 1'h1; - clr_pushed_stop_lvl = 1'h1; - set_pushed_data_lower = 1'h0; - clr_pushed_data_lower = 1'h1; - end :proc_seq_START_Output - default: begin :proc_seq_default_Output - cmrg_fifo_pop[0] = 1'h0; - cmrg_fifo_pop[1] = 1'h0; - cmrg_fifo_push[0] = 1'h0; - cmrg_fifo_push[1] = 1'h0; - clr_pushed_proc = 1'h1; - clr_pushed_stop_lvl = 1'h1; - set_pushed_data_lower = 1'h0; - clr_pushed_data_lower = 1'h1; - end :proc_seq_default_Output - endcase -end -reg_fifo_depth_0_w_17_afd_2 base_infifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in(base_infifo_in_packed), - .flush(flush), - .pop(base_infifo_true_pop), - .push(cmrg_coord_in_0_valid), - .rst_n(rst_n), - .data_out(base_infifo_out_packed), - .empty(base_infifo_empty), - .full(base_infifo_full) -); - -reg_fifo_depth_0_w_17_afd_2 proc_infifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in(proc_infifo_in_packed), - .flush(flush), - .pop(cmrg_fifo_pop[1]), - .push(cmrg_coord_in_1_valid), - .rst_n(rst_n), - .data_out(proc_infifo_out_packed), - .empty(proc_infifo_empty), - .full(proc_infifo_full) -); - -reg_fifo_depth_0_w_17_afd_2 base_outfifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in(base_outfifo_in_packed), - .flush(flush), - .pop(cmrg_coord_out_0_ready), - .push(cmrg_fifo_push[0]), - .rst_n(rst_n), - .data_out(base_outfifo_out_packed), - .empty(base_outfifo_empty), - .full(base_outfifo_full) -); - -reg_fifo_depth_0_w_17_afd_2 proc_outfifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in(proc_outfifo_in_packed), - .flush(flush), - .pop(cmrg_coord_out_1_ready), - .push(cmrg_fifo_push[1]), - .rst_n(rst_n), - .data_out(proc_outfifo_out_packed), - .empty(proc_outfifo_empty), - .full(proc_outfifo_full) -); - -endmodule // crddrop - -module crddrop_flat ( - input logic clk, - input logic clk_en, - input logic [0:0] [16:0] cmrg_coord_in_0_f_, - input logic cmrg_coord_in_0_valid_f_, - input logic [0:0] [16:0] cmrg_coord_in_1_f_, - input logic cmrg_coord_in_1_valid_f_, - input logic cmrg_coord_out_0_ready_f_, - input logic cmrg_coord_out_1_ready_f_, - input logic crddrop_inst_cmrg_enable, - input logic crddrop_inst_cmrg_mode, - input logic [15:0] crddrop_inst_cmrg_stop_lvl, - input logic crddrop_inst_tile_en, - input logic flush, - input logic rst_n, - output logic cmrg_coord_in_0_ready_f_, - output logic cmrg_coord_in_1_ready_f_, - output logic [0:0] [16:0] cmrg_coord_out_0_f_, - output logic cmrg_coord_out_0_valid_f_, - output logic [0:0] [16:0] cmrg_coord_out_1_f_, - output logic cmrg_coord_out_1_valid_f_ -); - -crddrop crddrop_inst ( - .clk(clk), - .clk_en(clk_en), - .cmrg_coord_in_0(cmrg_coord_in_0_f_), - .cmrg_coord_in_0_valid(cmrg_coord_in_0_valid_f_), - .cmrg_coord_in_1(cmrg_coord_in_1_f_), - .cmrg_coord_in_1_valid(cmrg_coord_in_1_valid_f_), - .cmrg_coord_out_0_ready(cmrg_coord_out_0_ready_f_), - .cmrg_coord_out_1_ready(cmrg_coord_out_1_ready_f_), - .cmrg_enable(crddrop_inst_cmrg_enable), - .cmrg_mode(crddrop_inst_cmrg_mode), - .cmrg_stop_lvl(crddrop_inst_cmrg_stop_lvl), - .flush(flush), - .rst_n(rst_n), - .tile_en(crddrop_inst_tile_en), - .cmrg_coord_in_0_ready(cmrg_coord_in_0_ready_f_), - .cmrg_coord_in_1_ready(cmrg_coord_in_1_ready_f_), - .cmrg_coord_out_0(cmrg_coord_out_0_f_), - .cmrg_coord_out_0_valid(cmrg_coord_out_0_valid_f_), - .cmrg_coord_out_1(cmrg_coord_out_1_f_), - .cmrg_coord_out_1_valid(cmrg_coord_out_1_valid_f_) -); - -endmodule // crddrop_flat - -module crdhold ( - input logic clk, - input logic clk_en, - input logic [16:0] cmrg_coord_in_0, - input logic cmrg_coord_in_0_valid, - input logic [16:0] cmrg_coord_in_1, - input logic cmrg_coord_in_1_valid, - input logic cmrg_coord_out_0_ready, - input logic cmrg_coord_out_1_ready, - input logic cmrg_enable, - input logic [15:0] cmrg_stop_lvl, - input logic flush, - input logic rst_n, - input logic tile_en, - output logic cmrg_coord_in_0_ready, - output logic cmrg_coord_in_1_ready, - output logic [16:0] cmrg_coord_out_0, - output logic cmrg_coord_out_0_valid, - output logic [16:0] cmrg_coord_out_1, - output logic cmrg_coord_out_1_valid -); - -typedef enum logic[1:0] { - DATA_SEEN = 2'h0, - DONE = 2'h1, - START = 2'h2 -} proc_seq_state; -logic base_data_seen; -logic base_done_seen; -logic base_eos_seen; -logic base_infifo_empty; -logic base_infifo_full; -logic [15:0] base_infifo_in_data; -logic base_infifo_in_eos; -logic [16:0] base_infifo_in_packed; -logic base_infifo_in_valid; -logic [16:0] base_infifo_out_packed; -logic base_outfifo_empty; -logic base_outfifo_full; -logic [16:0] base_outfifo_in_packed; -logic [16:0] base_outfifo_out_packed; -logic both_done; -logic clr_pushed_base; -logic clr_pushed_proc; -logic cmrg_coord_in_0_eos; -logic cmrg_coord_in_1_eos; -logic [1:0] cmrg_fifo_pop; -logic [1:0] cmrg_fifo_push; -logic [15:0] data_to_fifo; -logic eos_to_fifo; -logic gclk; -logic [15:0] hold_reg; -logic proc_data_seen; -logic proc_done_seen; -logic proc_eos_seen; -logic proc_infifo_empty; -logic proc_infifo_full; -logic [15:0] proc_infifo_in_data; -logic proc_infifo_in_eos; -logic [16:0] proc_infifo_in_packed; -logic proc_infifo_in_valid; -logic [16:0] proc_infifo_out_packed; -logic proc_outfifo_empty; -logic proc_outfifo_full; -logic [16:0] proc_outfifo_in_packed; -logic [16:0] proc_outfifo_out_packed; -proc_seq_state proc_seq_current_state; -proc_seq_state proc_seq_next_state; -logic pushed_base_sticky; -logic pushed_base_was_high; -logic pushed_proc_sticky; -logic pushed_proc_was_high; -logic pushing_done; -logic reg_clr; -logic reg_hold; -assign gclk = clk & tile_en; -assign cmrg_coord_in_0_eos = cmrg_coord_in_0[16]; -assign cmrg_coord_in_1_eos = cmrg_coord_in_1[16]; -assign base_infifo_in_packed[16] = cmrg_coord_in_0_eos; -assign base_infifo_in_packed[15:0] = cmrg_coord_in_0[15:0]; -assign base_infifo_in_eos = base_infifo_out_packed[16]; -assign base_infifo_in_data = base_infifo_out_packed[15:0]; -assign base_infifo_in_valid = ~base_infifo_empty; -assign cmrg_coord_in_0_ready = ~base_infifo_full; -assign proc_infifo_in_packed[16] = cmrg_coord_in_1_eos; -assign proc_infifo_in_packed[15:0] = cmrg_coord_in_1[15:0]; -assign proc_infifo_in_eos = proc_infifo_out_packed[16]; -assign proc_infifo_in_data = proc_infifo_out_packed[15:0]; -assign proc_infifo_in_valid = ~proc_infifo_empty; -assign cmrg_coord_in_1_ready = ~proc_infifo_full; -assign base_data_seen = base_infifo_in_valid & (~base_infifo_in_eos); -assign proc_data_seen = proc_infifo_in_valid & (~proc_infifo_in_eos); -assign base_eos_seen = base_infifo_in_valid & base_infifo_in_eos & (base_infifo_in_data[9:8] == 2'h0); -assign proc_eos_seen = proc_infifo_in_valid & proc_infifo_in_eos & (proc_infifo_in_data[9:8] == 2'h0); -assign base_done_seen = base_infifo_in_valid & base_infifo_in_eos & (base_infifo_in_data[9:8] == 2'h1); -assign proc_done_seen = proc_infifo_in_valid & proc_infifo_in_eos & (proc_infifo_in_data[9:8] == 2'h1); - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - pushed_proc_was_high <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - pushed_proc_was_high <= 1'h0; - end - else if (clr_pushed_proc) begin - pushed_proc_was_high <= 1'h0; - end - else if (cmrg_fifo_push[1]) begin - pushed_proc_was_high <= 1'h1; - end - end -end -assign pushed_proc_sticky = pushed_proc_was_high; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - pushed_base_was_high <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - pushed_base_was_high <= 1'h0; - end - else if (clr_pushed_base) begin - pushed_base_was_high <= 1'h0; - end - else if (cmrg_fifo_push[0]) begin - pushed_base_was_high <= 1'h1; - end - end -end -assign pushed_base_sticky = pushed_base_was_high; -assign both_done = base_infifo_in_valid & base_infifo_in_eos & proc_infifo_in_valid & - proc_infifo_in_eos & (base_infifo_in_data[9:8] == 2'h1) & - (proc_infifo_in_data[9:8] == 2'h1); -assign pushing_done = base_infifo_in_valid & base_infifo_in_eos & proc_infifo_in_valid & - proc_infifo_in_eos & (base_infifo_in_data[9:8] == 2'h1) & - (proc_infifo_in_data[9:8] == 2'h1) & (~base_outfifo_full) & (~proc_outfifo_full); - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - hold_reg <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - hold_reg <= 16'h0; - end - else if (reg_clr) begin - hold_reg <= 16'h0; - end - else if (reg_hold) begin - hold_reg <= proc_infifo_in_data; - end - end -end -assign base_outfifo_in_packed[16] = base_infifo_in_eos; -assign base_outfifo_in_packed[15:0] = base_infifo_in_data; -assign cmrg_coord_out_0[16] = base_outfifo_out_packed[16]; -assign cmrg_coord_out_0[15:0] = base_outfifo_out_packed[15:0]; -assign cmrg_coord_out_0_valid = ~base_outfifo_empty; -assign proc_outfifo_in_packed[16] = eos_to_fifo; -assign proc_outfifo_in_packed[15:0] = data_to_fifo; -assign cmrg_coord_out_1[16] = proc_outfifo_out_packed[16]; -assign cmrg_coord_out_1[15:0] = proc_outfifo_out_packed[15:0]; -assign cmrg_coord_out_1_valid = ~proc_outfifo_empty; - -always_ff @(posedge clk, negedge rst_n) begin - if (!rst_n) begin - proc_seq_current_state <= START; - end - else if (clk_en) begin - if (flush) begin - proc_seq_current_state <= START; - end - else proc_seq_current_state <= proc_seq_next_state; - end -end -always_comb begin - proc_seq_next_state = proc_seq_current_state; - unique case (proc_seq_current_state) - DATA_SEEN: begin - if (both_done) begin - proc_seq_next_state = DONE; - end - else proc_seq_next_state = DATA_SEEN; - end - DONE: begin - if ((~base_outfifo_full) & (~proc_outfifo_full)) begin - proc_seq_next_state = START; - end - end - START: begin - if (tile_en) begin - proc_seq_next_state = DATA_SEEN; - end - else proc_seq_next_state = START; - end - default: proc_seq_next_state = proc_seq_current_state; - endcase -end -always_comb begin - unique case (proc_seq_current_state) - DATA_SEEN: begin :proc_seq_DATA_SEEN_Output - cmrg_fifo_pop[0] = (base_eos_seen ? 1'h1 & (proc_data_seen | proc_done_seen): base_infifo_in_valid - & (~base_infifo_in_eos) & proc_infifo_in_valid & (~proc_infifo_in_eos)) & - (~base_outfifo_full) & (~proc_outfifo_full) & (~base_done_seen); - cmrg_fifo_pop[1] = (proc_eos_seen ? 1'h1: base_eos_seen & (~base_outfifo_full) & - (~proc_outfifo_full)) & (~proc_done_seen); - cmrg_fifo_push[0] = (base_eos_seen ? 1'h1 & (proc_data_seen | proc_done_seen): base_infifo_in_valid - & (~base_infifo_in_eos) & proc_infifo_in_valid & (~proc_infifo_in_eos)) & - (~base_outfifo_full) & (~proc_outfifo_full) & (~base_done_seen); - cmrg_fifo_push[1] = (base_eos_seen ? 1'h1 & (proc_data_seen | proc_done_seen): base_infifo_in_valid - & (~base_infifo_in_eos) & proc_infifo_in_valid & (~proc_infifo_in_eos)) & - (~base_outfifo_full) & (~proc_outfifo_full) & (~base_done_seen); - data_to_fifo = base_infifo_in_eos ? base_infifo_in_data: proc_infifo_in_data; - eos_to_fifo = base_infifo_in_eos; - clr_pushed_proc = 1'h1; - clr_pushed_base = 1'h1; - reg_clr = 1'h1; - reg_hold = 1'h0; - end :proc_seq_DATA_SEEN_Output - DONE: begin :proc_seq_DONE_Output - cmrg_fifo_pop[0] = (~proc_outfifo_full) & (~base_outfifo_full); - cmrg_fifo_pop[1] = (~proc_outfifo_full) & (~base_outfifo_full); - cmrg_fifo_push[0] = (~proc_outfifo_full) & (~base_outfifo_full); - cmrg_fifo_push[1] = (~proc_outfifo_full) & (~base_outfifo_full); - data_to_fifo = base_infifo_in_data; - eos_to_fifo = 1'h1; - clr_pushed_proc = 1'h1; - clr_pushed_base = 1'h1; - reg_clr = 1'h1; - reg_hold = 1'h0; - end :proc_seq_DONE_Output - START: begin :proc_seq_START_Output - cmrg_fifo_pop[0] = 1'h0; - cmrg_fifo_pop[1] = 1'h0; - cmrg_fifo_push[0] = 1'h0; - cmrg_fifo_push[1] = 1'h0; - data_to_fifo = 16'h0; - eos_to_fifo = 1'h0; - clr_pushed_proc = 1'h1; - clr_pushed_base = 1'h1; - reg_clr = 1'h0; - reg_hold = 1'h0; - end :proc_seq_START_Output - default: begin :proc_seq_default_Output - cmrg_fifo_pop[0] = 1'h0; - cmrg_fifo_pop[1] = 1'h0; - cmrg_fifo_push[0] = 1'h0; - cmrg_fifo_push[1] = 1'h0; - data_to_fifo = 16'h0; - eos_to_fifo = 1'h0; - clr_pushed_proc = 1'h1; - clr_pushed_base = 1'h1; - reg_clr = 1'h0; - reg_hold = 1'h0; - end :proc_seq_default_Output - endcase -end -reg_fifo_depth_0_w_17_afd_2 base_infifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in(base_infifo_in_packed), - .flush(flush), - .pop(cmrg_fifo_pop[0]), - .push(cmrg_coord_in_0_valid), - .rst_n(rst_n), - .data_out(base_infifo_out_packed), - .empty(base_infifo_empty), - .full(base_infifo_full) -); - -reg_fifo_depth_0_w_17_afd_2 proc_infifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in(proc_infifo_in_packed), - .flush(flush), - .pop(cmrg_fifo_pop[1]), - .push(cmrg_coord_in_1_valid), - .rst_n(rst_n), - .data_out(proc_infifo_out_packed), - .empty(proc_infifo_empty), - .full(proc_infifo_full) -); - -reg_fifo_depth_0_w_17_afd_2 base_outfifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in(base_outfifo_in_packed), - .flush(flush), - .pop(cmrg_coord_out_0_ready), - .push(cmrg_fifo_push[0]), - .rst_n(rst_n), - .data_out(base_outfifo_out_packed), - .empty(base_outfifo_empty), - .full(base_outfifo_full) -); - -reg_fifo_depth_0_w_17_afd_2 proc_outfifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in(proc_outfifo_in_packed), - .flush(flush), - .pop(cmrg_coord_out_1_ready), - .push(cmrg_fifo_push[1]), - .rst_n(rst_n), - .data_out(proc_outfifo_out_packed), - .empty(proc_outfifo_empty), - .full(proc_outfifo_full) -); - -endmodule // crdhold - -module crdhold_flat ( - input logic clk, - input logic clk_en, - input logic [0:0] [16:0] cmrg_coord_in_0_f_, - input logic cmrg_coord_in_0_valid_f_, - input logic [0:0] [16:0] cmrg_coord_in_1_f_, - input logic cmrg_coord_in_1_valid_f_, - input logic cmrg_coord_out_0_ready_f_, - input logic cmrg_coord_out_1_ready_f_, - input logic crdhold_inst_cmrg_enable, - input logic [15:0] crdhold_inst_cmrg_stop_lvl, - input logic crdhold_inst_tile_en, - input logic flush, - input logic rst_n, - output logic cmrg_coord_in_0_ready_f_, - output logic cmrg_coord_in_1_ready_f_, - output logic [0:0] [16:0] cmrg_coord_out_0_f_, - output logic cmrg_coord_out_0_valid_f_, - output logic [0:0] [16:0] cmrg_coord_out_1_f_, - output logic cmrg_coord_out_1_valid_f_ -); - -crdhold crdhold_inst ( - .clk(clk), - .clk_en(clk_en), - .cmrg_coord_in_0(cmrg_coord_in_0_f_), - .cmrg_coord_in_0_valid(cmrg_coord_in_0_valid_f_), - .cmrg_coord_in_1(cmrg_coord_in_1_f_), - .cmrg_coord_in_1_valid(cmrg_coord_in_1_valid_f_), - .cmrg_coord_out_0_ready(cmrg_coord_out_0_ready_f_), - .cmrg_coord_out_1_ready(cmrg_coord_out_1_ready_f_), - .cmrg_enable(crdhold_inst_cmrg_enable), - .cmrg_stop_lvl(crdhold_inst_cmrg_stop_lvl), - .flush(flush), - .rst_n(rst_n), - .tile_en(crdhold_inst_tile_en), - .cmrg_coord_in_0_ready(cmrg_coord_in_0_ready_f_), - .cmrg_coord_in_1_ready(cmrg_coord_in_1_ready_f_), - .cmrg_coord_out_0(cmrg_coord_out_0_f_), - .cmrg_coord_out_0_valid(cmrg_coord_out_0_valid_f_), - .cmrg_coord_out_1(cmrg_coord_out_1_f_), - .cmrg_coord_out_1_valid(cmrg_coord_out_1_valid_f_) -); - -endmodule // crdhold_flat - -module intersect_unit ( - input logic clk, - input logic clk_en, - input logic [16:0] coord_in_0, - input logic coord_in_0_valid, - input logic [16:0] coord_in_1, - input logic coord_in_1_valid, - input logic coord_out_ready, - input logic flush, - input logic joiner_op, - input logic [16:0] pos_in_0, - input logic pos_in_0_valid, - input logic [16:0] pos_in_1, - input logic pos_in_1_valid, - input logic pos_out_0_ready, - input logic pos_out_1_ready, - input logic rst_n, - input logic tile_en, - input logic vector_reduce_mode, - output logic coord_in_0_ready, - output logic coord_in_1_ready, - output logic [16:0] coord_out, - output logic coord_out_valid, - output logic pos_in_0_ready, - output logic pos_in_1_ready, - output logic [16:0] pos_out_0, - output logic pos_out_0_valid, - output logic [16:0] pos_out_1, - output logic pos_out_1_valid -); - -typedef enum logic[2:0] { - ALIGN = 3'h0, - DONE = 3'h1, - DRAIN = 3'h2, - IDLE = 3'h3, - ITER = 3'h4, - PASS_DONE = 3'h5, - UNION = 3'h6, - WAIT_FOR_VALID = 3'h7 -} intersect_seq_state; -logic all_are_valid; -logic all_are_valid_but_no_eos; -logic all_have_eos; -logic [1:0] all_have_eos_and_all_valid; -logic any_has_eos; -logic [1:0] clr_eos_sticky; -logic [16:0] coord_fifo_in_packed; -logic [16:0] coord_fifo_out_packed; -logic coord_in_0_fifo_eos_in; -logic [16:0] coord_in_0_fifo_in; -logic coord_in_0_fifo_valid_in; -logic coord_in_1_fifo_eos_in; -logic [16:0] coord_in_1_fifo_in; -logic coord_in_1_fifo_valid_in; -logic coord_in_fifo_0_empty; -logic coord_in_fifo_0_full; -logic coord_in_fifo_1_empty; -logic coord_in_fifo_1_full; -logic [15:0] coord_to_fifo; -logic coord_to_fifo_eos; -logic coordinate_fifo_empty; -logic coordinate_fifo_full; -logic [16:0] done_token; -logic [1:0] eos_in_sticky; -logic eos_sticky_0_sticky; -logic eos_sticky_0_was_high; -logic eos_sticky_1_sticky; -logic eos_sticky_1_was_high; -logic [2:0] fifo_full; -logic fifo_push; -logic gclk; -intersect_seq_state intersect_seq_current_state; -intersect_seq_state intersect_seq_next_state; -logic [15:0] maybe; -logic [1:0] pop_fifo; -logic pos0_fifo_empty; -logic pos0_fifo_full; -logic [16:0] pos0_fifo_in_packed; -logic [16:0] pos0_fifo_out_packed; -logic pos1_fifo_empty; -logic pos1_fifo_full; -logic [16:0] pos1_fifo_in_packed; -logic [16:0] pos1_fifo_out_packed; -logic pos_in_0_fifo_eos_in; -logic [16:0] pos_in_0_fifo_in; -logic pos_in_0_fifo_valid_in; -logic pos_in_1_fifo_eos_in; -logic [16:0] pos_in_1_fifo_in; -logic pos_in_1_fifo_valid_in; -logic pos_in_fifo_0_empty; -logic pos_in_fifo_0_full; -logic pos_in_fifo_1_empty; -logic pos_in_fifo_1_full; -logic [1:0][15:0] pos_to_fifo; -logic [1:0] pos_to_fifo_eos; -logic [16:0] semi_done_token; -assign gclk = clk & tile_en; -assign coord_in_0_fifo_eos_in = coord_in_0_fifo_in[16]; -assign coord_in_0_ready = ~coord_in_fifo_0_full; -assign coord_in_0_fifo_valid_in = ~coord_in_fifo_0_empty; -assign pos_in_0_fifo_eos_in = pos_in_0_fifo_in[16]; -assign pos_in_0_ready = ~pos_in_fifo_0_full; -assign pos_in_0_fifo_valid_in = ~pos_in_fifo_0_empty; -assign coord_in_1_fifo_eos_in = coord_in_1_fifo_in[16]; -assign coord_in_1_ready = ~coord_in_fifo_1_full; -assign coord_in_1_fifo_valid_in = ~coord_in_fifo_1_empty; -assign pos_in_1_fifo_eos_in = pos_in_1_fifo_in[16]; -assign pos_in_1_ready = ~pos_in_fifo_1_full; -assign pos_in_1_fifo_valid_in = ~pos_in_fifo_1_empty; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - eos_sticky_0_was_high <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - eos_sticky_0_was_high <= 1'h0; - end - else if (clr_eos_sticky[0]) begin - eos_sticky_0_was_high <= 1'h0; - end - else if (coord_in_0_fifo_eos_in & coord_in_0_fifo_valid_in & pos_in_0_fifo_eos_in & pos_in_0_fifo_valid_in) begin - eos_sticky_0_was_high <= 1'h1; - end - end -end -assign eos_sticky_0_sticky = (coord_in_0_fifo_eos_in & coord_in_0_fifo_valid_in & pos_in_0_fifo_eos_in & - pos_in_0_fifo_valid_in) | eos_sticky_0_was_high; -assign eos_in_sticky[0] = eos_sticky_0_sticky; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - eos_sticky_1_was_high <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - eos_sticky_1_was_high <= 1'h0; - end - else if (clr_eos_sticky[1]) begin - eos_sticky_1_was_high <= 1'h0; - end - else if (coord_in_1_fifo_eos_in & coord_in_1_fifo_valid_in & pos_in_1_fifo_eos_in & pos_in_1_fifo_valid_in) begin - eos_sticky_1_was_high <= 1'h1; - end - end -end -assign eos_sticky_1_sticky = (coord_in_1_fifo_eos_in & coord_in_1_fifo_valid_in & pos_in_1_fifo_eos_in & - pos_in_1_fifo_valid_in) | eos_sticky_1_was_high; -assign eos_in_sticky[1] = eos_sticky_1_sticky; -assign all_are_valid_but_no_eos = (&{coord_in_0_fifo_valid_in, coord_in_1_fifo_valid_in, pos_in_0_fifo_valid_in, - pos_in_1_fifo_valid_in}) & (~any_has_eos); -assign all_are_valid = &{coord_in_0_fifo_valid_in, coord_in_1_fifo_valid_in, pos_in_0_fifo_valid_in, - pos_in_1_fifo_valid_in}; -assign all_have_eos_and_all_valid[0] = coord_in_0_fifo_eos_in & pos_in_0_fifo_eos_in & coord_in_0_fifo_valid_in & - pos_in_0_fifo_valid_in; -assign all_have_eos_and_all_valid[1] = coord_in_1_fifo_eos_in & pos_in_1_fifo_eos_in & coord_in_1_fifo_valid_in & - pos_in_1_fifo_valid_in; -assign any_has_eos = |({coord_in_0_fifo_eos_in, coord_in_1_fifo_eos_in, pos_in_0_fifo_eos_in, - pos_in_1_fifo_eos_in} & {coord_in_0_fifo_valid_in, coord_in_1_fifo_valid_in, - pos_in_0_fifo_valid_in, pos_in_1_fifo_valid_in}); -assign all_have_eos = &({coord_in_0_fifo_eos_in, coord_in_1_fifo_eos_in, pos_in_0_fifo_eos_in, - pos_in_1_fifo_eos_in} & {coord_in_0_fifo_valid_in, coord_in_1_fifo_valid_in, - pos_in_0_fifo_valid_in, pos_in_1_fifo_valid_in}); -assign maybe = vector_reduce_mode ? 16'h0: {6'h0, 2'h2, 8'h0}; -assign semi_done_token = {1'h1, 11'h0, 1'h1, 4'h0}; -assign done_token = {1'h1, 7'h0, 1'h1, 8'h0}; -assign coord_fifo_in_packed[16] = coord_to_fifo_eos; -assign coord_fifo_in_packed[15:0] = coord_to_fifo; -assign coord_out[16] = coord_fifo_out_packed[16]; -assign coord_out[15:0] = coord_fifo_out_packed[15:0]; -assign pos0_fifo_in_packed[16] = pos_to_fifo_eos[0]; -assign pos0_fifo_in_packed[15:0] = pos_to_fifo[0]; -assign pos_out_0[16] = pos0_fifo_out_packed[16]; -assign pos_out_0[15:0] = pos0_fifo_out_packed[15:0]; -assign pos1_fifo_in_packed[16] = pos_to_fifo_eos[1]; -assign pos1_fifo_in_packed[15:0] = pos_to_fifo[1]; -assign pos_out_1[16] = pos1_fifo_out_packed[16]; -assign pos_out_1[15:0] = pos1_fifo_out_packed[15:0]; -assign fifo_full[0] = coordinate_fifo_full; -assign fifo_full[1] = pos0_fifo_full; -assign fifo_full[2] = pos1_fifo_full; -assign coord_out_valid = ~coordinate_fifo_empty; -assign pos_out_0_valid = ~pos0_fifo_empty; -assign pos_out_1_valid = ~pos1_fifo_empty; - -always_ff @(posedge clk, negedge rst_n) begin - if (!rst_n) begin - intersect_seq_current_state <= IDLE; - end - else if (clk_en) begin - if (flush) begin - intersect_seq_current_state <= IDLE; - end - else intersect_seq_current_state <= intersect_seq_next_state; - end -end -always_comb begin - intersect_seq_next_state = intersect_seq_current_state; - unique case (intersect_seq_current_state) - ALIGN: begin - if (all_have_eos) begin - intersect_seq_next_state = ITER; - end - else intersect_seq_next_state = ALIGN; - end - DONE: intersect_seq_next_state = IDLE; - DRAIN: begin - if (vector_reduce_mode & (~(|fifo_full)) & (&{coord_in_0_fifo_valid_in, coord_in_1_fifo_valid_in, pos_in_0_fifo_valid_in, pos_in_1_fifo_valid_in})) begin - intersect_seq_next_state = PASS_DONE; - end - else if ((~vector_reduce_mode) & (~all_have_eos) & (&{coord_in_0_fifo_valid_in, coord_in_1_fifo_valid_in, pos_in_0_fifo_valid_in, pos_in_1_fifo_valid_in})) begin - intersect_seq_next_state = DONE; - end - else intersect_seq_next_state = DRAIN; - end - IDLE: begin - if (all_are_valid & (joiner_op == 1'h1) & tile_en) begin - intersect_seq_next_state = UNION; - end - else if (any_has_eos & (joiner_op == 1'h0) & tile_en) begin - intersect_seq_next_state = ALIGN; - end - else if (all_are_valid_but_no_eos & (joiner_op == 1'h0) & tile_en) begin - intersect_seq_next_state = ITER; - end - else intersect_seq_next_state = IDLE; - end - ITER: begin - if (any_has_eos & (~all_have_eos)) begin - intersect_seq_next_state = ALIGN; - end - else intersect_seq_next_state = ITER; - end - PASS_DONE: begin - if ((~(|fifo_full)) & (&{coord_in_0_fifo_valid_in, coord_in_1_fifo_valid_in, pos_in_0_fifo_valid_in, pos_in_1_fifo_valid_in})) begin - intersect_seq_next_state = WAIT_FOR_VALID; - end - else intersect_seq_next_state = PASS_DONE; - end - UNION: begin - if (&eos_in_sticky) begin - intersect_seq_next_state = DRAIN; - end - else intersect_seq_next_state = UNION; - end - WAIT_FOR_VALID: begin - if (vector_reduce_mode & (&{coord_in_0_fifo_valid_in, coord_in_1_fifo_valid_in, pos_in_0_fifo_valid_in, pos_in_1_fifo_valid_in})) begin - intersect_seq_next_state = DONE; - end - else if ((~all_have_eos) & (&{coord_in_0_fifo_valid_in, coord_in_1_fifo_valid_in, pos_in_0_fifo_valid_in, pos_in_1_fifo_valid_in})) begin - intersect_seq_next_state = DONE; - end - else intersect_seq_next_state = WAIT_FOR_VALID; - end - default: begin end - endcase -end -always_comb begin - unique case (intersect_seq_current_state) - ALIGN: begin :intersect_seq_ALIGN_Output - pop_fifo[0] = ((~eos_in_sticky[0]) & coord_in_0_fifo_valid_in & pos_in_0_fifo_valid_in) | - (all_have_eos & (~(|fifo_full))); - pop_fifo[1] = ((~eos_in_sticky[1]) & coord_in_1_fifo_valid_in & pos_in_1_fifo_valid_in) | - (all_have_eos & (~(|fifo_full))); - fifo_push = all_have_eos & (~(|fifo_full)); - clr_eos_sticky[0] = all_have_eos & (~(|fifo_full)); - clr_eos_sticky[1] = all_have_eos & (~(|fifo_full)); - coord_to_fifo = coord_in_0_fifo_in[15:0]; - pos_to_fifo[0] = pos_in_0_fifo_in[15:0]; - pos_to_fifo[1] = pos_in_1_fifo_in[15:0]; - coord_to_fifo_eos = 1'h1; - pos_to_fifo_eos[0] = 1'h1; - pos_to_fifo_eos[1] = 1'h1; - end :intersect_seq_ALIGN_Output - DONE: begin :intersect_seq_DONE_Output - pop_fifo[0] = 1'h0; - pop_fifo[1] = 1'h0; - fifo_push = 1'h0; - clr_eos_sticky[0] = 1'h1; - clr_eos_sticky[1] = 1'h1; - coord_to_fifo = 16'h0; - pos_to_fifo[0] = 16'h0; - pos_to_fifo[1] = 16'h0; - coord_to_fifo_eos = 1'h0; - pos_to_fifo_eos[0] = 1'h0; - pos_to_fifo_eos[1] = 1'h0; - end :intersect_seq_DONE_Output - DRAIN: begin :intersect_seq_DRAIN_Output - pop_fifo[0] = (~(|fifo_full)) & all_have_eos & (&{coord_in_0_fifo_valid_in, - coord_in_1_fifo_valid_in, pos_in_0_fifo_valid_in, pos_in_1_fifo_valid_in}); - pop_fifo[1] = (~(|fifo_full)) & all_have_eos & (&{coord_in_0_fifo_valid_in, - coord_in_1_fifo_valid_in, pos_in_0_fifo_valid_in, pos_in_1_fifo_valid_in}); - fifo_push = (~(|fifo_full)) & all_have_eos & (&{coord_in_0_fifo_valid_in, - coord_in_1_fifo_valid_in, pos_in_0_fifo_valid_in, pos_in_1_fifo_valid_in}); - clr_eos_sticky[0] = 1'h0; - clr_eos_sticky[1] = 1'h0; - coord_to_fifo = coord_in_0_fifo_in[15:0]; - pos_to_fifo[0] = pos_in_0_fifo_in[15:0]; - pos_to_fifo[1] = pos_in_0_fifo_in[15:0]; - coord_to_fifo_eos = any_has_eos; - pos_to_fifo_eos[0] = any_has_eos; - pos_to_fifo_eos[1] = any_has_eos; - end :intersect_seq_DRAIN_Output - IDLE: begin :intersect_seq_IDLE_Output - pop_fifo[0] = 1'h0; - pop_fifo[1] = 1'h0; - fifo_push = 1'h0; - clr_eos_sticky[0] = 1'h0; - clr_eos_sticky[1] = 1'h0; - coord_to_fifo = 16'h0; - pos_to_fifo[0] = 16'h0; - pos_to_fifo[1] = 16'h0; - coord_to_fifo_eos = 1'h0; - pos_to_fifo_eos[0] = 1'h0; - pos_to_fifo_eos[1] = 1'h0; - end :intersect_seq_IDLE_Output - ITER: begin :intersect_seq_ITER_Output - pop_fifo[0] = (all_are_valid_but_no_eos | (all_are_valid & all_have_eos)) & - (coord_in_0_fifo_in <= coord_in_1_fifo_in) & (~(|fifo_full)); - pop_fifo[1] = (all_are_valid_but_no_eos | (all_are_valid & all_have_eos)) & - (coord_in_0_fifo_in >= coord_in_1_fifo_in) & (~(|fifo_full)); - fifo_push = all_are_valid & (((coord_in_0_fifo_in == coord_in_1_fifo_in) & (~any_has_eos)) | - all_have_eos) & (~(|fifo_full)); - clr_eos_sticky[0] = all_have_eos & (~(|fifo_full)); - clr_eos_sticky[1] = all_have_eos & (~(|fifo_full)); - coord_to_fifo = coord_in_0_fifo_in[15:0]; - pos_to_fifo[0] = pos_in_0_fifo_in[15:0]; - pos_to_fifo[1] = pos_in_1_fifo_in[15:0]; - coord_to_fifo_eos = all_have_eos; - pos_to_fifo_eos[0] = all_have_eos; - pos_to_fifo_eos[1] = all_have_eos; - end :intersect_seq_ITER_Output - PASS_DONE: begin :intersect_seq_PASS_DONE_Output - pop_fifo[0] = (&{coord_in_0_fifo_valid_in, coord_in_1_fifo_valid_in, pos_in_0_fifo_valid_in, - pos_in_1_fifo_valid_in}) & (coord_in_0_fifo_in == done_token); - pop_fifo[1] = (&{coord_in_0_fifo_valid_in, coord_in_1_fifo_valid_in, pos_in_0_fifo_valid_in, - pos_in_1_fifo_valid_in}) & (coord_in_1_fifo_in == done_token); - fifo_push = (~(|fifo_full)) & (&{coord_in_0_fifo_valid_in, coord_in_1_fifo_valid_in, - pos_in_0_fifo_valid_in, pos_in_1_fifo_valid_in}); - clr_eos_sticky[0] = 1'h0; - clr_eos_sticky[1] = 1'h0; - coord_to_fifo = (coord_in_0_fifo_in == done_token) ? done_token[15:0]: semi_done_token[15:0]; - pos_to_fifo[0] = (coord_in_0_fifo_in == done_token) ? done_token[15:0]: semi_done_token[15:0]; - pos_to_fifo[1] = (coord_in_0_fifo_in == done_token) ? done_token[15:0]: semi_done_token[15:0]; - coord_to_fifo_eos = 1'h1; - pos_to_fifo_eos[0] = 1'h1; - pos_to_fifo_eos[1] = 1'h1; - end :intersect_seq_PASS_DONE_Output - UNION: begin :intersect_seq_UNION_Output - pop_fifo[0] = all_are_valid & ((coord_in_0_fifo_in <= coord_in_1_fifo_in) | - coord_in_1_fifo_eos_in) & (~(|fifo_full)) & (~coord_in_0_fifo_eos_in); - pop_fifo[1] = all_are_valid & ((coord_in_0_fifo_in >= coord_in_1_fifo_in) | - coord_in_0_fifo_eos_in) & (~(|fifo_full)) & (~coord_in_1_fifo_eos_in); - fifo_push = all_are_valid & (~(|fifo_full)) & (~all_have_eos); - clr_eos_sticky[0] = 1'h0; - clr_eos_sticky[1] = 1'h0; - coord_to_fifo = pop_fifo[0] ? coord_in_0_fifo_in[15:0]: coord_in_1_fifo_in[15:0]; - pos_to_fifo[0] = pop_fifo[0] ? pos_in_0_fifo_in[15:0]: maybe; - pos_to_fifo[1] = pop_fifo[1] ? pos_in_1_fifo_in[15:0]: maybe; - coord_to_fifo_eos = 1'h0; - pos_to_fifo_eos[0] = (~vector_reduce_mode) & (~pop_fifo[0]); - pos_to_fifo_eos[1] = (~vector_reduce_mode) & (~pop_fifo[1]); - end :intersect_seq_UNION_Output - WAIT_FOR_VALID: begin :intersect_seq_WAIT_FOR_VALID_Output - pop_fifo[0] = 1'h0; - pop_fifo[1] = 1'h0; - fifo_push = 1'h0; - clr_eos_sticky[0] = 1'h0; - clr_eos_sticky[1] = 1'h0; - coord_to_fifo = 16'h0; - pos_to_fifo[0] = 16'h0; - pos_to_fifo[1] = 16'h0; - coord_to_fifo_eos = 1'h0; - pos_to_fifo_eos[0] = 1'h0; - pos_to_fifo_eos[1] = 1'h0; - end :intersect_seq_WAIT_FOR_VALID_Output - default: begin end - endcase -end -reg_fifo_depth_0_w_17_afd_2 coord_in_fifo_0 ( - .clk(gclk), - .clk_en(clk_en), - .data_in(coord_in_0), - .flush(flush), - .pop(pop_fifo[0]), - .push(coord_in_0_valid), - .rst_n(rst_n), - .data_out(coord_in_0_fifo_in), - .empty(coord_in_fifo_0_empty), - .full(coord_in_fifo_0_full) -); - -reg_fifo_depth_0_w_17_afd_2 pos_in_fifo_0 ( - .clk(gclk), - .clk_en(clk_en), - .data_in(pos_in_0), - .flush(flush), - .pop(pop_fifo[0]), - .push(pos_in_0_valid), - .rst_n(rst_n), - .data_out(pos_in_0_fifo_in), - .empty(pos_in_fifo_0_empty), - .full(pos_in_fifo_0_full) -); - -reg_fifo_depth_0_w_17_afd_2 coord_in_fifo_1 ( - .clk(gclk), - .clk_en(clk_en), - .data_in(coord_in_1), - .flush(flush), - .pop(pop_fifo[1]), - .push(coord_in_1_valid), - .rst_n(rst_n), - .data_out(coord_in_1_fifo_in), - .empty(coord_in_fifo_1_empty), - .full(coord_in_fifo_1_full) -); - -reg_fifo_depth_0_w_17_afd_2 pos_in_fifo_1 ( - .clk(gclk), - .clk_en(clk_en), - .data_in(pos_in_1), - .flush(flush), - .pop(pop_fifo[1]), - .push(pos_in_1_valid), - .rst_n(rst_n), - .data_out(pos_in_1_fifo_in), - .empty(pos_in_fifo_1_empty), - .full(pos_in_fifo_1_full) -); - -reg_fifo_depth_0_w_17_afd_2 coordinate_fifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in(coord_fifo_in_packed), - .flush(flush), - .pop(coord_out_ready), - .push(fifo_push), - .rst_n(rst_n), - .data_out(coord_fifo_out_packed), - .empty(coordinate_fifo_empty), - .full(coordinate_fifo_full) -); - -reg_fifo_depth_0_w_17_afd_2 pos0_fifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in(pos0_fifo_in_packed), - .flush(flush), - .pop(pos_out_0_ready), - .push(fifo_push), - .rst_n(rst_n), - .data_out(pos0_fifo_out_packed), - .empty(pos0_fifo_empty), - .full(pos0_fifo_full) -); - -reg_fifo_depth_0_w_17_afd_2 pos1_fifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in(pos1_fifo_in_packed), - .flush(flush), - .pop(pos_out_1_ready), - .push(fifo_push), - .rst_n(rst_n), - .data_out(pos1_fifo_out_packed), - .empty(pos1_fifo_empty), - .full(pos1_fifo_full) -); - -endmodule // intersect_unit - -module intersect_unit_flat ( - input logic clk, - input logic clk_en, - input logic [0:0] [16:0] coord_in_0_f_, - input logic coord_in_0_valid_f_, - input logic [0:0] [16:0] coord_in_1_f_, - input logic coord_in_1_valid_f_, - input logic coord_out_ready_f_, - input logic flush, - input logic intersect_unit_inst_joiner_op, - input logic intersect_unit_inst_tile_en, - input logic intersect_unit_inst_vector_reduce_mode, - input logic [0:0] [16:0] pos_in_0_f_, - input logic pos_in_0_valid_f_, - input logic [0:0] [16:0] pos_in_1_f_, - input logic pos_in_1_valid_f_, - input logic pos_out_0_ready_f_, - input logic pos_out_1_ready_f_, - input logic rst_n, - output logic coord_in_0_ready_f_, - output logic coord_in_1_ready_f_, - output logic [0:0] [16:0] coord_out_f_, - output logic coord_out_valid_f_, - output logic pos_in_0_ready_f_, - output logic pos_in_1_ready_f_, - output logic [0:0] [16:0] pos_out_0_f_, - output logic pos_out_0_valid_f_, - output logic [0:0] [16:0] pos_out_1_f_, - output logic pos_out_1_valid_f_ -); - -intersect_unit intersect_unit_inst ( - .clk(clk), - .clk_en(clk_en), - .coord_in_0(coord_in_0_f_), - .coord_in_0_valid(coord_in_0_valid_f_), - .coord_in_1(coord_in_1_f_), - .coord_in_1_valid(coord_in_1_valid_f_), - .coord_out_ready(coord_out_ready_f_), - .flush(flush), - .joiner_op(intersect_unit_inst_joiner_op), - .pos_in_0(pos_in_0_f_), - .pos_in_0_valid(pos_in_0_valid_f_), - .pos_in_1(pos_in_1_f_), - .pos_in_1_valid(pos_in_1_valid_f_), - .pos_out_0_ready(pos_out_0_ready_f_), - .pos_out_1_ready(pos_out_1_ready_f_), - .rst_n(rst_n), - .tile_en(intersect_unit_inst_tile_en), - .vector_reduce_mode(intersect_unit_inst_vector_reduce_mode), - .coord_in_0_ready(coord_in_0_ready_f_), - .coord_in_1_ready(coord_in_1_ready_f_), - .coord_out(coord_out_f_), - .coord_out_valid(coord_out_valid_f_), - .pos_in_0_ready(pos_in_0_ready_f_), - .pos_in_1_ready(pos_in_1_ready_f_), - .pos_out_0(pos_out_0_f_), - .pos_out_0_valid(pos_out_0_valid_f_), - .pos_out_1(pos_out_1_f_), - .pos_out_1_valid(pos_out_1_valid_f_) -); - -endmodule // intersect_unit_flat - -module reduce_pe_cluster ( - input logic bit0, - input logic bit1, - input logic bit2, - input logic clk, - input logic clk_en, - input logic [16:0] data0, - input logic data0_valid, - input logic [16:0] data1, - input logic data1_valid, - input logic [16:0] data2, - input logic data2_valid, - input logic flush, - input logic pe_dense_mode, - input logic pe_in_external, - input logic [83:0] pe_onyxpeintf_inst, - input logic [2:0] pe_sparse_num_inputs, - input logic pe_tile_en, - input logic [16:0] reduce_data_in, - input logic reduce_data_in_valid, - input logic reduce_data_out_ready, - input logic [15:0] reduce_default_value, - input logic [15:0] reduce_stop_lvl, - input logic reduce_tile_en, - input logic res_ready, - input logic rst_n, - input logic tile_en, - output logic data0_ready, - output logic data1_ready, - output logic data2_ready, - output logic [15:0] pe_onyxpeintf_O2, - output logic [15:0] pe_onyxpeintf_O3, - output logic [15:0] pe_onyxpeintf_O4, - output logic reduce_data_in_ready, - output logic [16:0] reduce_data_out, - output logic reduce_data_out_valid, - output logic [16:0] res, - output logic res_p, - output logic res_valid -); - -logic gclk; -logic [16:0] pe_data0; -logic [16:0] pe_data1; -logic [16:0] pe_data2; -logic [16:0] pe_data_to_reduce; -logic [16:0] pe_res; -logic [16:0] reduce_data_to_pe0; -logic [16:0] reduce_data_to_pe1; -assign gclk = clk & tile_en; -assign res = pe_res; -assign pe_data0 = pe_in_external ? data0: reduce_data_to_pe0; -assign pe_data1 = pe_in_external ? data1: reduce_data_to_pe1; -assign pe_data2 = data2; -assign pe_data_to_reduce = pe_res; -reg_cr reduce ( - .clk(gclk), - .clk_en(clk_en), - .data_from_pe(pe_data_to_reduce), - .data_in(reduce_data_in), - .data_in_valid(reduce_data_in_valid), - .data_out_ready(reduce_data_out_ready), - .default_value(reduce_default_value), - .flush(flush), - .rst_n(rst_n), - .stop_lvl(reduce_stop_lvl), - .tile_en(reduce_tile_en), - .data_in_ready(reduce_data_in_ready), - .data_out(reduce_data_out), - .data_out_valid(reduce_data_out_valid), - .data_to_pe0(reduce_data_to_pe0), - .data_to_pe1(reduce_data_to_pe1) -); - -PE_onyx pe ( - .bit0(bit0), - .bit1(bit1), - .bit2(bit2), - .clk(gclk), - .clk_en(clk_en), - .data0(pe_data0), - .data0_valid(data0_valid), - .data1(pe_data1), - .data1_valid(data1_valid), - .data2(pe_data2), - .data2_valid(data2_valid), - .dense_mode(pe_dense_mode), - .flush(flush), - .onyxpeintf_inst(pe_onyxpeintf_inst), - .res_ready(res_ready), - .rst_n(rst_n), - .sparse_num_inputs(pe_sparse_num_inputs), - .tile_en(pe_tile_en), - .data0_ready(data0_ready), - .data1_ready(data1_ready), - .data2_ready(data2_ready), - .onyxpeintf_O2(pe_onyxpeintf_O2), - .onyxpeintf_O3(pe_onyxpeintf_O3), - .onyxpeintf_O4(pe_onyxpeintf_O4), - .res(pe_res), - .res_p(res_p), - .res_valid(res_valid) -); - -endmodule // reduce_pe_cluster - -module reduce_pe_cluster_flat ( - input logic bit0_f_, - input logic bit1_f_, - input logic bit2_f_, - input logic clk, - input logic clk_en, - input logic [0:0] [16:0] data0_f_, - input logic data0_valid_f_, - input logic [0:0] [16:0] data1_f_, - input logic data1_valid_f_, - input logic [0:0] [16:0] data2_f_, - input logic data2_valid_f_, - input logic flush, - input logic [0:0] [16:0] reduce_data_in_f_, - input logic reduce_data_in_valid_f_, - input logic reduce_data_out_ready_f_, - input logic reduce_pe_cluster_inst_pe_dense_mode, - input logic reduce_pe_cluster_inst_pe_in_external, - input logic [83:0] reduce_pe_cluster_inst_pe_onyxpeintf_inst, - input logic [2:0] reduce_pe_cluster_inst_pe_sparse_num_inputs, - input logic reduce_pe_cluster_inst_pe_tile_en, - input logic [15:0] reduce_pe_cluster_inst_reduce_default_value, - input logic [15:0] reduce_pe_cluster_inst_reduce_stop_lvl, - input logic reduce_pe_cluster_inst_reduce_tile_en, - input logic reduce_pe_cluster_inst_tile_en, - input logic res_ready_f_, - input logic rst_n, - output logic data0_ready_f_, - output logic data1_ready_f_, - output logic data2_ready_f_, - output logic reduce_data_in_ready_f_, - output logic [0:0] [16:0] reduce_data_out_f_, - output logic reduce_data_out_valid_f_, - output logic [15:0] reduce_pe_cluster_inst_pe_onyxpeintf_O2, - output logic [15:0] reduce_pe_cluster_inst_pe_onyxpeintf_O3, - output logic [15:0] reduce_pe_cluster_inst_pe_onyxpeintf_O4, - output logic [0:0] [16:0] res_f_, - output logic res_p_f_, - output logic res_valid_f_ -); - -reduce_pe_cluster reduce_pe_cluster_inst ( - .bit0(bit0_f_), - .bit1(bit1_f_), - .bit2(bit2_f_), - .clk(clk), - .clk_en(clk_en), - .data0(data0_f_), - .data0_valid(data0_valid_f_), - .data1(data1_f_), - .data1_valid(data1_valid_f_), - .data2(data2_f_), - .data2_valid(data2_valid_f_), - .flush(flush), - .pe_dense_mode(reduce_pe_cluster_inst_pe_dense_mode), - .pe_in_external(reduce_pe_cluster_inst_pe_in_external), - .pe_onyxpeintf_inst(reduce_pe_cluster_inst_pe_onyxpeintf_inst), - .pe_sparse_num_inputs(reduce_pe_cluster_inst_pe_sparse_num_inputs), - .pe_tile_en(reduce_pe_cluster_inst_pe_tile_en), - .reduce_data_in(reduce_data_in_f_), - .reduce_data_in_valid(reduce_data_in_valid_f_), - .reduce_data_out_ready(reduce_data_out_ready_f_), - .reduce_default_value(reduce_pe_cluster_inst_reduce_default_value), - .reduce_stop_lvl(reduce_pe_cluster_inst_reduce_stop_lvl), - .reduce_tile_en(reduce_pe_cluster_inst_reduce_tile_en), - .res_ready(res_ready_f_), - .rst_n(rst_n), - .tile_en(reduce_pe_cluster_inst_tile_en), - .data0_ready(data0_ready_f_), - .data1_ready(data1_ready_f_), - .data2_ready(data2_ready_f_), - .pe_onyxpeintf_O2(reduce_pe_cluster_inst_pe_onyxpeintf_O2), - .pe_onyxpeintf_O3(reduce_pe_cluster_inst_pe_onyxpeintf_O3), - .pe_onyxpeintf_O4(reduce_pe_cluster_inst_pe_onyxpeintf_O4), - .reduce_data_in_ready(reduce_data_in_ready_f_), - .reduce_data_out(reduce_data_out_f_), - .reduce_data_out_valid(reduce_data_out_valid_f_), - .res(res_f_), - .res_p(res_p_f_), - .res_valid(res_valid_f_) -); - -endmodule // reduce_pe_cluster_flat - -module reg_cr ( - input logic clk, - input logic clk_en, - input logic [16:0] data_from_pe, - input logic [16:0] data_in, - input logic data_in_valid, - input logic data_out_ready, - input logic [15:0] default_value, - input logic flush, - input logic rst_n, - input logic [15:0] stop_lvl, - input logic tile_en, - output logic data_in_ready, - output logic [16:0] data_out, - output logic data_out_valid, - output logic [16:0] data_to_pe0, - output logic [16:0] data_to_pe1 -); - -typedef enum logic[2:0] { - ACCUM = 3'h0, - DONE = 3'h1, - OUTPUT = 3'h2, - START = 3'h3, - STOP_PASS = 3'h4 -} accum_seq_state; -logic [15:0] accum_reg; -accum_seq_state accum_seq_current_state; -accum_seq_state accum_seq_next_state; -logic [15:0] data_to_fifo; -logic gclk; -logic [16:0] infifo_in_packed; -logic [15:0] infifo_out_data; -logic infifo_out_eos; -logic [16:0] infifo_out_packed; -logic infifo_out_valid; -logic infifo_pop; -logic infifo_push; -logic input_fifo_empty; -logic input_fifo_full; -logic outfifo_full; -logic outfifo_in_eos; -logic [16:0] outfifo_in_packed; -logic [16:0] outfifo_out_packed; -logic outfifo_pop; -logic outfifo_push; -logic output_fifo_empty; -logic reg_clr; -logic update_accum_reg; -assign gclk = clk & tile_en; -assign data_in_ready = ~input_fifo_full; -assign infifo_in_packed[16:0] = data_in; -assign infifo_out_eos = infifo_out_packed[16]; -assign infifo_out_data = infifo_out_packed[15:0]; -assign infifo_push = data_in_valid; -assign infifo_out_valid = ~input_fifo_empty; -assign data_to_pe0 = infifo_out_packed; -assign data_to_pe1[15:0] = accum_reg; -assign data_to_pe1[16] = 1'h0; -assign outfifo_in_packed[16] = outfifo_in_eos; -assign outfifo_in_packed[15:0] = data_to_fifo; -assign data_out = outfifo_out_packed[16:0]; -assign data_out_valid = ~output_fifo_empty; -assign outfifo_pop = data_out_ready; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - accum_reg <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - accum_reg <= 16'h0; - end - else if (reg_clr) begin - accum_reg <= default_value; - end - else if (update_accum_reg) begin - accum_reg <= data_from_pe[15:0]; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (!rst_n) begin - accum_seq_current_state <= START; - end - else if (clk_en) begin - if (flush) begin - accum_seq_current_state <= START; - end - else accum_seq_current_state <= accum_seq_next_state; - end -end -always_comb begin - accum_seq_next_state = accum_seq_current_state; - unique case (accum_seq_current_state) - ACCUM: begin - if (infifo_out_valid & infifo_out_eos) begin - accum_seq_next_state = OUTPUT; - end - else accum_seq_next_state = ACCUM; - end - DONE: begin - if (~outfifo_full) begin - accum_seq_next_state = START; - end - else accum_seq_next_state = DONE; - end - OUTPUT: begin - if (~outfifo_full) begin - accum_seq_next_state = STOP_PASS; - end - else accum_seq_next_state = OUTPUT; - end - START: begin - if (infifo_out_valid & (~infifo_out_eos)) begin - accum_seq_next_state = ACCUM; - end - else if (infifo_out_valid & infifo_out_eos & (infifo_out_data[9:8] == 2'h1)) begin - accum_seq_next_state = DONE; - end - else if (infifo_out_valid & infifo_out_eos & (infifo_out_data[9:8] == 2'h0)) begin - accum_seq_next_state = OUTPUT; - end - else accum_seq_next_state = START; - end - STOP_PASS: begin - if (~outfifo_full) begin - accum_seq_next_state = START; - end - else accum_seq_next_state = STOP_PASS; - end - default: accum_seq_next_state = accum_seq_current_state; - endcase -end -always_comb begin - unique case (accum_seq_current_state) - ACCUM: begin :accum_seq_ACCUM_Output - infifo_pop = infifo_out_valid & (~infifo_out_eos); - outfifo_push = 1'h0; - data_to_fifo = 16'h0; - outfifo_in_eos = 1'h0; - reg_clr = 1'h0; - update_accum_reg = infifo_out_valid & (~infifo_out_eos); - end :accum_seq_ACCUM_Output - DONE: begin :accum_seq_DONE_Output - infifo_pop = ~outfifo_full; - outfifo_push = ~outfifo_full; - reg_clr = 1'h1; - data_to_fifo = infifo_out_data; - outfifo_in_eos = infifo_out_eos; - update_accum_reg = 1'h0; - end :accum_seq_DONE_Output - OUTPUT: begin :accum_seq_OUTPUT_Output - infifo_pop = 1'h0; - outfifo_push = ~outfifo_full; - reg_clr = 1'h0; - data_to_fifo = accum_reg; - outfifo_in_eos = 1'h0; - update_accum_reg = 1'h0; - end :accum_seq_OUTPUT_Output - START: begin :accum_seq_START_Output - infifo_pop = 1'h0; - outfifo_push = 1'h0; - data_to_fifo = 16'h0; - outfifo_in_eos = 1'h0; - reg_clr = 1'h0; - update_accum_reg = 1'h0; - end :accum_seq_START_Output - STOP_PASS: begin :accum_seq_STOP_PASS_Output - infifo_pop = (~outfifo_full) & infifo_out_valid & infifo_out_eos & (infifo_out_data[9:8] == - 2'h0); - outfifo_push = (~outfifo_full) & infifo_out_valid & infifo_out_eos & (infifo_out_data[9:8] == - 2'h0) & (infifo_out_data[7:0] > 8'h0); - reg_clr = 1'h1; - data_to_fifo = infifo_out_data - 16'h1; - outfifo_in_eos = 1'h1; - update_accum_reg = 1'h0; - end :accum_seq_STOP_PASS_Output - default: begin :accum_seq_default_Output - infifo_pop = 1'h0; - outfifo_push = 1'h0; - data_to_fifo = 16'h0; - outfifo_in_eos = 1'h0; - reg_clr = 1'h0; - update_accum_reg = 1'h0; - end :accum_seq_default_Output - endcase -end -reg_fifo_depth_0_w_17_afd_2 input_fifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in(infifo_in_packed), - .flush(flush), - .pop(infifo_pop), - .push(infifo_push), - .rst_n(rst_n), - .data_out(infifo_out_packed), - .empty(input_fifo_empty), - .full(input_fifo_full) -); - -reg_fifo_depth_0_w_17_afd_2 output_fifo ( - .clk(gclk), - .clk_en(clk_en), - .data_in(outfifo_in_packed), - .flush(flush), - .pop(outfifo_pop), - .push(outfifo_push), - .rst_n(rst_n), - .data_out(outfifo_out_packed), - .empty(output_fifo_empty), - .full(outfifo_full) -); - -endmodule // reg_cr - -module reg_fifo_depth_0_w_17_afd_2 ( - input logic clk, - input logic clk_en, - input logic [0:0] [16:0] data_in, - input logic flush, - input logic pop, - input logic push, - input logic rst_n, - output logic almost_full, - output logic [0:0] [16:0] data_out, - output logic empty, - output logic full, - output logic valid -); - -assign data_out = data_in; -assign valid = push; -assign empty = ~push; -assign full = ~pop; -assign almost_full = ~pop; -endmodule // reg_fifo_depth_0_w_17_afd_2 - -module reg_fifo_depth_2_w_17_afd_2 ( - input logic clk, - input logic clk_en, - input logic [0:0] [16:0] data_in, - input logic flush, - input logic pop, - input logic push, - input logic rst_n, - output logic almost_full, - output logic [0:0] [16:0] data_out, - output logic empty, - output logic full, - output logic valid -); - -logic [1:0] num_items; -logic passthru; -logic rd_ptr; -logic read; -logic [1:0][0:0][16:0] reg_array; -logic wr_ptr; -logic write; -assign full = num_items == 2'h2; -assign almost_full = num_items >= 2'h0; -assign empty = num_items == 2'h0; -assign read = pop & (~passthru) & (~empty); -assign passthru = 1'h0; -assign write = push & (~passthru) & (~full); - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - num_items <= 2'h0; - end - else if (flush) begin - num_items <= 2'h0; - end - else if (clk_en) begin - if (write & (~read)) begin - num_items <= num_items + 2'h1; - end - else if ((~write) & read) begin - num_items <= num_items - 2'h1; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - reg_array <= 34'h0; - end - else if (flush) begin - reg_array <= 34'h0; - end - else if (clk_en) begin - if (write) begin - reg_array[wr_ptr] <= data_in; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - wr_ptr <= 1'h0; - end - else if (flush) begin - wr_ptr <= 1'h0; - end - else if (clk_en) begin - if (write) begin - if (wr_ptr == 1'h1) begin - wr_ptr <= 1'h0; - end - else wr_ptr <= wr_ptr + 1'h1; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - rd_ptr <= 1'h0; - end - else if (flush) begin - rd_ptr <= 1'h0; - end - else if (clk_en) begin - if (read) begin - rd_ptr <= rd_ptr + 1'h1; - end - end -end -always_comb begin - if (passthru) begin - data_out = data_in; - end - else data_out = reg_array[rd_ptr]; -end -always_comb begin - valid = (~empty) | passthru; -end -endmodule // reg_fifo_depth_2_w_17_afd_2 - diff --git a/sam/onyx/.magma/PondTop_W-kratos.sv b/sam/onyx/.magma/PondTop_W-kratos.sv deleted file mode 100644 index f23d7e2e..00000000 --- a/sam/onyx/.magma/PondTop_W-kratos.sv +++ /dev/null @@ -1,1362 +0,0 @@ -module PondTop ( - input logic [31:0] CONFIG_SPACE_0, - input logic [31:0] CONFIG_SPACE_1, - input logic [31:0] CONFIG_SPACE_10, - input logic [31:0] CONFIG_SPACE_11, - input logic [31:0] CONFIG_SPACE_12, - input logic [31:0] CONFIG_SPACE_13, - input logic [31:0] CONFIG_SPACE_14, - input logic [31:0] CONFIG_SPACE_15, - input logic [29:0] CONFIG_SPACE_16, - input logic [31:0] CONFIG_SPACE_2, - input logic [31:0] CONFIG_SPACE_3, - input logic [31:0] CONFIG_SPACE_4, - input logic [31:0] CONFIG_SPACE_5, - input logic [31:0] CONFIG_SPACE_6, - input logic [31:0] CONFIG_SPACE_7, - input logic [31:0] CONFIG_SPACE_8, - input logic [31:0] CONFIG_SPACE_9, - input logic [0:0] [16:0] PondTop_input_width_17_num_0, - input logic [0:0] [16:0] PondTop_input_width_17_num_1, - input logic clk, - input logic clk_en, - input logic [7:0] config_addr_in, - input logic [31:0] config_data_in, - input logic config_en, - input logic config_read, - input logic config_write, - input logic flush, - input logic rst_n, - input logic tile_en, - output logic [0:0] [16:0] PondTop_output_width_17_num_0, - output logic [0:0] [16:0] PondTop_output_width_17_num_1, - output logic PondTop_output_width_1_num_0, - output logic PondTop_output_width_1_num_1, - output logic [0:0] [31:0] config_data_out -); - -logic [541:0] CONFIG_SPACE; -logic [15:0] config_data_in_shrt; -logic [0:0][15:0] config_data_out_shrt; -logic [4:0] config_seq_addr_out; -logic config_seq_clk_en; -logic [0:0][0:0][15:0] config_seq_rd_data_stg; -logic config_seq_ren_out; -logic config_seq_wen_out; -logic [0:0][15:0] config_seq_wr_data; -logic gclk; -logic mem_ctrl_strg_ub_thin_PondTop_flat_clk; -logic [0:0][16:0] mem_ctrl_strg_ub_thin_PondTop_flat_data_out_f_0; -logic [0:0][16:0] mem_ctrl_strg_ub_thin_PondTop_flat_data_out_f_1; -logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_data_from_strg_lifted; -logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_data_to_strg_lifted; -logic [4:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_starting_addr; -logic [4:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_starting_addr2; -logic [4:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides2_0; -logic [4:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides2_1; -logic [4:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_0; -logic [4:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_1; -logic [4:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_2; -logic [4:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_3; -logic [2:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_dimensionality; -logic [1:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_dimensionality2; -logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges2_0; -logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges2_1; -logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_0; -logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_1; -logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_2; -logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_3; -logic mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_enable; -logic mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_enable2; -logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_starting_addr; -logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_starting_addr2; -logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides2_0; -logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides2_1; -logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_0; -logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_1; -logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_2; -logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_3; -logic [4:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_rd_addr_out_lifted; -logic [4:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_starting_addr; -logic [4:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_starting_addr2; -logic [4:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides2_0; -logic [4:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides2_1; -logic [4:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_0; -logic [4:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_1; -logic [4:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_2; -logic [4:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_3; -logic [2:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_dimensionality; -logic [1:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_dimensionality2; -logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges2_0; -logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges2_1; -logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_0; -logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_1; -logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_2; -logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_3; -logic mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_enable; -logic mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_enable2; -logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_starting_addr; -logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_starting_addr2; -logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides2_0; -logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides2_1; -logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_0; -logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_1; -logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_2; -logic [15:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_3; -logic mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_ren_to_strg_lifted; -logic [4:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_tmp0_rdaddr_lifted; -logic mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_tmp0_rden_lifted; -logic mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_wen_to_strg_lifted; -logic [4:0] mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_wr_addr_out_lifted; -logic mem_ctrl_strg_ub_thin_PondTop_flat_valid_out_f_b_0; -logic mem_ctrl_strg_ub_thin_PondTop_flat_valid_out_f_b_1; -logic memory_0_clk_en; -logic [15:0] memory_0_data_in_p0; -logic [15:0] memory_0_data_out_p0; -logic [15:0] memory_0_data_out_p1; -logic [4:0] memory_0_read_addr_p0; -logic [4:0] memory_0_read_addr_p1; -logic memory_0_read_enable_p0; -logic memory_0_read_enable_p1; -logic [4:0] memory_0_write_addr_p0; -logic memory_0_write_enable_p0; -logic mode; -assign mode = 1'h0; -assign gclk = clk & tile_en; -assign mem_ctrl_strg_ub_thin_PondTop_flat_clk = gclk; -always_comb begin - PondTop_output_width_17_num_0 = 17'h0; - if (1'h0 == mode) begin - PondTop_output_width_17_num_0 = mem_ctrl_strg_ub_thin_PondTop_flat_data_out_f_0; - end - else PondTop_output_width_17_num_0 = 17'h0; -end -always_comb begin - PondTop_output_width_17_num_1 = 17'h0; - if (1'h0 == mode) begin - PondTop_output_width_17_num_1 = mem_ctrl_strg_ub_thin_PondTop_flat_data_out_f_1; - end - else PondTop_output_width_17_num_1 = 17'h0; -end -always_comb begin - PondTop_output_width_1_num_0 = 1'h0; - if (1'h0 == mode) begin - PondTop_output_width_1_num_0 = mem_ctrl_strg_ub_thin_PondTop_flat_valid_out_f_b_0; - end - else PondTop_output_width_1_num_0 = 1'h0; -end -always_comb begin - PondTop_output_width_1_num_1 = 1'h0; - if (1'h0 == mode) begin - PondTop_output_width_1_num_1 = mem_ctrl_strg_ub_thin_PondTop_flat_valid_out_f_b_1; - end - else PondTop_output_width_1_num_1 = 1'h0; -end -always_comb begin - memory_0_data_in_p0 = 16'h0; - memory_0_write_addr_p0 = 5'h0; - memory_0_write_enable_p0 = 1'h0; - memory_0_read_addr_p0 = 5'h0; - memory_0_read_enable_p0 = 1'h0; - if (|config_en) begin - memory_0_data_in_p0 = config_seq_wr_data; - memory_0_write_addr_p0 = config_seq_addr_out; - memory_0_write_enable_p0 = config_seq_wen_out; - memory_0_read_addr_p0 = config_seq_addr_out; - memory_0_read_enable_p0 = config_seq_ren_out; - end - else if (1'h0 == mode) begin - memory_0_data_in_p0 = mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_data_to_strg_lifted; - memory_0_write_addr_p0 = mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_wr_addr_out_lifted; - memory_0_write_enable_p0 = mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_wen_to_strg_lifted; - memory_0_read_addr_p0 = mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_tmp0_rdaddr_lifted; - memory_0_read_enable_p0 = mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_tmp0_rden_lifted; - end -end -always_comb begin - config_seq_rd_data_stg = memory_0_data_out_p0; -end -always_comb begin - memory_0_read_addr_p1 = 5'h0; - memory_0_read_enable_p1 = 1'h0; - if (1'h0 == mode) begin - memory_0_read_addr_p1 = mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_rd_addr_out_lifted; - memory_0_read_enable_p1 = mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_ren_to_strg_lifted; - end -end -always_comb begin - mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_data_from_strg_lifted = memory_0_data_out_p1; -end -assign config_data_in_shrt = config_data_in[15:0]; -assign config_data_out[0] = 32'(config_data_out_shrt[0]); -assign config_seq_clk_en = clk_en | (|config_en); -assign memory_0_clk_en = clk_en | (|config_en); -assign {mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_starting_addr, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_starting_addr2, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides2_0, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides2_1, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_0, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_1, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_2, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_3, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_dimensionality, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_dimensionality2, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges2_0, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges2_1, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_0, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_1, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_2, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_3, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_enable, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_enable2, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_starting_addr, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_starting_addr2, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides2_0, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides2_1, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_0, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_1, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_2, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_3, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_starting_addr, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_starting_addr2, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides2_0, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides2_1, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_0, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_1, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_2, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_3, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_dimensionality, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_dimensionality2, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges2_0, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges2_1, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_0, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_1, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_2, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_3, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_enable, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_enable2, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_starting_addr, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_starting_addr2, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides2_0, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides2_1, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_0, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_1, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_2, mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_3} = CONFIG_SPACE[541:0]; -assign CONFIG_SPACE[31:0] = CONFIG_SPACE_0; -assign CONFIG_SPACE[63:32] = CONFIG_SPACE_1; -assign CONFIG_SPACE[95:64] = CONFIG_SPACE_2; -assign CONFIG_SPACE[127:96] = CONFIG_SPACE_3; -assign CONFIG_SPACE[159:128] = CONFIG_SPACE_4; -assign CONFIG_SPACE[191:160] = CONFIG_SPACE_5; -assign CONFIG_SPACE[223:192] = CONFIG_SPACE_6; -assign CONFIG_SPACE[255:224] = CONFIG_SPACE_7; -assign CONFIG_SPACE[287:256] = CONFIG_SPACE_8; -assign CONFIG_SPACE[319:288] = CONFIG_SPACE_9; -assign CONFIG_SPACE[351:320] = CONFIG_SPACE_10; -assign CONFIG_SPACE[383:352] = CONFIG_SPACE_11; -assign CONFIG_SPACE[415:384] = CONFIG_SPACE_12; -assign CONFIG_SPACE[447:416] = CONFIG_SPACE_13; -assign CONFIG_SPACE[479:448] = CONFIG_SPACE_14; -assign CONFIG_SPACE[511:480] = CONFIG_SPACE_15; -assign CONFIG_SPACE[541:512] = CONFIG_SPACE_16; -strg_ub_thin_PondTop_flat mem_ctrl_strg_ub_thin_PondTop_flat ( - .clk(mem_ctrl_strg_ub_thin_PondTop_flat_clk), - .clk_en(clk_en), - .data_in_f_0(PondTop_input_width_17_num_0), - .data_in_f_1(PondTop_input_width_17_num_1), - .flush(flush), - .rst_n(rst_n), - .strg_ub_thin_PondTop_inst_data_from_strg_lifted(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_data_from_strg_lifted), - .strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_starting_addr(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_starting_addr), - .strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_starting_addr2(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_starting_addr2), - .strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides2_0(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides2_0), - .strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides2_1(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides2_1), - .strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_0(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_0), - .strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_1(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_1), - .strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_2(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_2), - .strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_3(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_3), - .strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_dimensionality(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_dimensionality), - .strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_dimensionality2(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_dimensionality2), - .strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges2_0(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges2_0), - .strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges2_1(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges2_1), - .strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_0(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_0), - .strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_1(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_1), - .strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_2(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_2), - .strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_3(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_3), - .strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_enable(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_enable), - .strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_enable2(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_enable2), - .strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_starting_addr(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_starting_addr), - .strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_starting_addr2(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_starting_addr2), - .strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides2_0(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides2_0), - .strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides2_1(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides2_1), - .strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_0(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_0), - .strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_1(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_1), - .strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_2(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_2), - .strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_3(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_3), - .strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_starting_addr(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_starting_addr), - .strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_starting_addr2(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_starting_addr2), - .strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides2_0(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides2_0), - .strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides2_1(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides2_1), - .strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_0(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_0), - .strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_1(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_1), - .strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_2(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_2), - .strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_3(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_3), - .strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_dimensionality(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_dimensionality), - .strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_dimensionality2(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_dimensionality2), - .strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges2_0(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges2_0), - .strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges2_1(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges2_1), - .strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_0(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_0), - .strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_1(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_1), - .strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_2(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_2), - .strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_3(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_3), - .strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_enable(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_enable), - .strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_enable2(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_enable2), - .strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_starting_addr(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_starting_addr), - .strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_starting_addr2(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_starting_addr2), - .strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides2_0(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides2_0), - .strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides2_1(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides2_1), - .strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_0(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_0), - .strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_1(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_1), - .strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_2(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_2), - .strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_3(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_3), - .data_out_f_0(mem_ctrl_strg_ub_thin_PondTop_flat_data_out_f_0), - .data_out_f_1(mem_ctrl_strg_ub_thin_PondTop_flat_data_out_f_1), - .strg_ub_thin_PondTop_inst_data_to_strg_lifted(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_data_to_strg_lifted), - .strg_ub_thin_PondTop_inst_rd_addr_out_lifted(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_rd_addr_out_lifted), - .strg_ub_thin_PondTop_inst_ren_to_strg_lifted(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_ren_to_strg_lifted), - .strg_ub_thin_PondTop_inst_tmp0_rdaddr_lifted(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_tmp0_rdaddr_lifted), - .strg_ub_thin_PondTop_inst_tmp0_rden_lifted(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_tmp0_rden_lifted), - .strg_ub_thin_PondTop_inst_wen_to_strg_lifted(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_wen_to_strg_lifted), - .strg_ub_thin_PondTop_inst_wr_addr_out_lifted(mem_ctrl_strg_ub_thin_PondTop_flat_strg_ub_thin_PondTop_inst_wr_addr_out_lifted), - .valid_out_f_b_0(mem_ctrl_strg_ub_thin_PondTop_flat_valid_out_f_b_0), - .valid_out_f_b_1(mem_ctrl_strg_ub_thin_PondTop_flat_valid_out_f_b_1) -); - -sram_dp__0 memory_0 ( - .clk(gclk), - .clk_en(memory_0_clk_en), - .data_in_p0(memory_0_data_in_p0), - .flush(flush), - .read_addr_p0(memory_0_read_addr_p0), - .read_addr_p1(memory_0_read_addr_p1), - .read_enable_p0(memory_0_read_enable_p0), - .read_enable_p1(memory_0_read_enable_p1), - .write_addr_p0(memory_0_write_addr_p0), - .write_enable_p0(memory_0_write_enable_p0), - .data_out_p0(memory_0_data_out_p0), - .data_out_p1(memory_0_data_out_p1) -); - -storage_config_seq_1_16_16 config_seq ( - .clk(gclk), - .clk_en(config_seq_clk_en), - .config_addr_in(config_addr_in), - .config_data_in(config_data_in_shrt), - .config_en(config_en), - .config_rd(config_read), - .config_wr(config_write), - .flush(flush), - .rd_data_stg(config_seq_rd_data_stg), - .rst_n(rst_n), - .addr_out(config_seq_addr_out), - .rd_data_out(config_data_out_shrt), - .ren_out(config_seq_ren_out), - .wen_out(config_seq_wen_out), - .wr_data(config_seq_wr_data) -); - -endmodule // PondTop - -module PondTop_W ( - input logic [31:0] CONFIG_SPACE_0, - input logic [31:0] CONFIG_SPACE_1, - input logic [31:0] CONFIG_SPACE_10, - input logic [31:0] CONFIG_SPACE_11, - input logic [31:0] CONFIG_SPACE_12, - input logic [31:0] CONFIG_SPACE_13, - input logic [31:0] CONFIG_SPACE_14, - input logic [31:0] CONFIG_SPACE_15, - input logic [29:0] CONFIG_SPACE_16, - input logic [31:0] CONFIG_SPACE_2, - input logic [31:0] CONFIG_SPACE_3, - input logic [31:0] CONFIG_SPACE_4, - input logic [31:0] CONFIG_SPACE_5, - input logic [31:0] CONFIG_SPACE_6, - input logic [31:0] CONFIG_SPACE_7, - input logic [31:0] CONFIG_SPACE_8, - input logic [31:0] CONFIG_SPACE_9, - input logic [0:0] [16:0] PondTop_input_width_17_num_0, - input logic [0:0] [16:0] PondTop_input_width_17_num_1, - input logic clk, - input logic clk_en, - input logic [7:0] config_addr_in, - input logic [31:0] config_data_in, - input logic config_en, - input logic config_read, - input logic config_write, - input logic flush, - input logic rst_n, - input logic tile_en, - output logic [0:0] [16:0] PondTop_output_width_17_num_0, - output logic [0:0] [16:0] PondTop_output_width_17_num_1, - output logic PondTop_output_width_1_num_0, - output logic PondTop_output_width_1_num_1, - output logic [0:0] [31:0] config_data_out -); - -PondTop PondTop ( - .CONFIG_SPACE_0(CONFIG_SPACE_0), - .CONFIG_SPACE_1(CONFIG_SPACE_1), - .CONFIG_SPACE_10(CONFIG_SPACE_10), - .CONFIG_SPACE_11(CONFIG_SPACE_11), - .CONFIG_SPACE_12(CONFIG_SPACE_12), - .CONFIG_SPACE_13(CONFIG_SPACE_13), - .CONFIG_SPACE_14(CONFIG_SPACE_14), - .CONFIG_SPACE_15(CONFIG_SPACE_15), - .CONFIG_SPACE_16(CONFIG_SPACE_16), - .CONFIG_SPACE_2(CONFIG_SPACE_2), - .CONFIG_SPACE_3(CONFIG_SPACE_3), - .CONFIG_SPACE_4(CONFIG_SPACE_4), - .CONFIG_SPACE_5(CONFIG_SPACE_5), - .CONFIG_SPACE_6(CONFIG_SPACE_6), - .CONFIG_SPACE_7(CONFIG_SPACE_7), - .CONFIG_SPACE_8(CONFIG_SPACE_8), - .CONFIG_SPACE_9(CONFIG_SPACE_9), - .PondTop_input_width_17_num_0(PondTop_input_width_17_num_0), - .PondTop_input_width_17_num_1(PondTop_input_width_17_num_1), - .clk(clk), - .clk_en(clk_en), - .config_addr_in(config_addr_in), - .config_data_in(config_data_in), - .config_en(config_en), - .config_read(config_read), - .config_write(config_write), - .flush(flush), - .rst_n(rst_n), - .tile_en(tile_en), - .PondTop_output_width_17_num_0(PondTop_output_width_17_num_0), - .PondTop_output_width_17_num_1(PondTop_output_width_17_num_1), - .PondTop_output_width_1_num_0(PondTop_output_width_1_num_0), - .PondTop_output_width_1_num_1(PondTop_output_width_1_num_1), - .config_data_out(config_data_out) -); - -endmodule // PondTop_W - -module addr_gen_4_16_dual_config_2 ( - input logic clk, - input logic clk_en, - input logic flush, - input logic [2:0] mux_sel, - input logic mux_sel_msb_init, - input logic restart, - input logic rst_n, - input logic [15:0] starting_addr, - input logic [15:0] starting_addr2, - input logic step, - input logic [3:0] [15:0] strides, - input logic [1:0] [15:0] strides2, - output logic [15:0] addr_out, - output logic starting_addr_comp -); - -logic [15:0] calc_addr; -logic [15:0] cur_stride; -logic [15:0] current_addr; -logic [15:0] flush_addr; -logic [1:0] mux_sel_iter1; -logic mux_sel_iter2; -logic mux_sel_msb; -logic [15:0] restart_addr; -logic [15:0] strt_addr; -assign starting_addr_comp = starting_addr2 < starting_addr; -assign mux_sel_iter1 = mux_sel[1:0]; -assign mux_sel_iter2 = mux_sel[0]; -assign mux_sel_msb = mux_sel[2]; -assign flush_addr = mux_sel_msb_init ? starting_addr2: starting_addr; -assign strt_addr = mux_sel_msb ? starting_addr2: starting_addr; -assign restart_addr = (~mux_sel_msb) ? starting_addr2: starting_addr; -assign cur_stride = mux_sel_msb ? strides2[mux_sel_iter2]: strides[mux_sel_iter1]; -assign addr_out = calc_addr; -assign calc_addr = current_addr; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - current_addr <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - current_addr <= flush_addr; - end - else if (step) begin - if (restart) begin - current_addr <= restart_addr; - end - else current_addr <= current_addr + cur_stride; - end - end -end -endmodule // addr_gen_4_16_dual_config_2 - -module addr_gen_4_5_dual_config_2 ( - input logic clk, - input logic clk_en, - input logic flush, - input logic [2:0] mux_sel, - input logic mux_sel_msb_init, - input logic restart, - input logic rst_n, - input logic [4:0] starting_addr, - input logic [4:0] starting_addr2, - input logic step, - input logic [3:0] [4:0] strides, - input logic [1:0] [4:0] strides2, - output logic [4:0] addr_out, - output logic starting_addr_comp -); - -logic [4:0] calc_addr; -logic [4:0] cur_stride; -logic [4:0] current_addr; -logic [4:0] flush_addr; -logic [1:0] mux_sel_iter1; -logic mux_sel_iter2; -logic mux_sel_msb; -logic [4:0] restart_addr; -logic [4:0] strt_addr; -assign starting_addr_comp = starting_addr2 < starting_addr; -assign mux_sel_iter1 = mux_sel[1:0]; -assign mux_sel_iter2 = mux_sel[0]; -assign mux_sel_msb = mux_sel[2]; -assign flush_addr = mux_sel_msb_init ? starting_addr2: starting_addr; -assign strt_addr = mux_sel_msb ? starting_addr2: starting_addr; -assign restart_addr = (~mux_sel_msb) ? starting_addr2: starting_addr; -assign cur_stride = mux_sel_msb ? strides2[mux_sel_iter2]: strides[mux_sel_iter1]; -assign addr_out = calc_addr; -assign calc_addr = current_addr; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - current_addr <= 5'h0; - end - else if (clk_en) begin - if (flush) begin - current_addr <= flush_addr; - end - else if (step) begin - if (restart) begin - current_addr <= restart_addr; - end - else current_addr <= current_addr + cur_stride; - end - end -end -endmodule // addr_gen_4_5_dual_config_2 - -module for_loop_dual_config_4_2_16 #( - parameter CONFIG_WIDTH = 5'h10, - parameter ITERATOR_SUPPORT = 3'h4, - parameter ITERATOR_SUPPORT2 = 2'h2 -) -( - input logic clk, - input logic clk_en, - input logic [2:0] dimensionality, - input logic [1:0] dimensionality2, - input logic flush, - input logic mux_sel_msb_init, - input logic [3:0] [15:0] ranges, - input logic [1:0] [15:0] ranges2, - input logic rst_n, - input logic step, - output logic [2:0] mux_sel_out, - output logic restart -); - -logic [3:0] clear; -logic [2:0] cur_dimensionality; -logic [15:0] cur_range; -logic [3:0][15:0] dim_counter; -logic done; -logic [3:0] inc; -logic [15:0] inced_cnt; -logic [3:0] max_value; -logic maxed_value; -logic [1:0] mux_sel; -logic [1:0] mux_sel_iter1; -logic mux_sel_iter2; -logic mux_sel_msb; -logic mux_sel_msb_r; -assign mux_sel_msb = mux_sel_msb_r; -assign cur_dimensionality = mux_sel_msb ? 3'(dimensionality2): dimensionality; -assign mux_sel_iter1 = mux_sel[1:0]; -assign mux_sel_iter2 = mux_sel[0]; -assign mux_sel_out = {mux_sel_msb, mux_sel}; -assign inced_cnt = dim_counter[mux_sel] + 16'h1; -assign cur_range = mux_sel_msb ? ranges2[mux_sel_iter2]: ranges[mux_sel_iter1]; -assign maxed_value = (dim_counter[mux_sel] == cur_range) & inc[mux_sel]; -always_comb begin - mux_sel = 2'h0; - done = 1'h0; - if (~done) begin - if ((~max_value[0]) & (cur_dimensionality > 3'h0)) begin - mux_sel = 2'h0; - done = 1'h1; - end - end - if (~done) begin - if ((~max_value[1]) & (cur_dimensionality > 3'h1)) begin - mux_sel = 2'h1; - done = 1'h1; - end - end - if (~done) begin - if ((~max_value[2]) & (cur_dimensionality > 3'h2)) begin - mux_sel = 2'h2; - done = 1'h1; - end - end - if (~done) begin - if ((~max_value[3]) & (cur_dimensionality > 3'h3)) begin - mux_sel = 2'h3; - done = 1'h1; - end - end -end -always_comb begin - clear[0] = 1'h0; - if (((mux_sel > 2'h0) | (~done)) & step) begin - clear[0] = 1'h1; - end -end -always_comb begin - inc[0] = 1'h0; - if ((5'h0 == 5'h0) & step & (cur_dimensionality > 3'h0)) begin - inc[0] = 1'h1; - end - else if ((mux_sel == 2'h0) & step & (cur_dimensionality > 3'h0)) begin - inc[0] = 1'h1; - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - dim_counter[0] <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - dim_counter[0] <= 16'h0; - end - else if (clear[0]) begin - dim_counter[0] <= 16'h0; - end - else if (inc[0]) begin - dim_counter[0] <= inced_cnt; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - max_value[0] <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - max_value[0] <= 1'h0; - end - else if (clear[0]) begin - max_value[0] <= 1'h0; - end - else if (inc[0]) begin - max_value[0] <= maxed_value; - end - end -end -always_comb begin - clear[1] = 1'h0; - if (((mux_sel > 2'h1) | (~done)) & step) begin - clear[1] = 1'h1; - end -end -always_comb begin - inc[1] = 1'h0; - if ((5'h1 == 5'h0) & step & (cur_dimensionality > 3'h1)) begin - inc[1] = 1'h1; - end - else if ((mux_sel == 2'h1) & step & (cur_dimensionality > 3'h1)) begin - inc[1] = 1'h1; - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - dim_counter[1] <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - dim_counter[1] <= 16'h0; - end - else if (clear[1]) begin - dim_counter[1] <= 16'h0; - end - else if (inc[1]) begin - dim_counter[1] <= inced_cnt; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - max_value[1] <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - max_value[1] <= 1'h0; - end - else if (clear[1]) begin - max_value[1] <= 1'h0; - end - else if (inc[1]) begin - max_value[1] <= maxed_value; - end - end -end -always_comb begin - clear[2] = 1'h0; - if (((mux_sel > 2'h2) | (~done)) & step) begin - clear[2] = 1'h1; - end -end -always_comb begin - inc[2] = 1'h0; - if ((5'h2 == 5'h0) & step & (cur_dimensionality > 3'h2)) begin - inc[2] = 1'h1; - end - else if ((mux_sel == 2'h2) & step & (cur_dimensionality > 3'h2)) begin - inc[2] = 1'h1; - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - dim_counter[2] <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - dim_counter[2] <= 16'h0; - end - else if (clear[2]) begin - dim_counter[2] <= 16'h0; - end - else if (inc[2]) begin - dim_counter[2] <= inced_cnt; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - max_value[2] <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - max_value[2] <= 1'h0; - end - else if (clear[2]) begin - max_value[2] <= 1'h0; - end - else if (inc[2]) begin - max_value[2] <= maxed_value; - end - end -end -always_comb begin - clear[3] = 1'h0; - if (((mux_sel > 2'h3) | (~done)) & step) begin - clear[3] = 1'h1; - end -end -always_comb begin - inc[3] = 1'h0; - if ((5'h3 == 5'h0) & step & (cur_dimensionality > 3'h3)) begin - inc[3] = 1'h1; - end - else if ((mux_sel == 2'h3) & step & (cur_dimensionality > 3'h3)) begin - inc[3] = 1'h1; - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - dim_counter[3] <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - dim_counter[3] <= 16'h0; - end - else if (clear[3]) begin - dim_counter[3] <= 16'h0; - end - else if (inc[3]) begin - dim_counter[3] <= inced_cnt; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - max_value[3] <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - max_value[3] <= 1'h0; - end - else if (clear[3]) begin - max_value[3] <= 1'h0; - end - else if (inc[3]) begin - max_value[3] <= maxed_value; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - mux_sel_msb_r <= 1'h0; - end - else if (clk_en) begin - if (flush) begin - mux_sel_msb_r <= mux_sel_msb_init; - end - else if (restart) begin - mux_sel_msb_r <= ~mux_sel_msb_r; - end - end -end -assign restart = step & (~done); -endmodule // for_loop_dual_config_4_2_16 - -module sched_gen_4_16_dual_config_2 ( - input logic clk, - input logic clk_en, - input logic [15:0] cycle_count, - input logic enable, - input logic enable2, - input logic finished, - input logic flush, - input logic [2:0] mux_sel, - input logic rst_n, - input logic [15:0] sched_addr_gen_starting_addr, - input logic [15:0] sched_addr_gen_starting_addr2, - input logic [15:0] sched_addr_gen_strides2_0, - input logic [15:0] sched_addr_gen_strides2_1, - input logic [15:0] sched_addr_gen_strides_0, - input logic [15:0] sched_addr_gen_strides_1, - input logic [15:0] sched_addr_gen_strides_2, - input logic [15:0] sched_addr_gen_strides_3, - output logic mux_sel_msb_init, - output logic valid_output -); - -logic [15:0] addr_out; -logic cur_enable; -logic cur_valid_gate; -logic mux_sel_msb_init_w; -logic sched_addr_gen_starting_addr_comp; -logic [3:0][15:0] sched_addr_gen_strides; -logic [1:0][15:0] sched_addr_gen_strides2; -logic [1:0] valid_gate; -logic [1:0] valid_gate_inv; -logic valid_out; -assign cur_valid_gate = valid_gate[mux_sel[2]]; -assign valid_gate = ~valid_gate_inv; -assign cur_enable = mux_sel[2] ? enable2: enable; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - valid_gate_inv <= 2'h0; - end - else if (clk_en) begin - if (flush) begin - valid_gate_inv <= 2'h0; - end - else if (finished) begin - valid_gate_inv[mux_sel[2]] <= 1'h1; - end - end -end -always_comb begin - if (enable & enable2) begin - mux_sel_msb_init_w = sched_addr_gen_starting_addr_comp; - end - else if (enable & (~enable2)) begin - mux_sel_msb_init_w = 1'h0; - end - else if ((~enable) & enable2) begin - mux_sel_msb_init_w = 1'h1; - end - else mux_sel_msb_init_w = 1'h0; -end -assign mux_sel_msb_init = mux_sel_msb_init_w; -always_comb begin - valid_out = (cycle_count == addr_out) & cur_valid_gate & cur_enable; -end -always_comb begin - valid_output = valid_out; -end -assign sched_addr_gen_strides2[0] = sched_addr_gen_strides2_0; -assign sched_addr_gen_strides2[1] = sched_addr_gen_strides2_1; -assign sched_addr_gen_strides[0] = sched_addr_gen_strides_0; -assign sched_addr_gen_strides[1] = sched_addr_gen_strides_1; -assign sched_addr_gen_strides[2] = sched_addr_gen_strides_2; -assign sched_addr_gen_strides[3] = sched_addr_gen_strides_3; -addr_gen_4_16_dual_config_2 sched_addr_gen ( - .clk(clk), - .clk_en(clk_en), - .flush(flush), - .mux_sel(mux_sel), - .mux_sel_msb_init(mux_sel_msb_init_w), - .restart(finished), - .rst_n(rst_n), - .starting_addr(sched_addr_gen_starting_addr), - .starting_addr2(sched_addr_gen_starting_addr2), - .step(valid_out), - .strides(sched_addr_gen_strides), - .strides2(sched_addr_gen_strides2), - .addr_out(addr_out), - .starting_addr_comp(sched_addr_gen_starting_addr_comp) -); - -endmodule // sched_gen_4_16_dual_config_2 - -module sram_dp__0 ( - input logic clk, - input logic clk_en, - input logic [15:0] data_in_p0, - input logic flush, - input logic [4:0] read_addr_p0, - input logic [4:0] read_addr_p1, - input logic read_enable_p0, - input logic read_enable_p1, - input logic [4:0] write_addr_p0, - input logic write_enable_p0, - output logic [15:0] data_out_p0, - output logic [15:0] data_out_p1 -); - -logic [15:0] data_array [31:0]; - -always_ff @(posedge clk) begin - if (clk_en) begin - if (write_enable_p0 == 1'h1) begin - data_array[write_addr_p0] <= data_in_p0; - end - end -end -assign data_out_p0 = data_array[read_addr_p0]; -always_comb begin - data_out_p1 = data_array[read_addr_p1]; -end -endmodule // sram_dp__0 - -module storage_config_seq_1_16_16 ( - input logic clk, - input logic clk_en, - input logic [7:0] config_addr_in, - input logic [15:0] config_data_in, - input logic config_en, - input logic config_rd, - input logic config_wr, - input logic flush, - input logic [0:0][0:0] [15:0] rd_data_stg, - input logic rst_n, - output logic [4:0] addr_out, - output logic [0:0] [15:0] rd_data_out, - output logic ren_out, - output logic wen_out, - output logic [0:0] [15:0] wr_data -); - -assign addr_out = config_addr_in[4:0]; -assign wr_data[0] = config_data_in; -assign rd_data_out[0] = rd_data_stg[0]; -assign wen_out = config_wr; -assign ren_out = config_rd; -endmodule // storage_config_seq_1_16_16 - -module strg_ub_thin_PondTop ( - input logic clk, - input logic clk_en, - input logic [15:0] data_from_strg, - input logic [1:0] [16:0] data_in, - input logic flush, - input logic [4:0] in2regfile_0_addr_gen_starting_addr, - input logic [4:0] in2regfile_0_addr_gen_starting_addr2, - input logic [4:0] in2regfile_0_addr_gen_strides2_0, - input logic [4:0] in2regfile_0_addr_gen_strides2_1, - input logic [4:0] in2regfile_0_addr_gen_strides_0, - input logic [4:0] in2regfile_0_addr_gen_strides_1, - input logic [4:0] in2regfile_0_addr_gen_strides_2, - input logic [4:0] in2regfile_0_addr_gen_strides_3, - input logic [2:0] in2regfile_0_for_loop_dimensionality, - input logic [1:0] in2regfile_0_for_loop_dimensionality2, - input logic [15:0] in2regfile_0_for_loop_ranges2_0, - input logic [15:0] in2regfile_0_for_loop_ranges2_1, - input logic [15:0] in2regfile_0_for_loop_ranges_0, - input logic [15:0] in2regfile_0_for_loop_ranges_1, - input logic [15:0] in2regfile_0_for_loop_ranges_2, - input logic [15:0] in2regfile_0_for_loop_ranges_3, - input logic in2regfile_0_sched_gen_enable, - input logic in2regfile_0_sched_gen_enable2, - input logic [15:0] in2regfile_0_sched_gen_sched_addr_gen_starting_addr, - input logic [15:0] in2regfile_0_sched_gen_sched_addr_gen_starting_addr2, - input logic [15:0] in2regfile_0_sched_gen_sched_addr_gen_strides2_0, - input logic [15:0] in2regfile_0_sched_gen_sched_addr_gen_strides2_1, - input logic [15:0] in2regfile_0_sched_gen_sched_addr_gen_strides_0, - input logic [15:0] in2regfile_0_sched_gen_sched_addr_gen_strides_1, - input logic [15:0] in2regfile_0_sched_gen_sched_addr_gen_strides_2, - input logic [15:0] in2regfile_0_sched_gen_sched_addr_gen_strides_3, - input logic [4:0] regfile2out_0_addr_gen_starting_addr, - input logic [4:0] regfile2out_0_addr_gen_starting_addr2, - input logic [4:0] regfile2out_0_addr_gen_strides2_0, - input logic [4:0] regfile2out_0_addr_gen_strides2_1, - input logic [4:0] regfile2out_0_addr_gen_strides_0, - input logic [4:0] regfile2out_0_addr_gen_strides_1, - input logic [4:0] regfile2out_0_addr_gen_strides_2, - input logic [4:0] regfile2out_0_addr_gen_strides_3, - input logic [2:0] regfile2out_0_for_loop_dimensionality, - input logic [1:0] regfile2out_0_for_loop_dimensionality2, - input logic [15:0] regfile2out_0_for_loop_ranges2_0, - input logic [15:0] regfile2out_0_for_loop_ranges2_1, - input logic [15:0] regfile2out_0_for_loop_ranges_0, - input logic [15:0] regfile2out_0_for_loop_ranges_1, - input logic [15:0] regfile2out_0_for_loop_ranges_2, - input logic [15:0] regfile2out_0_for_loop_ranges_3, - input logic regfile2out_0_sched_gen_enable, - input logic regfile2out_0_sched_gen_enable2, - input logic [15:0] regfile2out_0_sched_gen_sched_addr_gen_starting_addr, - input logic [15:0] regfile2out_0_sched_gen_sched_addr_gen_starting_addr2, - input logic [15:0] regfile2out_0_sched_gen_sched_addr_gen_strides2_0, - input logic [15:0] regfile2out_0_sched_gen_sched_addr_gen_strides2_1, - input logic [15:0] regfile2out_0_sched_gen_sched_addr_gen_strides_0, - input logic [15:0] regfile2out_0_sched_gen_sched_addr_gen_strides_1, - input logic [15:0] regfile2out_0_sched_gen_sched_addr_gen_strides_2, - input logic [15:0] regfile2out_0_sched_gen_sched_addr_gen_strides_3, - input logic rst_n, - output logic [1:0] [16:0] data_out, - output logic [15:0] data_to_strg, - output logic [4:0] rd_addr_out, - output logic ren_to_strg, - output logic [4:0] tmp0_rdaddr, - output logic tmp0_rden, - output logic [1:0] valid_out, - output logic wen_to_strg, - output logic [4:0] wr_addr_out -); - -logic [15:0] cycle_count; -logic [1:0][15:0] data_in_thin; -logic [1:0][15:0] data_out_int; -logic [1:0][15:0] data_out_int_thin; -logic in2regfile_0_addr_gen_mux_sel_msb_init; -logic [3:0][4:0] in2regfile_0_addr_gen_strides; -logic [1:0][4:0] in2regfile_0_addr_gen_strides2; -logic in2regfile_0_for_loop_mux_sel_msb_init; -logic [2:0] in2regfile_0_for_loop_mux_sel_out; -logic [3:0][15:0] in2regfile_0_for_loop_ranges; -logic [1:0][15:0] in2regfile_0_for_loop_ranges2; -logic in2regfile_0_for_loop_restart; -logic in2regfile_0_sched_gen_mux_sel_msb_init; -logic in2regfile_0_sched_gen_valid_output; -logic read; -logic [4:0] read_addr; -logic read_mux_sel_msb; -logic regfile2out_0_addr_gen_mux_sel_msb_init; -logic [3:0][4:0] regfile2out_0_addr_gen_strides; -logic [1:0][4:0] regfile2out_0_addr_gen_strides2; -logic regfile2out_0_for_loop_mux_sel_msb_init; -logic [2:0] regfile2out_0_for_loop_mux_sel_out; -logic [3:0][15:0] regfile2out_0_for_loop_ranges; -logic [1:0][15:0] regfile2out_0_for_loop_ranges2; -logic regfile2out_0_for_loop_restart; -logic regfile2out_0_sched_gen_mux_sel_msb_init; -logic regfile2out_0_sched_gen_valid_output; -logic [1:0] valid_out_int; -logic write; -logic [4:0] write_addr; -logic write_mux_sel_msb; -assign data_in_thin[0] = data_in[0][15:0]; -assign data_in_thin[1] = data_in[1][15:0]; - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - cycle_count <= 16'h0; - end - else if (clk_en) begin - if (flush) begin - cycle_count <= 16'h0; - end - else cycle_count <= cycle_count + 16'h1; - end -end -assign valid_out_int[0] = read & (~read_mux_sel_msb); -assign valid_out_int[1] = read & read_mux_sel_msb; -assign data_out_int_thin = data_out_int; -assign data_out[0][15:0] = data_out_int_thin[0]; -assign data_out[0][16] = 1'h0; -assign data_out[1][15:0] = data_out_int_thin[1]; -assign data_out[1][16] = 1'h0; -assign valid_out = valid_out_int; -assign write = in2regfile_0_sched_gen_valid_output; -assign in2regfile_0_for_loop_mux_sel_msb_init = in2regfile_0_sched_gen_mux_sel_msb_init; -assign in2regfile_0_addr_gen_mux_sel_msb_init = in2regfile_0_sched_gen_mux_sel_msb_init; -assign write_mux_sel_msb = in2regfile_0_for_loop_mux_sel_out[2]; -assign read = regfile2out_0_sched_gen_valid_output; -assign regfile2out_0_for_loop_mux_sel_msb_init = regfile2out_0_sched_gen_mux_sel_msb_init; -assign regfile2out_0_addr_gen_mux_sel_msb_init = regfile2out_0_sched_gen_mux_sel_msb_init; -assign read_mux_sel_msb = regfile2out_0_for_loop_mux_sel_out[2]; -assign wen_to_strg = |write; -assign ren_to_strg = |read; -assign data_out_int[0] = data_from_strg; -assign data_out_int[1] = data_from_strg; -assign wr_addr_out = write_addr[4:0]; -assign data_to_strg = data_in_thin[write_mux_sel_msb]; -assign rd_addr_out = read_addr[4:0]; -assign tmp0_rdaddr = 5'h0; -assign tmp0_rden = 1'h0; -assign in2regfile_0_for_loop_ranges[0] = in2regfile_0_for_loop_ranges_0; -assign in2regfile_0_for_loop_ranges[1] = in2regfile_0_for_loop_ranges_1; -assign in2regfile_0_for_loop_ranges[2] = in2regfile_0_for_loop_ranges_2; -assign in2regfile_0_for_loop_ranges[3] = in2regfile_0_for_loop_ranges_3; -assign in2regfile_0_for_loop_ranges2[0] = in2regfile_0_for_loop_ranges2_0; -assign in2regfile_0_for_loop_ranges2[1] = in2regfile_0_for_loop_ranges2_1; -assign in2regfile_0_addr_gen_strides2[0] = in2regfile_0_addr_gen_strides2_0; -assign in2regfile_0_addr_gen_strides2[1] = in2regfile_0_addr_gen_strides2_1; -assign in2regfile_0_addr_gen_strides[0] = in2regfile_0_addr_gen_strides_0; -assign in2regfile_0_addr_gen_strides[1] = in2regfile_0_addr_gen_strides_1; -assign in2regfile_0_addr_gen_strides[2] = in2regfile_0_addr_gen_strides_2; -assign in2regfile_0_addr_gen_strides[3] = in2regfile_0_addr_gen_strides_3; -assign regfile2out_0_for_loop_ranges[0] = regfile2out_0_for_loop_ranges_0; -assign regfile2out_0_for_loop_ranges[1] = regfile2out_0_for_loop_ranges_1; -assign regfile2out_0_for_loop_ranges[2] = regfile2out_0_for_loop_ranges_2; -assign regfile2out_0_for_loop_ranges[3] = regfile2out_0_for_loop_ranges_3; -assign regfile2out_0_for_loop_ranges2[0] = regfile2out_0_for_loop_ranges2_0; -assign regfile2out_0_for_loop_ranges2[1] = regfile2out_0_for_loop_ranges2_1; -assign regfile2out_0_addr_gen_strides2[0] = regfile2out_0_addr_gen_strides2_0; -assign regfile2out_0_addr_gen_strides2[1] = regfile2out_0_addr_gen_strides2_1; -assign regfile2out_0_addr_gen_strides[0] = regfile2out_0_addr_gen_strides_0; -assign regfile2out_0_addr_gen_strides[1] = regfile2out_0_addr_gen_strides_1; -assign regfile2out_0_addr_gen_strides[2] = regfile2out_0_addr_gen_strides_2; -assign regfile2out_0_addr_gen_strides[3] = regfile2out_0_addr_gen_strides_3; -for_loop_dual_config_4_2_16 in2regfile_0_for_loop ( - .clk(clk), - .clk_en(clk_en), - .dimensionality(in2regfile_0_for_loop_dimensionality), - .dimensionality2(in2regfile_0_for_loop_dimensionality2), - .flush(flush), - .mux_sel_msb_init(in2regfile_0_for_loop_mux_sel_msb_init), - .ranges(in2regfile_0_for_loop_ranges), - .ranges2(in2regfile_0_for_loop_ranges2), - .rst_n(rst_n), - .step(write), - .mux_sel_out(in2regfile_0_for_loop_mux_sel_out), - .restart(in2regfile_0_for_loop_restart) -); - -addr_gen_4_5_dual_config_2 in2regfile_0_addr_gen ( - .clk(clk), - .clk_en(clk_en), - .flush(flush), - .mux_sel(in2regfile_0_for_loop_mux_sel_out), - .mux_sel_msb_init(in2regfile_0_addr_gen_mux_sel_msb_init), - .restart(in2regfile_0_for_loop_restart), - .rst_n(rst_n), - .starting_addr(in2regfile_0_addr_gen_starting_addr), - .starting_addr2(in2regfile_0_addr_gen_starting_addr2), - .step(write), - .strides(in2regfile_0_addr_gen_strides), - .strides2(in2regfile_0_addr_gen_strides2), - .addr_out(write_addr) -); - -sched_gen_4_16_dual_config_2 in2regfile_0_sched_gen ( - .clk(clk), - .clk_en(clk_en), - .cycle_count(cycle_count), - .enable(in2regfile_0_sched_gen_enable), - .enable2(in2regfile_0_sched_gen_enable2), - .finished(in2regfile_0_for_loop_restart), - .flush(flush), - .mux_sel(in2regfile_0_for_loop_mux_sel_out), - .rst_n(rst_n), - .sched_addr_gen_starting_addr(in2regfile_0_sched_gen_sched_addr_gen_starting_addr), - .sched_addr_gen_starting_addr2(in2regfile_0_sched_gen_sched_addr_gen_starting_addr2), - .sched_addr_gen_strides2_0(in2regfile_0_sched_gen_sched_addr_gen_strides2_0), - .sched_addr_gen_strides2_1(in2regfile_0_sched_gen_sched_addr_gen_strides2_1), - .sched_addr_gen_strides_0(in2regfile_0_sched_gen_sched_addr_gen_strides_0), - .sched_addr_gen_strides_1(in2regfile_0_sched_gen_sched_addr_gen_strides_1), - .sched_addr_gen_strides_2(in2regfile_0_sched_gen_sched_addr_gen_strides_2), - .sched_addr_gen_strides_3(in2regfile_0_sched_gen_sched_addr_gen_strides_3), - .mux_sel_msb_init(in2regfile_0_sched_gen_mux_sel_msb_init), - .valid_output(in2regfile_0_sched_gen_valid_output) -); - -for_loop_dual_config_4_2_16 regfile2out_0_for_loop ( - .clk(clk), - .clk_en(clk_en), - .dimensionality(regfile2out_0_for_loop_dimensionality), - .dimensionality2(regfile2out_0_for_loop_dimensionality2), - .flush(flush), - .mux_sel_msb_init(regfile2out_0_for_loop_mux_sel_msb_init), - .ranges(regfile2out_0_for_loop_ranges), - .ranges2(regfile2out_0_for_loop_ranges2), - .rst_n(rst_n), - .step(read), - .mux_sel_out(regfile2out_0_for_loop_mux_sel_out), - .restart(regfile2out_0_for_loop_restart) -); - -addr_gen_4_5_dual_config_2 regfile2out_0_addr_gen ( - .clk(clk), - .clk_en(clk_en), - .flush(flush), - .mux_sel(regfile2out_0_for_loop_mux_sel_out), - .mux_sel_msb_init(regfile2out_0_addr_gen_mux_sel_msb_init), - .restart(regfile2out_0_for_loop_restart), - .rst_n(rst_n), - .starting_addr(regfile2out_0_addr_gen_starting_addr), - .starting_addr2(regfile2out_0_addr_gen_starting_addr2), - .step(read), - .strides(regfile2out_0_addr_gen_strides), - .strides2(regfile2out_0_addr_gen_strides2), - .addr_out(read_addr) -); - -sched_gen_4_16_dual_config_2 regfile2out_0_sched_gen ( - .clk(clk), - .clk_en(clk_en), - .cycle_count(cycle_count), - .enable(regfile2out_0_sched_gen_enable), - .enable2(regfile2out_0_sched_gen_enable2), - .finished(regfile2out_0_for_loop_restart), - .flush(flush), - .mux_sel(regfile2out_0_for_loop_mux_sel_out), - .rst_n(rst_n), - .sched_addr_gen_starting_addr(regfile2out_0_sched_gen_sched_addr_gen_starting_addr), - .sched_addr_gen_starting_addr2(regfile2out_0_sched_gen_sched_addr_gen_starting_addr2), - .sched_addr_gen_strides2_0(regfile2out_0_sched_gen_sched_addr_gen_strides2_0), - .sched_addr_gen_strides2_1(regfile2out_0_sched_gen_sched_addr_gen_strides2_1), - .sched_addr_gen_strides_0(regfile2out_0_sched_gen_sched_addr_gen_strides_0), - .sched_addr_gen_strides_1(regfile2out_0_sched_gen_sched_addr_gen_strides_1), - .sched_addr_gen_strides_2(regfile2out_0_sched_gen_sched_addr_gen_strides_2), - .sched_addr_gen_strides_3(regfile2out_0_sched_gen_sched_addr_gen_strides_3), - .mux_sel_msb_init(regfile2out_0_sched_gen_mux_sel_msb_init), - .valid_output(regfile2out_0_sched_gen_valid_output) -); - -endmodule // strg_ub_thin_PondTop - -module strg_ub_thin_PondTop_flat ( - input logic clk, - input logic clk_en, - input logic [0:0] [16:0] data_in_f_0, - input logic [0:0] [16:0] data_in_f_1, - input logic flush, - input logic rst_n, - input logic [15:0] strg_ub_thin_PondTop_inst_data_from_strg_lifted, - input logic [4:0] strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_starting_addr, - input logic [4:0] strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_starting_addr2, - input logic [4:0] strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides2_0, - input logic [4:0] strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides2_1, - input logic [4:0] strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_0, - input logic [4:0] strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_1, - input logic [4:0] strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_2, - input logic [4:0] strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_3, - input logic [2:0] strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_dimensionality, - input logic [1:0] strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_dimensionality2, - input logic [15:0] strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges2_0, - input logic [15:0] strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges2_1, - input logic [15:0] strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_0, - input logic [15:0] strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_1, - input logic [15:0] strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_2, - input logic [15:0] strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_3, - input logic strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_enable, - input logic strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_enable2, - input logic [15:0] strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_starting_addr, - input logic [15:0] strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_starting_addr2, - input logic [15:0] strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides2_0, - input logic [15:0] strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides2_1, - input logic [15:0] strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_0, - input logic [15:0] strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_1, - input logic [15:0] strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_2, - input logic [15:0] strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_3, - input logic [4:0] strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_starting_addr, - input logic [4:0] strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_starting_addr2, - input logic [4:0] strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides2_0, - input logic [4:0] strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides2_1, - input logic [4:0] strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_0, - input logic [4:0] strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_1, - input logic [4:0] strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_2, - input logic [4:0] strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_3, - input logic [2:0] strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_dimensionality, - input logic [1:0] strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_dimensionality2, - input logic [15:0] strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges2_0, - input logic [15:0] strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges2_1, - input logic [15:0] strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_0, - input logic [15:0] strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_1, - input logic [15:0] strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_2, - input logic [15:0] strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_3, - input logic strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_enable, - input logic strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_enable2, - input logic [15:0] strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_starting_addr, - input logic [15:0] strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_starting_addr2, - input logic [15:0] strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides2_0, - input logic [15:0] strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides2_1, - input logic [15:0] strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_0, - input logic [15:0] strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_1, - input logic [15:0] strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_2, - input logic [15:0] strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_3, - output logic [0:0] [16:0] data_out_f_0, - output logic [0:0] [16:0] data_out_f_1, - output logic [15:0] strg_ub_thin_PondTop_inst_data_to_strg_lifted, - output logic [4:0] strg_ub_thin_PondTop_inst_rd_addr_out_lifted, - output logic strg_ub_thin_PondTop_inst_ren_to_strg_lifted, - output logic [4:0] strg_ub_thin_PondTop_inst_tmp0_rdaddr_lifted, - output logic strg_ub_thin_PondTop_inst_tmp0_rden_lifted, - output logic strg_ub_thin_PondTop_inst_wen_to_strg_lifted, - output logic [4:0] strg_ub_thin_PondTop_inst_wr_addr_out_lifted, - output logic valid_out_f_b_0, - output logic valid_out_f_b_1 -); - -logic [1:0][16:0] strg_ub_thin_PondTop_inst_data_in; -logic [1:0][16:0] strg_ub_thin_PondTop_inst_data_out; -logic [1:0] strg_ub_thin_PondTop_inst_valid_out; -assign strg_ub_thin_PondTop_inst_data_in[0] = data_in_f_0; -assign strg_ub_thin_PondTop_inst_data_in[1] = data_in_f_1; -assign valid_out_f_b_0 = strg_ub_thin_PondTop_inst_valid_out[0]; -assign valid_out_f_b_1 = strg_ub_thin_PondTop_inst_valid_out[1]; -assign data_out_f_0 = strg_ub_thin_PondTop_inst_data_out[0]; -assign data_out_f_1 = strg_ub_thin_PondTop_inst_data_out[1]; -strg_ub_thin_PondTop strg_ub_thin_PondTop_inst ( - .clk(clk), - .clk_en(clk_en), - .data_from_strg(strg_ub_thin_PondTop_inst_data_from_strg_lifted), - .data_in(strg_ub_thin_PondTop_inst_data_in), - .flush(flush), - .in2regfile_0_addr_gen_starting_addr(strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_starting_addr), - .in2regfile_0_addr_gen_starting_addr2(strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_starting_addr2), - .in2regfile_0_addr_gen_strides2_0(strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides2_0), - .in2regfile_0_addr_gen_strides2_1(strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides2_1), - .in2regfile_0_addr_gen_strides_0(strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_0), - .in2regfile_0_addr_gen_strides_1(strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_1), - .in2regfile_0_addr_gen_strides_2(strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_2), - .in2regfile_0_addr_gen_strides_3(strg_ub_thin_PondTop_inst_in2regfile_0_addr_gen_strides_3), - .in2regfile_0_for_loop_dimensionality(strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_dimensionality), - .in2regfile_0_for_loop_dimensionality2(strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_dimensionality2), - .in2regfile_0_for_loop_ranges2_0(strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges2_0), - .in2regfile_0_for_loop_ranges2_1(strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges2_1), - .in2regfile_0_for_loop_ranges_0(strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_0), - .in2regfile_0_for_loop_ranges_1(strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_1), - .in2regfile_0_for_loop_ranges_2(strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_2), - .in2regfile_0_for_loop_ranges_3(strg_ub_thin_PondTop_inst_in2regfile_0_for_loop_ranges_3), - .in2regfile_0_sched_gen_enable(strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_enable), - .in2regfile_0_sched_gen_enable2(strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_enable2), - .in2regfile_0_sched_gen_sched_addr_gen_starting_addr(strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_starting_addr), - .in2regfile_0_sched_gen_sched_addr_gen_starting_addr2(strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_starting_addr2), - .in2regfile_0_sched_gen_sched_addr_gen_strides2_0(strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides2_0), - .in2regfile_0_sched_gen_sched_addr_gen_strides2_1(strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides2_1), - .in2regfile_0_sched_gen_sched_addr_gen_strides_0(strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_0), - .in2regfile_0_sched_gen_sched_addr_gen_strides_1(strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_1), - .in2regfile_0_sched_gen_sched_addr_gen_strides_2(strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_2), - .in2regfile_0_sched_gen_sched_addr_gen_strides_3(strg_ub_thin_PondTop_inst_in2regfile_0_sched_gen_sched_addr_gen_strides_3), - .regfile2out_0_addr_gen_starting_addr(strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_starting_addr), - .regfile2out_0_addr_gen_starting_addr2(strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_starting_addr2), - .regfile2out_0_addr_gen_strides2_0(strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides2_0), - .regfile2out_0_addr_gen_strides2_1(strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides2_1), - .regfile2out_0_addr_gen_strides_0(strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_0), - .regfile2out_0_addr_gen_strides_1(strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_1), - .regfile2out_0_addr_gen_strides_2(strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_2), - .regfile2out_0_addr_gen_strides_3(strg_ub_thin_PondTop_inst_regfile2out_0_addr_gen_strides_3), - .regfile2out_0_for_loop_dimensionality(strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_dimensionality), - .regfile2out_0_for_loop_dimensionality2(strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_dimensionality2), - .regfile2out_0_for_loop_ranges2_0(strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges2_0), - .regfile2out_0_for_loop_ranges2_1(strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges2_1), - .regfile2out_0_for_loop_ranges_0(strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_0), - .regfile2out_0_for_loop_ranges_1(strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_1), - .regfile2out_0_for_loop_ranges_2(strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_2), - .regfile2out_0_for_loop_ranges_3(strg_ub_thin_PondTop_inst_regfile2out_0_for_loop_ranges_3), - .regfile2out_0_sched_gen_enable(strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_enable), - .regfile2out_0_sched_gen_enable2(strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_enable2), - .regfile2out_0_sched_gen_sched_addr_gen_starting_addr(strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_starting_addr), - .regfile2out_0_sched_gen_sched_addr_gen_starting_addr2(strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_starting_addr2), - .regfile2out_0_sched_gen_sched_addr_gen_strides2_0(strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides2_0), - .regfile2out_0_sched_gen_sched_addr_gen_strides2_1(strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides2_1), - .regfile2out_0_sched_gen_sched_addr_gen_strides_0(strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_0), - .regfile2out_0_sched_gen_sched_addr_gen_strides_1(strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_1), - .regfile2out_0_sched_gen_sched_addr_gen_strides_2(strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_2), - .regfile2out_0_sched_gen_sched_addr_gen_strides_3(strg_ub_thin_PondTop_inst_regfile2out_0_sched_gen_sched_addr_gen_strides_3), - .rst_n(rst_n), - .data_out(strg_ub_thin_PondTop_inst_data_out), - .data_to_strg(strg_ub_thin_PondTop_inst_data_to_strg_lifted), - .rd_addr_out(strg_ub_thin_PondTop_inst_rd_addr_out_lifted), - .ren_to_strg(strg_ub_thin_PondTop_inst_ren_to_strg_lifted), - .tmp0_rdaddr(strg_ub_thin_PondTop_inst_tmp0_rdaddr_lifted), - .tmp0_rden(strg_ub_thin_PondTop_inst_tmp0_rden_lifted), - .valid_out(strg_ub_thin_PondTop_inst_valid_out), - .wen_to_strg(strg_ub_thin_PondTop_inst_wen_to_strg_lifted), - .wr_addr_out(strg_ub_thin_PondTop_inst_wr_addr_out_lifted) -); - -endmodule // strg_ub_thin_PondTop_flat - diff --git a/sam/onyx/.magma/ReadyValidLoopBack-kratos.sv b/sam/onyx/.magma/ReadyValidLoopBack-kratos.sv deleted file mode 100644 index 5cb19020..00000000 --- a/sam/onyx/.magma/ReadyValidLoopBack-kratos.sv +++ /dev/null @@ -1,9 +0,0 @@ -module ReadyValidLoopBack ( - input logic ready_in, - input logic valid_in, - output logic valid_out -); - -assign valid_out = ready_in & valid_in; -endmodule // ReadyValidLoopBack - diff --git a/sam/onyx/.magma/SplitFifo_1-kratos.sv b/sam/onyx/.magma/SplitFifo_1-kratos.sv deleted file mode 100644 index 24d28540..00000000 --- a/sam/onyx/.magma/SplitFifo_1-kratos.sv +++ /dev/null @@ -1,57 +0,0 @@ -module SplitFifo_1 ( - input logic clk, - input logic clk_en, - input logic data_in, - input logic end_fifo, - input logic fifo_en, - input logic ready1, - input logic rst, - input logic start_fifo, - input logic valid0, - output logic data_out, - output logic ready0, - output logic valid1 -); - -logic empty; -logic empty_n; -logic ready_in; -logic valid_in; -logic value; -assign empty = ~empty_n; -assign ready_in = ready1 && (~start_fifo); -assign ready0 = fifo_en ? empty || ready_in: clk_en; -assign valid_in = valid0 && (~end_fifo); -assign valid1 = fifo_en ? (~empty) || valid_in: clk_en; -assign data_out = (empty && fifo_en) ? data_in: value; - -always_ff @(posedge clk, posedge rst) begin - if (rst) begin - value <= 1'h0; - end - else if (clk_en) begin - if ((~fifo_en) || (valid0 && ready0 && (~(empty && ready1 && valid1)))) begin - value <= data_in; - end - end -end - -always_ff @(posedge clk, posedge rst) begin - if (rst) begin - empty_n <= 1'h0; - end - else if (clk_en) begin - if (fifo_en) begin - if (valid1 && ready1) begin - if (~(valid0 && ready0)) begin - empty_n <= 1'h0; - end - end - else if (valid0 && ready0) begin - empty_n <= 1'h1; - end - end - end -end -endmodule // SplitFifo_1 - diff --git a/sam/onyx/.magma/SplitFifo_17-kratos.sv b/sam/onyx/.magma/SplitFifo_17-kratos.sv deleted file mode 100644 index e204afd4..00000000 --- a/sam/onyx/.magma/SplitFifo_17-kratos.sv +++ /dev/null @@ -1,57 +0,0 @@ -module SplitFifo_17 ( - input logic clk, - input logic clk_en, - input logic [16:0] data_in, - input logic end_fifo, - input logic fifo_en, - input logic ready1, - input logic rst, - input logic start_fifo, - input logic valid0, - output logic [16:0] data_out, - output logic ready0, - output logic valid1 -); - -logic empty; -logic empty_n; -logic ready_in; -logic valid_in; -logic [16:0] value; -assign empty = ~empty_n; -assign ready_in = ready1 && (~start_fifo); -assign ready0 = fifo_en ? empty || ready_in: clk_en; -assign valid_in = valid0 && (~end_fifo); -assign valid1 = fifo_en ? (~empty) || valid_in: clk_en; -assign data_out = (empty && fifo_en) ? data_in: value; - -always_ff @(posedge clk, posedge rst) begin - if (rst) begin - value <= 17'h0; - end - else if (clk_en) begin - if ((~fifo_en) || (valid0 && ready0 && (~(empty && ready1 && valid1)))) begin - value <= data_in; - end - end -end - -always_ff @(posedge clk, posedge rst) begin - if (rst) begin - empty_n <= 1'h0; - end - else if (clk_en) begin - if (fifo_en) begin - if (valid1 && ready1) begin - if (~(valid0 && ready0)) begin - empty_n <= 1'h0; - end - end - else if (valid0 && ready0) begin - empty_n <= 1'h1; - end - end - end -end -endmodule // SplitFifo_17 - diff --git a/sam/onyx/.magma/io_core_W-kratos.sv b/sam/onyx/.magma/io_core_W-kratos.sv deleted file mode 100644 index 6b07ee15..00000000 --- a/sam/onyx/.magma/io_core_W-kratos.sv +++ /dev/null @@ -1,376 +0,0 @@ -module io_core ( - input logic clk, - input logic clk_en, - input logic f2io_1, - input logic [16:0] f2io_17, - input logic f2io_17_valid, - input logic f2io_1_valid, - input logic flush, - input logic glb2io_1, - input logic [16:0] glb2io_17, - input logic glb2io_17_valid, - input logic glb2io_1_valid, - input logic io2f_17_ready, - input logic io2f_1_ready, - input logic io2glb_17_ready, - input logic io2glb_1_ready, - input logic rst_n, - input logic tile_en, - output logic f2io_17_ready, - output logic f2io_1_ready, - output logic glb2io_17_ready, - output logic glb2io_1_ready, - output logic io2f_1, - output logic [16:0] io2f_17, - output logic io2f_17_valid, - output logic io2f_1_valid, - output logic io2glb_1, - output logic [16:0] io2glb_17, - output logic io2glb_17_valid, - output logic io2glb_1_valid -); - -logic [0:0][16:0] f2io_2_io2glb_17_data_out; -logic f2io_2_io2glb_17_empty; -logic f2io_2_io2glb_17_full; -logic [0:0] f2io_2_io2glb_1_data_out; -logic f2io_2_io2glb_1_empty; -logic f2io_2_io2glb_1_full; -logic gclk; -logic glb2io_2_io2f_17_empty; -logic glb2io_2_io2f_17_full; -logic glb2io_2_io2f_1_empty; -logic glb2io_2_io2f_1_full; -assign gclk = clk & tile_en; -assign io2glb_1 = f2io_2_io2glb_1_data_out; -assign f2io_1_ready = ~f2io_2_io2glb_1_full; -assign io2glb_1_valid = ~f2io_2_io2glb_1_empty; -assign glb2io_1_ready = ~glb2io_2_io2f_1_full; -assign io2f_1_valid = ~glb2io_2_io2f_1_empty; -assign io2glb_17 = f2io_2_io2glb_17_data_out[0][16:0]; -assign f2io_17_ready = ~f2io_2_io2glb_17_full; -assign io2glb_17_valid = ~f2io_2_io2glb_17_empty; -assign glb2io_17_ready = ~glb2io_2_io2f_17_full; -assign io2f_17_valid = ~glb2io_2_io2f_17_empty; -reg_fifo_depth_2_w_1_afd_1_iocore_nof f2io_2_io2glb_1 ( - .clk(clk), - .clk_en(clk_en), - .data_in(f2io_1), - .flush(flush), - .pop(io2glb_1_ready), - .push(f2io_1_valid), - .rst_n(rst_n), - .data_out(f2io_2_io2glb_1_data_out), - .empty(f2io_2_io2glb_1_empty), - .full(f2io_2_io2glb_1_full) -); - -reg_fifo_depth_2_w_1_afd_1_iocore_nof glb2io_2_io2f_1 ( - .clk(gclk), - .clk_en(clk_en), - .data_in(glb2io_1), - .flush(flush), - .pop(io2f_1_ready), - .push(glb2io_1_valid), - .rst_n(rst_n), - .data_out(io2f_1), - .empty(glb2io_2_io2f_1_empty), - .full(glb2io_2_io2f_1_full) -); - -reg_fifo_depth_2_w_17_afd_1_iocore_nof f2io_2_io2glb_17 ( - .clk(clk), - .clk_en(clk_en), - .data_in(f2io_17), - .flush(flush), - .pop(io2glb_17_ready), - .push(f2io_17_valid), - .rst_n(rst_n), - .data_out(f2io_2_io2glb_17_data_out), - .empty(f2io_2_io2glb_17_empty), - .full(f2io_2_io2glb_17_full) -); - -reg_fifo_depth_2_w_17_afd_1_iocore_nof glb2io_2_io2f_17 ( - .clk(gclk), - .clk_en(clk_en), - .data_in(glb2io_17), - .flush(flush), - .pop(io2f_17_ready), - .push(glb2io_17_valid), - .rst_n(rst_n), - .data_out(io2f_17), - .empty(glb2io_2_io2f_17_empty), - .full(glb2io_2_io2f_17_full) -); - -endmodule // io_core - -module io_core_W ( - input logic clk, - input logic clk_en, - input logic f2io_1, - input logic [16:0] f2io_17, - input logic f2io_17_valid, - input logic f2io_1_valid, - input logic flush, - input logic glb2io_1, - input logic [16:0] glb2io_17, - input logic glb2io_17_valid, - input logic glb2io_1_valid, - input logic io2f_17_ready, - input logic io2f_1_ready, - input logic io2glb_17_ready, - input logic io2glb_1_ready, - input logic rst_n, - input logic tile_en, - output logic f2io_17_ready, - output logic f2io_1_ready, - output logic glb2io_17_ready, - output logic glb2io_1_ready, - output logic io2f_1, - output logic [16:0] io2f_17, - output logic io2f_17_valid, - output logic io2f_1_valid, - output logic io2glb_1, - output logic [16:0] io2glb_17, - output logic io2glb_17_valid, - output logic io2glb_1_valid -); - -io_core io_core ( - .clk(clk), - .clk_en(clk_en), - .f2io_1(f2io_1), - .f2io_17(f2io_17), - .f2io_17_valid(f2io_17_valid), - .f2io_1_valid(f2io_1_valid), - .flush(flush), - .glb2io_1(glb2io_1), - .glb2io_17(glb2io_17), - .glb2io_17_valid(glb2io_17_valid), - .glb2io_1_valid(glb2io_1_valid), - .io2f_17_ready(io2f_17_ready), - .io2f_1_ready(io2f_1_ready), - .io2glb_17_ready(io2glb_17_ready), - .io2glb_1_ready(io2glb_1_ready), - .rst_n(rst_n), - .tile_en(tile_en), - .f2io_17_ready(f2io_17_ready), - .f2io_1_ready(f2io_1_ready), - .glb2io_17_ready(glb2io_17_ready), - .glb2io_1_ready(glb2io_1_ready), - .io2f_1(io2f_1), - .io2f_17(io2f_17), - .io2f_17_valid(io2f_17_valid), - .io2f_1_valid(io2f_1_valid), - .io2glb_1(io2glb_1), - .io2glb_17(io2glb_17), - .io2glb_17_valid(io2glb_17_valid), - .io2glb_1_valid(io2glb_1_valid) -); - -endmodule // io_core_W - -module reg_fifo_depth_2_w_17_afd_1_iocore_nof ( - input logic clk, - input logic clk_en, - input logic [0:0] [16:0] data_in, - input logic flush, - input logic pop, - input logic push, - input logic rst_n, - output logic almost_full, - output logic [0:0] [16:0] data_out, - output logic empty, - output logic full, - output logic valid -); - -logic [1:0] num_items; -logic passthru; -logic rd_ptr; -logic read; -logic [1:0][0:0][16:0] reg_array; -logic wr_ptr; -logic write; -assign full = num_items == 2'h2; -assign almost_full = num_items >= 2'h1; -assign empty = num_items == 2'h0; -assign read = pop & (~passthru) & (~empty); -assign passthru = 1'h0; -assign write = push & (~passthru) & (~full); - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - num_items <= 2'h0; - end - else if (flush) begin - num_items <= 2'h0; - end - else if (clk_en) begin - if (write & (~read)) begin - num_items <= num_items + 2'h1; - end - else if ((~write) & read) begin - num_items <= num_items - 2'h1; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - reg_array <= 34'h0; - end - else if (flush) begin - reg_array <= 34'h0; - end - else if (clk_en) begin - if (write) begin - reg_array[wr_ptr] <= data_in; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - wr_ptr <= 1'h0; - end - else if (flush) begin - wr_ptr <= 1'h0; - end - else if (clk_en) begin - if (write) begin - if (wr_ptr == 1'h1) begin - wr_ptr <= 1'h0; - end - else wr_ptr <= wr_ptr + 1'h1; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - rd_ptr <= 1'h0; - end - else if (flush) begin - rd_ptr <= 1'h0; - end - else if (clk_en) begin - if (read) begin - rd_ptr <= rd_ptr + 1'h1; - end - end -end -always_comb begin - if (passthru) begin - data_out = data_in; - end - else data_out = reg_array[rd_ptr]; -end -always_comb begin - valid = (~empty) | passthru; -end -endmodule // reg_fifo_depth_2_w_17_afd_1_iocore_nof - -module reg_fifo_depth_2_w_1_afd_1_iocore_nof ( - input logic clk, - input logic clk_en, - input logic [0:0] data_in, - input logic flush, - input logic pop, - input logic push, - input logic rst_n, - output logic almost_full, - output logic [0:0] data_out, - output logic empty, - output logic full, - output logic valid -); - -logic [1:0] num_items; -logic passthru; -logic rd_ptr; -logic read; -logic [1:0][0:0] reg_array; -logic wr_ptr; -logic write; -assign full = num_items == 2'h2; -assign almost_full = num_items >= 2'h1; -assign empty = num_items == 2'h0; -assign read = pop & (~passthru) & (~empty); -assign passthru = 1'h0; -assign write = push & (~passthru) & (~full); - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - num_items <= 2'h0; - end - else if (flush) begin - num_items <= 2'h0; - end - else if (clk_en) begin - if (write & (~read)) begin - num_items <= num_items + 2'h1; - end - else if ((~write) & read) begin - num_items <= num_items - 2'h1; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - reg_array <= 2'h0; - end - else if (flush) begin - reg_array <= 2'h0; - end - else if (clk_en) begin - if (write) begin - reg_array[wr_ptr] <= data_in; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - wr_ptr <= 1'h0; - end - else if (flush) begin - wr_ptr <= 1'h0; - end - else if (clk_en) begin - if (write) begin - if (wr_ptr == 1'h1) begin - wr_ptr <= 1'h0; - end - else wr_ptr <= wr_ptr + 1'h1; - end - end -end - -always_ff @(posedge clk, negedge rst_n) begin - if (~rst_n) begin - rd_ptr <= 1'h0; - end - else if (flush) begin - rd_ptr <= 1'h0; - end - else if (clk_en) begin - if (read) begin - rd_ptr <= rd_ptr + 1'h1; - end - end -end -always_comb begin - if (passthru) begin - data_out = data_in; - end - else data_out = reg_array[rd_ptr]; -end -always_comb begin - valid = (~empty) | passthru; -end -endmodule // reg_fifo_depth_2_w_1_afd_1_iocore_nof - From c5b457bc6693a9fd43f3a8dc3921e2212776e7a6 Mon Sep 17 00:00:00 2001 From: Bo Wun Cheng Date: Sun, 21 Jan 2024 21:59:30 -0800 Subject: [PATCH 07/18] remove unwanted breakpoint --- sam/onyx/parse_dot.py | 2 -- 1 file changed, 2 deletions(-) diff --git a/sam/onyx/parse_dot.py b/sam/onyx/parse_dot.py index d6b80962..1916c5fa 100644 --- a/sam/onyx/parse_dot.py +++ b/sam/onyx/parse_dot.py @@ -176,8 +176,6 @@ def map_alu(self): metamapper_env = os.environ.copy() metamapper_env["PIPELINED"] = "0" subprocess.run(["python", "/aha/MetaMapper/scripts/map_app.py", self.collat_dir + "/alu_coreir_spec.json"], env=metamapper_env) - breakpoint() - def get_next_seq(self): ret = self.seq From 8cf35f8172e2e522a7dd56a87901f33948422691 Mon Sep 17 00:00:00 2001 From: Bo Wun Cheng Date: Mon, 22 Jan 2024 23:52:01 -0800 Subject: [PATCH 08/18] update parse_dot and compute_node along with relu graphs to support mapping operation with constant using metamapper --- .../sam-outputs/onyx-dot/mat_elemadd_relu.gv | 2 +- .../onyx-dot/matmul_ijk_crddrop_relu.gv | 2 +- .../onyx-dot/spmm_ijk_crddrop_relu.gv | 2 +- compiler/sam-outputs/onyx-dot/spmv_relu.gv | 2 +- sam/onyx/hw_nodes/compute_node.py | 9 ++-- sam/onyx/parse_dot.py | 49 ++++++++++++++----- 6 files changed, 47 insertions(+), 19 deletions(-) diff --git a/compiler/sam-outputs/onyx-dot/mat_elemadd_relu.gv b/compiler/sam-outputs/onyx-dot/mat_elemadd_relu.gv index 6e5a47ae..b0364766 100644 --- a/compiler/sam-outputs/onyx-dot/mat_elemadd_relu.gv +++ b/compiler/sam-outputs/onyx-dot/mat_elemadd_relu.gv @@ -9,7 +9,7 @@ digraph SAM { 5 [comment="type=arrayvals,tensor=C" label="Array Vals: C" color=green2 shape=box style=filled type="arrayvals" tensor="C"] 8 [comment="type=fiberlookup,index=j,tensor=C,mode=1,format=compressed,src=true,root=false" label="FiberLookup j: C1\ncompressed" color=green4 shape=box style=filled type="fiberlookup" index="j" tensor="C" mode="1" format="compressed" src="true" root="false"] 11 [comment="type=fiberlookup,index=i,tensor=C,mode=0,format=compressed,src=true,root=true" label="FiberLookup i: C0\ncompressed" color=green4 shape=box style=filled type="fiberlookup" index="i" tensor="C" mode="0" format="compressed" src="true" root="true"] - 12 [comment="type=max" label="Max 0" color=brown shape=box style=filled type="max"] + 12 [comment="type=smax,const0=0" label="Max 0" color=brown shape=box style=filled type="smax", const0="0"] 13 [comment="type=crddrop,outer=j,inner=val,mode=0" label="CrdDrop Compression j, val" color=orange style=filled type="crddrop" outer="j" inner="val" mode="0"] 0 [comment="type=fiberwrite,mode=vals,tensor=X,size=1*B0_dim*B1_dim,sink=true" label="FiberWrite Vals: X" color=green3 shape=box style=filled type="fiberwrite" tensor="X" mode="vals" size="2*B0_dim*B1_dim" sink="true"] 14 [comment="type=crddrop,outer=i,inner=j" label="CrdDrop i,j" color=orange shape=box style=filled type="crddrop" outer="i" inner="j"] diff --git a/compiler/sam-outputs/onyx-dot/matmul_ijk_crddrop_relu.gv b/compiler/sam-outputs/onyx-dot/matmul_ijk_crddrop_relu.gv index 107d4d2c..b4fb38c9 100644 --- a/compiler/sam-outputs/onyx-dot/matmul_ijk_crddrop_relu.gv +++ b/compiler/sam-outputs/onyx-dot/matmul_ijk_crddrop_relu.gv @@ -18,7 +18,7 @@ digraph SAM { 0 [comment="type=fiberwrite,mode=vals,tensor=X,size=1*B0_dim*C1_dim,sink=true" label="FiberWrite Vals: X" color=green3 shape=box style=filled type="fiberwrite" tensor="X" mode="vals" size="1*B0_dim*C1_dim" sink="true"] 6 [comment="type=arrayvals,tensor=C" label="Array Vals: C" color=green2 shape=box style=filled type="arrayvals" tensor="C"] 9 [comment="type=fiberlookup,index=k,tensor=C,mode=0,format=compressed,src=true,root=false" label="FiberLookup k: C0\ncompressed" color=green4 shape=box style=filled type="fiberlookup" index="k" tensor="C" mode="0" format="compressed" src="true" root="false"] - 20 [comment="type=max" label="Max 0" color=brown shape=box style=filled type="max"] + 20 [comment="type=smax,const0=0" label="Max 0" color=brown shape=box style=filled type="smax", const0="0"] 21 [comment="type=crddrop,outer=j,inner=val,mode=0" label="CrdDrop Compression j, val" color=orange style=filled type="crddrop" outer="j" inner="val" mode="0"] 22 [comment="type=crddrop,outer=i,inner=j" label="CrdDrop i,j" color=orange shape=box style=filled type="crddrop" outer="i" inner="j"] 17 -> 16 [label="crd" style=dashed type="crd" comment=""] diff --git a/compiler/sam-outputs/onyx-dot/spmm_ijk_crddrop_relu.gv b/compiler/sam-outputs/onyx-dot/spmm_ijk_crddrop_relu.gv index 7fdda848..f9414be6 100644 --- a/compiler/sam-outputs/onyx-dot/spmm_ijk_crddrop_relu.gv +++ b/compiler/sam-outputs/onyx-dot/spmm_ijk_crddrop_relu.gv @@ -18,7 +18,7 @@ digraph SAM { 0 [comment="type=fiberwrite,mode=vals,tensor=X,size=1*B0_dim*C1_dim,sink=true" label="FiberWrite Vals: X" color=green3 shape=box style=filled type="fiberwrite" tensor="X" mode="vals" size="1*B0_dim*C1_dim" sink="true"] 6 [comment="type=arrayvals,tensor=C" label="Array Vals: C" color=green2 shape=box style=filled type="arrayvals" tensor="C"] 9 [comment="type=fiberlookup,index=k,tensor=C,mode=0,format=compressed,src=true,root=false" label="FiberLookup k: C0\ncompressed" color=green4 shape=box style=filled type="fiberlookup" index="k" tensor="C" mode="0" format="compressed" src="true" root="false"] - 20 [comment="type=max" label="Max 0" color=brown shape=box style=filled type="max"] + 20 [comment="type=smax,const0=0" label="Max 0" color=brown shape=box style=filled type="smax", const0="0"] 21 [comment="type=crddrop,outer=j,inner=val,mode=0" label="CrdDrop Compression j, val" color=orange style=filled type="crddrop" outer="j" inner="val" mode="0"] 22 [comment="type=crddrop,outer=i,inner=j" label="CrdDrop i,j" color=orange shape=box style=filled type="crddrop" outer="i" inner="j"] 17 -> 16 [label="crd" style=dashed type="crd" comment=""] diff --git a/compiler/sam-outputs/onyx-dot/spmv_relu.gv b/compiler/sam-outputs/onyx-dot/spmv_relu.gv index 55d2bfe1..8bc06419 100644 --- a/compiler/sam-outputs/onyx-dot/spmv_relu.gv +++ b/compiler/sam-outputs/onyx-dot/spmv_relu.gv @@ -13,7 +13,7 @@ digraph SAM { 9 [comment="type=fiberlookup,index=j,tensor=B,mode=1,format=compressed,src=true,root=false" label="FiberLookup j: B1\ncompressed" color=green4 shape=box style=filled type="fiberlookup" index="j" tensor="B" mode="1" format="compressed" src="true" root="false"] - 20 [comment="type=max" label="Max 0" color=brown shape=box style=filled type="max"] + 20 [comment="type=smax,const0=0" label="Max 0" color=brown shape=box style=filled type="smax", const0="0"] 0 [comment="type=fiberwrite,mode=vals,tensor=x,size=1*B0_dim,sink=true" label="FiberWrite Vals: x" color=green3 shape=box style=filled type="fiberwrite" tensor="x" mode="vals" size="1*B0_dim" sink="true"] 21 [comment="type=crddrop,outer=i,inner=val,mode=0" label="CrdDrop Compression i, val" color=orange style=filled type="crddrop" outer="i" inner="val" mode="0"] 2 [comment="type=fiberwrite,index=i,tensor=x,mode=0,format=compressed,segsize=2,crdsize=B0_dim,sink=true" label="FiberWrite i: x0\ncompressed" color=green3 shape=box style=filled type="fiberwrite" index="i" tensor="x" mode="0" format="compressed" segsize="2" crdsize="B0_dim" sink="true"] diff --git a/sam/onyx/hw_nodes/compute_node.py b/sam/onyx/hw_nodes/compute_node.py index 8a6b3329..4f03b655 100644 --- a/sam/onyx/hw_nodes/compute_node.py +++ b/sam/onyx/hw_nodes/compute_node.py @@ -182,11 +182,12 @@ def parse_mapped_json(self, filename, node_id): opcode = "0x" + opcode.split('h')[1] # parse out the mapped input ports for connection in alu_mapped["namespaces"]["global"]["modules"]["ALU_" + node_id + "_mapped"]["connections"]: - src, dest = connection - # if the connection is to the data port of alu - if "self.in" in src: + port0, port1 = connection + if "self.in" in port0: # get the port name of the alu - self.mapped_input_ports.append(dest.split(".")[1].strip("data")) + self.mapped_input_ports.append(port1.split(".")[1].strip("data")) + elif "self.in" in port1: + self.mapped_input_ports.append(port0.split(".")[1].strip("data")) self.opcode = int(opcode, 0) def configure(self, attributes): diff --git a/sam/onyx/parse_dot.py b/sam/onyx/parse_dot.py index 1916c5fa..19654869 100644 --- a/sam/onyx/parse_dot.py +++ b/sam/onyx/parse_dot.py @@ -4,6 +4,7 @@ import coreir import os import subprocess +from hwtypes import BitVector from sam.onyx.hw_nodes.hw_node import HWNodeType @@ -96,22 +97,46 @@ def generate_coreir_spec(self, context, attributes, name): alu_op = "add" else: alu_op = attributes['type'].strip('"') - # import the desired operation from coreir - coreir_op = context.get_namespace("coreir").generators[alu_op] + # import the desired operation from coreir, commonlib, or float_DW + if alu_op in context.get_namespace("coreir").generators: + coreir_op = context.get_namespace("coreir").generators[alu_op] + elif alu_op in context.get_namespace("commonlib").generators: + coreir_op = context.get_namespace("commonlib").generators[alu_op] + elif alu_op in context.get_namespace("float_DW").generators: + coreir_op = context.get_namespace("flaot_DW").generators[alu_op] + else: + raise NotImplementedError(f"{alu_op} is not found in coreir, commonlib, or float_DW lib") # configure the width of the op # FIXME: hardcoded to 16 for now op = coreir_op(width=16) # add the operation instance to the module op_inst = module_def.add_module_instance(alu_op, op) + # instantiate the constant operand instances, if any + const_cnt = 0 + const_inst = [] + for i in range(2): + if f"const{i}" in attributes: + const_cnt += 1 + coreir_const = context.get_namespace("coreir").generators["const"] + const = coreir_const(width=16) + const_value = int(attributes[f"const{i}"].strip('"')) + const_inst.append(module_def.add_module_instance(f"const{i}", const, context.new_values({"value": BitVector[16](const_value)}))) + # connect the input to the op - _input0 = module_def.interface.select("in0").select("0") - _input1 = module_def.interface.select("in1").select("0") + # connect module input to the non-constant alu input ports + for i in range(2 - const_cnt): + _input = module_def.interface.select(f"in{i}").select("0") + _alu_in = op_inst.select(f"in{i}") + module_def.connect(_input, _alu_in) + # connect constant output to alu input ports + if const_cnt > 0: + for i in range(const_cnt, 2): + _const_out = const_inst[i - const_cnt].select("out") + _alu_in = op_inst.select(f"in{i}") + module_def.connect(_const_out, _alu_in) + # connect alu output to module output _output = module_def.interface.select("out") - _alu_in0 = op_inst.select("in0") - _alu_in1 = op_inst.select("in1") _alu_out = op_inst.select("out") - module_def.connect(_input0, _alu_in0) - module_def.connect(_input1, _alu_in1) module_def.connect(_output, _alu_out) module.definition = module_def assert module.definition is not None, "Should have a definitation by now" @@ -120,8 +145,6 @@ def map_nodes(self): ''' Iterate through the nodes and map them to the proper HWNodes ''' - c = coreir.Context() - contains_compute = False for node in self.graph.get_nodes(): # Simple write the HWNodeType attribute if 'hwnode' not in node.get_attributes(): @@ -138,7 +161,7 @@ def map_nodes(self): hw_nt = f"HWNodeType.RepSigGen" elif n_type == "repeat": hw_nt = f"HWNodeType.Repeat" - elif n_type == "mul" or n_type == "add" or n_type == "max" or n_type == "and": + elif n_type == "mul" or n_type == "add" or n_type == "smax" or n_type == "and": hw_nt = f"HWNodeType.Compute" self.alu_nodes.append(node) elif n_type == "fgetfint" or n_type == "fgetffrac" or n_type == "faddiexp": @@ -162,7 +185,11 @@ def map_nodes(self): def map_alu(self): if len(self.alu_nodes) > 0: + # coreir lib is loaded by default, need to load commonlib for smax + # and float_DW for floating point ops c = coreir.Context() + c.load_library("commonlib") + c.load_library("float_DW") # iterate through all compute nodes and generate their coreir spec for alu_node in self.alu_nodes: self.generate_coreir_spec(c, From 010929aa2364fd4148bbfcfbdad728c0dda8d3dc Mon Sep 17 00:00:00 2001 From: Bo Wun Cheng Date: Tue, 23 Jan 2024 00:15:01 -0800 Subject: [PATCH 09/18] fix code style --- sam/onyx/hw_nodes/compute_node.py | 5 +++-- sam/onyx/parse_dot.py | 25 +++++++++++++++---------- 2 files changed, 18 insertions(+), 12 deletions(-) diff --git a/sam/onyx/hw_nodes/compute_node.py b/sam/onyx/hw_nodes/compute_node.py index 4f03b655..b45acd88 100644 --- a/sam/onyx/hw_nodes/compute_node.py +++ b/sam/onyx/hw_nodes/compute_node.py @@ -140,7 +140,7 @@ def connect(self, other, edge, kwargs=None): other_conn = 1 else: assert 0 & "edge connected to faddiexp has to have comment specified to either 'exp' or 'fp'" - else: + else: other_conn = other.mapped_input_ports[other_conn] new_conns = { f'pe_to_pe_{other_conn}': [ @@ -178,7 +178,8 @@ def parse_mapped_json(self, filename, node_id): with open(filename, 'r') as alu_mapped_file: alu_mapped = json.load(alu_mapped_file) # parse out the mapped opcode - opcode = alu_mapped["namespaces"]["global"]["modules"]["ALU_" + node_id + "_mapped"]["instances"]["c0"]["modargs"]["value"][1] + module = alu_mapped["namespaces"]["global"]["modules"]["ALU_" + node_id + "_mapped"] + opcode = module["instances"]["c0"]["modargs"]["value"][1] opcode = "0x" + opcode.split('h')[1] # parse out the mapped input ports for connection in alu_mapped["namespaces"]["global"]["modules"]["ALU_" + node_id + "_mapped"]["connections"]: diff --git a/sam/onyx/parse_dot.py b/sam/onyx/parse_dot.py index 19654869..5b16b562 100644 --- a/sam/onyx/parse_dot.py +++ b/sam/onyx/parse_dot.py @@ -88,8 +88,10 @@ def get_mode_map(self): def generate_coreir_spec(self, context, attributes, name): # FIXME: change this if we want operation with constant # Declare I/O of ALU - module_typ = context.Record({"in0": context.Array(1, context.Array(16, context.BitIn())), "in1": context.Array(1, context.Array(16, context.BitIn())), "out": context.Array(16, context.Bit())}) - module = context.global_namespace.new_module("ALU_" + name, module_typ) + module_typ = context.Record({"in0": context.Array(1, context.Array(16, context.BitIn())), + "in1": context.Array(1, context.Array(16, context.BitIn())), + "out": context.Array(16, context.Bit())}) + module = context.global_namespace.new_module("ALU_" + name, module_typ) assert module.definition is None, "Should not have a definition" module_def = module.new_definition() # FIXME: hack for mapping reduce for now, fix reduce function to integer add @@ -107,7 +109,7 @@ def generate_coreir_spec(self, context, attributes, name): else: raise NotImplementedError(f"{alu_op} is not found in coreir, commonlib, or float_DW lib") # configure the width of the op - # FIXME: hardcoded to 16 for now + # FIXME: hardcoded to 16 for now op = coreir_op(width=16) # add the operation instance to the module op_inst = module_def.add_module_instance(alu_op, op) @@ -120,7 +122,9 @@ def generate_coreir_spec(self, context, attributes, name): coreir_const = context.get_namespace("coreir").generators["const"] const = coreir_const(width=16) const_value = int(attributes[f"const{i}"].strip('"')) - const_inst.append(module_def.add_module_instance(f"const{i}", const, context.new_values({"value": BitVector[16](const_value)}))) + const_inst.append(module_def.add_module_instance(f"const{i}", + const, + context.new_values({"value": BitVector[16](const_value)}))) # connect the input to the op # connect module input to the non-constant alu input ports @@ -134,13 +138,13 @@ def generate_coreir_spec(self, context, attributes, name): _const_out = const_inst[i - const_cnt].select("out") _alu_in = op_inst.select(f"in{i}") module_def.connect(_const_out, _alu_in) - # connect alu output to module output + # connect alu output to module output _output = module_def.interface.select("out") - _alu_out = op_inst.select("out") + _alu_out = op_inst.select("out") module_def.connect(_output, _alu_out) module.definition = module_def assert module.definition is not None, "Should have a definitation by now" - + def map_nodes(self): ''' Iterate through the nodes and map them to the proper HWNodes @@ -196,13 +200,14 @@ def map_alu(self): alu_node.get_attributes(), alu_node.get_name()) c.save_to_file(self.collat_dir + "/alu_coreir_spec.json") - - # use metamapper to map it + + # use metamapper to map it # set environment variable PIPELINED to zero to disable input buffering in the alu # in order to make sure the output comes out within the same cycle the input is given metamapper_env = os.environ.copy() metamapper_env["PIPELINED"] = "0" - subprocess.run(["python", "/aha/MetaMapper/scripts/map_app.py", self.collat_dir + "/alu_coreir_spec.json"], env=metamapper_env) + subprocess.run(["python", "/aha/MetaMapper/scripts/map_app.py", self.collat_dir + "/alu_coreir_spec.json"], + env=metamapper_env) def get_next_seq(self): ret = self.seq From 97cef1e41631f9ef905163e3b875cce7179858a4 Mon Sep 17 00:00:00 2001 From: Bo Wun Cheng Date: Tue, 23 Jan 2024 10:04:15 -0800 Subject: [PATCH 10/18] update compute_node and reduce_node to remove the hacked connection to max --- sam/onyx/hw_nodes/compute_node.py | 5 +---- sam/onyx/hw_nodes/reduce_node.py | 9 +-------- 2 files changed, 2 insertions(+), 12 deletions(-) diff --git a/sam/onyx/hw_nodes/compute_node.py b/sam/onyx/hw_nodes/compute_node.py index b45acd88..622716f8 100644 --- a/sam/onyx/hw_nodes/compute_node.py +++ b/sam/onyx/hw_nodes/compute_node.py @@ -129,10 +129,7 @@ def connect(self, other, edge, kwargs=None): other_pe = other.get_name() other_conn = other.get_num_inputs() pe = self.get_name() - # TODO: remove hack eventually - if 'Max 0' in other.op: - other_conn = 1 - elif 'Faddiexp' in other.op: + if 'Faddiexp' in other.op: comment = edge.get_attributes()["comment"].strip('"') if 'fp' in comment: other_conn = 0 diff --git a/sam/onyx/hw_nodes/reduce_node.py b/sam/onyx/hw_nodes/reduce_node.py index 4a43a9ec..0700373e 100644 --- a/sam/onyx/hw_nodes/reduce_node.py +++ b/sam/onyx/hw_nodes/reduce_node.py @@ -72,17 +72,10 @@ def connect(self, other, edge, kwargs=None): raise NotImplementedError(f'Cannot connect ReduceNode to {other_type}') elif other_type == ComputeNode: pe = other.get_name() - if 'Max 0' in other.op: - other_conn = 1 - else: - other_conn = other.get_num_inputs() + other_conn = other.mapped_input_ports[other.get_num_inputs()] new_conns = { f'reduce_to_pe_{other_conn}': [ - # send output to rd scanner ([(red, "reduce_data_out"), (pe, f"data{other_conn}")], 17), - # ([(red, "eos_out"), (wr_scan, "eos_in_0")], 1), - # ([(wr_scan, "ready_out_0"), (red, "ready_in")], 1), - # ([(red, "valid_out"), (wr_scan, "valid_in_0")], 1), ] } other.update_input_connections() From a32610284337d5c2ee8aaf1476e0f625b18d750f Mon Sep 17 00:00:00 2001 From: Bo Wun Cheng Date: Tue, 23 Jan 2024 11:34:20 -0800 Subject: [PATCH 11/18] remove the need to list all compute node type in map_app() within pasre_dot.py --- sam/onyx/parse_dot.py | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/sam/onyx/parse_dot.py b/sam/onyx/parse_dot.py index 5b16b562..73a61959 100644 --- a/sam/onyx/parse_dot.py +++ b/sam/onyx/parse_dot.py @@ -107,7 +107,7 @@ def generate_coreir_spec(self, context, attributes, name): elif alu_op in context.get_namespace("float_DW").generators: coreir_op = context.get_namespace("flaot_DW").generators[alu_op] else: - raise NotImplementedError(f"{alu_op} is not found in coreir, commonlib, or float_DW lib") + raise NotImplementedError(f"fail to map node {alu_op} to compute") # configure the width of the op # FIXME: hardcoded to 16 for now op = coreir_op(width=16) @@ -165,13 +165,6 @@ def map_nodes(self): hw_nt = f"HWNodeType.RepSigGen" elif n_type == "repeat": hw_nt = f"HWNodeType.Repeat" - elif n_type == "mul" or n_type == "add" or n_type == "smax" or n_type == "and": - hw_nt = f"HWNodeType.Compute" - self.alu_nodes.append(node) - elif n_type == "fgetfint" or n_type == "fgetffrac" or n_type == "faddiexp": - hw_nt = f"HWNodeType.Compute" - elif n_type == "fp_mul" or n_type == "fp_max" or n_type == "fp_add": - hw_nt = f"HWNodeType.Compute" elif n_type == "reduce": hw_nt = f"HWNodeType.Reduce" elif n_type == "intersect" or n_type == "union": @@ -183,8 +176,9 @@ def map_nodes(self): elif n_type == "vectorreducer": hw_nt = f"HWNodeType.VectorReducer" else: - print(n_type) - raise SAMDotGraphLoweringError(f"Node is of type {n_type}") + # if the current node is not any of the primitives, it must be a compute + hw_nt = f"HWNodeType.Compute" + self.alu_nodes.append(node) node.get_attributes()['hwnode'] = hw_nt def map_alu(self): From 5b4f346983a2dd9bf36e4438a4d5c53f9ae5549b Mon Sep 17 00:00:00 2001 From: Bo Wun Cheng Date: Tue, 23 Jan 2024 11:37:10 -0800 Subject: [PATCH 12/18] remove unwanted garnet_PE.v --- sam/onyx/garnet_PE.v | 5223 ------------------------------------------ 1 file changed, 5223 deletions(-) delete mode 100644 sam/onyx/garnet_PE.v diff --git a/sam/onyx/garnet_PE.v b/sam/onyx/garnet_PE.v deleted file mode 100644 index fd0bd370..00000000 --- a/sam/onyx/garnet_PE.v +++ /dev/null @@ -1,5223 +0,0 @@ -module PEGEN_mul_hack #( - parameter exp_bits = 1, - parameter frac_bits = 1, - parameter ieee_compliance = 1 -) ( - input [exp_bits+frac_bits:0] a, - input [exp_bits+frac_bits:0] b, - input [2:0] rnd, - output [exp_bits+frac_bits:0] z, - output [7:0] status -); - -wire [exp_bits+frac_bits:0] int_out; -wire [2:0] results_x; -reg sign; -reg [exp_bits-1:0] exp; -reg [frac_bits:0] frac; - -CW_fp_mult #(.sig_width(frac_bits+3), .exp_width(exp_bits), .ieee_compliance(ieee_compliance)) mul1 (.a({a,3'h0}),.b({b,3'h0}),.rnd(rnd),.z({int_out,results_x}),.status(status)); - -always @(*) begin - sign = int_out[exp_bits+frac_bits]; - exp = int_out[exp_bits+frac_bits-1:frac_bits]; - frac = {1'b0,int_out[frac_bits-1:0]}; - if ((results_x[2]&(results_x[1] | results_x[0])) | (int_out[0] & results_x[2])) begin - frac = frac + 1'd1; - if (~&exp) begin - exp = exp + {{(exp_bits-1){1'b0}},frac[frac_bits]}; - end - end -end -assign z = {sign, exp, frac[frac_bits-1:0]}; - -endmodule - -module PEGEN_add #( - parameter exp_bits = 1, - parameter frac_bits = 1, - parameter ieee_compliance = 1 -) ( - input [exp_bits+frac_bits:0] a, - input [exp_bits+frac_bits:0] b, - input [2:0] rnd, - output [exp_bits+frac_bits:0] z, - output [7:0] status -); -CW_fp_add #(.sig_width(frac_bits), .exp_width(exp_bits), .ieee_compliance(ieee_compliance)) add_inst (.a(a),.b(b),.rnd(rnd),.z(z),.status(status)); -endmodule - -module PEGEN_coreir_xor #( - parameter width = 1 -) ( - input [width-1:0] in0, - input [width-1:0] in1, - output [width-1:0] out -); - assign out = in0 ^ in1; -endmodule - -module PEGEN_coreir_ule #( - parameter width = 1 -) ( - input [width-1:0] in0, - input [width-1:0] in1, - output out -); - assign out = in0 <= in1; -endmodule - -module PEGEN_coreir_ugt #( - parameter width = 1 -) ( - input [width-1:0] in0, - input [width-1:0] in1, - output out -); - assign out = in0 > in1; -endmodule - -module PEGEN_coreir_uge #( - parameter width = 1 -) ( - input [width-1:0] in0, - input [width-1:0] in1, - output out -); - assign out = in0 >= in1; -endmodule - -module PEGEN_coreir_sub #( - parameter width = 1 -) ( - input [width-1:0] in0, - input [width-1:0] in1, - output [width-1:0] out -); - assign out = in0 - in1; -endmodule - -module PEGEN_coreir_slt #( - parameter width = 1 -) ( - input [width-1:0] in0, - input [width-1:0] in1, - output out -); - assign out = $signed(in0) < $signed(in1); -endmodule - -module PEGEN_coreir_sle #( - parameter width = 1 -) ( - input [width-1:0] in0, - input [width-1:0] in1, - output out -); - assign out = $signed(in0) <= $signed(in1); -endmodule - -module PEGEN_coreir_shl #( - parameter width = 1 -) ( - input [width-1:0] in0, - input [width-1:0] in1, - output [width-1:0] out -); - assign out = in0 << in1; -endmodule - -module PEGEN_coreir_sge #( - parameter width = 1 -) ( - input [width-1:0] in0, - input [width-1:0] in1, - output out -); - assign out = $signed(in0) >= $signed(in1); -endmodule - -module PEGEN_coreir_reg_arst #( - parameter width = 1, - parameter arst_posedge = 1, - parameter clk_posedge = 1, - parameter init = 1 -) ( - input clk, - input arst, - input [width-1:0] in, - output [width-1:0] out -); - reg [width-1:0] outReg; - wire real_rst; - assign real_rst = arst_posedge ? arst : ~arst; - wire real_clk; - assign real_clk = clk_posedge ? clk : ~clk; - always @(posedge real_clk, posedge real_rst) begin - if (real_rst) outReg <= init; - else outReg <= in; - end - assign out = outReg; -endmodule - -module PEGEN_coreir_or #( - parameter width = 1 -) ( - input [width-1:0] in0, - input [width-1:0] in1, - output [width-1:0] out -); - assign out = in0 | in1; -endmodule - -module PEGEN_coreir_not #( - parameter width = 1 -) ( - input [width-1:0] in, - output [width-1:0] out -); - assign out = ~in; -endmodule - -module PEGEN_coreir_neg #( - parameter width = 1 -) ( - input [width-1:0] in, - output [width-1:0] out -); - assign out = -in; -endmodule - -module PEGEN_coreir_mux #( - parameter width = 1 -) ( - input [width-1:0] in0, - input [width-1:0] in1, - input sel, - output [width-1:0] out -); - assign out = sel ? in1 : in0; -endmodule - -module PEGEN_coreir_mul #( - parameter width = 1 -) ( - input [width-1:0] in0, - input [width-1:0] in1, - output [width-1:0] out -); - assign out = in0 * in1; -endmodule - -module PEGEN_coreir_lshr #( - parameter width = 1 -) ( - input [width-1:0] in0, - input [width-1:0] in1, - output [width-1:0] out -); - assign out = in0 >> in1; -endmodule - -module PEGEN_coreir_eq #( - parameter width = 1 -) ( - input [width-1:0] in0, - input [width-1:0] in1, - output out -); - assign out = in0 == in1; -endmodule - -module PEGEN_coreir_const #( - parameter width = 1, - parameter value = 1 -) ( - output [width-1:0] out -); - assign out = value; -endmodule - -module PEGEN_float_mul__exp_bits8__frac_bits7 ( - input [15:0] in0, - input [15:0] in1, - output [15:0] out -); -wire [2:0] _$_U1_out; -wire [15:0] mi_z; -wire [7:0] mi_status; -PEGEN_coreir_const #( - .value(3'h1), - .width(3) -) _$_U1 ( - .out(_$_U1_out) -); -PEGEN_mul_hack #( - .exp_bits(8), - .frac_bits(7), - .ieee_compliance(1'b1) -) mi ( - .a(in0), - .b(in1), - .rnd(_$_U1_out), - .z(mi_z), - .status(mi_status) -); -assign out = mi_z; -endmodule - -module PEGEN_float_add__exp_bits8__frac_bits7 ( - input [15:0] in0, - input [15:0] in1, - output [15:0] out -); -wire [2:0] _$_U0_out; -wire [15:0] mi_z; -wire [7:0] mi_status; -PEGEN_coreir_const #( - .value(3'h0), - .width(3) -) _$_U0 ( - .out(_$_U0_out) -); -PEGEN_add #( - .exp_bits(8), - .frac_bits(7), - .ieee_compliance(1'b1) -) mi ( - .a(in0), - .b(in1), - .rnd(_$_U0_out), - .z(mi_z), - .status(mi_status) -); -assign out = mi_z; -endmodule - -module PEGEN_coreir_ashr #( - parameter width = 1 -) ( - input [width-1:0] in0, - input [width-1:0] in1, - output [width-1:0] out -); - assign out = $signed(in0) >>> in1; -endmodule - -module PEGEN_coreir_and #( - parameter width = 1 -) ( - input [width-1:0] in0, - input [width-1:0] in1, - output [width-1:0] out -); - assign out = in0 & in1; -endmodule - -module PEGEN_coreir_add #( - parameter width = 1 -) ( - input [width-1:0] in0, - input [width-1:0] in1, - output [width-1:0] out -); - assign out = in0 + in1; -endmodule - -module PEGEN_corebit_xor ( - input in0, - input in1, - output out -); - assign out = in0 ^ in1; -endmodule - -module PEGEN_corebit_or ( - input in0, - input in1, - output out -); - assign out = in0 | in1; -endmodule - -module PEGEN_corebit_not ( - input in, - output out -); - assign out = ~in; -endmodule - -module PEGEN_corebit_const #( - parameter value = 1 -) ( - output out -); - assign out = value; -endmodule - -module PEGEN_corebit_and ( - input in0, - input in1, - output out -); - assign out = in0 & in1; -endmodule - -module PEGEN_commonlib_muxn__N2__width9 ( - input [8:0] in_data [1:0], - input [0:0] in_sel, - output [8:0] out -); -wire [8:0] _join_out; -PEGEN_coreir_mux #( - .width(9) -) _join ( - .in0(in_data[0]), - .in1(in_data[1]), - .sel(in_sel[0]), - .out(_join_out) -); -assign out = _join_out; -endmodule - -module PEGEN_commonlib_muxn__N2__width8 ( - input [7:0] in_data [1:0], - input [0:0] in_sel, - output [7:0] out -); -wire [7:0] _join_out; -PEGEN_coreir_mux #( - .width(8) -) _join ( - .in0(in_data[0]), - .in1(in_data[1]), - .sel(in_sel[0]), - .out(_join_out) -); -assign out = _join_out; -endmodule - -module PEGEN_commonlib_muxn__N2__width5 ( - input [4:0] in_data [1:0], - input [0:0] in_sel, - output [4:0] out -); -wire [4:0] _join_out; -PEGEN_coreir_mux #( - .width(5) -) _join ( - .in0(in_data[0]), - .in1(in_data[1]), - .sel(in_sel[0]), - .out(_join_out) -); -assign out = _join_out; -endmodule - -module PEGEN_commonlib_muxn__N2__width32 ( - input [31:0] in_data [1:0], - input [0:0] in_sel, - output [31:0] out -); -wire [31:0] _join_out; -PEGEN_coreir_mux #( - .width(32) -) _join ( - .in0(in_data[0]), - .in1(in_data[1]), - .sel(in_sel[0]), - .out(_join_out) -); -assign out = _join_out; -endmodule - -module PEGEN_commonlib_muxn__N2__width3 ( - input [2:0] in_data [1:0], - input [0:0] in_sel, - output [2:0] out -); -wire [2:0] _join_out; -PEGEN_coreir_mux #( - .width(3) -) _join ( - .in0(in_data[0]), - .in1(in_data[1]), - .sel(in_sel[0]), - .out(_join_out) -); -assign out = _join_out; -endmodule - -module PEGEN_commonlib_muxn__N2__width23 ( - input [22:0] in_data [1:0], - input [0:0] in_sel, - output [22:0] out -); -wire [22:0] _join_out; -PEGEN_coreir_mux #( - .width(23) -) _join ( - .in0(in_data[0]), - .in1(in_data[1]), - .sel(in_sel[0]), - .out(_join_out) -); -assign out = _join_out; -endmodule - -module PEGEN_commonlib_muxn__N2__width16 ( - input [15:0] in_data [1:0], - input [0:0] in_sel, - output [15:0] out -); -wire [15:0] _join_out; -PEGEN_coreir_mux #( - .width(16) -) _join ( - .in0(in_data[0]), - .in1(in_data[1]), - .sel(in_sel[0]), - .out(_join_out) -); -assign out = _join_out; -endmodule - -module PEGEN_commonlib_muxn__N2__width1 ( - input [0:0] in_data [1:0], - input [0:0] in_sel, - output [0:0] out -); -wire [0:0] _join_out; -PEGEN_coreir_mux #( - .width(1) -) _join ( - .in0(in_data[0]), - .in1(in_data[1]), - .sel(in_sel[0]), - .out(_join_out) -); -assign out = _join_out; -endmodule - -module PEGEN_Op_unq1 ( - input [15:0] in0, - input [15:0] in1, - output [15:0] O, - input CLK, - input ASYNCRESET -); -wire [15:0] magma_BFloat_16_mul_inst0_out; -PEGEN_float_mul__exp_bits8__frac_bits7 magma_BFloat_16_mul_inst0 ( - .in0(in0), - .in1(in1), - .out(magma_BFloat_16_mul_inst0_out) -); -assign O = magma_BFloat_16_mul_inst0_out; -endmodule - -module PEGEN_Op ( - input [15:0] in0, - input [15:0] in1, - output [15:0] O, - input CLK, - input ASYNCRESET -); -wire [15:0] magma_BFloat_16_add_inst0_out; -PEGEN_float_add__exp_bits8__frac_bits7 magma_BFloat_16_add_inst0 ( - .in0(in0), - .in1(in1), - .out(magma_BFloat_16_add_inst0_out) -); -assign O = magma_BFloat_16_add_inst0_out; -endmodule - -module PEGEN_Mux2xUInt32 ( - input [31:0] I0, - input [31:0] I1, - input S, - output [31:0] O -); -wire [31:0] coreir_commonlib_mux2x32_inst0_out; -wire [31:0] coreir_commonlib_mux2x32_inst0_in_data [1:0]; -assign coreir_commonlib_mux2x32_inst0_in_data[1] = I1; -assign coreir_commonlib_mux2x32_inst0_in_data[0] = I0; -PEGEN_commonlib_muxn__N2__width32 coreir_commonlib_mux2x32_inst0 ( - .in_data(coreir_commonlib_mux2x32_inst0_in_data), - .in_sel(S), - .out(coreir_commonlib_mux2x32_inst0_out) -); -assign O = coreir_commonlib_mux2x32_inst0_out; -endmodule - -module PEGEN_Mux2xUInt16 ( - input [15:0] I0, - input [15:0] I1, - input S, - output [15:0] O -); -wire [15:0] coreir_commonlib_mux2x16_inst0_out; -wire [15:0] coreir_commonlib_mux2x16_inst0_in_data [1:0]; -assign coreir_commonlib_mux2x16_inst0_in_data[1] = I1; -assign coreir_commonlib_mux2x16_inst0_in_data[0] = I0; -PEGEN_commonlib_muxn__N2__width16 coreir_commonlib_mux2x16_inst0 ( - .in_data(coreir_commonlib_mux2x16_inst0_in_data), - .in_sel(S), - .out(coreir_commonlib_mux2x16_inst0_out) -); -assign O = coreir_commonlib_mux2x16_inst0_out; -endmodule - -module PEGEN_Mux2xSInt9 ( - input [8:0] I0, - input [8:0] I1, - input S, - output [8:0] O -); -wire [8:0] coreir_commonlib_mux2x9_inst0_out; -wire [8:0] coreir_commonlib_mux2x9_inst0_in_data [1:0]; -assign coreir_commonlib_mux2x9_inst0_in_data[1] = I1; -assign coreir_commonlib_mux2x9_inst0_in_data[0] = I0; -PEGEN_commonlib_muxn__N2__width9 coreir_commonlib_mux2x9_inst0 ( - .in_data(coreir_commonlib_mux2x9_inst0_in_data), - .in_sel(S), - .out(coreir_commonlib_mux2x9_inst0_out) -); -assign O = coreir_commonlib_mux2x9_inst0_out; -endmodule - -module PEGEN_Mux2xSInt16 ( - input [15:0] I0, - input [15:0] I1, - input S, - output [15:0] O -); -wire [15:0] coreir_commonlib_mux2x16_inst0_out; -wire [15:0] coreir_commonlib_mux2x16_inst0_in_data [1:0]; -assign coreir_commonlib_mux2x16_inst0_in_data[1] = I1; -assign coreir_commonlib_mux2x16_inst0_in_data[0] = I0; -PEGEN_commonlib_muxn__N2__width16 coreir_commonlib_mux2x16_inst0 ( - .in_data(coreir_commonlib_mux2x16_inst0_in_data), - .in_sel(S), - .out(coreir_commonlib_mux2x16_inst0_out) -); -assign O = coreir_commonlib_mux2x16_inst0_out; -endmodule - -module PEGEN_Mux2xMagmaADTFPU_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3 ( - input [2:0] I0, - input [2:0] I1, - input S, - output [2:0] O -); -wire [2:0] coreir_commonlib_mux2x3_inst0_out; -wire [2:0] coreir_commonlib_mux2x3_inst0_in_data [1:0]; -assign coreir_commonlib_mux2x3_inst0_in_data[1] = I1; -assign coreir_commonlib_mux2x3_inst0_in_data[0] = I0; -PEGEN_commonlib_muxn__N2__width3 coreir_commonlib_mux2x3_inst0 ( - .in_data(coreir_commonlib_mux2x3_inst0_in_data), - .in_sel(S), - .out(coreir_commonlib_mux2x3_inst0_out) -); -assign O = coreir_commonlib_mux2x3_inst0_out; -endmodule - -module PEGEN_Mux2xMagmaADTFPCustom_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3 ( - input [2:0] I0, - input [2:0] I1, - input S, - output [2:0] O -); -wire [2:0] coreir_commonlib_mux2x3_inst0_out; -wire [2:0] coreir_commonlib_mux2x3_inst0_in_data [1:0]; -assign coreir_commonlib_mux2x3_inst0_in_data[1] = I1; -assign coreir_commonlib_mux2x3_inst0_in_data[0] = I0; -PEGEN_commonlib_muxn__N2__width3 coreir_commonlib_mux2x3_inst0 ( - .in_data(coreir_commonlib_mux2x3_inst0_in_data), - .in_sel(S), - .out(coreir_commonlib_mux2x3_inst0_out) -); -assign O = coreir_commonlib_mux2x3_inst0_out; -endmodule - -module PEGEN_Mux2xMagmaADTALU_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3 ( - input [4:0] I0, - input [4:0] I1, - input S, - output [4:0] O -); -wire [4:0] coreir_commonlib_mux2x5_inst0_out; -wire [4:0] coreir_commonlib_mux2x5_inst0_in_data [1:0]; -assign coreir_commonlib_mux2x5_inst0_in_data[1] = I1; -assign coreir_commonlib_mux2x5_inst0_in_data[0] = I0; -PEGEN_commonlib_muxn__N2__width5 coreir_commonlib_mux2x5_inst0 ( - .in_data(coreir_commonlib_mux2x5_inst0_in_data), - .in_sel(S), - .out(coreir_commonlib_mux2x5_inst0_out) -); -assign O = coreir_commonlib_mux2x5_inst0_out; -endmodule - -module PEGEN_Mux2xBits8 ( - input [7:0] I0, - input [7:0] I1, - input S, - output [7:0] O -); -wire [7:0] coreir_commonlib_mux2x8_inst0_out; -wire [7:0] coreir_commonlib_mux2x8_inst0_in_data [1:0]; -assign coreir_commonlib_mux2x8_inst0_in_data[1] = I1; -assign coreir_commonlib_mux2x8_inst0_in_data[0] = I0; -PEGEN_commonlib_muxn__N2__width8 coreir_commonlib_mux2x8_inst0 ( - .in_data(coreir_commonlib_mux2x8_inst0_in_data), - .in_sel(S), - .out(coreir_commonlib_mux2x8_inst0_out) -); -assign O = coreir_commonlib_mux2x8_inst0_out; -endmodule - -module PEGEN_Mux2xBits23 ( - input [22:0] I0, - input [22:0] I1, - input S, - output [22:0] O -); -wire [22:0] coreir_commonlib_mux2x23_inst0_out; -wire [22:0] coreir_commonlib_mux2x23_inst0_in_data [1:0]; -assign coreir_commonlib_mux2x23_inst0_in_data[1] = I1; -assign coreir_commonlib_mux2x23_inst0_in_data[0] = I0; -PEGEN_commonlib_muxn__N2__width23 coreir_commonlib_mux2x23_inst0 ( - .in_data(coreir_commonlib_mux2x23_inst0_in_data), - .in_sel(S), - .out(coreir_commonlib_mux2x23_inst0_out) -); -assign O = coreir_commonlib_mux2x23_inst0_out; -endmodule - -module PEGEN_Mux2xBits16 ( - input [15:0] I0, - input [15:0] I1, - input S, - output [15:0] O -); -wire [15:0] coreir_commonlib_mux2x16_inst0_out; -wire [15:0] coreir_commonlib_mux2x16_inst0_in_data [1:0]; -assign coreir_commonlib_mux2x16_inst0_in_data[1] = I1; -assign coreir_commonlib_mux2x16_inst0_in_data[0] = I0; -PEGEN_commonlib_muxn__N2__width16 coreir_commonlib_mux2x16_inst0 ( - .in_data(coreir_commonlib_mux2x16_inst0_in_data), - .in_sel(S), - .out(coreir_commonlib_mux2x16_inst0_out) -); -assign O = coreir_commonlib_mux2x16_inst0_out; -endmodule - -module PEGEN_Register ( - input [15:0] value, - output [15:0] O, - input en, - input CLK, - input ASYNCRESET -); -wire [15:0] enable_mux_O; -wire [15:0] reg_PR16_inst0_out; -PEGEN_Mux2xBits16 enable_mux ( - .I0(reg_PR16_inst0_out), - .I1(value), - .S(en), - .O(enable_mux_O) -); -PEGEN_coreir_reg_arst #( - .arst_posedge(1'b1), - .clk_posedge(1'b1), - .init(16'h0000), - .width(16) -) reg_PR16_inst0 ( - .clk(CLK), - .arst(ASYNCRESET), - .in(enable_mux_O), - .out(reg_PR16_inst0_out) -); -assign O = reg_PR16_inst0_out; -endmodule - -module PEGEN_Mux2xBit ( - input I0, - input I1, - input S, - output O -); -wire [0:0] coreir_commonlib_mux2x1_inst0_out; -wire [0:0] coreir_commonlib_mux2x1_inst0_in_data [1:0]; -assign coreir_commonlib_mux2x1_inst0_in_data[1] = I1; -assign coreir_commonlib_mux2x1_inst0_in_data[0] = I0; -PEGEN_commonlib_muxn__N2__width1 coreir_commonlib_mux2x1_inst0 ( - .in_data(coreir_commonlib_mux2x1_inst0_in_data), - .in_sel(S), - .out(coreir_commonlib_mux2x1_inst0_out) -); -assign O = coreir_commonlib_mux2x1_inst0_out[0]; -endmodule - -module PEGEN_Register_unq1 ( - input value, - output O, - input en, - input CLK, - input ASYNCRESET -); -wire enable_mux_O; -wire [0:0] reg_PR1_inst0_out; -PEGEN_Mux2xBit enable_mux ( - .I0(reg_PR1_inst0_out[0]), - .I1(value), - .S(en), - .O(enable_mux_O) -); -PEGEN_coreir_reg_arst #( - .arst_posedge(1'b1), - .clk_posedge(1'b1), - .init(1'h0), - .width(1) -) reg_PR1_inst0 ( - .clk(CLK), - .arst(ASYNCRESET), - .in(enable_mux_O), - .out(reg_PR1_inst0_out) -); -assign O = reg_PR1_inst0_out[0]; -endmodule - -module PEGEN_RegisterMode_unq1 ( - input [1:0] mode, - input const_, - input value, - input clk_en, - output O0, - output O1, - input CLK, - input ASYNCRESET -); -wire Mux2xBit_inst0_O; -wire Mux2xBit_inst1_O; -wire Mux2xBit_inst2_O; -wire Mux2xBit_inst3_O; -wire Mux2xBit_inst4_O; -wire Mux2xBit_inst5_O; -wire Register_inst0_O; -wire bit_const_0_None_out; -wire [1:0] const_0_2_out; -wire [1:0] const_2_2_out; -wire [1:0] const_3_2_out; -wire magma_Bits_2_eq_inst0_out; -wire magma_Bits_2_eq_inst1_out; -wire magma_Bits_2_eq_inst2_out; -PEGEN_Mux2xBit Mux2xBit_inst0 ( - .I0(value), - .I1(value), - .S(magma_Bits_2_eq_inst0_out), - .O(Mux2xBit_inst0_O) -); -PEGEN_Mux2xBit Mux2xBit_inst1 ( - .I0(bit_const_0_None_out), - .I1(clk_en), - .S(magma_Bits_2_eq_inst0_out), - .O(Mux2xBit_inst1_O) -); -PEGEN_Mux2xBit Mux2xBit_inst2 ( - .I0(Register_inst0_O), - .I1(value), - .S(magma_Bits_2_eq_inst2_out), - .O(Mux2xBit_inst2_O) -); -PEGEN_Mux2xBit Mux2xBit_inst3 ( - .I0(Register_inst0_O), - .I1(Register_inst0_O), - .S(magma_Bits_2_eq_inst2_out), - .O(Mux2xBit_inst3_O) -); -PEGEN_Mux2xBit Mux2xBit_inst4 ( - .I0(Mux2xBit_inst2_O), - .I1(const_), - .S(magma_Bits_2_eq_inst1_out), - .O(Mux2xBit_inst4_O) -); -PEGEN_Mux2xBit Mux2xBit_inst5 ( - .I0(Mux2xBit_inst3_O), - .I1(Register_inst0_O), - .S(magma_Bits_2_eq_inst1_out), - .O(Mux2xBit_inst5_O) -); -PEGEN_Register_unq1 Register_inst0 ( - .value(Mux2xBit_inst0_O), - .O(Register_inst0_O), - .en(Mux2xBit_inst1_O), - .CLK(CLK), - .ASYNCRESET(ASYNCRESET) -); -PEGEN_corebit_const #( - .value(1'b0) -) bit_const_0_None ( - .out(bit_const_0_None_out) -); -PEGEN_coreir_const #( - .value(2'h0), - .width(2) -) const_0_2 ( - .out(const_0_2_out) -); -PEGEN_coreir_const #( - .value(2'h2), - .width(2) -) const_2_2 ( - .out(const_2_2_out) -); -PEGEN_coreir_const #( - .value(2'h3), - .width(2) -) const_3_2 ( - .out(const_3_2_out) -); -PEGEN_coreir_eq #( - .width(2) -) magma_Bits_2_eq_inst0 ( - .in0(mode), - .in1(const_3_2_out), - .out(magma_Bits_2_eq_inst0_out) -); -PEGEN_coreir_eq #( - .width(2) -) magma_Bits_2_eq_inst1 ( - .in0(mode), - .in1(const_0_2_out), - .out(magma_Bits_2_eq_inst1_out) -); -PEGEN_coreir_eq #( - .width(2) -) magma_Bits_2_eq_inst2 ( - .in0(mode), - .in1(const_2_2_out), - .out(magma_Bits_2_eq_inst2_out) -); -assign O0 = Mux2xBit_inst4_O; -assign O1 = Mux2xBit_inst5_O; -endmodule - -module PEGEN_RegisterMode ( - input [1:0] mode, - input [15:0] const_, - input [15:0] value, - input clk_en, - output [15:0] O0, - output [15:0] O1, - input CLK, - input ASYNCRESET -); -wire Mux2xBit_inst0_O; -wire [15:0] Mux2xBits16_inst0_O; -wire [15:0] Mux2xBits16_inst1_O; -wire [15:0] Mux2xBits16_inst2_O; -wire [15:0] Mux2xBits16_inst3_O; -wire [15:0] Mux2xBits16_inst4_O; -wire [15:0] Register_inst0_O; -wire bit_const_0_None_out; -wire [1:0] const_0_2_out; -wire [1:0] const_2_2_out; -wire [1:0] const_3_2_out; -wire magma_Bits_2_eq_inst0_out; -wire magma_Bits_2_eq_inst1_out; -wire magma_Bits_2_eq_inst2_out; -PEGEN_Mux2xBit Mux2xBit_inst0 ( - .I0(bit_const_0_None_out), - .I1(clk_en), - .S(magma_Bits_2_eq_inst0_out), - .O(Mux2xBit_inst0_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst0 ( - .I0(value), - .I1(value), - .S(magma_Bits_2_eq_inst0_out), - .O(Mux2xBits16_inst0_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst1 ( - .I0(Register_inst0_O), - .I1(value), - .S(magma_Bits_2_eq_inst2_out), - .O(Mux2xBits16_inst1_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst2 ( - .I0(Register_inst0_O), - .I1(Register_inst0_O), - .S(magma_Bits_2_eq_inst2_out), - .O(Mux2xBits16_inst2_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst3 ( - .I0(Mux2xBits16_inst1_O), - .I1(const_), - .S(magma_Bits_2_eq_inst1_out), - .O(Mux2xBits16_inst3_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst4 ( - .I0(Mux2xBits16_inst2_O), - .I1(Register_inst0_O), - .S(magma_Bits_2_eq_inst1_out), - .O(Mux2xBits16_inst4_O) -); -PEGEN_Register Register_inst0 ( - .value(Mux2xBits16_inst0_O), - .O(Register_inst0_O), - .en(Mux2xBit_inst0_O), - .CLK(CLK), - .ASYNCRESET(ASYNCRESET) -); -PEGEN_corebit_const #( - .value(1'b0) -) bit_const_0_None ( - .out(bit_const_0_None_out) -); -PEGEN_coreir_const #( - .value(2'h0), - .width(2) -) const_0_2 ( - .out(const_0_2_out) -); -PEGEN_coreir_const #( - .value(2'h2), - .width(2) -) const_2_2 ( - .out(const_2_2_out) -); -PEGEN_coreir_const #( - .value(2'h3), - .width(2) -) const_3_2 ( - .out(const_3_2_out) -); -PEGEN_coreir_eq #( - .width(2) -) magma_Bits_2_eq_inst0 ( - .in0(mode), - .in1(const_3_2_out), - .out(magma_Bits_2_eq_inst0_out) -); -PEGEN_coreir_eq #( - .width(2) -) magma_Bits_2_eq_inst1 ( - .in0(mode), - .in1(const_0_2_out), - .out(magma_Bits_2_eq_inst1_out) -); -PEGEN_coreir_eq #( - .width(2) -) magma_Bits_2_eq_inst2 ( - .in0(mode), - .in1(const_2_2_out), - .out(magma_Bits_2_eq_inst2_out) -); -assign O0 = Mux2xBits16_inst3_O; -assign O1 = Mux2xBits16_inst4_O; -endmodule - -module PEGEN_LUT ( - input [7:0] lut, - input bit0, - input bit1, - input bit2, - output O, - input CLK, - input ASYNCRESET -); -wire bit_const_0_None_out; -wire [7:0] const_1_8_out; -wire [7:0] magma_Bits_8_and_inst0_out; -wire [7:0] magma_Bits_8_lshr_inst0_out; -PEGEN_corebit_const #( - .value(1'b0) -) bit_const_0_None ( - .out(bit_const_0_None_out) -); -PEGEN_coreir_const #( - .value(8'h01), - .width(8) -) const_1_8 ( - .out(const_1_8_out) -); -PEGEN_coreir_and #( - .width(8) -) magma_Bits_8_and_inst0 ( - .in0(magma_Bits_8_lshr_inst0_out), - .in1(const_1_8_out), - .out(magma_Bits_8_and_inst0_out) -); -wire [7:0] magma_Bits_8_lshr_inst0_in1; -assign magma_Bits_8_lshr_inst0_in1 = {bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit2,bit1,bit0}; -PEGEN_coreir_lshr #( - .width(8) -) magma_Bits_8_lshr_inst0 ( - .in0(lut), - .in1(magma_Bits_8_lshr_inst0_in1), - .out(magma_Bits_8_lshr_inst0_out) -); -assign O = magma_Bits_8_and_inst0_out[0]; -endmodule - -module PEGEN_FPU ( - input [2:0] fpu_op, - input [15:0] a, - input [15:0] b, - output [15:0] res, - output N, - output Z, - input CLK, - input ASYNCRESET -); -wire Mux2xBit_inst0_O; -wire Mux2xBit_inst1_O; -wire [15:0] Mux2xBits16_inst0_O; -wire [15:0] Mux2xBits16_inst1_O; -wire [15:0] Mux2xBits16_inst2_O; -wire [15:0] Mux2xBits16_inst3_O; -wire [15:0] Op_inst0_O; -wire [15:0] Op_inst1_O; -wire bit_const_1_None_out; -wire [2:0] const_0_3_out; -wire [6:0] const_0_7_out; -wire [7:0] const_0_8_out; -wire [2:0] const_1_3_out; -wire [7:0] const_255_8_out; -wire [2:0] const_2_3_out; -wire [15:0] const_32768_16_out; -wire [2:0] const_4_3_out; -wire magma_Bit_and_inst0_out; -wire magma_Bit_and_inst1_out; -wire magma_Bit_and_inst2_out; -wire magma_Bit_and_inst3_out; -wire magma_Bit_and_inst4_out; -wire magma_Bit_not_inst0_out; -wire magma_Bit_or_inst0_out; -wire magma_Bit_or_inst1_out; -wire magma_Bit_or_inst2_out; -wire magma_Bit_or_inst3_out; -wire magma_Bit_xor_inst0_out; -wire [15:0] magma_Bits_16_xor_inst0_out; -wire magma_Bits_3_eq_inst0_out; -wire magma_Bits_3_eq_inst1_out; -wire magma_Bits_3_eq_inst2_out; -wire magma_Bits_3_eq_inst3_out; -wire magma_Bits_3_eq_inst4_out; -wire magma_Bits_3_eq_inst5_out; -wire magma_Bits_3_eq_inst6_out; -wire magma_Bits_3_eq_inst7_out; -wire magma_Bits_7_eq_inst0_out; -wire magma_Bits_7_eq_inst1_out; -wire magma_Bits_7_eq_inst2_out; -wire magma_Bits_8_eq_inst0_out; -wire magma_Bits_8_eq_inst1_out; -wire magma_Bits_8_eq_inst2_out; -PEGEN_Mux2xBit Mux2xBit_inst0 ( - .I0(magma_Bit_and_inst2_out), - .I1(bit_const_1_None_out), - .S(magma_Bit_and_inst4_out), - .O(Mux2xBit_inst0_O) -); -PEGEN_Mux2xBit Mux2xBit_inst1 ( - .I0(magma_Bit_and_inst2_out), - .I1(Mux2xBit_inst0_O), - .S(magma_Bits_3_eq_inst7_out), - .O(Mux2xBit_inst1_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst0 ( - .I0(b), - .I1(magma_Bits_16_xor_inst0_out), - .S(magma_Bit_or_inst1_out), - .O(Mux2xBits16_inst0_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst1 ( - .I0(a), - .I1(b), - .S(Op_inst0_O[15]), - .O(Mux2xBits16_inst1_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst2 ( - .I0(Op_inst1_O), - .I1(Mux2xBits16_inst1_O), - .S(magma_Bits_3_eq_inst6_out), - .O(Mux2xBits16_inst2_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst3 ( - .I0(Mux2xBits16_inst2_O), - .I1(Op_inst0_O), - .S(magma_Bit_or_inst3_out), - .O(Mux2xBits16_inst3_O) -); -PEGEN_Op Op_inst0 ( - .in0(a), - .in1(Mux2xBits16_inst0_O), - .O(Op_inst0_O), - .CLK(CLK), - .ASYNCRESET(ASYNCRESET) -); -PEGEN_Op_unq1 Op_inst1 ( - .in0(a), - .in1(Mux2xBits16_inst0_O), - .O(Op_inst1_O), - .CLK(CLK), - .ASYNCRESET(ASYNCRESET) -); -PEGEN_corebit_const #( - .value(1'b1) -) bit_const_1_None ( - .out(bit_const_1_None_out) -); -PEGEN_coreir_const #( - .value(3'h0), - .width(3) -) const_0_3 ( - .out(const_0_3_out) -); -PEGEN_coreir_const #( - .value(7'h00), - .width(7) -) const_0_7 ( - .out(const_0_7_out) -); -PEGEN_coreir_const #( - .value(8'h00), - .width(8) -) const_0_8 ( - .out(const_0_8_out) -); -PEGEN_coreir_const #( - .value(3'h1), - .width(3) -) const_1_3 ( - .out(const_1_3_out) -); -PEGEN_coreir_const #( - .value(8'hff), - .width(8) -) const_255_8 ( - .out(const_255_8_out) -); -PEGEN_coreir_const #( - .value(3'h2), - .width(3) -) const_2_3 ( - .out(const_2_3_out) -); -PEGEN_coreir_const #( - .value(16'h8000), - .width(16) -) const_32768_16 ( - .out(const_32768_16_out) -); -PEGEN_coreir_const #( - .value(3'h4), - .width(3) -) const_4_3 ( - .out(const_4_3_out) -); -PEGEN_corebit_and magma_Bit_and_inst0 ( - .in0(magma_Bits_8_eq_inst0_out), - .in1(magma_Bits_7_eq_inst0_out), - .out(magma_Bit_and_inst0_out) -); -PEGEN_corebit_and magma_Bit_and_inst1 ( - .in0(magma_Bits_8_eq_inst1_out), - .in1(magma_Bits_7_eq_inst1_out), - .out(magma_Bit_and_inst1_out) -); -PEGEN_corebit_and magma_Bit_and_inst2 ( - .in0(magma_Bits_8_eq_inst2_out), - .in1(magma_Bits_7_eq_inst2_out), - .out(magma_Bit_and_inst2_out) -); -PEGEN_corebit_and magma_Bit_and_inst3 ( - .in0(magma_Bit_and_inst0_out), - .in1(magma_Bit_and_inst1_out), - .out(magma_Bit_and_inst3_out) -); -PEGEN_corebit_and magma_Bit_and_inst4 ( - .in0(magma_Bit_and_inst3_out), - .in1(magma_Bit_not_inst0_out), - .out(magma_Bit_and_inst4_out) -); -PEGEN_corebit_not magma_Bit_not_inst0 ( - .in(magma_Bit_xor_inst0_out), - .out(magma_Bit_not_inst0_out) -); -PEGEN_corebit_or magma_Bit_or_inst0 ( - .in0(magma_Bits_3_eq_inst0_out), - .in1(magma_Bits_3_eq_inst1_out), - .out(magma_Bit_or_inst0_out) -); -PEGEN_corebit_or magma_Bit_or_inst1 ( - .in0(magma_Bit_or_inst0_out), - .in1(magma_Bits_3_eq_inst2_out), - .out(magma_Bit_or_inst1_out) -); -PEGEN_corebit_or magma_Bit_or_inst2 ( - .in0(magma_Bits_3_eq_inst3_out), - .in1(magma_Bits_3_eq_inst4_out), - .out(magma_Bit_or_inst2_out) -); -PEGEN_corebit_or magma_Bit_or_inst3 ( - .in0(magma_Bit_or_inst2_out), - .in1(magma_Bits_3_eq_inst5_out), - .out(magma_Bit_or_inst3_out) -); -PEGEN_corebit_xor magma_Bit_xor_inst0 ( - .in0(a[15]), - .in1(b[15]), - .out(magma_Bit_xor_inst0_out) -); -PEGEN_coreir_xor #( - .width(16) -) magma_Bits_16_xor_inst0 ( - .in0(b), - .in1(const_32768_16_out), - .out(magma_Bits_16_xor_inst0_out) -); -PEGEN_coreir_eq #( - .width(3) -) magma_Bits_3_eq_inst0 ( - .in0(fpu_op), - .in1(const_1_3_out), - .out(magma_Bits_3_eq_inst0_out) -); -PEGEN_coreir_eq #( - .width(3) -) magma_Bits_3_eq_inst1 ( - .in0(fpu_op), - .in1(const_2_3_out), - .out(magma_Bits_3_eq_inst1_out) -); -PEGEN_coreir_eq #( - .width(3) -) magma_Bits_3_eq_inst2 ( - .in0(fpu_op), - .in1(const_4_3_out), - .out(magma_Bits_3_eq_inst2_out) -); -PEGEN_coreir_eq #( - .width(3) -) magma_Bits_3_eq_inst3 ( - .in0(fpu_op), - .in1(const_0_3_out), - .out(magma_Bits_3_eq_inst3_out) -); -PEGEN_coreir_eq #( - .width(3) -) magma_Bits_3_eq_inst4 ( - .in0(fpu_op), - .in1(const_1_3_out), - .out(magma_Bits_3_eq_inst4_out) -); -PEGEN_coreir_eq #( - .width(3) -) magma_Bits_3_eq_inst5 ( - .in0(fpu_op), - .in1(const_2_3_out), - .out(magma_Bits_3_eq_inst5_out) -); -PEGEN_coreir_eq #( - .width(3) -) magma_Bits_3_eq_inst6 ( - .in0(fpu_op), - .in1(const_4_3_out), - .out(magma_Bits_3_eq_inst6_out) -); -PEGEN_coreir_eq #( - .width(3) -) magma_Bits_3_eq_inst7 ( - .in0(fpu_op), - .in1(const_2_3_out), - .out(magma_Bits_3_eq_inst7_out) -); -PEGEN_coreir_eq #( - .width(7) -) magma_Bits_7_eq_inst0 ( - .in0(a[6:0]), - .in1(const_0_7_out), - .out(magma_Bits_7_eq_inst0_out) -); -PEGEN_coreir_eq #( - .width(7) -) magma_Bits_7_eq_inst1 ( - .in0(b[6:0]), - .in1(const_0_7_out), - .out(magma_Bits_7_eq_inst1_out) -); -PEGEN_coreir_eq #( - .width(7) -) magma_Bits_7_eq_inst2 ( - .in0(Mux2xBits16_inst3_O[6:0]), - .in1(const_0_7_out), - .out(magma_Bits_7_eq_inst2_out) -); -PEGEN_coreir_eq #( - .width(8) -) magma_Bits_8_eq_inst0 ( - .in0(a[14:7]), - .in1(const_255_8_out), - .out(magma_Bits_8_eq_inst0_out) -); -PEGEN_coreir_eq #( - .width(8) -) magma_Bits_8_eq_inst1 ( - .in0(b[14:7]), - .in1(const_255_8_out), - .out(magma_Bits_8_eq_inst1_out) -); -PEGEN_coreir_eq #( - .width(8) -) magma_Bits_8_eq_inst2 ( - .in0(Mux2xBits16_inst3_O[14:7]), - .in1(const_0_8_out), - .out(magma_Bits_8_eq_inst2_out) -); -assign res = Mux2xBits16_inst3_O; -assign N = Mux2xBits16_inst3_O[15]; -assign Z = Mux2xBit_inst1_O; -endmodule - -module PEGEN_FPCustom ( - input [2:0] op, - input [0:0] signed_, - input [15:0] a, - input [15:0] b, - output [15:0] res, - output res_p, - output V, - input CLK, - input ASYNCRESET -); -wire Mux2xBit_inst0_O; -wire Mux2xBit_inst1_O; -wire Mux2xBit_inst10_O; -wire Mux2xBit_inst2_O; -wire Mux2xBit_inst3_O; -wire Mux2xBit_inst4_O; -wire Mux2xBit_inst5_O; -wire Mux2xBit_inst6_O; -wire Mux2xBit_inst7_O; -wire Mux2xBit_inst8_O; -wire Mux2xBit_inst9_O; -wire [15:0] Mux2xBits16_inst0_O; -wire [15:0] Mux2xBits16_inst1_O; -wire [15:0] Mux2xBits16_inst10_O; -wire [15:0] Mux2xBits16_inst11_O; -wire [15:0] Mux2xBits16_inst12_O; -wire [15:0] Mux2xBits16_inst13_O; -wire [15:0] Mux2xBits16_inst14_O; -wire [15:0] Mux2xBits16_inst15_O; -wire [15:0] Mux2xBits16_inst16_O; -wire [15:0] Mux2xBits16_inst17_O; -wire [15:0] Mux2xBits16_inst18_O; -wire [15:0] Mux2xBits16_inst19_O; -wire [15:0] Mux2xBits16_inst2_O; -wire [15:0] Mux2xBits16_inst20_O; -wire [15:0] Mux2xBits16_inst3_O; -wire [15:0] Mux2xBits16_inst4_O; -wire [15:0] Mux2xBits16_inst5_O; -wire [15:0] Mux2xBits16_inst6_O; -wire [15:0] Mux2xBits16_inst7_O; -wire [15:0] Mux2xBits16_inst8_O; -wire [15:0] Mux2xBits16_inst9_O; -wire [22:0] Mux2xBits23_inst0_O; -wire [7:0] Mux2xBits8_inst0_O; -wire [7:0] Mux2xBits8_inst1_O; -wire [7:0] Mux2xBits8_inst2_O; -wire [7:0] Mux2xBits8_inst3_O; -wire [7:0] Mux2xBits8_inst4_O; -wire [7:0] Mux2xBits8_inst5_O; -wire [15:0] Mux2xSInt16_inst0_O; -wire [15:0] Mux2xSInt16_inst1_O; -wire [15:0] Mux2xSInt16_inst10_O; -wire [15:0] Mux2xSInt16_inst11_O; -wire [15:0] Mux2xSInt16_inst12_O; -wire [15:0] Mux2xSInt16_inst13_O; -wire [15:0] Mux2xSInt16_inst14_O; -wire [15:0] Mux2xSInt16_inst15_O; -wire [15:0] Mux2xSInt16_inst16_O; -wire [15:0] Mux2xSInt16_inst17_O; -wire [15:0] Mux2xSInt16_inst18_O; -wire [15:0] Mux2xSInt16_inst19_O; -wire [15:0] Mux2xSInt16_inst2_O; -wire [15:0] Mux2xSInt16_inst20_O; -wire [15:0] Mux2xSInt16_inst21_O; -wire [15:0] Mux2xSInt16_inst22_O; -wire [15:0] Mux2xSInt16_inst23_O; -wire [15:0] Mux2xSInt16_inst24_O; -wire [15:0] Mux2xSInt16_inst25_O; -wire [15:0] Mux2xSInt16_inst26_O; -wire [15:0] Mux2xSInt16_inst27_O; -wire [15:0] Mux2xSInt16_inst28_O; -wire [15:0] Mux2xSInt16_inst29_O; -wire [15:0] Mux2xSInt16_inst3_O; -wire [15:0] Mux2xSInt16_inst30_O; -wire [15:0] Mux2xSInt16_inst4_O; -wire [15:0] Mux2xSInt16_inst5_O; -wire [15:0] Mux2xSInt16_inst6_O; -wire [15:0] Mux2xSInt16_inst7_O; -wire [15:0] Mux2xSInt16_inst8_O; -wire [15:0] Mux2xSInt16_inst9_O; -wire [8:0] Mux2xSInt9_inst0_O; -wire [8:0] Mux2xSInt9_inst1_O; -wire [8:0] Mux2xSInt9_inst10_O; -wire [8:0] Mux2xSInt9_inst11_O; -wire [8:0] Mux2xSInt9_inst12_O; -wire [8:0] Mux2xSInt9_inst2_O; -wire [8:0] Mux2xSInt9_inst3_O; -wire [8:0] Mux2xSInt9_inst4_O; -wire [8:0] Mux2xSInt9_inst5_O; -wire [8:0] Mux2xSInt9_inst6_O; -wire [8:0] Mux2xSInt9_inst7_O; -wire [8:0] Mux2xSInt9_inst8_O; -wire [8:0] Mux2xSInt9_inst9_O; -wire bit_const_0_None_out; -wire bit_const_1_None_out; -wire [15:0] const_0_16_out; -wire [22:0] const_0_23_out; -wire [2:0] const_0_3_out; -wire [8:0] const_0_9_out; -wire [15:0] const_10_16_out; -wire [15:0] const_11_16_out; -wire [15:0] const_127_16_out; -wire [7:0] const_127_8_out; -wire [8:0] const_127_9_out; -wire [15:0] const_128_16_out; -wire [15:0] const_12_16_out; -wire [15:0] const_13_16_out; -wire [7:0] const_142_8_out; -wire [15:0] const_14_16_out; -wire [15:0] const_15_16_out; -wire [0:0] const_1_1_out; -wire [15:0] const_1_16_out; -wire [2:0] const_1_3_out; -wire [8:0] const_255_9_out; -wire [15:0] const_2_16_out; -wire [2:0] const_2_3_out; -wire [15:0] const_32512_16_out; -wire [15:0] const_32640_16_out; -wire [15:0] const_32768_16_out; -wire [15:0] const_3_16_out; -wire [2:0] const_3_3_out; -wire [15:0] const_4_16_out; -wire [2:0] const_4_3_out; -wire [15:0] const_5_16_out; -wire [2:0] const_5_3_out; -wire [15:0] const_65409_16_out; -wire [15:0] const_6_16_out; -wire [2:0] const_6_3_out; -wire [15:0] const_7_16_out; -wire [22:0] const_7_23_out; -wire [15:0] const_8_16_out; -wire [15:0] const_9_16_out; -wire magma_Bit_not_inst0_out; -wire magma_Bit_not_inst1_out; -wire magma_Bit_not_inst10_out; -wire magma_Bit_not_inst11_out; -wire magma_Bit_not_inst12_out; -wire magma_Bit_not_inst13_out; -wire magma_Bit_not_inst14_out; -wire magma_Bit_not_inst15_out; -wire magma_Bit_not_inst16_out; -wire magma_Bit_not_inst17_out; -wire magma_Bit_not_inst18_out; -wire magma_Bit_not_inst19_out; -wire magma_Bit_not_inst2_out; -wire magma_Bit_not_inst20_out; -wire magma_Bit_not_inst21_out; -wire magma_Bit_not_inst22_out; -wire magma_Bit_not_inst23_out; -wire magma_Bit_not_inst24_out; -wire magma_Bit_not_inst3_out; -wire magma_Bit_not_inst4_out; -wire magma_Bit_not_inst5_out; -wire magma_Bit_not_inst6_out; -wire magma_Bit_not_inst7_out; -wire magma_Bit_not_inst8_out; -wire magma_Bit_not_inst9_out; -wire magma_Bit_xor_inst0_out; -wire magma_Bit_xor_inst1_out; -wire magma_Bit_xor_inst10_out; -wire magma_Bit_xor_inst11_out; -wire magma_Bit_xor_inst12_out; -wire magma_Bit_xor_inst13_out; -wire magma_Bit_xor_inst14_out; -wire magma_Bit_xor_inst15_out; -wire magma_Bit_xor_inst16_out; -wire magma_Bit_xor_inst17_out; -wire magma_Bit_xor_inst18_out; -wire magma_Bit_xor_inst19_out; -wire magma_Bit_xor_inst2_out; -wire magma_Bit_xor_inst20_out; -wire magma_Bit_xor_inst21_out; -wire magma_Bit_xor_inst22_out; -wire magma_Bit_xor_inst23_out; -wire magma_Bit_xor_inst24_out; -wire magma_Bit_xor_inst3_out; -wire magma_Bit_xor_inst4_out; -wire magma_Bit_xor_inst5_out; -wire magma_Bit_xor_inst6_out; -wire magma_Bit_xor_inst7_out; -wire magma_Bit_xor_inst8_out; -wire magma_Bit_xor_inst9_out; -wire [15:0] magma_Bits_16_and_inst0_out; -wire [15:0] magma_Bits_16_and_inst1_out; -wire [15:0] magma_Bits_16_and_inst10_out; -wire [15:0] magma_Bits_16_and_inst11_out; -wire [15:0] magma_Bits_16_and_inst12_out; -wire [15:0] magma_Bits_16_and_inst2_out; -wire [15:0] magma_Bits_16_and_inst3_out; -wire [15:0] magma_Bits_16_and_inst4_out; -wire [15:0] magma_Bits_16_and_inst5_out; -wire [15:0] magma_Bits_16_and_inst6_out; -wire [15:0] magma_Bits_16_and_inst7_out; -wire [15:0] magma_Bits_16_and_inst8_out; -wire [15:0] magma_Bits_16_and_inst9_out; -wire magma_Bits_16_eq_inst0_out; -wire magma_Bits_16_eq_inst1_out; -wire [15:0] magma_Bits_16_lshr_inst0_out; -wire [15:0] magma_Bits_16_lshr_inst1_out; -wire [15:0] magma_Bits_16_or_inst0_out; -wire [15:0] magma_Bits_16_or_inst1_out; -wire [15:0] magma_Bits_16_or_inst2_out; -wire [15:0] magma_Bits_16_or_inst3_out; -wire [15:0] magma_Bits_16_or_inst4_out; -wire [15:0] magma_Bits_16_or_inst5_out; -wire [15:0] magma_Bits_16_or_inst6_out; -wire [15:0] magma_Bits_16_or_inst7_out; -wire [15:0] magma_Bits_16_or_inst8_out; -wire [15:0] magma_Bits_16_shl_inst0_out; -wire [15:0] magma_Bits_16_shl_inst1_out; -wire [15:0] magma_Bits_16_shl_inst2_out; -wire [15:0] magma_Bits_16_shl_inst3_out; -wire magma_Bits_1_eq_inst0_out; -wire [22:0] magma_Bits_23_lshr_inst0_out; -wire [22:0] magma_Bits_23_shl_inst0_out; -wire magma_Bits_3_eq_inst0_out; -wire magma_Bits_3_eq_inst1_out; -wire magma_Bits_3_eq_inst2_out; -wire magma_Bits_3_eq_inst3_out; -wire magma_Bits_3_eq_inst4_out; -wire magma_Bits_3_eq_inst5_out; -wire magma_Bits_3_eq_inst6_out; -wire magma_Bits_3_eq_inst7_out; -wire [15:0] magma_SInt_16_add_inst0_out; -wire [15:0] magma_SInt_16_and_inst0_out; -wire [15:0] magma_SInt_16_neg_inst0_out; -wire [15:0] magma_SInt_16_neg_inst1_out; -wire [15:0] magma_SInt_16_neg_inst2_out; -wire magma_SInt_16_sge_inst0_out; -wire [15:0] magma_SInt_16_shl_inst0_out; -wire [15:0] magma_SInt_16_sub_inst0_out; -wire [15:0] magma_SInt_16_sub_inst1_out; -wire [8:0] magma_SInt_9_neg_inst0_out; -wire [8:0] magma_SInt_9_neg_inst1_out; -wire magma_SInt_9_slt_inst0_out; -wire magma_SInt_9_slt_inst1_out; -wire magma_SInt_9_slt_inst2_out; -wire [8:0] magma_SInt_9_sub_inst0_out; -wire [8:0] magma_SInt_9_sub_inst1_out; -wire [8:0] magma_SInt_9_sub_inst2_out; -wire [7:0] magma_UInt_8_add_inst0_out; -wire [7:0] magma_UInt_8_add_inst1_out; -wire [7:0] magma_UInt_8_sub_inst0_out; -wire magma_UInt_8_ugt_inst0_out; -wire [8:0] magma_UInt_9_add_inst0_out; -wire magma_UInt_9_ugt_inst0_out; -PEGEN_Mux2xBit Mux2xBit_inst0 ( - .I0(bit_const_0_None_out), - .I1(bit_const_0_None_out), - .S(magma_Bits_3_eq_inst7_out), - .O(Mux2xBit_inst0_O) -); -PEGEN_Mux2xBit Mux2xBit_inst1 ( - .I0(bit_const_0_None_out), - .I1(magma_UInt_8_ugt_inst0_out), - .S(magma_Bits_3_eq_inst6_out), - .O(Mux2xBit_inst1_O) -); -PEGEN_Mux2xBit Mux2xBit_inst10 ( - .I0(Mux2xBit_inst8_O), - .I1(bit_const_0_None_out), - .S(magma_Bits_3_eq_inst2_out), - .O(Mux2xBit_inst10_O) -); -PEGEN_Mux2xBit Mux2xBit_inst2 ( - .I0(Mux2xBit_inst0_O), - .I1(bit_const_0_None_out), - .S(magma_Bits_3_eq_inst6_out), - .O(Mux2xBit_inst2_O) -); -PEGEN_Mux2xBit Mux2xBit_inst3 ( - .I0(Mux2xBit_inst1_O), - .I1(bit_const_0_None_out), - .S(magma_Bits_3_eq_inst5_out), - .O(Mux2xBit_inst3_O) -); -PEGEN_Mux2xBit Mux2xBit_inst4 ( - .I0(Mux2xBit_inst2_O), - .I1(bit_const_0_None_out), - .S(magma_Bits_3_eq_inst5_out), - .O(Mux2xBit_inst4_O) -); -PEGEN_Mux2xBit Mux2xBit_inst5 ( - .I0(Mux2xBit_inst3_O), - .I1(bit_const_0_None_out), - .S(magma_Bits_3_eq_inst4_out), - .O(Mux2xBit_inst5_O) -); -PEGEN_Mux2xBit Mux2xBit_inst6 ( - .I0(Mux2xBit_inst4_O), - .I1(bit_const_0_None_out), - .S(magma_Bits_3_eq_inst4_out), - .O(Mux2xBit_inst6_O) -); -PEGEN_Mux2xBit Mux2xBit_inst7 ( - .I0(Mux2xBit_inst5_O), - .I1(bit_const_0_None_out), - .S(magma_Bits_3_eq_inst3_out), - .O(Mux2xBit_inst7_O) -); -PEGEN_Mux2xBit Mux2xBit_inst8 ( - .I0(Mux2xBit_inst6_O), - .I1(magma_UInt_9_ugt_inst0_out), - .S(magma_Bits_3_eq_inst3_out), - .O(Mux2xBit_inst8_O) -); -PEGEN_Mux2xBit Mux2xBit_inst9 ( - .I0(Mux2xBit_inst7_O), - .I1(bit_const_0_None_out), - .S(magma_Bits_3_eq_inst2_out), - .O(Mux2xBit_inst9_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst0 ( - .I0(const_0_16_out), - .I1(const_32768_16_out), - .S(magma_SInt_9_slt_inst0_out), - .O(Mux2xBits16_inst0_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst1 ( - .I0(const_0_16_out), - .I1(magma_Bits_16_and_inst0_out), - .S(magma_Bits_1_eq_inst0_out), - .O(Mux2xBits16_inst1_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst10 ( - .I0(magma_Bits_16_and_inst10_out), - .I1(magma_Bits_16_and_inst8_out), - .S(magma_Bits_3_eq_inst6_out), - .O(Mux2xBits16_inst10_O) -); -wire [15:0] Mux2xBits16_inst11_I1; -assign Mux2xBits16_inst11_I1 = {magma_Bits_23_lshr_inst0_out[15],magma_Bits_23_lshr_inst0_out[14],magma_Bits_23_lshr_inst0_out[13],magma_Bits_23_lshr_inst0_out[12],magma_Bits_23_lshr_inst0_out[11],magma_Bits_23_lshr_inst0_out[10],magma_Bits_23_lshr_inst0_out[9],magma_Bits_23_lshr_inst0_out[8],magma_Bits_23_lshr_inst0_out[7],magma_Bits_23_lshr_inst0_out[6],magma_Bits_23_lshr_inst0_out[5],magma_Bits_23_lshr_inst0_out[4],magma_Bits_23_lshr_inst0_out[3],magma_Bits_23_lshr_inst0_out[2],magma_Bits_23_lshr_inst0_out[1],magma_Bits_23_lshr_inst0_out[0]}; -PEGEN_Mux2xBits16 Mux2xBits16_inst11 ( - .I0(magma_Bits_16_and_inst12_out), - .I1(Mux2xBits16_inst11_I1), - .S(magma_Bits_3_eq_inst6_out), - .O(Mux2xBits16_inst11_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst12 ( - .I0(Mux2xBits16_inst9_O), - .I1(magma_Bits_16_or_inst1_out), - .S(magma_Bits_3_eq_inst5_out), - .O(Mux2xBits16_inst12_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst13 ( - .I0(Mux2xBits16_inst8_O), - .I1(magma_Bits_16_and_inst7_out), - .S(magma_Bits_3_eq_inst4_out), - .O(Mux2xBits16_inst13_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst14 ( - .I0(Mux2xBits16_inst12_O), - .I1(magma_Bits_16_or_inst6_out), - .S(magma_Bits_3_eq_inst4_out), - .O(Mux2xBits16_inst14_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst15 ( - .I0(Mux2xBits16_inst10_O), - .I1(magma_Bits_16_and_inst5_out), - .S(magma_Bits_3_eq_inst4_out), - .O(Mux2xBits16_inst15_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst16 ( - .I0(magma_Bits_16_shl_inst2_out), - .I1(magma_Bits_16_shl_inst1_out), - .S(magma_Bits_3_eq_inst3_out), - .O(Mux2xBits16_inst16_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst17 ( - .I0(Mux2xBits16_inst14_O), - .I1(magma_Bits_16_or_inst3_out), - .S(magma_Bits_3_eq_inst3_out), - .O(Mux2xBits16_inst17_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst18 ( - .I0(Mux2xBits16_inst3_O), - .I1(magma_Bits_16_and_inst3_out), - .S(magma_Bits_3_eq_inst3_out), - .O(Mux2xBits16_inst18_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst19 ( - .I0(Mux2xBits16_inst17_O), - .I1(magma_Bits_16_and_inst2_out), - .S(magma_Bits_3_eq_inst2_out), - .O(Mux2xBits16_inst19_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst2 ( - .I0(a), - .I1(magma_SInt_16_neg_inst0_out), - .S(magma_Bit_not_inst8_out), - .O(Mux2xBits16_inst2_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst20 ( - .I0(Mux2xBits16_inst18_O), - .I1(Mux2xBits16_inst3_O), - .S(magma_Bits_3_eq_inst2_out), - .O(Mux2xBits16_inst20_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst3 ( - .I0(Mux2xBits16_inst1_O), - .I1(Mux2xBits16_inst0_O), - .S(magma_Bits_3_eq_inst0_out), - .O(Mux2xBits16_inst3_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst4 ( - .I0(const_0_16_out), - .I1(magma_SInt_16_and_inst0_out), - .S(magma_SInt_16_sge_inst0_out), - .O(Mux2xBits16_inst4_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst5 ( - .I0(Mux2xBits16_inst4_O), - .I1(magma_Bits_16_lshr_inst0_out), - .S(magma_Bits_3_eq_inst1_out), - .O(Mux2xBits16_inst5_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst6 ( - .I0(magma_Bits_16_shl_inst3_out), - .I1(magma_Bits_16_lshr_inst1_out), - .S(magma_SInt_9_slt_inst2_out), - .O(Mux2xBits16_inst6_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst7 ( - .I0(magma_Bits_16_or_inst1_out), - .I1(Mux2xSInt16_inst29_O), - .S(magma_Bits_3_eq_inst7_out), - .O(Mux2xBits16_inst7_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst8 ( - .I0(magma_Bits_16_or_inst8_out), - .I1(magma_Bits_16_or_inst7_out), - .S(magma_Bits_3_eq_inst6_out), - .O(Mux2xBits16_inst8_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst9 ( - .I0(Mux2xBits16_inst7_O), - .I1(Mux2xSInt16_inst28_O), - .S(magma_Bits_3_eq_inst6_out), - .O(Mux2xBits16_inst9_O) -); -PEGEN_Mux2xBits23 Mux2xBits23_inst0 ( - .I0(magma_Bits_23_shl_inst0_out), - .I1(const_0_23_out), - .S(magma_SInt_9_slt_inst1_out), - .O(Mux2xBits23_inst0_O) -); -wire [7:0] Mux2xBits8_inst0_I0; -assign Mux2xBits8_inst0_I0 = {a[14],a[13],a[12],a[11],a[10],a[9],a[8],a[7]}; -wire [7:0] Mux2xBits8_inst0_I1; -assign Mux2xBits8_inst0_I1 = {a[14],a[13],a[12],a[11],a[10],a[9],a[8],a[7]}; -PEGEN_Mux2xBits8 Mux2xBits8_inst0 ( - .I0(Mux2xBits8_inst0_I0), - .I1(Mux2xBits8_inst0_I1), - .S(magma_Bits_3_eq_inst7_out), - .O(Mux2xBits8_inst0_O) -); -wire [7:0] Mux2xBits8_inst1_I1; -assign Mux2xBits8_inst1_I1 = {a[14],a[13],a[12],a[11],a[10],a[9],a[8],a[7]}; -PEGEN_Mux2xBits8 Mux2xBits8_inst1 ( - .I0(Mux2xBits8_inst0_O), - .I1(Mux2xBits8_inst1_I1), - .S(magma_Bits_3_eq_inst6_out), - .O(Mux2xBits8_inst1_O) -); -wire [7:0] Mux2xBits8_inst2_I1; -assign Mux2xBits8_inst2_I1 = {a[14],a[13],a[12],a[11],a[10],a[9],a[8],a[7]}; -PEGEN_Mux2xBits8 Mux2xBits8_inst2 ( - .I0(Mux2xBits8_inst1_O), - .I1(Mux2xBits8_inst2_I1), - .S(magma_Bits_3_eq_inst5_out), - .O(Mux2xBits8_inst2_O) -); -wire [7:0] Mux2xBits8_inst3_I1; -assign Mux2xBits8_inst3_I1 = {a[14],a[13],a[12],a[11],a[10],a[9],a[8],a[7]}; -PEGEN_Mux2xBits8 Mux2xBits8_inst3 ( - .I0(Mux2xBits8_inst2_O), - .I1(Mux2xBits8_inst3_I1), - .S(magma_Bits_3_eq_inst4_out), - .O(Mux2xBits8_inst3_O) -); -wire [7:0] Mux2xBits8_inst4_I1; -assign Mux2xBits8_inst4_I1 = {a[14],a[13],a[12],a[11],a[10],a[9],a[8],a[7]}; -PEGEN_Mux2xBits8 Mux2xBits8_inst4 ( - .I0(Mux2xBits8_inst3_O), - .I1(Mux2xBits8_inst4_I1), - .S(magma_Bits_3_eq_inst3_out), - .O(Mux2xBits8_inst4_O) -); -wire [7:0] Mux2xBits8_inst5_I1; -assign Mux2xBits8_inst5_I1 = {a[14],a[13],a[12],a[11],a[10],a[9],a[8],a[7]}; -PEGEN_Mux2xBits8 Mux2xBits8_inst5 ( - .I0(Mux2xBits8_inst4_O), - .I1(Mux2xBits8_inst5_I1), - .S(magma_Bits_3_eq_inst2_out), - .O(Mux2xBits8_inst5_O) -); -PEGEN_Mux2xSInt16 Mux2xSInt16_inst0 ( - .I0(const_65409_16_out), - .I1(const_0_16_out), - .S(magma_Bit_not_inst0_out), - .O(Mux2xSInt16_inst0_O) -); -PEGEN_Mux2xSInt16 Mux2xSInt16_inst1 ( - .I0(Mux2xSInt16_inst0_O), - .I1(const_1_16_out), - .S(magma_Bit_not_inst1_out), - .O(Mux2xSInt16_inst1_O) -); -PEGEN_Mux2xSInt16 Mux2xSInt16_inst10 ( - .I0(Mux2xSInt16_inst9_O), - .I1(const_2_16_out), - .S(magma_Bit_not_inst11_out), - .O(Mux2xSInt16_inst10_O) -); -PEGEN_Mux2xSInt16 Mux2xSInt16_inst11 ( - .I0(Mux2xSInt16_inst10_O), - .I1(const_3_16_out), - .S(magma_Bit_not_inst12_out), - .O(Mux2xSInt16_inst11_O) -); -PEGEN_Mux2xSInt16 Mux2xSInt16_inst12 ( - .I0(Mux2xSInt16_inst11_O), - .I1(const_4_16_out), - .S(magma_Bit_not_inst13_out), - .O(Mux2xSInt16_inst12_O) -); -PEGEN_Mux2xSInt16 Mux2xSInt16_inst13 ( - .I0(Mux2xSInt16_inst12_O), - .I1(const_5_16_out), - .S(magma_Bit_not_inst14_out), - .O(Mux2xSInt16_inst13_O) -); -PEGEN_Mux2xSInt16 Mux2xSInt16_inst14 ( - .I0(Mux2xSInt16_inst13_O), - .I1(const_6_16_out), - .S(magma_Bit_not_inst15_out), - .O(Mux2xSInt16_inst14_O) -); -PEGEN_Mux2xSInt16 Mux2xSInt16_inst15 ( - .I0(Mux2xSInt16_inst14_O), - .I1(const_7_16_out), - .S(magma_Bit_not_inst16_out), - .O(Mux2xSInt16_inst15_O) -); -PEGEN_Mux2xSInt16 Mux2xSInt16_inst16 ( - .I0(Mux2xSInt16_inst15_O), - .I1(const_8_16_out), - .S(magma_Bit_not_inst17_out), - .O(Mux2xSInt16_inst16_O) -); -PEGEN_Mux2xSInt16 Mux2xSInt16_inst17 ( - .I0(Mux2xSInt16_inst16_O), - .I1(const_9_16_out), - .S(magma_Bit_not_inst18_out), - .O(Mux2xSInt16_inst17_O) -); -PEGEN_Mux2xSInt16 Mux2xSInt16_inst18 ( - .I0(Mux2xSInt16_inst17_O), - .I1(const_10_16_out), - .S(magma_Bit_not_inst19_out), - .O(Mux2xSInt16_inst18_O) -); -PEGEN_Mux2xSInt16 Mux2xSInt16_inst19 ( - .I0(Mux2xSInt16_inst18_O), - .I1(const_11_16_out), - .S(magma_Bit_not_inst20_out), - .O(Mux2xSInt16_inst19_O) -); -PEGEN_Mux2xSInt16 Mux2xSInt16_inst2 ( - .I0(Mux2xSInt16_inst1_O), - .I1(const_2_16_out), - .S(magma_Bit_not_inst2_out), - .O(Mux2xSInt16_inst2_O) -); -PEGEN_Mux2xSInt16 Mux2xSInt16_inst20 ( - .I0(Mux2xSInt16_inst19_O), - .I1(const_12_16_out), - .S(magma_Bit_not_inst21_out), - .O(Mux2xSInt16_inst20_O) -); -PEGEN_Mux2xSInt16 Mux2xSInt16_inst21 ( - .I0(Mux2xSInt16_inst20_O), - .I1(const_13_16_out), - .S(magma_Bit_not_inst22_out), - .O(Mux2xSInt16_inst21_O) -); -PEGEN_Mux2xSInt16 Mux2xSInt16_inst22 ( - .I0(Mux2xSInt16_inst21_O), - .I1(const_14_16_out), - .S(magma_Bit_not_inst23_out), - .O(Mux2xSInt16_inst22_O) -); -PEGEN_Mux2xSInt16 Mux2xSInt16_inst23 ( - .I0(Mux2xSInt16_inst22_O), - .I1(const_15_16_out), - .S(magma_Bit_not_inst24_out), - .O(Mux2xSInt16_inst23_O) -); -PEGEN_Mux2xSInt16 Mux2xSInt16_inst24 ( - .I0(const_32512_16_out), - .I1(const_127_16_out), - .S(magma_Bits_3_eq_inst0_out), - .O(Mux2xSInt16_inst24_O) -); -wire [15:0] Mux2xSInt16_inst25_I1; -assign Mux2xSInt16_inst25_I1 = {Mux2xSInt9_inst0_O[7],Mux2xSInt9_inst0_O[7],Mux2xSInt9_inst0_O[7],Mux2xSInt9_inst0_O[7],Mux2xSInt9_inst0_O[7],Mux2xSInt9_inst0_O[7],Mux2xSInt9_inst0_O[7],Mux2xSInt9_inst0_O[7],Mux2xSInt9_inst0_O[7],Mux2xSInt9_inst0_O[6],Mux2xSInt9_inst0_O[5],Mux2xSInt9_inst0_O[4],Mux2xSInt9_inst0_O[3],Mux2xSInt9_inst0_O[2],Mux2xSInt9_inst0_O[1],Mux2xSInt9_inst0_O[0]}; -PEGEN_Mux2xSInt16 Mux2xSInt16_inst25 ( - .I0(Mux2xBits16_inst2_O), - .I1(Mux2xSInt16_inst25_I1), - .S(magma_Bits_3_eq_inst0_out), - .O(Mux2xSInt16_inst25_O) -); -PEGEN_Mux2xSInt16 Mux2xSInt16_inst26 ( - .I0(magma_SInt_16_sub_inst1_out), - .I1(magma_SInt_16_sub_inst0_out), - .S(magma_Bits_3_eq_inst0_out), - .O(Mux2xSInt16_inst26_O) -); -PEGEN_Mux2xSInt16 Mux2xSInt16_inst27 ( - .I0(Mux2xSInt16_inst23_O), - .I1(Mux2xSInt16_inst7_O), - .S(magma_Bits_3_eq_inst0_out), - .O(Mux2xSInt16_inst27_O) -); -wire [15:0] Mux2xSInt16_inst28_I0; -assign Mux2xSInt16_inst28_I0 = {magma_Bits_23_lshr_inst0_out[15],magma_Bits_23_lshr_inst0_out[14],magma_Bits_23_lshr_inst0_out[13],magma_Bits_23_lshr_inst0_out[12],magma_Bits_23_lshr_inst0_out[11],magma_Bits_23_lshr_inst0_out[10],magma_Bits_23_lshr_inst0_out[9],magma_Bits_23_lshr_inst0_out[8],magma_Bits_23_lshr_inst0_out[7],magma_Bits_23_lshr_inst0_out[6],magma_Bits_23_lshr_inst0_out[5],magma_Bits_23_lshr_inst0_out[4],magma_Bits_23_lshr_inst0_out[3],magma_Bits_23_lshr_inst0_out[2],magma_Bits_23_lshr_inst0_out[1],magma_Bits_23_lshr_inst0_out[0]}; -PEGEN_Mux2xSInt16 Mux2xSInt16_inst28 ( - .I0(Mux2xSInt16_inst28_I0), - .I1(magma_SInt_16_neg_inst1_out), - .S(magma_Bits_16_eq_inst0_out), - .O(Mux2xSInt16_inst28_O) -); -PEGEN_Mux2xSInt16 Mux2xSInt16_inst29 ( - .I0(magma_Bits_16_and_inst12_out), - .I1(magma_SInt_16_neg_inst2_out), - .S(magma_Bits_16_eq_inst1_out), - .O(Mux2xSInt16_inst29_O) -); -PEGEN_Mux2xSInt16 Mux2xSInt16_inst3 ( - .I0(Mux2xSInt16_inst2_O), - .I1(const_3_16_out), - .S(magma_Bit_not_inst3_out), - .O(Mux2xSInt16_inst3_O) -); -PEGEN_Mux2xSInt16 Mux2xSInt16_inst30 ( - .I0(Mux2xSInt16_inst29_O), - .I1(Mux2xSInt16_inst28_O), - .S(magma_Bits_3_eq_inst6_out), - .O(Mux2xSInt16_inst30_O) -); -PEGEN_Mux2xSInt16 Mux2xSInt16_inst4 ( - .I0(Mux2xSInt16_inst3_O), - .I1(const_4_16_out), - .S(magma_Bit_not_inst4_out), - .O(Mux2xSInt16_inst4_O) -); -PEGEN_Mux2xSInt16 Mux2xSInt16_inst5 ( - .I0(Mux2xSInt16_inst4_O), - .I1(const_5_16_out), - .S(magma_Bit_not_inst5_out), - .O(Mux2xSInt16_inst5_O) -); -PEGEN_Mux2xSInt16 Mux2xSInt16_inst6 ( - .I0(Mux2xSInt16_inst5_O), - .I1(const_6_16_out), - .S(magma_Bit_not_inst6_out), - .O(Mux2xSInt16_inst6_O) -); -PEGEN_Mux2xSInt16 Mux2xSInt16_inst7 ( - .I0(Mux2xSInt16_inst6_O), - .I1(const_7_16_out), - .S(magma_Bit_not_inst7_out), - .O(Mux2xSInt16_inst7_O) -); -PEGEN_Mux2xSInt16 Mux2xSInt16_inst8 ( - .I0(const_65409_16_out), - .I1(const_0_16_out), - .S(magma_Bit_not_inst9_out), - .O(Mux2xSInt16_inst8_O) -); -PEGEN_Mux2xSInt16 Mux2xSInt16_inst9 ( - .I0(Mux2xSInt16_inst8_O), - .I1(const_1_16_out), - .S(magma_Bit_not_inst10_out), - .O(Mux2xSInt16_inst9_O) -); -PEGEN_Mux2xSInt9 Mux2xSInt9_inst0 ( - .I0(magma_SInt_9_sub_inst0_out), - .I1(magma_SInt_9_neg_inst0_out), - .S(magma_SInt_9_slt_inst0_out), - .O(Mux2xSInt9_inst0_O) -); -wire [8:0] Mux2xSInt9_inst1_I0; -assign Mux2xSInt9_inst1_I0 = {bit_const_0_None_out,a[14],a[13],a[12],a[11],a[10],a[9],a[8],a[7]}; -wire [8:0] Mux2xSInt9_inst1_I1; -assign Mux2xSInt9_inst1_I1 = {bit_const_0_None_out,a[14],a[13],a[12],a[11],a[10],a[9],a[8],a[7]}; -PEGEN_Mux2xSInt9 Mux2xSInt9_inst1 ( - .I0(Mux2xSInt9_inst1_I0), - .I1(Mux2xSInt9_inst1_I1), - .S(magma_Bits_3_eq_inst7_out), - .O(Mux2xSInt9_inst1_O) -); -PEGEN_Mux2xSInt9 Mux2xSInt9_inst10 ( - .I0(Mux2xSInt9_inst8_O), - .I1(magma_SInt_9_sub_inst0_out), - .S(magma_Bits_3_eq_inst3_out), - .O(Mux2xSInt9_inst10_O) -); -wire [8:0] Mux2xSInt9_inst11_I1; -assign Mux2xSInt9_inst11_I1 = {bit_const_0_None_out,a[14],a[13],a[12],a[11],a[10],a[9],a[8],a[7]}; -PEGEN_Mux2xSInt9 Mux2xSInt9_inst11 ( - .I0(Mux2xSInt9_inst9_O), - .I1(Mux2xSInt9_inst11_I1), - .S(magma_Bits_3_eq_inst2_out), - .O(Mux2xSInt9_inst11_O) -); -PEGEN_Mux2xSInt9 Mux2xSInt9_inst12 ( - .I0(Mux2xSInt9_inst10_O), - .I1(magma_SInt_9_sub_inst0_out), - .S(magma_Bits_3_eq_inst2_out), - .O(Mux2xSInt9_inst12_O) -); -PEGEN_Mux2xSInt9 Mux2xSInt9_inst2 ( - .I0(magma_SInt_9_sub_inst0_out), - .I1(magma_SInt_9_sub_inst2_out), - .S(magma_Bits_3_eq_inst7_out), - .O(Mux2xSInt9_inst2_O) -); -wire [8:0] Mux2xSInt9_inst3_I1; -assign Mux2xSInt9_inst3_I1 = {bit_const_0_None_out,a[14],a[13],a[12],a[11],a[10],a[9],a[8],a[7]}; -PEGEN_Mux2xSInt9 Mux2xSInt9_inst3 ( - .I0(Mux2xSInt9_inst1_O), - .I1(Mux2xSInt9_inst3_I1), - .S(magma_Bits_3_eq_inst6_out), - .O(Mux2xSInt9_inst3_O) -); -PEGEN_Mux2xSInt9 Mux2xSInt9_inst4 ( - .I0(Mux2xSInt9_inst2_O), - .I1(magma_SInt_9_sub_inst1_out), - .S(magma_Bits_3_eq_inst6_out), - .O(Mux2xSInt9_inst4_O) -); -wire [8:0] Mux2xSInt9_inst5_I1; -assign Mux2xSInt9_inst5_I1 = {bit_const_0_None_out,a[14],a[13],a[12],a[11],a[10],a[9],a[8],a[7]}; -PEGEN_Mux2xSInt9 Mux2xSInt9_inst5 ( - .I0(Mux2xSInt9_inst3_O), - .I1(Mux2xSInt9_inst5_I1), - .S(magma_Bits_3_eq_inst5_out), - .O(Mux2xSInt9_inst5_O) -); -PEGEN_Mux2xSInt9 Mux2xSInt9_inst6 ( - .I0(Mux2xSInt9_inst4_O), - .I1(magma_SInt_9_sub_inst0_out), - .S(magma_Bits_3_eq_inst5_out), - .O(Mux2xSInt9_inst6_O) -); -wire [8:0] Mux2xSInt9_inst7_I1; -assign Mux2xSInt9_inst7_I1 = {bit_const_0_None_out,a[14],a[13],a[12],a[11],a[10],a[9],a[8],a[7]}; -PEGEN_Mux2xSInt9 Mux2xSInt9_inst7 ( - .I0(Mux2xSInt9_inst5_O), - .I1(Mux2xSInt9_inst7_I1), - .S(magma_Bits_3_eq_inst4_out), - .O(Mux2xSInt9_inst7_O) -); -PEGEN_Mux2xSInt9 Mux2xSInt9_inst8 ( - .I0(Mux2xSInt9_inst6_O), - .I1(magma_SInt_9_sub_inst0_out), - .S(magma_Bits_3_eq_inst4_out), - .O(Mux2xSInt9_inst8_O) -); -wire [8:0] Mux2xSInt9_inst9_I1; -assign Mux2xSInt9_inst9_I1 = {bit_const_0_None_out,a[14],a[13],a[12],a[11],a[10],a[9],a[8],a[7]}; -PEGEN_Mux2xSInt9 Mux2xSInt9_inst9 ( - .I0(Mux2xSInt9_inst7_O), - .I1(Mux2xSInt9_inst9_I1), - .S(magma_Bits_3_eq_inst3_out), - .O(Mux2xSInt9_inst9_O) -); -PEGEN_corebit_const #( - .value(1'b0) -) bit_const_0_None ( - .out(bit_const_0_None_out) -); -PEGEN_corebit_const #( - .value(1'b1) -) bit_const_1_None ( - .out(bit_const_1_None_out) -); -PEGEN_coreir_const #( - .value(16'h0000), - .width(16) -) const_0_16 ( - .out(const_0_16_out) -); -PEGEN_coreir_const #( - .value(23'h000000), - .width(23) -) const_0_23 ( - .out(const_0_23_out) -); -PEGEN_coreir_const #( - .value(3'h0), - .width(3) -) const_0_3 ( - .out(const_0_3_out) -); -PEGEN_coreir_const #( - .value(9'h000), - .width(9) -) const_0_9 ( - .out(const_0_9_out) -); -PEGEN_coreir_const #( - .value(16'h000a), - .width(16) -) const_10_16 ( - .out(const_10_16_out) -); -PEGEN_coreir_const #( - .value(16'h000b), - .width(16) -) const_11_16 ( - .out(const_11_16_out) -); -PEGEN_coreir_const #( - .value(16'h007f), - .width(16) -) const_127_16 ( - .out(const_127_16_out) -); -PEGEN_coreir_const #( - .value(8'h7f), - .width(8) -) const_127_8 ( - .out(const_127_8_out) -); -PEGEN_coreir_const #( - .value(9'h07f), - .width(9) -) const_127_9 ( - .out(const_127_9_out) -); -PEGEN_coreir_const #( - .value(16'h0080), - .width(16) -) const_128_16 ( - .out(const_128_16_out) -); -PEGEN_coreir_const #( - .value(16'h000c), - .width(16) -) const_12_16 ( - .out(const_12_16_out) -); -PEGEN_coreir_const #( - .value(16'h000d), - .width(16) -) const_13_16 ( - .out(const_13_16_out) -); -PEGEN_coreir_const #( - .value(8'h8e), - .width(8) -) const_142_8 ( - .out(const_142_8_out) -); -PEGEN_coreir_const #( - .value(16'h000e), - .width(16) -) const_14_16 ( - .out(const_14_16_out) -); -PEGEN_coreir_const #( - .value(16'h000f), - .width(16) -) const_15_16 ( - .out(const_15_16_out) -); -PEGEN_coreir_const #( - .value(1'h1), - .width(1) -) const_1_1 ( - .out(const_1_1_out) -); -PEGEN_coreir_const #( - .value(16'h0001), - .width(16) -) const_1_16 ( - .out(const_1_16_out) -); -PEGEN_coreir_const #( - .value(3'h1), - .width(3) -) const_1_3 ( - .out(const_1_3_out) -); -PEGEN_coreir_const #( - .value(9'h0ff), - .width(9) -) const_255_9 ( - .out(const_255_9_out) -); -PEGEN_coreir_const #( - .value(16'h0002), - .width(16) -) const_2_16 ( - .out(const_2_16_out) -); -PEGEN_coreir_const #( - .value(3'h2), - .width(3) -) const_2_3 ( - .out(const_2_3_out) -); -PEGEN_coreir_const #( - .value(16'h7f00), - .width(16) -) const_32512_16 ( - .out(const_32512_16_out) -); -PEGEN_coreir_const #( - .value(16'h7f80), - .width(16) -) const_32640_16 ( - .out(const_32640_16_out) -); -PEGEN_coreir_const #( - .value(16'h8000), - .width(16) -) const_32768_16 ( - .out(const_32768_16_out) -); -PEGEN_coreir_const #( - .value(16'h0003), - .width(16) -) const_3_16 ( - .out(const_3_16_out) -); -PEGEN_coreir_const #( - .value(3'h3), - .width(3) -) const_3_3 ( - .out(const_3_3_out) -); -PEGEN_coreir_const #( - .value(16'h0004), - .width(16) -) const_4_16 ( - .out(const_4_16_out) -); -PEGEN_coreir_const #( - .value(3'h4), - .width(3) -) const_4_3 ( - .out(const_4_3_out) -); -PEGEN_coreir_const #( - .value(16'h0005), - .width(16) -) const_5_16 ( - .out(const_5_16_out) -); -PEGEN_coreir_const #( - .value(3'h5), - .width(3) -) const_5_3 ( - .out(const_5_3_out) -); -PEGEN_coreir_const #( - .value(16'hff81), - .width(16) -) const_65409_16 ( - .out(const_65409_16_out) -); -PEGEN_coreir_const #( - .value(16'h0006), - .width(16) -) const_6_16 ( - .out(const_6_16_out) -); -PEGEN_coreir_const #( - .value(3'h6), - .width(3) -) const_6_3 ( - .out(const_6_3_out) -); -PEGEN_coreir_const #( - .value(16'h0007), - .width(16) -) const_7_16 ( - .out(const_7_16_out) -); -PEGEN_coreir_const #( - .value(23'h000007), - .width(23) -) const_7_23 ( - .out(const_7_23_out) -); -PEGEN_coreir_const #( - .value(16'h0008), - .width(16) -) const_8_16 ( - .out(const_8_16_out) -); -PEGEN_coreir_const #( - .value(16'h0009), - .width(16) -) const_9_16 ( - .out(const_9_16_out) -); -PEGEN_corebit_not magma_Bit_not_inst0 ( - .in(magma_Bit_xor_inst0_out), - .out(magma_Bit_not_inst0_out) -); -PEGEN_corebit_not magma_Bit_not_inst1 ( - .in(magma_Bit_xor_inst1_out), - .out(magma_Bit_not_inst1_out) -); -PEGEN_corebit_not magma_Bit_not_inst10 ( - .in(magma_Bit_xor_inst10_out), - .out(magma_Bit_not_inst10_out) -); -PEGEN_corebit_not magma_Bit_not_inst11 ( - .in(magma_Bit_xor_inst11_out), - .out(magma_Bit_not_inst11_out) -); -PEGEN_corebit_not magma_Bit_not_inst12 ( - .in(magma_Bit_xor_inst12_out), - .out(magma_Bit_not_inst12_out) -); -PEGEN_corebit_not magma_Bit_not_inst13 ( - .in(magma_Bit_xor_inst13_out), - .out(magma_Bit_not_inst13_out) -); -PEGEN_corebit_not magma_Bit_not_inst14 ( - .in(magma_Bit_xor_inst14_out), - .out(magma_Bit_not_inst14_out) -); -PEGEN_corebit_not magma_Bit_not_inst15 ( - .in(magma_Bit_xor_inst15_out), - .out(magma_Bit_not_inst15_out) -); -PEGEN_corebit_not magma_Bit_not_inst16 ( - .in(magma_Bit_xor_inst16_out), - .out(magma_Bit_not_inst16_out) -); -PEGEN_corebit_not magma_Bit_not_inst17 ( - .in(magma_Bit_xor_inst17_out), - .out(magma_Bit_not_inst17_out) -); -PEGEN_corebit_not magma_Bit_not_inst18 ( - .in(magma_Bit_xor_inst18_out), - .out(magma_Bit_not_inst18_out) -); -PEGEN_corebit_not magma_Bit_not_inst19 ( - .in(magma_Bit_xor_inst19_out), - .out(magma_Bit_not_inst19_out) -); -PEGEN_corebit_not magma_Bit_not_inst2 ( - .in(magma_Bit_xor_inst2_out), - .out(magma_Bit_not_inst2_out) -); -PEGEN_corebit_not magma_Bit_not_inst20 ( - .in(magma_Bit_xor_inst20_out), - .out(magma_Bit_not_inst20_out) -); -PEGEN_corebit_not magma_Bit_not_inst21 ( - .in(magma_Bit_xor_inst21_out), - .out(magma_Bit_not_inst21_out) -); -PEGEN_corebit_not magma_Bit_not_inst22 ( - .in(magma_Bit_xor_inst22_out), - .out(magma_Bit_not_inst22_out) -); -PEGEN_corebit_not magma_Bit_not_inst23 ( - .in(magma_Bit_xor_inst23_out), - .out(magma_Bit_not_inst23_out) -); -PEGEN_corebit_not magma_Bit_not_inst24 ( - .in(magma_Bit_xor_inst24_out), - .out(magma_Bit_not_inst24_out) -); -PEGEN_corebit_not magma_Bit_not_inst3 ( - .in(magma_Bit_xor_inst3_out), - .out(magma_Bit_not_inst3_out) -); -PEGEN_corebit_not magma_Bit_not_inst4 ( - .in(magma_Bit_xor_inst4_out), - .out(magma_Bit_not_inst4_out) -); -PEGEN_corebit_not magma_Bit_not_inst5 ( - .in(magma_Bit_xor_inst5_out), - .out(magma_Bit_not_inst5_out) -); -PEGEN_corebit_not magma_Bit_not_inst6 ( - .in(magma_Bit_xor_inst6_out), - .out(magma_Bit_not_inst6_out) -); -PEGEN_corebit_not magma_Bit_not_inst7 ( - .in(magma_Bit_xor_inst7_out), - .out(magma_Bit_not_inst7_out) -); -PEGEN_corebit_not magma_Bit_not_inst8 ( - .in(magma_Bit_xor_inst8_out), - .out(magma_Bit_not_inst8_out) -); -PEGEN_corebit_not magma_Bit_not_inst9 ( - .in(magma_Bit_xor_inst9_out), - .out(magma_Bit_not_inst9_out) -); -PEGEN_corebit_xor magma_Bit_xor_inst0 ( - .in0(Mux2xSInt9_inst0_O[0]), - .in1(bit_const_1_None_out), - .out(magma_Bit_xor_inst0_out) -); -PEGEN_corebit_xor magma_Bit_xor_inst1 ( - .in0(Mux2xSInt9_inst0_O[1]), - .in1(bit_const_1_None_out), - .out(magma_Bit_xor_inst1_out) -); -PEGEN_corebit_xor magma_Bit_xor_inst10 ( - .in0(Mux2xBits16_inst2_O[1]), - .in1(bit_const_1_None_out), - .out(magma_Bit_xor_inst10_out) -); -PEGEN_corebit_xor magma_Bit_xor_inst11 ( - .in0(Mux2xBits16_inst2_O[2]), - .in1(bit_const_1_None_out), - .out(magma_Bit_xor_inst11_out) -); -PEGEN_corebit_xor magma_Bit_xor_inst12 ( - .in0(Mux2xBits16_inst2_O[3]), - .in1(bit_const_1_None_out), - .out(magma_Bit_xor_inst12_out) -); -PEGEN_corebit_xor magma_Bit_xor_inst13 ( - .in0(Mux2xBits16_inst2_O[4]), - .in1(bit_const_1_None_out), - .out(magma_Bit_xor_inst13_out) -); -PEGEN_corebit_xor magma_Bit_xor_inst14 ( - .in0(Mux2xBits16_inst2_O[5]), - .in1(bit_const_1_None_out), - .out(magma_Bit_xor_inst14_out) -); -PEGEN_corebit_xor magma_Bit_xor_inst15 ( - .in0(Mux2xBits16_inst2_O[6]), - .in1(bit_const_1_None_out), - .out(magma_Bit_xor_inst15_out) -); -PEGEN_corebit_xor magma_Bit_xor_inst16 ( - .in0(Mux2xBits16_inst2_O[7]), - .in1(bit_const_1_None_out), - .out(magma_Bit_xor_inst16_out) -); -PEGEN_corebit_xor magma_Bit_xor_inst17 ( - .in0(Mux2xBits16_inst2_O[8]), - .in1(bit_const_1_None_out), - .out(magma_Bit_xor_inst17_out) -); -PEGEN_corebit_xor magma_Bit_xor_inst18 ( - .in0(Mux2xBits16_inst2_O[9]), - .in1(bit_const_1_None_out), - .out(magma_Bit_xor_inst18_out) -); -PEGEN_corebit_xor magma_Bit_xor_inst19 ( - .in0(Mux2xBits16_inst2_O[10]), - .in1(bit_const_1_None_out), - .out(magma_Bit_xor_inst19_out) -); -PEGEN_corebit_xor magma_Bit_xor_inst2 ( - .in0(Mux2xSInt9_inst0_O[2]), - .in1(bit_const_1_None_out), - .out(magma_Bit_xor_inst2_out) -); -PEGEN_corebit_xor magma_Bit_xor_inst20 ( - .in0(Mux2xBits16_inst2_O[11]), - .in1(bit_const_1_None_out), - .out(magma_Bit_xor_inst20_out) -); -PEGEN_corebit_xor magma_Bit_xor_inst21 ( - .in0(Mux2xBits16_inst2_O[12]), - .in1(bit_const_1_None_out), - .out(magma_Bit_xor_inst21_out) -); -PEGEN_corebit_xor magma_Bit_xor_inst22 ( - .in0(Mux2xBits16_inst2_O[13]), - .in1(bit_const_1_None_out), - .out(magma_Bit_xor_inst22_out) -); -PEGEN_corebit_xor magma_Bit_xor_inst23 ( - .in0(Mux2xBits16_inst2_O[14]), - .in1(bit_const_1_None_out), - .out(magma_Bit_xor_inst23_out) -); -PEGEN_corebit_xor magma_Bit_xor_inst24 ( - .in0(Mux2xBits16_inst2_O[15]), - .in1(bit_const_1_None_out), - .out(magma_Bit_xor_inst24_out) -); -PEGEN_corebit_xor magma_Bit_xor_inst3 ( - .in0(Mux2xSInt9_inst0_O[3]), - .in1(bit_const_1_None_out), - .out(magma_Bit_xor_inst3_out) -); -PEGEN_corebit_xor magma_Bit_xor_inst4 ( - .in0(Mux2xSInt9_inst0_O[4]), - .in1(bit_const_1_None_out), - .out(magma_Bit_xor_inst4_out) -); -PEGEN_corebit_xor magma_Bit_xor_inst5 ( - .in0(Mux2xSInt9_inst0_O[5]), - .in1(bit_const_1_None_out), - .out(magma_Bit_xor_inst5_out) -); -PEGEN_corebit_xor magma_Bit_xor_inst6 ( - .in0(Mux2xSInt9_inst0_O[6]), - .in1(bit_const_1_None_out), - .out(magma_Bit_xor_inst6_out) -); -PEGEN_corebit_xor magma_Bit_xor_inst7 ( - .in0(Mux2xSInt9_inst0_O[7]), - .in1(bit_const_1_None_out), - .out(magma_Bit_xor_inst7_out) -); -PEGEN_corebit_xor magma_Bit_xor_inst8 ( - .in0(Mux2xBits16_inst1_O[15]), - .in1(bit_const_1_None_out), - .out(magma_Bit_xor_inst8_out) -); -PEGEN_corebit_xor magma_Bit_xor_inst9 ( - .in0(Mux2xBits16_inst2_O[0]), - .in1(bit_const_1_None_out), - .out(magma_Bit_xor_inst9_out) -); -PEGEN_coreir_and #( - .width(16) -) magma_Bits_16_and_inst0 ( - .in0(a), - .in1(const_32768_16_out), - .out(magma_Bits_16_and_inst0_out) -); -PEGEN_coreir_and #( - .width(16) -) magma_Bits_16_and_inst1 ( - .in0(magma_Bits_16_shl_inst0_out), - .in1(const_32640_16_out), - .out(magma_Bits_16_and_inst1_out) -); -PEGEN_coreir_and #( - .width(16) -) magma_Bits_16_and_inst10 ( - .in0(a), - .in1(const_32768_16_out), - .out(magma_Bits_16_and_inst10_out) -); -PEGEN_coreir_and #( - .width(16) -) magma_Bits_16_and_inst11 ( - .in0(a), - .in1(const_127_16_out), - .out(magma_Bits_16_and_inst11_out) -); -PEGEN_coreir_and #( - .width(16) -) magma_Bits_16_and_inst12 ( - .in0(Mux2xBits16_inst6_O), - .in1(const_127_16_out), - .out(magma_Bits_16_and_inst12_out) -); -PEGEN_coreir_and #( - .width(16) -) magma_Bits_16_and_inst2 ( - .in0(a), - .in1(const_127_16_out), - .out(magma_Bits_16_and_inst2_out) -); -PEGEN_coreir_and #( - .width(16) -) magma_Bits_16_and_inst3 ( - .in0(a), - .in1(const_32768_16_out), - .out(magma_Bits_16_and_inst3_out) -); -PEGEN_coreir_and #( - .width(16) -) magma_Bits_16_and_inst4 ( - .in0(a), - .in1(const_127_16_out), - .out(magma_Bits_16_and_inst4_out) -); -PEGEN_coreir_and #( - .width(16) -) magma_Bits_16_and_inst5 ( - .in0(a), - .in1(const_32768_16_out), - .out(magma_Bits_16_and_inst5_out) -); -PEGEN_coreir_and #( - .width(16) -) magma_Bits_16_and_inst6 ( - .in0(b), - .in1(const_32768_16_out), - .out(magma_Bits_16_and_inst6_out) -); -PEGEN_coreir_and #( - .width(16) -) magma_Bits_16_and_inst7 ( - .in0(a), - .in1(const_127_16_out), - .out(magma_Bits_16_and_inst7_out) -); -PEGEN_coreir_and #( - .width(16) -) magma_Bits_16_and_inst8 ( - .in0(a), - .in1(const_32768_16_out), - .out(magma_Bits_16_and_inst8_out) -); -PEGEN_coreir_and #( - .width(16) -) magma_Bits_16_and_inst9 ( - .in0(a), - .in1(const_127_16_out), - .out(magma_Bits_16_and_inst9_out) -); -PEGEN_coreir_eq #( - .width(16) -) magma_Bits_16_eq_inst0 ( - .in0(magma_Bits_16_and_inst8_out), - .in1(const_32768_16_out), - .out(magma_Bits_16_eq_inst0_out) -); -PEGEN_coreir_eq #( - .width(16) -) magma_Bits_16_eq_inst1 ( - .in0(magma_Bits_16_and_inst10_out), - .in1(const_32768_16_out), - .out(magma_Bits_16_eq_inst1_out) -); -PEGEN_coreir_lshr #( - .width(16) -) magma_Bits_16_lshr_inst0 ( - .in0(Mux2xBits16_inst4_O), - .in1(const_8_16_out), - .out(magma_Bits_16_lshr_inst0_out) -); -wire [15:0] magma_Bits_16_lshr_inst1_in1; -assign magma_Bits_16_lshr_inst1_in1 = {bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,magma_SInt_9_neg_inst1_out}; -PEGEN_coreir_lshr #( - .width(16) -) magma_Bits_16_lshr_inst1 ( - .in0(magma_Bits_16_or_inst8_out), - .in1(magma_Bits_16_lshr_inst1_in1), - .out(magma_Bits_16_lshr_inst1_out) -); -PEGEN_coreir_or #( - .width(16) -) magma_Bits_16_or_inst0 ( - .in0(Mux2xBits16_inst3_O), - .in1(magma_Bits_16_and_inst1_out), - .out(magma_Bits_16_or_inst0_out) -); -PEGEN_coreir_or #( - .width(16) -) magma_Bits_16_or_inst1 ( - .in0(magma_Bits_16_or_inst0_out), - .in1(Mux2xBits16_inst5_O), - .out(magma_Bits_16_or_inst1_out) -); -PEGEN_coreir_or #( - .width(16) -) magma_Bits_16_or_inst2 ( - .in0(magma_Bits_16_and_inst3_out), - .in1(magma_Bits_16_shl_inst1_out), - .out(magma_Bits_16_or_inst2_out) -); -PEGEN_coreir_or #( - .width(16) -) magma_Bits_16_or_inst3 ( - .in0(magma_Bits_16_or_inst2_out), - .in1(magma_Bits_16_and_inst4_out), - .out(magma_Bits_16_or_inst3_out) -); -PEGEN_coreir_or #( - .width(16) -) magma_Bits_16_or_inst4 ( - .in0(magma_Bits_16_and_inst5_out), - .in1(magma_Bits_16_and_inst6_out), - .out(magma_Bits_16_or_inst4_out) -); -PEGEN_coreir_or #( - .width(16) -) magma_Bits_16_or_inst5 ( - .in0(magma_Bits_16_or_inst4_out), - .in1(magma_Bits_16_shl_inst2_out), - .out(magma_Bits_16_or_inst5_out) -); -PEGEN_coreir_or #( - .width(16) -) magma_Bits_16_or_inst6 ( - .in0(magma_Bits_16_or_inst5_out), - .in1(magma_Bits_16_and_inst7_out), - .out(magma_Bits_16_or_inst6_out) -); -PEGEN_coreir_or #( - .width(16) -) magma_Bits_16_or_inst7 ( - .in0(magma_Bits_16_and_inst9_out), - .in1(const_128_16_out), - .out(magma_Bits_16_or_inst7_out) -); -PEGEN_coreir_or #( - .width(16) -) magma_Bits_16_or_inst8 ( - .in0(magma_Bits_16_and_inst11_out), - .in1(const_128_16_out), - .out(magma_Bits_16_or_inst8_out) -); -PEGEN_coreir_shl #( - .width(16) -) magma_Bits_16_shl_inst0 ( - .in0(magma_SInt_16_add_inst0_out), - .in1(const_7_16_out), - .out(magma_Bits_16_shl_inst0_out) -); -wire [15:0] magma_Bits_16_shl_inst1_in0; -assign magma_Bits_16_shl_inst1_in0 = {bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,magma_UInt_8_add_inst0_out}; -PEGEN_coreir_shl #( - .width(16) -) magma_Bits_16_shl_inst1 ( - .in0(magma_Bits_16_shl_inst1_in0), - .in1(const_7_16_out), - .out(magma_Bits_16_shl_inst1_out) -); -wire [15:0] magma_Bits_16_shl_inst2_in0; -assign magma_Bits_16_shl_inst2_in0 = {bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,magma_UInt_8_add_inst1_out}; -PEGEN_coreir_shl #( - .width(16) -) magma_Bits_16_shl_inst2 ( - .in0(magma_Bits_16_shl_inst2_in0), - .in1(const_7_16_out), - .out(magma_Bits_16_shl_inst2_out) -); -wire [15:0] magma_Bits_16_shl_inst3_in1; -assign magma_Bits_16_shl_inst3_in1 = {bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,magma_SInt_9_sub_inst2_out}; -PEGEN_coreir_shl #( - .width(16) -) magma_Bits_16_shl_inst3 ( - .in0(magma_Bits_16_or_inst8_out), - .in1(magma_Bits_16_shl_inst3_in1), - .out(magma_Bits_16_shl_inst3_out) -); -PEGEN_coreir_eq #( - .width(1) -) magma_Bits_1_eq_inst0 ( - .in0(signed_), - .in1(const_1_1_out), - .out(magma_Bits_1_eq_inst0_out) -); -PEGEN_coreir_lshr #( - .width(23) -) magma_Bits_23_lshr_inst0 ( - .in0(Mux2xBits23_inst0_O), - .in1(const_7_23_out), - .out(magma_Bits_23_lshr_inst0_out) -); -wire [22:0] magma_Bits_23_shl_inst0_in0; -assign magma_Bits_23_shl_inst0_in0 = {bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,magma_Bits_16_or_inst7_out}; -wire [22:0] magma_Bits_23_shl_inst0_in1; -assign magma_Bits_23_shl_inst0_in1 = {bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,magma_SInt_9_sub_inst1_out}; -PEGEN_coreir_shl #( - .width(23) -) magma_Bits_23_shl_inst0 ( - .in0(magma_Bits_23_shl_inst0_in0), - .in1(magma_Bits_23_shl_inst0_in1), - .out(magma_Bits_23_shl_inst0_out) -); -PEGEN_coreir_eq #( - .width(3) -) magma_Bits_3_eq_inst0 ( - .in0(op), - .in1(const_3_3_out), - .out(magma_Bits_3_eq_inst0_out) -); -PEGEN_coreir_eq #( - .width(3) -) magma_Bits_3_eq_inst1 ( - .in0(op), - .in1(const_6_3_out), - .out(magma_Bits_3_eq_inst1_out) -); -PEGEN_coreir_eq #( - .width(3) -) magma_Bits_3_eq_inst2 ( - .in0(op), - .in1(const_0_3_out), - .out(magma_Bits_3_eq_inst2_out) -); -PEGEN_coreir_eq #( - .width(3) -) magma_Bits_3_eq_inst3 ( - .in0(op), - .in1(const_1_3_out), - .out(magma_Bits_3_eq_inst3_out) -); -PEGEN_coreir_eq #( - .width(3) -) magma_Bits_3_eq_inst4 ( - .in0(op), - .in1(const_2_3_out), - .out(magma_Bits_3_eq_inst4_out) -); -PEGEN_coreir_eq #( - .width(3) -) magma_Bits_3_eq_inst5 ( - .in0(op), - .in1(const_3_3_out), - .out(magma_Bits_3_eq_inst5_out) -); -PEGEN_coreir_eq #( - .width(3) -) magma_Bits_3_eq_inst6 ( - .in0(op), - .in1(const_4_3_out), - .out(magma_Bits_3_eq_inst6_out) -); -PEGEN_coreir_eq #( - .width(3) -) magma_Bits_3_eq_inst7 ( - .in0(op), - .in1(const_5_3_out), - .out(magma_Bits_3_eq_inst7_out) -); -PEGEN_coreir_add #( - .width(16) -) magma_SInt_16_add_inst0 ( - .in0(Mux2xSInt16_inst27_O), - .in1(const_127_16_out), - .out(magma_SInt_16_add_inst0_out) -); -PEGEN_coreir_and #( - .width(16) -) magma_SInt_16_and_inst0 ( - .in0(magma_SInt_16_shl_inst0_out), - .in1(Mux2xSInt16_inst24_O), - .out(magma_SInt_16_and_inst0_out) -); -PEGEN_coreir_neg #( - .width(16) -) magma_SInt_16_neg_inst0 ( - .in(a), - .out(magma_SInt_16_neg_inst0_out) -); -wire [15:0] magma_SInt_16_neg_inst1_in; -assign magma_SInt_16_neg_inst1_in = {magma_Bits_23_lshr_inst0_out[15],magma_Bits_23_lshr_inst0_out[14],magma_Bits_23_lshr_inst0_out[13],magma_Bits_23_lshr_inst0_out[12],magma_Bits_23_lshr_inst0_out[11],magma_Bits_23_lshr_inst0_out[10],magma_Bits_23_lshr_inst0_out[9],magma_Bits_23_lshr_inst0_out[8],magma_Bits_23_lshr_inst0_out[7],magma_Bits_23_lshr_inst0_out[6],magma_Bits_23_lshr_inst0_out[5],magma_Bits_23_lshr_inst0_out[4],magma_Bits_23_lshr_inst0_out[3],magma_Bits_23_lshr_inst0_out[2],magma_Bits_23_lshr_inst0_out[1],magma_Bits_23_lshr_inst0_out[0]}; -PEGEN_coreir_neg #( - .width(16) -) magma_SInt_16_neg_inst1 ( - .in(magma_SInt_16_neg_inst1_in), - .out(magma_SInt_16_neg_inst1_out) -); -PEGEN_coreir_neg #( - .width(16) -) magma_SInt_16_neg_inst2 ( - .in(magma_Bits_16_and_inst12_out), - .out(magma_SInt_16_neg_inst2_out) -); -PEGEN_coreir_sge #( - .width(16) -) magma_SInt_16_sge_inst0 ( - .in0(Mux2xSInt16_inst27_O), - .in1(const_0_16_out), - .out(magma_SInt_16_sge_inst0_out) -); -PEGEN_coreir_shl #( - .width(16) -) magma_SInt_16_shl_inst0 ( - .in0(Mux2xSInt16_inst25_O), - .in1(Mux2xSInt16_inst26_O), - .out(magma_SInt_16_shl_inst0_out) -); -PEGEN_coreir_sub #( - .width(16) -) magma_SInt_16_sub_inst0 ( - .in0(const_7_16_out), - .in1(Mux2xSInt16_inst7_O), - .out(magma_SInt_16_sub_inst0_out) -); -PEGEN_coreir_sub #( - .width(16) -) magma_SInt_16_sub_inst1 ( - .in0(const_15_16_out), - .in1(Mux2xSInt16_inst23_O), - .out(magma_SInt_16_sub_inst1_out) -); -PEGEN_coreir_neg #( - .width(9) -) magma_SInt_9_neg_inst0 ( - .in(magma_SInt_9_sub_inst0_out), - .out(magma_SInt_9_neg_inst0_out) -); -PEGEN_coreir_neg #( - .width(9) -) magma_SInt_9_neg_inst1 ( - .in(magma_SInt_9_sub_inst2_out), - .out(magma_SInt_9_neg_inst1_out) -); -PEGEN_coreir_slt #( - .width(9) -) magma_SInt_9_slt_inst0 ( - .in0(magma_SInt_9_sub_inst0_out), - .in1(const_0_9_out), - .out(magma_SInt_9_slt_inst0_out) -); -PEGEN_coreir_slt #( - .width(9) -) magma_SInt_9_slt_inst1 ( - .in0(magma_SInt_9_sub_inst1_out), - .in1(const_0_9_out), - .out(magma_SInt_9_slt_inst1_out) -); -PEGEN_coreir_slt #( - .width(9) -) magma_SInt_9_slt_inst2 ( - .in0(magma_SInt_9_sub_inst2_out), - .in1(const_0_9_out), - .out(magma_SInt_9_slt_inst2_out) -); -wire [8:0] magma_SInt_9_sub_inst0_in0; -assign magma_SInt_9_sub_inst0_in0 = {bit_const_0_None_out,a[14],a[13],a[12],a[11],a[10],a[9],a[8],a[7]}; -PEGEN_coreir_sub #( - .width(9) -) magma_SInt_9_sub_inst0 ( - .in0(magma_SInt_9_sub_inst0_in0), - .in1(const_127_9_out), - .out(magma_SInt_9_sub_inst0_out) -); -wire [8:0] magma_SInt_9_sub_inst1_in0; -assign magma_SInt_9_sub_inst1_in0 = {bit_const_0_None_out,a[14],a[13],a[12],a[11],a[10],a[9],a[8],a[7]}; -PEGEN_coreir_sub #( - .width(9) -) magma_SInt_9_sub_inst1 ( - .in0(magma_SInt_9_sub_inst1_in0), - .in1(const_127_9_out), - .out(magma_SInt_9_sub_inst1_out) -); -wire [8:0] magma_SInt_9_sub_inst2_in0; -assign magma_SInt_9_sub_inst2_in0 = {bit_const_0_None_out,a[14],a[13],a[12],a[11],a[10],a[9],a[8],a[7]}; -PEGEN_coreir_sub #( - .width(9) -) magma_SInt_9_sub_inst2 ( - .in0(magma_SInt_9_sub_inst2_in0), - .in1(const_127_9_out), - .out(magma_SInt_9_sub_inst2_out) -); -wire [7:0] magma_UInt_8_add_inst0_in0; -assign magma_UInt_8_add_inst0_in0 = {a[14],a[13],a[12],a[11],a[10],a[9],a[8],a[7]}; -wire [7:0] magma_UInt_8_add_inst0_in1; -assign magma_UInt_8_add_inst0_in1 = {b[7],b[6],b[5],b[4],b[3],b[2],b[1],b[0]}; -PEGEN_coreir_add #( - .width(8) -) magma_UInt_8_add_inst0 ( - .in0(magma_UInt_8_add_inst0_in0), - .in1(magma_UInt_8_add_inst0_in1), - .out(magma_UInt_8_add_inst0_out) -); -PEGEN_coreir_add #( - .width(8) -) magma_UInt_8_add_inst1 ( - .in0(magma_UInt_8_sub_inst0_out), - .in1(const_127_8_out), - .out(magma_UInt_8_add_inst1_out) -); -wire [7:0] magma_UInt_8_sub_inst0_in0; -assign magma_UInt_8_sub_inst0_in0 = {a[14],a[13],a[12],a[11],a[10],a[9],a[8],a[7]}; -wire [7:0] magma_UInt_8_sub_inst0_in1; -assign magma_UInt_8_sub_inst0_in1 = {b[14],b[13],b[12],b[11],b[10],b[9],b[8],b[7]}; -PEGEN_coreir_sub #( - .width(8) -) magma_UInt_8_sub_inst0 ( - .in0(magma_UInt_8_sub_inst0_in0), - .in1(magma_UInt_8_sub_inst0_in1), - .out(magma_UInt_8_sub_inst0_out) -); -wire [7:0] magma_UInt_8_ugt_inst0_in0; -assign magma_UInt_8_ugt_inst0_in0 = {a[14],a[13],a[12],a[11],a[10],a[9],a[8],a[7]}; -PEGEN_coreir_ugt #( - .width(8) -) magma_UInt_8_ugt_inst0 ( - .in0(magma_UInt_8_ugt_inst0_in0), - .in1(const_142_8_out), - .out(magma_UInt_8_ugt_inst0_out) -); -wire [8:0] magma_UInt_9_add_inst0_in0; -assign magma_UInt_9_add_inst0_in0 = {bit_const_0_None_out,a[14],a[13],a[12],a[11],a[10],a[9],a[8],a[7]}; -wire [8:0] magma_UInt_9_add_inst0_in1; -assign magma_UInt_9_add_inst0_in1 = {b[8],b[7],b[6],b[5],b[4],b[3],b[2],b[1],b[0]}; -PEGEN_coreir_add #( - .width(9) -) magma_UInt_9_add_inst0 ( - .in0(magma_UInt_9_add_inst0_in0), - .in1(magma_UInt_9_add_inst0_in1), - .out(magma_UInt_9_add_inst0_out) -); -PEGEN_coreir_ugt #( - .width(9) -) magma_UInt_9_ugt_inst0 ( - .in0(magma_UInt_9_add_inst0_out), - .in1(const_255_9_out), - .out(magma_UInt_9_ugt_inst0_out) -); -assign res = Mux2xBits16_inst19_O; -assign res_p = Mux2xBit_inst10_O; -assign V = Mux2xBit_inst9_O; -endmodule - -module PEGEN_Cond ( - input [4:0] code, - input alu, - input lut, - input Z, - input N, - input C, - input V, - output O, - input CLK, - input ASYNCRESET -); -wire Mux2xBit_inst0_O; -wire Mux2xBit_inst1_O; -wire Mux2xBit_inst10_O; -wire Mux2xBit_inst11_O; -wire Mux2xBit_inst12_O; -wire Mux2xBit_inst13_O; -wire Mux2xBit_inst14_O; -wire Mux2xBit_inst15_O; -wire Mux2xBit_inst16_O; -wire Mux2xBit_inst17_O; -wire Mux2xBit_inst18_O; -wire Mux2xBit_inst2_O; -wire Mux2xBit_inst3_O; -wire Mux2xBit_inst4_O; -wire Mux2xBit_inst5_O; -wire Mux2xBit_inst6_O; -wire Mux2xBit_inst7_O; -wire Mux2xBit_inst8_O; -wire Mux2xBit_inst9_O; -wire [4:0] const_0_5_out; -wire [4:0] const_10_5_out; -wire [4:0] const_11_5_out; -wire [4:0] const_12_5_out; -wire [4:0] const_13_5_out; -wire [4:0] const_14_5_out; -wire [4:0] const_15_5_out; -wire [4:0] const_16_5_out; -wire [4:0] const_17_5_out; -wire [4:0] const_18_5_out; -wire [4:0] const_1_5_out; -wire [4:0] const_2_5_out; -wire [4:0] const_3_5_out; -wire [4:0] const_4_5_out; -wire [4:0] const_5_5_out; -wire [4:0] const_6_5_out; -wire [4:0] const_7_5_out; -wire [4:0] const_8_5_out; -wire [4:0] const_9_5_out; -wire magma_Bit_and_inst0_out; -wire magma_Bit_and_inst1_out; -wire magma_Bit_and_inst2_out; -wire magma_Bit_and_inst3_out; -wire magma_Bit_not_inst0_out; -wire magma_Bit_not_inst1_out; -wire magma_Bit_not_inst10_out; -wire magma_Bit_not_inst11_out; -wire magma_Bit_not_inst12_out; -wire magma_Bit_not_inst2_out; -wire magma_Bit_not_inst3_out; -wire magma_Bit_not_inst4_out; -wire magma_Bit_not_inst5_out; -wire magma_Bit_not_inst6_out; -wire magma_Bit_not_inst7_out; -wire magma_Bit_not_inst8_out; -wire magma_Bit_not_inst9_out; -wire magma_Bit_or_inst0_out; -wire magma_Bit_or_inst1_out; -wire magma_Bit_or_inst2_out; -wire magma_Bit_or_inst3_out; -wire magma_Bit_or_inst4_out; -wire magma_Bit_or_inst5_out; -wire magma_Bit_xor_inst0_out; -wire magma_Bit_xor_inst1_out; -wire magma_Bit_xor_inst2_out; -wire magma_Bit_xor_inst3_out; -wire magma_Bits_5_eq_inst0_out; -wire magma_Bits_5_eq_inst1_out; -wire magma_Bits_5_eq_inst10_out; -wire magma_Bits_5_eq_inst11_out; -wire magma_Bits_5_eq_inst12_out; -wire magma_Bits_5_eq_inst13_out; -wire magma_Bits_5_eq_inst14_out; -wire magma_Bits_5_eq_inst15_out; -wire magma_Bits_5_eq_inst16_out; -wire magma_Bits_5_eq_inst17_out; -wire magma_Bits_5_eq_inst18_out; -wire magma_Bits_5_eq_inst19_out; -wire magma_Bits_5_eq_inst2_out; -wire magma_Bits_5_eq_inst20_out; -wire magma_Bits_5_eq_inst3_out; -wire magma_Bits_5_eq_inst4_out; -wire magma_Bits_5_eq_inst5_out; -wire magma_Bits_5_eq_inst6_out; -wire magma_Bits_5_eq_inst7_out; -wire magma_Bits_5_eq_inst8_out; -wire magma_Bits_5_eq_inst9_out; -PEGEN_Mux2xBit Mux2xBit_inst0 ( - .I0(magma_Bit_and_inst3_out), - .I1(magma_Bit_or_inst5_out), - .S(magma_Bits_5_eq_inst20_out), - .O(Mux2xBit_inst0_O) -); -PEGEN_Mux2xBit Mux2xBit_inst1 ( - .I0(Mux2xBit_inst0_O), - .I1(magma_Bit_and_inst2_out), - .S(magma_Bits_5_eq_inst19_out), - .O(Mux2xBit_inst1_O) -); -PEGEN_Mux2xBit Mux2xBit_inst10 ( - .I0(Mux2xBit_inst9_O), - .I1(magma_Bit_and_inst0_out), - .S(magma_Bits_5_eq_inst10_out), - .O(Mux2xBit_inst10_O) -); -PEGEN_Mux2xBit Mux2xBit_inst11 ( - .I0(Mux2xBit_inst10_O), - .I1(magma_Bit_not_inst3_out), - .S(magma_Bits_5_eq_inst9_out), - .O(Mux2xBit_inst11_O) -); -PEGEN_Mux2xBit Mux2xBit_inst12 ( - .I0(Mux2xBit_inst11_O), - .I1(V), - .S(magma_Bits_5_eq_inst8_out), - .O(Mux2xBit_inst12_O) -); -PEGEN_Mux2xBit Mux2xBit_inst13 ( - .I0(Mux2xBit_inst12_O), - .I1(magma_Bit_not_inst2_out), - .S(magma_Bits_5_eq_inst7_out), - .O(Mux2xBit_inst13_O) -); -PEGEN_Mux2xBit Mux2xBit_inst14 ( - .I0(Mux2xBit_inst13_O), - .I1(N), - .S(magma_Bits_5_eq_inst6_out), - .O(Mux2xBit_inst14_O) -); -PEGEN_Mux2xBit Mux2xBit_inst15 ( - .I0(Mux2xBit_inst14_O), - .I1(magma_Bit_not_inst1_out), - .S(magma_Bit_or_inst1_out), - .O(Mux2xBit_inst15_O) -); -PEGEN_Mux2xBit Mux2xBit_inst16 ( - .I0(Mux2xBit_inst15_O), - .I1(C), - .S(magma_Bit_or_inst0_out), - .O(Mux2xBit_inst16_O) -); -PEGEN_Mux2xBit Mux2xBit_inst17 ( - .I0(Mux2xBit_inst16_O), - .I1(magma_Bit_not_inst0_out), - .S(magma_Bits_5_eq_inst1_out), - .O(Mux2xBit_inst17_O) -); -PEGEN_Mux2xBit Mux2xBit_inst18 ( - .I0(Mux2xBit_inst17_O), - .I1(Z), - .S(magma_Bits_5_eq_inst0_out), - .O(Mux2xBit_inst18_O) -); -PEGEN_Mux2xBit Mux2xBit_inst2 ( - .I0(Mux2xBit_inst1_O), - .I1(magma_Bit_or_inst4_out), - .S(magma_Bits_5_eq_inst18_out), - .O(Mux2xBit_inst2_O) -); -PEGEN_Mux2xBit Mux2xBit_inst3 ( - .I0(Mux2xBit_inst2_O), - .I1(lut), - .S(magma_Bits_5_eq_inst17_out), - .O(Mux2xBit_inst3_O) -); -PEGEN_Mux2xBit Mux2xBit_inst4 ( - .I0(Mux2xBit_inst3_O), - .I1(alu), - .S(magma_Bits_5_eq_inst16_out), - .O(Mux2xBit_inst4_O) -); -PEGEN_Mux2xBit Mux2xBit_inst5 ( - .I0(Mux2xBit_inst4_O), - .I1(magma_Bit_or_inst3_out), - .S(magma_Bits_5_eq_inst15_out), - .O(Mux2xBit_inst5_O) -); -PEGEN_Mux2xBit Mux2xBit_inst6 ( - .I0(Mux2xBit_inst5_O), - .I1(magma_Bit_and_inst1_out), - .S(magma_Bits_5_eq_inst14_out), - .O(Mux2xBit_inst6_O) -); -PEGEN_Mux2xBit Mux2xBit_inst7 ( - .I0(Mux2xBit_inst6_O), - .I1(magma_Bit_xor_inst1_out), - .S(magma_Bits_5_eq_inst13_out), - .O(Mux2xBit_inst7_O) -); -PEGEN_Mux2xBit Mux2xBit_inst8 ( - .I0(Mux2xBit_inst7_O), - .I1(magma_Bit_not_inst6_out), - .S(magma_Bits_5_eq_inst12_out), - .O(Mux2xBit_inst8_O) -); -PEGEN_Mux2xBit Mux2xBit_inst9 ( - .I0(Mux2xBit_inst8_O), - .I1(magma_Bit_or_inst2_out), - .S(magma_Bits_5_eq_inst11_out), - .O(Mux2xBit_inst9_O) -); -PEGEN_coreir_const #( - .value(5'h00), - .width(5) -) const_0_5 ( - .out(const_0_5_out) -); -PEGEN_coreir_const #( - .value(5'h0a), - .width(5) -) const_10_5 ( - .out(const_10_5_out) -); -PEGEN_coreir_const #( - .value(5'h0b), - .width(5) -) const_11_5 ( - .out(const_11_5_out) -); -PEGEN_coreir_const #( - .value(5'h0c), - .width(5) -) const_12_5 ( - .out(const_12_5_out) -); -PEGEN_coreir_const #( - .value(5'h0d), - .width(5) -) const_13_5 ( - .out(const_13_5_out) -); -PEGEN_coreir_const #( - .value(5'h0e), - .width(5) -) const_14_5 ( - .out(const_14_5_out) -); -PEGEN_coreir_const #( - .value(5'h0f), - .width(5) -) const_15_5 ( - .out(const_15_5_out) -); -PEGEN_coreir_const #( - .value(5'h10), - .width(5) -) const_16_5 ( - .out(const_16_5_out) -); -PEGEN_coreir_const #( - .value(5'h11), - .width(5) -) const_17_5 ( - .out(const_17_5_out) -); -PEGEN_coreir_const #( - .value(5'h12), - .width(5) -) const_18_5 ( - .out(const_18_5_out) -); -PEGEN_coreir_const #( - .value(5'h01), - .width(5) -) const_1_5 ( - .out(const_1_5_out) -); -PEGEN_coreir_const #( - .value(5'h02), - .width(5) -) const_2_5 ( - .out(const_2_5_out) -); -PEGEN_coreir_const #( - .value(5'h03), - .width(5) -) const_3_5 ( - .out(const_3_5_out) -); -PEGEN_coreir_const #( - .value(5'h04), - .width(5) -) const_4_5 ( - .out(const_4_5_out) -); -PEGEN_coreir_const #( - .value(5'h05), - .width(5) -) const_5_5 ( - .out(const_5_5_out) -); -PEGEN_coreir_const #( - .value(5'h06), - .width(5) -) const_6_5 ( - .out(const_6_5_out) -); -PEGEN_coreir_const #( - .value(5'h07), - .width(5) -) const_7_5 ( - .out(const_7_5_out) -); -PEGEN_coreir_const #( - .value(5'h08), - .width(5) -) const_8_5 ( - .out(const_8_5_out) -); -PEGEN_coreir_const #( - .value(5'h09), - .width(5) -) const_9_5 ( - .out(const_9_5_out) -); -PEGEN_corebit_and magma_Bit_and_inst0 ( - .in0(C), - .in1(magma_Bit_not_inst4_out), - .out(magma_Bit_and_inst0_out) -); -PEGEN_corebit_and magma_Bit_and_inst1 ( - .in0(magma_Bit_not_inst7_out), - .in1(magma_Bit_not_inst8_out), - .out(magma_Bit_and_inst1_out) -); -PEGEN_corebit_and magma_Bit_and_inst2 ( - .in0(magma_Bit_not_inst10_out), - .in1(magma_Bit_not_inst11_out), - .out(magma_Bit_and_inst2_out) -); -PEGEN_corebit_and magma_Bit_and_inst3 ( - .in0(N), - .in1(magma_Bit_not_inst12_out), - .out(magma_Bit_and_inst3_out) -); -PEGEN_corebit_not magma_Bit_not_inst0 ( - .in(Z), - .out(magma_Bit_not_inst0_out) -); -PEGEN_corebit_not magma_Bit_not_inst1 ( - .in(C), - .out(magma_Bit_not_inst1_out) -); -PEGEN_corebit_not magma_Bit_not_inst10 ( - .in(N), - .out(magma_Bit_not_inst10_out) -); -PEGEN_corebit_not magma_Bit_not_inst11 ( - .in(Z), - .out(magma_Bit_not_inst11_out) -); -PEGEN_corebit_not magma_Bit_not_inst12 ( - .in(Z), - .out(magma_Bit_not_inst12_out) -); -PEGEN_corebit_not magma_Bit_not_inst2 ( - .in(N), - .out(magma_Bit_not_inst2_out) -); -PEGEN_corebit_not magma_Bit_not_inst3 ( - .in(V), - .out(magma_Bit_not_inst3_out) -); -PEGEN_corebit_not magma_Bit_not_inst4 ( - .in(Z), - .out(magma_Bit_not_inst4_out) -); -PEGEN_corebit_not magma_Bit_not_inst5 ( - .in(C), - .out(magma_Bit_not_inst5_out) -); -PEGEN_corebit_not magma_Bit_not_inst6 ( - .in(magma_Bit_xor_inst0_out), - .out(magma_Bit_not_inst6_out) -); -PEGEN_corebit_not magma_Bit_not_inst7 ( - .in(Z), - .out(magma_Bit_not_inst7_out) -); -PEGEN_corebit_not magma_Bit_not_inst8 ( - .in(magma_Bit_xor_inst2_out), - .out(magma_Bit_not_inst8_out) -); -PEGEN_corebit_not magma_Bit_not_inst9 ( - .in(N), - .out(magma_Bit_not_inst9_out) -); -PEGEN_corebit_or magma_Bit_or_inst0 ( - .in0(magma_Bits_5_eq_inst2_out), - .in1(magma_Bits_5_eq_inst3_out), - .out(magma_Bit_or_inst0_out) -); -PEGEN_corebit_or magma_Bit_or_inst1 ( - .in0(magma_Bits_5_eq_inst4_out), - .in1(magma_Bits_5_eq_inst5_out), - .out(magma_Bit_or_inst1_out) -); -PEGEN_corebit_or magma_Bit_or_inst2 ( - .in0(magma_Bit_not_inst5_out), - .in1(Z), - .out(magma_Bit_or_inst2_out) -); -PEGEN_corebit_or magma_Bit_or_inst3 ( - .in0(Z), - .in1(magma_Bit_xor_inst3_out), - .out(magma_Bit_or_inst3_out) -); -PEGEN_corebit_or magma_Bit_or_inst4 ( - .in0(magma_Bit_not_inst9_out), - .in1(Z), - .out(magma_Bit_or_inst4_out) -); -PEGEN_corebit_or magma_Bit_or_inst5 ( - .in0(N), - .in1(Z), - .out(magma_Bit_or_inst5_out) -); -PEGEN_corebit_xor magma_Bit_xor_inst0 ( - .in0(N), - .in1(V), - .out(magma_Bit_xor_inst0_out) -); -PEGEN_corebit_xor magma_Bit_xor_inst1 ( - .in0(N), - .in1(V), - .out(magma_Bit_xor_inst1_out) -); -PEGEN_corebit_xor magma_Bit_xor_inst2 ( - .in0(N), - .in1(V), - .out(magma_Bit_xor_inst2_out) -); -PEGEN_corebit_xor magma_Bit_xor_inst3 ( - .in0(N), - .in1(V), - .out(magma_Bit_xor_inst3_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst0 ( - .in0(code), - .in1(const_0_5_out), - .out(magma_Bits_5_eq_inst0_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst1 ( - .in0(code), - .in1(const_1_5_out), - .out(magma_Bits_5_eq_inst1_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst10 ( - .in0(code), - .in1(const_8_5_out), - .out(magma_Bits_5_eq_inst10_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst11 ( - .in0(code), - .in1(const_9_5_out), - .out(magma_Bits_5_eq_inst11_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst12 ( - .in0(code), - .in1(const_10_5_out), - .out(magma_Bits_5_eq_inst12_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst13 ( - .in0(code), - .in1(const_11_5_out), - .out(magma_Bits_5_eq_inst13_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst14 ( - .in0(code), - .in1(const_12_5_out), - .out(magma_Bits_5_eq_inst14_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst15 ( - .in0(code), - .in1(const_13_5_out), - .out(magma_Bits_5_eq_inst15_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst16 ( - .in0(code), - .in1(const_15_5_out), - .out(magma_Bits_5_eq_inst16_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst17 ( - .in0(code), - .in1(const_14_5_out), - .out(magma_Bits_5_eq_inst17_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst18 ( - .in0(code), - .in1(const_16_5_out), - .out(magma_Bits_5_eq_inst18_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst19 ( - .in0(code), - .in1(const_17_5_out), - .out(magma_Bits_5_eq_inst19_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst2 ( - .in0(code), - .in1(const_2_5_out), - .out(magma_Bits_5_eq_inst2_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst20 ( - .in0(code), - .in1(const_18_5_out), - .out(magma_Bits_5_eq_inst20_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst3 ( - .in0(code), - .in1(const_2_5_out), - .out(magma_Bits_5_eq_inst3_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst4 ( - .in0(code), - .in1(const_3_5_out), - .out(magma_Bits_5_eq_inst4_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst5 ( - .in0(code), - .in1(const_3_5_out), - .out(magma_Bits_5_eq_inst5_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst6 ( - .in0(code), - .in1(const_4_5_out), - .out(magma_Bits_5_eq_inst6_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst7 ( - .in0(code), - .in1(const_5_5_out), - .out(magma_Bits_5_eq_inst7_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst8 ( - .in0(code), - .in1(const_6_5_out), - .out(magma_Bits_5_eq_inst8_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst9 ( - .in0(code), - .in1(const_7_5_out), - .out(magma_Bits_5_eq_inst9_out) -); -assign O = Mux2xBit_inst18_O; -endmodule - -module PEGEN_ALU ( - input [4:0] alu, - input [0:0] signed_, - input [15:0] a, - input [15:0] b, - input [15:0] c, - input d, - output [15:0] res, - output res_p, - output Z, - output N, - output C, - output V, - input CLK, - input ASYNCRESET -); -wire Mux2xBit_inst0_O; -wire Mux2xBit_inst1_O; -wire Mux2xBit_inst10_O; -wire Mux2xBit_inst11_O; -wire Mux2xBit_inst12_O; -wire Mux2xBit_inst13_O; -wire Mux2xBit_inst14_O; -wire Mux2xBit_inst15_O; -wire Mux2xBit_inst16_O; -wire Mux2xBit_inst17_O; -wire Mux2xBit_inst18_O; -wire Mux2xBit_inst19_O; -wire Mux2xBit_inst2_O; -wire Mux2xBit_inst20_O; -wire Mux2xBit_inst21_O; -wire Mux2xBit_inst22_O; -wire Mux2xBit_inst23_O; -wire Mux2xBit_inst3_O; -wire Mux2xBit_inst4_O; -wire Mux2xBit_inst5_O; -wire Mux2xBit_inst6_O; -wire Mux2xBit_inst7_O; -wire Mux2xBit_inst8_O; -wire Mux2xBit_inst9_O; -wire [15:0] Mux2xBits16_inst0_O; -wire [15:0] Mux2xBits16_inst1_O; -wire [15:0] Mux2xBits16_inst10_O; -wire [15:0] Mux2xBits16_inst11_O; -wire [15:0] Mux2xBits16_inst12_O; -wire [15:0] Mux2xBits16_inst13_O; -wire [15:0] Mux2xBits16_inst14_O; -wire [15:0] Mux2xBits16_inst15_O; -wire [15:0] Mux2xBits16_inst16_O; -wire [15:0] Mux2xBits16_inst17_O; -wire [15:0] Mux2xBits16_inst18_O; -wire [15:0] Mux2xBits16_inst19_O; -wire [15:0] Mux2xBits16_inst2_O; -wire [15:0] Mux2xBits16_inst20_O; -wire [15:0] Mux2xBits16_inst21_O; -wire [15:0] Mux2xBits16_inst3_O; -wire [15:0] Mux2xBits16_inst4_O; -wire [15:0] Mux2xBits16_inst5_O; -wire [15:0] Mux2xBits16_inst6_O; -wire [15:0] Mux2xBits16_inst7_O; -wire [15:0] Mux2xBits16_inst8_O; -wire [15:0] Mux2xBits16_inst9_O; -wire [15:0] Mux2xUInt16_inst0_O; -wire [31:0] Mux2xUInt32_inst0_O; -wire [31:0] Mux2xUInt32_inst1_O; -wire bit_const_0_None_out; -wire bit_const_1_None_out; -wire [15:0] const_0_16_out; -wire [4:0] const_0_5_out; -wire [4:0] const_10_5_out; -wire [4:0] const_11_5_out; -wire [4:0] const_12_5_out; -wire [4:0] const_13_5_out; -wire [4:0] const_14_5_out; -wire [4:0] const_15_5_out; -wire [4:0] const_16_5_out; -wire [4:0] const_17_5_out; -wire [4:0] const_18_5_out; -wire [4:0] const_19_5_out; -wire [0:0] const_1_1_out; -wire [4:0] const_1_5_out; -wire [4:0] const_2_5_out; -wire [4:0] const_3_5_out; -wire [4:0] const_4_5_out; -wire [4:0] const_5_5_out; -wire [4:0] const_6_5_out; -wire [4:0] const_7_5_out; -wire [4:0] const_8_5_out; -wire [4:0] const_9_5_out; -wire magma_Bit_and_inst0_out; -wire magma_Bit_and_inst1_out; -wire magma_Bit_and_inst2_out; -wire magma_Bit_and_inst3_out; -wire magma_Bit_not_inst0_out; -wire magma_Bit_not_inst1_out; -wire magma_Bit_not_inst2_out; -wire magma_Bit_or_inst0_out; -wire magma_Bit_or_inst1_out; -wire magma_Bit_or_inst10_out; -wire magma_Bit_or_inst11_out; -wire magma_Bit_or_inst12_out; -wire magma_Bit_or_inst13_out; -wire magma_Bit_or_inst2_out; -wire magma_Bit_or_inst3_out; -wire magma_Bit_or_inst4_out; -wire magma_Bit_or_inst5_out; -wire magma_Bit_or_inst6_out; -wire magma_Bit_or_inst7_out; -wire magma_Bit_or_inst8_out; -wire magma_Bit_or_inst9_out; -wire [15:0] magma_Bits_16_and_inst0_out; -wire [15:0] magma_Bits_16_not_inst0_out; -wire [15:0] magma_Bits_16_not_inst1_out; -wire [15:0] magma_Bits_16_or_inst0_out; -wire [15:0] magma_Bits_16_shl_inst0_out; -wire [15:0] magma_Bits_16_xor_inst0_out; -wire magma_Bits_1_eq_inst0_out; -wire magma_Bits_1_eq_inst1_out; -wire magma_Bits_1_eq_inst2_out; -wire magma_Bits_1_eq_inst3_out; -wire magma_Bits_5_eq_inst0_out; -wire magma_Bits_5_eq_inst1_out; -wire magma_Bits_5_eq_inst10_out; -wire magma_Bits_5_eq_inst11_out; -wire magma_Bits_5_eq_inst12_out; -wire magma_Bits_5_eq_inst13_out; -wire magma_Bits_5_eq_inst14_out; -wire magma_Bits_5_eq_inst15_out; -wire magma_Bits_5_eq_inst16_out; -wire magma_Bits_5_eq_inst17_out; -wire magma_Bits_5_eq_inst18_out; -wire magma_Bits_5_eq_inst19_out; -wire magma_Bits_5_eq_inst2_out; -wire magma_Bits_5_eq_inst20_out; -wire magma_Bits_5_eq_inst21_out; -wire magma_Bits_5_eq_inst22_out; -wire magma_Bits_5_eq_inst23_out; -wire magma_Bits_5_eq_inst24_out; -wire magma_Bits_5_eq_inst25_out; -wire magma_Bits_5_eq_inst26_out; -wire magma_Bits_5_eq_inst27_out; -wire magma_Bits_5_eq_inst28_out; -wire magma_Bits_5_eq_inst29_out; -wire magma_Bits_5_eq_inst3_out; -wire magma_Bits_5_eq_inst30_out; -wire magma_Bits_5_eq_inst4_out; -wire magma_Bits_5_eq_inst5_out; -wire magma_Bits_5_eq_inst6_out; -wire magma_Bits_5_eq_inst7_out; -wire magma_Bits_5_eq_inst8_out; -wire magma_Bits_5_eq_inst9_out; -wire [15:0] magma_SInt_16_ashr_inst0_out; -wire magma_SInt_16_eq_inst0_out; -wire [15:0] magma_SInt_16_neg_inst0_out; -wire magma_SInt_16_sge_inst0_out; -wire magma_SInt_16_sle_inst0_out; -wire magma_SInt_16_sle_inst1_out; -wire [15:0] magma_UInt_16_lshr_inst0_out; -wire magma_UInt_16_uge_inst0_out; -wire magma_UInt_16_ule_inst0_out; -wire [16:0] magma_UInt_17_add_inst0_out; -wire [16:0] magma_UInt_17_add_inst1_out; -wire [16:0] magma_UInt_17_add_inst2_out; -wire [16:0] magma_UInt_17_add_inst3_out; -wire [31:0] magma_UInt_32_mul_inst0_out; -PEGEN_Mux2xBit Mux2xBit_inst0 ( - .I0(magma_UInt_16_ule_inst0_out), - .I1(magma_SInt_16_sle_inst0_out), - .S(magma_Bits_1_eq_inst1_out), - .O(Mux2xBit_inst0_O) -); -PEGEN_Mux2xBit Mux2xBit_inst1 ( - .I0(magma_UInt_16_uge_inst0_out), - .I1(magma_SInt_16_sge_inst0_out), - .S(magma_Bits_1_eq_inst2_out), - .O(Mux2xBit_inst1_O) -); -PEGEN_Mux2xBit Mux2xBit_inst10 ( - .I0(Mux2xBit_inst9_O), - .I1(bit_const_0_None_out), - .S(magma_Bits_5_eq_inst18_out), - .O(Mux2xBit_inst10_O) -); -PEGEN_Mux2xBit Mux2xBit_inst11 ( - .I0(Mux2xBit_inst10_O), - .I1(a[15]), - .S(magma_Bits_5_eq_inst17_out), - .O(Mux2xBit_inst11_O) -); -PEGEN_Mux2xBit Mux2xBit_inst12 ( - .I0(bit_const_0_None_out), - .I1(bit_const_0_None_out), - .S(magma_Bits_5_eq_inst16_out), - .O(Mux2xBit_inst12_O) -); -PEGEN_Mux2xBit Mux2xBit_inst13 ( - .I0(bit_const_0_None_out), - .I1(bit_const_0_None_out), - .S(magma_Bits_5_eq_inst16_out), - .O(Mux2xBit_inst13_O) -); -PEGEN_Mux2xBit Mux2xBit_inst14 ( - .I0(Mux2xBit_inst11_O), - .I1(bit_const_0_None_out), - .S(magma_Bits_5_eq_inst16_out), - .O(Mux2xBit_inst14_O) -); -PEGEN_Mux2xBit Mux2xBit_inst15 ( - .I0(Mux2xBit_inst12_O), - .I1(bit_const_0_None_out), - .S(magma_Bits_5_eq_inst15_out), - .O(Mux2xBit_inst15_O) -); -PEGEN_Mux2xBit Mux2xBit_inst16 ( - .I0(Mux2xBit_inst13_O), - .I1(bit_const_0_None_out), - .S(magma_Bits_5_eq_inst15_out), - .O(Mux2xBit_inst16_O) -); -PEGEN_Mux2xBit Mux2xBit_inst17 ( - .I0(Mux2xBit_inst14_O), - .I1(bit_const_0_None_out), - .S(magma_Bits_5_eq_inst15_out), - .O(Mux2xBit_inst17_O) -); -PEGEN_Mux2xBit Mux2xBit_inst18 ( - .I0(Mux2xBit_inst15_O), - .I1(bit_const_0_None_out), - .S(magma_Bits_5_eq_inst14_out), - .O(Mux2xBit_inst18_O) -); -PEGEN_Mux2xBit Mux2xBit_inst19 ( - .I0(Mux2xBit_inst16_O), - .I1(bit_const_0_None_out), - .S(magma_Bits_5_eq_inst14_out), - .O(Mux2xBit_inst19_O) -); -PEGEN_Mux2xBit Mux2xBit_inst2 ( - .I0(bit_const_0_None_out), - .I1(bit_const_1_None_out), - .S(magma_Bit_or_inst6_out), - .O(Mux2xBit_inst2_O) -); -PEGEN_Mux2xBit Mux2xBit_inst20 ( - .I0(Mux2xBit_inst17_O), - .I1(bit_const_0_None_out), - .S(magma_Bits_5_eq_inst14_out), - .O(Mux2xBit_inst20_O) -); -PEGEN_Mux2xBit Mux2xBit_inst21 ( - .I0(Mux2xBit_inst18_O), - .I1(magma_UInt_17_add_inst1_out[16]), - .S(magma_Bit_or_inst7_out), - .O(Mux2xBit_inst21_O) -); -PEGEN_Mux2xBit Mux2xBit_inst22 ( - .I0(Mux2xBit_inst19_O), - .I1(magma_Bit_or_inst8_out), - .S(magma_Bit_or_inst7_out), - .O(Mux2xBit_inst22_O) -); -PEGEN_Mux2xBit Mux2xBit_inst23 ( - .I0(Mux2xBit_inst20_O), - .I1(magma_UInt_17_add_inst1_out[16]), - .S(magma_Bit_or_inst7_out), - .O(Mux2xBit_inst23_O) -); -PEGEN_Mux2xBit Mux2xBit_inst3 ( - .I0(bit_const_0_None_out), - .I1(bit_const_0_None_out), - .S(magma_Bits_5_eq_inst30_out), - .O(Mux2xBit_inst3_O) -); -PEGEN_Mux2xBit Mux2xBit_inst4 ( - .I0(Mux2xBit_inst3_O), - .I1(bit_const_0_None_out), - .S(magma_Bit_or_inst13_out), - .O(Mux2xBit_inst4_O) -); -PEGEN_Mux2xBit Mux2xBit_inst5 ( - .I0(Mux2xBit_inst4_O), - .I1(bit_const_0_None_out), - .S(magma_Bits_5_eq_inst23_out), - .O(Mux2xBit_inst5_O) -); -PEGEN_Mux2xBit Mux2xBit_inst6 ( - .I0(Mux2xBit_inst5_O), - .I1(bit_const_0_None_out), - .S(magma_Bits_5_eq_inst22_out), - .O(Mux2xBit_inst6_O) -); -PEGEN_Mux2xBit Mux2xBit_inst7 ( - .I0(Mux2xBit_inst6_O), - .I1(bit_const_0_None_out), - .S(magma_Bits_5_eq_inst21_out), - .O(Mux2xBit_inst7_O) -); -PEGEN_Mux2xBit Mux2xBit_inst8 ( - .I0(Mux2xBit_inst7_O), - .I1(bit_const_0_None_out), - .S(magma_Bits_5_eq_inst20_out), - .O(Mux2xBit_inst8_O) -); -PEGEN_Mux2xBit Mux2xBit_inst9 ( - .I0(Mux2xBit_inst8_O), - .I1(bit_const_0_None_out), - .S(magma_Bits_5_eq_inst19_out), - .O(Mux2xBit_inst9_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst0 ( - .I0(b), - .I1(a), - .S(Mux2xBit_inst0_O), - .O(Mux2xBits16_inst0_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst1 ( - .I0(b), - .I1(Mux2xBits16_inst0_O), - .S(magma_Bits_5_eq_inst0_out), - .O(Mux2xBits16_inst1_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst10 ( - .I0(Mux2xBits16_inst9_O), - .I1(magma_UInt_17_add_inst3_out[15:0]), - .S(magma_Bit_or_inst13_out), - .O(Mux2xBits16_inst10_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst11 ( - .I0(Mux2xBits16_inst10_O), - .I1(magma_Bits_16_shl_inst0_out), - .S(magma_Bits_5_eq_inst23_out), - .O(Mux2xBits16_inst11_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst12 ( - .I0(Mux2xBits16_inst11_O), - .I1(Mux2xBits16_inst4_O), - .S(magma_Bits_5_eq_inst22_out), - .O(Mux2xBits16_inst12_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst13 ( - .I0(Mux2xBits16_inst12_O), - .I1(magma_Bits_16_xor_inst0_out), - .S(magma_Bits_5_eq_inst21_out), - .O(Mux2xBits16_inst13_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst14 ( - .I0(Mux2xBits16_inst13_O), - .I1(magma_Bits_16_or_inst0_out), - .S(magma_Bits_5_eq_inst20_out), - .O(Mux2xBits16_inst14_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst15 ( - .I0(Mux2xBits16_inst14_O), - .I1(magma_Bits_16_and_inst0_out), - .S(magma_Bits_5_eq_inst19_out), - .O(Mux2xBits16_inst15_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst16 ( - .I0(Mux2xBits16_inst15_O), - .I1(Mux2xBits16_inst8_O), - .S(magma_Bits_5_eq_inst18_out), - .O(Mux2xBits16_inst16_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst17 ( - .I0(Mux2xBits16_inst16_O), - .I1(Mux2xBits16_inst7_O), - .S(magma_Bits_5_eq_inst17_out), - .O(Mux2xBits16_inst17_O) -); -wire [15:0] Mux2xBits16_inst18_I1; -assign Mux2xBits16_inst18_I1 = {magma_UInt_32_mul_inst0_out[31],magma_UInt_32_mul_inst0_out[30],magma_UInt_32_mul_inst0_out[29],magma_UInt_32_mul_inst0_out[28],magma_UInt_32_mul_inst0_out[27],magma_UInt_32_mul_inst0_out[26],magma_UInt_32_mul_inst0_out[25],magma_UInt_32_mul_inst0_out[24],magma_UInt_32_mul_inst0_out[23],magma_UInt_32_mul_inst0_out[22],magma_UInt_32_mul_inst0_out[21],magma_UInt_32_mul_inst0_out[20],magma_UInt_32_mul_inst0_out[19],magma_UInt_32_mul_inst0_out[18],magma_UInt_32_mul_inst0_out[17],magma_UInt_32_mul_inst0_out[16]}; -PEGEN_Mux2xBits16 Mux2xBits16_inst18 ( - .I0(Mux2xBits16_inst17_O), - .I1(Mux2xBits16_inst18_I1), - .S(magma_Bits_5_eq_inst16_out), - .O(Mux2xBits16_inst18_O) -); -wire [15:0] Mux2xBits16_inst19_I1; -assign Mux2xBits16_inst19_I1 = {magma_UInt_32_mul_inst0_out[23],magma_UInt_32_mul_inst0_out[22],magma_UInt_32_mul_inst0_out[21],magma_UInt_32_mul_inst0_out[20],magma_UInt_32_mul_inst0_out[19],magma_UInt_32_mul_inst0_out[18],magma_UInt_32_mul_inst0_out[17],magma_UInt_32_mul_inst0_out[16],magma_UInt_32_mul_inst0_out[15],magma_UInt_32_mul_inst0_out[14],magma_UInt_32_mul_inst0_out[13],magma_UInt_32_mul_inst0_out[12],magma_UInt_32_mul_inst0_out[11],magma_UInt_32_mul_inst0_out[10],magma_UInt_32_mul_inst0_out[9],magma_UInt_32_mul_inst0_out[8]}; -PEGEN_Mux2xBits16 Mux2xBits16_inst19 ( - .I0(Mux2xBits16_inst18_O), - .I1(Mux2xBits16_inst19_I1), - .S(magma_Bits_5_eq_inst15_out), - .O(Mux2xBits16_inst19_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst2 ( - .I0(c), - .I1(Mux2xBits16_inst1_O), - .S(Mux2xBit_inst1_O), - .O(Mux2xBits16_inst2_O) -); -wire [15:0] Mux2xBits16_inst20_I1; -assign Mux2xBits16_inst20_I1 = {magma_UInt_32_mul_inst0_out[15],magma_UInt_32_mul_inst0_out[14],magma_UInt_32_mul_inst0_out[13],magma_UInt_32_mul_inst0_out[12],magma_UInt_32_mul_inst0_out[11],magma_UInt_32_mul_inst0_out[10],magma_UInt_32_mul_inst0_out[9],magma_UInt_32_mul_inst0_out[8],magma_UInt_32_mul_inst0_out[7],magma_UInt_32_mul_inst0_out[6],magma_UInt_32_mul_inst0_out[5],magma_UInt_32_mul_inst0_out[4],magma_UInt_32_mul_inst0_out[3],magma_UInt_32_mul_inst0_out[2],magma_UInt_32_mul_inst0_out[1],magma_UInt_32_mul_inst0_out[0]}; -PEGEN_Mux2xBits16 Mux2xBits16_inst20 ( - .I0(Mux2xBits16_inst19_O), - .I1(Mux2xBits16_inst20_I1), - .S(magma_Bits_5_eq_inst14_out), - .O(Mux2xBits16_inst20_O) -); -wire [15:0] Mux2xBits16_inst21_I1; -assign Mux2xBits16_inst21_I1 = {magma_UInt_17_add_inst1_out[15],magma_UInt_17_add_inst1_out[14],magma_UInt_17_add_inst1_out[13],magma_UInt_17_add_inst1_out[12],magma_UInt_17_add_inst1_out[11],magma_UInt_17_add_inst1_out[10],magma_UInt_17_add_inst1_out[9],magma_UInt_17_add_inst1_out[8],magma_UInt_17_add_inst1_out[7],magma_UInt_17_add_inst1_out[6],magma_UInt_17_add_inst1_out[5],magma_UInt_17_add_inst1_out[4],magma_UInt_17_add_inst1_out[3],magma_UInt_17_add_inst1_out[2],magma_UInt_17_add_inst1_out[1],magma_UInt_17_add_inst1_out[0]}; -PEGEN_Mux2xBits16 Mux2xBits16_inst21 ( - .I0(Mux2xBits16_inst20_O), - .I1(Mux2xBits16_inst21_I1), - .S(magma_Bit_or_inst7_out), - .O(Mux2xBits16_inst21_O) -); -wire [15:0] Mux2xBits16_inst3_I1; -assign Mux2xBits16_inst3_I1 = {magma_UInt_32_mul_inst0_out[15],magma_UInt_32_mul_inst0_out[14],magma_UInt_32_mul_inst0_out[13],magma_UInt_32_mul_inst0_out[12],magma_UInt_32_mul_inst0_out[11],magma_UInt_32_mul_inst0_out[10],magma_UInt_32_mul_inst0_out[9],magma_UInt_32_mul_inst0_out[8],magma_UInt_32_mul_inst0_out[7],magma_UInt_32_mul_inst0_out[6],magma_UInt_32_mul_inst0_out[5],magma_UInt_32_mul_inst0_out[4],magma_UInt_32_mul_inst0_out[3],magma_UInt_32_mul_inst0_out[2],magma_UInt_32_mul_inst0_out[1],magma_UInt_32_mul_inst0_out[0]}; -PEGEN_Mux2xBits16 Mux2xBits16_inst3 ( - .I0(a), - .I1(Mux2xBits16_inst3_I1), - .S(magma_Bits_5_eq_inst1_out), - .O(Mux2xBits16_inst3_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst4 ( - .I0(magma_UInt_16_lshr_inst0_out), - .I1(magma_SInt_16_ashr_inst0_out), - .S(magma_Bits_1_eq_inst3_out), - .O(Mux2xBits16_inst4_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst5 ( - .I0(b), - .I1(magma_Bits_16_not_inst0_out), - .S(magma_Bit_or_inst1_out), - .O(Mux2xBits16_inst5_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst6 ( - .I0(c), - .I1(magma_Bits_16_not_inst1_out), - .S(magma_Bit_or_inst6_out), - .O(Mux2xBits16_inst6_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst7 ( - .I0(magma_SInt_16_neg_inst0_out), - .I1(a), - .S(magma_SInt_16_sle_inst1_out), - .O(Mux2xBits16_inst7_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst8 ( - .I0(Mux2xBits16_inst5_O), - .I1(a), - .S(d), - .O(Mux2xBits16_inst8_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst9 ( - .I0(Mux2xBits16_inst4_O), - .I1(Mux2xBits16_inst2_O), - .S(magma_Bits_5_eq_inst30_out), - .O(Mux2xBits16_inst9_O) -); -wire [15:0] Mux2xUInt16_inst0_I0; -assign Mux2xUInt16_inst0_I0 = {magma_UInt_32_mul_inst0_out[15],magma_UInt_32_mul_inst0_out[14],magma_UInt_32_mul_inst0_out[13],magma_UInt_32_mul_inst0_out[12],magma_UInt_32_mul_inst0_out[11],magma_UInt_32_mul_inst0_out[10],magma_UInt_32_mul_inst0_out[9],magma_UInt_32_mul_inst0_out[8],magma_UInt_32_mul_inst0_out[7],magma_UInt_32_mul_inst0_out[6],magma_UInt_32_mul_inst0_out[5],magma_UInt_32_mul_inst0_out[4],magma_UInt_32_mul_inst0_out[3],magma_UInt_32_mul_inst0_out[2],magma_UInt_32_mul_inst0_out[1],magma_UInt_32_mul_inst0_out[0]}; -wire [15:0] Mux2xUInt16_inst0_I1; -assign Mux2xUInt16_inst0_I1 = {magma_UInt_17_add_inst1_out[15],magma_UInt_17_add_inst1_out[14],magma_UInt_17_add_inst1_out[13],magma_UInt_17_add_inst1_out[12],magma_UInt_17_add_inst1_out[11],magma_UInt_17_add_inst1_out[10],magma_UInt_17_add_inst1_out[9],magma_UInt_17_add_inst1_out[8],magma_UInt_17_add_inst1_out[7],magma_UInt_17_add_inst1_out[6],magma_UInt_17_add_inst1_out[5],magma_UInt_17_add_inst1_out[4],magma_UInt_17_add_inst1_out[3],magma_UInt_17_add_inst1_out[2],magma_UInt_17_add_inst1_out[1],magma_UInt_17_add_inst1_out[0]}; -PEGEN_Mux2xUInt16 Mux2xUInt16_inst0 ( - .I0(Mux2xUInt16_inst0_I0), - .I1(Mux2xUInt16_inst0_I1), - .S(magma_Bit_or_inst4_out), - .O(Mux2xUInt16_inst0_O) -); -wire [31:0] Mux2xUInt32_inst0_I0; -assign Mux2xUInt32_inst0_I0 = {bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,a}; -wire [31:0] Mux2xUInt32_inst0_I1; -assign Mux2xUInt32_inst0_I1 = {a[15],a[15],a[15],a[15],a[15],a[15],a[15],a[15],a[15],a[15],a[15],a[15],a[15],a[15],a[15],a[15],a}; -PEGEN_Mux2xUInt32 Mux2xUInt32_inst0 ( - .I0(Mux2xUInt32_inst0_I0), - .I1(Mux2xUInt32_inst0_I1), - .S(magma_Bits_1_eq_inst0_out), - .O(Mux2xUInt32_inst0_O) -); -wire [31:0] Mux2xUInt32_inst1_I0; -assign Mux2xUInt32_inst1_I0 = {bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,b}; -wire [31:0] Mux2xUInt32_inst1_I1; -assign Mux2xUInt32_inst1_I1 = {b[15],b[15],b[15],b[15],b[15],b[15],b[15],b[15],b[15],b[15],b[15],b[15],b[15],b[15],b[15],b[15],b}; -PEGEN_Mux2xUInt32 Mux2xUInt32_inst1 ( - .I0(Mux2xUInt32_inst1_I0), - .I1(Mux2xUInt32_inst1_I1), - .S(magma_Bits_1_eq_inst0_out), - .O(Mux2xUInt32_inst1_O) -); -PEGEN_corebit_const #( - .value(1'b0) -) bit_const_0_None ( - .out(bit_const_0_None_out) -); -PEGEN_corebit_const #( - .value(1'b1) -) bit_const_1_None ( - .out(bit_const_1_None_out) -); -PEGEN_coreir_const #( - .value(16'h0000), - .width(16) -) const_0_16 ( - .out(const_0_16_out) -); -PEGEN_coreir_const #( - .value(5'h00), - .width(5) -) const_0_5 ( - .out(const_0_5_out) -); -PEGEN_coreir_const #( - .value(5'h0a), - .width(5) -) const_10_5 ( - .out(const_10_5_out) -); -PEGEN_coreir_const #( - .value(5'h0b), - .width(5) -) const_11_5 ( - .out(const_11_5_out) -); -PEGEN_coreir_const #( - .value(5'h0c), - .width(5) -) const_12_5 ( - .out(const_12_5_out) -); -PEGEN_coreir_const #( - .value(5'h0d), - .width(5) -) const_13_5 ( - .out(const_13_5_out) -); -PEGEN_coreir_const #( - .value(5'h0e), - .width(5) -) const_14_5 ( - .out(const_14_5_out) -); -PEGEN_coreir_const #( - .value(5'h0f), - .width(5) -) const_15_5 ( - .out(const_15_5_out) -); -PEGEN_coreir_const #( - .value(5'h10), - .width(5) -) const_16_5 ( - .out(const_16_5_out) -); -PEGEN_coreir_const #( - .value(5'h11), - .width(5) -) const_17_5 ( - .out(const_17_5_out) -); -PEGEN_coreir_const #( - .value(5'h12), - .width(5) -) const_18_5 ( - .out(const_18_5_out) -); -PEGEN_coreir_const #( - .value(5'h13), - .width(5) -) const_19_5 ( - .out(const_19_5_out) -); -PEGEN_coreir_const #( - .value(1'h1), - .width(1) -) const_1_1 ( - .out(const_1_1_out) -); -PEGEN_coreir_const #( - .value(5'h01), - .width(5) -) const_1_5 ( - .out(const_1_5_out) -); -PEGEN_coreir_const #( - .value(5'h02), - .width(5) -) const_2_5 ( - .out(const_2_5_out) -); -PEGEN_coreir_const #( - .value(5'h03), - .width(5) -) const_3_5 ( - .out(const_3_5_out) -); -PEGEN_coreir_const #( - .value(5'h04), - .width(5) -) const_4_5 ( - .out(const_4_5_out) -); -PEGEN_coreir_const #( - .value(5'h05), - .width(5) -) const_5_5 ( - .out(const_5_5_out) -); -PEGEN_coreir_const #( - .value(5'h06), - .width(5) -) const_6_5 ( - .out(const_6_5_out) -); -PEGEN_coreir_const #( - .value(5'h07), - .width(5) -) const_7_5 ( - .out(const_7_5_out) -); -PEGEN_coreir_const #( - .value(5'h08), - .width(5) -) const_8_5 ( - .out(const_8_5_out) -); -PEGEN_coreir_const #( - .value(5'h09), - .width(5) -) const_9_5 ( - .out(const_9_5_out) -); -PEGEN_corebit_and magma_Bit_and_inst0 ( - .in0(a[15]), - .in1(Mux2xBits16_inst5_O[15]), - .out(magma_Bit_and_inst0_out) -); -PEGEN_corebit_and magma_Bit_and_inst1 ( - .in0(magma_Bit_and_inst0_out), - .in1(magma_Bit_not_inst0_out), - .out(magma_Bit_and_inst1_out) -); -PEGEN_corebit_and magma_Bit_and_inst2 ( - .in0(magma_Bit_not_inst1_out), - .in1(magma_Bit_not_inst2_out), - .out(magma_Bit_and_inst2_out) -); -PEGEN_corebit_and magma_Bit_and_inst3 ( - .in0(magma_Bit_and_inst2_out), - .in1(magma_UInt_17_add_inst1_out[15]), - .out(magma_Bit_and_inst3_out) -); -PEGEN_corebit_not magma_Bit_not_inst0 ( - .in(magma_UInt_17_add_inst1_out[15]), - .out(magma_Bit_not_inst0_out) -); -PEGEN_corebit_not magma_Bit_not_inst1 ( - .in(a[15]), - .out(magma_Bit_not_inst1_out) -); -PEGEN_corebit_not magma_Bit_not_inst2 ( - .in(Mux2xBits16_inst5_O[15]), - .out(magma_Bit_not_inst2_out) -); -PEGEN_corebit_or magma_Bit_or_inst0 ( - .in0(magma_Bits_5_eq_inst2_out), - .in1(magma_Bits_5_eq_inst3_out), - .out(magma_Bit_or_inst0_out) -); -PEGEN_corebit_or magma_Bit_or_inst1 ( - .in0(magma_Bit_or_inst0_out), - .in1(magma_Bits_5_eq_inst4_out), - .out(magma_Bit_or_inst1_out) -); -PEGEN_corebit_or magma_Bit_or_inst10 ( - .in0(magma_Bit_or_inst9_out), - .in1(magma_Bits_5_eq_inst26_out), - .out(magma_Bit_or_inst10_out) -); -PEGEN_corebit_or magma_Bit_or_inst11 ( - .in0(magma_Bit_or_inst10_out), - .in1(magma_Bits_5_eq_inst27_out), - .out(magma_Bit_or_inst11_out) -); -PEGEN_corebit_or magma_Bit_or_inst12 ( - .in0(magma_Bit_or_inst11_out), - .in1(magma_Bits_5_eq_inst28_out), - .out(magma_Bit_or_inst12_out) -); -PEGEN_corebit_or magma_Bit_or_inst13 ( - .in0(magma_Bit_or_inst12_out), - .in1(magma_Bits_5_eq_inst29_out), - .out(magma_Bit_or_inst13_out) -); -PEGEN_corebit_or magma_Bit_or_inst2 ( - .in0(magma_Bits_5_eq_inst5_out), - .in1(magma_Bits_5_eq_inst6_out), - .out(magma_Bit_or_inst2_out) -); -PEGEN_corebit_or magma_Bit_or_inst3 ( - .in0(magma_Bit_or_inst2_out), - .in1(magma_Bits_5_eq_inst7_out), - .out(magma_Bit_or_inst3_out) -); -PEGEN_corebit_or magma_Bit_or_inst4 ( - .in0(magma_Bit_or_inst3_out), - .in1(magma_Bits_5_eq_inst8_out), - .out(magma_Bit_or_inst4_out) -); -PEGEN_corebit_or magma_Bit_or_inst5 ( - .in0(magma_Bits_5_eq_inst9_out), - .in1(magma_Bits_5_eq_inst10_out), - .out(magma_Bit_or_inst5_out) -); -PEGEN_corebit_or magma_Bit_or_inst6 ( - .in0(magma_Bit_or_inst5_out), - .in1(magma_Bits_5_eq_inst11_out), - .out(magma_Bit_or_inst6_out) -); -PEGEN_corebit_or magma_Bit_or_inst7 ( - .in0(magma_Bits_5_eq_inst12_out), - .in1(magma_Bits_5_eq_inst13_out), - .out(magma_Bit_or_inst7_out) -); -PEGEN_corebit_or magma_Bit_or_inst8 ( - .in0(magma_Bit_and_inst1_out), - .in1(magma_Bit_and_inst3_out), - .out(magma_Bit_or_inst8_out) -); -PEGEN_corebit_or magma_Bit_or_inst9 ( - .in0(magma_Bits_5_eq_inst24_out), - .in1(magma_Bits_5_eq_inst25_out), - .out(magma_Bit_or_inst9_out) -); -PEGEN_coreir_and #( - .width(16) -) magma_Bits_16_and_inst0 ( - .in0(a), - .in1(Mux2xBits16_inst5_O), - .out(magma_Bits_16_and_inst0_out) -); -PEGEN_coreir_not #( - .width(16) -) magma_Bits_16_not_inst0 ( - .in(b), - .out(magma_Bits_16_not_inst0_out) -); -PEGEN_coreir_not #( - .width(16) -) magma_Bits_16_not_inst1 ( - .in(c), - .out(magma_Bits_16_not_inst1_out) -); -PEGEN_coreir_or #( - .width(16) -) magma_Bits_16_or_inst0 ( - .in0(a), - .in1(Mux2xBits16_inst5_O), - .out(magma_Bits_16_or_inst0_out) -); -PEGEN_coreir_shl #( - .width(16) -) magma_Bits_16_shl_inst0 ( - .in0(a), - .in1(Mux2xBits16_inst5_O), - .out(magma_Bits_16_shl_inst0_out) -); -PEGEN_coreir_xor #( - .width(16) -) magma_Bits_16_xor_inst0 ( - .in0(a), - .in1(Mux2xBits16_inst5_O), - .out(magma_Bits_16_xor_inst0_out) -); -PEGEN_coreir_eq #( - .width(1) -) magma_Bits_1_eq_inst0 ( - .in0(signed_), - .in1(const_1_1_out), - .out(magma_Bits_1_eq_inst0_out) -); -PEGEN_coreir_eq #( - .width(1) -) magma_Bits_1_eq_inst1 ( - .in0(signed_), - .in1(const_1_1_out), - .out(magma_Bits_1_eq_inst1_out) -); -PEGEN_coreir_eq #( - .width(1) -) magma_Bits_1_eq_inst2 ( - .in0(signed_), - .in1(const_1_1_out), - .out(magma_Bits_1_eq_inst2_out) -); -PEGEN_coreir_eq #( - .width(1) -) magma_Bits_1_eq_inst3 ( - .in0(signed_), - .in1(const_1_1_out), - .out(magma_Bits_1_eq_inst3_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst0 ( - .in0(alu), - .in1(const_18_5_out), - .out(magma_Bits_5_eq_inst0_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst1 ( - .in0(alu), - .in1(const_19_5_out), - .out(magma_Bits_5_eq_inst1_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst10 ( - .in0(alu), - .in1(const_15_5_out), - .out(magma_Bits_5_eq_inst10_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst11 ( - .in0(alu), - .in1(const_17_5_out), - .out(magma_Bits_5_eq_inst11_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst12 ( - .in0(alu), - .in1(const_0_5_out), - .out(magma_Bits_5_eq_inst12_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst13 ( - .in0(alu), - .in1(const_1_5_out), - .out(magma_Bits_5_eq_inst13_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst14 ( - .in0(alu), - .in1(const_4_5_out), - .out(magma_Bits_5_eq_inst14_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst15 ( - .in0(alu), - .in1(const_5_5_out), - .out(magma_Bits_5_eq_inst15_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst16 ( - .in0(alu), - .in1(const_6_5_out), - .out(magma_Bits_5_eq_inst16_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst17 ( - .in0(alu), - .in1(const_2_5_out), - .out(magma_Bits_5_eq_inst17_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst18 ( - .in0(alu), - .in1(const_3_5_out), - .out(magma_Bits_5_eq_inst18_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst19 ( - .in0(alu), - .in1(const_10_5_out), - .out(magma_Bits_5_eq_inst19_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst2 ( - .in0(alu), - .in1(const_1_5_out), - .out(magma_Bits_5_eq_inst2_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst20 ( - .in0(alu), - .in1(const_9_5_out), - .out(magma_Bits_5_eq_inst20_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst21 ( - .in0(alu), - .in1(const_11_5_out), - .out(magma_Bits_5_eq_inst21_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst22 ( - .in0(alu), - .in1(const_7_5_out), - .out(magma_Bits_5_eq_inst22_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst23 ( - .in0(alu), - .in1(const_8_5_out), - .out(magma_Bits_5_eq_inst23_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst24 ( - .in0(alu), - .in1(const_12_5_out), - .out(magma_Bits_5_eq_inst24_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst25 ( - .in0(alu), - .in1(const_13_5_out), - .out(magma_Bits_5_eq_inst25_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst26 ( - .in0(alu), - .in1(const_14_5_out), - .out(magma_Bits_5_eq_inst26_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst27 ( - .in0(alu), - .in1(const_16_5_out), - .out(magma_Bits_5_eq_inst27_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst28 ( - .in0(alu), - .in1(const_15_5_out), - .out(magma_Bits_5_eq_inst28_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst29 ( - .in0(alu), - .in1(const_17_5_out), - .out(magma_Bits_5_eq_inst29_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst3 ( - .in0(alu), - .in1(const_16_5_out), - .out(magma_Bits_5_eq_inst3_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst30 ( - .in0(alu), - .in1(const_18_5_out), - .out(magma_Bits_5_eq_inst30_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst4 ( - .in0(alu), - .in1(const_17_5_out), - .out(magma_Bits_5_eq_inst4_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst5 ( - .in0(alu), - .in1(const_14_5_out), - .out(magma_Bits_5_eq_inst5_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst6 ( - .in0(alu), - .in1(const_15_5_out), - .out(magma_Bits_5_eq_inst6_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst7 ( - .in0(alu), - .in1(const_16_5_out), - .out(magma_Bits_5_eq_inst7_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst8 ( - .in0(alu), - .in1(const_17_5_out), - .out(magma_Bits_5_eq_inst8_out) -); -PEGEN_coreir_eq #( - .width(5) -) magma_Bits_5_eq_inst9 ( - .in0(alu), - .in1(const_13_5_out), - .out(magma_Bits_5_eq_inst9_out) -); -PEGEN_coreir_ashr #( - .width(16) -) magma_SInt_16_ashr_inst0 ( - .in0(Mux2xBits16_inst3_O), - .in1(c), - .out(magma_SInt_16_ashr_inst0_out) -); -PEGEN_coreir_eq #( - .width(16) -) magma_SInt_16_eq_inst0 ( - .in0(const_0_16_out), - .in1(Mux2xBits16_inst21_O), - .out(magma_SInt_16_eq_inst0_out) -); -PEGEN_coreir_neg #( - .width(16) -) magma_SInt_16_neg_inst0 ( - .in(a), - .out(magma_SInt_16_neg_inst0_out) -); -PEGEN_coreir_sge #( - .width(16) -) magma_SInt_16_sge_inst0 ( - .in0(Mux2xBits16_inst1_O), - .in1(c), - .out(magma_SInt_16_sge_inst0_out) -); -PEGEN_coreir_sle #( - .width(16) -) magma_SInt_16_sle_inst0 ( - .in0(a), - .in1(b), - .out(magma_SInt_16_sle_inst0_out) -); -PEGEN_coreir_sle #( - .width(16) -) magma_SInt_16_sle_inst1 ( - .in0(const_0_16_out), - .in1(a), - .out(magma_SInt_16_sle_inst1_out) -); -PEGEN_coreir_lshr #( - .width(16) -) magma_UInt_16_lshr_inst0 ( - .in0(Mux2xBits16_inst3_O), - .in1(c), - .out(magma_UInt_16_lshr_inst0_out) -); -PEGEN_coreir_uge #( - .width(16) -) magma_UInt_16_uge_inst0 ( - .in0(Mux2xBits16_inst1_O), - .in1(c), - .out(magma_UInt_16_uge_inst0_out) -); -PEGEN_coreir_ule #( - .width(16) -) magma_UInt_16_ule_inst0 ( - .in0(a), - .in1(b), - .out(magma_UInt_16_ule_inst0_out) -); -wire [16:0] magma_UInt_17_add_inst0_in0; -assign magma_UInt_17_add_inst0_in0 = {bit_const_0_None_out,a}; -wire [16:0] magma_UInt_17_add_inst0_in1; -assign magma_UInt_17_add_inst0_in1 = {bit_const_0_None_out,Mux2xBits16_inst5_O}; -PEGEN_coreir_add #( - .width(17) -) magma_UInt_17_add_inst0 ( - .in0(magma_UInt_17_add_inst0_in0), - .in1(magma_UInt_17_add_inst0_in1), - .out(magma_UInt_17_add_inst0_out) -); -wire [16:0] magma_UInt_17_add_inst1_in1; -assign magma_UInt_17_add_inst1_in1 = {bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,d}; -PEGEN_coreir_add #( - .width(17) -) magma_UInt_17_add_inst1 ( - .in0(magma_UInt_17_add_inst0_out), - .in1(magma_UInt_17_add_inst1_in1), - .out(magma_UInt_17_add_inst1_out) -); -wire [16:0] magma_UInt_17_add_inst2_in0; -assign magma_UInt_17_add_inst2_in0 = {bit_const_0_None_out,Mux2xUInt16_inst0_O}; -wire [16:0] magma_UInt_17_add_inst2_in1; -assign magma_UInt_17_add_inst2_in1 = {bit_const_0_None_out,Mux2xBits16_inst6_O}; -PEGEN_coreir_add #( - .width(17) -) magma_UInt_17_add_inst2 ( - .in0(magma_UInt_17_add_inst2_in0), - .in1(magma_UInt_17_add_inst2_in1), - .out(magma_UInt_17_add_inst2_out) -); -wire [16:0] magma_UInt_17_add_inst3_in1; -assign magma_UInt_17_add_inst3_in1 = {bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,bit_const_0_None_out,Mux2xBit_inst2_O}; -PEGEN_coreir_add #( - .width(17) -) magma_UInt_17_add_inst3 ( - .in0(magma_UInt_17_add_inst2_out), - .in1(magma_UInt_17_add_inst3_in1), - .out(magma_UInt_17_add_inst3_out) -); -PEGEN_coreir_mul #( - .width(32) -) magma_UInt_32_mul_inst0 ( - .in0(Mux2xUInt32_inst0_O), - .in1(Mux2xUInt32_inst1_O), - .out(magma_UInt_32_mul_inst0_out) -); -assign res = Mux2xBits16_inst21_O; -assign res_p = Mux2xBit_inst23_O; -assign Z = magma_SInt_16_eq_inst0_out; -assign N = Mux2xBits16_inst21_O[15]; -assign C = Mux2xBit_inst21_O; -assign V = Mux2xBit_inst22_O; -endmodule - -module PEGEN_PE ( - input [83:0] inst, - input [15:0] data0, - input [15:0] data1, - input [15:0] data2, - input bit0, - input bit1, - input bit2, - input clk_en, - output [15:0] O0, - output O1, - output [15:0] O2, - output [15:0] O3, - output [15:0] O4, - input CLK, - input ASYNCRESET -); -wire [15:0] ALU_inst0_res; -wire ALU_inst0_res_p; -wire ALU_inst0_Z; -wire ALU_inst0_N; -wire ALU_inst0_C; -wire ALU_inst0_V; -wire Cond_inst0_O; -wire [15:0] FPCustom_inst0_res; -wire FPCustom_inst0_res_p; -wire FPCustom_inst0_V; -wire [15:0] FPU_inst0_res; -wire FPU_inst0_N; -wire FPU_inst0_Z; -wire LUT_inst0_O; -wire Mux2xBit_inst0_O; -wire Mux2xBit_inst1_O; -wire Mux2xBit_inst2_O; -wire Mux2xBit_inst3_O; -wire Mux2xBit_inst4_O; -wire Mux2xBit_inst5_O; -wire Mux2xBit_inst6_O; -wire Mux2xBit_inst7_O; -wire [15:0] Mux2xBits16_inst0_O; -wire [15:0] Mux2xBits16_inst1_O; -wire [4:0] Mux2xMagmaADTALU_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst0_O; -wire [2:0] Mux2xMagmaADTFPCustom_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst0_O; -wire [2:0] Mux2xMagmaADTFPCustom_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst1_O; -wire [2:0] Mux2xMagmaADTFPU_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst0_O; -wire [2:0] Mux2xMagmaADTFPU_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst1_O; -wire [15:0] RegisterMode_inst0_O0; -wire [15:0] RegisterMode_inst0_O1; -wire [15:0] RegisterMode_inst1_O0; -wire [15:0] RegisterMode_inst1_O1; -wire [15:0] RegisterMode_inst2_O0; -wire [15:0] RegisterMode_inst2_O1; -wire RegisterMode_inst3_O0; -wire RegisterMode_inst3_O1; -wire RegisterMode_inst4_O0; -wire RegisterMode_inst4_O1; -wire RegisterMode_inst5_O0; -wire RegisterMode_inst5_O1; -wire bit_const_0_None_out; -wire [1:0] const_0_2_out; -wire [2:0] const_0_3_out; -wire [4:0] const_0_5_out; -wire [1:0] const_1_2_out; -wire [1:0] const_2_2_out; -wire magma_Bits_2_eq_inst0_out; -wire magma_Bits_2_eq_inst1_out; -wire magma_Bits_2_eq_inst2_out; -wire magma_Bits_2_eq_inst3_out; -wire magma_Bits_2_eq_inst4_out; -wire magma_Bits_2_eq_inst5_out; -wire magma_Bits_2_eq_inst6_out; -PEGEN_ALU ALU_inst0 ( - .alu(Mux2xMagmaADTALU_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst0_O), - .signed_(inst[7:7]), - .a(RegisterMode_inst0_O0), - .b(RegisterMode_inst1_O0), - .c(RegisterMode_inst2_O0), - .d(RegisterMode_inst3_O0), - .res(ALU_inst0_res), - .res_p(ALU_inst0_res_p), - .Z(ALU_inst0_Z), - .N(ALU_inst0_N), - .C(ALU_inst0_C), - .V(ALU_inst0_V), - .CLK(CLK), - .ASYNCRESET(ASYNCRESET) -); -PEGEN_Cond Cond_inst0 ( - .code(inst[20:16]), - .alu(Mux2xBit_inst7_O), - .lut(LUT_inst0_O), - .Z(Mux2xBit_inst6_O), - .N(Mux2xBit_inst4_O), - .C(ALU_inst0_C), - .V(Mux2xBit_inst5_O), - .O(Cond_inst0_O), - .CLK(CLK), - .ASYNCRESET(ASYNCRESET) -); -PEGEN_FPCustom FPCustom_inst0 ( - .op(Mux2xMagmaADTFPCustom_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst1_O), - .signed_(inst[7:7]), - .a(RegisterMode_inst0_O0), - .b(RegisterMode_inst1_O0), - .res(FPCustom_inst0_res), - .res_p(FPCustom_inst0_res_p), - .V(FPCustom_inst0_V), - .CLK(CLK), - .ASYNCRESET(ASYNCRESET) -); -PEGEN_FPU FPU_inst0 ( - .fpu_op(Mux2xMagmaADTFPU_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst1_O), - .a(RegisterMode_inst0_O0), - .b(RegisterMode_inst1_O0), - .res(FPU_inst0_res), - .N(FPU_inst0_N), - .Z(FPU_inst0_Z), - .CLK(CLK), - .ASYNCRESET(ASYNCRESET) -); -wire [7:0] LUT_inst0_lut; -assign LUT_inst0_lut = {inst[15],inst[14],inst[13],inst[12],inst[11],inst[10],inst[9],inst[8]}; -PEGEN_LUT LUT_inst0 ( - .lut(LUT_inst0_lut), - .bit0(RegisterMode_inst3_O0), - .bit1(RegisterMode_inst4_O0), - .bit2(RegisterMode_inst5_O0), - .O(LUT_inst0_O), - .CLK(CLK), - .ASYNCRESET(ASYNCRESET) -); -PEGEN_Mux2xBit Mux2xBit_inst0 ( - .I0(bit_const_0_None_out), - .I1(FPU_inst0_N), - .S(magma_Bits_2_eq_inst6_out), - .O(Mux2xBit_inst0_O) -); -PEGEN_Mux2xBit Mux2xBit_inst1 ( - .I0(FPCustom_inst0_V), - .I1(bit_const_0_None_out), - .S(magma_Bits_2_eq_inst6_out), - .O(Mux2xBit_inst1_O) -); -PEGEN_Mux2xBit Mux2xBit_inst2 ( - .I0(bit_const_0_None_out), - .I1(FPU_inst0_Z), - .S(magma_Bits_2_eq_inst6_out), - .O(Mux2xBit_inst2_O) -); -PEGEN_Mux2xBit Mux2xBit_inst3 ( - .I0(FPCustom_inst0_res_p), - .I1(bit_const_0_None_out), - .S(magma_Bits_2_eq_inst6_out), - .O(Mux2xBit_inst3_O) -); -PEGEN_Mux2xBit Mux2xBit_inst4 ( - .I0(Mux2xBit_inst0_O), - .I1(ALU_inst0_N), - .S(magma_Bits_2_eq_inst5_out), - .O(Mux2xBit_inst4_O) -); -PEGEN_Mux2xBit Mux2xBit_inst5 ( - .I0(Mux2xBit_inst1_O), - .I1(ALU_inst0_V), - .S(magma_Bits_2_eq_inst5_out), - .O(Mux2xBit_inst5_O) -); -PEGEN_Mux2xBit Mux2xBit_inst6 ( - .I0(Mux2xBit_inst2_O), - .I1(ALU_inst0_Z), - .S(magma_Bits_2_eq_inst5_out), - .O(Mux2xBit_inst6_O) -); -PEGEN_Mux2xBit Mux2xBit_inst7 ( - .I0(Mux2xBit_inst3_O), - .I1(ALU_inst0_res_p), - .S(magma_Bits_2_eq_inst5_out), - .O(Mux2xBit_inst7_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst0 ( - .I0(FPCustom_inst0_res), - .I1(FPU_inst0_res), - .S(magma_Bits_2_eq_inst6_out), - .O(Mux2xBits16_inst0_O) -); -PEGEN_Mux2xBits16 Mux2xBits16_inst1 ( - .I0(Mux2xBits16_inst0_O), - .I1(ALU_inst0_res), - .S(magma_Bits_2_eq_inst5_out), - .O(Mux2xBits16_inst1_O) -); -wire [4:0] Mux2xMagmaADTALU_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst0_I1; -assign Mux2xMagmaADTALU_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst0_I1 = {inst[6],inst[5],inst[4],inst[3],inst[2]}; -PEGEN_Mux2xMagmaADTALU_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3 Mux2xMagmaADTALU_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst0 ( - .I0(const_0_5_out), - .I1(Mux2xMagmaADTALU_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst0_I1), - .S(magma_Bits_2_eq_inst0_out), - .O(Mux2xMagmaADTALU_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst0_O) -); -wire [2:0] Mux2xMagmaADTFPCustom_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst0_I0; -assign Mux2xMagmaADTFPCustom_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst0_I0 = {inst[4],inst[3],inst[2]}; -PEGEN_Mux2xMagmaADTFPCustom_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3 Mux2xMagmaADTFPCustom_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst0 ( - .I0(Mux2xMagmaADTFPCustom_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst0_I0), - .I1(const_0_3_out), - .S(magma_Bits_2_eq_inst2_out), - .O(Mux2xMagmaADTFPCustom_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst0_O) -); -PEGEN_Mux2xMagmaADTFPCustom_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3 Mux2xMagmaADTFPCustom_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst1 ( - .I0(Mux2xMagmaADTFPCustom_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst0_O), - .I1(const_0_3_out), - .S(magma_Bits_2_eq_inst0_out), - .O(Mux2xMagmaADTFPCustom_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst1_O) -); -wire [2:0] Mux2xMagmaADTFPU_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst0_I1; -assign Mux2xMagmaADTFPU_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst0_I1 = {inst[4],inst[3],inst[2]}; -PEGEN_Mux2xMagmaADTFPU_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3 Mux2xMagmaADTFPU_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst0 ( - .I0(const_0_3_out), - .I1(Mux2xMagmaADTFPU_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst0_I1), - .S(magma_Bits_2_eq_inst2_out), - .O(Mux2xMagmaADTFPU_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst0_O) -); -PEGEN_Mux2xMagmaADTFPU_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3 Mux2xMagmaADTFPU_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst1 ( - .I0(Mux2xMagmaADTFPU_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst0_O), - .I1(const_0_3_out), - .S(magma_Bits_2_eq_inst0_out), - .O(Mux2xMagmaADTFPU_t_classpeakassemblerassemblerAssembler_Bits_DirectionUndirected3_inst1_O) -); -wire [15:0] RegisterMode_inst0_const_; -assign RegisterMode_inst0_const_ = {inst[38],inst[37],inst[36],inst[35],inst[34],inst[33],inst[32],inst[31],inst[30],inst[29],inst[28],inst[27],inst[26],inst[25],inst[24],inst[23]}; -PEGEN_RegisterMode RegisterMode_inst0 ( - .mode(inst[22:21]), - .const_(RegisterMode_inst0_const_), - .value(data0), - .clk_en(clk_en), - .O0(RegisterMode_inst0_O0), - .O1(RegisterMode_inst0_O1), - .CLK(CLK), - .ASYNCRESET(ASYNCRESET) -); -wire [15:0] RegisterMode_inst1_const_; -assign RegisterMode_inst1_const_ = {inst[56],inst[55],inst[54],inst[53],inst[52],inst[51],inst[50],inst[49],inst[48],inst[47],inst[46],inst[45],inst[44],inst[43],inst[42],inst[41]}; -PEGEN_RegisterMode RegisterMode_inst1 ( - .mode(inst[40:39]), - .const_(RegisterMode_inst1_const_), - .value(data1), - .clk_en(clk_en), - .O0(RegisterMode_inst1_O0), - .O1(RegisterMode_inst1_O1), - .CLK(CLK), - .ASYNCRESET(ASYNCRESET) -); -wire [15:0] RegisterMode_inst2_const_; -assign RegisterMode_inst2_const_ = {inst[74],inst[73],inst[72],inst[71],inst[70],inst[69],inst[68],inst[67],inst[66],inst[65],inst[64],inst[63],inst[62],inst[61],inst[60],inst[59]}; -PEGEN_RegisterMode RegisterMode_inst2 ( - .mode(inst[58:57]), - .const_(RegisterMode_inst2_const_), - .value(data2), - .clk_en(clk_en), - .O0(RegisterMode_inst2_O0), - .O1(RegisterMode_inst2_O1), - .CLK(CLK), - .ASYNCRESET(ASYNCRESET) -); -PEGEN_RegisterMode_unq1 RegisterMode_inst3 ( - .mode(inst[76:75]), - .const_(inst[77]), - .value(bit0), - .clk_en(clk_en), - .O0(RegisterMode_inst3_O0), - .O1(RegisterMode_inst3_O1), - .CLK(CLK), - .ASYNCRESET(ASYNCRESET) -); -PEGEN_RegisterMode_unq1 RegisterMode_inst4 ( - .mode(inst[79:78]), - .const_(inst[80]), - .value(bit1), - .clk_en(clk_en), - .O0(RegisterMode_inst4_O0), - .O1(RegisterMode_inst4_O1), - .CLK(CLK), - .ASYNCRESET(ASYNCRESET) -); -PEGEN_RegisterMode_unq1 RegisterMode_inst5 ( - .mode(inst[82:81]), - .const_(inst[83]), - .value(bit2), - .clk_en(clk_en), - .O0(RegisterMode_inst5_O0), - .O1(RegisterMode_inst5_O1), - .CLK(CLK), - .ASYNCRESET(ASYNCRESET) -); -PEGEN_corebit_const #( - .value(1'b0) -) bit_const_0_None ( - .out(bit_const_0_None_out) -); -PEGEN_coreir_const #( - .value(2'h0), - .width(2) -) const_0_2 ( - .out(const_0_2_out) -); -PEGEN_coreir_const #( - .value(3'h0), - .width(3) -) const_0_3 ( - .out(const_0_3_out) -); -PEGEN_coreir_const #( - .value(5'h00), - .width(5) -) const_0_5 ( - .out(const_0_5_out) -); -PEGEN_coreir_const #( - .value(2'h1), - .width(2) -) const_1_2 ( - .out(const_1_2_out) -); -PEGEN_coreir_const #( - .value(2'h2), - .width(2) -) const_2_2 ( - .out(const_2_2_out) -); -wire [1:0] magma_Bits_2_eq_inst0_in0; -assign magma_Bits_2_eq_inst0_in0 = {inst[1],inst[0]}; -PEGEN_coreir_eq #( - .width(2) -) magma_Bits_2_eq_inst0 ( - .in0(magma_Bits_2_eq_inst0_in0), - .in1(const_0_2_out), - .out(magma_Bits_2_eq_inst0_out) -); -wire [1:0] magma_Bits_2_eq_inst1_in0; -assign magma_Bits_2_eq_inst1_in0 = {inst[1],inst[0]}; -PEGEN_coreir_eq #( - .width(2) -) magma_Bits_2_eq_inst1 ( - .in0(magma_Bits_2_eq_inst1_in0), - .in1(const_0_2_out), - .out(magma_Bits_2_eq_inst1_out) -); -wire [1:0] magma_Bits_2_eq_inst2_in0; -assign magma_Bits_2_eq_inst2_in0 = {inst[1],inst[0]}; -PEGEN_coreir_eq #( - .width(2) -) magma_Bits_2_eq_inst2 ( - .in0(magma_Bits_2_eq_inst2_in0), - .in1(const_2_2_out), - .out(magma_Bits_2_eq_inst2_out) -); -wire [1:0] magma_Bits_2_eq_inst3_in0; -assign magma_Bits_2_eq_inst3_in0 = {inst[1],inst[0]}; -PEGEN_coreir_eq #( - .width(2) -) magma_Bits_2_eq_inst3 ( - .in0(magma_Bits_2_eq_inst3_in0), - .in1(const_2_2_out), - .out(magma_Bits_2_eq_inst3_out) -); -wire [1:0] magma_Bits_2_eq_inst4_in0; -assign magma_Bits_2_eq_inst4_in0 = {inst[1],inst[0]}; -PEGEN_coreir_eq #( - .width(2) -) magma_Bits_2_eq_inst4 ( - .in0(magma_Bits_2_eq_inst4_in0), - .in1(const_1_2_out), - .out(magma_Bits_2_eq_inst4_out) -); -wire [1:0] magma_Bits_2_eq_inst5_in0; -assign magma_Bits_2_eq_inst5_in0 = {inst[1],inst[0]}; -PEGEN_coreir_eq #( - .width(2) -) magma_Bits_2_eq_inst5 ( - .in0(magma_Bits_2_eq_inst5_in0), - .in1(const_0_2_out), - .out(magma_Bits_2_eq_inst5_out) -); -wire [1:0] magma_Bits_2_eq_inst6_in0; -assign magma_Bits_2_eq_inst6_in0 = {inst[1],inst[0]}; -PEGEN_coreir_eq #( - .width(2) -) magma_Bits_2_eq_inst6 ( - .in0(magma_Bits_2_eq_inst6_in0), - .in1(const_2_2_out), - .out(magma_Bits_2_eq_inst6_out) -); -assign O0 = Mux2xBits16_inst1_O; -assign O1 = Cond_inst0_O; -assign O2 = RegisterMode_inst0_O1; -assign O3 = RegisterMode_inst1_O1; -assign O4 = RegisterMode_inst2_O1; -endmodule - From ca670690465abd4c36ec46183a3cba8ee276bdc2 Mon Sep 17 00:00:00 2001 From: Bo Wun Cheng Date: Sat, 27 Jan 2024 00:57:58 -0800 Subject: [PATCH 13/18] updated parse_dot.py to support floating point ops --- sam/onyx/parse_dot.py | 78 ++++++++++++++++++++++++++++++++++++------- 1 file changed, 66 insertions(+), 12 deletions(-) diff --git a/sam/onyx/parse_dot.py b/sam/onyx/parse_dot.py index 73a61959..9cb7565c 100644 --- a/sam/onyx/parse_dot.py +++ b/sam/onyx/parse_dot.py @@ -6,6 +6,7 @@ import subprocess from hwtypes import BitVector from sam.onyx.hw_nodes.hw_node import HWNodeType +from lassen.utils import float2bfbin, bfbin2float class SAMDotGraphLoweringError(Exception): @@ -86,7 +87,6 @@ def get_mode_map(self): return self.remaining def generate_coreir_spec(self, context, attributes, name): - # FIXME: change this if we want operation with constant # Declare I/O of ALU module_typ = context.Record({"in0": context.Array(1, context.Array(16, context.BitIn())), "in1": context.Array(1, context.Array(16, context.BitIn())), @@ -99,48 +99,102 @@ def generate_coreir_spec(self, context, attributes, name): alu_op = "add" else: alu_op = attributes['type'].strip('"') - # import the desired operation from coreir, commonlib, or float_DW + # import the desired operation from coreir, commonlib, float_DW, or the float lib + # specify the width of the operations + # TODO: parameterize bit width + op = None + lib_name = None if alu_op in context.get_namespace("coreir").generators: coreir_op = context.get_namespace("coreir").generators[alu_op] + op = coreir_op(width=16) + lib_name = "coreir" elif alu_op in context.get_namespace("commonlib").generators: - coreir_op = context.get_namespace("commonlib").generators[alu_op] + commonlib_op = context.get_namespace("commonlib").generators[alu_op] + op = commonlib_op(width=16) + lib_name = "commonlib" elif alu_op in context.get_namespace("float_DW").generators: - coreir_op = context.get_namespace("flaot_DW").generators[alu_op] + float_DW_op = context.get_namespace("float_DW").generators[alu_op] + op = float_DW_op(exp_width=8, ieee_compliance=False, sig_width=7) + lib_name = "float_DW" + elif alu_op in context.get_namespace("float").generators: + float_op = context.get_namespace("float").genrators[alu_op] + op = float_op(exp_bits=8, frac_bits=7) + lib_name = "float" else: - raise NotImplementedError(f"fail to map node {alu_op} to compute") - # configure the width of the op - # FIXME: hardcoded to 16 for now - op = coreir_op(width=16) + # if the op is in none of the libs, it may be mapped using the custom rewrite rules + # in map_app.py + custom_rule_names = { + "mult_middle": "commonlib.mult_middle", + "abs": "commonlib.abs", + "fp_exp": "float.exp", + "fp_max": "float.max", + "fp_div": "float.div", + "fp_mux": "float.mux", + "fp_mul": "float_DW.fp_mul", + "fp_add": "float_DW.fp_add", + "fp_sub": "float.sub", + } + if alu_op in custom_rule_names: + custom_rule_lib = custom_rule_names[alu_op].split(".")[0] + custom_relu_op = custom_rule_names[alu_op].split(".")[1] + print(custom_rule_lib) + print(custom_relu_op) + custom_op = context.get_namespace(custom_rule_lib).generators[custom_relu_op] + op = custom_op(exp_bits=8, frac_bits=7) + print(op) + lib_name = custom_rule_lib + else: + raise NotImplementedError(f"fail to map node {alu_op} to compute") # add the operation instance to the module op_inst = module_def.add_module_instance(alu_op, op) # instantiate the constant operand instances, if any const_cnt = 0 const_inst = [] + # TODO: does any floating point use more then three inputs? for i in range(2): if f"const{i}" in attributes: const_cnt += 1 coreir_const = context.get_namespace("coreir").generators["const"] const = coreir_const(width=16) - const_value = int(attributes[f"const{i}"].strip('"')) + # constant string contains a decimal point, its a floating point constant + if ("." in attributes[f"const{i}"].strip('"')): + assert "fp" in alu_op, "only support floating point constant for fp ops" + const_value = float(attributes[f"const{i}"].strip('"')) + const_value = int(float2bfbin(const_value), 2) + else: + const_value = int(attributes[f"const{i}"].strip('"')) const_inst.append(module_def.add_module_instance(f"const{i}", const, context.new_values({"value": BitVector[16](const_value)}))) # connect the input to the op # connect module input to the non-constant alu input ports + # note that for ops in commonlib, coreir, and float, the input ports are `in0`, `in1`, `in2` + # and the output port is `out`. + # however, the inputs for ops in float_DW are a, b, c, and the output is z + float_DW_port_mapping = ['a', 'b', 'c'] for i in range(2 - const_cnt): _input = module_def.interface.select(f"in{i}").select("0") - _alu_in = op_inst.select(f"in{i}") + if lib_name != "float_DW": + _alu_in = op_inst.select(f"in{i}") + else: + _alu_in = op_inst.select(float_DW_port_mapping[i]) module_def.connect(_input, _alu_in) # connect constant output to alu input ports if const_cnt > 0: for i in range(const_cnt, 2): _const_out = const_inst[i - const_cnt].select("out") - _alu_in = op_inst.select(f"in{i}") + if lib_name != "float_DW": + _alu_in = op_inst.select(f"in{i}") + else: + _alu_in = op_inst.select(float_DW_port_mapping[i]) module_def.connect(_const_out, _alu_in) # connect alu output to module output _output = module_def.interface.select("out") - _alu_out = op_inst.select("out") + if lib_name != "float_DW": + _alu_out = op_inst.select("out") + else: + _alu_out = op_inst.select("z") module_def.connect(_output, _alu_out) module.definition = module_def assert module.definition is not None, "Should have a definitation by now" From a888fe5111db6ce515e3594b3076fcc395b7dcf0 Mon Sep 17 00:00:00 2001 From: Bo Wun Cheng Date: Thu, 1 Feb 2024 11:45:59 -0800 Subject: [PATCH 14/18] update the mat_elemadd_leakdy_relu graph to rely on metamapper to remap the complex op --- .../onyx-dot/mat_elemadd_leakyrelu_exp.gv | 19 +++---------------- 1 file changed, 3 insertions(+), 16 deletions(-) diff --git a/compiler/sam-outputs/onyx-dot/mat_elemadd_leakyrelu_exp.gv b/compiler/sam-outputs/onyx-dot/mat_elemadd_leakyrelu_exp.gv index aaad0587..e360afc4 100644 --- a/compiler/sam-outputs/onyx-dot/mat_elemadd_leakyrelu_exp.gv +++ b/compiler/sam-outputs/onyx-dot/mat_elemadd_leakyrelu_exp.gv @@ -9,15 +9,9 @@ digraph SAM { 4 [comment="type=arrayvals,tensor=B" label="Array Vals: B" color=green2 shape=box style=filled type="arrayvals" tensor="B"] 3 [comment="type=fp_add" label="FP_Add" color=brown shape=box style=filled type="fp_add"] 12 [comment="broadcast" shape=point style=invis type="broadcast"] - 13 [comment="type=fp_mul,rb_const=0.2" label="FP_Mul * 0.2" color=brown shape=box style=filled type="fp_mul" rb_const="0.2"] + 13 [comment="type=fp_mul,const0=0.2" label="FP_Mul * 0.2" color=brown shape=box style=filled type="fp_mul" const0="0.2"] 14 [comment="type=fp_max" label="FP_Max" color=brown shape=box style=filled type="fp_max"] - 15 [comment="type=fp_mul,rb_const=1.44269504089" label="FP_Mul * 1.44269504089" color=brown shape=box style=filled type="fp_mul" rb_const="1.44269504089"] - 16 [comment="type=broadcast" shape=point style=invis type="broadcast"] - 17 [comment="type=fgetfint" label="Fgetfint" color=brown shape=box style=filled type="fgetfint"] - 18 [comment="type=fgetffrac" label="Fgetffrac" color=brown shape=box style=filled type="fgetffrac"] - 19 [comment="type=and,rb_const=255" label="And 0x00FF" color=brown shape=box style=filled type="and" rb_const="255"] - 20 [comment="type=faddiexp" label="Faddiexp" color=brown shape=box style=filled type="faddiexp"] - 21 [comment="type=arrayvals,tensor=exp" label="Array Vals: exp" color=green2 shape=box style=filled type="arrayvals" tensor="exp"] + 15 [comment="type=exp" label="Exp" color=brown shape=box style=filled type="exp"] 0 [comment="type=fiberwrite,mode=vals,tensor=X,size=1*B0_dim*B1_dim,sink=true" label="FiberWrite Vals: X" color=green3 shape=box style=filled type="fiberwrite" tensor="X" mode="vals" size="1*B0_dim*B1_dim" sink="true"] 5 [comment="type=arrayvals,tensor=C" label="Array Vals: C" color=green2 shape=box style=filled type="arrayvals" tensor="C"] 8 [comment="type=fiberlookup,index=j,tensor=C,mode=1,format=compressed,src=true,root=false" label="FiberLookup j: C1\ncompressed" color=green4 shape=box style=filled type="fiberlookup" index="j" tensor="C" mode="1" format="compressed" src="true" root="false"] @@ -34,14 +28,7 @@ digraph SAM { 12 -> 14 [label="val" type="val"] 13 -> 14 [label="val" type="val"] 14 -> 15 [label="val" type="val"] - 15 -> 16 [label="val" type="val"] - 16 -> 17 [label="val" type="val"] - 16 -> 18 [label="val" type="val"] - 18 -> 19 [label="val" type="val"] - 19 -> 21 [label="ref" style=bold type="ref"] - 21 -> 20 [label="val" type="val" comment="fp"] - 17 -> 20 [label="val" type="val" comment="exp"] - 20 -> 0 [label="val" type="val"] + 15 -> 0 [label="val" type="val"] 6 -> 5 [label="ref_out-C" style=bold type="ref" comment="out-C"] 5 -> 3 [label="val" type="val"] 7 -> 6 [label="ref_in-B" style=bold type="ref" comment="in-B"] From 47df7394df4be2baa914f5891ee4c7318c207a0f Mon Sep 17 00:00:00 2001 From: Bo Wun Cheng Date: Thu, 1 Feb 2024 11:48:19 -0800 Subject: [PATCH 15/18] updated compute_node to support parsing opcode for remmapped complex op alus, also update the connection logic to allow destination port specification by metamapper --- sam/onyx/hw_nodes/compute_node.py | 98 ++++++++++++++------------ sam/onyx/hw_nodes/read_scanner_node.py | 34 ++++----- 2 files changed, 72 insertions(+), 60 deletions(-) diff --git a/sam/onyx/hw_nodes/compute_node.py b/sam/onyx/hw_nodes/compute_node.py index 622716f8..6b5a1b39 100644 --- a/sam/onyx/hw_nodes/compute_node.py +++ b/sam/onyx/hw_nodes/compute_node.py @@ -1,13 +1,11 @@ from sam.onyx.hw_nodes.hw_node import * from lassen.utils import float2bfbin -import coreir -import subprocess import json -import os class ComputeNode(HWNode): - def __init__(self, name=None, op=None, sam_graph_node_id=None, mapped_coreir_dir=None) -> None: + def __init__(self, name=None, op=None, sam_graph_node_id=None, + mapped_coreir_dir=None, is_mapped_from_complex_op=False, original_complex_op_id=None) -> None: super().__init__(name=name) self.num_inputs = 2 self.num_outputs = 1 @@ -18,8 +16,8 @@ def __init__(self, name=None, op=None, sam_graph_node_id=None, mapped_coreir_dir self.opcode = None self.mapped_coreir_dir = mapped_coreir_dir # parse the mapped coreir file to get the input ports and opcode - self.parse_mapped_json(self.mapped_coreir_dir + "/alu_coreir_spec_mapped.json", sam_graph_node_id) - assert len(self.mapped_input_ports) > 0 + self.parse_mapped_json(self.mapped_coreir_dir + "/alu_coreir_spec_mapped.json", + sam_graph_node_id, is_mapped_from_complex_op, original_complex_op_id) assert self.opcode is not None def connect(self, other, edge, kwargs=None): @@ -129,21 +127,23 @@ def connect(self, other, edge, kwargs=None): other_pe = other.get_name() other_conn = other.get_num_inputs() pe = self.get_name() - if 'Faddiexp' in other.op: - comment = edge.get_attributes()["comment"].strip('"') - if 'fp' in comment: - other_conn = 0 - elif 'exp' in comment: - other_conn = 1 - else: - assert 0 & "edge connected to faddiexp has to have comment specified to either 'exp' or 'fp'" + edge_attr = edge.get_attributes() + # a destination port name has been specified by metamapper + if "specified_port" in edge_attr and edge_attr["specified_port"] is not None: + other_conn = edge_attr["specified_port"] + other.mapped_input_ports.append(other_conn.strip("data")) + new_conns = { + f'pe_to_pe_{other_conn}': [ + ([(pe, "res"), (other_pe, f"{other_conn}")], 17), + ] + } else: other_conn = other.mapped_input_ports[other_conn] - new_conns = { - f'pe_to_pe_{other_conn}': [ - ([(pe, "res"), (other_pe, f"data{other_conn}")], 17), - ] - } + new_conns = { + f'pe_to_pe_{other_conn}': [ + ([(pe, "res"), (other_pe, f"data{other_conn}")], 17), + ] + } other.update_input_connections() return new_conns elif other_type == BroadcastNode: @@ -171,21 +171,44 @@ def update_input_connections(self): def get_num_inputs(self): return self.num_inputs_connected - def parse_mapped_json(self, filename, node_id): + def parse_mapped_json(self, filename, node_id, is_mapped_from_complex_op, original_complex_op_id): with open(filename, 'r') as alu_mapped_file: alu_mapped = json.load(alu_mapped_file) # parse out the mapped opcode - module = alu_mapped["namespaces"]["global"]["modules"]["ALU_" + node_id + "_mapped"] - opcode = module["instances"]["c0"]["modargs"]["value"][1] - opcode = "0x" + opcode.split('h')[1] - # parse out the mapped input ports - for connection in alu_mapped["namespaces"]["global"]["modules"]["ALU_" + node_id + "_mapped"]["connections"]: + alu_instance_name = None + module = None + if not is_mapped_from_complex_op: + module = alu_mapped["namespaces"]["global"]["modules"]["ALU_" + node_id + "_mapped"] + for instance_name, instance in module["instances"].items(): + if "modref" in instance and instance["modref"] == "global.PE": + alu_instance_name = instance_name + break + for connection in alu_mapped["namespaces"]["global"]["modules"]["ALU_" + node_id + "_mapped"]["connections"]: + port0, port1 = connection + if "self.in" in port0: + # get the port name of the alu + self.mapped_input_ports.append(port1.split(".")[1].strip("data")) + elif "self.in" in port1: + self.mapped_input_ports.append(port0.split(".")[1].strip("data")) + assert(len(self.mapped_input_ports) > 0) + else: + assert original_complex_op_id is not None + module = alu_mapped["namespaces"]["global"]["modules"]["ALU_" + original_complex_op_id + "_mapped"] + # node namae of a remapped alu node from a complex op is of the format _ + alu_instance_name = '_'.join(node_id.split("_")[0:-1]) + # no need to find the input and output port for remapped op + # as it is already assigned when we remap the complex op and stored in the edge object + # look for the constant coreir object that supplies the opcode to the alu at question + # insturction is supplied through the "inst" port of the alu + for connection in module["connections"]: port0, port1 = connection - if "self.in" in port0: - # get the port name of the alu - self.mapped_input_ports.append(port1.split(".")[1].strip("data")) - elif "self.in" in port1: - self.mapped_input_ports.append(port0.split(".")[1].strip("data")) + if f"{alu_instance_name}.inst" in port0: + constant_name = port1.split(".")[0] + elif f"{alu_instance_name}.inst" in port1: + constant_name = port0.split(".")[0] + opcode = module["instances"][constant_name]["modargs"]["value"][1] + opcode = "0x" + opcode.split('h')[1] + self.opcode = int(opcode, 0) def configure(self, attributes): @@ -208,24 +231,11 @@ def configure(self, attributes): print("".join(num_sparse_inputs)) num_sparse_inputs = int("".join(num_sparse_inputs), 2) - rb_const = None - if "rb_const" in attributes: - # the b operand of the op is a constant - rb_const = attributes["rb_const"].strip('"') - if "." in rb_const: - # constant is a floating point - rb_const = float(rb_const) - rb_const = int(float2bfbin(rb_const), 2) - else: - # it is a int - rb_const = int(rb_const) - cfg_kwargs = { 'op': self.opcode, 'use_dense': use_dense, 'pe_only': pe_only, 'pe_in_external': pe_in_external, - 'rb_const': rb_const, 'num_sparse_inputs': num_sparse_inputs } - return (op_code, use_dense, pe_only, pe_in_external, rb_const, num_sparse_inputs), cfg_kwargs + return (op_code, use_dense, pe_only, pe_in_external, num_sparse_inputs), cfg_kwargs diff --git a/sam/onyx/hw_nodes/read_scanner_node.py b/sam/onyx/hw_nodes/read_scanner_node.py index ebffe2c6..a57c2550 100644 --- a/sam/onyx/hw_nodes/read_scanner_node.py +++ b/sam/onyx/hw_nodes/read_scanner_node.py @@ -197,22 +197,24 @@ def connect(self, other, edge, kwargs=None): # Can use dynamic information to assign inputs to compute nodes # since add/mul are commutative compute_conn = other.get_num_inputs() - # TODO: get rid of this hack - if 'Faddiexp' in other.op: - comment = edge.get_attributes()["comment"].strip('"') - if 'fp' in comment: - compute_conn = 0 - elif 'exp' in comment: - compute_conn = 1 - else: - assert 0 & "edge connected to faddiexp has to have comment specified to either 'exp' or 'fp'" - new_conns = { - f'rd_scan_to_compute_{compute_conn}': [ - ([(rd_scan, "coord_out"), (compute, f"data{other.mapped_input_ports[compute_conn]}")], 17), - ] - } - # Now update the PE/compute to use the next connection next time - other.update_input_connections() + edge_attr = edge.get_attributes() + if "specified_port" in edge_attr and edge_attr["specified_port"] is not None: + compute_conn = edge_attr["specified_port"] + other.mapped_input_ports.append(compute_conn.strip("data")) + new_conns = { + f'rd_scan_to_compute_{compute_conn}': [ + ([(rd_scan, "coord_out"), (compute, f"{compute_conn}")], 17), + ] + } + else: + compute_conn = other.mapped_input_ports[compute_conn] + new_conns = { + f'rd_scan_to_compute_{compute_conn}': [ + ([(rd_scan, "coord_out"), (compute, f"data{compute_conn}")], 17), + ] + } + # Now update the PE/compute to use the next connection next time + other.update_input_connections() return new_conns From 7765100a719cfb770e238843b77988fa6e627099 Mon Sep 17 00:00:00 2001 From: Bo Wun Cheng Date: Thu, 1 Feb 2024 11:49:10 -0800 Subject: [PATCH 16/18] added support for remapping complex op using metamapper, now works for all apps in the regression, further cleanup WIP --- sam/onyx/parse_dot.py | 162 ++++++++++++++++++++++++++++++++++++++---- 1 file changed, 150 insertions(+), 12 deletions(-) diff --git a/sam/onyx/parse_dot.py b/sam/onyx/parse_dot.py index 9cb7565c..5d9aa52b 100644 --- a/sam/onyx/parse_dot.py +++ b/sam/onyx/parse_dot.py @@ -6,7 +6,8 @@ import subprocess from hwtypes import BitVector from sam.onyx.hw_nodes.hw_node import HWNodeType -from lassen.utils import float2bfbin, bfbin2float +from lassen.utils import float2bfbin +import json class SAMDotGraphLoweringError(Exception): @@ -56,6 +57,8 @@ def __init__(self, filename=None, local_mems=True, use_fork=False, self.rewrite_rsg_broadcast() self.map_nodes() self.map_alu() + if len(self.alu_nodes) > 0: + self.rewrite_complex_ops() def get_mode_map(self): sc = self.graph.get_comment().strip('"') @@ -94,11 +97,7 @@ def generate_coreir_spec(self, context, attributes, name): module = context.global_namespace.new_module("ALU_" + name, module_typ) assert module.definition is None, "Should not have a definition" module_def = module.new_definition() - # FIXME: hack for mapping reduce for now, fix reduce function to integer add - if attributes['type'].strip('"') == "reduce": - alu_op = "add" - else: - alu_op = attributes['type'].strip('"') + alu_op = attributes['type'].strip('"') # import the desired operation from coreir, commonlib, float_DW, or the float lib # specify the width of the operations # TODO: parameterize bit width @@ -117,7 +116,7 @@ def generate_coreir_spec(self, context, attributes, name): op = float_DW_op(exp_width=8, ieee_compliance=False, sig_width=7) lib_name = "float_DW" elif alu_op in context.get_namespace("float").generators: - float_op = context.get_namespace("float").genrators[alu_op] + float_op = context.get_namespace("float").generators[alu_op] op = float_op(exp_bits=8, frac_bits=7) lib_name = "float" else: @@ -137,11 +136,8 @@ def generate_coreir_spec(self, context, attributes, name): if alu_op in custom_rule_names: custom_rule_lib = custom_rule_names[alu_op].split(".")[0] custom_relu_op = custom_rule_names[alu_op].split(".")[1] - print(custom_rule_lib) - print(custom_relu_op) custom_op = context.get_namespace(custom_rule_lib).generators[custom_relu_op] op = custom_op(exp_bits=8, frac_bits=7) - print(op) lib_name = custom_rule_lib else: raise NotImplementedError(f"fail to map node {alu_op} to compute") @@ -176,7 +172,17 @@ def generate_coreir_spec(self, context, attributes, name): for i in range(2 - const_cnt): _input = module_def.interface.select(f"in{i}").select("0") if lib_name != "float_DW": - _alu_in = op_inst.select(f"in{i}") + try: + _alu_in = op_inst.select(f"in{i}") + except: + print(f"Cannot select port 'in{i}', fall back to using port 'in'") + # FIXME for now the only op that raise this exception is the single input + # op fp_exp + _alu_in = op_inst.select("in") + # connect the input and break to exit the loop since there're no more port + # to connect + module_def.connect(_input, _alu_in) + break else: _alu_in = op_inst.select(float_DW_port_mapping[i]) module_def.connect(_input, _alu_in) @@ -254,6 +260,10 @@ def map_alu(self): # in order to make sure the output comes out within the same cycle the input is given metamapper_env = os.environ.copy() metamapper_env["PIPELINED"] = "0" + # no need to peroform branch delay matching because we have rv interface in sparse + metamapper_env["PROVE"] = "0" + # FIXME: disable for now until verification of floating point computation is fixed + metamapper_env["MATCH_BRANCH_DELAY"] = "0" subprocess.run(["python", "/aha/MetaMapper/scripts/map_app.py", self.collat_dir + "/alu_coreir_spec.json"], env=metamapper_env) @@ -268,6 +278,130 @@ def find_node_by_name(self, name): return node assert False + def rewrite_complex_ops(self): + # parse the mapped json file, instantiate the compute/memory nodes generated by + # metamapper breaking down the complex op node + with open(self.collat_dir + "/alu_coreir_spec_mapped.json", 'r') as alu_mapped_file: + alu_mapped = json.load(alu_mapped_file) + # iterate through all the modules + modules_dict = alu_mapped["namespaces"]["global"]["modules"] + for node in self.alu_nodes: + module = modules_dict[f"ALU_{node.get_name()}_mapped"] + if len(module["instances"]) <= 3: + # for non complex op, each module contains three instances + # 1. the pe module itself + # 2. the coreir.const that supplies the op code + # 3. the coreir.const that supplies the clk_en signal + continue + complex_node_op = node.get_type().strip('"') + complex_node_label = node.get_label().strip('"') + incoming_edges = [edge for edge in self.graph.get_edges() if edge.get_destination() == node.get_name()] + outgoing_edges = [edge for edge in self.graph.get_edges() if edge.get_source() == node.get_name()] + # have more than three instances, it is a complex op + instances_dict = module["instances"] + instance_name_node_mappging = {} + for instance_name in instances_dict: + instance = instances_dict[instance_name] + # stamp out PEs and ROMs only, not the constant + if "modref" in instance and instance["modref"] == "global.PE": + # skip the bit constant PE that supplies ren data to the rom + # as the rom in sparse flow will use fiber access + if instance_name.split("_")[0] == "bit" and instance_name.split("_")[1] == "const": + continue + # the last two string of the instance name is the stance id, we only want the op + new_alu_node_op = '_'.join(instance_name.split("_")[0:-2]) + new_alu_node = pydot.Node(f"{instance_name}_{self.get_next_seq()}", + label=f"{complex_node_label}_{new_alu_node_op}", + hwnode=f"{HWNodeType.Compute}", + original_complex_op_id=node.get_name(), + is_mapped_from_complex_op=True, + type=f"{new_alu_node_op}", comment=f"type={new_alu_node_op}") + new_alu_node.create_attribute_methods(new_alu_node.get_attributes()) + self.graph.add_node(new_alu_node) + instance_name_node_mappging[instance_name] = new_alu_node + # create rom node using arrayvals + elif "genref" in instance and instance["genref"] == "memory.rom2": + attrs = {} + attrs["tensor"] = complex_node_op + rom_arrayvals_node = pydot.Node(f"{complex_node_op}_lut_{self.get_next_seq()}", + label=f"{complex_node_label}_lut", tensor=f"{complex_node_op}", + type="arrayvals", comment=f"type=arrayvals,tensor={complex_node_op}") + rom_arrayvals_node.create_attribute_methods(rom_arrayvals_node.get_attributes()) + self.graph.add_node(rom_arrayvals_node) + instance_name_node_mappging[instance_name] = rom_arrayvals_node + # connect the nodes + for connection in module["connections"]: + for i in range(2): + # the connection endpoint with 'datax', 'raddr', and 'self.out' is a connection to + # a PE, an arrayvals, or an original output of the complex op + if 'data0' in connection[i] or 'data1' in connection[i] or 'data2' in connection[i] or 'raddr' in connection[i] or 'self.out' in connection[i]: + edge_attr = {} + specified_port = None + edge_type = None + # internal connection within the complex op + if 'self.out' not in connection[i]: + dest_node_name = connection[i].split(".")[0] + dest_node = instance_name_node_mappging[dest_node_name] + # for internal conection we need to specify the edge type. + # for connection to arrayvals, the connection logic in hwnodes wil take + # care of the port name, no need to specify port name here + if dest_node.get_type() == "arrayvals": + edge_type = "ref" + specified_port = None + else: + edge_type = "val" + specified_port = connection[i].split(".")[1] + # FIXME: only support a single output complex op for now + # if it is an existing outgoing edge, inherit the edge properties + else: + dest_node = outgoing_edges[0].get_destination() + edge_attr = outgoing_edges[0].get_attributes() + self.graph.del_edge(outgoing_edges[0].get_source(), outgoing_edges[0].get_destination()) + + # select the other port as src + if i == 0: + src_port = connection[1] + else: + src_port = connection[0] + src_node_name = src_port.split(".")[0] + # if the src port is a node originally connects to the input of the complex op + # inherit the edge properties of that edge + if "self.in" in src_port: + # FIXME: only support a single input complex op for now + src_node = incoming_edges[0].get_source() + # an edge connot be a incoming to and outgoing from the complex op simultaneously + assert not edge_attr + edge_attr = incoming_edges[0].get_attributes() + # connecting to a new node, use the port specified by metamapper + self.graph.del_edge(incoming_edges[0].get_source(), incoming_edges[0].get_destination()) + # the srouce node is not a PE we just stamp out, skip the connection + elif src_node_name not in instance_name_node_mappging: + break + else: + src_node = instance_name_node_mappging[src_node_name] + # a new edge + if not edge_attr: + new_edge = pydot.Edge(src=src_node, + dst=dest_node, + type=edge_type, + label=edge_type, + specified_port=specified_port, + comment=edge_type) + # existing edge, inherit its attributes + else: + new_edge = pydot.Edge(src=src_node, + dst=dest_node, + **edge_attr, + specified_port=specified_port) + + self.graph.add_edge(new_edge) + # done adding the edge for the connection, don't need to check the other port + break + # finally remove the original complex op node + self.graph.del_node(node) + # turn the lut arrayvals into FA + self.rewrite_arrays() + def rewrite_VectorReducer(self): # Get the vr node and the resulting fiberwrites @@ -994,7 +1128,11 @@ def rewrite_arrays(self): ''' Rewrites the array nodes to become (lookup, buffet) triples ''' - nodes_to_proc = [node for node in self.graph.get_nodes() if 'arrayvals' in node.get_comment()] + # nodes_to_proc = [node for node in self.graph.get_nodes() if 'arrayvals' in node.get_comment()] + nodes_to_proc = [] + for node in self.graph.get_nodes(): + if 'arrayvals' in node.get_comment() and 'hwnode' not in node.get_attributes(): + nodes_to_proc.append(node) for node in nodes_to_proc: # Now we have arrayvals, let's turn it into same stuff # Rewrite this node to a read From 6242c3ae15d6c0340ec326cfb9ab7b21eb65bde8 Mon Sep 17 00:00:00 2001 From: Bo Wun Cheng Date: Thu, 1 Feb 2024 12:01:35 -0800 Subject: [PATCH 17/18] fix codestyle --- sam/onyx/hw_nodes/compute_node.py | 8 +++--- sam/onyx/hw_nodes/read_scanner_node.py | 2 +- sam/onyx/parse_dot.py | 37 +++++++++++++------------- 3 files changed, 24 insertions(+), 23 deletions(-) diff --git a/sam/onyx/hw_nodes/compute_node.py b/sam/onyx/hw_nodes/compute_node.py index 6b5a1b39..0d75db36 100644 --- a/sam/onyx/hw_nodes/compute_node.py +++ b/sam/onyx/hw_nodes/compute_node.py @@ -4,7 +4,7 @@ class ComputeNode(HWNode): - def __init__(self, name=None, op=None, sam_graph_node_id=None, + def __init__(self, name=None, op=None, sam_graph_node_id=None, mapped_coreir_dir=None, is_mapped_from_complex_op=False, original_complex_op_id=None) -> None: super().__init__(name=name) self.num_inputs = 2 @@ -16,7 +16,7 @@ def __init__(self, name=None, op=None, sam_graph_node_id=None, self.opcode = None self.mapped_coreir_dir = mapped_coreir_dir # parse the mapped coreir file to get the input ports and opcode - self.parse_mapped_json(self.mapped_coreir_dir + "/alu_coreir_spec_mapped.json", + self.parse_mapped_json(self.mapped_coreir_dir + "/alu_coreir_spec_mapped.json", sam_graph_node_id, is_mapped_from_complex_op, original_complex_op_id) assert self.opcode is not None @@ -191,11 +191,11 @@ def parse_mapped_json(self, filename, node_id, is_mapped_from_complex_op, origin elif "self.in" in port1: self.mapped_input_ports.append(port0.split(".")[1].strip("data")) assert(len(self.mapped_input_ports) > 0) - else: + else: assert original_complex_op_id is not None module = alu_mapped["namespaces"]["global"]["modules"]["ALU_" + original_complex_op_id + "_mapped"] # node namae of a remapped alu node from a complex op is of the format _ - alu_instance_name = '_'.join(node_id.split("_")[0:-1]) + alu_instance_name = '_'.join(node_id.split("_")[0:-1]) # no need to find the input and output port for remapped op # as it is already assigned when we remap the complex op and stored in the edge object # look for the constant coreir object that supplies the opcode to the alu at question diff --git a/sam/onyx/hw_nodes/read_scanner_node.py b/sam/onyx/hw_nodes/read_scanner_node.py index a57c2550..3a952a35 100644 --- a/sam/onyx/hw_nodes/read_scanner_node.py +++ b/sam/onyx/hw_nodes/read_scanner_node.py @@ -205,7 +205,7 @@ def connect(self, other, edge, kwargs=None): f'rd_scan_to_compute_{compute_conn}': [ ([(rd_scan, "coord_out"), (compute, f"{compute_conn}")], 17), ] - } + } else: compute_conn = other.mapped_input_ports[compute_conn] new_conns = { diff --git a/sam/onyx/parse_dot.py b/sam/onyx/parse_dot.py index 5d9aa52b..7e40fa5f 100644 --- a/sam/onyx/parse_dot.py +++ b/sam/onyx/parse_dot.py @@ -167,19 +167,19 @@ def generate_coreir_spec(self, context, attributes, name): # connect module input to the non-constant alu input ports # note that for ops in commonlib, coreir, and float, the input ports are `in0`, `in1`, `in2` # and the output port is `out`. - # however, the inputs for ops in float_DW are a, b, c, and the output is z + # however, the inputs for ops in float_DW are a, b, c, and the output is z float_DW_port_mapping = ['a', 'b', 'c'] for i in range(2 - const_cnt): _input = module_def.interface.select(f"in{i}").select("0") if lib_name != "float_DW": try: _alu_in = op_inst.select(f"in{i}") - except: + except Exception: print(f"Cannot select port 'in{i}', fall back to using port 'in'") - # FIXME for now the only op that raise this exception is the single input + # FIXME for now the only op that raise this exception is the single input # op fp_exp _alu_in = op_inst.select("in") - # connect the input and break to exit the loop since there're no more port + # connect the input and break to exit the loop since there're no more port # to connect module_def.connect(_input, _alu_in) break @@ -304,14 +304,14 @@ def rewrite_complex_ops(self): instance = instances_dict[instance_name] # stamp out PEs and ROMs only, not the constant if "modref" in instance and instance["modref"] == "global.PE": - # skip the bit constant PE that supplies ren data to the rom + # skip the bit constant PE that supplies ren data to the rom # as the rom in sparse flow will use fiber access if instance_name.split("_")[0] == "bit" and instance_name.split("_")[1] == "const": continue # the last two string of the instance name is the stance id, we only want the op new_alu_node_op = '_'.join(instance_name.split("_")[0:-2]) - new_alu_node = pydot.Node(f"{instance_name}_{self.get_next_seq()}", - label=f"{complex_node_label}_{new_alu_node_op}", + new_alu_node = pydot.Node(f"{instance_name}_{self.get_next_seq()}", + label=f"{complex_node_label}_{new_alu_node_op}", hwnode=f"{HWNodeType.Compute}", original_complex_op_id=node.get_name(), is_mapped_from_complex_op=True, @@ -323,7 +323,7 @@ def rewrite_complex_ops(self): elif "genref" in instance and instance["genref"] == "memory.rom2": attrs = {} attrs["tensor"] = complex_node_op - rom_arrayvals_node = pydot.Node(f"{complex_node_op}_lut_{self.get_next_seq()}", + rom_arrayvals_node = pydot.Node(f"{complex_node_op}_lut_{self.get_next_seq()}", label=f"{complex_node_label}_lut", tensor=f"{complex_node_op}", type="arrayvals", comment=f"type=arrayvals,tensor={complex_node_op}") rom_arrayvals_node.create_attribute_methods(rom_arrayvals_node.get_attributes()) @@ -332,9 +332,10 @@ def rewrite_complex_ops(self): # connect the nodes for connection in module["connections"]: for i in range(2): - # the connection endpoint with 'datax', 'raddr', and 'self.out' is a connection to + # the connection endpoint with 'datax', 'raddr', and 'self.out' is a connection to # a PE, an arrayvals, or an original output of the complex op - if 'data0' in connection[i] or 'data1' in connection[i] or 'data2' in connection[i] or 'raddr' in connection[i] or 'self.out' in connection[i]: + if 'data0' in connection[i] or 'data1' in connection[i] or 'data2' in connection[i] \ + or 'raddr' in connection[i] or 'self.out' in connection[i]: edge_attr = {} specified_port = None edge_type = None @@ -343,7 +344,7 @@ def rewrite_complex_ops(self): dest_node_name = connection[i].split(".")[0] dest_node = instance_name_node_mappging[dest_node_name] # for internal conection we need to specify the edge type. - # for connection to arrayvals, the connection logic in hwnodes wil take + # for connection to arrayvals, the connection logic in hwnodes wil take # care of the port name, no need to specify port name here if dest_node.get_type() == "arrayvals": edge_type = "ref" @@ -357,7 +358,7 @@ def rewrite_complex_ops(self): dest_node = outgoing_edges[0].get_destination() edge_attr = outgoing_edges[0].get_attributes() self.graph.del_edge(outgoing_edges[0].get_source(), outgoing_edges[0].get_destination()) - + # select the other port as src if i == 0: src_port = connection[1] @@ -377,13 +378,13 @@ def rewrite_complex_ops(self): # the srouce node is not a PE we just stamp out, skip the connection elif src_node_name not in instance_name_node_mappging: break - else: + else: src_node = instance_name_node_mappging[src_node_name] # a new edge if not edge_attr: - new_edge = pydot.Edge(src=src_node, - dst=dest_node, - type=edge_type, + new_edge = pydot.Edge(src=src_node, + dst=dest_node, + type=edge_type, label=edge_type, specified_port=specified_port, comment=edge_type) @@ -399,8 +400,8 @@ def rewrite_complex_ops(self): break # finally remove the original complex op node self.graph.del_node(node) - # turn the lut arrayvals into FA - self.rewrite_arrays() + # turn the lut arrayvals into FA + self.rewrite_arrays() def rewrite_VectorReducer(self): From d76c95fa95c72a7ecb96c1a501a46b9de9ba42ba Mon Sep 17 00:00:00 2001 From: Bo Wun Cheng Date: Thu, 1 Feb 2024 12:48:31 -0800 Subject: [PATCH 18/18] fix style again --- sam/onyx/hw_nodes/compute_node.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sam/onyx/hw_nodes/compute_node.py b/sam/onyx/hw_nodes/compute_node.py index 0d75db36..0107ff83 100644 --- a/sam/onyx/hw_nodes/compute_node.py +++ b/sam/onyx/hw_nodes/compute_node.py @@ -190,7 +190,7 @@ def parse_mapped_json(self, filename, node_id, is_mapped_from_complex_op, origin self.mapped_input_ports.append(port1.split(".")[1].strip("data")) elif "self.in" in port1: self.mapped_input_ports.append(port0.split(".")[1].strip("data")) - assert(len(self.mapped_input_ports) > 0) + assert (len(self.mapped_input_ports) > 0) else: assert original_complex_op_id is not None module = alu_mapped["namespaces"]["global"]["modules"]["ALU_" + original_complex_op_id + "_mapped"]