diff --git a/.assets/tn9k.png b/.assets/tn9k.png new file mode 100644 index 0000000..9b78a2e Binary files /dev/null and b/.assets/tn9k.png differ diff --git a/.assets/vic20_tn9k_rework.png b/.assets/vic20_tn9k_rework.png new file mode 100644 index 0000000..98b7632 Binary files /dev/null and b/.assets/vic20_tn9k_rework.png differ diff --git a/.assets/vic20_tn9k_rework.svg b/.assets/vic20_tn9k_rework.svg new file mode 100644 index 0000000..9ffec7d --- /dev/null +++ b/.assets/vic20_tn9k_rework.svg @@ -0,0 +1,2087 @@ + + + +pin 1pin 49pin 48pin 8SD Data 2SD Data 1 diff --git a/.assets/vic20_tn9k_top.svg b/.assets/vic20_tn9k_top.svg new file mode 100644 index 0000000..3b071d9 --- /dev/null +++ b/.assets/vic20_tn9k_top.svg @@ -0,0 +1,561 @@ + + + ++5VGNDMISOMOSICSNSCKIRQ+5VGNDIO10IO11IO12IO13IO14SPIM0SDockMIDI INMIDI OUTDualshock_GNDDualshock_3V3Dualshock_CSDualshock_MISODualshock_MOSIDualshock_MCLKBTN0DOWNUPRIGHTLEFTJoystickBTN0DOWNUPRIGHTLEFTLEDfirmwarestatusJoystickOSD hotkey:F12Reset /Flash diff --git a/INSTALLATION_WINDOWS.md b/INSTALLATION_WINDOWS.md index 08fd4dc..53092cf 100644 --- a/INSTALLATION_WINDOWS.md +++ b/INSTALLATION_WINDOWS.md @@ -63,9 +63,12 @@ should see following screen:** | Type | TN20k | TP20k |TP25k | TM138k |TM60k | | | FPGA bitstream | 0x000000 | 0x000000 | 0x000000 | 0x000000 |0x000000|ROM size | +For the TN9k there might be an older version of the programmer SW be needed. + **shell / command line Programming alternative** Windows shell and Gowin Programmer
+```programmer_cli -r 36 --fsFile a2600nano_tn9k.fs --cable-index 1 --d GW1NR-9C```
```programmer_cli -r 36 --fsFile a2600nano_tn20k.fs --spiaddr 0x000000 --cable-index 1 --d GW2AR-18C```
```programmer_cli -r 36 --fsFile a2600nano_tp20k.fs --spiaddr 0x000000 --cable-index 1 --d GW2A-18C```
```programmer_cli -r 36 --fsFile a2600nano_tp25k.fs --spiaddr 0x000000 --cable-index 1 --d GW5A-25A```
diff --git a/README.md b/README.md index c44e9b3..c941b4b 100644 --- a/README.md +++ b/README.md @@ -3,6 +3,7 @@ The A2600Nano is a port of the [MiSTer](https://github.com/MiSTer-devel/Atari260 | Board | FPGA | support |Note| | --- | - | - |-| +| [Tang Nano 9k](https://wiki.sipeed.com/hardware/en/tang/Tang-Nano-9K/Nano-9K.html) | [GW1NR](https://www.gowinsemi.com/en/product/detail/38/) |X |micro SD card [HW modification](TANG_NANO_9K.md#hw-modification) needed| | [Tang Nano 20k](https://wiki.sipeed.com/nano20k) | [GW2AR](https://www.gowinsemi.com/en/product/detail/38/) | X |- | | [Tang Primer 20K Dock ext Board](https://wiki.sipeed.com/hardware/en/tang/tang-primer-20k/primer-20k.html)| [GW2A](https://www.gowinsemi.com/en/product/detail/46/)| X |double Dualshock | | [Tang Primer 25K](https://wiki.sipeed.com/hardware/en/tang/tang-primer-25k/primer-25k.html) | [GW5A-25](https://www.gowinsemi.com/en/product/detail/60/) | X |no Dualshock, no retro D9 Joystick | @@ -46,6 +47,9 @@ Planned features: HID interfaces aligned in pinmap and control to match [FPGA-Companion](https://github.com/harbaum/FPGA-Companion).
Basically a µC M0S/BL616 / Raspberry Pi Pico RP2040 / ESP32-S2/S3 acts as USB host for USB devices and as an OSD controller using a [SPI communication protocol](https://github.com/harbaum/MiSTeryNano/blob/main/SPI.md).
+## A2600Nano on Tang Nano 9K +See [Tang Nano 9K](TANG_NANO_9K.md) + ## A2600Nano on Tang Primer 20K (Dock ext board) See [Tang Primer 20K](TANG_PRIMER_20K.md)
@@ -152,8 +156,8 @@ You have first to set the DS2 Sticks into analog mode by pressing the DS2 ANALOG | LED | function | TN20K | TP20K | TP25K | TM60K |TM138k| | --- | - | - |- | - | - | - | -| 0 |Cartridge selected| x |- | x | x | x | -| 1 | reserved | x |x | unsup | x |unsup| +| 0 |Cartridge selected| x |x | x | x | x | +| 1 | reserved | x |x | x | x | x | | 2 | Game unsupported | x |x | - | x | - | | 3 | Game unsupported | x |x | - | x | - | | 4 | Game unsupported | x |x | - | x | - | diff --git a/TANG_NANO_9K.md b/TANG_NANO_9K.md new file mode 100644 index 0000000..63b415e --- /dev/null +++ b/TANG_NANO_9K.md @@ -0,0 +1,67 @@ +# A2600Nano on Tang Nano 9K + +A2600Nano can be used in the [Tang Nano 9k](https://wiki.sipeed.com/hardware/en/tang/Tang-Nano-9K/Nano-9K.html). + +The whole setup will look like this:
+![A2600Nano on TN9K](./.assets/tn9k.png) + + +**D9 retro Joystick Interface** + +|Bus|Signal| D9 |TN9k pin| FPGA Signal | +| - |------|-------------------|-|-------| +| 0 | Trigger | - |27| Trigger | +| 1 | Down | - |28| Down | +| 2 | Up | - |25| Up | +| 3 | Right | - |26 | Right | +| 4 | Left | - |29 | Left | +| - | GND | - |GND | GND | + +**Pinmap Dualshock 2 Controller Interface**
+image +| DS pin | TN9 pin | Signal | DS Function | +| ----------- | --- | -------- | ----- | +| 1 | 54 | MISO | JOYDAT | +| 2 | 53 | MOSI | JOYCMD | +| 3 | n.c. | - | 7V5 | +| 4 | | GND | GND | +| 5 | | 3V3 | 3V3 | +| 6 | 55 | CS | JOYATN| +| 7 | 51 | MCLK | JOYCLK | +| 8 | n.c. | - | JOYIRQ | +| 9 | n.c. | - | JOYACK | + +**M0S Dock BL616 µC** + +|Bus|M0S Signal|M0S Pin|TN9k pin | Signal | +| - |------ |-------------------|-------------------|--------------------------------------| +| - | +5V | +5V | 5V | 5V | +| - | +3V3 | +3V3 | n.c | don't connect ! | +| - | GND | GND | GND | GND | +| - | GND | GND | GND | GND | +| 5 | - | - | 41 | don't connect | +| 4 | IRQn | GPIO14 | 35 | Interrupt from FPGA to MCU| +| 3 | SCK | GPIO13 | 40 | SPI clock, idle low | +| 2 | CSn | GPIO12 | 34 | SPI select, active low | +| 1 | MOSI | GPIO11 | 33 | SPI data from MCU to FPGA | +| 0 | MISO | GPIO10 | 30 | SPI data from FPGA to MCU | + + +On the software side the setup is very simuilar to the original Tang Nano 20K based solution. The core needs to be built specifically +for the different FPGA of the Tang Primer using either the [TCL script with the GoWin command line interface](build_tn9k.tcl) or the +[project file for the graphical GoWin IDE](vic20nano_tn9k.gprj). The resulting bitstream is flashed to the TN9K as usual. + +You might need to use an older version of the Gowin Programmer [SW](https://dl.sipeed.com/shareURL/TANG/programmer) for the GW1NR device.
+```programmer_cli -r 38 --mcuFile 32k.bin --spiaddr 0x000000 --cable-index 1 --d GW1NR-9C``` + +And also the firmware for the M0S Dock is the [same version as for +the Tang Nano 20K](https://github.com/harbaum/MiSTeryNano/tree/main/firmware/misterynano_fw/). + +# HW modification + +Mandatory HW modification TN9K needed to fully support micro SD Card in 4bit data transfer mode.
+Rework place with Soldering Iron and a Microscope or magnifying glass needed.
+- **SD Card Data 1**
Wire SD card holder SD_dat1 pin 8 to TN9k FPGA pin 48. SPI LCD interface will be blocked by that.
+- **SD Card Data 2**
Wire SD card holder SD_dat2 pin 1 to TN9k FPGA pin 49. SPI LCD interface will be blocked by that.
+ +![TN9K rework](./.assets/vic20_tn9k_rework.png) \ No newline at end of file diff --git a/a2600nano_tn9k.gprj b/a2600nano_tn9k.gprj new file mode 100644 index 0000000..b9eb1b9 --- /dev/null +++ b/a2600nano_tn9k.gprj @@ -0,0 +1,53 @@ + + + + + 5 + gw1nr9c-004 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/build_all.bat b/build_all.bat new file mode 100644 index 0000000..9842482 --- /dev/null +++ b/build_all.bat @@ -0,0 +1,32 @@ + +@echo off +set GWSH=C:\Gowin\Gowin_V1.9.10.03_x64\IDE\bin\gw_sh + +echo. +echo ============ build mega138k pro =============== +echo. +%GWSH% build_tm138k_pro.tcl +echo. +echo ============ build mega 60k =============== +echo. +%GWSH% build_tm60k.tcl +echo. +echo ============ build primer 25k =============== +echo. +%GWSH% build_tp25k.tcl +echo. +echo ============ build nano 20k =============== +echo. +%GWSH% build_tn20k.tcl +echo. +echo ============ build primer 20k =============== +echo. +%GWSH% build_tp20k.tcl +echo. +echo ============ build nano 9k =============== +echo. +%GWSH% build_tn9k.tcl + +echo "done." +dir impl\pnr\*.fs + diff --git a/build_all.sh b/build_all.sh new file mode 100644 index 0000000..93b8449 --- /dev/null +++ b/build_all.sh @@ -0,0 +1,10 @@ +#!/bin/bash + +rm -f impl/pnr/*.fs + +grc --config=gw_sh.grc gw_sh ./build_tm138k_pro.tcl +grc --config=gw_sh.grc gw_sh ./build_tm60k.tcl +grc --config=gw_sh.grc gw_sh ./build_tp25k.tcl +grc --config=gw_sh.grc gw_sh ./build_tn20k.tcl +grc --config=gw_sh.grc gw_sh ./build_tp20k.tcl +grc --config=gw_sh.grc gw_sh ./build_tn9k.tcl diff --git a/build_tn9k.tcl b/build_tn9k.tcl new file mode 100644 index 0000000..0421175 --- /dev/null +++ b/build_tn9k.tcl @@ -0,0 +1,61 @@ +set_device GW1NR-LV9QN88PC6/I5 -name GW1NR-9C + +add_file src/dualshock2.v +add_file src/gowin_dpb/gowin_dpb_track_buffer_b.v +add_file src/gowin_dpb/sector_dpram.v +add_file src/hdmi/audio_clock_regeneration_packet.sv +add_file src/hdmi/audio_info_frame.sv +add_file src/hdmi/audio_sample_packet.sv +add_file src/hdmi/auxiliary_video_information_info_frame.sv +add_file src/hdmi/hdmi.sv +add_file src/hdmi/packet_assembler.sv +add_file src/hdmi/packet_picker.sv +add_file src/hdmi/serializer.sv +add_file src/hdmi/source_product_description_info_frame.sv +add_file src/hdmi/tmds_channel.sv +add_file src/misc/hid.v +add_file src/misc/mcu_spi.v +add_file src/misc/osd_u8g2.v +add_file src/misc/scandoubler.v +add_file src/misc/sd_card.v +add_file src/misc/sd_rw.v +add_file src/misc/sdcmd_ctrl.v +add_file src/misc/sysctrl.v +add_file src/misc/video.v +add_file src/misc/video_analyzer.v +add_file src/misc/ws2812.v +add_file src/t65/T65.vhd +add_file src/t65/T65_ALU.vhd +add_file src/t65/T65_MCode.vhd +add_file src/t65/T65_Pack.vhd +add_file src/loader_sd_card.sv +add_file src/A2601Core.vhd +add_file src/A2601top.vhd +add_file src/A6507.vhd +add_file src/A6532.vhd +add_file src/TIA/Common.vhd +add_file src/TIA/NTSCLookups.vhd +add_file src/TIA/TIA.vhd +add_file src/TIA/VGAColorTable.vhd +add_file src/TIA/audio_argh2600.vhd +add_file src/gowin_sdpb/gowin_sdpb_tn9k.vhd +add_file src/a2600_top_tn9k.vhd +add_file src/a2600_top_tn9k.cst +add_file src/a2600_top_tn9k.sdc +add_file src/video_stabilize.sv +add_file src/detect2600.sv + +set_option -synthesis_tool gowinsynthesis +set_option -output_base_name a2600nano_tn9k +set_option -verilog_std sysv2017 +set_option -vhdl_std vhd2008 +set_option -top_module A2600_top +set_option -use_mspi_as_gpio 1 +set_option -use_sspi_as_gpio 1 +set_option -print_all_synthesis_warning 1 +set_option -rw_check_on_ram 0 +set_option -user_code 00000001 +set_option -bit_security 0 + +#run syn +run all diff --git a/gw_sh.grc b/gw_sh.grc new file mode 100644 index 0000000..094c3cc --- /dev/null +++ b/gw_sh.grc @@ -0,0 +1,11 @@ +# NOTE lines +regexp=^NOTE.* +colour=green +- +# WARNing lines +regexp=^WARN.* +colour=yellow +- +# ERROR lines +regexp=^ERROR.* +colour=red diff --git a/impl/a2600nano_tn9k_process_config.json b/impl/a2600nano_tn9k_process_config.json new file mode 100644 index 0000000..ff85b98 --- /dev/null +++ b/impl/a2600nano_tn9k_process_config.json @@ -0,0 +1,92 @@ +{ + "BACKGROUND_PROGRAMMING" : "off", + "COMPRESS" : false, + "CPU" : false, + "CRC_CHECK" : true, + "Clock_Route_Order" : 0, + "Convert_SDP32_36_to_SDP16_18" : true, + "Correct_Hold_Violation" : true, + "DONE" : true, + "DOWNLOAD_SPEED" : "default", + "Disable_Insert_Pad" : false, + "ENABLE_CTP" : false, + "ENABLE_MERGE_MODE" : false, + "ENCRYPTION_KEY" : false, + "ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000", + "ERROR_DECTION_AND_CORRECTION" : false, + "ERROR_DECTION_ONLY" : false, + "ERROR_INJECTION" : false, + "EXTERNAL_MASTER_CONFIG_CLOCK" : false, + "Enable_DSRM" : false, + "FORMAT" : "binary", + "FREQUENCY_DIVIDER" : "", + "Generate_Constraint_File_of_Ports" : false, + "Generate_IBIS_File" : false, + "Generate_Plain_Text_Timing_Report" : false, + "Generate_Post_PNR_Simulation_Model_File" : false, + "Generate_Post_Place_File" : false, + "Generate_SDF_File" : false, + "Generate_VHDL_Post_PNR_Simulation_Model_File" : false, + "Global_Freq" : "default", + "GwSyn_Loop_Limit" : 2000, + "HOTBOOT" : false, + "I2C" : false, + "I2C_SLAVE_ADDR" : "00", + "INCREMENTAL_PLACE_AND_ROUTING" : "0", + "INCREMENTAL_PLACE_ONLY" : "0", + "IncludePath" : [ + + ], + "Incremental_Compile" : "", + "Initialize_Primitives" : false, + "JTAG" : false, + "MODE_IO" : false, + "MSPI" : true, + "MSPI_JUMP" : false, + "MULTIBOOT_ADDRESS_WIDTH" : "24", + "MULTIBOOT_MODE" : "Normal", + "MULTIBOOT_SPI_FLASH_ADDRESS" : "00000000", + "MULTIJUMP_ADDRESS_WIDTH" : "24", + "MULTIJUMP_MODE" : "Normal", + "MULTIJUMP_SPI_FLASH_ADDRESS" : "000000", + "Multi_Boot" : false, + "OUTPUT_BASE_NAME" : "a2600nano_tn9k", + "POWER_ON_RESET_MONITOR" : true, + "PRINT_BSRAM_VALUE" : false, + "PROGRAM_DONE_BYPASS" : false, + "PlaceInRegToIob" : true, + "PlaceIoRegToIob" : true, + "PlaceOutRegToIob" : true, + "Place_Option" : "0", + "Process_Configuration_Verion" : "1.0", + "Promote_Physical_Constraint_Warning_to_Error" : true, + "READY" : true, + "RECONFIG_N" : false, + "Ram_RW_Check" : false, + "Replicate_Resources" : false, + "Report_Auto-Placed_Io_Information" : false, + "Route_Maxfan" : 23, + "Route_Option" : "0", + "Run_Timing_Driven" : true, + "SECURE_MODE" : false, + "SECURITY_BIT" : true, + "SEU_HANDLER" : false, + "SEU_HANDLER_CHECKSUM" : false, + "SEU_HANDLER_MODE" : "auto", + "SSPI" : true, + "STOP_SEU_HANDLER" : false, + "Show_All_Warnings" : false, + "Synthesize_tool" : "GowinSyn", + "TclPre" : "", + "TopModule" : "A2600_top", + "USERCODE" : "00000001", + "Unused_Pin" : "As_input_tri_stated_with_pull_up", + "VCC" : "1.2", + "VCCAUX" : 3.3, + "VCCX" : "3.3", + "VHDL_Standard" : "VHDL_Std_2008", + "Verilog_Standard" : "Vlg_Std_Sysv2017", + "WAKE_UP" : "0", + "show_all_warnings" : true, + "turn_off_bg" : false +} \ No newline at end of file diff --git a/src/a2600_top_tn9k.cst b/src/a2600_top_tn9k.cst new file mode 100644 index 0000000..3cc5bbd --- /dev/null +++ b/src/a2600_top_tn9k.cst @@ -0,0 +1,111 @@ +// HDMI +IO_LOC "tmds_clk_p" 69,68; +IO_PORT "tmds_clk_p" PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3; +IO_LOC "tmds_d_p[0]" 71,70; +IO_PORT "tmds_d_p[0]" PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3; +IO_LOC "tmds_d_p[1]" 73,72; +IO_PORT "tmds_d_p[1]" PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3; +IO_LOC "tmds_d_p[2]" 75,74; +IO_PORT "tmds_d_p[2]" PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3; + +IO_LOC "leds_n[5]" 16; +IO_PORT "leds_n[5]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8; +IO_LOC "leds_n[4]" 15; +IO_PORT "leds_n[4]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8; +IO_LOC "leds_n[3]" 14; +IO_PORT "leds_n[3]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8; +IO_LOC "leds_n[2]" 13; +IO_PORT "leds_n[2]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8; +IO_LOC "leds_n[1]" 11; +IO_PORT "leds_n[1]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8; +IO_LOC "leds_n[0]" 10; +IO_PORT "leds_n[0]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8; + +IO_LOC "reset" 4; +IO_PORT "reset" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8; +IO_LOC "user" 3; +IO_PORT "user" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8; +IO_LOC "clk_27mhz" 52; +IO_PORT "clk_27mhz" IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3; + +// connection to the external BL616/M0S +IO_LOC "m0s[0]" 30; // MISO +IO_PORT "m0s[0]" PULL_MODE=UP IO_TYPE=LVCMOS33; +IO_LOC "m0s[1]" 33; // MOSI +IO_PORT "m0s[1]" PULL_MODE=UP IO_TYPE=LVCMOS33; +IO_LOC "m0s[2]" 34; // CSn +IO_PORT "m0s[2]" PULL_MODE=UP IO_TYPE=LVCMOS33; +IO_LOC "m0s[3]" 40; // CLK +IO_PORT "m0s[3]" PULL_MODE=UP IO_TYPE=LVCMOS33; +IO_LOC "m0s[4]" 35; // IRQn +IO_PORT "m0s[4]" PULL_MODE=UP IO_TYPE=LVCMOS33; +//IO_LOC "m0s[5]" 41; // +//IO_PORT "m0s[5]" PULL_MODE=UP IO_TYPE=LVCMOS33; + +// digital retro Joystick +// 0 TR +// 1 DN +// 2 UP +// 3 RI +// 4 LE +IO_LOC "io[0]" 27; +IO_PORT "io[0]" PULL_MODE=UP IO_TYPE=LVCMOS33; +IO_LOC "io[1]" 28; +IO_PORT "io[1]" PULL_MODE=UP IO_TYPE=LVCMOS33; +IO_LOC "io[2]" 25; +IO_PORT "io[2]" PULL_MODE=UP IO_TYPE=LVCMOS33; +IO_LOC "io[3]" 26; +IO_PORT "io[3]" PULL_MODE=UP IO_TYPE=LVCMOS33; +IO_LOC "io[4]" 29; +IO_PORT "io[4]" PULL_MODE=UP IO_TYPE=LVCMOS33; + +// SD card +IO_LOC "sd_clk" 36; +IO_PORT "sd_clk" PULL_MODE=NONE IO_TYPE=LVCMOS33; +IO_LOC "sd_cmd" 37; // MOSI +IO_PORT "sd_cmd" PULL_MODE=NONE IO_TYPE=LVCMOS33; +IO_LOC "sd_dat[0]" 39; // MISO +IO_PORT "sd_dat[0]" PULL_MODE=NONE IO_TYPE=LVCMOS33; +IO_LOC "sd_dat[1]" 48; // Hardware modification needed ! +IO_PORT "sd_dat[1]" PULL_MODE=NONE IO_TYPE=LVCMOS33; +IO_LOC "sd_dat[2]" 49; // Hardware modification needed ! +IO_PORT "sd_dat[2]" PULL_MODE=NONE IO_TYPE=LVCMOS33; +IO_LOC "sd_dat[3]" 38; +IO_PORT "sd_dat[3]" PULL_MODE=NONE IO_TYPE=LVCMOS33; + +// Joystick and MIDI +IO_LOC "joystick_clk" 51; +IO_PORT "joystick_clk" PULL_MODE=UP IO_TYPE=LVCMOS33; +IO_LOC "joystick_mosi" 53; +IO_PORT "joystick_mosi" PULL_MODE=UP IO_TYPE=LVCMOS33; +IO_LOC "joystick_miso" 54; +IO_PORT "joystick_miso" PULL_MODE=UP IO_TYPE=LVCMOS33; +IO_LOC "joystick_cs" 55; +IO_PORT "joystick_cs" PULL_MODE=UP IO_TYPE=LVCMOS33; + +// SPI FLASH +//IO_LOC "mspi_clk" 59; +//IO_PORT "mspi_clk" IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=4 BANK_VCCIO=3.3; +//IO_LOC "mspi_cs" 60; +//IO_PORT "mspi_cs" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=4 BANK_VCCIO=3.3; +//IO_LOC "mspi_do" 62; +//IO_PORT "mspi_do" IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=4 BANK_VCCIO=3.3; +//IO_LOC "mspi_di" 61; +//IO_PORT "mspi_di" IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3; + +//IO_LOC "PIN49_IOR24A_SPILCD_RS" 49; +//IO_LOC "PIN77_IOT37A_SPILCD_MO; 77" +//IO_LOC "PIN76_IOT37B_SPILCD_MCLK" 76; +//IO_LOC "PIN48_IOR24B_SPILCD_CS" 48; +//IO_LOC "PIN47_IOB43B_SPILCD_EN" 47; + +//IO_LOC "PIN25_IOB8A" 25; +//IO_LOC "PIN26_IOB8B" 26; +//IO_LOC "PIN27_IOB11A 27; +//IO_LOC "PIN28_IOB11B 28; +//IO_LOC "PIN29_IOB13A" 29; +//IO_LOC "PIN30_IOB13B" 30; + +//IO_LOC "I_PS2_CLK" 76; +//IO_LOC "I_PS2_DATA" 77; +//IO_LOC "O_AUDIO" 30; \ No newline at end of file diff --git a/src/a2600_top_tn9k.sdc b/src/a2600_top_tn9k.sdc new file mode 100644 index 0000000..c08020c --- /dev/null +++ b/src/a2600_top_tn9k.sdc @@ -0,0 +1,11 @@ +create_clock -name clk_27mhz -period 37.037 -waveform {0 5} [get_ports {clk_27mhz}] +create_clock -name ds2_clk -period 8000 -waveform {0 5} [get_nets {gamepad/clk_spi}] +create_clock -name joymiso -period 8000 -waveform {0 20} [get_ports {joystick_miso}] +create_clock -name clk -period 34.722 -waveform {0 5} [get_nets {clk}] +create_clock -name clk_14 -period 70 -waveform {0 5} [get_nets {clk_14}] +create_clock -name clk_cpu -period 279.408 -waveform {0 5} [get_nets {clk_cpu}] +create_clock -name m0s[3] -period 40 -waveform {0 5} [get_ports {m0s[3]}] -add +create_clock -name clk_pixel_x5 -period 6.944 -waveform {0 1.25} [get_nets {clk_pixel_x5}] -add +create_clock -name clk_audio -period 20833.332 -waveform {0 5} [get_nets {video_inst/clk_audio}] -add +report_timing -hold -from_clock [get_clocks {clk*}] -to_clock [get_clocks {clk*}] -max_paths 25 -max_common_paths 1 +report_timing -setup -from_clock [get_clocks {clk*}] -to_clock [get_clocks {clk*}] -max_paths 25 -max_common_paths 1 diff --git a/src/a2600_top_tn9k.vhd b/src/a2600_top_tn9k.vhd new file mode 100644 index 0000000..8ec7122 --- /dev/null +++ b/src/a2600_top_tn9k.vhd @@ -0,0 +1,915 @@ +------------------------------------------------------------------------- +-- A2600 Top level for Tang Nano 9k +-- 2024 Stefan Voss +-- based on the work of many others +-- +------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.numeric_std.ALL; + +entity A2600_top is + port + ( + clk_27mhz : in std_logic; -- 27 Mhz XO + --clk_0 : in std_logic; -- Mhz PLL + --clk_1 : in std_logic; -- Mhz PLL + --clk_2 : in std_logic; -- Mhz PLL + reset : in std_logic; -- S2 button + user : in std_logic; -- S1 button + leds_n : out std_logic_vector(5 downto 0); + io : in std_logic_vector(4 downto 0); + + -- SPI interface Sipeed M0S Dock external BL616 uC + m0s : inout std_logic_vector(4 downto 0); + -- + tmds_clk_n : out std_logic; + tmds_clk_p : out std_logic; + tmds_d_n : out std_logic_vector( 2 downto 0); + tmds_d_p : out std_logic_vector( 2 downto 0); + -- sd interface + sd_clk : out std_logic; + sd_cmd : inout std_logic; + sd_dat : inout std_logic_vector(3 downto 0); + ws2812 : out std_logic; + + -- Gamepad + joystick_clk : out std_logic; + joystick_mosi : out std_logic; + joystick_miso : inout std_logic; + joystick_cs : inout std_logic + ); +end; + +architecture Behavioral_top of A2600_top is + +signal clk : std_logic; +signal clk_cpu : std_logic; +signal clk_14 : std_logic; +signal pll_locked : std_logic; +signal clk_pixel_x5 : std_logic; +attribute syn_keep : integer; +attribute syn_keep of clk_cpu : signal is 1; +attribute syn_keep of clk : signal is 1; +attribute syn_keep of clk_14 : signal is 1; +attribute syn_keep of clk_pixel_x5 : signal is 1; +attribute syn_keep of m0s : signal is 1; + + -- keyboard +signal keyboard_matrix_out : std_logic_vector(7 downto 0); +signal keyboard_matrix_in : std_logic_vector(7 downto 0); +signal joyUsb1 : std_logic_vector(15 downto 0); +signal joyUsb2 : std_logic_vector(15 downto 0); +signal joyDigital : std_logic_vector(15 downto 0); +signal joyNumpad : std_logic_vector(15 downto 0); +signal joyMouse : std_logic_vector(15 downto 0); +signal numpad : std_logic_vector(7 downto 0); +signal joyDS2 : std_logic_vector(15 downto 0); +-- joystick interface +signal joyA : std_logic_vector(15 downto 0); +signal joyB : std_logic_vector(15 downto 0); +signal joy_p1 : std_logic_vector(15 downto 0); +signal joy_p2 : std_logic_vector(15 downto 0); +signal port_1_sel : std_logic_vector(3 downto 0); +signal port_2_sel : std_logic_vector(3 downto 0); +-- mouse / paddle +signal pot1 : std_logic_vector(7 downto 0); +signal pot2 : std_logic_vector(7 downto 0); +signal pot3 : std_logic_vector(7 downto 0); +signal pot4 : std_logic_vector(7 downto 0); +signal pd1,pd2 : std_logic_vector(7 downto 0); +signal pd3,pd4 : std_logic_vector(7 downto 0); +signal p1,p2,p3,p4 : std_logic_vector(7 downto 0); +signal mouse_x_pos : signed(10 downto 0); +signal mouse_y_pos : signed(10 downto 0); +signal pal : std_logic; +signal system_video_std : std_logic_vector(1 downto 0); +signal hsync : std_logic; +signal vsync : std_logic; +signal r : unsigned(7 downto 0); +signal g : unsigned(7 downto 0); +signal b : unsigned(7 downto 0); + +-- BL616 interfaces +signal mcu_start : std_logic; +signal mcu_sys_strobe : std_logic; +signal mcu_hid_strobe : std_logic; +signal mcu_osd_strobe : std_logic; +signal mcu_sdc_strobe : std_logic; +signal data_in_start : std_logic; +signal mcu_data_out : std_logic_vector(7 downto 0); +signal hid_data_out : std_logic_vector(7 downto 0); +signal osd_data_out : std_logic_vector(7 downto 0) := X"55"; +signal sys_data_out : std_logic_vector(7 downto 0); +signal sdc_data_out : std_logic_vector(7 downto 0); +signal hid_int : std_logic; +signal system_scanlines : std_logic_vector(1 downto 0); +signal system_volume : std_logic_vector(1 downto 0); +signal joystick1 : std_logic_vector(7 downto 0); +signal joystick2 : std_logic_vector(7 downto 0); +signal mouse_btns : std_logic_vector(1 downto 0); +signal mouse_x : signed(7 downto 0); +signal mouse_y : signed(7 downto 0); +signal mouse_strobe : std_logic; +signal osd_status : std_logic; +signal ws2812_color : std_logic_vector(23 downto 0); +signal system_reset : std_logic_vector(1 downto 0); +signal sd_img_size : std_logic_vector(31 downto 0); +signal sd_img_size_d : std_logic_vector(31 downto 0); +signal sd_img_mounted : std_logic_vector(4 downto 0); +signal sd_rd : std_logic_vector(4 downto 0); +signal sd_wr : std_logic_vector(4 downto 0); +signal sd_lba : std_logic_vector(31 downto 0); +signal sd_busy : std_logic; +signal sd_done : std_logic; +signal sd_rd_byte_strobe : std_logic; +signal sd_byte_index : std_logic_vector(8 downto 0); +signal sd_rd_data : std_logic_vector(7 downto 0); +signal sd_wr_data : std_logic_vector(7 downto 0); +signal sd_change : std_logic; +signal sdc_int : std_logic; +signal sdc_iack : std_logic; +signal int_ack : std_logic_vector(7 downto 0); +signal spi_ext : std_logic; +signal spi_io_din : std_logic; +signal spi_io_ss : std_logic; +signal spi_io_clk : std_logic; +signal spi_io_dout : std_logic; +signal system_wide_screen : std_logic; +signal leds : std_logic_vector(5 downto 0); +signal system_leds : std_logic_vector(1 downto 0); +signal db9_joy : std_logic_vector(5 downto 0); +signal hblank : std_logic; +signal vblank : std_logic; +signal joystick_cs_i : std_logic; +signal joystick_miso_i : std_logic; +signal paddle_1 : std_logic_vector(7 downto 0); +signal paddle_2 : std_logic_vector(7 downto 0); +signal paddle_3 : std_logic_vector(7 downto 0); +signal paddle_4 : std_logic_vector(7 downto 0); +signal key_r1 : std_logic; +signal key_r2 : std_logic; +signal key_l1 : std_logic; +signal key_l2 : std_logic; +signal key_triangle : std_logic; +signal key_square : std_logic; +signal key_circle : std_logic; +signal key_cross : std_logic; +signal key_up : std_logic; +signal key_down : std_logic; +signal key_left : std_logic; +signal key_right : std_logic; +signal key_start : std_logic; +signal key_select : std_logic; +signal key_lstick : std_logic; +signal key_rstick : std_logic; +--- +signal video_r : std_logic_vector(7 downto 0); +signal video_g : std_logic_vector(7 downto 0); +signal video_b : std_logic_vector(7 downto 0); +signal audio0 : std_logic_vector(3 downto 0); +signal audio1 : std_logic_vector(3 downto 0); + +-- loader +signal load_crt : std_logic := '0'; +signal load_prg : std_logic := '0'; +signal load_rom : std_logic := '0'; +signal load_tap : std_logic := '0'; +signal loader_lba : std_logic_vector(31 downto 0); +signal loader_busy : std_logic; +signal img_select : std_logic_vector(2 downto 0); +signal ioctl_download : std_logic := '0'; +signal ioctl_load_addr : std_logic_vector(22 downto 0); +signal ioctl_wr : std_logic; +signal ioctl_data : std_logic_vector(7 downto 0); +signal ioctl_addr : std_logic_vector(22 downto 0); +signal ioctl_wait : std_logic := '0'; +signal dl_addr : std_logic_vector(15 downto 0); +signal dl_data : std_logic_vector(7 downto 0); +signal dl_wr : std_logic; +signal ioctl_file_ext : std_logic_vector(31 downto 0) := x"00000000"; +signal rom_a : std_logic_vector(15 downto 0); +signal rom_do : std_logic_vector(7 downto 0); +signal reset2600 : std_logic; +signal system_sc : std_logic_vector(1 downto 0); +signal sc : std_logic; +signal scdetect : std_logic; +signal decomb : std_logic; +signal p_dif1 : std_logic; +signal p_dif2 : std_logic; +signal p_color : std_logic; +signal paddle_1a : std_logic_vector(7 downto 0); +signal paddle_2a : std_logic_vector(7 downto 0); +signal p_start : std_logic; +signal p_select : std_logic; +signal vblank_regen : std_logic; +signal force_bs : std_logic_vector(4 downto 0); +signal joystick0ax : signed(7 downto 0); +signal joystick0ay : signed(7 downto 0); +signal joystick1ax : signed(7 downto 0); +signal joystick1ay : signed(7 downto 0); +signal joystick_strobe : std_logic; +signal joystick1_x_pos : std_logic_vector(7 downto 0); +signal joystick1_y_pos : std_logic_vector(7 downto 0); +signal joystick2_x_pos : std_logic_vector(7 downto 0); +signal joystick2_y_pos : std_logic_vector(7 downto 0); +signal extra_button0 : std_logic_vector(7 downto 0); +signal extra_button1 : std_logic_vector(7 downto 0); +signal img_size_crt : std_logic_vector(31 downto 0); +signal paddle_inv : std_logic; +signal joyswap : std_logic; +signal paldetect : std_logic; +signal reset_detect : std_logic; +signal cart_download_d : std_logic; +signal cart_download : std_logic; +signal bs_unsupported : std_logic; + +component CLKDIV + generic ( + DIV_MODE : STRING := "2"; + GSREN: in string := "false" + ); + port ( + CLKOUT: out std_logic; + HCLKIN: in std_logic; + RESETN: in std_logic; + CALIB: in std_logic + ); +end component; + +component rPLL + generic ( + FCLKIN: in string := "100.0"; + DEVICE: in string := "GW2A-18"; + DYN_IDIV_SEL: in string := "false"; + IDIV_SEL: in integer := 0; + DYN_FBDIV_SEL: in string := "false"; + FBDIV_SEL: in integer := 0; + DYN_ODIV_SEL: in string := "false"; + ODIV_SEL: in integer := 8; + PSDA_SEL: in string := "0000"; + DYN_DA_EN: in string := "false"; + DUTYDA_SEL: in string := "1000"; + CLKOUT_FT_DIR: in bit := '1'; + CLKOUTP_FT_DIR: in bit := '1'; + CLKOUT_DLY_STEP: in integer := 0; + CLKOUTP_DLY_STEP: in integer := 0; + CLKOUTD3_SRC: in string := "CLKOUT"; + CLKFB_SEL: in string := "internal"; + CLKOUT_BYPASS: in string := "false"; + CLKOUTP_BYPASS: in string := "false"; + CLKOUTD_BYPASS: in string := "false"; + CLKOUTD_SRC: in string := "CLKOUT"; + DYN_SDIV_SEL: in integer := 2 + ); + port ( + CLKOUT: out std_logic; + LOCK: out std_logic; + CLKOUTP: out std_logic; + CLKOUTD: out std_logic; + CLKOUTD3: out std_logic; + RESET: in std_logic; + RESET_P: in std_logic; + CLKIN: in std_logic; + CLKFB: in std_logic; + FBDSEL: in std_logic_vector(5 downto 0); + IDSEL: in std_logic_vector(5 downto 0); + ODSEL: in std_logic_vector(5 downto 0); + PSDA: in std_logic_vector(3 downto 0); + DUTYDA: in std_logic_vector(3 downto 0); + FDLY: in std_logic_vector(3 downto 0) + ); +end component; + +begin +-- ----------------- SPI input parser ---------------------- +-- map output data onto both spi outputs + spi_io_din <= m0s(1); + spi_io_ss <= m0s(2); + spi_io_clk <= m0s(3); + m0s(0) <= spi_io_dout; -- M0 Dock + +joystick_cs <= joystick_cs_i; +joystick_miso_i <= joystick_miso; + +-- https://store.curiousinventor.com/guides/PS2/ +-- https://hackaday.io/project/170365-blueretro/log/186471-playstation-playstation-2-spi-interface + +gamepad: entity work.dualshock2 + port map ( + clk => clk, + rst => system_reset(0) and not pll_locked, + vsync => vsync, + ds2_dat => joystick_miso_i, + ds2_cmd => joystick_mosi, + ds2_att => joystick_cs_i, + ds2_clk => joystick_clk, + ds2_ack => '0', + stick_lx => paddle_1, + stick_ly => paddle_2, + stick_rx => paddle_3, + stick_ry => paddle_4, + key_up => key_up, + key_down => key_down, + key_left => key_left, + key_right => key_right, + key_l1 => key_l1, + key_l2 => key_l2, + key_r1 => key_r1, + key_r2 => key_r2, + key_triangle => key_triangle, + key_square => key_square, + key_circle => key_circle, + key_cross => key_cross, + key_start => key_start, + key_select => key_select, + key_lstick => key_lstick, + key_rstick => key_rstick, + debug1 => open, + debug2 => open + ); + +led_ws2812: entity work.ws2812 + port map + ( + clk => clk, + color => ws2812_color, + data => ws2812 + ); + +sdc_iack <= int_ack(3); + +sd_card_inst: entity work.sd_card +generic map ( + CLK_DIV => 1 + ) + port map ( + rstn => pll_locked, + clk => clk, + + -- SD card signals + sdclk => sd_clk, + sdcmd => sd_cmd, + sddat => sd_dat, + + -- mcu interface + data_strobe => mcu_sdc_strobe, + data_start => mcu_start, + data_in => mcu_data_out, + data_out => sdc_data_out, + + -- interrupt to signal communication request + irq => sdc_int, + iack => sdc_iack, + + -- output file/image information. Image size is e.g. used by fdc to + -- translate between sector/track/side and lba sector + image_size => sd_img_size, -- length of image file + image_mounted => sd_img_mounted, + ioctl_file_ext => ioctl_file_ext, + + -- user read sector command interface (sync with clk) + rstart => sd_rd, + wstart => sd_wr, + rsector => loader_lba, + rbusy => sd_busy, + rdone => sd_done, -- done from sd reader acknowledges/clears start + + -- sector data output interface (sync with clk) + inbyte => sd_wr_data, -- sector data output interface (sync with clk) + outen => sd_rd_byte_strobe, -- when outen=1, a byte of sector content is read out from outbyte + outaddr => sd_byte_index, -- outaddr from 0 to 511, because the sector size is 512 + outbyte => sd_rd_data -- a byte of sector content +); + +video_inst: entity work.video +port map( + pll_lock => pll_locked, + clk => clk, + clk_pixel_x5 => clk_pixel_x5, + + vb_in => vblank, + hb_in => hblank, + hs_in_n => not hsync, + vs_in_n => not vsync, + + r_in => video_r(7 downto 4), + g_in => video_g(7 downto 4), + b_in => video_b(7 downto 4), + audio_l => signed("0" & audio0 & "0000000000"), + audio_r => signed("0" & audio1 & "0000000000"), + osd_status => osd_status, + vblank_regenerate => vblank_regen, + paldetect => paldetect, + mcu_start => mcu_start, + mcu_osd_strobe => mcu_osd_strobe, + mcu_data => mcu_data_out, + + -- values that can be configure by the user via osd + system_wide_screen => system_wide_screen, + system_scanlines => system_scanlines, + system_volume => system_volume, + + tmds_clk_n => tmds_clk_n, + tmds_clk_p => tmds_clk_p, + tmds_d_n => tmds_d_n, + tmds_d_p => tmds_d_p + ); + +-- target +-- PAL 3.546894 Hz 28.375152 141.875760 +-- NTSC 3.579545 Hz 28.636360 143.181800 + +-- Clock tree and all frequencies in Hz +-- TN20 NTSC +-- hdmi 144000000 +-- core 28800000 +-- pixel 3600000 +-- IDIV 2, FBDIV 15 + +-- TN20 PAL +-- hdmi 141.750.000 +-- core 28.350.000 +-- pixel 3.543.750 +-- IDIV 3, FBDIV 20 + +-- MS5351M PLL IC @ 25Mhz XO + +mainclock: rPLL +generic map ( + FCLKIN => "27", + DEVICE => "GW1NR-9C", + DYN_IDIV_SEL => "false", + IDIV_SEL => 2, + DYN_FBDIV_SEL => "false", + FBDIV_SEL => 15, + DYN_ODIV_SEL => "false", + ODIV_SEL => 4, + PSDA_SEL => "0100", + DYN_DA_EN => "false", + DUTYDA_SEL => "1000", + CLKOUT_FT_DIR => '1', + CLKOUTP_FT_DIR => '1', + CLKOUT_DLY_STEP => 0, + CLKOUTP_DLY_STEP => 0, + CLKFB_SEL => "internal", + CLKOUT_BYPASS => "false", + CLKOUTP_BYPASS => "false", + CLKOUTD_BYPASS => "false", + DYN_SDIV_SEL => 2, + CLKOUTD_SRC => "CLKOUT", + CLKOUTD3_SRC => "CLKOUT" + ) + port map ( + CLKOUT => clk_pixel_x5, + LOCK => pll_locked, + CLKOUTP => open, -- 90deg shifted + CLKOUTD => open, + CLKOUTD3 => open, + RESET => '0', + RESET_P => '0', + CLKIN => clk_27mhz, + CLKFB => '0', + FBDSEL => (others => '0'), + IDSEL => (others => '0'), + ODSEL => (others => '0'), + PSDA => (others => '0'), + DUTYDA => (others => '0'), + FDLY => (others => '1') + ); + +div1_inst: CLKDIV +generic map( + DIV_MODE => "5", + GSREN => "false" +) +port map( + CLKOUT => clk, -- 28Mhz + HCLKIN => clk_pixel_x5, + RESETN => pll_locked, + CALIB => '0' +); + +div2_inst: CLKDIV +generic map( + DIV_MODE => "2", + GSREN => "false" +) +port map( + CLKOUT => clk_14, + HCLKIN => clk, + RESETN => pll_locked, + CALIB => '0' +); + +div3_inst: CLKDIV +generic map( + DIV_MODE => "4", + GSREN => "false" +) +port map( + CLKOUT => clk_cpu, + HCLKIN => clk_14, + RESETN => pll_locked, + CALIB => '0' +); + +leds_n <= not leds; +leds(5 downto 1) <= "11111" when force_bs > 14 else "00000"; -- indicate unsupported mapper + +-- 9 pin d-sub joystick pinout: +-- pin 1: up +-- pin 2: down +-- pin 3: left +-- pin 4: right +-- pin 6: fire +-- pin 9: fire 2nd button + +-- Atari 2600, 6532 ports: +-- PA0: right joystick, up +-- PA1: right joystick, down +-- PA2: right joystick, left +-- PA3: right joystick, right +-- PA4: left joystick, up +-- PA5: left joystick, down +-- PA6: left joystick, left +-- PA7: left joystick, right +-- PB0: start +-- PB1: select +-- PB3: B/W, color +-- PB6: left difficulty +-- PB7: right difficulty + +-- Atari 2600, TIA input: +-- I5: right joystick, fire +-- I6: left joystick, fire + +-- pinout docking station joystick 1/2: +-- bit 0: up +-- bit 1: down +-- bit 2: left +-- bit 3: right +-- bit 4: fire +-- bit 5: 2nd fire (required for paddle emulation) + +-- BTN_RIGHT 0 +-- BTN_LEFT 1 +-- BTN_DOWN 2 +-- BTN_UP 3 +-- BTN_A 4 +-- BTN_B 5 +-- BTN_X 6 +-- BTN_Y 7 +-- BTN_SL 8 +-- BTN_SR 9 +-- BTN_SELECT 10 +-- BTN_START 11 +joyDS2 <= key_rstick & key_lstick & key_r2 & key_l2 & key_start & key_select & key_r1 & key_l1 & + key_square & key_triangle & key_cross & key_circle & key_up & key_down & key_left & key_right; +joyDigital <= not(x"FF" & "111" & io(0) & io(2) & io(1) & io(4) & io(3)); +joyUsb1 <= extra_button0 & joystick1(7 downto 4) & joystick1(3) & joystick1(2) & joystick1(1) & joystick1(0); +joyUsb2 <= extra_button1 & joystick2(7 downto 4) & joystick2(3) & joystick2(2) & joystick2(1) & joystick2(0); +joyNumpad <= x"00" & "000" & numpad(4) & numpad(3) & numpad(2) & numpad(1) & numpad(0); +joyMouse <= x"0000"; + +-- send external DB9 joystick port to µC +db9_joy <= not('1' & io(0) & io(1) & io(2) & io(3) & io(4)); + +process(clk) +begin + if rising_edge(clk) then + case port_1_sel is + when "0000" => joyA <= joyDigital; + when "0001" => joyA <= joyUsb1; + when "0010" => joyA <= joyUsb2; + when "0011" => joyA <= joyNumpad; + when "0100" => joyA <= joyDS2; + when "0101" => joyA <= joyMouse; + when "0110" => joyA <= (others => '0'); + when others => null; + end case; + end if; +end process; + +process(clk) +begin + if rising_edge(clk) then + case port_2_sel is + when "0000" => joyB <= joyDigital; + when "0001" => joyB <= joyUsb1; + when "0010" => joyB <= joyUsb2; + when "0011" => joyB <= joyNumpad; + when "0100" => joyB <= joyDS2; + when "0101" => joyB <= joyMouse; + when "0110" => joyB <= (others => '0'); + when others => null; + end case; + end if; +end process; + +-- paddle pins +pd1 <= not paddle_1 when port_1_sel = "0100" else + joystick1_x_pos(7 downto 0) when port_1_sel = "0001" else + x"ff"; +pd2 <= not paddle_2 when port_1_sel = "0100" else + joystick1_y_pos(7 downto 0) when port_1_sel = "0001" else + x"ff"; +pd3 <= not paddle_3 when port_2_sel = "0100" else + joystick2_x_pos(7 downto 0) when port_2_sel = "0010" else + x"ff"; +pd4 <= not paddle_4 when port_2_sel = "0100" else + joystick2_y_pos(7 downto 0) when port_2_sel = "0010" else + x"ff"; + +process(clk, system_reset(0)) + variable mov_x: signed(6 downto 0); + variable mov_y: signed(6 downto 0); + begin + if system_reset(0) = '1' then + joystick1_x_pos <= x"ff"; + joystick1_y_pos <= x"ff"; + joystick2_x_pos <= x"ff"; + joystick2_y_pos <= x"ff"; + elsif rising_edge(clk) then + if joystick_strobe = '1' then + joystick1_x_pos <= std_logic_vector(joystick0ax(7 downto 0)); + joystick1_y_pos <= std_logic_vector(joystick0ay(7 downto 0)); + joystick2_x_pos <= std_logic_vector(joystick1ax(7 downto 0)); + joystick2_y_pos <= std_logic_vector(joystick1ay(7 downto 0)); + end if; + end if; +end process; + +mcu_spi_inst: entity work.mcu_spi +port map ( + clk => clk, + reset => not pll_locked, + -- SPI interface to BL616 MCU + spi_io_ss => spi_io_ss, -- SPI CSn + spi_io_clk => spi_io_clk, -- SPI SCLK + spi_io_din => spi_io_din, -- SPI MOSI + spi_io_dout => spi_io_dout, -- SPI MISO + -- byte interface to the various core components + mcu_sys_strobe => mcu_sys_strobe, -- byte strobe for system control target + mcu_hid_strobe => mcu_hid_strobe, -- byte strobe for HID target + mcu_osd_strobe => mcu_osd_strobe, -- byte strobe for OSD target + mcu_sdc_strobe => mcu_sdc_strobe, -- byte strobe for SD card target + mcu_start => mcu_start, + mcu_sys_din => sys_data_out, + mcu_hid_din => hid_data_out, + mcu_osd_din => osd_data_out, + mcu_sdc_din => sdc_data_out, + mcu_dout => mcu_data_out +); + +-- decode SPI/MCU data received for human input devices (HID) +hid_inst: entity work.hid + port map + ( + clk => clk, + reset => not pll_locked, + -- interface to receive user data from MCU (mouse, kbd, ...) + data_in_strobe => mcu_hid_strobe, + data_in_start => mcu_start, + data_in => mcu_data_out, + data_out => hid_data_out, + + -- input local db9 port events to be sent to MCU + db9_port => db9_joy, + irq => hid_int, + iack => int_ack(1), + -- output HID data received from USB + joystick0 => joystick1, + joystick1 => joystick2, + numpad => numpad, + keyboard_matrix_out => keyboard_matrix_out, + keyboard_matrix_in => keyboard_matrix_in, + key_restore => open, + tape_play => open, + mod_key => open, + mouse_btns => mouse_btns, + mouse_x => mouse_x, + mouse_y => mouse_y, + mouse_strobe => mouse_strobe, + joystick0ax => joystick0ax, + joystick0ay => joystick0ay, + joystick1ax => joystick1ax, + joystick1ay => joystick1ay, + joystick_strobe => joystick_strobe, + extra_button0 => extra_button0, + extra_button1 => extra_button1 + ); + +module_inst: entity work.sysctrl + port map + ( + clk => clk, + reset => not pll_locked, +-- + data_in_strobe => mcu_sys_strobe, + data_in_start => mcu_start, + data_in => mcu_data_out, + data_out => sys_data_out, + + -- values that can be configured by the user + system_reset => system_reset, + system_scanlines => system_scanlines, + system_volume => system_volume, + system_wide_screen => system_wide_screen, + system_port_1 => port_1_sel, + system_port_2 => port_2_sel, + system_paddle => paddle_inv, + system_diff_p1 => p_dif1, + system_diff_p2 => p_dif2, + system_decomb => decomb, + system_vblank => vblank_regen, + system_vm => p_color, + system_sc => system_sc, + system_video_std => system_video_std, + system_joyswap => joyswap, + + int_out_n => m0s(4), + int_in => std_logic_vector(unsigned'("0000" & sdc_int & '0' & hid_int & '0')), + int_ack => int_ack, + + buttons => unsigned'(not reset & not user), -- S0 and S1 buttons + leds => system_leds, -- two leds can be controlled from the MCU + color => ws2812_color -- a 24bit color to e.g. be used to drive the ws2812 +); + +sd_rd(4) <= '0'; +sd_wr(4 downto 0) <= "00000"; + + crt_inst : entity work.loader_sd_card + port map ( + clk => clk, + system_reset => system_reset, + + sd_lba => loader_lba, + sd_rd => sd_rd(3 downto 0), + sd_wr => open, + sd_busy => sd_busy, + sd_done => sd_done, + + sd_byte_index => sd_byte_index, + sd_rd_data => sd_rd_data, + sd_rd_byte_strobe => sd_rd_byte_strobe, + + sd_img_mounted => sd_img_mounted, + loader_busy => loader_busy, + load_crt => load_crt, + sd_img_size => sd_img_size, + leds(0) => leds(0), + img_select => img_select, + img_size_crt => img_size_crt, + + ioctl_download => ioctl_download, + ioctl_addr => ioctl_addr, + ioctl_data => ioctl_data, + ioctl_wr => ioctl_wr, + ioctl_wait => ioctl_wait + ); + +reset2600 <= system_reset(0) or not pll_locked or cart_download; + +-- swap joysticks and paddle +joy_p1 <= joyB when joyswap = '1' else joyA; +joy_p2 <= joyA when joyswap = '1' else joyB; +pot1 <= (not pd3(7) & pd3(6 downto 0)) when joyswap = '1' else (not pd1(7) & pd1(6 downto 0)); +pot2 <= (not pd4(7) & pd4(6 downto 0)) when joyswap = '1' else (not pd2(7) & pd2(6 downto 0)); +pot3 <= (not pd1(7) & pd1(6 downto 0)) when joyswap = '1' else (not pd3(7) & pd3(6 downto 0)); +pot4 <= (not pd2(7) & pd2(6 downto 0)) when joyswap = '1' else (not pd4(7) & pd4(6 downto 0)); + +-- invert paddle +p1 <= not pot1 when paddle_inv = '1' else pot1; +p2 <= not pot2 when paddle_inv = '1' else pot2; +p3 <= not pot3 when paddle_inv = '1' else pot3; +p4 <= not pot4 when paddle_inv = '1' else pot4; + +a2601_inst: entity work.A2601top + port map( + reset => reset2600, + clk => clk_cpu, -- 3.5Mhz + vid_clk => clk, -- 28Mhz + + aud0 => audio0, + aud1 => audio1, + + O_VSYNC => vsync, + O_HSYNC => hsync, + O_HBLANK => hblank, + O_VBLANK => vblank, + O_VIDEO_R => video_r, + O_VIDEO_G => video_g, + O_VIDEO_B => video_b, + p1_l => not joy_p1(1), + p1_r => not joy_p1(0), + p1_u => not joy_p1(3), + p1_d => not joy_p1(2), + p1_f => not joy_p1(4), -- BTN_A + p1_f2 => not joy_p1(7), -- BTN_Y + + p2_l => not joy_p2(1), + p2_r => not joy_p2(0), + p2_u => not joy_p2(3), + p2_d => not joy_p2(2), + p2_f => not joy_p2(4), -- BTN_A + p2_f2 => not joy_p2(7), -- BTN_Y + + p_1 => not joy_p1(5), -- BTN_B + paddle_1 => p1, + + p_2 => not joy_p1(6), -- BTN_X + paddle_2 => p2, + + p_3 => not joy_p2(5), -- BTN_B + paddle_3 => p3, + + p_4 => not joy_p2(6), -- BTN_X + paddle_4 => p4, + + p_type => "00", + + p_start => p_start, + p_select => p_select, + p_color => p_color, + + sc => sc, -- SuperChip enable + force_bs => force_bs, -- forced bank switch type + rom_a => rom_a, + rom_do => rom_do, + rom_size => img_size_crt(16 downto 0), + + pause => '0', + + pal => pal, + p_dif => not (p_dif2 & p_dif1), -- 0 = B, 1 = A + decomb => decomb + ); + +p_start <= '0' when (joyA(11) = '1' or joyB(11) = '1' or numpad(6) = '1') else '1';-- BTN_SELECT / F11 +p_select <= '0' when (joyA(10) = '1' or joyB(10) = '1' or numpad(7) = '1') else '1';-- BTN_START / PAGE UP + +cart_download <= ioctl_download and load_crt; +process(clk) +begin + if rising_edge(clk) then + reset_detect <= '0'; + cart_download_d <= cart_download; + if (not cart_download_d and cart_download) then + reset_detect <= '1'; + end if; + end if; +end process; + +detect_inst: entity work.detect2600 +port map( + clk => clk, + reset => reset_detect or system_reset(0), + addr => dl_addr(15 downto 0), + enable => ioctl_wr and cart_download, + cart_size => img_size_crt, + data => dl_data, + force_bs => force_bs, + sc => scdetect +); + +pal <= '1' when system_video_std(1 downto 0) = 2 else + '0' when system_video_std(1 downto 0) = 1 else + paldetect; +sc <= '1' when system_sc(1 downto 0) = 2 else + '0' when system_sc(1 downto 0) = 1 else + scdetect; + +process(clk) +begin + if rising_edge(clk) then + dl_wr <= '0'; + if cart_download then + if ioctl_wr = '1' then + dl_addr <= ioctl_addr(15 downto 0); + dl_data <= ioctl_data; + dl_wr <= '1'; + end if; + end if; + end if; +end process; + +ram_inst: entity work.Gowin_SDPB + port map ( + dout => rom_do, + adb => rom_a(14 downto 0), + ceb => '1', + clkb => clk_cpu, + resetb => '0', + oce => '1', + + clka => clk, + cea => dl_wr, + reseta => '0', + ada => dl_addr(14 downto 0), + din => dl_data + ); + +end Behavioral_top; diff --git a/src/gowin_rpll/gowin_rpll.ipc b/src/gowin_rpll/gowin_rpll.ipc index f414d00..16fb5cd 100644 --- a/src/gowin_rpll/gowin_rpll.ipc +++ b/src/gowin_rpll/gowin_rpll.ipc @@ -2,7 +2,7 @@ ipc_version=4 file=gowin_rpll module=Gowin_rPLL -target_device=gw2ar18c-000 +target_device=gw1nr9c-004 type=clock_rpll version=1.0 @@ -11,17 +11,14 @@ CKLOUTD3=false CLKFB_SOURCE=0 CLKIN_FREQ=27 CLKOUTD=false -CLKOUTP=true +CLKOUTP=false CLKOUT_BYPASS=false -CLKOUT_DIVIDE_DYN=true -CLKOUT_FREQ=141.75 -CLKOUT_TOLERANCE=0 +CLKOUT_DIVIDE_DYN=false DYNAMIC=false LANG=1 LOCK_EN=true MODE_GENERAL=true PLL_PWD=false -RESET_PLL=true -CLKOUTP_BYPASS=false -CLKOUTP_DUTY_CYCLE=6 -CLKOUTP_PHASE=4 +RESET_PLL=false +CLKOUT_FREQ=144 +CLKOUT_TOLERANCE=0 diff --git a/src/gowin_rpll/gowin_rpll.vhd b/src/gowin_rpll/gowin_rpll.vhd index 2fc19e4..06119d3 100644 --- a/src/gowin_rpll/gowin_rpll.vhd +++ b/src/gowin_rpll/gowin_rpll.vhd @@ -1,11 +1,11 @@ --Copyright (C)2014-2024 Gowin Semiconductor Corporation. --All rights reserved. --File Title: IP file ---Tool Version: V1.9.10.01 (64-bit) ---Part Number: GW2AR-LV18QN88C8/I7 ---Device: GW2AR-18 +--Tool Version: V1.9.10.03 (64-bit) +--Part Number: GW1NR-LV9QN88PC6/I5 +--Device: GW1NR-9 --Device Version: C ---Created Time: Sat Sep 28 16:42:39 2024 +--Created Time: Sun Dec 15 13:57:00 2024 library IEEE; use IEEE.std_logic_1164.all; @@ -14,17 +14,15 @@ entity Gowin_rPLL is port ( clkout: out std_logic; lock: out std_logic; - clkoutp: out std_logic; - reset: in std_logic; clkin: in std_logic ); end Gowin_rPLL; architecture Behavioral of Gowin_rPLL is + signal clkoutp_o: std_logic; signal clkoutd_o: std_logic; signal clkoutd3_o: std_logic; - signal gw_vcc: std_logic; signal gw_gnd: std_logic; signal FBDSEL_i: std_logic_vector(5 downto 0); signal IDSEL_i: std_logic_vector(5 downto 0); @@ -37,7 +35,7 @@ architecture Behavioral of Gowin_rPLL is component rPLL generic ( FCLKIN: in string := "100.0"; - DEVICE: in string := "GW2A-18"; + DEVICE: in string := "GW1N-4"; DYN_IDIV_SEL: in string := "false"; IDIV_SEL: in integer := 0; DYN_FBDIV_SEL: in string := "false"; @@ -79,7 +77,6 @@ architecture Behavioral of Gowin_rPLL is end component; begin - gw_vcc <= '1'; gw_gnd <= '0'; FBDSEL_i <= gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd; @@ -87,19 +84,19 @@ begin ODSEL_i <= gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd; PSDA_i <= gw_gnd & gw_gnd & gw_gnd & gw_gnd; DUTYDA_i <= gw_gnd & gw_gnd & gw_gnd & gw_gnd; - FDLY_i <= gw_vcc & gw_vcc & gw_vcc & gw_vcc; + FDLY_i <= gw_gnd & gw_gnd & gw_gnd & gw_gnd; rpll_inst: rPLL generic map ( FCLKIN => "27", - DEVICE => "GW2AR-18C", + DEVICE => "GW1NR-9C", DYN_IDIV_SEL => "false", - IDIV_SEL => 3, + IDIV_SEL => 2, DYN_FBDIV_SEL => "false", - FBDIV_SEL => 20, + FBDIV_SEL => 15, DYN_ODIV_SEL => "false", ODIV_SEL => 4, - PSDA_SEL => "0100", + PSDA_SEL => "0000", DYN_DA_EN => "false", DUTYDA_SEL => "1000", CLKOUT_FT_DIR => '1', @@ -117,10 +114,10 @@ begin port map ( CLKOUT => clkout, LOCK => lock, - CLKOUTP => clkoutp, + CLKOUTP => clkoutp_o, CLKOUTD => clkoutd_o, CLKOUTD3 => clkoutd3_o, - RESET => reset, + RESET => gw_gnd, RESET_P => gw_gnd, CLKIN => clkin, CLKFB => gw_gnd, diff --git a/src/gowin_sdpb/Hunchy II_ii_ntsc_tn9k.mi b/src/gowin_sdpb/Hunchy II_ii_ntsc_tn9k.mi new file mode 100644 index 0000000..bffb58d --- /dev/null +++ b/src/gowin_sdpb/Hunchy II_ii_ntsc_tn9k.mi @@ -0,0 +1,4099 @@ +#File_format=Hex +#Address_depth=32768 +#Data_width=8 +78 +D8 +A2 +00 +8A +A8 +CA +9A +48 +D0 +FB +20 +A3 +F8 +A9 +02 +85 +02 +85 +00 +85 +02 +85 +02 +4A +85 +02 +85 +00 +A0 +2B +8C +96 +02 +A0 +00 +AD +82 +02 +C5 +84 +F0 +1F +85 +84 +A5 +CC +C9 +0E +B0 +0C +A9 +02 +24 +84 +50 +06 +D0 +04 +84 +FD +84 +81 +A9 +01 +24 +84 +D0 +05 +84 +CD +20 +A3 +F8 +C6 +80 +D0 +06 +A5 +81 +F0 +02 +C6 +81 +A5 +82 +F0 +11 +C6 +82 +F8 +18 +A5 +CF +69 +05 +85 +CF +A5 +CE +69 +00 +85 +CE +D8 +A5 +CC +10 +03 +4C +5A +F9 +A5 +FD +D0 +08 +A5 +81 +85 +82 +E6 +CC +D0 +1C +A5 +D3 +4A +90 +26 +A9 +65 +E5 +D1 +4A +4A +85 +17 +A9 +08 +85 +19 +4A +85 +15 +E6 +85 +C6 +D1 +D0 +0E +C6 +CD +A5 +CC +29 +0F +09 +80 +85 +CC +A9 +5A +85 +89 +4C +92 +F1 +A5 +80 +4A +B0 +F8 +A5 +CC +29 +0F +C9 +0F +D0 +1E +24 +D3 +10 +EC +A5 +86 +C9 +18 +90 +08 +C9 +30 +90 +E2 +E6 +D0 +D0 +DE +A9 +08 +85 +0B +C5 +D0 +B0 +D6 +C6 +D0 +D0 +D2 +24 +D3 +10 +0B +2C +80 +02 +30 +06 +E6 +D0 +A9 +00 +F0 +0D +24 +D3 +50 +1C +2C +80 +02 +70 +17 +C6 +D0 +A9 +08 +85 +0B +A9 +FD +25 +D3 +85 +D3 +A9 +06 +85 +17 +85 +19 +0A +85 +15 +E6 +85 +A9 +20 +25 +D3 +F0 +09 +2C +80 +02 +D0 +04 +C6 +D1 +D0 +0D +A9 +10 +25 +D3 +F0 +1A +2C +80 +02 +D0 +15 +E6 +D1 +A9 +02 +05 +D3 +85 +D3 +A9 +04 +85 +17 +A9 +06 +85 +19 +0A +85 +15 +E6 +85 +A9 +08 +25 +D3 +F0 +35 +A5 +D2 +F0 +1E +38 +A9 +0E +E5 +D2 +85 +17 +A9 +06 +85 +19 +0A +85 +15 +E6 +85 +E6 +D2 +A5 +D2 +C9 +0A +F0 +1D +B0 +17 +E6 +D1 +90 +17 +A9 +04 +25 +D3 +D0 +11 +A5 +0C +30 +0D +A9 +FD +25 +D3 +85 +D3 +A9 +01 +2C +A9 +00 +85 +D2 +A5 +D2 +D0 +1F +A9 +04 +25 +D3 +F0 +19 +C6 +D1 +A9 +65 +E5 +D1 +4A +4A +85 +17 +A9 +06 +85 +19 +0A +85 +15 +E6 +85 +A5 +D3 +29 +FD +85 +D3 +A9 +1F +85 +EE +A5 +85 +D0 +03 +85 +19 +2C +C6 +85 +A0 +01 +A2 +0B +A5 +CC +29 +0F +F0 +08 +C9 +0F +D0 +0B +A0 +04 +A2 +07 +84 +16 +46 +EE +20 +38 +FA +A5 +DA +29 +01 +F0 +61 +A9 +08 +25 +DA +F0 +09 +A5 +80 +4A +B0 +56 +C6 +D7 +90 +52 +C6 +DE +10 +4E +A9 +02 +85 +DE +A9 +10 +25 +DA +F0 +0C +A4 +D7 +88 +88 +C4 +D1 +B0 +04 +E6 +D7 +D0 +38 +A9 +20 +25 +DA +F0 +0C +A4 +D1 +C8 +C8 +C4 +D7 +B0 +04 +C6 +D7 +D0 +26 +A9 +40 +25 +DA +F0 +0E +A5 +D0 +C5 +D6 +B0 +08 +C6 +D6 +A9 +00 +85 +0C +F0 +12 +A9 +80 +25 +DA +F0 +0C +A5 +D6 +C5 +D0 +B0 +06 +E6 +D6 +A9 +08 +85 +0C +A5 +EE +24 +80 +D0 +7F +A5 +ED +29 +07 +F0 +79 +C9 +05 +B0 +34 +C9 +03 +B0 +17 +C9 +01 +F0 +03 +A9 +C3 +2C +A9 +04 +A0 +0B +B6 +DF +D0 +03 +99 +DF +00 +88 +10 +F6 +30 +5A +C9 +03 +F0 +03 +A9 +C3 +2C +A9 +04 +A0 +0B +B6 +DF +F0 +05 +88 +10 +F9 +30 +46 +99 +DF +00 +F0 +41 +A5 +ED +4A +4A +4A +4A +4A +C5 +EC +F0 +36 +20 +EB +F3 +29 +07 +85 +BB +20 +EB +F3 +29 +03 +38 +65 +BB +A8 +B9 +DF +00 +D0 +21 +A5 +ED +29 +07 +C9 +06 +D0 +04 +A9 +C3 +D0 +10 +C9 +05 +D0 +04 +A9 +04 +D0 +08 +A9 +04 +24 +83 +10 +02 +A9 +C3 +99 +DF +00 +E6 +EC +C6 +EF +10 +26 +A5 +ED +29 +18 +4A +4A +4A +85 +EF +A0 +0B +B6 +DF +F0 +14 +30 +07 +E8 +E0 +43 +D0 +0B +F0 +05 +CA +E0 +84 +B0 +04 +C6 +EC +A2 +00 +96 +DF +88 +10 +E5 +A5 +ED +29 +07 +AA +BD +48 +FE +85 +EB +A5 +CC +C9 +0F +D0 +0E +A6 +86 +E0 +4D +90 +04 +A9 +CB +D0 +0F +A9 +D0 +D0 +0B +A5 +80 +4A +4A +4A +29 +07 +AA +BD +40 +FE +85 +FC +A9 +FE +85 +C5 +85 +C9 +85 +CB +A9 +FF +85 +C7 +A0 +06 +A2 +5C +A9 +FD +99 +BD +00 +96 +BC +88 +88 +10 +F7 +A9 +18 +85 +06 +38 +A5 +D1 +AA +E9 +0B +85 +D5 +E0 +60 +90 +03 +09 +80 +AA +86 +D4 +A5 +D3 +29 +03 +F0 +0C +A5 +D1 +29 +04 +4A +4A +AA +BD +E5 +FF +D0 +0A +A5 +D0 +29 +0C +4A +4A +AA +BD +E1 +FF +38 +E5 +D5 +85 +C4 +A5 +D7 +85 +D8 +38 +E9 +0D +85 +D9 +A5 +DA +29 +04 +F0 +15 +A9 +42 +85 +07 +A9 +FE +85 +C7 +A5 +80 +29 +18 +4A +4A +4A +AA +BD +F1 +FF +D0 +3A +A9 +84 +85 +07 +A5 +DA +29 +02 +F0 +15 +A5 +D7 +38 +E9 +11 +85 +D9 +A5 +80 +29 +30 +4A +4A +4A +4A +AA +BD +ED +FF +D0 +1B +A5 +DA +29 +30 +F0 +0C +A5 +D7 +29 +04 +4A +4A +AA +BD +EB +FF +D0 +09 +A5 +D6 +29 +06 +4A +AA +BD +E7 +FF +38 +E5 +D9 +85 +C6 +A5 +D5 +09 +80 +85 +D5 +A5 +D9 +09 +80 +85 +D9 +A2 +00 +A5 +D0 +20 +EC +F4 +A5 +D6 +20 +EC +F4 +85 +02 +85 +2A +A5 +DC +85 +05 +85 +2C +A9 +0B +85 +BA +A2 +00 +A0 +60 +AD +84 +02 +D0 +FB +85 +01 +85 +02 +85 +2B +A9 +C5 +85 +0A +85 +0D +4C +18 +F4 +A5 +83 +0A +90 +02 +49 +CF +85 +83 +60 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +A5 +D5 +8D +D4 +00 +D0 +3B +24 +00 +EA +4C +42 +F4 +A5 +D9 +85 +D8 +D0 +4F +EA +EA +4C +62 +F4 +A9 +FF +85 +0E +85 +0F +85 +02 +86 +1D +A6 +BA +B5 +F0 +38 +E9 +0F +B0 +FC +AA +BD +0F +FE +8D +12 +00 +85 +22 +88 +85 +02 +C4 +D4 +F0 +C5 +10 +CA +B1 +C4 +8D +1B +00 +B1 +BC +85 +0E +B1 +BE +85 +0F +B1 +C2 +85 +0E +B1 +C0 +85 +0F +38 +98 +E9 +09 +85 +BB +C4 +D8 +F0 +B1 +10 +B5 +B1 +C6 +85 +1C +A5 +BA +85 +2A +0A +0A +AA +B1 +BC +85 +0E +B1 +BE +85 +0F +38 +B5 +8A +E5 +BB +85 +BC +EA +38 +B1 +C0 +85 +0F +B1 +C2 +85 +0E +B5 +8B +E5 +BB +85 +BE +38 +B5 +8C +E5 +BB +85 +C0 +88 +C4 +D4 +F0 +42 +10 +46 +B1 +C4 +85 +1B +A9 +00 +85 +0E +85 +0F +38 +B5 +8D +E5 +BB +85 +C2 +A5 +FC +E5 +BB +85 +CA +A6 +BA +A5 +EB +E5 +BB +85 +C8 +C4 +D8 +F0 +28 +10 +2C +B1 +C6 +85 +1C +85 +2B +88 +B5 +DF +0A +E9 +0F +B0 +FC +AA +BD +0F +FE +A2 +06 +85 +13 +85 +23 +4C +3B +F5 +A5 +D5 +85 +D4 +D0 +BE +EA +EA +4C +9A +F4 +A5 +D9 +85 +D8 +D0 +D8 +EA +EA +4C +BF +F4 +85 +02 +38 +E9 +0F +B0 +FC +EA +A8 +B9 +0F +FE +95 +20 +95 +10 +E8 +60 +00 +00 +A5 +D5 +8D +D4 +00 +D0 +41 +24 +00 +EA +4C +48 +F5 +A5 +D9 +8D +D8 +00 +D0 +52 +24 +00 +EA +4C +66 +F5 +A5 +D9 +85 +D8 +D0 +11 +EA +EA +4C +31 +F5 +C6 +BA +C4 +D8 +F0 +EF +10 +F3 +B1 +C6 +85 +1C +4C +20 +F4 +B1 +C8 +85 +23 +4C +91 +F5 +85 +02 +C4 +D4 +F0 +BF +10 +C4 +B1 +C4 +8D +1B +00 +B1 +BC +85 +0E +B1 +BE +85 +0F +B1 +C2 +85 +0E +B1 +C0 +85 +0F +CA +F0 +CA +C4 +D8 +F0 +AE +10 +B3 +B1 +C6 +8D +1C +00 +B1 +CA +85 +22 +85 +2A +85 +1D +0A +0A +85 +04 +24 +00 +B1 +BC +85 +0E +B1 +BE +85 +0F +B1 +C2 +85 +0E +B1 +C0 +85 +0F +88 +C4 +DB +10 +AB +A5 +DD +85 +05 +A9 +00 +EA +EA +8D +1E +00 +C0 +01 +D0 +A5 +88 +84 +0D +84 +1B +84 +1D +A0 +03 +84 +0A +EA +A6 +CD +BD +EE +FC +85 +0E +BD +F6 +FC +85 +0F +A5 +81 +4A +AA +BD +00 +FE +85 +0F +BD +F0 +FD +85 +0E +85 +02 +EA +EA +EA +EA +EA +EA +88 +D0 +DB +84 +0E +84 +0F +A9 +02 +85 +02 +85 +01 +A0 +23 +8C +96 +02 +A5 +01 +30 +10 +A5 +D1 +C9 +0B +90 +0A +A5 +DA +29 +04 +D0 +0A +A5 +07 +10 +06 +A5 +D3 +09 +01 +85 +D3 +4C +66 +F6 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +85 +02 +A0 +09 +84 +BA +A0 +03 +84 +25 +84 +26 +84 +04 +84 +05 +A9 +0C +85 +06 +85 +07 +A9 +10 +85 +0B +85 +0C +85 +21 +85 +10 +85 +11 +85 +21 +C8 +B1 +BC +85 +1B +B1 +BE +84 +02 +84 +2A +D0 +0A +A5 +BA +4A +A8 +B1 +BC +85 +1B +B1 +BE +85 +1C +B1 +C0 +85 +1B +B1 +C2 +AA +B1 +C4 +85 +BB +B1 +C6 +A8 +A5 +BB +86 +1C +85 +1B +84 +1C +85 +1B +C6 +BA +10 +D8 +A9 +00 +85 +1B +85 +1C +85 +1B +85 +25 +85 +26 +60 +A5 +D3 +29 +03 +09 +CC +85 +D3 +29 +01 +F0 +03 +4C +A5 +F7 +A5 +D0 +C9 +89 +B0 +21 +69 +07 +AA +38 +A5 +D1 +E9 +03 +20 +74 +F8 +C9 +01 +F0 +12 +18 +A5 +D0 +69 +07 +AA +38 +A5 +D1 +E9 +08 +20 +74 +F8 +C9 +01 +D0 +06 +A5 +D3 +29 +7F +85 +D3 +A6 +D0 +E0 +10 +90 +1A +38 +A5 +D1 +E9 +03 +20 +74 +F8 +C9 +01 +F0 +0E +A6 +D0 +38 +A5 +D1 +E9 +08 +20 +74 +F8 +C9 +01 +D0 +06 +A5 +D3 +29 +BF +85 +D3 +A5 +D1 +C9 +0B +90 +38 +E9 +09 +A6 +D0 +E8 +20 +74 +F8 +C9 +01 +F0 +2C +C9 +00 +F0 +08 +A5 +D3 +29 +DB +09 +20 +85 +D3 +18 +A5 +D0 +69 +06 +AA +38 +A5 +D1 +E9 +09 +20 +74 +F8 +C9 +01 +F0 +0E +C9 +00 +F0 +10 +A5 +D3 +29 +DB +09 +20 +85 +D3 +D0 +06 +A5 +D3 +29 +DB +85 +D3 +18 +A5 +D0 +69 +06 +AA +A5 +D1 +C9 +60 +B0 +2F +38 +E9 +02 +20 +74 +F8 +C9 +01 +F0 +25 +C9 +02 +D0 +06 +A5 +D3 +09 +10 +85 +D3 +A6 +D0 +E8 +38 +A5 +D1 +E9 +02 +20 +74 +F8 +C9 +01 +F0 +0C +C9 +02 +D0 +0E +A5 +D3 +09 +10 +85 +D3 +D0 +06 +A5 +D3 +29 +E7 +85 +D3 +A5 +00 +29 +40 +F0 +52 +18 +A5 +D0 +69 +06 +85 +D5 +38 +A5 +D1 +E9 +01 +4A +4A +4A +A8 +B9 +F0 +00 +F0 +1C +18 +69 +07 +85 +D4 +C5 +D0 +30 +04 +C5 +D5 +30 +18 +18 +69 +08 +85 +D5 +A5 +D0 +C5 +D4 +30 +04 +C5 +D5 +30 +09 +38 +A5 +D1 +E9 +08 +4A +4A +4A +A8 +B9 +F0 +00 +F0 +13 +A9 +0C +85 +19 +85 +15 +A9 +02 +85 +17 +85 +85 +A9 +00 +99 +F0 +00 +C6 +FD +A5 +DA +29 +07 +09 +F8 +85 +DA +A5 +D6 +C9 +88 +B0 +21 +69 +08 +AA +38 +A5 +D7 +E9 +03 +20 +74 +F8 +C9 +01 +F0 +12 +18 +A5 +D6 +69 +08 +AA +38 +A5 +D7 +E9 +0A +20 +74 +F8 +C9 +01 +D0 +06 +A5 +DA +29 +7F +85 +DA +A6 +D6 +E0 +11 +90 +1C +CA +38 +A5 +D7 +E9 +03 +20 +74 +F8 +C9 +01 +F0 +0F +A6 +D6 +CA +38 +A5 +D7 +E9 +0A +20 +74 +F8 +C9 +01 +D0 +06 +A5 +DA +29 +BF +85 +DA +A5 +D7 +C9 +0F +90 +34 +E9 +0B +A6 +D6 +20 +74 +F8 +C9 +01 +F0 +29 +C9 +02 +D0 +06 +A5 +DA +29 +F7 +85 +DA +18 +A5 +D6 +69 +07 +AA +38 +A5 +D7 +E9 +0B +20 +74 +F8 +C9 +01 +F0 +0D +C9 +02 +D0 +0F +A5 +DA +29 +F7 +85 +DA +4C +42 +F8 +A5 +DA +29 +D7 +85 +DA +18 +A5 +D6 +69 +07 +AA +A5 +D7 +C9 +60 +B0 +18 +38 +E9 +02 +20 +74 +F8 +C9 +02 +D0 +0E +A6 +D6 +38 +A5 +D7 +E9 +02 +20 +74 +F8 +C9 +02 +F0 +06 +A5 +DA +29 +EF +85 +DA +AD +84 +02 +D0 +FB +4C +0E +F0 +4A +29 +FC +85 +BA +38 +8A +E9 +10 +30 +23 +4A +4A +4A +AA +4A +4A +18 +65 +BA +A8 +B9 +8A +00 +85 +C4 +A9 +FD +85 +C5 +A0 +00 +B1 +C4 +BC +30 +FE +F0 +05 +4A +4A +88 +D0 +FB +29 +03 +60 +A5 +CC +29 +0F +A6 +CD +D0 +0B +8A +85 +FD +85 +CE +85 +CF +A2 +04 +86 +CD +85 +CC +0A +AA +BD +10 +FE +85 +C4 +BD +11 +FE +85 +C5 +A0 +00 +84 +80 +84 +D3 +84 +D2 +84 +EC +84 +88 +84 +86 +84 +87 +E6 +87 +A2 +0B +94 +DF +CA +10 +FB +B1 +C4 +BE +50 +FE +F0 +05 +95 +00 +C8 +D0 +F4 +A5 +FD +D0 +22 +E8 +B1 +C4 +0A +0A +0A +95 +F0 +F0 +02 +E6 +FD +E8 +C8 +E0 +0C +90 +EF +A2 +00 +A5 +CC +29 +0F +F0 +06 +C9 +0F +F0 +02 +A2 +1F +86 +81 +A0 +0F +84 +83 +A5 +CC +C9 +0F +F0 +25 +A9 +FC +85 +C7 +A0 +00 +A2 +00 +18 +B1 +C6 +29 +0F +0A +0A +0A +69 +68 +95 +8A +E8 +B1 +C6 +29 +F0 +4A +69 +68 +95 +8A +E8 +C8 +E0 +30 +90 +E5 +60 +A2 +2F +A9 +68 +95 +8A +CA +10 +FB +A9 +C0 +85 +8A +85 +8B +85 +8D +A9 +64 +85 +8C +A9 +67 +85 +8E +85 +90 +60 +A9 +FF +A0 +0A +99 +BD +00 +88 +88 +10 +F9 +A5 +CD +D0 +1A +A9 +0F +85 +BC +85 +C6 +A9 +23 +85 +BE +A9 +28 +85 +C0 +A9 +2D +85 +C2 +A9 +32 +85 +C4 +A2 +42 +D0 +41 +A9 +14 +85 +BC +A9 +19 +85 +BE +A9 +1E +85 +C0 +A9 +0F +85 +C2 +A5 +CC +29 +0F +85 +BA +A9 +00 +85 +BB +A2 +08 +F8 +06 +BA +A5 +BB +65 +BB +85 +BB +CA +D0 +F5 +D8 +29 +F0 +4A +4A +4A +4A +AA +BD +37 +FF +85 +C4 +A5 +BB +29 +0F +AA +BD +37 +FF +85 +C6 +A2 +84 +86 +08 +A9 +01 +85 +0A +AD +84 +02 +D0 +FB +85 +01 +85 +02 +85 +19 +85 +1A +85 +0D +A9 +FF +85 +0E +85 +0F +20 +00 +F6 +A9 +03 +85 +BB +A5 +BB +0A +A8 +4A +4A +AA +B5 +CE +B0 +07 +29 +F0 +4A +4A +4A +4A +2C +29 +0F +AA +BD +37 +FF +99 +BE +00 +C6 +BB +10 +E1 +A9 +0F +85 +BC +85 +C6 +20 +00 +F6 +85 +02 +85 +0E +85 +0F +A2 +A6 +85 +02 +CA +D0 +FB +A9 +02 +85 +02 +85 +01 +A0 +23 +8C +96 +02 +A5 +89 +F0 +04 +C6 +89 +D0 +07 +A5 +0C +30 +03 +20 +A3 +F8 +4C +6C +F8 +C6 +87 +30 +03 +4C +C4 +FA +86 +87 +C9 +0F +D0 +5C +A5 +86 +C9 +5C +D0 +04 +A2 +68 +86 +8E +C9 +47 +F0 +0C +C9 +41 +F0 +08 +C9 +3B +F0 +04 +C9 +35 +D0 +02 +C6 +8C +C9 +2F +D0 +07 +A2 +68 +86 +90 +CA +86 +8F +C9 +1C +90 +21 +C9 +24 +B0 +1D +A9 +00 +85 +F2 +A9 +E7 +85 +ED +A2 +1B +B5 +96 +95 +9A +CA +10 +F9 +A5 +86 +29 +07 +AA +BD +58 +FD +85 +97 +85 +98 +A5 +86 +C9 +17 +D0 +04 +A2 +68 +86 +8F +C9 +01 +D0 +02 +C6 +FD +C6 +86 +10 +04 +A9 +5F +85 +86 +A5 +86 +4A +AA +BD +CE +FA +B0 +04 +4A +4A +4A +4A +29 +0F +F0 +0A +AA +BD +FF +FA +85 +18 +A9 +1A +85 +88 +A5 +88 +F0 +05 +C6 +88 +4A +85 +1A +60 +00 +00 +67 +89 +AB +54 +0B +9B +96 +0B +60 +9B +09 +69 +B6 +05 +60 +56 +04 +23 +42 +01 +20 +12 +00 +00 +64 +05 +45 +64 +05 +40 +65 +45 +40 +6B +00 +00 +96 +07 +67 +96 +07 +60 +97 +67 +60 +97 +00 +00 +0D +0F +11 +12 +14 +17 +18 +1A +1B +1D +1F +16 +84 +07 +20 +20 +1E +20 +10 +36 +32 +05 +08 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +2E +D4 +3D +20 +00 +00 +88 +60 +14 +00 +00 +10 +01 +0E +00 +00 +10 +0A +00 +0D +02 +07 +46 +24 +5D +20 +00 +00 +88 +38 +14 +00 +00 +00 +0D +01 +07 +0D +00 +07 +01 +00 +0F +07 +5E +04 +55 +20 +02 +3C +88 +10 +49 +32 +00 +07 +05 +01 +0A +04 +0A +0E +01 +00 +08 +00 +76 +92 +3F +20 +00 +00 +60 +20 +14 +00 +00 +01 +05 +10 +09 +00 +10 +05 +0C +09 +01 +0B +8E +F4 +56 +20 +00 +00 +18 +10 +31 +42 +00 +10 +00 +02 +09 +07 +04 +01 +00 +04 +0E +07 +A6 +54 +5F +20 +00 +00 +40 +58 +58 +26 +02 +02 +0E +05 +09 +01 +0C +0A +01 +09 +10 +0B +2E +D4 +7F +20 +00 +00 +28 +28 +32 +12 +01 +01 +0F +10 +00 +00 +0E +04 +0B +0F +02 +0B +46 +24 +95 +20 +20 +32 +32 +20 +32 +12 +01 +09 +01 +09 +10 +00 +09 +07 +0E +00 +01 +10 +5E +04 +B3 +10 +02 +50 +88 +10 +48 +36 +02 +00 +06 +00 +07 +10 +01 +0A +03 +00 +09 +10 +76 +92 +9D +20 +00 +00 +60 +10 +38 +46 +02 +07 +09 +0B +04 +09 +01 +0D +09 +01 +0A +10 +00 +00 +00 +8E +F4 +D7 +20 +00 +00 +28 +10 +54 +42 +01 +01 +0D +04 +07 +09 +01 +0E +10 +08 +0B +01 +BB +B1 +00 +70 +00 +70 +00 +B9 +50 +02 +41 +32 +41 +39 +41 +57 +47 +37 +49 +36 +67 +74 +04 +74 +BB +BB +F0 +00 +F0 +20 +D9 +7B +F0 +00 +F0 +20 +D5 +04 +F0 +05 +F0 +70 +D4 +0A +F0 +20 +00 +00 +BB +BB +FE +FE +DE +FC +FE +FE +0E +00 +BC +6B +FE +0E +0E +3E +FE +7E +DC +7C +FE +2E +00 +00 +78 +25 +0E +90 +0E +05 +7E +00 +2E +21 +9E +9A +00 +F0 +08 +F0 +00 +F0 +B9 +DB +00 +00 +00 +00 +78 +79 +0E +04 +6C +D9 +0E +F4 +B0 +D9 +0C +F4 +31 +01 +0C +0C +7E +D4 +01 +F4 +AE +08 +08 +71 +BB +BB +00 +F0 +00 +F0 +B8 +DB +2E +FE +2E +0E +B0 +7C +F0 +0E +F1 +91 +FE +3A +FC +04 +00 +00 +94 +09 +01 +30 +2E +0A +0C +08 +3E +F0 +BE +D0 +01 +0A +F0 +05 +F4 +F1 +D1 +D0 +08 +3A +00 +01 +A1 +34 +70 +08 +0E +00 +0E +0E +6E +3C +0C +20 +A0 +3B +34 +0E +34 +20 +B4 +0C +00 +00 +70 +28 +B8 +30 +F0 +00 +01 +F0 +2E +FE +04 +00 +0E +0E +F1 +A0 +00 +3E +04 +30 +F0 +0E +D1 +0C +00 +00 +00 +40 +50 +54 +55 +55 +55 +55 +00 +00 +00 +00 +00 +02 +0A +2A +00 +00 +A6 +54 +7A +20 +20 +48 +40 +10 +14 +00 +00 +0A +01 +10 +07 +0B +00 +01 +0D +02 +10 +0B +BE +B4 +7D +20 +26 +1C +28 +38 +38 +16 +02 +10 +09 +01 +0D +07 +10 +07 +05 +10 +09 +01 +D6 +50 +96 +10 +00 +00 +28 +20 +48 +2E +02 +0F +01 +09 +0B +10 +09 +0D +01 +09 +10 +06 +16 +44 +00 +20 +20 +1E +12 +10 +80 +12 +05 +00 +08 +00 +00 +00 +00 +00 +00 +00 +00 +00 +C0 +C0 +C0 +E8 +68 +78 +98 +B8 +55 +00 +00 +00 +00 +00 +AA +55 +00 +00 +00 +00 +00 +00 +00 +00 +01 +00 +00 +00 +03 +02 +01 +03 +40 +00 +00 +00 +C0 +40 +80 +C0 +04 +00 +00 +00 +0C +04 +08 +0C +10 +00 +00 +00 +30 +20 +10 +30 +05 +00 +00 +00 +0F +06 +09 +0F +50 +00 +00 +00 +F0 +60 +90 +F0 +11 +00 +00 +00 +33 +22 +11 +33 +44 +00 +00 +00 +CC +44 +88 +CC +15 +00 +00 +00 +3F +26 +19 +3F +54 +00 +00 +00 +FC +64 +98 +FC +55 +00 +00 +00 +FF +66 +99 +FF +59 +00 +00 +0C +F3 +62 +91 +FF +65 +00 +00 +30 +CF +46 +89 +FF +08 +00 +00 +0C +00 +00 +00 +0C +20 +00 +00 +30 +00 +00 +00 +30 +14 +00 +00 +00 +3C +24 +18 +3C +00 +40 +60 +70 +78 +7C +7E +7F +7F +7F +7F +7F +7F +7F +7F +7F +00 +00 +00 +00 +00 +00 +00 +00 +00 +01 +03 +07 +0F +1F +3F +7F +0B +FB +21 +FB +37 +FB +4D +FB +63 +FB +79 +FB +8F +FB +A5 +FB +BB +FB +D1 +FB +E7 +FB +00 +FC +00 +FD +16 +FD +2C +FD +42 +FD +03 +02 +01 +00 +00 +01 +02 +03 +03 +02 +01 +00 +00 +01 +02 +03 +D5 +DA +DF +E4 +E4 +DF +DA +D5 +F8 +EC +F2 +EC +F2 +EC +F2 +F8 +C6 +08 +ED +DC +DD +DB +D0 +D1 +D6 +D7 +DA +00 +00 +00 +00 +00 +00 +1C +18 +1C +36 +6E +6E +3C +12 +3A +1C +00 +24 +4E +1C +1E +5E +6E +3C +12 +3A +1C +00 +24 +72 +3C +3E +72 +6E +3C +12 +3A +1C +00 +30 +36 +3E +3E +3C +3E +7A +66 +64 +58 +00 +0C +6C +7C +7C +3C +7C +5E +66 +26 +1A +00 +3E +3E +3E +3C +3C +3A +32 +7C +38 +14 +34 +38 +00 +3E +3C +3C +3C +38 +32 +32 +7C +3A +14 +34 +38 +00 +3E +3E +3C +3C +38 +3A +32 +7C +3A +12 +34 +38 +00 +3E +3E +3E +3C +3C +3A +32 +7C +3A +12 +34 +38 +02 +02 +02 +F2 +F2 +D2 +0E +3E +12 +12 +D2 +0E +3E +E2 +2E +0A +1A +06 +D2 +2E +0A +1A +06 +C2 +2E +0A +1A +06 +B2 +2E +0A +1A +06 +00 +00 +00 +04 +16 +F6 +00 +00 +00 +04 +F6 +16 +00 +00 +00 +04 +16 +16 +00 +00 +62 +52 +42 +32 +22 +12 +02 +F2 +E2 +D2 +C2 +B2 +A2 +92 +82 +00 +00 +00 +00 +00 +EE +88 +8C +88 +8E +4E +48 +AC +A8 +AE +E0 +86 +80 +86 +80 +6A +AA +AE +8A +64 +AE +A8 +AC +E8 +AE +44 +A4 +AA +AA +4A +EA +8A +CC +8A +EC +46 +41 +52 +4A +44 +54 +50 +42 +4E +4C +0C +0C +0C +0C +0C +78 +CC +CC +CC +78 +0C +78 +0C +78 +CC +78 +CC +78 +C0 +78 +0C +78 +C0 +78 +00 +00 +00 +00 +00 +00 +00 +00 +AC +8C +BC +AE +AE +86 +AE +BE +EC +84 +3C +18 +00 +18 +98 +BC +AC +AD +85 +AF +BE +AC +C4 +BC +18 +00 +34 +30 +BC +AC +AD +85 +AF +BE +AC +84 +FC +98 +00 +18 +98 +BC +AE +AE +86 +AE +BE +AC +C4 +BC +18 +00 +0C +6C +FC +EC +AD +85 +AF +BE +AC +84 +FC +98 +00 +B0 +B6 +BE +B6 +B4 +A0 +B6 +BF +F5 +A1 +3C +18 +00 +56 +46 +5E +57 +57 +43 +57 +5F +76 +42 +1E +0C +00 +00 +00 +00 +00 +16 +06 +1E +97 +97 +83 +97 +5F +56 +42 +5E +6C +40 +00 +00 +00 +00 +16 +06 +1E +17 +17 +03 +97 +9F +96 +42 +5E +4C +20 +20 +18 +10 +60 +6B +60 +76 +81 +8C +60 +6D +7A +87 +94 +A1 +AE +BF +D0 +BF +97 +A4 +B1 +BE +00 +00 +00 +00 +00 +00 +F0 +00 +F0 +00 +F0 \ No newline at end of file diff --git a/src/gowin_sdpb/gowin_sdpb_tn9k.ipc b/src/gowin_sdpb/gowin_sdpb_tn9k.ipc new file mode 100644 index 0000000..26239c1 --- /dev/null +++ b/src/gowin_sdpb/gowin_sdpb_tn9k.ipc @@ -0,0 +1,19 @@ +[General] +ipc_version=4 +file=gowin_sdpb_tn9k +module=Gowin_SDPB +target_device=gw1nr9c-004 +type=ram_sdpb +version=1.0 + +[Config] +BYTE_SIZE=0 +DEPTH_A=32768 +DEPTH_B=32768 +LANG=1 +READ=0 +RESET_MODE=true +WIDTH_A=8 +WIDTH_B=8 +DIMENSION_MATCH=65 +MEM_FILE=Hunchy II_ii_ntsc_tn9k.mi diff --git a/src/gowin_sdpb/gowin_sdpb_tn9k.vhd b/src/gowin_sdpb/gowin_sdpb_tn9k.vhd new file mode 100644 index 0000000..74b1156 --- /dev/null +++ b/src/gowin_sdpb/gowin_sdpb_tn9k.vhd @@ -0,0 +1,925 @@ +--Copyright (C)2014-2024 Gowin Semiconductor Corporation. +--All rights reserved. +--File Title: IP file +--Tool Version: V1.9.10.03 (64-bit) +--Part Number: GW1NR-LV9QN88PC6/I5 +--Device: GW1NR-9 +--Device Version: C +--Created Time: Sun Dec 15 14:37:36 2024 + +library IEEE; +use IEEE.std_logic_1164.all; + +entity Gowin_SDPB is + port ( + dout: out std_logic_vector(7 downto 0); + clka: in std_logic; + cea: in std_logic; + reseta: in std_logic; + clkb: in std_logic; + ceb: in std_logic; + resetb: in std_logic; + oce: in std_logic; + ada: in std_logic_vector(14 downto 0); + din: in std_logic_vector(7 downto 0); + adb: in std_logic_vector(14 downto 0) + ); +end Gowin_SDPB; + +architecture Behavioral of Gowin_SDPB is + + signal sdpb_inst_0_dout_w: std_logic_vector(30 downto 0); + signal sdpb_inst_0_dout: std_logic_vector(0 downto 0); + signal sdpb_inst_1_dout_w: std_logic_vector(30 downto 0); + signal sdpb_inst_1_dout: std_logic_vector(0 downto 0); + signal sdpb_inst_2_dout_w: std_logic_vector(30 downto 0); + signal sdpb_inst_2_dout: std_logic_vector(1 downto 1); + signal sdpb_inst_3_dout_w: std_logic_vector(30 downto 0); + signal sdpb_inst_3_dout: std_logic_vector(1 downto 1); + signal sdpb_inst_4_dout_w: std_logic_vector(30 downto 0); + signal sdpb_inst_4_dout: std_logic_vector(2 downto 2); + signal sdpb_inst_5_dout_w: std_logic_vector(30 downto 0); + signal sdpb_inst_5_dout: std_logic_vector(2 downto 2); + signal sdpb_inst_6_dout_w: std_logic_vector(30 downto 0); + signal sdpb_inst_6_dout: std_logic_vector(3 downto 3); + signal sdpb_inst_7_dout_w: std_logic_vector(30 downto 0); + signal sdpb_inst_7_dout: std_logic_vector(3 downto 3); + signal sdpb_inst_8_dout_w: std_logic_vector(30 downto 0); + signal sdpb_inst_8_dout: std_logic_vector(4 downto 4); + signal sdpb_inst_9_dout_w: std_logic_vector(30 downto 0); + signal sdpb_inst_9_dout: std_logic_vector(4 downto 4); + signal sdpb_inst_10_dout_w: std_logic_vector(30 downto 0); + signal sdpb_inst_10_dout: std_logic_vector(5 downto 5); + signal sdpb_inst_11_dout_w: std_logic_vector(30 downto 0); + signal sdpb_inst_11_dout: std_logic_vector(5 downto 5); + signal sdpb_inst_12_dout_w: std_logic_vector(30 downto 0); + signal sdpb_inst_12_dout: std_logic_vector(6 downto 6); + signal sdpb_inst_13_dout_w: std_logic_vector(30 downto 0); + signal sdpb_inst_13_dout: std_logic_vector(6 downto 6); + signal sdpb_inst_14_dout_w: std_logic_vector(30 downto 0); + signal sdpb_inst_14_dout: std_logic_vector(7 downto 7); + signal sdpb_inst_15_dout_w: std_logic_vector(30 downto 0); + signal sdpb_inst_15_dout: std_logic_vector(7 downto 7); + signal dff_q_0: std_logic; + signal gw_gnd: std_logic; + signal sdpb_inst_0_BLKSELA_i: std_logic_vector(2 downto 0); + signal sdpb_inst_0_BLKSELB_i: std_logic_vector(2 downto 0); + signal sdpb_inst_0_DI_i: std_logic_vector(31 downto 0); + signal sdpb_inst_0_DO_o: std_logic_vector(31 downto 0); + signal sdpb_inst_1_BLKSELA_i: std_logic_vector(2 downto 0); + signal sdpb_inst_1_BLKSELB_i: std_logic_vector(2 downto 0); + signal sdpb_inst_1_DI_i: std_logic_vector(31 downto 0); + signal sdpb_inst_1_DO_o: std_logic_vector(31 downto 0); + signal sdpb_inst_2_BLKSELA_i: std_logic_vector(2 downto 0); + signal sdpb_inst_2_BLKSELB_i: std_logic_vector(2 downto 0); + signal sdpb_inst_2_DI_i: std_logic_vector(31 downto 0); + signal sdpb_inst_2_DO_o: std_logic_vector(31 downto 0); + signal sdpb_inst_3_BLKSELA_i: std_logic_vector(2 downto 0); + signal sdpb_inst_3_BLKSELB_i: std_logic_vector(2 downto 0); + signal sdpb_inst_3_DI_i: std_logic_vector(31 downto 0); + signal sdpb_inst_3_DO_o: std_logic_vector(31 downto 0); + signal sdpb_inst_4_BLKSELA_i: std_logic_vector(2 downto 0); + signal sdpb_inst_4_BLKSELB_i: std_logic_vector(2 downto 0); + signal sdpb_inst_4_DI_i: std_logic_vector(31 downto 0); + signal sdpb_inst_4_DO_o: std_logic_vector(31 downto 0); + signal sdpb_inst_5_BLKSELA_i: std_logic_vector(2 downto 0); + signal sdpb_inst_5_BLKSELB_i: std_logic_vector(2 downto 0); + signal sdpb_inst_5_DI_i: std_logic_vector(31 downto 0); + signal sdpb_inst_5_DO_o: std_logic_vector(31 downto 0); + signal sdpb_inst_6_BLKSELA_i: std_logic_vector(2 downto 0); + signal sdpb_inst_6_BLKSELB_i: std_logic_vector(2 downto 0); + signal sdpb_inst_6_DI_i: std_logic_vector(31 downto 0); + signal sdpb_inst_6_DO_o: std_logic_vector(31 downto 0); + signal sdpb_inst_7_BLKSELA_i: std_logic_vector(2 downto 0); + signal sdpb_inst_7_BLKSELB_i: std_logic_vector(2 downto 0); + signal sdpb_inst_7_DI_i: std_logic_vector(31 downto 0); + signal sdpb_inst_7_DO_o: std_logic_vector(31 downto 0); + signal sdpb_inst_8_BLKSELA_i: std_logic_vector(2 downto 0); + signal sdpb_inst_8_BLKSELB_i: std_logic_vector(2 downto 0); + signal sdpb_inst_8_DI_i: std_logic_vector(31 downto 0); + signal sdpb_inst_8_DO_o: std_logic_vector(31 downto 0); + signal sdpb_inst_9_BLKSELA_i: std_logic_vector(2 downto 0); + signal sdpb_inst_9_BLKSELB_i: std_logic_vector(2 downto 0); + signal sdpb_inst_9_DI_i: std_logic_vector(31 downto 0); + signal sdpb_inst_9_DO_o: std_logic_vector(31 downto 0); + signal sdpb_inst_10_BLKSELA_i: std_logic_vector(2 downto 0); + signal sdpb_inst_10_BLKSELB_i: std_logic_vector(2 downto 0); + signal sdpb_inst_10_DI_i: std_logic_vector(31 downto 0); + signal sdpb_inst_10_DO_o: std_logic_vector(31 downto 0); + signal sdpb_inst_11_BLKSELA_i: std_logic_vector(2 downto 0); + signal sdpb_inst_11_BLKSELB_i: std_logic_vector(2 downto 0); + signal sdpb_inst_11_DI_i: std_logic_vector(31 downto 0); + signal sdpb_inst_11_DO_o: std_logic_vector(31 downto 0); + signal sdpb_inst_12_BLKSELA_i: std_logic_vector(2 downto 0); + signal sdpb_inst_12_BLKSELB_i: std_logic_vector(2 downto 0); + signal sdpb_inst_12_DI_i: std_logic_vector(31 downto 0); + signal sdpb_inst_12_DO_o: std_logic_vector(31 downto 0); + signal sdpb_inst_13_BLKSELA_i: std_logic_vector(2 downto 0); + signal sdpb_inst_13_BLKSELB_i: std_logic_vector(2 downto 0); + signal sdpb_inst_13_DI_i: std_logic_vector(31 downto 0); + signal sdpb_inst_13_DO_o: std_logic_vector(31 downto 0); + signal sdpb_inst_14_BLKSELA_i: std_logic_vector(2 downto 0); + signal sdpb_inst_14_BLKSELB_i: std_logic_vector(2 downto 0); + signal sdpb_inst_14_DI_i: std_logic_vector(31 downto 0); + signal sdpb_inst_14_DO_o: std_logic_vector(31 downto 0); + signal sdpb_inst_15_BLKSELA_i: std_logic_vector(2 downto 0); + signal sdpb_inst_15_BLKSELB_i: std_logic_vector(2 downto 0); + signal sdpb_inst_15_DI_i: std_logic_vector(31 downto 0); + signal sdpb_inst_15_DO_o: std_logic_vector(31 downto 0); + + --component declaration + component SDPB + generic ( + READ_MODE: in bit := '0'; + BIT_WIDTH_0: in integer :=16; + BIT_WIDTH_1: in integer :=16; + BLK_SEL_0: in bit_vector := "000"; + BLK_SEL_1: in bit_vector := "000"; + RESET_MODE: in string := "SYNC"; + INIT_RAM_00: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_01: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_02: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_03: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_04: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_05: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_06: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_07: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_08: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_09: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_0A: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_0B: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_0C: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_0D: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_0E: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_0F: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_10: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_11: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_12: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_13: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_14: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_15: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_16: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_17: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_18: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_19: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_1A: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_1B: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_1C: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_1D: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_1E: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_1F: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_20: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_21: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_22: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_23: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_24: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_25: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_26: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_27: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_28: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_29: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_2A: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_2B: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_2C: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_2D: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_2E: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_2F: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_30: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_31: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_32: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_33: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_34: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_35: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_36: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_37: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_38: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_39: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_3A: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_3B: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_3C: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_3D: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_3E: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; + INIT_RAM_3F: in bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" + ); + port ( + DO: out std_logic_vector(31 downto 0); + CLKA: in std_logic; + CEA: in std_logic; + RESETA: in std_logic; + CLKB: in std_logic; + CEB: in std_logic; + RESETB: in std_logic; + OCE: in std_logic; + BLKSELA: in std_logic_vector(2 downto 0); + BLKSELB: in std_logic_vector(2 downto 0); + ADA: in std_logic_vector(13 downto 0); + DI: in std_logic_vector(31 downto 0); + ADB: in std_logic_vector(13 downto 0) + ); + end component; + + -- component declaration + component DFFE + port ( + Q: out std_logic; + D: in std_logic; + CLK: in std_logic; + CE: in std_logic + ); + end component; + + -- component declaration + component MUX2 + port ( + O: out std_logic; + I0: in std_logic; + I1: in std_logic; + S0: in std_logic + ); + end component; + +begin + gw_gnd <= '0'; + + sdpb_inst_0_BLKSELA_i <= gw_gnd & gw_gnd & ada(14); + sdpb_inst_0_BLKSELB_i <= gw_gnd & gw_gnd & adb(14); + sdpb_inst_0_DI_i <= gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & din(0); + sdpb_inst_0_dout(0) <= sdpb_inst_0_DO_o(0); + sdpb_inst_0_dout_w(30 downto 0) <= sdpb_inst_0_DO_o(31 downto 1) ; + sdpb_inst_1_BLKSELA_i <= gw_gnd & gw_gnd & ada(14); + sdpb_inst_1_BLKSELB_i <= gw_gnd & gw_gnd & adb(14); + sdpb_inst_1_DI_i <= gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & din(0); + sdpb_inst_1_dout(0) <= sdpb_inst_1_DO_o(0); + sdpb_inst_1_dout_w(30 downto 0) <= sdpb_inst_1_DO_o(31 downto 1) ; + sdpb_inst_2_BLKSELA_i <= gw_gnd & gw_gnd & ada(14); + sdpb_inst_2_BLKSELB_i <= gw_gnd & gw_gnd & adb(14); + sdpb_inst_2_DI_i <= gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & din(1); + sdpb_inst_2_dout(1) <= sdpb_inst_2_DO_o(0); + sdpb_inst_2_dout_w(30 downto 0) <= sdpb_inst_2_DO_o(31 downto 1) ; + sdpb_inst_3_BLKSELA_i <= gw_gnd & gw_gnd & ada(14); + sdpb_inst_3_BLKSELB_i <= gw_gnd & gw_gnd & adb(14); + sdpb_inst_3_DI_i <= gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & din(1); + sdpb_inst_3_dout(1) <= sdpb_inst_3_DO_o(0); + sdpb_inst_3_dout_w(30 downto 0) <= sdpb_inst_3_DO_o(31 downto 1) ; + sdpb_inst_4_BLKSELA_i <= gw_gnd & gw_gnd & ada(14); + sdpb_inst_4_BLKSELB_i <= gw_gnd & gw_gnd & adb(14); + sdpb_inst_4_DI_i <= gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & din(2); + sdpb_inst_4_dout(2) <= sdpb_inst_4_DO_o(0); + sdpb_inst_4_dout_w(30 downto 0) <= sdpb_inst_4_DO_o(31 downto 1) ; + sdpb_inst_5_BLKSELA_i <= gw_gnd & gw_gnd & ada(14); + sdpb_inst_5_BLKSELB_i <= gw_gnd & gw_gnd & adb(14); + sdpb_inst_5_DI_i <= gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & din(2); + sdpb_inst_5_dout(2) <= sdpb_inst_5_DO_o(0); + sdpb_inst_5_dout_w(30 downto 0) <= sdpb_inst_5_DO_o(31 downto 1) ; + sdpb_inst_6_BLKSELA_i <= gw_gnd & gw_gnd & ada(14); + sdpb_inst_6_BLKSELB_i <= gw_gnd & gw_gnd & adb(14); + sdpb_inst_6_DI_i <= gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & din(3); + sdpb_inst_6_dout(3) <= sdpb_inst_6_DO_o(0); + sdpb_inst_6_dout_w(30 downto 0) <= sdpb_inst_6_DO_o(31 downto 1) ; + sdpb_inst_7_BLKSELA_i <= gw_gnd & gw_gnd & ada(14); + sdpb_inst_7_BLKSELB_i <= gw_gnd & gw_gnd & adb(14); + sdpb_inst_7_DI_i <= gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & din(3); + sdpb_inst_7_dout(3) <= sdpb_inst_7_DO_o(0); + sdpb_inst_7_dout_w(30 downto 0) <= sdpb_inst_7_DO_o(31 downto 1) ; + sdpb_inst_8_BLKSELA_i <= gw_gnd & gw_gnd & ada(14); + sdpb_inst_8_BLKSELB_i <= gw_gnd & gw_gnd & adb(14); + sdpb_inst_8_DI_i <= gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & din(4); + sdpb_inst_8_dout(4) <= sdpb_inst_8_DO_o(0); + sdpb_inst_8_dout_w(30 downto 0) <= sdpb_inst_8_DO_o(31 downto 1) ; + sdpb_inst_9_BLKSELA_i <= gw_gnd & gw_gnd & ada(14); + sdpb_inst_9_BLKSELB_i <= gw_gnd & gw_gnd & adb(14); + sdpb_inst_9_DI_i <= gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & din(4); + sdpb_inst_9_dout(4) <= sdpb_inst_9_DO_o(0); + sdpb_inst_9_dout_w(30 downto 0) <= sdpb_inst_9_DO_o(31 downto 1) ; + sdpb_inst_10_BLKSELA_i <= gw_gnd & gw_gnd & ada(14); + sdpb_inst_10_BLKSELB_i <= gw_gnd & gw_gnd & adb(14); + sdpb_inst_10_DI_i <= gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & din(5); + sdpb_inst_10_dout(5) <= sdpb_inst_10_DO_o(0); + sdpb_inst_10_dout_w(30 downto 0) <= sdpb_inst_10_DO_o(31 downto 1) ; + sdpb_inst_11_BLKSELA_i <= gw_gnd & gw_gnd & ada(14); + sdpb_inst_11_BLKSELB_i <= gw_gnd & gw_gnd & adb(14); + sdpb_inst_11_DI_i <= gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & din(5); + sdpb_inst_11_dout(5) <= sdpb_inst_11_DO_o(0); + sdpb_inst_11_dout_w(30 downto 0) <= sdpb_inst_11_DO_o(31 downto 1) ; + sdpb_inst_12_BLKSELA_i <= gw_gnd & gw_gnd & ada(14); + sdpb_inst_12_BLKSELB_i <= gw_gnd & gw_gnd & adb(14); + sdpb_inst_12_DI_i <= gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & din(6); + sdpb_inst_12_dout(6) <= sdpb_inst_12_DO_o(0); + sdpb_inst_12_dout_w(30 downto 0) <= sdpb_inst_12_DO_o(31 downto 1) ; + sdpb_inst_13_BLKSELA_i <= gw_gnd & gw_gnd & ada(14); + sdpb_inst_13_BLKSELB_i <= gw_gnd & gw_gnd & adb(14); + sdpb_inst_13_DI_i <= gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & din(6); + sdpb_inst_13_dout(6) <= sdpb_inst_13_DO_o(0); + sdpb_inst_13_dout_w(30 downto 0) <= sdpb_inst_13_DO_o(31 downto 1) ; + sdpb_inst_14_BLKSELA_i <= gw_gnd & gw_gnd & ada(14); + sdpb_inst_14_BLKSELB_i <= gw_gnd & gw_gnd & adb(14); + sdpb_inst_14_DI_i <= gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & din(7); + sdpb_inst_14_dout(7) <= sdpb_inst_14_DO_o(0); + sdpb_inst_14_dout_w(30 downto 0) <= sdpb_inst_14_DO_o(31 downto 1) ; + sdpb_inst_15_BLKSELA_i <= gw_gnd & gw_gnd & ada(14); + sdpb_inst_15_BLKSELB_i <= gw_gnd & gw_gnd & adb(14); + sdpb_inst_15_DI_i <= gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & gw_gnd & din(7); + sdpb_inst_15_dout(7) <= sdpb_inst_15_DO_o(0); + sdpb_inst_15_dout_w(30 downto 0) <= sdpb_inst_15_DO_o(31 downto 1) ; + + sdpb_inst_0: SDPB + generic map ( + READ_MODE => '0', + BIT_WIDTH_0 => 1, + BIT_WIDTH_1 => 1, + RESET_MODE => "SYNC", + BLK_SEL_0 => "000", + BLK_SEL_1 => "000", + INIT_RAM_00 => X"6F7FD205202807404523D0CD5D8ADB9E30739257F098C151D008AC904A555400", + INIT_RAM_01 => X"8A44429110AA04196D01166D4EDFFB6E7D6CABFE6DAA52DBA86DB6EFB40DA05B", + INIT_RAM_02 => X"FA9619B20DCBE400A9158721E48998FCDBDF841CC952EC0EA5DD9DF0A828A282", + INIT_RAM_03 => X"000F18DF7883BAA109BEEEE2DC38B702FB974E0BBB2F9DDC29C39E18F6581E1F", + INIT_RAM_04 => X"0561940E01F78C6DA80F8EBED7403A7D7475AA1568F35755A424B1927704E047", + INIT_RAM_05 => X"0003F314F316B1005B93CA6154A23F4D5D51354B00D5D5690ED0B4189E00F047", + INIT_RAM_06 => X"F131E2B7C4C0CFFCC3831E03F30E68C79DBAF7CFBA1999D3ABA203AF77758289", + INIT_RAM_07 => X"D30E163C21D30E28C78CABB17DF620EB17462E087B50BF9B89870DC6C29CAFCD", + INIT_RAM_08 => X"4108461832A8020DA463756B8413D24048A1174438108769D0ECD8F34E8D833D", + INIT_RAM_09 => X"7B0320FC6FBBC5C1EF7814FC1AEBABAC2BABAE70CCBAFAC590294A341B6D519A", + INIT_RAM_0A => X"2D62D60A2EB7089558C022E11C1AF5B16F599816199980A70A0A68C5AC4D42F4", + INIT_RAM_0B => X"07DC022A800899E0258380967002458201D2C02087209B780250200800202727", + INIT_RAM_0C => X"003C04040400080061A40180C020E10C88830088800200C02430C5FD20F1DC04", + INIT_RAM_0D => X"FF80000000D1D1D100D100D100D1000000D1008100001000F7800DBC0126D000", + INIT_RAM_0E => X"000000000000000000000000000000000000000002B400A5A5A5AA3FFFFFFE00", + INIT_RAM_0F => X"000B552401F000F8007C0E000E000003801C0000000000000100000000000000" + ) + port map ( + DO => sdpb_inst_0_DO_o, + CLKA => clka, + CEA => cea, + RESETA => reseta, + CLKB => clkb, + CEB => ceb, + RESETB => resetb, + OCE => oce, + BLKSELA => sdpb_inst_0_BLKSELA_i, + BLKSELB => sdpb_inst_0_BLKSELB_i, + ADA => ada(13 downto 0), + DI => sdpb_inst_0_DI_i, + ADB => adb(13 downto 0) + ); + + sdpb_inst_1: SDPB + generic map ( + READ_MODE => '0', + BIT_WIDTH_0 => 1, + BIT_WIDTH_1 => 1, + RESET_MODE => "SYNC", + BLK_SEL_0 => "001", + BLK_SEL_1 => "001" + ) + port map ( + DO => sdpb_inst_1_DO_o, + CLKA => clka, + CEA => cea, + RESETA => reseta, + CLKB => clkb, + CEB => ceb, + RESETB => resetb, + OCE => oce, + BLKSELA => sdpb_inst_1_BLKSELA_i, + BLKSELB => sdpb_inst_1_BLKSELB_i, + ADA => ada(13 downto 0), + DI => sdpb_inst_1_DI_i, + ADB => adb(13 downto 0) + ); + + sdpb_inst_2: SDPB + generic map ( + READ_MODE => '0', + BIT_WIDTH_0 => 1, + BIT_WIDTH_1 => 1, + RESET_MODE => "SYNC", + BLK_SEL_0 => "000", + BLK_SEL_1 => "000", + INIT_RAM_00 => X"92A886840D2A6226022A8222086521616180508A232625000111046345A294D4", + INIT_RAM_01 => X"5164041811157742029D9446222A2495824540A00898AD255288494549281210", + INIT_RAM_02 => X"044DC8A0E8A606A1291D70B55400114092D5A3E0A070AA8AE145011107111064", + INIT_RAM_03 => X"000AB0228A0D0142020010DD1B9054F8022A29E154100813853814C8288840D5", + INIT_RAM_04 => X"00C92580B8157A5910057450A22810AAA12951E880822AA11049690DAA5C0A40", + INIT_RAM_05 => X"001A2A8A80D1553FA14C949D10058148AA80CA85458AA8411080546301480200", + INIT_RAM_06 => X"A0800C22800108AA00181086A800C204301222911071328D050D5500022808A2", + INIT_RAM_07 => X"A814F0290EA81492052051480A020E000000040380841551500818A804830AA8", + INIT_RAM_08 => X"C0C7100296FA0A0213168CC29900049FC5154AA853A102D2A55500A695500E2A", + INIT_RAM_09 => X"B6795DAA54445216DA37C1AB314514019405450028501458C04491E890453D50", + INIT_RAM_0A => X"2DF2002692F5150236BCDD46C6944346B2800EB4C1016845CB0A243455BAA446", + INIT_RAM_0B => X"0817018CAC2A301B0FA260B10F02E1440B0000386942392000E4400200192DAA", + INIT_RAM_0C => X"380002233000287408094C0323E0C440110203550CFE77C20020C6E280524205", + INIT_RAM_0D => X"FFC0000000B0B0B000B000B000B0000000B000400000098604E050A18468C805", + INIT_RAM_0E => X"30C30FFFFFFFF9B38D8C2C20677803B8DD1BA37007215466C3C3443BBBBBFC00", + INIT_RAM_0F => X"001366140FFE07FF03FF83381800F806003001F000000000C6AF917AA3107FFF" + ) + port map ( + DO => sdpb_inst_2_DO_o, + CLKA => clka, + CEA => cea, + RESETA => reseta, + CLKB => clkb, + CEB => ceb, + RESETB => resetb, + OCE => oce, + BLKSELA => sdpb_inst_2_BLKSELA_i, + BLKSELB => sdpb_inst_2_BLKSELB_i, + ADA => ada(13 downto 0), + DI => sdpb_inst_2_DI_i, + ADB => adb(13 downto 0) + ); + + sdpb_inst_3: SDPB + generic map ( + READ_MODE => '0', + BIT_WIDTH_0 => 1, + BIT_WIDTH_1 => 1, + RESET_MODE => "SYNC", + BLK_SEL_0 => "001", + BLK_SEL_1 => "001" + ) + port map ( + DO => sdpb_inst_3_DO_o, + CLKA => clka, + CEA => cea, + RESETA => reseta, + CLKB => clkb, + CEB => ceb, + RESETB => resetb, + OCE => oce, + BLKSELA => sdpb_inst_3_BLKSELA_i, + BLKSELB => sdpb_inst_3_BLKSELB_i, + ADA => ada(13 downto 0), + DI => sdpb_inst_3_DI_i, + ADB => adb(13 downto 0) + ); + + sdpb_inst_4: SDPB + generic map ( + READ_MODE => '0', + BIT_WIDTH_0 => 1, + BIT_WIDTH_1 => 1, + RESET_MODE => "SYNC", + BLK_SEL_0 => "000", + BLK_SEL_1 => "000", + INIT_RAM_00 => X"E79646330C446524039AB094CBE7C98D1B5326CFB11464763D657D918A550000", + INIT_RAM_01 => X"C976321C9C996711011F445874F99F363234A45AC69A17CDB264F3728C449889", + INIT_RAM_02 => X"BDD4108AEB6AE674815983BD03150558880C2C18A1650088CA045173E73C8666", + INIT_RAM_03 => X"00060DD951827EBBC88E7AE5945C2700A3878A03D94B1FD449C4C380C2C8D55C", + INIT_RAM_04 => X"05C51E0B4BEADD4CF42AABAEF1A32ED730D5DC17A14333B8C5A4F5177EA4B48F", + INIT_RAM_05 => X"001D1B2411629E007BD1FFF26E861E2CCEE7351C48CCEE356D4BC4B41790B48F", + INIT_RAM_06 => X"10842490421101661098420598424810903C185EE82EEA609CC22CC55D3EFF11", + INIT_RAM_07 => X"9846708C8D984618118069383CD80023B7073C800B902CC8C421146210852464", + INIT_RAM_08 => X"5188871AC33F754EF4FBF1D80563B04000C636611B84035992CC4232CCC02CAD", + INIT_RAM_09 => X"BA8160527DAA8D1BE9F8045508DB367063267C6088F76A04902088281D5B3156", + INIT_RAM_0A => X"2DF0DF01B0490994588267D78656F561CE4A2C9594056575B360E658A06F67C2", + INIT_RAM_0B => X"01250280A4063000396200E09903F3000E3088285304F96883D0420E00293E33", + INIT_RAM_0C => X"003E0A63700371F48061544D2BC006F33700015D8FFD7F012C003EE000027107", + INIT_RAM_0D => X"FFE0B10088B188B1B1B1B10000B100B1000000810000108E20A051B08DC44103", + INIT_RAM_0E => X"38E3894A52C6024F923CD1E69F3FE6F936A7F4FA031D2ABD0000BE905050F800", + INIT_RAM_0F => X"00176D501BBE0DDF06EF9778FFE7FC3FE9FF0FFE0022ABBF98D075A2AB500000" + ) + port map ( + DO => sdpb_inst_4_DO_o, + CLKA => clka, + CEA => cea, + RESETA => reseta, + CLKB => clkb, + CEB => ceb, + RESETB => resetb, + OCE => oce, + BLKSELA => sdpb_inst_4_BLKSELA_i, + BLKSELB => sdpb_inst_4_BLKSELB_i, + ADA => ada(13 downto 0), + DI => sdpb_inst_4_DI_i, + ADB => adb(13 downto 0) + ); + + sdpb_inst_5: SDPB + generic map ( + READ_MODE => '0', + BIT_WIDTH_0 => 1, + BIT_WIDTH_1 => 1, + RESET_MODE => "SYNC", + BLK_SEL_0 => "001", + BLK_SEL_1 => "001" + ) + port map ( + DO => sdpb_inst_5_DO_o, + CLKA => clka, + CEA => cea, + RESETA => reseta, + CLKB => clkb, + CEB => ceb, + RESETB => resetb, + OCE => oce, + BLKSELA => sdpb_inst_5_BLKSELA_i, + BLKSELB => sdpb_inst_5_BLKSELB_i, + ADA => ada(13 downto 0), + DI => sdpb_inst_5_DI_i, + ADB => adb(13 downto 0) + ); + + sdpb_inst_6: SDPB + generic map ( + READ_MODE => '0', + BIT_WIDTH_0 => 1, + BIT_WIDTH_1 => 1, + RESET_MODE => "SYNC", + BLK_SEL_0 => "000", + BLK_SEL_1 => "000", + INIT_RAM_00 => X"1843B031206002E06C8BEA1B9EA036624A0AE59A6C000240900DC410C10065F3", + INIT_RAM_01 => X"520194C06533404AC6D01774182CC0C9890C0D0E8102C0321E030C88206180C2", + INIT_RAM_02 => X"475BC9B22EBD8C4122157E29A0C888B0F5528BF0CA53462CA6888CD158052490", + INIT_RAM_03 => X"000323A60885C508413085BA5FA4D7FA4C186BF86235E037E57A485039339F07", + INIT_RAM_04 => X"10FDC7D4F8181F7B45555515A60095AA23AB55EA02BE22A99010FDCA2B3D4644", + INIT_RAM_05 => X"0004409AC020357F2B5CADEC5507A5588AA0E8985588AA610123054728C1CE04", + INIT_RAM_06 => X"C1999A472664EC3066498980C199A46269844D0153555489155D45500A430028", + INIT_RAM_07 => X"E199931382E199E4627996D1412C3F9800F0038FA44882024CC4C10463929301", + INIT_RAM_08 => X"570724429680A00297A2AD71B940C7BF8F771B862498E4A66B34CCCD330CC332", + INIT_RAM_09 => X"EFFA5FA457504660BE2FD9AAD3719DC8099C9756EC4CD4DB81DD37F20671119C", + INIT_RAM_0A => X"000200000EB6162BBEFCF8610D091E9629193A4709CCD19650F088880D0A0164", + INIT_RAM_0B => X"0B5882240282294005A218B5A8C2208083620022682C28486214408A004107C3", + INIT_RAM_0C => X"30000A23306229F60C097C872BF0DC719DC313554FFF7FC20030C108205A9041", + INIT_RAM_0D => X"FFF0D00089D089D0D0D0D00000D000D000000040F8004080B6B4041479648824", + INIT_RAM_0E => X"00000739CEC604DFA6FD33E9BF4FE9F1B637E6EE043EAB660000BAABBEEBF000", + INIT_RAM_0F => X"0011634499080C8406423211BBEDDF6EE377DBBE0177FFFF847F9F783FF00000" + ) + port map ( + DO => sdpb_inst_6_DO_o, + CLKA => clka, + CEA => cea, + RESETA => reseta, + CLKB => clkb, + CEB => ceb, + RESETB => resetb, + OCE => oce, + BLKSELA => sdpb_inst_6_BLKSELA_i, + BLKSELB => sdpb_inst_6_BLKSELB_i, + ADA => ada(13 downto 0), + DI => sdpb_inst_6_DI_i, + ADB => adb(13 downto 0) + ); + + sdpb_inst_7: SDPB + generic map ( + READ_MODE => '0', + BIT_WIDTH_0 => 1, + BIT_WIDTH_1 => 1, + RESET_MODE => "SYNC", + BLK_SEL_0 => "001", + BLK_SEL_1 => "001" + ) + port map ( + DO => sdpb_inst_7_DO_o, + CLKA => clka, + CEA => cea, + RESETA => reseta, + CLKB => clkb, + CEB => ceb, + RESETB => resetb, + OCE => oce, + BLKSELA => sdpb_inst_7_BLKSELA_i, + BLKSELB => sdpb_inst_7_BLKSELB_i, + ADA => ada(13 downto 0), + DI => sdpb_inst_7_DI_i, + ADB => adb(13 downto 0) + ); + + sdpb_inst_8: SDPB + generic map ( + READ_MODE => '0', + BIT_WIDTH_0 => 1, + BIT_WIDTH_1 => 1, + RESET_MODE => "SYNC", + BLK_SEL_0 => "000", + BLK_SEL_1 => "000", + INIT_RAM_00 => X"4A2A0B1C921BB839986C0C6200189110AC06C9000CC112081282060100002683", + INIT_RAM_01 => X"30CC4C731350DD8612C40880090AA24445C740A938EF289147B82445163A6430", + INIT_RAM_02 => X"055006441028160850F8084188226202D4913002DCE013CDC026661804D3184D", + INIT_RAM_03 => X"000046000C040412911445A134135D0456C83E10419468B413412504852CDD04", + INIT_RAM_04 => X"0DA64C758EB1158C4AC44513025613A446A6660A7E8C44CD2B01567A0283506A", + INIT_RAM_05 => X"001224492C4001800E503940504404C113302053B211334BC6193B58EA0D502A", + INIT_RAM_06 => X"AC4C5162913232A93164C5EAA4C517314251208151D551933764876280800020", + INIT_RAM_07 => X"A4C5498AEAA4C5173142545308A360566A3CD1D8162E11352262AA9131485A98", + INIT_RAM_08 => X"21384D97BB000A039C002200C3D082A033498893164C7216A9522628B52268CA", + INIT_RAM_09 => X"F804A0A204506000E2382EAA9100155210041198C90000640C22480604801220", + INIT_RAM_0A => X"2490002092681042B901A04920315C1BE08C610833220318449111100600210C", + INIT_RAM_0B => X"1000C3C1055B021B200460C800C300138C0908380054A000C202120C001D0FFC", + INIT_RAM_0C => X"003F05A429D158818BD3C247DCBAE2C6E8C3AB1247E53FC5D575EAAA6AC40186", + INIT_RAM_0D => X"FFF8D1880088D1D1D1D100D1D100D10000000081E0000B850800F242E9D02186", + INIT_RAM_0E => X"30C304A128BDC7FFBFFDFFEFFF4F89FDEF3DC79E07F8D5E70000AEAFAEBAE000", + INIT_RAM_0F => X"A81BCA118BBA05DD02EEB77D908C87643B21D908015554403200000000002AAA" + ) + port map ( + DO => sdpb_inst_8_DO_o, + CLKA => clka, + CEA => cea, + RESETA => reseta, + CLKB => clkb, + CEB => ceb, + RESETB => resetb, + OCE => oce, + BLKSELA => sdpb_inst_8_BLKSELA_i, + BLKSELB => sdpb_inst_8_BLKSELB_i, + ADA => ada(13 downto 0), + DI => sdpb_inst_8_DI_i, + ADB => adb(13 downto 0) + ); + + sdpb_inst_9: SDPB + generic map ( + READ_MODE => '0', + BIT_WIDTH_0 => 1, + BIT_WIDTH_1 => 1, + RESET_MODE => "SYNC", + BLK_SEL_0 => "001", + BLK_SEL_1 => "001" + ) + port map ( + DO => sdpb_inst_9_DO_o, + CLKA => clka, + CEA => cea, + RESETA => reseta, + CLKB => clkb, + CEB => ceb, + RESETB => resetb, + OCE => oce, + BLKSELA => sdpb_inst_9_BLKSELA_i, + BLKSELB => sdpb_inst_9_BLKSELB_i, + ADA => ada(13 downto 0), + DI => sdpb_inst_9_DI_i, + ADB => adb(13 downto 0) + ); + + sdpb_inst_10: SDPB + generic map ( + READ_MODE => '0', + BIT_WIDTH_0 => 1, + BIT_WIDTH_1 => 1, + RESET_MODE => "SYNC", + BLK_SEL_0 => "000", + BLK_SEL_1 => "000", + INIT_RAM_00 => X"80471122AA44104681905CC10501020F1113821454514382902A221460007C25", + INIT_RAM_01 => X"AB082BCA0AA2009575F0A0AA9064D40838A88D1D451515022D754088285500AE", + INIT_RAM_02 => X"075A111141ADE0CA46AB07AC2288083C7DF3F81A18AB518056A266F38A8AA888", + INIT_RAM_03 => X"00100C0608ECC31DEA0823F29E2BA7868D546F0A62A8C47E29E2AA431B1896A6", + INIT_RAM_04 => X"32BECD83387437A50D87E79B04441BB447B6672C6C9444CC22085EFC03D832C1", + INIT_RAM_05 => X"001811141518203F0E5939D88081A30113340A4362113309849C365B07503281", + INIT_RAM_06 => X"544EBA89533D61343AD4EB14D0EBA93AEE39417402401D9A2676466820410A64", + INIT_RAM_07 => X"D0EB29D614D0EBA93AEE24B2410570B44448825C2C52A6808275D0433BE6A142", + INIT_RAM_08 => X"CBB07706B0502012960420AD83D4C3C46B691353AD0ED9A85868275D46867584", + INIT_RAM_09 => X"BD86B2E686004444F73C34BEB3288CC8999D92309E1980C3F69B6614A7888A2A", + INIT_RAM_0A => X"1A424912590520513D41B221018216B05B9680641322182044DD41460C302934", + INIT_RAM_0B => X"0000A4800408000FD00039A00104800214000668004500004500011A001AC000", + INIT_RAM_0C => X"200001AC39F1DEC1C8D1C6075DDAE64664C1A8D0CEE73BCCD36DEE8A2AC0004A", + INIT_RAM_0D => X"FFFCB0890089B0B0B0B000B0B000B00000000040B8000060002C000077C0001D", + INIT_RAM_0E => X"004201884384C6FFB7FDBFEDFF37C7FCBF9612F00004FF180000BABBEFBEC000", + INIT_RAM_0F => X"A81D739E6000080000801FFCBBC5DC2EF9770BBA015554400045DFB878101999" + ) + port map ( + DO => sdpb_inst_10_DO_o, + CLKA => clka, + CEA => cea, + RESETA => reseta, + CLKB => clkb, + CEB => ceb, + RESETB => resetb, + OCE => oce, + BLKSELA => sdpb_inst_10_BLKSELA_i, + BLKSELB => sdpb_inst_10_BLKSELB_i, + ADA => ada(13 downto 0), + DI => sdpb_inst_10_DI_i, + ADB => adb(13 downto 0) + ); + + sdpb_inst_11: SDPB + generic map ( + READ_MODE => '0', + BIT_WIDTH_0 => 1, + BIT_WIDTH_1 => 1, + RESET_MODE => "SYNC", + BLK_SEL_0 => "001", + BLK_SEL_1 => "001" + ) + port map ( + DO => sdpb_inst_11_DO_o, + CLKA => clka, + CEA => cea, + RESETA => reseta, + CLKB => clkb, + CEB => ceb, + RESETB => resetb, + OCE => oce, + BLKSELA => sdpb_inst_11_BLKSELA_i, + BLKSELB => sdpb_inst_11_BLKSELB_i, + ADA => ada(13 downto 0), + DI => sdpb_inst_11_DI_i, + ADB => adb(13 downto 0) + ); + + sdpb_inst_12: SDPB + generic map ( + READ_MODE => '0', + BIT_WIDTH_0 => 1, + BIT_WIDTH_1 => 1, + RESET_MODE => "SYNC", + BLK_SEL_0 => "000", + BLK_SEL_1 => "000", + INIT_RAM_00 => X"802A0D0C980BEC3E44A52A5282DD207C6706E59A654516481280C28001002743", + INIT_RAM_01 => X"34E7CC399311774632980A902122A401F6C340A818316D00619840051A187430", + INIT_RAM_02 => X"5561C66316B0A4635E31723D4022B29288C19FF6A8C0968981288E5906730867", + INIT_RAM_03 => X"001305080C40041AD11456C939924E784A481CE14494AAD99399250394080515", + INIT_RAM_04 => X"308C8BF576A8112810F3134800AF48108910000087108800578044A002FF5E2A", + INIT_RAM_05 => X"001E2048600001BF0C4431A800518462200000843F220014E52A57B76BCD5E6A", + INIT_RAM_06 => X"A55CC322957646897325CC1AA5CC317308D528A0012002244008801000000000", + INIT_RAM_07 => X"25CCCB991AA5CC317308D45A00014EC33A467253B26715312AE668957238CA98", + INIT_RAM_08 => X"4FB0ADC756102A0A50A2A314DB22A05B885B8A97325C8E32AF52AE61952AE91A", + INIT_RAM_09 => X"207C4C020400600280A3EF1080144007444040D00A110152339EA60814B002A4", + INIT_RAM_0A => X"1A43ED04C9092540313CC843A92818140A81124AAABB939A71F0150007002412", + INIT_RAM_0B => X"0001208002420000080000C000E300040C0002080020A0000280010400000000", + INIT_RAM_0C => X"003F85042910004103D2800558AA22C2ACC2A81047C63F05D5752D754A000306", + INIT_RAM_0D => X"FFFE000000B1B1B1B100B100B1000000B10000813F0000080010300001000066", + INIT_RAM_0E => X"004200042121C04002001000801DCF001903206007FDFFFF0000EABEAFEA8000", + INIT_RAM_0F => X"A800839E1C001F8001FF840081C200200080020001DFD7C1FFD6288846100787" + ) + port map ( + DO => sdpb_inst_12_DO_o, + CLKA => clka, + CEA => cea, + RESETA => reseta, + CLKB => clkb, + CEB => ceb, + RESETB => resetb, + OCE => oce, + BLKSELA => sdpb_inst_12_BLKSELA_i, + BLKSELB => sdpb_inst_12_BLKSELB_i, + ADA => ada(13 downto 0), + DI => sdpb_inst_12_DI_i, + ADB => adb(13 downto 0) + ); + + sdpb_inst_13: SDPB + generic map ( + READ_MODE => '0', + BIT_WIDTH_0 => 1, + BIT_WIDTH_1 => 1, + RESET_MODE => "SYNC", + BLK_SEL_0 => "001", + BLK_SEL_1 => "001" + ) + port map ( + DO => sdpb_inst_13_DO_o, + CLKA => clka, + CEA => cea, + RESETA => reseta, + CLKB => clkb, + CEB => ceb, + RESETB => resetb, + OCE => oce, + BLKSELA => sdpb_inst_13_BLKSELA_i, + BLKSELB => sdpb_inst_13_BLKSELB_i, + ADA => ada(13 downto 0), + DI => sdpb_inst_13_DI_i, + ADB => adb(13 downto 0) + ); + + sdpb_inst_14: SDPB + generic map ( + READ_MODE => '0', + BIT_WIDTH_0 => 1, + BIT_WIDTH_1 => 1, + RESET_MODE => "SYNC", + BLK_SEL_0 => "000", + BLK_SEL_1 => "000", + INIT_RAM_00 => X"A57B5C44B88BFD7F57A53DEDE3DF4A9AB7F787CF377DDF6CFA4AFBB5AA5576F6", + INIT_RAM_01 => X"B2EFECBBFB3A6EB65392AA9AE5F7BD2A6ECBE9EC59757F4AE9D9D2AF3A997533", + INIT_RAM_02 => X"FFD83775D7ECEEEF563B833DE4AABA9AF0D99C1ACAEAD4ADD5AAAA6DAEFB6AEF", + INIT_RAM_03 => X"000E5C5D5DAEAEBBDBDF7EF1BE1A6F81EB4DDF07EA9EBFDE1BE1A7E5DE5BDEBF", + INIT_RAM_04 => X"15BE9DFFBFE2B7AEB8FFFFFE55C7FEFDDDFCEF1DEFD9DDDCF7B4DEBD579BF22F", + INIT_RAM_05 => X"0013314D716AABFF5EDB7BFAABD3AF77777115CF7F77773DEE78F7F37E45F22F", + INIT_RAM_06 => X"B558E9B2D56757ED63B58E5F358E9963A3F938CAAB6ABFFEEEF6AEF555555575", + INIT_RAM_07 => X"B58EEB1D5F358E9963A3FC7B755570E33F06785C3B323DB9AAC77CD5625E6EDC", + INIT_RAM_08 => X"EFB8EFD6F77FFFDEF6F7FB98E377F7840DC9BED63B58979BB9DAAC74DDAACD5F", + INIT_RAM_09 => X"EC04F2F62EAAED5FB3EC2FEEBB9EEEEAEEEEFAF6DDEEFFDD5BE2F80CBEBEEAA6", + INIT_RAM_0A => X"2490000012660B7D7D01F7A7AEAFF677DFD55FABAAAAEAEBE3985DDAAF7567B6", + INIT_RAM_0B => X"0000030000880000200000400000800006000010000800002000008400001000", + INIT_RAM_0C => X"0000050C2941040043D38045D4BAC682E803AB0205453FC55555C00020C00007", + INIT_RAM_0D => X"0000000000D0D0D0D000D000D0000000D0000040CF0004000000500000C00001", + INIT_RAM_0E => X"004200842121C00000000000000000000000000007FDFFFF0000AABFFAAA0000", + INIT_RAM_0F => X"A81FFC600380007800000FFDFF87FE7FE1FF87FE008A8380007DDF77F9F07F80" + ) + port map ( + DO => sdpb_inst_14_DO_o, + CLKA => clka, + CEA => cea, + RESETA => reseta, + CLKB => clkb, + CEB => ceb, + RESETB => resetb, + OCE => oce, + BLKSELA => sdpb_inst_14_BLKSELA_i, + BLKSELB => sdpb_inst_14_BLKSELB_i, + ADA => ada(13 downto 0), + DI => sdpb_inst_14_DI_i, + ADB => adb(13 downto 0) + ); + + sdpb_inst_15: SDPB + generic map ( + READ_MODE => '0', + BIT_WIDTH_0 => 1, + BIT_WIDTH_1 => 1, + RESET_MODE => "SYNC", + BLK_SEL_0 => "001", + BLK_SEL_1 => "001" + ) + port map ( + DO => sdpb_inst_15_DO_o, + CLKA => clka, + CEA => cea, + RESETA => reseta, + CLKB => clkb, + CEB => ceb, + RESETB => resetb, + OCE => oce, + BLKSELA => sdpb_inst_15_BLKSELA_i, + BLKSELB => sdpb_inst_15_BLKSELB_i, + ADA => ada(13 downto 0), + DI => sdpb_inst_15_DI_i, + ADB => adb(13 downto 0) + ); + + dff_inst_0: DFFE + port map ( + Q => dff_q_0, + D => adb(14), + CLK => clkb, + CE => ceb + ); + + mux_inst_0: MUX2 + port map ( + O => dout(0), + I0 => sdpb_inst_0_dout(0), + I1 => sdpb_inst_1_dout(0), + S0 => dff_q_0 + ); + + mux_inst_1: MUX2 + port map ( + O => dout(1), + I0 => sdpb_inst_2_dout(1), + I1 => sdpb_inst_3_dout(1), + S0 => dff_q_0 + ); + + mux_inst_2: MUX2 + port map ( + O => dout(2), + I0 => sdpb_inst_4_dout(2), + I1 => sdpb_inst_5_dout(2), + S0 => dff_q_0 + ); + + mux_inst_3: MUX2 + port map ( + O => dout(3), + I0 => sdpb_inst_6_dout(3), + I1 => sdpb_inst_7_dout(3), + S0 => dff_q_0 + ); + + mux_inst_4: MUX2 + port map ( + O => dout(4), + I0 => sdpb_inst_8_dout(4), + I1 => sdpb_inst_9_dout(4), + S0 => dff_q_0 + ); + + mux_inst_5: MUX2 + port map ( + O => dout(5), + I0 => sdpb_inst_10_dout(5), + I1 => sdpb_inst_11_dout(5), + S0 => dff_q_0 + ); + + mux_inst_6: MUX2 + port map ( + O => dout(6), + I0 => sdpb_inst_12_dout(6), + I1 => sdpb_inst_13_dout(6), + S0 => dff_q_0 + ); + + mux_inst_7: MUX2 + port map ( + O => dout(7), + I0 => sdpb_inst_14_dout(7), + I1 => sdpb_inst_15_dout(7), + S0 => dff_q_0 + ); + +end Behavioral; --Gowin_SDPB