Questionable values written to registers

[welash]

I was looking through the code and noticed some writes to hardware registers
that I can't match up to the ST documents. I've given the registers and the
code lines that seem a little off to me and the reason why.

It doesn't seem like these are causing any real issues, but I thought I would
document what I see.

SWIM_CSR (0x7f80)
        bit7    SAFE_MASK (rw)
        bit6    NO_ACCESS (ro)
        bit5    SWIM_DM   (rw)
        bit4    HS        (rw)
        bit3    OSCOFF    (rw)
        bit2    RST       (rw)
        bit1    HSIT      (ro)
        bit0    PRI       (rw)

in stlink2_init_session()
        // I think this is just a mistake in the comment, 0xa0 seems
        // like the correct value to write (setting SAFE_MASK and SWIM_DM)
        stlink2_write_byte(pgm, 0xa0, 0x7f80); // mov 0x0a, SWIM_CSR2 ;; Init SWIM

at the end of stlinkv2_swim_write_range()
        // This one may be ok, but it seems odd that we would be switching to HS mode
        // and setting the HSIT bit which is read only
        stlink2_write_byte(pgm, 0xb6, 0x7f80);

DM_CSR2 (0x7f99)
        bit7    Reserved Must be kept 0
        bit6    Reserved Must be kept 0
        bit5    SWBKE (rw)
        bit4    SWBKF (ro)
        bit3    STALL (rw)
        bit2    Reserved Must be kept 0
        bit1    Reserved Must be kept 0
        bit0    FLUSH (set by sw, cleared by hw)

in stlink2_init_session()
        // This would seem ok if it were 0x20, but it has a reserved bit set
        stlink2_write_and_read_byte(pgm, 0xa0, 0x7f99);

FLASH_IAPSR
        bit7    Reserved
        bit6    HVOFF  (readonly)
        bit5    Reserved, forced by hardware to 0
        bit4    Reserved, forced by hardware to 0
        bit3    DUL  (set by hw, write to 0 to clear)
        bit2    EOP  (read to clear)
        bit1    PUL  (set by hw, write to 0 to clear)
        bit0    WR_PG_DIS (read to clear)

in stlink2_wait_until_transfer_completes()
        // This seems odd, in that it it sets a reserved bit, and it clears DUL (locks eeprom memory)
        // and writes a 1 to a bit that can only be set by unlocking the flash area, however the value
        // is being tested against the EOP bit, so the read part seems ok.
        TRY(8, stlink2_write_and_read_byte(pgm, 0x82, device->regs.FLASH_IAPSR) & 0x4);

in stlink2_swim_write_range()
        // Another strange value to right, sets a read only bit and reserved bit in the upper nibble
        // and sets EOP and PUL, reading will clear EOP and WR_PG_DIS if they are set.
        stlink2_write_and_read_byte(pgm, 0x56, device->regs.FLASH_IAPSR); // mov 0x56, FLASH_IAPSR

[joshuadavila]

Hi welash, I have reviewing the code too, and have the same doubts as you, It doesn't match with ST documentation but it does work. I have been trying to modify this code to avoid leaving the mcu on STALL.