From a4eebe234abb7844b809d665fdd4c7336c8e7a15 Mon Sep 17 00:00:00 2001 From: Vasudev Date: Wed, 20 Nov 2024 02:08:03 +0530 Subject: [PATCH] minor corrections --- ...el-plans-to-integrate-3D-VCache-Tech-in-their-CPU-by-2025.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/source/_posts/Intel-plans-to-integrate-3D-VCache-Tech-in-their-CPU-by-2025.md b/source/_posts/Intel-plans-to-integrate-3D-VCache-Tech-in-their-CPU-by-2025.md index 4a3f6bb..b19cef8 100644 --- a/source/_posts/Intel-plans-to-integrate-3D-VCache-Tech-in-their-CPU-by-2025.md +++ b/source/_posts/Intel-plans-to-integrate-3D-VCache-Tech-in-their-CPU-by-2025.md @@ -21,7 +21,7 @@ Florian said Intel is planning to add large shared L3 cache approach in a phased At the moment Intel is busy with providing microcode fixes for Arrow Lake CPUs that began shipping in November 2024 to compete against AMD Zen 5 X3D variants and non-X3D variants. -### SOurce(s) +### Source(s) - [TPU][def] - [Der8auer German Video][def2]