Hammer Flow with Custom Verilog and ASAP7 #871
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I am currently trying to build our own custom verilog code with hammer flow, without involving the chipyard generated design. While going through the documents I came across this section which mentions the commands to do it.
I tried the same command, but it resulted in the following issues.
Scenario 1 - After make clean
Running the hammer scripts simply for my design resulted in make errors.
Design used - or gate
Command used - make buildfile CUSTOM_VLOG=or_gate.sv VLSI_TOP=or_gate
Make Error:
`:121.28-126.5: Warning (simple_bus_reg): /soc/subsystem_mbus_clock: missing or empty reg/ranges property
:127.28-132.5: Warning (simple_bus_reg): /soc/subsystem_pbus_clock: missing or empty reg/ranges property
:42.29-46.6: Warning (interrupt_provider): /cpus/cpu@0/interrupt-controller: Missing #address-cells in interrupt provider
:98.36-107.5: Warning (interrupt_provider): /soc/interrupt-controller@c000000: Missing #address-cells in interrupt provider
Clock subsystem_pbus_0: using diplomatically specified frequency of 500.0.
Clock subsystem_mbus_0: using diplomatically specified frequency of 500.0.
/dts-v1/;
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "ucb-bar,chipyard-dev";
model = "ucb-bar,chipyard";
L24: aliases {
serial0 = &L18;
};
L11: chosen {
stdout-path = &L18;
};
L23: cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <1000000>;
L6: cpu@0 {
clock-frequency = <0>;
compatible = "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <16384>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
hardware-exec-breakpoint-count = <1>;
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <16384>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
next-level-cache = <&L3>;
reg = <0x0>;
riscv,isa = "rv64imafdczicsr_zifencei_zihpm_xrocket";
riscv,pmpgranularity = <4>;
riscv,pmpregions = <8>;
status = "okay";
timebase-frequency = <1000000>;
tlb-split;
L4: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
};
L25: htif {
compatible = "ucb,htif0";
};
L14: memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
L22: soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "ucb-bar,chipyard-soc", "simple-bus";
ranges;
L17: boot-address-reg@4000 {
reg = <0x4000 0x1000>;
reg-names = "control";
};
L3: cache-controller@2010000 {
cache-block-size = <64>;
cache-level = <2>;
cache-sets = <1024>;
cache-size = <524288>;
cache-unified;
compatible = "sifive,inclusivecache0", "cache";
next-level-cache = <&L14>;
reg = <0x2010000 0x1000>;
reg-names = "control";
sifive,mshr-count = <7>;
};
L8: clint@2000000 {
compatible = "riscv,clint0";
interrupts-extended = <&L4 3 &L4 7>;
reg = <0x2000000 0x10000>;
reg-names = "control";
};
L19: clock-gater@100000 {
reg = <0x100000 0x1000>;
reg-names = "control";
};
L9: debug-controller@0 {
compatible = "sifive,debug-013", "riscv,debug-013";
debug-attach = "jtag";
interrupts-extended = <&L4 65535>;
reg = <0x0 0x1000>;
reg-names = "control";
};
L1: error-device@3000 {
compatible = "sifive,error0";
reg = <0x3000 0x1000>;
};
L7: interrupt-controller@c000000 {
#interrupt-cells = <1>;
compatible = "riscv,plic0";
interrupt-controller;
interrupts-extended = <&L4 11 &L4 9>;
reg = <0xc000000 0x4000000>;
reg-names = "control";
riscv,max-priority = <1>;
riscv,ndev = <1>;
};
L16: rom@10000 {
compatible = "sifive,rom0";
reg = <0x10000 0x10000>;
reg-names = "mem";
};
L18: serial@54000000 {
clocks = <&L0>;
compatible = "sifive,uart0";
interrupt-parent = <&L7>;
interrupts = <1>;
reg = <0x54000000 0x1000>;
reg-names = "control";
};
L2: subsystem_mbus_clock {
#clock-cells = <0>;
clock-frequency = <500000000>;
clock-output-names = "subsystem_mbus_clock";
compatible = "fixed-clock";
};
L0: subsystem_pbus_clock {
#clock-cells = <0>;
clock-frequency = <500000000>;
clock-output-names = "subsystem_pbus_clock";
compatible = "fixed-clock";
};
L20: tile-reset-setter@110000 {
reg = <0x110000 0x1000>;
reg-names = "control";
};
};
};
Generated Address Map
0 - 1000 ARWX debug-controller@0
3000 - 4000 ARWX error-device@3000
4000 - 5000 ARW boot-address-reg@4000
10000 - 20000 R X rom@10000
100000 - 101000 ARW clock-gater@100000
110000 - 111000 ARW tile-reset-setter@110000
2000000 - 2010000 ARW clint@2000000
2010000 - 2011000 ARW cache-controller@2010000
c000000 - 10000000 ARW interrupt-controller@c000000
54000000 - 54001000 ARW serial@54000000
80000000 - 90000000 ARWXC memory@80000000
IOCells generated by IOBinders:
IOBinder for interface testchipip.CanHavePeripheryTLSerial generated:
35 X GenericDigitalInIOCell
34 X GenericDigitalOutIOCell
IOBinder for interface testchipip.CanHavePeripheryCustomBootPin generated:
1 X GenericDigitalInIOCell
IOBinder for interface sifive.blocks.devices.uart.HasPeripheryUARTModuleImp generated:
1 X GenericDigitalInIOCell
1 X GenericDigitalOutIOCell
IOBinder for interface freechips.rocketchip.devices.debug.HasPeripheryDebug generated:
3 X GenericDigitalInIOCell
1 X GenericDigitalOutIOCell
Total generated 76 IOCells:
40 X GenericDigitalInIOCell
36 X GenericDigitalOutIOCell
Harness binder clock is 100.0
echo "$mfc_extra_anno_contents" > /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.extrafirtool.anno.json
echo "$sfc_extra_low_transforms_anno_contents" > /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.extrasfc.anno.json
jq -s '[.[][]]' /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.anno.json /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.extrafirtool.anno.json > /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.extra.anno.json
echo none > /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/.sfc_level
echo "" > /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/.extra_firrtl_options
if [ none = low ]; then jq -s '[.[][]]' /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.extra.anno.json /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.extrasfc.anno.json > /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.appended.anno.json; fi
if [ none = none ]; then cat /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.extra.anno.json > /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.appended.anno.json; fi
touch /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.appended.anno.json
mkdir -p /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/
echo "emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,verifLabels,locationInfoStyle=wrapInAtSquareBracket" > /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/.mfc_lowering_options
rm -rf /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/gen-collateral
cd /u/jonthom/creating-a-gds/chipyard && java -cp /u/jonthom/creating-a-gds/chipyard/.classpath_cache/tapeout.jar barstools.tapeout.transforms.GenerateModelStageMain --no-dedup --output-file /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.sfc --output-annotation-file /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.sfc.anno.json --target-dir /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/gen-collateral --input-file /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.fir --annotation-file /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.appended.anno.json --log-level error --allow-unrecognized-annotations -X none
Picked up JAVA_TOOL_OPTIONS: -Xmx8G -Xss8M -Djava.io.tmpdir=/u/jonthom/creating-a-gds/chipyard/.java_tmp
mv /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.sfc.lo.fir /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.sfc.fir 2> /dev/null # Optionally change file type when SFC generates LowFIRRTL
make: [/u/jonthom/creating-a-gds/chipyard/common.mk:227: /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/model_module_hierarchy.json] Error 1 (ignored)
firtool
--format=fir
--dedup
--export-module-hierarchy
--emit-metadata
--verify-each=true
--warn-on-unprocessed-annotations
--disable-annotation-classless
--disable-annotation-unknown
--mlir-timing
--lowering-options=emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,verifLabels,locationInfoStyle=wrapInAtSquareBracket
--repl-seq-mem
--repl-seq-mem-file=/u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.mems.conf
--repl-seq-mem-circuit=TestHarness
--annotation-file=/u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.sfc.anno.json
--split-verilog
-o /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/gen-collateral
/u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.sfc.fir
/u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.sfc.fir:2:1: warning: unprocessed annotation:'firrtl.transforms.NoCircuitDedupAnnotation$' still remaining after LowerToHW
circuit TestHarness :
^
/u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.sfc.fir:2:1: warning: unprocessed annotation:'logger.LogLevelAnnotation' still remaining after LowerToHW
circuit TestHarness :
^
/u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.sfc.fir:39599:10: warning: unprocessed annotation:'freechips.rocketchip.util.RegFieldDescMappingAnnotation' still remaining after LowerToHW
module PeripheryBus :
^
/u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.sfc.fir:186364:10: warning: unprocessed annotation:'firrtl.transforms.DontTouchAnnotation' still remaining after LowerToHW
module DCache :
^
/u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.sfc.fir:206452:10: warning: unprocessed annotation:'freechips.rocketchip.util.ParamsAnnotation' still remaining after LowerToHW
module BTB :
^
/u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.sfc.fir:211238:10: warning: unprocessed annotation:'freechips.rocketchip.util.RetimeModuleAnnotation' still remaining after LowerToHW
module FPUFMAPipe :
^
/u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.sfc.fir:340202:10: warning: unprocessed annotation:'freechips.rocketchip.util.AddressMapAnnotation' still remaining after LowerToHW
module DigitalTop :
^
DescribedSRAM.scala:17:26: warning: unprocessed annotation:'freechips.rocketchip.util.SRAMAnnotation' still remaining after LowerToHW
===-------------------------------------------------------------------------===
... Execution time report ...
===-------------------------------------------------------------------------===
Total Execution Time: 13.1727 seconds
----User Time---- ----Wall Time---- ----Name----
2.8314 ( 7.6%) 2.8314 ( 21.5%) FIR Parser
0.0513 ( 0.1%) 0.0513 ( 0.4%) Parse annotations
0.0000 ( 0.0%) 0.0000 ( 0.0%) Parse OMIR
2.4710 ( 6.6%) 2.4710 ( 18.8%) Parse modules
0.2384 ( 0.6%) 0.2384 ( 1.8%) Verify circuit
22.7374 ( 60.8%) 7.0231 ( 53.3%) 'firrtl.circuit' Pipeline
0.3071 ( 0.8%) 0.3071 ( 2.3%) LowerFIRRTLAnnotations
0.0847 ( 0.2%) 0.0847 ( 0.6%) (A) circt::firrtl::InstanceGraph
0.0641 ( 0.2%) 0.0641 ( 0.5%) LowerIntrinsics
0.0639 ( 0.2%) 0.0639 ( 0.5%) (A) circt::firrtl::InstanceGraph
4.5850 ( 12.3%) 0.3463 ( 2.6%) 'firrtl.module' Pipeline
3.0782 ( 8.2%) 0.2163 ( 1.6%) DropName
1.4507 ( 3.9%) 0.1290 ( 1.0%) CSE
0.0119 ( 0.0%) 0.0026 ( 0.0%) (A) DominanceInfo
0.0000 ( 0.0%) 0.0000 ( 0.0%) InjectDUTHierarchy
1.1487 ( 3.1%) 0.0442 ( 0.3%) 'firrtl.module' Pipeline
0.6162 ( 1.6%) 0.0295 ( 0.2%) LowerCHIRRTLPass
0.6288 ( 1.7%) 0.6288 ( 4.8%) InferWidths
0.2024 ( 0.5%) 0.2024 ( 1.5%) MemToRegOfVec
0.4198 ( 1.1%) 0.4198 ( 3.2%) InferResets
0.0711 ( 0.2%) 0.0711 ( 0.5%) (A) circt::firrtl::InstanceGraph
0.5615 ( 1.5%) 0.5615 ( 4.3%) Dedup
0.0002 ( 0.0%) 0.0002 ( 0.0%) (A) circt::firrtl::NLATable
0.0821 ( 0.2%) 0.0821 ( 0.6%) WireDFT
1.3539 ( 3.6%) 0.1027 ( 0.8%) 'firrtl.module' Pipeline
1.3015 ( 3.5%) 0.1018 ( 0.8%) FlattenMemory
0.3818 ( 1.0%) 0.3818 ( 2.9%) LowerFIRRTLTypes
1.9017 ( 5.1%) 0.1638 ( 1.2%) 'firrtl.module' Pipeline
1.6462 ( 4.4%) 0.1216 ( 0.9%) ExpandWhens
0.1875 ( 0.5%) 0.0418 ( 0.3%) SFCCompat
0.5925 ( 1.6%) 0.5925 ( 4.5%) Inliner
1.5326 ( 4.1%) 0.1006 ( 0.8%) 'firrtl.module' Pipeline
1.4783 ( 4.0%) 0.0897 ( 0.7%) RandomizeRegisterInit
0.5337 ( 1.4%) 0.5337 ( 4.1%) CheckCombLoops
0.0855 ( 0.2%) 0.0855 ( 0.6%) (A) circt::firrtl::InstanceGraph
4.3346 ( 11.6%) 0.3713 ( 2.8%) 'firrtl.module' Pipeline
4.0387 ( 10.8%) 0.3521 ( 2.7%) Canonicalizer
0.2564 ( 0.7%) 0.0185 ( 0.1%) InferReadWrite
0.1951 ( 0.5%) 0.1951 ( 1.5%) LowerMemory
0.0484 ( 0.1%) 0.0484 ( 0.4%) (A) circt::firrtl::InstanceGraph
0.0001 ( 0.0%) 0.0001 ( 0.0%) (A) SymbolTable
0.1084 ( 0.3%) 0.1084 ( 0.8%) PrefixModules
0.0380 ( 0.1%) 0.0380 ( 0.3%) (A) circt::firrtl::InstanceGraph
0.0002 ( 0.0%) 0.0002 ( 0.0%) (A) circt::firrtl::NLATable
0.4413 ( 1.2%) 0.4413 ( 3.3%) IMConstProp
0.0348 ( 0.1%) 0.0348 ( 0.3%) AddSeqMemPorts
0.0346 ( 0.1%) 0.0346 ( 0.3%) (A) circt::firrtl::InstanceGraph
0.1077 ( 0.3%) 0.1077 ( 0.8%) CreateSiFiveMetadata
0.0262 ( 0.1%) 0.0262 ( 0.2%) ExtractInstances
0.0002 ( 0.0%) 0.0002 ( 0.0%) (A) circt::firrtl::NLATable
0.0001 ( 0.0%) 0.0001 ( 0.0%) GrandCentral
0.1003 ( 0.3%) 0.1003 ( 0.8%) BlackBoxReader
0.8578 ( 2.3%) 0.0506 ( 0.4%) 'firrtl.module' Pipeline
0.7959 ( 2.1%) 0.0504 ( 0.4%) DropName
0.2814 ( 0.8%) 0.2814 ( 2.1%) SymbolDCE
0.2333 ( 0.6%) 0.2333 ( 1.8%) InnerSymbolDCE
1.8497 ( 4.9%) 0.6243 ( 4.7%) 'firrtl.circuit' Pipeline
1.2255 ( 3.3%) 0.1130 ( 0.9%) 'firrtl.module' Pipeline
1.1754 ( 3.1%) 0.1128 ( 0.9%) Canonicalizer
0.3083 ( 0.8%) 0.3083 ( 2.3%) IMDeadCodeElim
0.0338 ( 0.1%) 0.0338 ( 0.3%) (A) circt::firrtl::InstanceGraph
0.0001 ( 0.0%) 0.0001 ( 0.0%) EmitOMIR
0.0430 ( 0.1%) 0.0430 ( 0.3%) ResolveTraces
0.0001 ( 0.0%) 0.0001 ( 0.0%) (A) circt::firrtl::NLATable
0.1054 ( 0.3%) 0.1054 ( 0.8%) LowerXMR
0.0252 ( 0.1%) 0.0252 ( 0.2%) (A) circt::firrtl::InstanceGraph
0.3323 ( 0.9%) 0.3323 ( 2.5%) LowerFIRRTLToHW
0.0001 ( 0.0%) 0.0001 ( 0.0%) (A) circt::firrtl::NLATable
0.0191 ( 0.1%) 0.0191 ( 0.1%) (A) circt::firrtl::InstanceGraph
3.1479 ( 8.4%) 0.1662 ( 1.3%) 'hw.module' Pipeline
0.6464 ( 1.7%) 0.0403 ( 0.3%) CSE
0.0193 ( 0.1%) 0.0050 ( 0.0%) (A) DominanceInfo
1.8626 ( 5.0%) 0.1072 ( 0.8%) Canonicalizer
0.2707 ( 0.7%) 0.0122 ( 0.1%) CSE
0.0038 ( 0.0%) 0.0010 ( 0.0%) (A) DominanceInfo
0.2890 ( 0.8%) 0.0147 ( 0.1%) LowerSeqFIRRTLToSV
0.0468 ( 0.1%) 0.0468 ( 0.4%) HWMemSimImpl
2.0826 ( 5.6%) 0.0847 ( 0.6%) 'hw.module' Pipeline
0.6269 ( 1.7%) 0.0406 ( 0.3%) CSE
0.0592 ( 0.2%) 0.0061 ( 0.0%) (A) DominanceInfo
0.7212 ( 1.9%) 0.0337 ( 0.3%) Canonicalizer
0.3632 ( 1.0%) 0.0179 ( 0.1%) CSE
0.0335 ( 0.1%) 0.0055 ( 0.0%) (A) DominanceInfo
0.1835 ( 0.5%) 0.0094 ( 0.1%) HWCleanup
0.8796 ( 2.4%) 0.0363 ( 0.3%) 'hw.module' Pipeline
0.1618 ( 0.4%) 0.0104 ( 0.1%) HWLegalizeModules
0.4828 ( 1.3%) 0.0311 ( 0.2%) PrettifyVerilog
0.0703 ( 0.2%) 0.0703 ( 0.5%) StripDebugInfoWithPred
1.5274 ( 4.1%) 1.5274 ( 11.6%) ExportSplitVerilog
1.3290 ( 3.6%) 0.1347 ( 1.0%) 'builtin.module' Pipeline
1.1943 ( 3.2%) 0.0638 ( 0.5%) 'hw.module' Pipeline
1.1452 ( 3.1%) 0.0624 ( 0.5%) PrepareForEmission
0.0492 ( 0.1%) 0.0492 ( 0.4%) HWExportModuleHierarchy
-0.1146 ( -0.3%) -0.1146 ( -0.9%) Rest
37.4167 (100.0%) 13.1727 (100.0%) Total
mv /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.sfc.mems.conf /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.mems.conf 2> /dev/null
make: [/u/jonthom/creating-a-gds/chipyard/common.mk:232: /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/model_module_hierarchy.json] Error 1 (ignored)
sed -i 's/./& /' /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.mems.conf # need trailing space for SFC macrocompiler
/u/jonthom/creating-a-gds/chipyard/scripts/uniquify-module-names.py
--model-hier-json /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/model_module_hierarchy.json
--top-hier-json /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/top_module_hierarchy.json
--in-all-filelist /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/gen-collateral/filelist.f
--dut ChipTop
--model TestHarness
--target-dir /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/gen-collateral
--out-dut-filelist /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.top.f
--out-model-filelist /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.model.f
--out-model-hier-json /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/model_module_hierarchy.uniquified.json
--gcpath /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/gen-collateral
sed -i s/"module plusarg_reader"/"module plusarg_reader_TestHarness_UNIQUIFIED"/ /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/gen-collateral/plusarg_reader_TestHarness_UNIQUIFIED.v
sed -i s/"plusarg_reader "/"plusarg_reader_TestHarness_UNIQUIFIED "/ /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/gen-collateral/TestHarness.sv
sed -i s/"module plusarg_reader"/"module plusarg_reader_TestHarness_UNIQUIFIED"/ /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/gen-collateral/plusarg_reader_TestHarness_UNIQUIFIED.v
sed -i s/"module ResetCatchAndSync_d3"/"module ResetCatchAndSync_d3_TestHarness_UNIQUIFIED"/ /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/gen-collateral/ResetCatchAndSync_d3_TestHarness_UNIQUIFIED.sv
sed -i s/"ResetCatchAndSync_d3 "/"ResetCatchAndSync_d3_TestHarness_UNIQUIFIED "/ /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/gen-collateral/TestHarness.sv
sed -i s/"module UARTRx"/"module UARTRx_TestHarness_UNIQUIFIED"/ /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/gen-collateral/UARTRx_TestHarness_UNIQUIFIED.sv
sed -i s/"UARTRx "/"UARTRx_TestHarness_UNIQUIFIED "/ /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/gen-collateral/UARTAdapter.sv
sed -i s/"module UARTTx"/"module UARTTx_TestHarness_UNIQUIFIED"/ /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/gen-collateral/UARTTx_TestHarness_UNIQUIFIED.sv
sed -i s/"UARTTx "/"UARTTx_TestHarness_UNIQUIFIED "/ /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/gen-collateral/UARTAdapter.sv
sed -i s/"module AsyncResetSynchronizerShiftReg_w1_d3_i0"/"module AsyncResetSynchronizerShiftReg_w1_d3_i0_TestHarness_UNIQUIFIED"/ /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/gen-collateral/AsyncResetSynchronizerShiftReg_w1_d3_i0_TestHarness_UNIQUIFIED.sv
sed -i s/"AsyncResetSynchronizerShiftReg_w1_d3_i0 "/"AsyncResetSynchronizerShiftReg_w1_d3_i0_TestHarness_UNIQUIFIED "/ /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/gen-collateral/ResetCatchAndSync_d3_TestHarness_UNIQUIFIED.sv
sed -i s/"module HellaPeekingArbiter"/"module HellaPeekingArbiter_TestHarness_UNIQUIFIED"/ /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/gen-collateral/HellaPeekingArbiter_TestHarness_UNIQUIFIED.sv
sed -i s/"HellaPeekingArbiter "/"HellaPeekingArbiter_TestHarness_UNIQUIFIED "/ /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/gen-collateral/TLSerdesser_1.sv
sed -i s/"module GenericSerializer"/"module GenericSerializer_TestHarness_UNIQUIFIED"/ /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/gen-collateral/GenericSerializer_TestHarness_UNIQUIFIED.sv
sed -i s/"GenericSerializer "/"GenericSerializer_TestHarness_UNIQUIFIED "/ /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/gen-collateral/TLSerdesser_1.sv
sed -i s/"module GenericDeserializer"/"module GenericDeserializer_TestHarness_UNIQUIFIED"/ /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/gen-collateral/GenericDeserializer_TestHarness_UNIQUIFIED.sv
sed -i s/"GenericDeserializer "/"GenericDeserializer_TestHarness_UNIQUIFIED "/ /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/gen-collateral/TLSerdesser_1.sv
sed -i s/"module plusarg_reader"/"module plusarg_reader_TestHarness_UNIQUIFIED"/ /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/gen-collateral/plusarg_reader_TestHarness_UNIQUIFIED.v
sed -i s/"plusarg_reader "/"plusarg_reader_TestHarness_UNIQUIFIED "/ /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/gen-collateral/UARTTx_TestHarness_UNIQUIFIED.sv
sed -i s/"module plusarg_reader"/"module plusarg_reader_TestHarness_UNIQUIFIED"/ /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/gen-collateral/plusarg_reader_TestHarness_UNIQUIFIED.v
sed -i s/"module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0"/"module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_TestHarness_UNIQUIFIED"/ /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/gen-collateral/AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_TestHarness_UNIQUIFIED.sv
sed -i s/"AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 "/"AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_TestHarness_UNIQUIFIED "/ /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/gen-collateral/AsyncResetSynchronizerShiftReg_w1_d3_i0_TestHarness_UNIQUIFIED.sv
sed -i s/"module plusarg_reader"/"module plusarg_reader_TestHarness_UNIQUIFIED"/ /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/gen-collateral/plusarg_reader_TestHarness_UNIQUIFIED.v
sed -i s/"plusarg_reader "/"plusarg_reader_TestHarness_UNIQUIFIED "/ /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/gen-collateral/TLMonitor_56.sv
sed -i s/"module plusarg_reader"/"module plusarg_reader_TestHarness_UNIQUIFIED"/ /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/gen-collateral/plusarg_reader_TestHarness_UNIQUIFIED.v
sed -i s/"module plusarg_reader"/"module plusarg_reader_TestHarness_UNIQUIFIED"/ /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/gen-collateral/plusarg_reader_TestHarness_UNIQUIFIED.v
sed -i s/"plusarg_reader "/"plusarg_reader_TestHarness_UNIQUIFIED "/ /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/gen-collateral/TLMonitor_57.sv
sed -i s/"module plusarg_reader"/"module plusarg_reader_TestHarness_UNIQUIFIED"/ /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/gen-collateral/plusarg_reader_TestHarness_UNIQUIFIED.v
sed -i s/"module ram_combMem_19"/"module ram_combMem_19_TestHarness_UNIQUIFIED"/ /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/gen-collateral/ram_combMem_19_TestHarness_UNIQUIFIED.sv
sed -i s/"ram_combMem_19 "/"ram_combMem_19_TestHarness_UNIQUIFIED "/ /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/gen-collateral/Queue_62.sv
sed -e 's;^;/u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/gen-collateral/;' /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/gen-collateral/firrtl_black_box_resource_files.f > /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.bb.f
sed -i 's/.///' /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.top.f
sed -i 's/.///' /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.model.f
sed -i 's/.///' /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.bb.f
sort -u /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.top.f /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.model.f /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.bb.f > /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.all.f
/u/jonthom/creating-a-gds/chipyard/scripts/split-mems-conf.py
--in-smems-conf /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.mems.conf
--in-model-hrchy-json /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/model_module_hierarchy.uniquified.json
--dut-module-name ChipTop
--model-module-name TestHarness
--out-dut-smems-conf /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.top.mems.conf
--out-model-smems-conf /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.model.mems.conf
cd /u/jonthom/creating-a-gds/chipyard && java -cp /u/jonthom/creating-a-gds/chipyard/.classpath_cache/tapeout.jar barstools.macros.MacroCompiler -n /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.top.mems.conf -v /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/gen-collateral/chipyard.harness.TestHarness.RocketConfig.top.mems.v -f /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.top.mems.fir -l /u/jonthom/creating-a-gds/chipyard/.conda-env/lib/python3.10/site-packages/hammer/technology/asap7/sram-cache.json -hir /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.mems.hammer.json --mode strict
Picked up JAVA_TOOL_OPTIONS: -Xmx8G -Xss8M -Djava.io.tmpdir=/u/jonthom/creating-a-gds/chipyard/.java_tmp
Unmasked target memory: unaligned mem maskGran 16 with lib (SRAM1RW128x12) width 12 not supported
Error occurred during bitPairs calculations (bitPairs is empty).
Unmasked target memory: unaligned mem maskGran 16 with lib (SRAM1RW128x14) width 14 not supported
Error occurred during bitPairs calculations (bitPairs is empty).
INFO: unable to compile cc_dir_ext using SRAM2RW128x16 port count must match
INFO: unable to compile cc_dir_ext using SRAM2RW128x32 port count must match
INFO: unable to compile cc_dir_ext using SRAM2RW128x4 port count must match
INFO: unable to compile cc_dir_ext using SRAM2RW128x8 port count must match
INFO: unable to compile cc_dir_ext using SRAM2RW16x16 port count must match
INFO: unable to compile cc_dir_ext using SRAM2RW16x32 port count must match
INFO: unable to compile cc_dir_ext using SRAM2RW16x4 port count must match
INFO: unable to compile cc_dir_ext using SRAM2RW16x8 port count must match
INFO: unable to compile cc_dir_ext using SRAM2RW32x16 port count must match
INFO: unable to compile cc_dir_ext using SRAM2RW32x22 port count must match
INFO: unable to compile cc_dir_ext using SRAM2RW32x32 port count must match
INFO: unable to compile cc_dir_ext using SRAM2RW32x33 port count must match
INFO: unable to compile cc_dir_ext using SRAM2RW32x39 port count must match
INFO: unable to compile cc_dir_ext using SRAM2RW32x4 port count must match
INFO: unable to compile cc_dir_ext using SRAM2RW32x8 port count must match
INFO: unable to compile cc_dir_ext using SRAM2RW64x16 port count must match
INFO: unable to compile cc_dir_ext using SRAM2RW64x24 port count must match
INFO: unable to compile cc_dir_ext using SRAM2RW64x32 port count must match
INFO: unable to compile cc_dir_ext using SRAM2RW64x4 port count must match
INFO: unable to compile cc_dir_ext using SRAM2RW64x8 port count must match
INFO: unable to compile cc_banks_0_ext using SRAM2RW128x16 port count must match
INFO: unable to compile cc_banks_0_ext using SRAM2RW128x32 port count must match
INFO: unable to compile cc_banks_0_ext using SRAM2RW128x4 port count must match
INFO: unable to compile cc_banks_0_ext using SRAM2RW128x8 port count must match
INFO: unable to compile cc_banks_0_ext using SRAM2RW16x16 port count must match
INFO: unable to compile cc_banks_0_ext using SRAM2RW16x32 port count must match
INFO: unable to compile cc_banks_0_ext using SRAM2RW16x4 port count must match
INFO: unable to compile cc_banks_0_ext using SRAM2RW16x8 port count must match
INFO: unable to compile cc_banks_0_ext using SRAM2RW32x16 port count must match
INFO: unable to compile cc_banks_0_ext using SRAM2RW32x22 port count must match
INFO: unable to compile cc_banks_0_ext using SRAM2RW32x32 port count must match
INFO: unable to compile cc_banks_0_ext using SRAM2RW32x33 port count must match
INFO: unable to compile cc_banks_0_ext using SRAM2RW32x39 port count must match
INFO: unable to compile cc_banks_0_ext using SRAM2RW32x4 port count must match
INFO: unable to compile cc_banks_0_ext using SRAM2RW32x8 port count must match
INFO: unable to compile cc_banks_0_ext using SRAM2RW64x16 port count must match
INFO: unable to compile cc_banks_0_ext using SRAM2RW64x24 port count must match
INFO: unable to compile cc_banks_0_ext using SRAM2RW64x32 port count must match
INFO: unable to compile cc_banks_0_ext using SRAM2RW64x4 port count must match
INFO: unable to compile cc_banks_0_ext using SRAM2RW64x8 port count must match
INFO: unable to compile data_arrays_0_ext using SRAM2RW128x16 port count must match
INFO: unable to compile data_arrays_0_ext using SRAM2RW128x32 port count must match
INFO: unable to compile data_arrays_0_ext using SRAM2RW128x4 port count must match
INFO: unable to compile data_arrays_0_ext using SRAM2RW128x8 port count must match
INFO: unable to compile data_arrays_0_ext using SRAM2RW16x16 port count must match
INFO: unable to compile data_arrays_0_ext using SRAM2RW16x32 port count must match
INFO: unable to compile data_arrays_0_ext using SRAM2RW16x4 port count must match
INFO: unable to compile data_arrays_0_ext using SRAM2RW16x8 port count must match
INFO: unable to compile data_arrays_0_ext using SRAM2RW32x16 port count must match
INFO: unable to compile data_arrays_0_ext using SRAM2RW32x22 port count must match
INFO: unable to compile data_arrays_0_ext using SRAM2RW32x32 port count must match
INFO: unable to compile data_arrays_0_ext using SRAM2RW32x33 port count must match
INFO: unable to compile data_arrays_0_ext using SRAM2RW32x39 port count must match
INFO: unable to compile data_arrays_0_ext using SRAM2RW32x4 port count must match
INFO: unable to compile data_arrays_0_ext using SRAM2RW32x8 port count must match
INFO: unable to compile data_arrays_0_ext using SRAM2RW64x16 port count must match
INFO: unable to compile data_arrays_0_ext using SRAM2RW64x24 port count must match
INFO: unable to compile data_arrays_0_ext using SRAM2RW64x32 port count must match
INFO: unable to compile data_arrays_0_ext using SRAM2RW64x4 port count must match
INFO: unable to compile data_arrays_0_ext using SRAM2RW64x8 port count must match
Unmasked target memory: unaligned mem maskGran 22 with lib (SRAM1RW1024x16) width 16 not supported
Error occurred during bitPairs calculations (bitPairs is empty).
Unmasked target memory: unaligned mem maskGran 22 with lib (SRAM1RW1024x17) width 17 not supported
Error occurred during bitPairs calculations (bitPairs is empty).
Unmasked target memory: unaligned mem maskGran 22 with lib (SRAM1RW1024x8) width 8 not supported
Error occurred during bitPairs calculations (bitPairs is empty).
Unmasked target memory: unaligned mem maskGran 22 with lib (SRAM1RW2048x8) width 8 not supported
Error occurred during bitPairs calculations (bitPairs is empty).
Unmasked target memory: unaligned mem maskGran 22 with lib (SRAM1RW128x12) width 12 not supported
Error occurred during bitPairs calculations (bitPairs is empty).
Unmasked target memory: unaligned mem maskGran 22 with lib (SRAM1RW128x14) width 14 not supported
Error occurred during bitPairs calculations (bitPairs is empty).
Unmasked target memory: unaligned mem maskGran 22 with lib (SRAM1RW128x8) width 8 not supported
Error occurred during bitPairs calculations (bitPairs is empty).
Unmasked target memory: unaligned mem maskGran 22 with lib (SRAM1RW256x8) width 8 not supported
Error occurred during bitPairs calculations (bitPairs is empty).
Unmasked target memory: unaligned mem maskGran 22 with lib (SRAM1RW4096x16) width 16 not supported
Error occurred during bitPairs calculations (bitPairs is empty).
Unmasked target memory: unaligned mem maskGran 22 with lib (SRAM1RW4096x8) width 8 not supported
Error occurred during bitPairs calculations (bitPairs is empty).
Unmasked target memory: unaligned mem maskGran 22 with lib (SRAM1RW512x8) width 8 not supported
Error occurred during bitPairs calculations (bitPairs is empty).
Unmasked target memory: unaligned mem maskGran 22 with lib (SRAM1RW64x20) width 20 not supported
Error occurred during bitPairs calculations (bitPairs is empty).
Unmasked target memory: unaligned mem maskGran 22 with lib (SRAM1RW64x21) width 21 not supported
Error occurred during bitPairs calculations (bitPairs is empty).
Unmasked target memory: unaligned mem maskGran 22 with lib (SRAM1RW64x8) width 8 not supported
Error occurred during bitPairs calculations (bitPairs is empty).
INFO: unable to compile tag_array_ext using SRAM2RW128x16 port count must match
INFO: unable to compile tag_array_ext using SRAM2RW128x32 port count must match
INFO: unable to compile tag_array_ext using SRAM2RW128x4 port count must match
INFO: unable to compile tag_array_ext using SRAM2RW128x8 port count must match
INFO: unable to compile tag_array_ext using SRAM2RW16x16 port count must match
INFO: unable to compile tag_array_ext using SRAM2RW16x32 port count must match
INFO: unable to compile tag_array_ext using SRAM2RW16x4 port count must match
INFO: unable to compile tag_array_ext using SRAM2RW16x8 port count must match
INFO: unable to compile tag_array_ext using SRAM2RW32x16 port count must match
INFO: unable to compile tag_array_ext using SRAM2RW32x22 port count must match
INFO: unable to compile tag_array_ext using SRAM2RW32x32 port count must match
INFO: unable to compile tag_array_ext using SRAM2RW32x33 port count must match
INFO: unable to compile tag_array_ext using SRAM2RW32x39 port count must match
INFO: unable to compile tag_array_ext using SRAM2RW32x4 port count must match
INFO: unable to compile tag_array_ext using SRAM2RW32x8 port count must match
INFO: unable to compile tag_array_ext using SRAM2RW64x16 port count must match
INFO: unable to compile tag_array_ext using SRAM2RW64x24 port count must match
INFO: unable to compile tag_array_ext using SRAM2RW64x32 port count must match
INFO: unable to compile tag_array_ext using SRAM2RW64x4 port count must match
INFO: unable to compile tag_array_ext using SRAM2RW64x8 port count must match
Unmasked target memory: unaligned mem maskGran 21 with lib (SRAM1RW1024x16) width 16 not supported
Error occurred during bitPairs calculations (bitPairs is empty).
Unmasked target memory: unaligned mem maskGran 21 with lib (SRAM1RW1024x17) width 17 not supported
Error occurred during bitPairs calculations (bitPairs is empty).
Unmasked target memory: unaligned mem maskGran 21 with lib (SRAM1RW1024x8) width 8 not supported
Error occurred during bitPairs calculations (bitPairs is empty).
Unmasked target memory: unaligned mem maskGran 21 with lib (SRAM1RW2048x8) width 8 not supported
Error occurred during bitPairs calculations (bitPairs is empty).
Unmasked target memory: unaligned mem maskGran 21 with lib (SRAM1RW128x12) width 12 not supported
Error occurred during bitPairs calculations (bitPairs is empty).
Unmasked target memory: unaligned mem maskGran 21 with lib (SRAM1RW128x14) width 14 not supported
Error occurred during bitPairs calculations (bitPairs is empty).
Unmasked target memory: unaligned mem maskGran 21 with lib (SRAM1RW128x8) width 8 not supported
Error occurred during bitPairs calculations (bitPairs is empty).
Unmasked target memory: unaligned mem maskGran 21 with lib (SRAM1RW256x8) width 8 not supported
Error occurred during bitPairs calculations (bitPairs is empty).
Unmasked target memory: unaligned mem maskGran 21 with lib (SRAM1RW4096x16) width 16 not supported
Error occurred during bitPairs calculations (bitPairs is empty).
Unmasked target memory: unaligned mem maskGran 21 with lib (SRAM1RW4096x8) width 8 not supported
Error occurred during bitPairs calculations (bitPairs is empty).
Unmasked target memory: unaligned mem maskGran 21 with lib (SRAM1RW512x8) width 8 not supported
Error occurred during bitPairs calculations (bitPairs is empty).
Unmasked target memory: unaligned mem maskGran 21 with lib (SRAM1RW64x20) width 20 not supported
Error occurred during bitPairs calculations (bitPairs is empty).
Unmasked target memory: unaligned mem maskGran 21 with lib (SRAM1RW64x8) width 8 not supported
Error occurred during bitPairs calculations (bitPairs is empty).
INFO: unable to compile tag_array_0_ext using SRAM2RW128x16 port count must match
INFO: unable to compile tag_array_0_ext using SRAM2RW128x32 port count must match
INFO: unable to compile tag_array_0_ext using SRAM2RW128x4 port count must match
INFO: unable to compile tag_array_0_ext using SRAM2RW128x8 port count must match
INFO: unable to compile tag_array_0_ext using SRAM2RW16x16 port count must match
INFO: unable to compile tag_array_0_ext using SRAM2RW16x32 port count must match
INFO: unable to compile tag_array_0_ext using SRAM2RW16x4 port count must match
INFO: unable to compile tag_array_0_ext using SRAM2RW16x8 port count must match
INFO: unable to compile tag_array_0_ext using SRAM2RW32x16 port count must match
INFO: unable to compile tag_array_0_ext using SRAM2RW32x22 port count must match
INFO: unable to compile tag_array_0_ext using SRAM2RW32x32 port count must match
INFO: unable to compile tag_array_0_ext using SRAM2RW32x33 port count must match
INFO: unable to compile tag_array_0_ext using SRAM2RW32x39 port count must match
INFO: unable to compile tag_array_0_ext using SRAM2RW32x4 port count must match
INFO: unable to compile tag_array_0_ext using SRAM2RW32x8 port count must match
INFO: unable to compile tag_array_0_ext using SRAM2RW64x16 port count must match
INFO: unable to compile tag_array_0_ext using SRAM2RW64x24 port count must match
INFO: unable to compile tag_array_0_ext using SRAM2RW64x32 port count must match
INFO: unable to compile tag_array_0_ext using SRAM2RW64x4 port count must match
INFO: unable to compile tag_array_0_ext using SRAM2RW64x8 port count must match
Unmasked target memory: unaligned mem maskGran 32 with lib (SRAM1RW1024x17) width 17 not supported
Error occurred during bitPairs calculations (bitPairs is empty).
Unmasked target memory: unaligned mem maskGran 32 with lib (SRAM1RW128x12) width 12 not supported
Error occurred during bitPairs calculations (bitPairs is empty).
Unmasked target memory: unaligned mem maskGran 32 with lib (SRAM1RW128x14) width 14 not supported
Error occurred during bitPairs calculations (bitPairs is empty).
Unmasked target memory: unaligned mem maskGran 32 with lib (SRAM1RW128x22) width 22 not supported
Error occurred during bitPairs calculations (bitPairs is empty).
Unmasked target memory: unaligned mem maskGran 32 with lib (SRAM1RW64x20) width 20 not supported
Error occurred during bitPairs calculations (bitPairs is empty).
Unmasked target memory: unaligned mem maskGran 32 with lib (SRAM1RW64x21) width 21 not supported
Error occurred during bitPairs calculations (bitPairs is empty).
Unmasked target memory: unaligned mem maskGran 32 with lib (SRAM1RW64x22) width 22 not supported
Error occurred during bitPairs calculations (bitPairs is empty).
INFO: unable to compile data_arrays_0_0_ext using SRAM2RW128x16 port count must match
INFO: unable to compile data_arrays_0_0_ext using SRAM2RW128x32 port count must match
INFO: unable to compile data_arrays_0_0_ext using SRAM2RW128x4 port count must match
INFO: unable to compile data_arrays_0_0_ext using SRAM2RW128x8 port count must match
INFO: unable to compile data_arrays_0_0_ext using SRAM2RW16x16 port count must match
INFO: unable to compile data_arrays_0_0_ext using SRAM2RW16x32 port count must match
INFO: unable to compile data_arrays_0_0_ext using SRAM2RW16x4 port count must match
INFO: unable to compile data_arrays_0_0_ext using SRAM2RW16x8 port count must match
INFO: unable to compile data_arrays_0_0_ext using SRAM2RW32x16 port count must match
INFO: unable to compile data_arrays_0_0_ext using SRAM2RW32x22 port count must match
INFO: unable to compile data_arrays_0_0_ext using SRAM2RW32x32 port count must match
INFO: unable to compile data_arrays_0_0_ext using SRAM2RW32x33 port count must match
INFO: unable to compile data_arrays_0_0_ext using SRAM2RW32x39 port count must match
INFO: unable to compile data_arrays_0_0_ext using SRAM2RW32x4 port count must match
INFO: unable to compile data_arrays_0_0_ext using SRAM2RW32x8 port count must match
INFO: unable to compile data_arrays_0_0_ext using SRAM2RW64x16 port count must match
INFO: unable to compile data_arrays_0_0_ext using SRAM2RW64x24 port count must match
INFO: unable to compile data_arrays_0_0_ext using SRAM2RW64x32 port count must match
INFO: unable to compile data_arrays_0_0_ext using SRAM2RW64x4 port count must match
INFO: unable to compile data_arrays_0_0_ext using SRAM2RW64x8 port count must match
cat /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.top.f | sort -u > /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/syn.f
echo /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/gen-collateral/chipyard.harness.TestHarness.RocketConfig.top.mems.v >> /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/syn.f
mkdir -p /u/jonthom/creating-a-gds/chipyard/vlsi/build/chipyard.harness.TestHarness.RocketConfig-ChipTop/
echo "sim.inputs:" > /u/jonthom/creating-a-gds/chipyard/vlsi/build/chipyard.harness.TestHarness.RocketConfig-ChipTop/inputs.yml
echo " input_files:" >> /u/jonthom/creating-a-gds/chipyard/vlsi/build/chipyard.harness.TestHarness.RocketConfig-ChipTop/inputs.yml
for x in $(cat /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/syn.f); do
echo ' - "'$x'"' >> /u/jonthom/creating-a-gds/chipyard/vlsi/build/chipyard.harness.TestHarness.RocketConfig-ChipTop/inputs.yml;
done
echo " input_files_meta: 'append'" >> /u/jonthom/creating-a-gds/chipyard/vlsi/build/chipyard.harness.TestHarness.RocketConfig-ChipTop/inputs.yml
echo "synthesis.inputs:" >> /u/jonthom/creating-a-gds/chipyard/vlsi/build/chipyard.harness.TestHarness.RocketConfig-ChipTop/inputs.yml
echo " top_module: ChipTop" >> /u/jonthom/creating-a-gds/chipyard/vlsi/build/chipyard.harness.TestHarness.RocketConfig-ChipTop/inputs.yml
echo " input_files:" >> /u/jonthom/creating-a-gds/chipyard/vlsi/build/chipyard.harness.TestHarness.RocketConfig-ChipTop/inputs.yml
for x in $(cat /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/syn.f); do
echo ' - "'$x'"' >> /u/jonthom/creating-a-gds/chipyard/vlsi/build/chipyard.harness.TestHarness.RocketConfig-ChipTop/inputs.yml;
done
mkdir -p /u/jonthom/creating-a-gds/chipyard/vlsi/build/chipyard.harness.TestHarness.RocketConfig-ChipTop/
echo "vlsi.inputs.sram_parameters: '/u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig/chipyard.harness.TestHarness.RocketConfig.mems.hammer.json'" >> /u/jonthom/creating-a-gds/chipyard/vlsi/build/chipyard.harness.TestHarness.RocketConfig-ChipTop/sram_generator-input.yml
echo "vlsi.inputs.sram_parameters_meta: ["transclude", "json2list"]">> /u/jonthom/creating-a-gds/chipyard/vlsi/build/chipyard.harness.TestHarness.RocketConfig-ChipTop/sram_generator-input.yml
cd /u/jonthom/creating-a-gds/chipyard/vlsi && ./example-vlsi -e /u/jonthom/creating-a-gds/chipyard/vlsi/env.yml -p example-tools.yml -p example-asap7.yml -p /u/jonthom/creating-a-gds/chipyard/vlsi/build/chipyard.harness.TestHarness.RocketConfig-ChipTop/sram_generator-input.yml --obj_dir /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.RocketConfig sram_generator
[] Loading hammer-vlsi libraries and reading settings
[] Loading technology 'hammer.technology.asap7'
[] Key technology.asap7.pdk_install_dir has a type str is not yet implemented
[] Key technology.asap7.stdcell_install_dir has a type str is not yet implemented
[tech] Extracting/verifying tarball /stash/asap7/ASAP7_PDK_CalibreDeck.tar
[tech] gdstk not found, falling back to gdspy...
[tech] Generating GDS for Multi-VT cells using gdspy...
[tech] Fixing ICG LIBs...
[] Starting SRAM Generator with tool 'sram_compiler'
[sram_generator] Running sub-step 'generate_all_srams_and_corners'
Action sram_generator config output written to output.json
cd /u/jonthom/creating-a-gds/chipyard/vlsi && cp output.json /u/jonthom/creating-a-gds/chipyard/vlsi/build/chipyard.harness.TestHarness.RocketConfig-ChipTop/sram_generator-output.json
./example-vlsi -e /u/jonthom/creating-a-gds/chipyard/vlsi/env.yml -p example-tools.yml -p example-asap7.yml -p /u/jonthom/creating-a-gds/chipyard/vlsi/build/chipyard.harness.TestHarness.RocketConfig-ChipTop/inputs.yml -p /u/jonthom/creating-a-gds/chipyard/vlsi/build/chipyard.harness.TestHarness.RocketConfig-ChipTop/sram_generator-output.json --obj_dir /u/jonthom/creating-a-gds/chipyard/vlsi/build/chipyard.harness.TestHarness.RocketConfig-ChipTop build
[] Loading hammer-vlsi libraries and reading settings
[] Loading technology 'hammer.technology.asap7'
[] Key technology.asap7.pdk_install_dir has a type str is not yet implemented
[] Key technology.asap7.stdcell_install_dir has a type str is not yet implemented
[tech] Extracting/verifying tarball /stash/asap7/ASAP7_PDK_CalibreDeck.tar
[tech] gdstk not found, falling back to gdspy...
[tech] Generating GDS for Multi-VT cells using gdspy...
[tech] Fixing ICG LIBs...
Action build config output written to output.json
Running with RISCV=/u/jonthom/creating-a-gds/chipyard/.conda-env/riscv-tools
rm -rf build hammer-vlsi.log pycache output.json /u/jonthom/creating-a-gds/chipyard/vlsi/build/chipyard.harness.TestHarness.RocketConfig-ChipTop/inputs.yml /u/jonthom/creating-a-gds/chipyard/vlsi/build/chipyard.harness.TestHarness.RocketConfig-ChipTop/sram_generator-output.json /u/jonthom/creating-a-gds/chipyard/.classpath_cache /u/jonthom/creating-a-gds/chipyard/vlsi/generated-src /u/jonthom/creating-a-gds/chipyard/vlsi/build/chipyard.harness.TestHarness.RocketConfig-ChipTop/sim-inputs.yml /u/jonthom/creating-a-gds/chipyard/vlsi/build/chipyard.harness.TestHarness.RocketConfig-ChipTop/sim-debug-inputs.yml /u/jonthom/creating-a-gds/chipyard/vlsi/build/chipyard.harness.TestHarness.RocketConfig-ChipTop/sim-timing-inputs.yml /u/jonthom/creating-a-gds/chipyard/vlsi/build/chipyard.harness.TestHarness.RocketConfig-ChipTop/power-inputs.yml
(/u/jonthom/creating-a-gds/chipyard/.conda-env) bash-4.2$ make buildfile CUSTOM_VLOG=or_gate.sv VLSI_TOP=or_gate
Running with RISCV=/u/jonthom/creating-a-gds/chipyard/.conda-env/riscv-tools
It seems like the hammer scripts will still look for the default RocketConfig verilog files list.
Scenario 2 - Without Make clean
Here, the make command was run for the custom Verilog, but the entire Hammer VLSI flow had already been run on TinyRocketConfig (or any other Chipyard config). The same "CONFIG" (TinyRocketConfig in this case) was given for the custom verilog hammer flow also.
Design used - the same or gate as before
Commands used:
Error:
No more make errors and the input.yml and the hammer.d files are getting generated for the correct RTL(or gate in this case).
But placement and routing never completes(it hangs).
The following errors were seen in the log files
Genus.log
Innovus.log
Could you please provide us with some instructions on how to proceed. Thanks.
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