From e7ac96e6b63b3ca617e827cbfcb0fb1514b6c04f Mon Sep 17 00:00:00 2001 From: Ethan Wu Date: Tue, 3 Sep 2024 13:28:54 -0700 Subject: [PATCH] Fix floorplan for example Sky130 VLSI flow Update floorplan for changed SRAM instances. --- .../sky130-openroad-rockettile.yml | 46 ++++++++-------- vlsi/example-designs/sky130-openroad.yml | 45 +++++++++------- vlsi/example-designs/sky130-rocket.yml | 14 ++--- vlsi/example-sky130.yml | 53 ++++++++++--------- 4 files changed, 86 insertions(+), 72 deletions(-) diff --git a/vlsi/example-designs/sky130-openroad-rockettile.yml b/vlsi/example-designs/sky130-openroad-rockettile.yml index cfc4c5bb52..0cb61792ae 100644 --- a/vlsi/example-designs/sky130-openroad-rockettile.yml +++ b/vlsi/example-designs/sky130-openroad-rockettile.yml @@ -13,38 +13,42 @@ vlsi.inputs.placement_constraints: type: toplevel x: 0 y: 0 - width: 4000 - height: 3000 + width: 3588 + height: 2992 margins: - left: 10 - right: 0 - top: 10 - bottom: 10 + left: 10.12 + right: 10.12 + top: 10.88 + bottom: 10.88 # Place SRAM memory instances # data cache - - path: "RocketTile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0" + - path: "RocketTile/dcache/data/rockettile_dcache_data_arrays_0/rockettile_dcache_data_arrays_0_ext/mem_0_0" type: hardmacro - x: 50 - y: 50 + x: 49.68 + y: 149.6 orientation: r90 - - path: "RocketTile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0" + - path: "RocketTile/dcache/data/rockettile_dcache_data_arrays_1/rockettile_dcache_data_arrays_0_ext/mem_0_0" type: hardmacro - x: 50 - y: 800 + x: 49.68 + y: 748 orientation: r90 # tag array - - path: "RocketTile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0" + - path: "RocketTile/system/tile_prci_domain/element_reset_domain_rockettile/frontend/icache/rockettile_icache_tag_array_0/rockettile_icache_tag_array_0_ext/mem_0_0" type: hardmacro - x: 50 - y: 1600 - orientation: r90 + x: 2612.8 + y: 1033.6 + orientation: mx90 # instruction cache - - path: "RocketTile/frontend/icache/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0" + - path: "RocketTile/frontend/icache/rockettile_icache_data_arrays_0_0/rockettile_icache_data_arrays_0_0_ext/mem_0_0" type: hardmacro - x: 50 - y: 2100 - orientation: r90 - + x: 2612.8 + y: 149.6 + orientation: mx90 + - path: "RocketTile/frontend/icache/rockettile_icache_data_arrays_1_0/rockettile_icache_data_arrays_0_0_ext/mem_0_0" + type: hardmacro + x: 2612.8 + y: 598.4 + orientation: mx90 diff --git a/vlsi/example-designs/sky130-openroad.yml b/vlsi/example-designs/sky130-openroad.yml index a686fbba4f..a70422c203 100644 --- a/vlsi/example-designs/sky130-openroad.yml +++ b/vlsi/example-designs/sky130-openroad.yml @@ -45,37 +45,42 @@ vlsi.inputs.placement_constraints: type: toplevel x: 0 y: 0 - width: 4000 - height: 3000 + width: 3588 + height: 2992 margins: - left: 10 - right: 0 - top: 10 - bottom: 10 + left: 10.12 + right: 10.12 + top: 10.88 + bottom: 10.88 # Place SRAM memory instances # data cache - - path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0" + - path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/dcache/data/rockettile_dcache_data_arrays_0/rockettile_dcache_data_arrays_0_ext/mem_0_0" type: hardmacro - x: 50 - y: 50 + x: 49.68 + y: 149.6 orientation: r90 - - path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0" + - path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/dcache/data/rockettile_dcache_data_arrays_1/rockettile_dcache_data_arrays_0_ext/mem_0_0" type: hardmacro - x: 50 - y: 800 + x: 49.68 + y: 748 orientation: r90 # tag array - - path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0" + - path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/frontend/icache/rockettile_icache_tag_array_0/rockettile_icache_tag_array_0_ext/mem_0_0" type: hardmacro - x: 50 - y: 1600 - orientation: r90 + x: 2612.8 + y: 1033.6 + orientation: mx90 # instruction cache - - path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/frontend/icache/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0" + - path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/frontend/icache/rockettile_icache_data_arrays_0_0/rockettile_icache_data_arrays_0_0_ext/mem_0_0" type: hardmacro - x: 50 - y: 2100 - orientation: r90 + x: 2612.8 + y: 149.6 + orientation: mx90 + - path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/frontend/icache/rockettile_icache_data_arrays_1_0/rockettile_icache_data_arrays_0_0_ext/mem_0_0" + type: hardmacro + x: 2612.8 + y: 598.4 + orientation: mx90 diff --git a/vlsi/example-designs/sky130-rocket.yml b/vlsi/example-designs/sky130-rocket.yml index 7e95e331ed..e47e9f10d5 100644 --- a/vlsi/example-designs/sky130-rocket.yml +++ b/vlsi/example-designs/sky130-rocket.yml @@ -3,7 +3,7 @@ # Specify clock signals # Rocket/RocketTile names clock signal "clock" instead of "clock_uncore" vlsi.inputs.clocks: [ - {name: "clock", period: "5ns", uncertainty: "1ns"} + {name: "clock", period: "20ns", uncertainty: "1ns"} ] # Placement Constraints @@ -13,10 +13,10 @@ vlsi.inputs.placement_constraints: type: toplevel x: 0 y: 0 - width: 2500 - height: 1500 + width: 2500.1 + height: 1496 margins: - left: 10 - right: 10 - top: 10 - bottom: 10 + left: 10.12 + right: 10.12 + top: 10.88 + bottom: 10.88 diff --git a/vlsi/example-sky130.yml b/vlsi/example-sky130.yml index 3f45bd3d26..644a567a8c 100644 --- a/vlsi/example-sky130.yml +++ b/vlsi/example-sky130.yml @@ -2,15 +2,15 @@ # Technology used is Sky130 vlsi.core.technology: "hammer.technology.sky130" -vlsi.core.max_threads: 12 +vlsi.core.max_threads: 48 # Technology paths technology.sky130: - sky130A: "/path/to/sky130A" - sram22_sky130_macros: "/path/to/sram22_sky130_macros" + sky130A: "/home/etw/chipyard/.conda-env/share/pdk/sky130A" + sram22_sky130_macros: "/home/etw/sram22_sky130_macros" # this key is OPTIONAL, no NDA files will be used if it does not point to a valid path - sky130_nda: "/path/to/skywater-src-nda" + #sky130_nda: "/path/to/skywater-src-nda" # General Hammer Inputs @@ -33,40 +33,45 @@ vlsi.inputs.placement_constraints: type: toplevel x: 0 y: 0 - width: 4000 - height: 3000 + width: 3588 + height: 2992 margins: - left: 10 - right: 0 - top: 10 - bottom: 10 + left: 10.12 + right: 10.12 + top: 10.88 + bottom: 10.88 # Place SRAM memory instances # data cache - - path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0" + - path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/dcache/data/rockettile_dcache_data_arrays_0/rockettile_dcache_data_arrays_0_ext/mem_0_0" type: hardmacro - x: 50 - y: 50 + x: 49.68 + y: 149.6 orientation: r90 - - path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0" + - path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/dcache/data/rockettile_dcache_data_arrays_1/rockettile_dcache_data_arrays_0_ext/mem_0_0" type: hardmacro - x: 50 - y: 800 + x: 49.68 + y: 748 orientation: r90 # tag array - - path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0" + - path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/frontend/icache/rockettile_icache_tag_array_0/rockettile_icache_tag_array_0_ext/mem_0_0" type: hardmacro - x: 50 - y: 1600 - orientation: r90 + x: 2612.8 + y: 1033.6 + orientation: mx90 # instruction cache - - path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/frontend/icache/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0" + - path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/frontend/icache/rockettile_icache_data_arrays_0_0/rockettile_icache_data_arrays_0_0_ext/mem_0_0" type: hardmacro - x: 50 - y: 2100 - orientation: r90 + x: 2612.8 + y: 149.6 + orientation: mx90 + - path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/frontend/icache/rockettile_icache_data_arrays_1_0/rockettile_icache_data_arrays_0_0_ext/mem_0_0" + type: hardmacro + x: 2612.8 + y: 598.4 + orientation: mx90 # Power Straps