From 82101197a818849f098bb8ca10dd8d6959fbab99 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 6 Aug 2024 00:37:36 -0700 Subject: [PATCH 1/2] Support variable MMU capabilities in cosim --- generators/chipyard/src/main/scala/iobinders/IOBinders.scala | 1 + generators/testchipip | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala index ca64fc47be..32060c79cb 100644 --- a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala +++ b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala @@ -487,6 +487,7 @@ class WithTraceIOPunchthrough extends OverrideLazyIOBinder({ val cfg = SpikeCosimConfig( isa = tiles.headOption.map(_.isaDTS).getOrElse(""), priv = tiles.headOption.map(t => if (t.usingUser) "MSU" else if (t.usingSupervisor) "MS" else "M").getOrElse(""), + maxpglevels = tiles.headOption.map(_.tileParams.core.pgLevels).getOrElse(0), mem0_base = p(ExtMem).map(_.master.base).getOrElse(BigInt(0)), mem0_size = p(ExtMem).map(_.master.size).getOrElse(BigInt(0)), pmpregions = tiles.headOption.map(_.tileParams.core.nPMPs).getOrElse(0), diff --git a/generators/testchipip b/generators/testchipip index ebd119882d..541864d602 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit ebd119882d92a5af2fc59da91da1e2656e379abe +Subproject commit 541864d602ba9021e0256d7bf0da2a2a25acdb91 From a85c9ed263143e49f4d970da721db52dc9429e65 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 6 Aug 2024 12:41:23 -0700 Subject: [PATCH 2/2] Bump firesim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 1aedadba44..c655c8905d 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 1aedadba448bf6f2343157e6c43642cac1766c05 +Subproject commit c655c8905dc0e59d1aa61bb3ccbbf1d07c888648