diff --git a/CHANGELOG.md b/CHANGELOG.md
index 3644fa296c..8e7ed00315 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -2,6 +2,34 @@
 
 This changelog follows the format defined here: https://keepachangelog.com/en/1.0.0/
 
+## [1.9.1] - 2023-04-21
+
+Various fixes for Linux boot, More Chip/bringup examples, Chisel 3.5.6 bump
+
+### Added
+* QoL improvement to IOBinders + custom ChipTop example by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1399
+* PLL integration example + FlatChipTop/TestHarness by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1427
+* Bump TestChipIp to improve default serial_tl behavior by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1435
+* Bump testchipip to standardize TL serdesser bundle params by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1446
+* HarnessBinder asserts to catch bad clock generation by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1460
+
+### Changed
+* New Scala-based Config Finder by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1424
+* Bump to latest rocket-chip/chisel3.5.6 by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1411
+* Resolve merge conflicts in chisel3.5.6 bump by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1430
+* bump testchipip by @joey0320 in https://github.com/ucb-bar/chipyard/pull/1434
+* ADD: improve Makefile in tests/, add explicit arch flags by @T-K-233 in https://github.com/ucb-bar/chipyard/pull/1439
+* Various submodule bumps by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1448
+* Support not instantiating tile reset/clock contorl features by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1459
+
+### Fixed
+* Various improvements and fixes by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1420
+* Ensure conda cleanup regex properly filters out non-numeric chars by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1425
+* Fix ChipLikeQuadRocketConfig crossing by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1436
+* Uniquify module names that are common to Top & Model by @joey0320 in https://github.com/ucb-bar/chipyard/pull/1442
+* Support for no-bootROM systems by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1458
+* Support for no-UART systems by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1457
+
 ## [1.9.0] - 2023-03-23
 
 Faster FIRRTL build support work CIRCT. New software support for RISC-V GCC12 and Linux 6.2. Various bumps and fixes of all submodules.
diff --git a/README.md b/README.md
index a21b142edd..91aa07efe8 100644
--- a/README.md
+++ b/README.md
@@ -2,9 +2,6 @@
 
 # Chipyard Framework [![Test](https://github.com/ucb-bar/chipyard/actions/workflows/chipyard-run-tests.yml/badge.svg)](https://github.com/ucb-bar/chipyard/actions)
 
-| We're running the First FireSim and Chipyard User/Developer Workshop at ASPLOS 2023 on March 26, 2023! This workshop will feature a full-day of submitted talks from users and developers in the FireSim and Chipyard community. Learn more and **submit your work** on the [2023 Workshop Page](https://fires.im/workshop-2023/)! |
-|-----|
-
 ## Quick Links
 
 * **Stable Documentation**: https://chipyard.readthedocs.io/
diff --git a/generators/gemmini b/generators/gemmini
index 965ea0b3c5..80e7376cf5 160000
--- a/generators/gemmini
+++ b/generators/gemmini
@@ -1 +1 @@
-Subproject commit 965ea0b3c5ffd7b68e6bf5a50ea9ff0750a5b988
+Subproject commit 80e7376cf554ed302975d72ed091ac86a9e553e8
diff --git a/sims/firesim b/sims/firesim
index 8c85960b93..3ae68ec307 160000
--- a/sims/firesim
+++ b/sims/firesim
@@ -1 +1 @@
-Subproject commit 8c85960b939a0090de30a31936981972874d979d
+Subproject commit 3ae68ec3076c010c633ded369fd3874ec2e5e557