uart_pl011.c

/*-
 * Copyright (c) 2012 Semihalf.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

#include <subr.h>
#include <types.h>
#include <bcm2836.h>

/* PL011 UART registers and masks*/
#define	UART_DR		0x00		/* Data register */
#define	DR_FE		(1 << 8)	/* Framing error */
#define	DR_PE		(1 << 9)	/* Parity error */
#define	DR_BE		(1 << 10)	/* Break error */
#define	DR_OE		(1 << 11)	/* Overrun error */

#define	UART_FR		0x06		/* Flag register */
#define	FR_TXFF		(1 << 5)	/* Transmit FIFO/reg full */
#define	FR_RXFF		(1 << 6)	/* Receive FIFO/reg full */
#define	FR_TXFE		(1 << 7)	/* Transmit FIFO/reg empty */

#define	UART_IBRD	0x09		/* Integer baud rate register */
#define	IBRD_BDIVINT	0xffff	/* Significant part of int. divisor value */

#define	UART_FBRD	0x0a		/* Fractional baud rate register */
#define	FBRD_BDIVFRAC	0x3f	/* Significant part of frac. divisor value */

#define	UART_LCR_H	0x0b		/* Line control register */
#define	LCR_H_WLEN8	(0x3 << 5)
#define	LCR_H_WLEN7	(0x2 << 5)
#define	LCR_H_WLEN6	(0x1 << 5)
#define	LCR_H_FEN	(1 << 4)	/* FIFO mode enable */
#define	LCR_H_STP2	(1 << 3)	/* 2 stop frames at the end */
#define	LCR_H_EPS	(1 << 2)	/* Even parity select */
#define	LCR_H_PEN	(1 << 1)	/* Parity enable */

#define	UART_CR		0x0c		/* Control register */
#define	CR_RXE		(1 << 9)	/* Receive enable */
#define	CR_TXE		(1 << 8)	/* Transmit enable */
#define	CR_UARTEN	(1 << 0)	/* UART enable */

#define	UART_IMSC	0x0e		/* Interrupt mask set/clear register */
#define	IMSC_MASK_ALL	0x7ff		/* Mask all interrupts */

#define	UART_RIS	0x0f		/* Raw interrupt status register */
#define	UART_RXREADY	(1 << 4)	/* RX buffer full */
#define	UART_TXEMPTY	(1 << 5)	/* TX buffer empty */
#define	RIS_RTIM	(1 << 6)	/* Receive timeout */
#define	RIS_FE		(1 << 7)	/* Framing error interrupt status */
#define	RIS_PE		(1 << 8)	/* Parity error interrupt status */
#define	RIS_BE		(1 << 9)	/* Break error interrupt status */
#define	RIS_OE		(1 << 10)	/* Overrun interrupt status */

#define	UART_MIS	0x10		/* Masked interrupt status register */
#define	UART_ICR	0x11		/* Interrupt clear register */

#define __uart_getreg(b, o) \
	bus_space_read_4(b, o)
#define __uart_setreg(b, o, v) \
	bus_space_write_4(b, o, v)

/* UART base address for RPI2 */
volatile register_t *uart_base = (register_t *)BMC2836_UART0;

static __inline uint32_t
bus_space_read_4(volatile uint32_t *base, u_long offset)
{
	return (*((volatile uint32_t *)(base + offset)));
}

static __inline void
bus_space_write_4(volatile uint32_t *base, u_long offset, uint32_t data)
{
	*((volatile uint32_t *)(base + offset)) = data;
}

int
uart_pl011_probe(void)
{

	return (0);
}

void
uart_pl011_param(int baudrate, int databits, int stopbits,
    int parity)
{
	uint32_t ctrl, line;
	uint32_t baud;

	/*
	 * Zero all settings to make sure
	 * UART is disabled and not configured
	 */
	ctrl = line = 0x0;
	__uart_setreg(uart_base, UART_CR, ctrl);

	/* As we know UART is disabled we may setup the line */
	switch (databits) {
	case 7:
		line |= LCR_H_WLEN7;
		break;
	case 6:
		line |= LCR_H_WLEN6;
		break;
	case 8:
	default:
		line |= LCR_H_WLEN8;
		break;
	}

	if (stopbits == 2)
		line |= LCR_H_STP2;
	else
		line &= ~LCR_H_STP2;

	if (parity)
		line |= LCR_H_PEN;
	else
		line &= ~LCR_H_PEN;

	/* Configure the rest */
	line &=  ~LCR_H_FEN;
	ctrl |= (CR_RXE | CR_TXE | CR_UARTEN);

/*
	if (bas->rclk != 0 && baudrate != 0) {
		baud = bas->rclk * 4 / baudrate;
		__uart_setreg(bas, UART_IBRD, ((uint32_t)(baud >> 6)) & IBRD_BDIVINT);
		__uart_setreg(bas, UART_FBRD, (uint32_t)(baud & 0x3F) & FBRD_BDIVFRAC);
	}
*/
	/* Add config. to line before reenabling UART */
	__uart_setreg(uart_base, UART_LCR_H, (__uart_getreg(uart_base, UART_LCR_H) &
	    ~0xff) | line);

	__uart_setreg(uart_base, UART_CR, ctrl);
}

void
uart_pl011_init(int baudrate, int databits, int stopbits,
    int parity)
{
	/* Mask all interrupts */
	__uart_setreg(uart_base, UART_IMSC, __uart_getreg(uart_base, UART_IMSC) &
	    ~IMSC_MASK_ALL);

	uart_pl011_param(baudrate, databits, stopbits, parity);

	kprintf("Initialising PrimeCell UART (PL011)\n");
}

void
uart_pl011_term(void)
{
}

void
uart_pl011_putc(int c, void *arg)
{

	/* Wait when TX FIFO full. Push character otherwise. */
	while (__uart_getreg(uart_base, UART_FR) & FR_TXFF)
		;
	__uart_setreg(uart_base, UART_DR, c & 0xff);
}

int
uart_pl011_rxready(void)
{

	return (__uart_getreg(uart_base, UART_FR) & FR_RXFF);
}

int
uart_pl011_getc()
{
	int c;

	while (!uart_pl011_rxready())
		;
	c = __uart_getreg(uart_base, UART_DR) & 0xff;

	return (c);
}