diff --git a/spiOverJtag/Makefile b/spiOverJtag/Makefile index 8070236984..e22a0416df 100644 --- a/spiOverJtag/Makefile +++ b/spiOverJtag/Makefile @@ -8,7 +8,7 @@ XILINX_PARTS := xc3s500evq100 \ xc7a35tcpg236 xc7a35tcsg324 xc7a35tftg256 xc7a35tfgg484 \ xc7a50tcsg324 xc7a50tfgg484 xc7a50tcpg236 xc7a75tfgg484 \ xc7a100tcsg324 xc7a100tfgg484 xc7a100tfgg676\ - xc7a200tsbg484 xc7a200tfbg484 \ + xc7a200tsbg484 xc7a200tfbg484 xc7a200tfbg676\ xc7s25csga225 xc7s25csga324 xc7s50csga324 \ xc7k70tfbg484 xc7k70tfbg676 \ xc7k160tffg676 \ diff --git a/spiOverJtag/build.py b/spiOverJtag/build.py index b0ea1ac82a..beccf8d2c0 100755 --- a/spiOverJtag/build.py +++ b/spiOverJtag/build.py @@ -98,6 +98,7 @@ "xc7a100tfgg676" : "xc7a_fgg676", "xc7a200tsbg484" : "xc7a_sbg484", "xc7a200tfbg484" : "xc7a_fbg484", + "xc7a200tfbg676" : "xc7a_fbg676", "xc7k70tfbg484" : "xc7k_fbg484", "xc7k70tfbg676" : "xc7k_fbg676", "xc7k160tffg676" : "xc7k_ffg676", diff --git a/spiOverJtag/constr_xc7a_fbg676.xdc b/spiOverJtag/constr_xc7a_fbg676.xdc new file mode 100644 index 0000000000..fe12330099 --- /dev/null +++ b/spiOverJtag/constr_xc7a_fbg676.xdc @@ -0,0 +1,10 @@ +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design] +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] + +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVTTL} [get_ports {csn}] +set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVTTL} [get_ports {sdi_dq0}] +set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVTTL} [get_ports {sdo_dq1}] +set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVTTL} [get_ports {wpn_dq2}] +set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVTTL} [get_ports {hldn_dq3}] diff --git a/spiOverJtag/spiOverJtag_xc7a200tfbg676.bit.gz b/spiOverJtag/spiOverJtag_xc7a200tfbg676.bit.gz new file mode 100644 index 0000000000..c8b381dc6a Binary files /dev/null and b/spiOverJtag/spiOverJtag_xc7a200tfbg676.bit.gz differ