From 9bb8d9cef2f215814c77350ceb00b97b6f12afb0 Mon Sep 17 00:00:00 2001 From: Jonas Schumacher Date: Tue, 23 Jul 2024 09:49:16 +0200 Subject: [PATCH 01/19] Limit decimattion to even values --- src/lib/rp-daq-lib.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/lib/rp-daq-lib.c b/src/lib/rp-daq-lib.c index 93a4b10e..ffa18329 100644 --- a/src/lib/rp-daq-lib.c +++ b/src/lib/rp-daq-lib.c @@ -540,6 +540,10 @@ int setArbitraryWaveform(float* values, int channel) { // Fast ADC int setDecimation(uint16_t decimation) { + if(!(decimation % 2 == 0)) { + return -1; + } + if(decimation < 8 || decimation > 8192) { return -1; } From f4f60e4145f2263bf7f522bee485590f26a352f4 Mon Sep 17 00:00:00 2001 From: Jonas Schumacher Date: Tue, 23 Jul 2024 09:49:59 +0200 Subject: [PATCH 02/19] Switch minor release image version --- src/fpga/bd/bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/fpga/bd/bd.tcl b/src/fpga/bd/bd.tcl index 765faf17..8e2e13fc 100644 --- a/src/fpga/bd/bd.tcl +++ b/src/fpga/bd/bd.tcl @@ -1576,7 +1576,7 @@ proc create_hier_cell_system_1 { parentCell nameHier } { # Create instance: image_version, and set properties set image_version [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 image_version ] set_property -dict [ list \ - CONFIG.CONST_VAL {7} \ + CONFIG.CONST_VAL {8} \ CONFIG.CONST_WIDTH {32} \ ] $image_version From 26f9094aad08142847b91295944f837d72f829f5 Mon Sep 17 00:00:00 2001 From: Jonas Schumacher Date: Tue, 23 Jul 2024 09:52:11 +0200 Subject: [PATCH 03/19] Bump client version number --- src/client/julia/Project.toml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/client/julia/Project.toml b/src/client/julia/Project.toml index 2ec00448..654c97b0 100644 --- a/src/client/julia/Project.toml +++ b/src/client/julia/Project.toml @@ -1,7 +1,7 @@ name = "RedPitayaDAQServer" uuid = "c544963a-496b-56d4-a5fe-f99a3f174c8f" authors = ["Tobias Knopp "] -version = "0.7.0" +version = "0.8.2" [deps] LinearAlgebra = "37e2e46d-f89d-539d-b4ee-838fcccc9c8e" From 503eea3f1082b2d29f2e6154c3e0d60411b0e5e9 Mon Sep 17 00:00:00 2001 From: Jonas Schumacher Date: Tue, 23 Jul 2024 09:56:24 +0200 Subject: [PATCH 04/19] Throw decimation error directly in client --- src/client/julia/src/ADC.jl | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/client/julia/src/ADC.jl b/src/client/julia/src/ADC.jl index 4ac7d1e6..36d48c38 100644 --- a/src/client/julia/src/ADC.jl +++ b/src/client/julia/src/ADC.jl @@ -97,6 +97,10 @@ julia> decimation(rp) ``` """ function decimation!(rp::RedPitaya, dec) + if dec < 8 || dec > 8192 || mod(dec, 2) != 0 + error("Decimation must be an even value between 8 and 8192. Supplied value is $dec.") + end + rp.decimation = Int64(dec) return query(rp, scpiCommand(decimation!, rp.decimation), scpiReturn(decimation!)) end From 0b77d176480a2cb7e7f391027aa116da4793a49f Mon Sep 17 00:00:00 2001 From: Jonas Schumacher Date: Tue, 23 Jul 2024 10:33:26 +0200 Subject: [PATCH 05/19] Add cic gain to calibration --- src/client/julia/src/Acquisition.jl | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/src/client/julia/src/Acquisition.jl b/src/client/julia/src/Acquisition.jl index 9cb9265c..b4de67c6 100644 --- a/src/client/julia/src/Acquisition.jl +++ b/src/client/julia/src/Acquisition.jl @@ -34,7 +34,7 @@ function readSamplesHeartbeat(rpu::Union{RedPitaya,RedPitayaCluster, RedPitayaCl # Current WP query as a heartbeat to avoid timeouts with "distant" wpStarts timeDifference = time() - heartBeatStartTime if timeDifference / (heartbeatTimeout*1000.0) >= timeOutCounter - @warn "Still waiting for write pointer (currently it is $(currentWP(rpu)). Are you sure there is no error and this loop is running infinitely?" + @warn "Still waiting for write pointer (currently it is $(currentWP(rpu))). Are you sure there is no error and this loop is running infinitely?" timeOutCounter += 1 end end @@ -53,6 +53,11 @@ function correctFilterDelay(wpStart::Int64, dec::Int64) return correctedWp end +# See https://support.xilinx.com/s/question/0D52E00006hpfy6SAA/cic-filter-gain?language=en_US +gain_cic(rp::RedPitaya) = gain_cic(round(Int, rp.decimation / 2), 1, 6) # M and N are fixed due to the FPGA image settings +gain_cic(rpc::RedPitayaCluster) = gain_cic(round(Int, master(rpc).decimation / 2), 1, 6) # M and N are fixed due to the FPGA image settings +gain_cic(rpcv::RedPitayaClusterView) = gain_cic(rpcv.rpc) +gain_cic(R::Int64, M::Int64, N::Int64) = ((R * M)^N) / 2^(ceil(N * log2(R * M))) """ readSamples(rpu::Union{RedPitaya,RedPitayaCluster, RedPitayaClusterView}, wpStart::Int64, numOfRequestedSamples::Int64; chunkSize::Int64 = 25000, rpInfo=nothing) @@ -220,8 +225,9 @@ function convertSamplesToFrames(rpu::Union{RedPitaya, RedPitayaCluster, RedPitay frames = convertSamplesToFrames(samples, numChan, numSampPerPeriod, numPeriods, numFrames, numBlockAverages, numPeriodsPerPatch) calibs = [x.calib for x in rpu] calib = hcat(calibs...) + gainCorr_ = 1 / gain_cic(rpu) for d = 1:size(frames, 2) - frames[:, d, :, :] .*= calib[1, d] + frames[:, d, :, :] .*= calib[1, d] * gainCorr_ frames[:, d, :, :] .+= calib[2, d] end return frames @@ -255,8 +261,9 @@ function convertSamplesToFrames!(rpu::Union{RedPitaya, RedPitayaCluster, RedPita convertSamplesToFrames!(samples, frames, numChan, numSampPerPeriod, numPeriods, numFrames, numTrueSampPerPeriod, numBlockAverages, numPeriodsPerPatch) calibs = [x.calib for x in rpu] calib = hcat(calibs...) + gainCorr_ = 1 / gain_cic(rpu) for d = 1:size(frames, 2) - frames[:, d, :, :] .*= calib[1, d] + frames[:, d, :, :] .*= calib[1, d] * gainCorr_ frames[:, d, :, :] .+= calib[2, d] end end @@ -331,8 +338,9 @@ function convertSamplesToPeriods!(rpu::Union{RedPitaya, RedPitayaCluster, RedPit convertSamplesToPeriods!(samples, periods, numChan, numSampPerPeriod, numPeriods, numBlockAverages) calibs = [x.calib for x in rpu] calib = hcat(calibs...) + gainCorr_ = 1 / gain_cic(rpu) for d = 1:size(periods, 2) - periods[:, d, :] .*= calib[1, d] + periods[:, d, :] .*= calib[1, d] * gainCorr_ periods[:, d, :] .+= calib[2, d] end return periods From e0b80459a5a2ab0d6e251b6d0a5872234f703d6a Mon Sep 17 00:00:00 2001 From: Jonas Schumacher Date: Tue, 23 Jul 2024 10:34:45 +0200 Subject: [PATCH 06/19] Minor styling --- src/client/julia/src/Cluster.jl | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/client/julia/src/Cluster.jl b/src/client/julia/src/Cluster.jl index 0c7a53e0..dca6c990 100644 --- a/src/client/julia/src/Cluster.jl +++ b/src/client/julia/src/Cluster.jl @@ -49,15 +49,16 @@ function RedPitayaCluster(hosts::Vector{String}, port::Int64=5025, dataPort::Int modes = fill(INTERNAL, length(rps)) modes[1] = EXTERNAL end - @sync for (i, rp) in enumerate(rps) - @async begin + + @sync for (i, rp) ∈ enumerate(rps) + @async begin triggerMode!(rp, modes[i]) triggerPropagation!(rp, true) end end triggerPropagation!(rps[end], false) - + return RedPitayaCluster(rps) end From 2fce5b9857b3fdbaa840e551af1b5fe94c8a05ed Mon Sep 17 00:00:00 2001 From: rp_local Date: Tue, 24 Sep 2024 12:38:04 +0000 Subject: [PATCH 07/19] Revert scpi-parser to v2.2 --- libs/scpi-parser | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libs/scpi-parser b/libs/scpi-parser index 361fe25c..a765b9ea 160000 --- a/libs/scpi-parser +++ b/libs/scpi-parser @@ -1 +1 @@ -Subproject commit 361fe25cb1fe4cacb4f7494944c5d4084eb07f61 +Subproject commit a765b9eadd3fe29de5f8d426549b69fc0a96793c From 58d04322534bc1902e23ddd0c92b4e6e0127a066 Mon Sep 17 00:00:00 2001 From: rp_local Date: Tue, 24 Sep 2024 15:42:18 +0000 Subject: [PATCH 08/19] Init Resync FPGA image --- src/fpga/bd/bd.tcl | 41 ++++++++++++++++++++++++++++++----- src/fpga/bd/waveform_gen.tcl | 26 ++++++++++++++++++---- src/fpga/hdl/sequence_slice.v | 2 ++ 3 files changed, 59 insertions(+), 10 deletions(-) diff --git a/src/fpga/bd/bd.tcl b/src/fpga/bd/bd.tcl index 8e2e13fc..206a1a32 100644 --- a/src/fpga/bd/bd.tcl +++ b/src/fpga/bd/bd.tcl @@ -796,6 +796,7 @@ proc create_hier_cell_signal_compose1 { parentCell nameHier } { create_bd_pin -dir O -from 0 -to 0 m_axis_data_tvalid_1 create_bd_pin -dir I -from 15 -to 0 offset create_bd_pin -dir O -from 1 -to 0 ramp_state_1 + create_bd_pin -dir I resync_dac create_bd_pin -dir I start_ramp_down # Create instance: signal_calib_0, and set properties @@ -899,10 +900,11 @@ proc create_hier_cell_signal_compose1 { parentCell nameHier } { connect_bd_net -net disable_dac_1 [get_bd_pins disable_dac] [get_bd_pins signal_composer_0/disable_dac] connect_bd_net -net enable_ramping_1 [get_bd_pins enable_ramping] [get_bd_pins signal_ramp_0/enableRamping] connect_bd_net -net offset_1 [get_bd_pins offset] [get_bd_pins signal_composer_0/seq] + connect_bd_net -net resync_dac_1 [get_bd_pins resync_dac] [get_bd_pins waveform_gen_0/resync] [get_bd_pins waveform_gen_1/resync] [get_bd_pins waveform_gen_2/resync] [get_bd_pins waveform_gen_3/resync] connect_bd_net -net rst_ps7_0_125M_peripheral_aresetn [get_bd_pins aresetn] [get_bd_pins signal_ramp_0/aresetn] [get_bd_pins waveform_awg1/aresetn] [get_bd_pins waveform_gen_0/aresetn] [get_bd_pins waveform_gen_1/aresetn] [get_bd_pins waveform_gen_2/aresetn] [get_bd_pins waveform_gen_3/aresetn] connect_bd_net -net signal_calib_0_signal_out [get_bd_pins S] [get_bd_pins signal_calib_0/signal_out] - connect_bd_net -net signal_cfg_slice_0_calib_limit_lower [get_bd_pins signal_calib_0/calib_limit_lower] [get_bd_pins signal_cfg_slice_0/calib_limit_lower] - connect_bd_net -net signal_cfg_slice_0_calib_limit_upper [get_bd_pins signal_calib_0/calib_limit_upper] [get_bd_pins signal_cfg_slice_0/calib_limit_upper] + connect_bd_net -net signal_cfg_slice_0_calib_limit_lower [get_bd_pins signal_cfg_slice_0/calib_limit_lower] + connect_bd_net -net signal_cfg_slice_0_calib_limit_upper [get_bd_pins signal_cfg_slice_0/calib_limit_upper] connect_bd_net -net signal_cfg_slice_0_calib_offset [get_bd_pins signal_calib_0/calib_offset] [get_bd_pins signal_cfg_slice_0/calib_offset] connect_bd_net -net signal_cfg_slice_0_calib_scale [get_bd_pins signal_calib_0/calib_scale] [get_bd_pins signal_cfg_slice_0/calib_scale] connect_bd_net -net signal_cfg_slice_0_comp_0_amp [get_bd_pins signal_cfg_slice_0/comp_0_amp] [get_bd_pins waveform_gen_0/amplitude] @@ -990,6 +992,7 @@ proc create_hier_cell_signal_compose { parentCell nameHier } { create_bd_pin -dir O -from 0 -to 0 m_axis_data_tvalid_1 create_bd_pin -dir I -from 15 -to 0 offset create_bd_pin -dir O -from 1 -to 0 ramp_state_0 + create_bd_pin -dir I resync_dac create_bd_pin -dir I start_ramp_down # Create instance: signal_calib_0, and set properties @@ -1094,9 +1097,10 @@ proc create_hier_cell_signal_compose { parentCell nameHier } { connect_bd_net -net disable_dac_1 [get_bd_pins disable_dac] [get_bd_pins signal_composer_0/disable_dac] connect_bd_net -net offset_1 [get_bd_pins offset] [get_bd_pins signal_composer_0/seq] connect_bd_net -net ramping_enable_1 [get_bd_pins enable_ramping] [get_bd_pins signal_ramp/enableRamping] + connect_bd_net -net resync_dac_1 [get_bd_pins resync_dac] [get_bd_pins waveform_gen_0/resync] [get_bd_pins waveform_gen_1/resync] [get_bd_pins waveform_gen_2/resync] [get_bd_pins waveform_gen_3/resync] connect_bd_net -net signal_calib_0_signal_out [get_bd_pins S] [get_bd_pins signal_calib_0/signal_out] - connect_bd_net -net signal_cfg_slice_0_calib_limit_lower [get_bd_pins signal_calib_0/calib_limit_lower] [get_bd_pins signal_cfg_slice_0/calib_limit_lower] - connect_bd_net -net signal_cfg_slice_0_calib_limit_upper [get_bd_pins signal_calib_0/calib_limit_upper] [get_bd_pins signal_cfg_slice_0/calib_limit_upper] + connect_bd_net -net signal_cfg_slice_0_calib_limit_lower [get_bd_pins signal_cfg_slice_0/calib_limit_lower] + connect_bd_net -net signal_cfg_slice_0_calib_limit_upper [get_bd_pins signal_cfg_slice_0/calib_limit_upper] connect_bd_net -net signal_cfg_slice_0_calib_offset [get_bd_pins signal_calib_0/calib_offset] [get_bd_pins signal_cfg_slice_0/calib_offset] connect_bd_net -net signal_cfg_slice_0_calib_scale [get_bd_pins signal_calib_0/calib_scale] [get_bd_pins signal_cfg_slice_0/calib_scale] connect_bd_net -net signal_cfg_slice_0_comp_0_amp [get_bd_pins signal_cfg_slice_0/comp_0_amp] [get_bd_pins waveform_gen_0/amplitude] @@ -1576,7 +1580,7 @@ proc create_hier_cell_system_1 { parentCell nameHier } { # Create instance: image_version, and set properties set image_version [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 image_version ] set_property -dict [ list \ - CONFIG.CONST_VAL {8} \ + CONFIG.CONST_VAL {9} \ CONFIG.CONST_WIDTH {32} \ ] $image_version @@ -2099,6 +2103,7 @@ proc create_hier_cell_sequencer { parentCell nameHier } { create_bd_pin -dir I -type rst keep_alive_aresetn create_bd_pin -dir O -from 31 -to 0 oa_dac create_bd_pin -dir O -from 31 -to 0 pdm_sts + create_bd_pin -dir O -from 1 -to 0 resync_dac create_bd_pin -dir O -from 1 -to 0 seq_ramp_down # Create instance: axi_bram_ctrl_0, and set properties @@ -2251,6 +2256,7 @@ proc create_hier_cell_sequencer { parentCell nameHier } { connect_bd_net -net sequence_slice_0_pdm_value_1 [get_bd_pins pdm_2/din] [get_bd_pins sequence_slice_0/pdm_value_1] connect_bd_net -net sequence_slice_0_pdm_value_2 [get_bd_pins pdm_3/din] [get_bd_pins sequence_slice_0/pdm_value_2] connect_bd_net -net sequence_slice_0_pdm_value_3 [get_bd_pins pdm_4/din] [get_bd_pins sequence_slice_0/pdm_value_3] + connect_bd_net -net sequence_slice_0_resync_dac [get_bd_pins resync_dac] [get_bd_pins sequence_slice_0/resync_dac] connect_bd_net -net util_vector_logic_7_Res [get_bd_pins dout] [get_bd_pins util_vector_logic_7/Res] connect_bd_net -net xlconcat_0_dout [get_bd_pins util_vector_logic_7/Op1] [get_bd_pins xlconcat_0/dout] connect_bd_net -net xlconcat_1_dout [get_bd_pins oa_dac] [get_bd_pins xlconcat_1/dout] @@ -2313,6 +2319,7 @@ proc create_hier_cell_fourier_synth_standard { parentCell nameHier } { create_bd_pin -dir I -from 31 -to 0 oa_dac create_bd_pin -dir O -from 1 -to 0 ramp_state_0 create_bd_pin -dir O -from 1 -to 0 ramp_state_1 + create_bd_pin -dir I -from 1 -to 0 resync_dac create_bd_pin -dir I -from 1 -to 0 seq_ramp_down create_bd_pin -dir I -from 1 -to 0 start_ramp_down create_bd_pin -dir O -from 31 -to 0 synth_tdata @@ -2405,6 +2412,23 @@ proc create_hier_cell_fourier_synth_standard { parentCell nameHier } { CONFIG.DOUT_WIDTH {1} \ ] $xlslice_5 + # Create instance: xlslice_6, and set properties + set xlslice_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_6 ] + set_property -dict [ list \ + CONFIG.DIN_FROM {0} \ + CONFIG.DIN_TO {0} \ + CONFIG.DIN_WIDTH {2} \ + ] $xlslice_6 + + # Create instance: xlslice_7, and set properties + set xlslice_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_7 ] + set_property -dict [ list \ + CONFIG.DIN_FROM {1} \ + CONFIG.DIN_TO {1} \ + CONFIG.DIN_WIDTH {2} \ + CONFIG.DOUT_WIDTH {1} \ + ] $xlslice_7 + # Create interface connections connect_bd_intf_net -intf_net awg_0_bram_1 [get_bd_intf_pins awg_0_bram] [get_bd_intf_pins signal_compose/awg_bram] connect_bd_intf_net -intf_net awg_1_bram_1 [get_bd_intf_pins awg_1_bram] [get_bd_intf_pins signal_compose1/awg_bram] @@ -2422,6 +2446,7 @@ proc create_hier_cell_fourier_synth_standard { parentCell nameHier } { connect_bd_net -net enable_ramping_slice_0_start_ramp_down_0 [get_bd_pins enable_ramping_slice_0/start_ramp_down_0] [get_bd_pins signal_compose/start_ramp_down] connect_bd_net -net enable_ramping_slice_0_start_ramp_down_1 [get_bd_pins enable_ramping_slice_0/start_ramp_down_1] [get_bd_pins signal_compose1/start_ramp_down] connect_bd_net -net oa_dac_1 [get_bd_pins oa_dac] [get_bd_pins xlslice_2/Din] [get_bd_pins xlslice_3/Din] + connect_bd_net -net resync_dac_1 [get_bd_pins resync_dac] [get_bd_pins xlslice_6/Din] [get_bd_pins xlslice_7/Din] connect_bd_net -net seq_ramp_down_1 [get_bd_pins seq_ramp_down] [get_bd_pins enable_ramping_slice_0/seq_ramp_down] connect_bd_net -net signal_compose1_S [get_bd_pins signal_compose1/S] [get_bd_pins xlconcat_2/In1] connect_bd_net -net signal_compose1_m_axis_data_tvalid_1 [get_bd_pins signal_compose1/m_axis_data_tvalid_1] [get_bd_pins util_vector_logic_1/Op2] @@ -2438,6 +2463,8 @@ proc create_hier_cell_fourier_synth_standard { parentCell nameHier } { connect_bd_net -net xlslice_3_Dout [get_bd_pins signal_compose/offset] [get_bd_pins xlslice_3/Dout] connect_bd_net -net xlslice_4_Dout [get_bd_pins signal_compose/disable_dac] [get_bd_pins xlslice_4/Dout] connect_bd_net -net xlslice_5_Dout [get_bd_pins signal_compose1/disable_dac] [get_bd_pins xlslice_5/Dout] + connect_bd_net -net xlslice_6_Dout [get_bd_pins signal_compose/resync_dac] [get_bd_pins xlslice_6/Dout] + connect_bd_net -net xlslice_7_Dout [get_bd_pins signal_compose1/resync_dac] [get_bd_pins xlslice_7/Dout] # Restore current instance current_bd_instance $oldCurInst @@ -3391,6 +3418,7 @@ proc create_root_design { parentCell } { connect_bd_net -net selectio_wiz_2_clk_out [get_bd_pins clk_wiz_1/clk_in1] [get_bd_pins selectio_wiz_2/clk_out] connect_bd_net -net selectio_wiz_2_data_in_to_device [get_bd_pins reset_manager_0/sata_trigger] [get_bd_pins selectio_wiz_2/data_in_to_device] connect_bd_net -net sequencer_enable_dac [get_bd_pins fourier_synth_standard/enable_dac] [get_bd_pins sequencer/enable_dac] + connect_bd_net -net sequencer_resync_dac [get_bd_pins fourier_synth_standard/resync_dac] [get_bd_pins sequencer/resync_dac] connect_bd_net -net sequencer_seq_ramp_down [get_bd_pins fourier_synth_standard/seq_ramp_down] [get_bd_pins sequencer/seq_ramp_down] connect_bd_net -net system_FCLK_RESET0_N [get_bd_pins system/FCLK_RESET0_N] [get_bd_pins util_vector_logic_1/Op1] connect_bd_net -net system_cfg_data [get_bd_pins fourier_synth_standard/cfg_data] [get_bd_pins system/dac_cfg] @@ -3434,7 +3462,6 @@ proc create_root_design { parentCell } { # Restore current instance current_bd_instance $oldCurInst - validate_bd_design save_bd_design } # End of create_root_design() @@ -3447,3 +3474,5 @@ proc create_root_design { parentCell } { create_root_design "" +common::send_gid_msg -ssname BD::TCL -id 2053 -severity "WARNING" "This Tcl script was generated from a block design that has not been validated. It is possible that design <$design_name> may result in errors during validation." + diff --git a/src/fpga/bd/waveform_gen.tcl b/src/fpga/bd/waveform_gen.tcl index f56db04a..ac9b77b2 100644 --- a/src/fpga/bd/waveform_gen.tcl +++ b/src/fpga/bd/waveform_gen.tcl @@ -128,6 +128,7 @@ xilinx.com:ip:dds_compiler:6.0\ xilinx.com:ip:mult_gen:12.0\ jbeuke:user:signal_generator:1.0\ xilinx.com:ip:xlconcat:2.1\ +xilinx.com:ip:xlconstant:1.1\ " set list_ips_missing "" @@ -203,12 +204,13 @@ proc create_root_design { parentCell } { set freq [ create_bd_port -dir I -from 47 -to 0 freq ] set m_axis_data_tvalid_1 [ create_bd_port -dir O m_axis_data_tvalid_1 ] set phase [ create_bd_port -dir I -from 47 -to 0 phase ] + set resync [ create_bd_port -dir I resync ] set wave [ create_bd_port -dir O -from 15 -to 0 -type data wave ] # Create instance: axis_variable_A_channel_1, and set properties set axis_variable_A_channel_1 [ create_bd_cell -type ip -vlnv pavel-demin:user:axis_variable:1.0 axis_variable_A_channel_1 ] set_property -dict [ list \ - CONFIG.AXIS_TDATA_WIDTH {96} \ + CONFIG.AXIS_TDATA_WIDTH {104} \ ] $axis_variable_A_channel_1 # Create instance: dds_compiler_A_channel_1, and set properties @@ -233,10 +235,11 @@ proc create_root_design { parentCell } { CONFIG.POFF1 {0} \ CONFIG.Parameter_Entry {System_Parameters} \ CONFIG.PartsPresent {Phase_Generator_and_SIN_COS_LUT} \ - CONFIG.Phase_Increment {Programmable} \ + CONFIG.Phase_Increment {Streaming} \ CONFIG.Phase_Offset_Angles1 {0} \ CONFIG.Phase_Width {48} \ - CONFIG.Phase_offset {Programmable} \ + CONFIG.Phase_offset {Streaming} \ + CONFIG.Resync {true} \ CONFIG.S_PHASE_Has_TUSER {Not_Required} \ CONFIG.Spurious_Free_Dynamic_Range {84} \ ] $dds_compiler_A_channel_1 @@ -261,15 +264,27 @@ proc create_root_design { parentCell } { CONFIG.CFG_DATA_WIDTH {48} \ ] $signal_generator_0 + # Create instance: xlconcat_0, and set properties + set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] + # Create instance: xlconcat_A_channel_1, and set properties set xlconcat_A_channel_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_A_channel_1 ] set_property -dict [ list \ CONFIG.IN0_WIDTH {48} \ CONFIG.IN1_WIDTH {48} \ + CONFIG.IN2_WIDTH {8} \ + CONFIG.NUM_PORTS {3} \ ] $xlconcat_A_channel_1 + # Create instance: xlconstant_0, and set properties + set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] + set_property -dict [ list \ + CONFIG.CONST_VAL {0} \ + CONFIG.CONST_WIDTH {7} \ + ] $xlconstant_0 + # Create interface connections - connect_bd_intf_net -intf_net axis_variable_A_channel_1_M_AXIS [get_bd_intf_pins axis_variable_A_channel_1/M_AXIS] [get_bd_intf_pins dds_compiler_A_channel_1/S_AXIS_CONFIG] + connect_bd_intf_net -intf_net axis_variable_A_channel_1_M_AXIS [get_bd_intf_pins axis_variable_A_channel_1/M_AXIS] [get_bd_intf_pins dds_compiler_A_channel_1/S_AXIS_PHASE] connect_bd_intf_net -intf_net dds_compiler_A_channel_1_M_AXIS_DATA [get_bd_intf_pins dds_compiler_A_channel_1/M_AXIS_DATA] [get_bd_intf_pins signal_generator_0/s_axis] connect_bd_intf_net -intf_net dds_compiler_A_channel_1_M_AXIS_PHASE [get_bd_intf_pins dds_compiler_A_channel_1/M_AXIS_PHASE] [get_bd_intf_pins signal_generator_0/s_axis_phase] @@ -280,10 +295,13 @@ proc create_root_design { parentCell } { connect_bd_net -net mult_gen_0_P [get_bd_ports wave] [get_bd_pins mult_gen_0/P] connect_bd_net -net phase_1 [get_bd_ports phase] [get_bd_pins xlconcat_A_channel_1/In1] connect_bd_net -net phase_A_channel_1_slice1_Dout [get_bd_ports cfg_data] [get_bd_pins signal_generator_0/cfg_data] + connect_bd_net -net resync_1 [get_bd_ports resync] [get_bd_pins xlconcat_0/In0] connect_bd_net -net rst_ps7_0_125M_peripheral_aresetn [get_bd_ports aresetn] [get_bd_pins axis_variable_A_channel_1/aresetn] [get_bd_pins dds_compiler_A_channel_1/aresetn] [get_bd_pins signal_generator_0/aresetn] connect_bd_net -net signal_generator_0_m_axis_tdata [get_bd_pins mult_gen_0/B] [get_bd_pins signal_generator_0/m_axis_tdata] connect_bd_net -net signal_generator_0_m_axis_tvalid [get_bd_ports m_axis_data_tvalid_1] [get_bd_pins signal_generator_0/m_axis_tvalid] + connect_bd_net -net xlconcat_0_dout [get_bd_pins xlconcat_0/dout] [get_bd_pins xlconcat_A_channel_1/In2] connect_bd_net -net xlconcat_A_channel_1_dout [get_bd_pins axis_variable_A_channel_1/cfg_data] [get_bd_pins xlconcat_A_channel_1/dout] + connect_bd_net -net xlconstant_0_dout [get_bd_pins xlconcat_0/In1] [get_bd_pins xlconstant_0/dout] # Create address segments diff --git a/src/fpga/hdl/sequence_slice.v b/src/fpga/hdl/sequence_slice.v index 7e3f15f8..67b36e07 100644 --- a/src/fpga/hdl/sequence_slice.v +++ b/src/fpga/hdl/sequence_slice.v @@ -11,6 +11,7 @@ module sequence_slice( output [10:0] pdm_value_2, output [10:0] pdm_value_3, output [1:0] enable_dac, + output [1:0] resync_dac, output [3:0] enable_pdm, output [1:0] enable_dac_ramp_down ); @@ -41,6 +42,7 @@ assign pdm_value_3[10:0] = seq_data_int[90:80]; // Flags assign enable_dac[1:0] = seq_data_int[97:96]; assign enable_pdm[3:0] = seq_data_int[101:98]; +assign resync_dac[1:0] = seq_data_init[31:30]; assign enable_dac_ramp_down[0] = seq_data_int[112]; assign enable_dac_ramp_down[1] = seq_data_int[113]; From ed6f10164c817b331dcb7f20d8c199797a8f32c1 Mon Sep 17 00:00:00 2001 From: rp_local Date: Tue, 24 Sep 2024 15:42:44 +0000 Subject: [PATCH 09/19] Init resync rp-lib --- src/lib/rp-daq-lib.c | 26 ++++++++++++++++++++++++++ src/lib/rp-daq-lib.h | 2 ++ 2 files changed, 28 insertions(+) diff --git a/src/lib/rp-daq-lib.c b/src/lib/rp-daq-lib.c index ffa18329..37f26941 100644 --- a/src/lib/rp-daq-lib.c +++ b/src/lib/rp-daq-lib.c @@ -637,6 +637,32 @@ int setEnableDAC(int8_t value, int channel, int index) { return 0; } +int setResyncDACAll(int8_t value, int channel) { + for(int i=0; i= 2) { + return -2; + } + + if (value < 0 || value >= 2) + return -1; + + int bitpos = 14 + channel; + // Reset bit is in the 2-th channel + int offset = 8 * index + 2; + // clear the bit + *((int16_t *)(pdm_cfg + offset)) &= ~(1u << bitpos); + // set the bit + *((int16_t *)(pdm_cfg + offset)) |= (value << bitpos); + //printf("%d reset pdm\n", *((int16_t *)(pdm_cfg + 2*(0+4*index)))); + return 0; +} + int setResetDAC(int8_t value, int index) { if (value < 0 || value >= 2) return -1; diff --git a/src/lib/rp-daq-lib.h b/src/lib/rp-daq-lib.h index 649a6dcc..9dc8378f 100644 --- a/src/lib/rp-daq-lib.h +++ b/src/lib/rp-daq-lib.h @@ -143,6 +143,8 @@ extern uint32_t getXADCValue(int); extern float getXADCValueVolt(int); extern int setEnableDACAll(int8_t, int); extern int setEnableDAC(int8_t, int, int); +extern int setResyncDACAll(int8_t, int); +extern int setResyncDAC(int8_t, int, int); //extern int setResetDAC(int8_t, int); extern int setRampDownDAC(int8_t, int, int); extern int getRampDownDAC(int, int); From d82017459db92e6396a7e4f9b5a278463a5276a4 Mon Sep 17 00:00:00 2001 From: rp_local Date: Tue, 24 Sep 2024 15:43:00 +0000 Subject: [PATCH 10/19] Init resync server --- src/server/control.c | 19 +++++++++++++++++++ src/server/daq_server_scpi.h | 2 ++ src/server/scpi_commands.c | 26 ++++++++++++++++++++++++++ 3 files changed, 47 insertions(+) diff --git a/src/server/control.c b/src/server/control.c index abca9c2a..0ec9b880 100644 --- a/src/server/control.c +++ b/src/server/control.c @@ -46,6 +46,7 @@ sequenceData_t * allocSequence() { seq->enableLUT = NULL; seq->rampUp = NULL; seq->rampDown = NULL; + seq->resyncLUT = NULL; return seq; } @@ -66,6 +67,10 @@ void freeSequence(sequenceData_t *seqData) { freeRamping(seqData->rampDown); seqData->rampDown = NULL; } + if (seqData->resyncLUT != NULL) { + free(seqData->resyncLUT); + seqData->resyncLUT = NULL; + } } rampingData_t * allocRamping() { @@ -120,6 +125,15 @@ bool getSequenceEnableValue(sequenceData_t *seqData, int seqStep, int channel) { return result; } +bool getSequenceResyncValue(sequenceData_t *seqData, int seqStep, int channel) { + bool result = false; + if (seqData->resyncLUT != NULL) { + int localStep = seqStep % seqData->numStepsPerRepetition; + result = seqData->resyncLUT[localStep + channel]; + } + return result; +} + float getRampingValue(rampingData_t *rampData, int rampStep, int channel) { int localStep = rampStep % rampData->numStepsPerRepetition; return rampData->LUT[localStep * numSlowDACChan + channel]; @@ -216,6 +230,7 @@ static void setLUTValuesFor(int futureStep, int channel, int currPDMIndex) { float val = 0.0; bool enable = true; bool rampDown = false; + bool resync = false; switch(interval) { case RAMPUP: @@ -224,6 +239,7 @@ static void setLUTValuesFor(int futureStep, int channel, int currPDMIndex) { case REGULAR: val = getSequenceValue(activeSequence, localStep, channel); enable = getSequenceEnableValue(activeSequence, localStep, channel); + resync = getSequenceResyncValue(activeSequence, localStep, channel); break; case RAMPDOWN: val = getRampingValue(activeSequence->rampDown, localStep, channel); @@ -240,6 +256,9 @@ static void setLUTValuesFor(int futureStep, int channel, int currPDMIndex) { printf("Could not set AO[%d] voltage.\n", channel); } setEnableDAC(enable, channel, currPDMIndex); + if (channel < 2) { + setResyncDAC(resync, channel, currPDMIndex); + } setRampDownDAC(rampDown, channel, currPDMIndex); } diff --git a/src/server/daq_server_scpi.h b/src/server/daq_server_scpi.h index 4fdf6f08..08e9adf2 100644 --- a/src/server/daq_server_scpi.h +++ b/src/server/daq_server_scpi.h @@ -107,6 +107,7 @@ typedef struct { int numStepsPerRepetition; // How many steps per repetition float* LUT; // LUT for value function pointer bool * enableLUT; + bool * resyncLUT; rampingData_t* rampUp; rampingData_t* rampDown; } sequenceData_t; @@ -131,6 +132,7 @@ extern sequenceInterval_t computeInterval(sequenceData_t *seqData, int step); extern bool isSequenceConfigurable(); extern float getSequenceValue(sequenceData_t *seqData, int seqStep, int channel); extern bool getSequenceEnableValue(sequenceData_t *seqData, int seqStep, int channel); +extern bool getSequenceResyncValue(sequenceData_t *seqData, int seqStep, int channel); extern float getRampingValue(rampingData_t *rampData, int rampStep, int channel); extern int getRampUpSteps(sequenceData_t *seqData); extern int getRampDownSteps(sequenceData_t *seqData); diff --git a/src/server/scpi_commands.c b/src/server/scpi_commands.c index 7629ba5b..6025297e 100644 --- a/src/server/scpi_commands.c +++ b/src/server/scpi_commands.c @@ -1056,6 +1056,31 @@ static scpi_result_t RP_DAC_SetEnableLUT(scpi_t * context) { } } +static scpi_result_t RP_DAC_SetResyncLUT(scpi_t * context) { + + readyConfigSequence(); + + if(configSeq->LUT != NULL && numSlowDACChan > 0 && isSequenceConfigurable()) { + if(configSeq->resyncLUT != NULL) { + free(configSeq->resyncLUT); + configSeq->resyncLUT = NULL; + } + + int numChan = numSlowDACChan > 2 ? 2 : numSlowDACChan; + printf("Allocating ressyncLUT\n"); + configSeq->resyncLUT = (bool *)calloc(numChan, configSeq->numStepsPerRepetition * sizeof(bool)); + + int n = readAll(newdatasockfd, configSeq->resyncLUT, numSlowDACChan * configSeq->numStepsPerRepetition * sizeof(bool)); + seqState = CONFIG; + if (n < 0) perror("ERROR reading from socket"); + return returnSCPIBool(context, true); + } + else { + return returnSCPIBool(context, false); + } + +} + static scpi_result_t RP_DAC_SetUpLUT(scpi_t * context) { readyConfigSequence(); @@ -1739,6 +1764,7 @@ const scpi_command_t scpi_commands[] = { {.pattern = "RP:DAC:SEQ:CHan?", .callback = RP_DAC_GetNumSlowDACChan,}, {.pattern = "RP:DAC:SEQ:LUT", .callback = RP_DAC_SetValueLUT,}, {.pattern = "RP:DAC:SEQ:LUT:ENaBle", .callback = RP_DAC_SetEnableLUT,}, + {.pattern = "RP:DAC:SEQ:LUT:ReSYNC", .callback = RP_DAC_SetResyncLUT,}, {.pattern = "RP:DAC:SEQ:LUT:UP", .callback = RP_DAC_SetUpLUT,}, {.pattern = "RP:DAC:SEQ:LUT:DOWN", .callback = RP_DAC_SetDownLUT,}, {.pattern = "RP:DAC:SEQ:SET", .callback = RP_DAC_SetSequence,}, From 268702b496b433daa4b314edcd1a86a3634859a9 Mon Sep 17 00:00:00 2001 From: rp_local Date: Tue, 24 Sep 2024 15:43:11 +0000 Subject: [PATCH 11/19] Init resync julia client --- src/client/julia/src/Sequence.jl | 52 ++++++++++++++++++++++++-------- 1 file changed, 40 insertions(+), 12 deletions(-) diff --git a/src/client/julia/src/Sequence.jl b/src/client/julia/src/Sequence.jl index db223879..25054eef 100644 --- a/src/client/julia/src/Sequence.jl +++ b/src/client/julia/src/Sequence.jl @@ -134,17 +134,19 @@ abstract type RampingSequence <: AbstractSequence end struct SimpleRampingSequence <: AbstractSequence lut::SequenceLUT enable::Union{Array{Bool}, Nothing} + resync::Union{Array{Bool}, Nothing} rampUp::SequenceLUT rampDown::SequenceLUT - function SimpleRampingSequencee(lut::SequenceLUT, up::SequenceLUT, down::SequenceLUT, enable::Union{Array{Bool}, Nothing}=nothing) + function SimpleRampingSequencee(lut::SequenceLUT, up::SequenceLUT, down::SequenceLUT, enable::Union{Array{Bool}, Nothing}=nothing, resync::Union{Array{Bool}, Nothing}=nothing) if !isnothing(enable) && size(values(lut)) != size(enable) throw(DimensionMismatch("Size of enable LUT does not match size of value LUT")) end - return new(SequenceLUT(lut, repetitions), enable, up, down) + return new(SequenceLUT(lut, repetitions), enable, resync, up, down) end end enableLUT(seq::SimpleRampingSequence) = seq.enable +resyncLUT(seq::SimpleRampingSequence) = seq.resync valueLUT(seq::SimpleRampingSequence) = seq.lut rampUpLUT(seq::SimpleRampingSequence) = nothing rampDownLUT(seq::SimpleRampingSequence) = nothing @@ -158,6 +160,7 @@ end struct HoldBorderRampingSequence <: RampingSequence lut::SequenceLUT enable::Union{Array{Bool}, Nothing} + resync::Union{Array{Bool}, Nothing} rampUp::SequenceLUT rampDown::SequenceLUT @@ -170,13 +173,13 @@ struct HoldBorderRampingSequence <: RampingSequence - `lut`,`repetitions`,`enable` are used the same as for a `SimpleSequence` - `rampingSteps` is the number of steps the first and last value of the given sequence are repeated before the sequence is started """ - function HoldBorderRampingSequence(lut::Array{Float32}, repetitions::Integer, rampingSteps::Integer, enable::Union{Array{Bool}, Nothing}=nothing) + function HoldBorderRampingSequence(lut::Array{Float32}, repetitions::Integer, rampingSteps::Integer, enable::Union{Array{Bool}, Nothing}=nothing, resync::Union{Array{Bool}, Nothing}=nothing) if !isnothing(enable) && size(lut) != size(enable) throw(DimensionMismatch("Size of enable LUT does not match size of value LUT")) end up = SequenceLUT(lut[:, 1], rampingSteps) down = SequenceLUT(lut[:, end], rampingSteps) - return new(SequenceLUT(lut, repetitions), enable, up, down) + return new(SequenceLUT(lut, repetitions), enable, resync, up, down) end end @@ -190,6 +193,7 @@ function HoldBorderRampingSequence(rp::RedPitaya, lut, repetitions, enable=nothi end enableLUT(seq::HoldBorderRampingSequence) = seq.enable +resyncLUT(seq::HoldBorderRampingSequence) = seq.resync valueLUT(seq::HoldBorderRampingSequence) = seq.lut rampUpLUT(seq::HoldBorderRampingSequence) = seq.rampUp rampDownLUT(seq::HoldBorderRampingSequence) = seq.rampDown @@ -197,14 +201,15 @@ rampDownLUT(seq::HoldBorderRampingSequence) = seq.rampDown struct ConstantRampingSequence <: RampingSequence lut::SequenceLUT enable::Union{Array{Bool}, Nothing} + resync::Union{Array{Bool}, Nothing} ramping::SequenceLUT - function ConstantRampingSequence(lut::Array{Float32}, repetitions::Integer, rampingValue::Float32, rampingSteps::Integer, enable::Union{Array{Bool}, Nothing}=nothing) + function ConstantRampingSequence(lut::Array{Float32}, repetitions::Integer, rampingValue::Float32, rampingSteps::Integer, enable::Union{Array{Bool}, Nothing}=nothing, resync::Union{Array{Bool}, Nothing}=nothing) if !isnothing(enable) && size(lut) != size(enable) throw(DimensionMismatch("Size of enable LUT does not match size of value LUT")) end rampingLut = SequenceLUT([rampingValue for i = 1:size(lut, 1)], rampingSteps) - return new(SequenceLUT(lut, repetitions), enable, rampingLut) + return new(SequenceLUT(lut, repetitions), enable, resync, rampingLut) end end ConstantRampingSequence(lut::Array{T}, repetitions::Integer, rampingValue::Real, rampingSteps::Integer, enable::Union{Array{Bool}, Nothing}=nothing) where T <: Real = ConstantRampingSequence(map(Float32, lut), repetitions, Float32(rampingValue), rampingSteps, enable) @@ -212,6 +217,7 @@ ConstantRampingSequence(lut::Vector{Float32}, repetitions::Integer, rampingValue ConstantRampingSequence(lut::Vector{T}, repetitions::Integer, rampingValue::Real, rampingSteps::Integer, enable::Union{Array{Bool}, Nothing}=nothing) where T <: Real = ConstantRampingSequence(reshape(lut, 1, :), repetitions, rampingValue, rampingSteps, enable) enableLUT(seq::ConstantRampingSequence) = seq.enable +resyncLUT(seq::ConstantRampingSequence) = seq.resync valueLUT(seq::ConstantRampingSequence) = seq.lut rampUpLUT(seq::ConstantRampingSequence) = seq.ramping rampDownLUT(seq::ConstantRampingSequence) = seq.ramping @@ -219,9 +225,10 @@ rampDownLUT(seq::ConstantRampingSequence) = seq.ramping struct StartUpSequence <: RampingSequence lut::SequenceLUT enable::Union{Array{Bool}, Nothing} + resync::Union{Array{Bool}, Nothing} rampUp::SequenceLUT rampDown::SequenceLUT - function StartUpSequence(lut::Array{Float32}, repetitions::Integer, rampingSteps::Integer, startUpSteps::Integer, enable::Union{Array{Bool}, Nothing}=nothing) + function StartUpSequence(lut::Array{Float32}, repetitions::Integer, rampingSteps::Integer, startUpSteps::Integer, enable::Union{Array{Bool}, Nothing}=nothing, resync::Union{Array{Bool}, Nothing}=nothing) if !isnothing(enable) && size(lut) != size(enable) throw(DimensionMismatch("Size of enable LUT does not match size of value LUT")) end @@ -239,7 +246,7 @@ struct StartUpSequence <: RampingSequence end up = SequenceLUT(upLut, 1) down = SequenceLUT(lut[:, end], rampingSteps) - return new(SequenceLUT(lut, repetitions), enable, up, down) + return new(SequenceLUT(lut, repetitions), enable, resync, up, down) end end StartUpSequence(lut::Array{T}, repetitions::Integer, rampingSteps::Integer, startUpSteps::Integer, enable::Union{Array{Bool}, Nothing}=nothing) where T <: Real = StartUpSequence(map(Float32, lut), repetitions, rampingSteps, startUpSteps, enable) @@ -247,6 +254,7 @@ StartUpSequence(lut::Array{T}, repetitions::Integer, rampingSteps::Integer, star StartUpSequence(lut::Vector{T}, repetitions::Integer, rampingSteps::Integer, startUpSteps::Integer, enable::Union{Array{Bool}, Nothing}=nothing) where T <: Real = StartUpSequence(reshape(lut, 1, :), repetitions, rampingSteps, startUpSteps, enable) enableLUT(seq::StartUpSequence) = seq.enable +resyncLUT(seq::StartUpSequence) = seq.resync valueLUT(seq::StartUpSequence) = seq.lut rampUpLUT(seq::StartUpSequence) = seq.rampUp rampDownLUT(seq::StartUpSequence) = seq.rampDown @@ -269,10 +277,11 @@ Transmit the client-side representation `seq` to the server and append it to the """ function sequence!(rp::RedPitaya, seq::AbstractSequence) result = true - result &= valueLUT!(rp, valueLUT(seq)) - result &= enableLUT!(rp, enableLUT(seq)) - result &= rampUpLUT!(rp, rampUpLUT(seq)) - result &= rampDownLUT!(rp, rampDownLUT(seq)) + result &= valueLUT!(rp, seq) + result &= enableLUT!(rp, seq) + result &= resyncLUT!(rp, seq) + result &= rampUpLUT!(rp, seq) + result &= rampDownLUT!(rp, seq) result &= setSequence!(rp) return result end @@ -283,11 +292,13 @@ function transmitLUT!(rp::RedPitaya, lut::Array{Float32}, cmd::String, repetitio return parse(Bool, receive(rp)) end +valueLUT!(rp::RedPitaya, lut::AbstractSequence) = valueLUT!(rp, valueLUT(lut)) function valueLUT!(rp::RedPitaya, lut::SequenceLUT) lutFloat32 = map(Float32, values(lut)) return transmitLUT!(rp, lutFloat32, "RP:DAC:SEQ:LUT", repetitions(lut)) end +rampUpLUT!(rp::RedPitaya, lut::AbstractSequence) = rampUpLUT!(rp, rampUpLUT(lut)) function rampUpLUT!(rp::RedPitaya, lut::SequenceLUT) lutFloat32 = map(Float32, values(lut)) return transmitLUT!(rp, lutFloat32, "RP:DAC:SEQ:LUT:UP", repetitions(lut)) @@ -298,6 +309,7 @@ function rampUpLUT!(rp::RedPitaya, lut::Nothing) return true end +rampDownLUT!(rp::RedPitaya, lut::AbstractSequence) = rampDownLUT!(rp, rampDownLUT(lut)) function rampDownLUT!(rp::RedPitaya, lut::SequenceLUT) lutFloat32 = map(Float32, values(lut)) return transmitLUT!(rp, lutFloat32, "RP:DAC:SEQ:LUT:DOWN", repetitions(lut)) @@ -308,6 +320,7 @@ function rampDownLUT!(rp::RedPitaya, lut::Nothing) return true end +enableLUT!(rp::RedPitaya, lut::AbstractSequence) = enableLUT!(rp, enableLUT(lut)) function enableLUT!(rp::RedPitaya, lut::Array) lutBool = map(Bool, lut) send(rp, string("RP:DAC:SEQ:LUT:ENaBle")) @@ -322,6 +335,21 @@ function enableLUT!(rp::RedPitaya, lut::Nothing) return true end +resyncLUT!(rp::RedPitaya, lut::AbstractSequence) = resyncLUT!(rp, resyncLUT(lut)) +function resyncLUT!(rp::RedPitaya, lut::Array) + lutBool = map(Bool, lut) + send(rp, string("RP:DAC:SEQ:LUT:ReSYNC")) + @debug "Writing resync DAC LUT" + write(rp.dataSocket, lutBool) + reply = receive(rp) + return parse(Bool, reply) +end + +function resyncLUT!(rp::RedPitaya, lut::Nothing) + # NOP + return true +end + function seqTiming(seq::AbstractSequence) up = 0 if !isnothing(rampUpLUT(seq)) From 7b8d04e42773a6f995a32144e5c5eead13bdb968 Mon Sep 17 00:00:00 2001 From: rp_local Date: Tue, 24 Sep 2024 15:54:25 +0000 Subject: [PATCH 12/19] Fix variable name in seq_data_int --- src/fpga/hdl/sequence_slice.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/fpga/hdl/sequence_slice.v b/src/fpga/hdl/sequence_slice.v index 67b36e07..ab2e91a5 100644 --- a/src/fpga/hdl/sequence_slice.v +++ b/src/fpga/hdl/sequence_slice.v @@ -42,7 +42,7 @@ assign pdm_value_3[10:0] = seq_data_int[90:80]; // Flags assign enable_dac[1:0] = seq_data_int[97:96]; assign enable_pdm[3:0] = seq_data_int[101:98]; -assign resync_dac[1:0] = seq_data_init[31:30]; +assign resync_dac[1:0] = seq_data_int[31:30]; assign enable_dac_ramp_down[0] = seq_data_int[112]; assign enable_dac_ramp_down[1] = seq_data_int[113]; From 0457f85cf1d6d720f3f73e57605fe49db0ce0ac0 Mon Sep 17 00:00:00 2001 From: rp_local Date: Wed, 25 Sep 2024 16:05:18 +0000 Subject: [PATCH 13/19] Init working resync based on aresetn --- src/client/julia/Project.toml | 2 +- src/client/julia/src/Sequence.jl | 12 +++++---- src/fpga/bd/bd.tcl | 9 +++++-- src/fpga/bd/waveform_gen.tcl | 45 ++++++++++++++++++-------------- src/lib/rp-daq-lib.c | 5 ++-- src/server/control.c | 6 +++-- 6 files changed, 47 insertions(+), 32 deletions(-) diff --git a/src/client/julia/Project.toml b/src/client/julia/Project.toml index 654c97b0..26393c4d 100644 --- a/src/client/julia/Project.toml +++ b/src/client/julia/Project.toml @@ -1,7 +1,7 @@ name = "RedPitayaDAQServer" uuid = "c544963a-496b-56d4-a5fe-f99a3f174c8f" authors = ["Tobias Knopp "] -version = "0.8.2" +version = "0.9.0" [deps] LinearAlgebra = "37e2e46d-f89d-539d-b4ee-838fcccc9c8e" diff --git a/src/client/julia/src/Sequence.jl b/src/client/julia/src/Sequence.jl index 25054eef..7b197ed5 100644 --- a/src/client/julia/src/Sequence.jl +++ b/src/client/julia/src/Sequence.jl @@ -103,7 +103,8 @@ Struct representing a sequence in which the server directly takes the values fro """ struct SimpleSequence <: AbstractSequence lut::SequenceLUT - enable::Union{Array{Bool}, Nothing} + enable::Union{Matrix{Bool}, Nothing} + resync::Union{Matrix{Bool}, Nothing} """ SimpleSequence(lut, repetitions, enable=nothing) @@ -114,17 +115,18 @@ struct SimpleSequence <: AbstractSequence - `repetitions::Int32`: the number of times the sequence should be repeated - `emable::Union{Array{Bool}, Nothing}`: matrix containing enable flags """ - function SimpleSequence(lut::Array{Float32}, repetitions::Integer, enable::Union{Array{Bool}, Nothing}=nothing) + function SimpleSequence(lut::Matrix{Float32}, repetitions::Integer, enable::Union{Matrix{Bool}, Nothing}=nothing, resync::Union{Matrix{Bool}, Nothing} = nothing) if !isnothing(enable) && size(lut) != size(enable) throw(DimensionMismatch("Size of enable LUT does not match size of value LUT")) end - return new(SequenceLUT(lut, repetitions), enable) + return new(SequenceLUT(lut, repetitions), enable, resync) end end -SimpleSequence(lut::Array{T}, repetitions::Integer, enable::Union{Array{Bool}, Nothing}=nothing) where T <: Real = SimpleSequence(map(Float32, lut), repetitions, enable) -SimpleSequence(lut::Vector{T}, repetitions::Integer, enable::Union{Array{Bool}, Nothing}=nothing) where T <: Real = SimpleSequence(reshape(lut, 1, :), repetitions, enable) +SimpleSequence(lut::Array{T}, repetitions::Integer, args...) where T <: Real = SimpleSequence(map(Float32, lut), repetitions, args...) +SimpleSequence(lut::Vector{T}, repetitions::Integer, args...) where T <: Real = SimpleSequence(reshape(lut, 1, :), repetitions, args...) enableLUT(seq::SimpleSequence) = seq.enable +resyncLUT(seq::SimpleSequence) = seq.resync valueLUT(seq::SimpleSequence) = seq.lut rampUpLUT(seq::SimpleSequence) = nothing rampDownLUT(seq::SimpleSequence) = nothing diff --git a/src/fpga/bd/bd.tcl b/src/fpga/bd/bd.tcl index 206a1a32..e9ae2bab 100644 --- a/src/fpga/bd/bd.tcl +++ b/src/fpga/bd/bd.tcl @@ -402,6 +402,9 @@ proc create_hier_cell_waveform_awg1 { parentCell nameHier } { # Create instance: xlconcat_0, and set properties set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] + set_property -dict [ list \ + CONFIG.IN0_WIDTH {48} \ + ] $xlconcat_0 # Create instance: xlconstant_0, and set properties set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] @@ -572,6 +575,9 @@ proc create_hier_cell_waveform_awg { parentCell nameHier } { # Create instance: xlconcat_0, and set properties set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] + set_property -dict [ list \ + CONFIG.IN0_WIDTH {48} \ + ] $xlconcat_0 # Create instance: xlconstant_0, and set properties set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] @@ -3462,6 +3468,7 @@ proc create_root_design { parentCell } { # Restore current instance current_bd_instance $oldCurInst + validate_bd_design save_bd_design } # End of create_root_design() @@ -3474,5 +3481,3 @@ proc create_root_design { parentCell } { create_root_design "" -common::send_gid_msg -ssname BD::TCL -id 2053 -severity "WARNING" "This Tcl script was generated from a block design that has not been validated. It is possible that design <$design_name> may result in errors during validation." - diff --git a/src/fpga/bd/waveform_gen.tcl b/src/fpga/bd/waveform_gen.tcl index ac9b77b2..8b6070f9 100644 --- a/src/fpga/bd/waveform_gen.tcl +++ b/src/fpga/bd/waveform_gen.tcl @@ -127,8 +127,8 @@ pavel-demin:user:axis_variable:1.0\ xilinx.com:ip:dds_compiler:6.0\ xilinx.com:ip:mult_gen:12.0\ jbeuke:user:signal_generator:1.0\ +xilinx.com:ip:util_vector_logic:2.0\ xilinx.com:ip:xlconcat:2.1\ -xilinx.com:ip:xlconstant:1.1\ " set list_ips_missing "" @@ -210,7 +210,7 @@ proc create_root_design { parentCell } { # Create instance: axis_variable_A_channel_1, and set properties set axis_variable_A_channel_1 [ create_bd_cell -type ip -vlnv pavel-demin:user:axis_variable:1.0 axis_variable_A_channel_1 ] set_property -dict [ list \ - CONFIG.AXIS_TDATA_WIDTH {104} \ + CONFIG.AXIS_TDATA_WIDTH {96} \ ] $axis_variable_A_channel_1 # Create instance: dds_compiler_A_channel_1, and set properties @@ -220,6 +220,7 @@ proc create_root_design { parentCell } { CONFIG.DATA_Has_TLAST {Not_Required} \ CONFIG.DDS_Clock_Rate {125} \ CONFIG.Frequency_Resolution {4.440893e-7} \ + CONFIG.Has_ACLKEN {false} \ CONFIG.Has_ARESETn {true} \ CONFIG.Has_Phase_Out {true} \ CONFIG.Has_TREADY {false} \ @@ -235,11 +236,11 @@ proc create_root_design { parentCell } { CONFIG.POFF1 {0} \ CONFIG.Parameter_Entry {System_Parameters} \ CONFIG.PartsPresent {Phase_Generator_and_SIN_COS_LUT} \ - CONFIG.Phase_Increment {Streaming} \ + CONFIG.Phase_Increment {Programmable} \ CONFIG.Phase_Offset_Angles1 {0} \ CONFIG.Phase_Width {48} \ - CONFIG.Phase_offset {Streaming} \ - CONFIG.Resync {true} \ + CONFIG.Phase_offset {Programmable} \ + CONFIG.Resync {false} \ CONFIG.S_PHASE_Has_TUSER {Not_Required} \ CONFIG.Spurious_Free_Dynamic_Range {84} \ ] $dds_compiler_A_channel_1 @@ -264,8 +265,19 @@ proc create_root_design { parentCell } { CONFIG.CFG_DATA_WIDTH {48} \ ] $signal_generator_0 - # Create instance: xlconcat_0, and set properties - set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] + # Create instance: util_vector_logic_0, and set properties + set util_vector_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_0 ] + set_property -dict [ list \ + CONFIG.C_OPERATION {not} \ + CONFIG.C_SIZE {1} \ + CONFIG.LOGO_FILE {data/sym_notgate.png} \ + ] $util_vector_logic_0 + + # Create instance: util_vector_logic_1, and set properties + set util_vector_logic_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_1 ] + set_property -dict [ list \ + CONFIG.C_SIZE {1} \ + ] $util_vector_logic_1 # Create instance: xlconcat_A_channel_1, and set properties set xlconcat_A_channel_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_A_channel_1 ] @@ -273,35 +285,28 @@ proc create_root_design { parentCell } { CONFIG.IN0_WIDTH {48} \ CONFIG.IN1_WIDTH {48} \ CONFIG.IN2_WIDTH {8} \ - CONFIG.NUM_PORTS {3} \ + CONFIG.NUM_PORTS {2} \ ] $xlconcat_A_channel_1 - # Create instance: xlconstant_0, and set properties - set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {0} \ - CONFIG.CONST_WIDTH {7} \ - ] $xlconstant_0 - # Create interface connections - connect_bd_intf_net -intf_net axis_variable_A_channel_1_M_AXIS [get_bd_intf_pins axis_variable_A_channel_1/M_AXIS] [get_bd_intf_pins dds_compiler_A_channel_1/S_AXIS_PHASE] + connect_bd_intf_net -intf_net axis_variable_A_channel_1_M_AXIS [get_bd_intf_pins axis_variable_A_channel_1/M_AXIS] [get_bd_intf_pins dds_compiler_A_channel_1/S_AXIS_CONFIG] connect_bd_intf_net -intf_net dds_compiler_A_channel_1_M_AXIS_DATA [get_bd_intf_pins dds_compiler_A_channel_1/M_AXIS_DATA] [get_bd_intf_pins signal_generator_0/s_axis] connect_bd_intf_net -intf_net dds_compiler_A_channel_1_M_AXIS_PHASE [get_bd_intf_pins dds_compiler_A_channel_1/M_AXIS_PHASE] [get_bd_intf_pins signal_generator_0/s_axis_phase] # Create port connections connect_bd_net -net amplitude_A_channel_1_slice1_Dout [get_bd_ports amplitude] [get_bd_pins mult_gen_0/A] + connect_bd_net -net aresetn_1 [get_bd_ports aresetn] [get_bd_pins axis_variable_A_channel_1/aresetn] [get_bd_pins signal_generator_0/aresetn] [get_bd_pins util_vector_logic_1/Op2] connect_bd_net -net clk_wiz_0_clk_internal [get_bd_ports aclk] [get_bd_pins axis_variable_A_channel_1/aclk] [get_bd_pins dds_compiler_A_channel_1/aclk] [get_bd_pins mult_gen_0/CLK] [get_bd_pins signal_generator_0/clk] connect_bd_net -net freq_1 [get_bd_ports freq] [get_bd_pins xlconcat_A_channel_1/In0] connect_bd_net -net mult_gen_0_P [get_bd_ports wave] [get_bd_pins mult_gen_0/P] connect_bd_net -net phase_1 [get_bd_ports phase] [get_bd_pins xlconcat_A_channel_1/In1] connect_bd_net -net phase_A_channel_1_slice1_Dout [get_bd_ports cfg_data] [get_bd_pins signal_generator_0/cfg_data] - connect_bd_net -net resync_1 [get_bd_ports resync] [get_bd_pins xlconcat_0/In0] - connect_bd_net -net rst_ps7_0_125M_peripheral_aresetn [get_bd_ports aresetn] [get_bd_pins axis_variable_A_channel_1/aresetn] [get_bd_pins dds_compiler_A_channel_1/aresetn] [get_bd_pins signal_generator_0/aresetn] + connect_bd_net -net resync_1 [get_bd_ports resync] [get_bd_pins util_vector_logic_0/Op1] connect_bd_net -net signal_generator_0_m_axis_tdata [get_bd_pins mult_gen_0/B] [get_bd_pins signal_generator_0/m_axis_tdata] connect_bd_net -net signal_generator_0_m_axis_tvalid [get_bd_ports m_axis_data_tvalid_1] [get_bd_pins signal_generator_0/m_axis_tvalid] - connect_bd_net -net xlconcat_0_dout [get_bd_pins xlconcat_0/dout] [get_bd_pins xlconcat_A_channel_1/In2] + connect_bd_net -net util_vector_logic_0_Res [get_bd_pins util_vector_logic_0/Res] [get_bd_pins util_vector_logic_1/Op1] + connect_bd_net -net util_vector_logic_1_Res [get_bd_pins dds_compiler_A_channel_1/aresetn] [get_bd_pins util_vector_logic_1/Res] connect_bd_net -net xlconcat_A_channel_1_dout [get_bd_pins axis_variable_A_channel_1/cfg_data] [get_bd_pins xlconcat_A_channel_1/dout] - connect_bd_net -net xlconstant_0_dout [get_bd_pins xlconcat_0/In1] [get_bd_pins xlconstant_0/dout] # Create address segments diff --git a/src/lib/rp-daq-lib.c b/src/lib/rp-daq-lib.c index 37f26941..0d555380 100644 --- a/src/lib/rp-daq-lib.c +++ b/src/lib/rp-daq-lib.c @@ -653,8 +653,8 @@ int setResyncDAC(int8_t value, int channel, int index) { return -1; int bitpos = 14 + channel; - // Reset bit is in the 2-th channel - int offset = 8 * index + 2; + // Reset bits are in the 2nd channel -> bitpos 31:30 + int offset = 8 * index + 1; // clear the bit *((int16_t *)(pdm_cfg + offset)) &= ~(1u << bitpos); // set the bit @@ -1306,6 +1306,7 @@ void stopTx() { for(int d=0; d<5; d++) { setPDMAllValuesVolt(0.0, d); setEnableDACAll(1,d); + setResyncDACAll(0,d); } } diff --git a/src/server/control.c b/src/server/control.c index 0ec9b880..64c7abc8 100644 --- a/src/server/control.c +++ b/src/server/control.c @@ -102,9 +102,11 @@ void clearSequence() { setPDMAllValuesVolt(0.0, 2); setPDMAllValuesVolt(0.0, 3); - for(int d=0; d<4; d++) { + for(int d=0; d<6; d++) { setEnableDACAll(1,d); - } + setResyncDACAll(0,d); + } + } bool isSequenceConfigurable() { From 45d19c13ddb9268c8ae66b48e25c8cc1342b8b67 Mon Sep 17 00:00:00 2001 From: Tobias Knopp Date: Thu, 26 Sep 2024 07:17:33 +0200 Subject: [PATCH 14/19] fix multi-channel resync issues --- src/server/control.c | 3 ++- src/server/scpi_commands.c | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/server/control.c b/src/server/control.c index 64c7abc8..bfd08aed 100644 --- a/src/server/control.c +++ b/src/server/control.c @@ -129,9 +129,10 @@ bool getSequenceEnableValue(sequenceData_t *seqData, int seqStep, int channel) { bool getSequenceResyncValue(sequenceData_t *seqData, int seqStep, int channel) { bool result = false; + int numChan = numSlowDACChan > 2 ? 2 : numSlowDACChan; if (seqData->resyncLUT != NULL) { int localStep = seqStep % seqData->numStepsPerRepetition; - result = seqData->resyncLUT[localStep + channel]; + result = seqData->resyncLUT[localStep * numChan + channel]; } return result; } diff --git a/src/server/scpi_commands.c b/src/server/scpi_commands.c index 6025297e..b7308745 100644 --- a/src/server/scpi_commands.c +++ b/src/server/scpi_commands.c @@ -1070,7 +1070,7 @@ static scpi_result_t RP_DAC_SetResyncLUT(scpi_t * context) { printf("Allocating ressyncLUT\n"); configSeq->resyncLUT = (bool *)calloc(numChan, configSeq->numStepsPerRepetition * sizeof(bool)); - int n = readAll(newdatasockfd, configSeq->resyncLUT, numSlowDACChan * configSeq->numStepsPerRepetition * sizeof(bool)); + int n = readAll(newdatasockfd, configSeq->resyncLUT, numChan * configSeq->numStepsPerRepetition * sizeof(bool)); seqState = CONFIG; if (n < 0) perror("ERROR reading from socket"); return returnSCPIBool(context, true); From cdb0ae9e8a21654a4c6fc5f7cbe971daa36779f1 Mon Sep 17 00:00:00 2001 From: rp_local Date: Thu, 26 Sep 2024 09:23:01 +0000 Subject: [PATCH 15/19] Move resync flag to bit 14 of each DAC channel --- src/fpga/hdl/sequence_slice.v | 5 +++-- src/lib/rp-daq-lib.c | 6 +++--- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/src/fpga/hdl/sequence_slice.v b/src/fpga/hdl/sequence_slice.v index ab2e91a5..3ffc5840 100644 --- a/src/fpga/hdl/sequence_slice.v +++ b/src/fpga/hdl/sequence_slice.v @@ -42,8 +42,9 @@ assign pdm_value_3[10:0] = seq_data_int[90:80]; // Flags assign enable_dac[1:0] = seq_data_int[97:96]; assign enable_pdm[3:0] = seq_data_int[101:98]; -assign resync_dac[1:0] = seq_data_int[31:30]; +assign resync_dac[0] = seq_data_int[14]; +assign resync_dac[1] = seq_data_int[30]; assign enable_dac_ramp_down[0] = seq_data_int[112]; assign enable_dac_ramp_down[1] = seq_data_int[113]; -endmodule +endmodule \ No newline at end of file diff --git a/src/lib/rp-daq-lib.c b/src/lib/rp-daq-lib.c index 0d555380..fe6eff16 100644 --- a/src/lib/rp-daq-lib.c +++ b/src/lib/rp-daq-lib.c @@ -652,9 +652,9 @@ int setResyncDAC(int8_t value, int channel, int index) { if (value < 0 || value >= 2) return -1; - int bitpos = 14 + channel; - // Reset bits are in the 2nd channel -> bitpos 31:30 - int offset = 8 * index + 1; + int bitpos = 14; + // Reset bits are in the 14th bit of the respective DAC channel -> 14 and 30 + int offset = 8 * index + channel; // clear the bit *((int16_t *)(pdm_cfg + offset)) &= ~(1u << bitpos); // set the bit From 823c37e6624f212d832b1184ef0433d5d783bf33 Mon Sep 17 00:00:00 2001 From: rp_local Date: Thu, 26 Sep 2024 09:23:34 +0000 Subject: [PATCH 16/19] Restrict getSequenceResyncValue to DAC channel --- src/server/control.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/server/control.c b/src/server/control.c index bfd08aed..3e662510 100644 --- a/src/server/control.c +++ b/src/server/control.c @@ -129,8 +129,8 @@ bool getSequenceEnableValue(sequenceData_t *seqData, int seqStep, int channel) { bool getSequenceResyncValue(sequenceData_t *seqData, int seqStep, int channel) { bool result = false; - int numChan = numSlowDACChan > 2 ? 2 : numSlowDACChan; - if (seqData->resyncLUT != NULL) { + int numChan = numSlowDACChan > 2 ? 2 : numSlowDACChan; + if (seqData->resyncLUT != NULL && channel < numChan) { int localStep = seqStep % seqData->numStepsPerRepetition; result = seqData->resyncLUT[localStep * numChan + channel]; } @@ -215,6 +215,7 @@ static void setLUTValuesFor(int futureStep, int channel, int currPDMIndex) { if (activeSequence == NULL) { setPDMValueVolt(0.0, channel, currPDMIndex); setEnableDAC(false, channel, currPDMIndex); + setResyncDAC(false, channel, currPDMIndex); setRampDownDAC(false, channel, currPDMIndex); return; } From b79123c0d24e173321b1cab3ca144b0c3ff86d51 Mon Sep 17 00:00:00 2001 From: rp_local Date: Fri, 29 Nov 2024 13:07:08 +0000 Subject: [PATCH 17/19] Init test of step counting with writepointer lowest bit --- src/fpga/hdl/sequence_stepper.v | 41 ++++++++++++++++++++------------- 1 file changed, 25 insertions(+), 16 deletions(-) diff --git a/src/fpga/hdl/sequence_stepper.v b/src/fpga/hdl/sequence_stepper.v index 9a28dd9a..25754421 100644 --- a/src/fpga/hdl/sequence_stepper.v +++ b/src/fpga/hdl/sequence_stepper.v @@ -1,36 +1,45 @@ `timescale 1ns / 1ps module sequence_stepper( - input [63:0] writepointer, + input [63:0] writePointer, input [31:0] stepSize, input clk, input aresetn, - output [31:0] step_counter + output [31:0] seq_counter ); -reg [63:0] end_of_step, next_end_of_step; -reg [31:0] step_counter_reg, step_counter_next; +reg [31:0] stepSize_int; +reg [31:0] seq_counter_state; +reg [31:0] sample_counter; +reg wp_prev, wp_next; always @(posedge clk) begin + stepSize_int <= stepSize; + wp_next <= writePointer[0]; if (~aresetn) begin - step_counter_reg <= 0; - step_counter_next <= 0; - end_of_step <= stepSize; - next_end_of_step <= stepSize; + seq_counter_state <= 0; + sample_counter <= stepSize_int; + wp_prev <= 0; end else begin - step_counter_reg <= step_counter_next; - end_of_step <= next_end_of_step; - if (end_of_step < writepointer) begin - next_end_of_step <= end_of_step + stepSize; - step_counter_next <= step_counter_reg + 1; + wp_prev <= wp_next; + if (wp_prev != wp_next) begin + + if (sample_counter == 0) begin + sample_counter <= stepSize_int; + seq_counter_state <= seq_counter_state + 1; + end else begin + sample_counter <= sample_counter - 1; + seq_counter_state <= seq_counter_state; + end + end else begin - next_end_of_step <= next_end_of_step; - step_counter_next <= step_counter_reg; + sample_counter <= sample_counter; + seq_counter_state <= seq_counter_state; end end end -assign step_counter = step_counter_reg; +assign seq_counter = seq_counter_state; endmodule From 3bada952605943f4a7dfeb63b8732ed54d7c246a Mon Sep 17 00:00:00 2001 From: Tobias Knopp Date: Sun, 1 Dec 2024 14:48:28 +0100 Subject: [PATCH 18/19] add sequenceIssue.jl --- src/examples/julia/sequenceIssue.jl | 60 +++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 src/examples/julia/sequenceIssue.jl diff --git a/src/examples/julia/sequenceIssue.jl b/src/examples/julia/sequenceIssue.jl new file mode 100644 index 00000000..5d387cb8 --- /dev/null +++ b/src/examples/julia/sequenceIssue.jl @@ -0,0 +1,60 @@ +using RedPitayaDAQServer +using CairoMakie + +# obtain the URL of the RedPitaya +include("config.jl") + +rp = RedPitaya(URLs[1]) +serverMode!(rp, CONFIGURATION) + + +dec = 128 +base_frequency = 125000000 + +samples_per_step = 40 #30*16 +steps_per_frame = 4 +numSamples = steps_per_frame * samples_per_step + +decimation!(rp, dec) +samplesPerPeriod!(rp, 1) +periodsPerFrame!(rp, numSamples) +samplesPerStep!(rp, samples_per_step) +triggerMode!(rp, INTERNAL) + + +amplitudeDAC!(rp, 1, 1, 0.0) +amplitudeDAC!(rp, 2, 1, 0.0 ) + +clearSequence!(rp) + +# Climbing offset for first channel, fixed offset for second channel +seqChan!(rp, 6) +lutB = collect(ones(steps_per_frame)) +lutB[1:2:end] .= 0.0 +lut = collect(cat(-lutB,-lutB*0.3, 0*lutB,0*lutB,0*lutB,0*lutB,dims=2)') +#lut = collect(cat(-lutB,dims=2)')#,lutB,lutB,lutB,lutB,dims=2)') + +lutEnableDACA = ones(Bool, steps_per_frame) + +#enableLUT = collect( cat(lutEnableDACA,lutEnableDACA,lutEnableDACA,lutEnableDACA,lutEnableDACA,lutEnableDACA,dims=2)' ) +enableLUT = collect( cat(lutEnableDACA,lutEnableDACA,lutEnableDACA,lutEnableDACA,lutEnableDACA,lutEnableDACA,dims=2)' ) +#enableLUT = collect( cat(lutEnableDACA,dims=2)') #,lutEnableDACA,lutEnableDACA,lutEnableDACA,lutEnableDACA,dims=2)' ) + +seq = SimpleSequence(lut, 300, enableLUT) +sequence!(rp, seq) + +serverMode!(rp, ACQUISITION) +masterTrigger!(rp, true) + +uCurrentPeriod = readFrames(rp, 1, 3) + +masterTrigger!(rp, false) +serverMode!(rp, CONFIGURATION) + +plot = lines(vec(uCurrentPeriod[:,1,:,1]), label = "Rx1") +lines!(plot.axis, vec(uCurrentPeriod[:,2,:,1]), label = "Rx2") +lines!(plot.axis, vec(uCurrentPeriod[:,1,:,2]), label = "Rx1_2") +lines!(plot.axis, vec(uCurrentPeriod[:,2,:,2]), label = "Rx2_2") +axislegend(plot.axis) +save(joinpath(@__DIR__(), "images", "sequenceIssue.png"), plot) +plot \ No newline at end of file From f1130c45fc93992b4046f941dd88dee32ee45656 Mon Sep 17 00:00:00 2001 From: Tobias Knopp Date: Sun, 1 Dec 2024 17:38:51 +0100 Subject: [PATCH 19/19] fix sequence stepper issue --- src/fpga/bd/bd.tcl | 9 +++---- src/fpga/hdl/sequence_stepper.v | 42 +++++++++++++-------------------- src/lib/rp-daq-lib.c | 4 ++-- 3 files changed, 24 insertions(+), 31 deletions(-) diff --git a/src/fpga/bd/bd.tcl b/src/fpga/bd/bd.tcl index e9ae2bab..494b4cfb 100644 --- a/src/fpga/bd/bd.tcl +++ b/src/fpga/bd/bd.tcl @@ -2099,7 +2099,6 @@ proc create_hier_cell_sequencer { parentCell nameHier } { # Create pins create_bd_pin -dir I -type clk aclk - create_bd_pin -dir I -from 63 -to 0 adc_sts create_bd_pin -dir I -type rst aresetn create_bd_pin -dir I bram_aresetn create_bd_pin -dir I -from 31 -to 0 cfg_data @@ -2220,6 +2219,9 @@ proc create_hier_cell_sequencer { parentCell nameHier } { # Create instance: xlconstant_0, and set properties set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] + # Create instance: xlslice_0, and set properties + set xlslice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 ] + # Create instance: zero_constant, and set properties set zero_constant [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 zero_constant ] set_property -dict [ list \ @@ -2240,7 +2242,6 @@ proc create_hier_cell_sequencer { parentCell nameHier } { # Create port connections connect_bd_net -net aclk_1 [get_bd_pins aclk] [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins blk_mem_gen_0/clkb] [get_bd_pins sequence_slice_0/clk] [get_bd_pins sequence_stepper_0/clk] - connect_bd_net -net adc_sts_1 [get_bd_pins adc_sts] [get_bd_pins sequence_stepper_0/writepointer] connect_bd_net -net aresetn3_1 [get_bd_pins keep_alive_aresetn] [get_bd_pins util_vector_logic_0/Op2] connect_bd_net -net blk_mem_gen_0_doutb [get_bd_pins blk_mem_gen_0/doutb] [get_bd_pins sequence_slice_0/seq_data] connect_bd_net -net bram_aresetn_1 [get_bd_pins bram_aresetn] [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] @@ -2267,7 +2268,7 @@ proc create_hier_cell_sequencer { parentCell nameHier } { connect_bd_net -net xlconcat_0_dout [get_bd_pins util_vector_logic_7/Op1] [get_bd_pins xlconcat_0/dout] connect_bd_net -net xlconcat_1_dout [get_bd_pins oa_dac] [get_bd_pins xlconcat_1/dout] connect_bd_net -net xlconstant_0_dout [get_bd_pins blk_mem_gen_0/enb] [get_bd_pins xlconstant_0/dout] - connect_bd_net -net xlslice_1_Dout [get_bd_pins pdm_sts] [get_bd_pins bram_element_slice/Din] [get_bd_pins sequence_stepper_0/step_counter] + connect_bd_net -net xlslice_1_Dout [get_bd_pins pdm_sts] [get_bd_pins bram_element_slice/Din] [get_bd_pins sequence_stepper_0/step_counter] [get_bd_pins xlslice_0/Din] connect_bd_net -net zero_constant1_dout [get_bd_pins concat_element_addr/In0] [get_bd_pins zero_constant1/dout] connect_bd_net -net zero_constant_dout [get_bd_pins concat_element_addr/In2] [get_bd_pins zero_constant/dout] @@ -3436,7 +3437,7 @@ proc create_root_design { parentCell } { connect_bd_net -net util_vector_logic_0_Res [get_bd_pins clk_wiz_0/clk_in_sel] [get_bd_pins reset_manager_0/isMaster] [get_bd_pins util_vector_logic_0/Res] connect_bd_net -net write_to_ram_adc_out_A [get_bd_pins counter_trigger/adc0] [get_bd_pins write_to_ram/adc_out_A] connect_bd_net -net write_to_ram_adc_out_B [get_bd_pins counter_trigger/adc1] [get_bd_pins write_to_ram/adc_out_B] - connect_bd_net -net xlconcat_0_dout [get_bd_pins sequencer/adc_sts] [get_bd_pins system/adc_sts] [get_bd_pins write_to_ram/sts_data] + connect_bd_net -net xlconcat_0_dout [get_bd_pins system/adc_sts] [get_bd_pins write_to_ram/sts_data] connect_bd_net -net xlconcat_0_dout1 [get_bd_ports dac_pwm_o] [get_bd_pins sequencer/dout] connect_bd_net -net xlconcat_1_dout [get_bd_pins counter_trigger/counter_trigger_sts] [get_bd_pins system/counter_trigger_sts] connect_bd_net -net xlconstant_0_dout [get_bd_ports ext_DIO1_N] [get_bd_pins xlconstant_0/dout] diff --git a/src/fpga/hdl/sequence_stepper.v b/src/fpga/hdl/sequence_stepper.v index 25754421..2431364e 100644 --- a/src/fpga/hdl/sequence_stepper.v +++ b/src/fpga/hdl/sequence_stepper.v @@ -1,45 +1,37 @@ `timescale 1ns / 1ps module sequence_stepper( - input [63:0] writePointer, input [31:0] stepSize, input clk, input aresetn, - output [31:0] seq_counter + output [31:0] step_counter ); -reg [31:0] stepSize_int; -reg [31:0] seq_counter_state; -reg [31:0] sample_counter; -reg wp_prev, wp_next; +reg [63:0] step_counter_local, step_counter_local_next; +reg [31:0] step_counter_reg, step_counter_next; +reg [31:0] step_size_local; always @(posedge clk) begin - stepSize_int <= stepSize; - wp_next <= writePointer[0]; if (~aresetn) begin - seq_counter_state <= 0; - sample_counter <= stepSize_int; - wp_prev <= 0; + step_counter_reg <= 0; + step_counter_next <= 0; + step_counter_local <= 0; + step_counter_local_next <= 0; + step_size_local <= stepSize-1; end else begin - wp_prev <= wp_next; - if (wp_prev != wp_next) begin - - if (sample_counter == 0) begin - sample_counter <= stepSize_int; - seq_counter_state <= seq_counter_state + 1; - end else begin - sample_counter <= sample_counter - 1; - seq_counter_state <= seq_counter_state; - end - + step_counter_reg <= step_counter_next; + step_counter_local <= step_counter_local_next; + if (step_counter_local == step_size_local) begin + step_counter_local_next <= 0; + step_counter_next <= step_counter_reg + 1; end else begin - sample_counter <= sample_counter; - seq_counter_state <= seq_counter_state; + step_counter_local_next <= step_counter_local + 1; + step_counter_next <= step_counter_reg; end end end -assign seq_counter = seq_counter_state; +assign step_counter = step_counter_reg; endmodule diff --git a/src/lib/rp-daq-lib.c b/src/lib/rp-daq-lib.c index fe6eff16..2e3ecc12 100644 --- a/src/lib/rp-daq-lib.c +++ b/src/lib/rp-daq-lib.c @@ -777,11 +777,11 @@ int setPDMAllValuesVolt(float voltage, int channel) { int getSamplesPerStep() { int32_t value = *((int32_t *)(cfg + 4)); - return value; + return value*2/getDecimation(); } int setSamplesPerStep(int samples) { - *((int32_t *)(cfg + 4)) = samples; + *((int32_t *)(cfg + 4)) = samples/2*getDecimation(); return 0; }