From 58d04322534bc1902e23ddd0c92b4e6e0127a066 Mon Sep 17 00:00:00 2001
From: rp_local <n.a>
Date: Tue, 24 Sep 2024 15:42:18 +0000
Subject: [PATCH 01/38] Init Resync FPGA image

---
 src/fpga/bd/bd.tcl            | 41 ++++++++++++++++++++++++++++++-----
 src/fpga/bd/waveform_gen.tcl  | 26 ++++++++++++++++++----
 src/fpga/hdl/sequence_slice.v |  2 ++
 3 files changed, 59 insertions(+), 10 deletions(-)

diff --git a/src/fpga/bd/bd.tcl b/src/fpga/bd/bd.tcl
index 8e2e13fc..206a1a32 100644
--- a/src/fpga/bd/bd.tcl
+++ b/src/fpga/bd/bd.tcl
@@ -796,6 +796,7 @@ proc create_hier_cell_signal_compose1 { parentCell nameHier } {
   create_bd_pin -dir O -from 0 -to 0 m_axis_data_tvalid_1
   create_bd_pin -dir I -from 15 -to 0 offset
   create_bd_pin -dir O -from 1 -to 0 ramp_state_1
+  create_bd_pin -dir I resync_dac
   create_bd_pin -dir I start_ramp_down
 
   # Create instance: signal_calib_0, and set properties
@@ -899,10 +900,11 @@ proc create_hier_cell_signal_compose1 { parentCell nameHier } {
   connect_bd_net -net disable_dac_1 [get_bd_pins disable_dac] [get_bd_pins signal_composer_0/disable_dac]
   connect_bd_net -net enable_ramping_1 [get_bd_pins enable_ramping] [get_bd_pins signal_ramp_0/enableRamping]
   connect_bd_net -net offset_1 [get_bd_pins offset] [get_bd_pins signal_composer_0/seq]
+  connect_bd_net -net resync_dac_1 [get_bd_pins resync_dac] [get_bd_pins waveform_gen_0/resync] [get_bd_pins waveform_gen_1/resync] [get_bd_pins waveform_gen_2/resync] [get_bd_pins waveform_gen_3/resync]
   connect_bd_net -net rst_ps7_0_125M_peripheral_aresetn [get_bd_pins aresetn] [get_bd_pins signal_ramp_0/aresetn] [get_bd_pins waveform_awg1/aresetn] [get_bd_pins waveform_gen_0/aresetn] [get_bd_pins waveform_gen_1/aresetn] [get_bd_pins waveform_gen_2/aresetn] [get_bd_pins waveform_gen_3/aresetn]
   connect_bd_net -net signal_calib_0_signal_out [get_bd_pins S] [get_bd_pins signal_calib_0/signal_out]
-  connect_bd_net -net signal_cfg_slice_0_calib_limit_lower [get_bd_pins signal_calib_0/calib_limit_lower] [get_bd_pins signal_cfg_slice_0/calib_limit_lower]
-  connect_bd_net -net signal_cfg_slice_0_calib_limit_upper [get_bd_pins signal_calib_0/calib_limit_upper] [get_bd_pins signal_cfg_slice_0/calib_limit_upper]
+  connect_bd_net -net signal_cfg_slice_0_calib_limit_lower [get_bd_pins signal_cfg_slice_0/calib_limit_lower]
+  connect_bd_net -net signal_cfg_slice_0_calib_limit_upper [get_bd_pins signal_cfg_slice_0/calib_limit_upper]
   connect_bd_net -net signal_cfg_slice_0_calib_offset [get_bd_pins signal_calib_0/calib_offset] [get_bd_pins signal_cfg_slice_0/calib_offset]
   connect_bd_net -net signal_cfg_slice_0_calib_scale [get_bd_pins signal_calib_0/calib_scale] [get_bd_pins signal_cfg_slice_0/calib_scale]
   connect_bd_net -net signal_cfg_slice_0_comp_0_amp [get_bd_pins signal_cfg_slice_0/comp_0_amp] [get_bd_pins waveform_gen_0/amplitude]
@@ -990,6 +992,7 @@ proc create_hier_cell_signal_compose { parentCell nameHier } {
   create_bd_pin -dir O -from 0 -to 0 m_axis_data_tvalid_1
   create_bd_pin -dir I -from 15 -to 0 offset
   create_bd_pin -dir O -from 1 -to 0 ramp_state_0
+  create_bd_pin -dir I resync_dac
   create_bd_pin -dir I start_ramp_down
 
   # Create instance: signal_calib_0, and set properties
@@ -1094,9 +1097,10 @@ proc create_hier_cell_signal_compose { parentCell nameHier } {
   connect_bd_net -net disable_dac_1 [get_bd_pins disable_dac] [get_bd_pins signal_composer_0/disable_dac]
   connect_bd_net -net offset_1 [get_bd_pins offset] [get_bd_pins signal_composer_0/seq]
   connect_bd_net -net ramping_enable_1 [get_bd_pins enable_ramping] [get_bd_pins signal_ramp/enableRamping]
+  connect_bd_net -net resync_dac_1 [get_bd_pins resync_dac] [get_bd_pins waveform_gen_0/resync] [get_bd_pins waveform_gen_1/resync] [get_bd_pins waveform_gen_2/resync] [get_bd_pins waveform_gen_3/resync]
   connect_bd_net -net signal_calib_0_signal_out [get_bd_pins S] [get_bd_pins signal_calib_0/signal_out]
-  connect_bd_net -net signal_cfg_slice_0_calib_limit_lower [get_bd_pins signal_calib_0/calib_limit_lower] [get_bd_pins signal_cfg_slice_0/calib_limit_lower]
-  connect_bd_net -net signal_cfg_slice_0_calib_limit_upper [get_bd_pins signal_calib_0/calib_limit_upper] [get_bd_pins signal_cfg_slice_0/calib_limit_upper]
+  connect_bd_net -net signal_cfg_slice_0_calib_limit_lower [get_bd_pins signal_cfg_slice_0/calib_limit_lower]
+  connect_bd_net -net signal_cfg_slice_0_calib_limit_upper [get_bd_pins signal_cfg_slice_0/calib_limit_upper]
   connect_bd_net -net signal_cfg_slice_0_calib_offset [get_bd_pins signal_calib_0/calib_offset] [get_bd_pins signal_cfg_slice_0/calib_offset]
   connect_bd_net -net signal_cfg_slice_0_calib_scale [get_bd_pins signal_calib_0/calib_scale] [get_bd_pins signal_cfg_slice_0/calib_scale]
   connect_bd_net -net signal_cfg_slice_0_comp_0_amp [get_bd_pins signal_cfg_slice_0/comp_0_amp] [get_bd_pins waveform_gen_0/amplitude]
@@ -1576,7 +1580,7 @@ proc create_hier_cell_system_1 { parentCell nameHier } {
   # Create instance: image_version, and set properties
   set image_version [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 image_version ]
   set_property -dict [ list \
-   CONFIG.CONST_VAL {8} \
+   CONFIG.CONST_VAL {9} \
    CONFIG.CONST_WIDTH {32} \
  ] $image_version
 
@@ -2099,6 +2103,7 @@ proc create_hier_cell_sequencer { parentCell nameHier } {
   create_bd_pin -dir I -type rst keep_alive_aresetn
   create_bd_pin -dir O -from 31 -to 0 oa_dac
   create_bd_pin -dir O -from 31 -to 0 pdm_sts
+  create_bd_pin -dir O -from 1 -to 0 resync_dac
   create_bd_pin -dir O -from 1 -to 0 seq_ramp_down
 
   # Create instance: axi_bram_ctrl_0, and set properties
@@ -2251,6 +2256,7 @@ proc create_hier_cell_sequencer { parentCell nameHier } {
   connect_bd_net -net sequence_slice_0_pdm_value_1 [get_bd_pins pdm_2/din] [get_bd_pins sequence_slice_0/pdm_value_1]
   connect_bd_net -net sequence_slice_0_pdm_value_2 [get_bd_pins pdm_3/din] [get_bd_pins sequence_slice_0/pdm_value_2]
   connect_bd_net -net sequence_slice_0_pdm_value_3 [get_bd_pins pdm_4/din] [get_bd_pins sequence_slice_0/pdm_value_3]
+  connect_bd_net -net sequence_slice_0_resync_dac [get_bd_pins resync_dac] [get_bd_pins sequence_slice_0/resync_dac]
   connect_bd_net -net util_vector_logic_7_Res [get_bd_pins dout] [get_bd_pins util_vector_logic_7/Res]
   connect_bd_net -net xlconcat_0_dout [get_bd_pins util_vector_logic_7/Op1] [get_bd_pins xlconcat_0/dout]
   connect_bd_net -net xlconcat_1_dout [get_bd_pins oa_dac] [get_bd_pins xlconcat_1/dout]
@@ -2313,6 +2319,7 @@ proc create_hier_cell_fourier_synth_standard { parentCell nameHier } {
   create_bd_pin -dir I -from 31 -to 0 oa_dac
   create_bd_pin -dir O -from 1 -to 0 ramp_state_0
   create_bd_pin -dir O -from 1 -to 0 ramp_state_1
+  create_bd_pin -dir I -from 1 -to 0 resync_dac
   create_bd_pin -dir I -from 1 -to 0 seq_ramp_down
   create_bd_pin -dir I -from 1 -to 0 start_ramp_down
   create_bd_pin -dir O -from 31 -to 0 synth_tdata
@@ -2405,6 +2412,23 @@ proc create_hier_cell_fourier_synth_standard { parentCell nameHier } {
    CONFIG.DOUT_WIDTH {1} \
  ] $xlslice_5
 
+  # Create instance: xlslice_6, and set properties
+  set xlslice_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_6 ]
+  set_property -dict [ list \
+   CONFIG.DIN_FROM {0} \
+   CONFIG.DIN_TO {0} \
+   CONFIG.DIN_WIDTH {2} \
+ ] $xlslice_6
+
+  # Create instance: xlslice_7, and set properties
+  set xlslice_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_7 ]
+  set_property -dict [ list \
+   CONFIG.DIN_FROM {1} \
+   CONFIG.DIN_TO {1} \
+   CONFIG.DIN_WIDTH {2} \
+   CONFIG.DOUT_WIDTH {1} \
+ ] $xlslice_7
+
   # Create interface connections
   connect_bd_intf_net -intf_net awg_0_bram_1 [get_bd_intf_pins awg_0_bram] [get_bd_intf_pins signal_compose/awg_bram]
   connect_bd_intf_net -intf_net awg_1_bram_1 [get_bd_intf_pins awg_1_bram] [get_bd_intf_pins signal_compose1/awg_bram]
@@ -2422,6 +2446,7 @@ proc create_hier_cell_fourier_synth_standard { parentCell nameHier } {
   connect_bd_net -net enable_ramping_slice_0_start_ramp_down_0 [get_bd_pins enable_ramping_slice_0/start_ramp_down_0] [get_bd_pins signal_compose/start_ramp_down]
   connect_bd_net -net enable_ramping_slice_0_start_ramp_down_1 [get_bd_pins enable_ramping_slice_0/start_ramp_down_1] [get_bd_pins signal_compose1/start_ramp_down]
   connect_bd_net -net oa_dac_1 [get_bd_pins oa_dac] [get_bd_pins xlslice_2/Din] [get_bd_pins xlslice_3/Din]
+  connect_bd_net -net resync_dac_1 [get_bd_pins resync_dac] [get_bd_pins xlslice_6/Din] [get_bd_pins xlslice_7/Din]
   connect_bd_net -net seq_ramp_down_1 [get_bd_pins seq_ramp_down] [get_bd_pins enable_ramping_slice_0/seq_ramp_down]
   connect_bd_net -net signal_compose1_S [get_bd_pins signal_compose1/S] [get_bd_pins xlconcat_2/In1]
   connect_bd_net -net signal_compose1_m_axis_data_tvalid_1 [get_bd_pins signal_compose1/m_axis_data_tvalid_1] [get_bd_pins util_vector_logic_1/Op2]
@@ -2438,6 +2463,8 @@ proc create_hier_cell_fourier_synth_standard { parentCell nameHier } {
   connect_bd_net -net xlslice_3_Dout [get_bd_pins signal_compose/offset] [get_bd_pins xlslice_3/Dout]
   connect_bd_net -net xlslice_4_Dout [get_bd_pins signal_compose/disable_dac] [get_bd_pins xlslice_4/Dout]
   connect_bd_net -net xlslice_5_Dout [get_bd_pins signal_compose1/disable_dac] [get_bd_pins xlslice_5/Dout]
+  connect_bd_net -net xlslice_6_Dout [get_bd_pins signal_compose/resync_dac] [get_bd_pins xlslice_6/Dout]
+  connect_bd_net -net xlslice_7_Dout [get_bd_pins signal_compose1/resync_dac] [get_bd_pins xlslice_7/Dout]
 
   # Restore current instance
   current_bd_instance $oldCurInst
@@ -3391,6 +3418,7 @@ proc create_root_design { parentCell } {
   connect_bd_net -net selectio_wiz_2_clk_out [get_bd_pins clk_wiz_1/clk_in1] [get_bd_pins selectio_wiz_2/clk_out]
   connect_bd_net -net selectio_wiz_2_data_in_to_device [get_bd_pins reset_manager_0/sata_trigger] [get_bd_pins selectio_wiz_2/data_in_to_device]
   connect_bd_net -net sequencer_enable_dac [get_bd_pins fourier_synth_standard/enable_dac] [get_bd_pins sequencer/enable_dac]
+  connect_bd_net -net sequencer_resync_dac [get_bd_pins fourier_synth_standard/resync_dac] [get_bd_pins sequencer/resync_dac]
   connect_bd_net -net sequencer_seq_ramp_down [get_bd_pins fourier_synth_standard/seq_ramp_down] [get_bd_pins sequencer/seq_ramp_down]
   connect_bd_net -net system_FCLK_RESET0_N [get_bd_pins system/FCLK_RESET0_N] [get_bd_pins util_vector_logic_1/Op1]
   connect_bd_net -net system_cfg_data [get_bd_pins fourier_synth_standard/cfg_data] [get_bd_pins system/dac_cfg]
@@ -3434,7 +3462,6 @@ proc create_root_design { parentCell } {
   # Restore current instance
   current_bd_instance $oldCurInst
 
-  validate_bd_design
   save_bd_design
 }
 # End of create_root_design()
@@ -3447,3 +3474,5 @@ proc create_root_design { parentCell } {
 create_root_design ""
 
 
+common::send_gid_msg -ssname BD::TCL -id 2053 -severity "WARNING" "This Tcl script was generated from a block design that has not been validated. It is possible that design <$design_name> may result in errors during validation."
+
diff --git a/src/fpga/bd/waveform_gen.tcl b/src/fpga/bd/waveform_gen.tcl
index f56db04a..ac9b77b2 100644
--- a/src/fpga/bd/waveform_gen.tcl
+++ b/src/fpga/bd/waveform_gen.tcl
@@ -128,6 +128,7 @@ xilinx.com:ip:dds_compiler:6.0\
 xilinx.com:ip:mult_gen:12.0\
 jbeuke:user:signal_generator:1.0\
 xilinx.com:ip:xlconcat:2.1\
+xilinx.com:ip:xlconstant:1.1\
 "
 
    set list_ips_missing ""
@@ -203,12 +204,13 @@ proc create_root_design { parentCell } {
   set freq [ create_bd_port -dir I -from 47 -to 0 freq ]
   set m_axis_data_tvalid_1 [ create_bd_port -dir O m_axis_data_tvalid_1 ]
   set phase [ create_bd_port -dir I -from 47 -to 0 phase ]
+  set resync [ create_bd_port -dir I resync ]
   set wave [ create_bd_port -dir O -from 15 -to 0 -type data wave ]
 
   # Create instance: axis_variable_A_channel_1, and set properties
   set axis_variable_A_channel_1 [ create_bd_cell -type ip -vlnv pavel-demin:user:axis_variable:1.0 axis_variable_A_channel_1 ]
   set_property -dict [ list \
-   CONFIG.AXIS_TDATA_WIDTH {96} \
+   CONFIG.AXIS_TDATA_WIDTH {104} \
  ] $axis_variable_A_channel_1
 
   # Create instance: dds_compiler_A_channel_1, and set properties
@@ -233,10 +235,11 @@ proc create_root_design { parentCell } {
    CONFIG.POFF1 {0} \
    CONFIG.Parameter_Entry {System_Parameters} \
    CONFIG.PartsPresent {Phase_Generator_and_SIN_COS_LUT} \
-   CONFIG.Phase_Increment {Programmable} \
+   CONFIG.Phase_Increment {Streaming} \
    CONFIG.Phase_Offset_Angles1 {0} \
    CONFIG.Phase_Width {48} \
-   CONFIG.Phase_offset {Programmable} \
+   CONFIG.Phase_offset {Streaming} \
+   CONFIG.Resync {true} \
    CONFIG.S_PHASE_Has_TUSER {Not_Required} \
    CONFIG.Spurious_Free_Dynamic_Range {84} \
  ] $dds_compiler_A_channel_1
@@ -261,15 +264,27 @@ proc create_root_design { parentCell } {
    CONFIG.CFG_DATA_WIDTH {48} \
  ] $signal_generator_0
 
+  # Create instance: xlconcat_0, and set properties
+  set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ]
+
   # Create instance: xlconcat_A_channel_1, and set properties
   set xlconcat_A_channel_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_A_channel_1 ]
   set_property -dict [ list \
    CONFIG.IN0_WIDTH {48} \
    CONFIG.IN1_WIDTH {48} \
+   CONFIG.IN2_WIDTH {8} \
+   CONFIG.NUM_PORTS {3} \
  ] $xlconcat_A_channel_1
 
+  # Create instance: xlconstant_0, and set properties
+  set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
+  set_property -dict [ list \
+   CONFIG.CONST_VAL {0} \
+   CONFIG.CONST_WIDTH {7} \
+ ] $xlconstant_0
+
   # Create interface connections
-  connect_bd_intf_net -intf_net axis_variable_A_channel_1_M_AXIS [get_bd_intf_pins axis_variable_A_channel_1/M_AXIS] [get_bd_intf_pins dds_compiler_A_channel_1/S_AXIS_CONFIG]
+  connect_bd_intf_net -intf_net axis_variable_A_channel_1_M_AXIS [get_bd_intf_pins axis_variable_A_channel_1/M_AXIS] [get_bd_intf_pins dds_compiler_A_channel_1/S_AXIS_PHASE]
   connect_bd_intf_net -intf_net dds_compiler_A_channel_1_M_AXIS_DATA [get_bd_intf_pins dds_compiler_A_channel_1/M_AXIS_DATA] [get_bd_intf_pins signal_generator_0/s_axis]
   connect_bd_intf_net -intf_net dds_compiler_A_channel_1_M_AXIS_PHASE [get_bd_intf_pins dds_compiler_A_channel_1/M_AXIS_PHASE] [get_bd_intf_pins signal_generator_0/s_axis_phase]
 
@@ -280,10 +295,13 @@ proc create_root_design { parentCell } {
   connect_bd_net -net mult_gen_0_P [get_bd_ports wave] [get_bd_pins mult_gen_0/P]
   connect_bd_net -net phase_1 [get_bd_ports phase] [get_bd_pins xlconcat_A_channel_1/In1]
   connect_bd_net -net phase_A_channel_1_slice1_Dout [get_bd_ports cfg_data] [get_bd_pins signal_generator_0/cfg_data]
+  connect_bd_net -net resync_1 [get_bd_ports resync] [get_bd_pins xlconcat_0/In0]
   connect_bd_net -net rst_ps7_0_125M_peripheral_aresetn [get_bd_ports aresetn] [get_bd_pins axis_variable_A_channel_1/aresetn] [get_bd_pins dds_compiler_A_channel_1/aresetn] [get_bd_pins signal_generator_0/aresetn]
   connect_bd_net -net signal_generator_0_m_axis_tdata [get_bd_pins mult_gen_0/B] [get_bd_pins signal_generator_0/m_axis_tdata]
   connect_bd_net -net signal_generator_0_m_axis_tvalid [get_bd_ports m_axis_data_tvalid_1] [get_bd_pins signal_generator_0/m_axis_tvalid]
+  connect_bd_net -net xlconcat_0_dout [get_bd_pins xlconcat_0/dout] [get_bd_pins xlconcat_A_channel_1/In2]
   connect_bd_net -net xlconcat_A_channel_1_dout [get_bd_pins axis_variable_A_channel_1/cfg_data] [get_bd_pins xlconcat_A_channel_1/dout]
+  connect_bd_net -net xlconstant_0_dout [get_bd_pins xlconcat_0/In1] [get_bd_pins xlconstant_0/dout]
 
   # Create address segments
 
diff --git a/src/fpga/hdl/sequence_slice.v b/src/fpga/hdl/sequence_slice.v
index 7e3f15f8..67b36e07 100644
--- a/src/fpga/hdl/sequence_slice.v
+++ b/src/fpga/hdl/sequence_slice.v
@@ -11,6 +11,7 @@ module sequence_slice(
     output [10:0] pdm_value_2,
     output [10:0] pdm_value_3,
     output [1:0] enable_dac,
+    output [1:0] resync_dac,
     output [3:0] enable_pdm,
     output [1:0] enable_dac_ramp_down
 );
@@ -41,6 +42,7 @@ assign pdm_value_3[10:0] = seq_data_int[90:80];
 // Flags
 assign enable_dac[1:0] = seq_data_int[97:96];
 assign enable_pdm[3:0] = seq_data_int[101:98];
+assign resync_dac[1:0] = seq_data_init[31:30];
 assign enable_dac_ramp_down[0] = seq_data_int[112];
 assign enable_dac_ramp_down[1] = seq_data_int[113];
 

From ed6f10164c817b331dcb7f20d8c199797a8f32c1 Mon Sep 17 00:00:00 2001
From: rp_local <n.a>
Date: Tue, 24 Sep 2024 15:42:44 +0000
Subject: [PATCH 02/38] Init resync rp-lib

---
 src/lib/rp-daq-lib.c | 26 ++++++++++++++++++++++++++
 src/lib/rp-daq-lib.h |  2 ++
 2 files changed, 28 insertions(+)

diff --git a/src/lib/rp-daq-lib.c b/src/lib/rp-daq-lib.c
index ffa18329..37f26941 100644
--- a/src/lib/rp-daq-lib.c
+++ b/src/lib/rp-daq-lib.c
@@ -637,6 +637,32 @@ int setEnableDAC(int8_t value, int channel, int index) {
 	return 0;
 }
 
+int setResyncDACAll(int8_t value, int channel) {
+	for(int i=0; i<PDM_BUFF_SIZE; i++) {
+		setResyncDAC(value,channel,i);
+	}
+	return 0;
+}
+
+int setResyncDAC(int8_t value, int channel, int index) {
+	if(channel < 0 || channel >= 2) {
+		return -2;
+	}
+
+	if (value < 0 || value >= 2)
+		return -1;
+
+	int bitpos = 14 + channel;
+	// Reset bit is in the 2-th channel
+	int offset = 8 * index + 2;
+	// clear the bit
+	*((int16_t *)(pdm_cfg + offset)) &= ~(1u << bitpos);
+	// set the bit
+	*((int16_t *)(pdm_cfg + offset)) |= (value << bitpos);
+	//printf("%d reset pdm\n", *((int16_t *)(pdm_cfg + 2*(0+4*index))));
+	return 0;
+}
+
 int setResetDAC(int8_t value, int index) {
 	if (value < 0 || value >= 2)
 		return -1;
diff --git a/src/lib/rp-daq-lib.h b/src/lib/rp-daq-lib.h
index 649a6dcc..9dc8378f 100644
--- a/src/lib/rp-daq-lib.h
+++ b/src/lib/rp-daq-lib.h
@@ -143,6 +143,8 @@ extern uint32_t getXADCValue(int);
 extern float getXADCValueVolt(int);
 extern int setEnableDACAll(int8_t, int);
 extern int setEnableDAC(int8_t, int, int);
+extern int setResyncDACAll(int8_t, int);
+extern int setResyncDAC(int8_t, int, int);
 //extern int setResetDAC(int8_t, int);
 extern int setRampDownDAC(int8_t, int, int);
 extern int getRampDownDAC(int, int);

From d82017459db92e6396a7e4f9b5a278463a5276a4 Mon Sep 17 00:00:00 2001
From: rp_local <n.a>
Date: Tue, 24 Sep 2024 15:43:00 +0000
Subject: [PATCH 03/38] Init resync server

---
 src/server/control.c         | 19 +++++++++++++++++++
 src/server/daq_server_scpi.h |  2 ++
 src/server/scpi_commands.c   | 26 ++++++++++++++++++++++++++
 3 files changed, 47 insertions(+)

diff --git a/src/server/control.c b/src/server/control.c
index abca9c2a..0ec9b880 100644
--- a/src/server/control.c
+++ b/src/server/control.c
@@ -46,6 +46,7 @@ sequenceData_t * allocSequence() {
 	seq->enableLUT = NULL;
 	seq->rampUp = NULL;
 	seq->rampDown = NULL;
+	seq->resyncLUT = NULL;
 	return seq; 
 }
 
@@ -66,6 +67,10 @@ void freeSequence(sequenceData_t *seqData) {
 		freeRamping(seqData->rampDown);
 		seqData->rampDown = NULL;
 	}
+	if (seqData->resyncLUT != NULL) {
+		free(seqData->resyncLUT);
+		seqData->resyncLUT = NULL;
+	}
 }
 
 rampingData_t * allocRamping() {
@@ -120,6 +125,15 @@ bool getSequenceEnableValue(sequenceData_t *seqData, int seqStep, int channel) {
 	return result;
 }
 
+bool getSequenceResyncValue(sequenceData_t *seqData, int seqStep, int channel) {
+	bool result = false;
+	if (seqData->resyncLUT != NULL) {
+		int localStep = seqStep % seqData->numStepsPerRepetition;
+		result = seqData->resyncLUT[localStep + channel];
+	}
+	return result;
+}
+
 float getRampingValue(rampingData_t *rampData, int rampStep, int channel) {
 	int localStep = rampStep % rampData->numStepsPerRepetition;
 	return rampData->LUT[localStep * numSlowDACChan + channel];
@@ -216,6 +230,7 @@ static void setLUTValuesFor(int futureStep, int channel, int currPDMIndex) {
 	float val = 0.0;
 	bool enable = true;
 	bool rampDown = false;
+	bool resync = false;
 
 	switch(interval) {
 		case RAMPUP:
@@ -224,6 +239,7 @@ static void setLUTValuesFor(int futureStep, int channel, int currPDMIndex) {
 		case REGULAR:
 			val = getSequenceValue(activeSequence, localStep, channel);
 			enable = getSequenceEnableValue(activeSequence, localStep, channel);
+			resync = getSequenceResyncValue(activeSequence, localStep, channel);
 			break;
 		case RAMPDOWN:
 			val = getRampingValue(activeSequence->rampDown, localStep, channel);
@@ -240,6 +256,9 @@ static void setLUTValuesFor(int futureStep, int channel, int currPDMIndex) {
 		printf("Could not set AO[%d] voltage.\n", channel);	
 	}
 	setEnableDAC(enable, channel, currPDMIndex);
+	if (channel < 2) {
+		setResyncDAC(resync, channel, currPDMIndex);
+	}
 	setRampDownDAC(rampDown, channel, currPDMIndex);
 
 }
diff --git a/src/server/daq_server_scpi.h b/src/server/daq_server_scpi.h
index 4fdf6f08..08e9adf2 100644
--- a/src/server/daq_server_scpi.h
+++ b/src/server/daq_server_scpi.h
@@ -107,6 +107,7 @@ typedef struct {
 	int numStepsPerRepetition; // How many steps per repetition
 	float* LUT; // LUT for value function pointer
 	bool * enableLUT;
+	bool * resyncLUT;
 	rampingData_t* rampUp;
 	rampingData_t* rampDown;
 } sequenceData_t;
@@ -131,6 +132,7 @@ extern sequenceInterval_t computeInterval(sequenceData_t *seqData, int step);
 extern bool isSequenceConfigurable();
 extern float getSequenceValue(sequenceData_t *seqData, int seqStep, int channel);
 extern bool getSequenceEnableValue(sequenceData_t *seqData, int seqStep, int channel);
+extern bool getSequenceResyncValue(sequenceData_t *seqData, int seqStep, int channel);
 extern float getRampingValue(rampingData_t *rampData, int rampStep, int channel);
 extern int getRampUpSteps(sequenceData_t *seqData);
 extern int getRampDownSteps(sequenceData_t *seqData);
diff --git a/src/server/scpi_commands.c b/src/server/scpi_commands.c
index 7629ba5b..6025297e 100644
--- a/src/server/scpi_commands.c
+++ b/src/server/scpi_commands.c
@@ -1056,6 +1056,31 @@ static scpi_result_t RP_DAC_SetEnableLUT(scpi_t * context) {
 	}
 }
 
+static scpi_result_t RP_DAC_SetResyncLUT(scpi_t * context) {
+
+	readyConfigSequence();
+
+	if(configSeq->LUT != NULL && numSlowDACChan > 0 && isSequenceConfigurable()) {
+		if(configSeq->resyncLUT != NULL) {
+			free(configSeq->resyncLUT);
+			configSeq->resyncLUT = NULL;
+		}
+
+		int numChan = numSlowDACChan > 2 ? 2 : numSlowDACChan;
+		printf("Allocating ressyncLUT\n");
+		configSeq->resyncLUT = (bool *)calloc(numChan, configSeq->numStepsPerRepetition * sizeof(bool));
+
+		int n = readAll(newdatasockfd, configSeq->resyncLUT, numSlowDACChan * configSeq->numStepsPerRepetition * sizeof(bool));
+		seqState = CONFIG;
+		if (n < 0) perror("ERROR reading from socket");
+		return returnSCPIBool(context, true);
+	}
+	else {
+		return returnSCPIBool(context, false);
+	}
+
+}
+
 static scpi_result_t RP_DAC_SetUpLUT(scpi_t * context) {
 
 	readyConfigSequence();
@@ -1739,6 +1764,7 @@ const scpi_command_t scpi_commands[] = {
 	{.pattern = "RP:DAC:SEQ:CHan?", .callback = RP_DAC_GetNumSlowDACChan,},
 	{.pattern = "RP:DAC:SEQ:LUT", .callback = RP_DAC_SetValueLUT,},
 	{.pattern = "RP:DAC:SEQ:LUT:ENaBle", .callback = RP_DAC_SetEnableLUT,},
+	{.pattern = "RP:DAC:SEQ:LUT:ReSYNC", .callback = RP_DAC_SetResyncLUT,},
 	{.pattern = "RP:DAC:SEQ:LUT:UP", .callback = RP_DAC_SetUpLUT,},
 	{.pattern = "RP:DAC:SEQ:LUT:DOWN", .callback = RP_DAC_SetDownLUT,},
 	{.pattern = "RP:DAC:SEQ:SET", .callback = RP_DAC_SetSequence,},

From 268702b496b433daa4b314edcd1a86a3634859a9 Mon Sep 17 00:00:00 2001
From: rp_local <n.a>
Date: Tue, 24 Sep 2024 15:43:11 +0000
Subject: [PATCH 04/38] Init resync julia client

---
 src/client/julia/src/Sequence.jl | 52 ++++++++++++++++++++++++--------
 1 file changed, 40 insertions(+), 12 deletions(-)

diff --git a/src/client/julia/src/Sequence.jl b/src/client/julia/src/Sequence.jl
index db223879..25054eef 100644
--- a/src/client/julia/src/Sequence.jl
+++ b/src/client/julia/src/Sequence.jl
@@ -134,17 +134,19 @@ abstract type RampingSequence <: AbstractSequence end
 struct SimpleRampingSequence <: AbstractSequence 
   lut::SequenceLUT
   enable::Union{Array{Bool}, Nothing}
+  resync::Union{Array{Bool}, Nothing}
   rampUp::SequenceLUT
   rampDown::SequenceLUT
-  function SimpleRampingSequencee(lut::SequenceLUT, up::SequenceLUT, down::SequenceLUT, enable::Union{Array{Bool}, Nothing}=nothing)
+  function SimpleRampingSequencee(lut::SequenceLUT, up::SequenceLUT, down::SequenceLUT, enable::Union{Array{Bool}, Nothing}=nothing, resync::Union{Array{Bool}, Nothing}=nothing)
     if !isnothing(enable) && size(values(lut)) != size(enable)
       throw(DimensionMismatch("Size of enable LUT does not match size of value LUT"))
     end
-    return new(SequenceLUT(lut, repetitions), enable, up, down)
+    return new(SequenceLUT(lut, repetitions), enable, resync, up, down)
   end
 end
 
 enableLUT(seq::SimpleRampingSequence) = seq.enable
+resyncLUT(seq::SimpleRampingSequence) = seq.resync
 valueLUT(seq::SimpleRampingSequence) = seq.lut
 rampUpLUT(seq::SimpleRampingSequence) = nothing
 rampDownLUT(seq::SimpleRampingSequence) = nothing
@@ -158,6 +160,7 @@ end
 struct HoldBorderRampingSequence <: RampingSequence
   lut::SequenceLUT
   enable::Union{Array{Bool}, Nothing}
+  resync::Union{Array{Bool}, Nothing}
   rampUp::SequenceLUT
   rampDown::SequenceLUT
 
@@ -170,13 +173,13 @@ struct HoldBorderRampingSequence <: RampingSequence
   - `lut`,`repetitions`,`enable` are used the same as for a `SimpleSequence`
   - `rampingSteps` is the number of steps the first and last value of the given sequence are repeated before the sequence is started
   """
-  function HoldBorderRampingSequence(lut::Array{Float32}, repetitions::Integer, rampingSteps::Integer, enable::Union{Array{Bool}, Nothing}=nothing)
+  function HoldBorderRampingSequence(lut::Array{Float32}, repetitions::Integer, rampingSteps::Integer, enable::Union{Array{Bool}, Nothing}=nothing, resync::Union{Array{Bool}, Nothing}=nothing)
     if !isnothing(enable) && size(lut) != size(enable)
       throw(DimensionMismatch("Size of enable LUT does not match size of value LUT"))
     end
     up = SequenceLUT(lut[:, 1], rampingSteps)
     down = SequenceLUT(lut[:, end], rampingSteps)
-    return new(SequenceLUT(lut, repetitions), enable, up, down)
+    return new(SequenceLUT(lut, repetitions), enable, resync, up, down)
   end
 end
 
@@ -190,6 +193,7 @@ function HoldBorderRampingSequence(rp::RedPitaya, lut, repetitions, enable=nothi
 end
 
 enableLUT(seq::HoldBorderRampingSequence) = seq.enable
+resyncLUT(seq::HoldBorderRampingSequence) = seq.resync
 valueLUT(seq::HoldBorderRampingSequence) = seq.lut
 rampUpLUT(seq::HoldBorderRampingSequence) = seq.rampUp
 rampDownLUT(seq::HoldBorderRampingSequence) = seq.rampDown
@@ -197,14 +201,15 @@ rampDownLUT(seq::HoldBorderRampingSequence) = seq.rampDown
 struct ConstantRampingSequence <: RampingSequence
   lut::SequenceLUT
   enable::Union{Array{Bool}, Nothing}
+  resync::Union{Array{Bool}, Nothing}
   ramping::SequenceLUT
 
-  function ConstantRampingSequence(lut::Array{Float32}, repetitions::Integer, rampingValue::Float32, rampingSteps::Integer, enable::Union{Array{Bool}, Nothing}=nothing)
+  function ConstantRampingSequence(lut::Array{Float32}, repetitions::Integer, rampingValue::Float32, rampingSteps::Integer, enable::Union{Array{Bool}, Nothing}=nothing, resync::Union{Array{Bool}, Nothing}=nothing)
     if !isnothing(enable) && size(lut) != size(enable)
       throw(DimensionMismatch("Size of enable LUT does not match size of value LUT"))
     end
     rampingLut = SequenceLUT([rampingValue for i = 1:size(lut, 1)], rampingSteps)
-    return new(SequenceLUT(lut, repetitions), enable, rampingLut)
+    return new(SequenceLUT(lut, repetitions), enable, resync, rampingLut)
   end
 end
 ConstantRampingSequence(lut::Array{T}, repetitions::Integer, rampingValue::Real, rampingSteps::Integer, enable::Union{Array{Bool}, Nothing}=nothing) where T <: Real = ConstantRampingSequence(map(Float32, lut), repetitions, Float32(rampingValue), rampingSteps, enable)
@@ -212,6 +217,7 @@ ConstantRampingSequence(lut::Vector{Float32}, repetitions::Integer, rampingValue
 ConstantRampingSequence(lut::Vector{T}, repetitions::Integer, rampingValue::Real, rampingSteps::Integer, enable::Union{Array{Bool}, Nothing}=nothing) where T <: Real = ConstantRampingSequence(reshape(lut, 1, :), repetitions, rampingValue, rampingSteps, enable)
 
 enableLUT(seq::ConstantRampingSequence) = seq.enable
+resyncLUT(seq::ConstantRampingSequence) = seq.resync
 valueLUT(seq::ConstantRampingSequence) = seq.lut
 rampUpLUT(seq::ConstantRampingSequence) = seq.ramping
 rampDownLUT(seq::ConstantRampingSequence) = seq.ramping
@@ -219,9 +225,10 @@ rampDownLUT(seq::ConstantRampingSequence) = seq.ramping
 struct StartUpSequence <: RampingSequence
   lut::SequenceLUT
   enable::Union{Array{Bool}, Nothing}
+  resync::Union{Array{Bool}, Nothing}
   rampUp::SequenceLUT
   rampDown::SequenceLUT
-  function StartUpSequence(lut::Array{Float32}, repetitions::Integer, rampingSteps::Integer, startUpSteps::Integer, enable::Union{Array{Bool}, Nothing}=nothing)
+  function StartUpSequence(lut::Array{Float32}, repetitions::Integer, rampingSteps::Integer, startUpSteps::Integer, enable::Union{Array{Bool}, Nothing}=nothing, resync::Union{Array{Bool}, Nothing}=nothing)
     if !isnothing(enable) && size(lut) != size(enable)
       throw(DimensionMismatch("Size of enable LUT does not match size of value LUT"))
     end
@@ -239,7 +246,7 @@ struct StartUpSequence <: RampingSequence
     end
     up = SequenceLUT(upLut, 1)
     down = SequenceLUT(lut[:, end], rampingSteps)
-    return new(SequenceLUT(lut, repetitions), enable, up, down)
+    return new(SequenceLUT(lut, repetitions), enable, resync, up, down)
   end
 end
 StartUpSequence(lut::Array{T}, repetitions::Integer, rampingSteps::Integer, startUpSteps::Integer, enable::Union{Array{Bool}, Nothing}=nothing) where T <: Real = StartUpSequence(map(Float32, lut), repetitions, rampingSteps, startUpSteps, enable)
@@ -247,6 +254,7 @@ StartUpSequence(lut::Array{T}, repetitions::Integer, rampingSteps::Integer, star
 StartUpSequence(lut::Vector{T}, repetitions::Integer, rampingSteps::Integer, startUpSteps::Integer, enable::Union{Array{Bool}, Nothing}=nothing) where T <: Real = StartUpSequence(reshape(lut, 1, :), repetitions, rampingSteps, startUpSteps, enable)
 
 enableLUT(seq::StartUpSequence) = seq.enable
+resyncLUT(seq::StartUpSequence) = seq.resync
 valueLUT(seq::StartUpSequence) = seq.lut
 rampUpLUT(seq::StartUpSequence) = seq.rampUp
 rampDownLUT(seq::StartUpSequence) = seq.rampDown
@@ -269,10 +277,11 @@ Transmit the client-side representation `seq` to the server and append it to the
 """
 function sequence!(rp::RedPitaya, seq::AbstractSequence)
   result = true
-  result &= valueLUT!(rp, valueLUT(seq))
-  result &= enableLUT!(rp, enableLUT(seq))
-  result &= rampUpLUT!(rp, rampUpLUT(seq))
-  result &= rampDownLUT!(rp, rampDownLUT(seq))
+  result &= valueLUT!(rp, seq)
+  result &= enableLUT!(rp, seq)
+  result &= resyncLUT!(rp, seq)
+  result &= rampUpLUT!(rp, seq)
+  result &= rampDownLUT!(rp, seq)
   result &= setSequence!(rp)
   return result
 end
@@ -283,11 +292,13 @@ function transmitLUT!(rp::RedPitaya, lut::Array{Float32}, cmd::String, repetitio
   return parse(Bool, receive(rp))
 end
 
+valueLUT!(rp::RedPitaya, lut::AbstractSequence) = valueLUT!(rp, valueLUT(lut))
 function valueLUT!(rp::RedPitaya, lut::SequenceLUT)
   lutFloat32 = map(Float32, values(lut))
   return transmitLUT!(rp, lutFloat32, "RP:DAC:SEQ:LUT", repetitions(lut))
 end
 
+rampUpLUT!(rp::RedPitaya, lut::AbstractSequence) = rampUpLUT!(rp, rampUpLUT(lut))
 function rampUpLUT!(rp::RedPitaya, lut::SequenceLUT)
   lutFloat32 = map(Float32, values(lut))
   return transmitLUT!(rp, lutFloat32, "RP:DAC:SEQ:LUT:UP", repetitions(lut))
@@ -298,6 +309,7 @@ function rampUpLUT!(rp::RedPitaya, lut::Nothing)
   return true
 end
 
+rampDownLUT!(rp::RedPitaya, lut::AbstractSequence) = rampDownLUT!(rp, rampDownLUT(lut))
 function rampDownLUT!(rp::RedPitaya, lut::SequenceLUT)
   lutFloat32 = map(Float32, values(lut))
   return transmitLUT!(rp, lutFloat32, "RP:DAC:SEQ:LUT:DOWN", repetitions(lut))
@@ -308,6 +320,7 @@ function rampDownLUT!(rp::RedPitaya, lut::Nothing)
   return true
 end
 
+enableLUT!(rp::RedPitaya, lut::AbstractSequence) = enableLUT!(rp, enableLUT(lut))
 function enableLUT!(rp::RedPitaya, lut::Array)
   lutBool = map(Bool, lut)
   send(rp, string("RP:DAC:SEQ:LUT:ENaBle"))
@@ -322,6 +335,21 @@ function enableLUT!(rp::RedPitaya, lut::Nothing)
   return true
 end
 
+resyncLUT!(rp::RedPitaya, lut::AbstractSequence) = resyncLUT!(rp, resyncLUT(lut))
+function resyncLUT!(rp::RedPitaya, lut::Array)
+  lutBool = map(Bool, lut)
+  send(rp, string("RP:DAC:SEQ:LUT:ReSYNC"))
+  @debug "Writing resync DAC LUT"
+  write(rp.dataSocket, lutBool)
+  reply = receive(rp)
+  return parse(Bool, reply)
+end
+
+function resyncLUT!(rp::RedPitaya, lut::Nothing)
+  # NOP
+  return true
+end
+
 function seqTiming(seq::AbstractSequence)
   up = 0
   if !isnothing(rampUpLUT(seq)) 

From 7b8d04e42773a6f995a32144e5c5eead13bdb968 Mon Sep 17 00:00:00 2001
From: rp_local <n.a>
Date: Tue, 24 Sep 2024 15:54:25 +0000
Subject: [PATCH 05/38] Fix variable name in seq_data_int

---
 src/fpga/hdl/sequence_slice.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/fpga/hdl/sequence_slice.v b/src/fpga/hdl/sequence_slice.v
index 67b36e07..ab2e91a5 100644
--- a/src/fpga/hdl/sequence_slice.v
+++ b/src/fpga/hdl/sequence_slice.v
@@ -42,7 +42,7 @@ assign pdm_value_3[10:0] = seq_data_int[90:80];
 // Flags
 assign enable_dac[1:0] = seq_data_int[97:96];
 assign enable_pdm[3:0] = seq_data_int[101:98];
-assign resync_dac[1:0] = seq_data_init[31:30];
+assign resync_dac[1:0] = seq_data_int[31:30];
 assign enable_dac_ramp_down[0] = seq_data_int[112];
 assign enable_dac_ramp_down[1] = seq_data_int[113];
 

From 0457f85cf1d6d720f3f73e57605fe49db0ce0ac0 Mon Sep 17 00:00:00 2001
From: rp_local <n.a>
Date: Wed, 25 Sep 2024 16:05:18 +0000
Subject: [PATCH 06/38] Init working resync based on aresetn

---
 src/client/julia/Project.toml    |  2 +-
 src/client/julia/src/Sequence.jl | 12 +++++----
 src/fpga/bd/bd.tcl               |  9 +++++--
 src/fpga/bd/waveform_gen.tcl     | 45 ++++++++++++++++++--------------
 src/lib/rp-daq-lib.c             |  5 ++--
 src/server/control.c             |  6 +++--
 6 files changed, 47 insertions(+), 32 deletions(-)

diff --git a/src/client/julia/Project.toml b/src/client/julia/Project.toml
index 654c97b0..26393c4d 100644
--- a/src/client/julia/Project.toml
+++ b/src/client/julia/Project.toml
@@ -1,7 +1,7 @@
 name = "RedPitayaDAQServer"
 uuid = "c544963a-496b-56d4-a5fe-f99a3f174c8f"
 authors = ["Tobias Knopp <tobias@knoppweb.de>"]
-version = "0.8.2"
+version = "0.9.0"
 
 [deps]
 LinearAlgebra = "37e2e46d-f89d-539d-b4ee-838fcccc9c8e"
diff --git a/src/client/julia/src/Sequence.jl b/src/client/julia/src/Sequence.jl
index 25054eef..7b197ed5 100644
--- a/src/client/julia/src/Sequence.jl
+++ b/src/client/julia/src/Sequence.jl
@@ -103,7 +103,8 @@ Struct representing a sequence in which the server directly takes the values fro
 """
 struct SimpleSequence <: AbstractSequence
   lut::SequenceLUT
-  enable::Union{Array{Bool}, Nothing}
+  enable::Union{Matrix{Bool}, Nothing}
+  resync::Union{Matrix{Bool}, Nothing}
   """
     SimpleSequence(lut, repetitions, enable=nothing)
 
@@ -114,17 +115,18 @@ struct SimpleSequence <: AbstractSequence
   - `repetitions::Int32`: the number of times the sequence should be repeated
   - `emable::Union{Array{Bool}, Nothing}`: matrix containing enable flags
   """
-  function SimpleSequence(lut::Array{Float32}, repetitions::Integer, enable::Union{Array{Bool}, Nothing}=nothing)
+  function SimpleSequence(lut::Matrix{Float32}, repetitions::Integer, enable::Union{Matrix{Bool}, Nothing}=nothing, resync::Union{Matrix{Bool}, Nothing} = nothing)
     if !isnothing(enable) && size(lut) != size(enable)
       throw(DimensionMismatch("Size of enable LUT does not match size of value LUT"))
     end
-    return new(SequenceLUT(lut, repetitions), enable)
+    return new(SequenceLUT(lut, repetitions), enable, resync)
   end
 end
-SimpleSequence(lut::Array{T}, repetitions::Integer, enable::Union{Array{Bool}, Nothing}=nothing) where T <: Real = SimpleSequence(map(Float32, lut), repetitions, enable)
-SimpleSequence(lut::Vector{T}, repetitions::Integer, enable::Union{Array{Bool}, Nothing}=nothing) where T <: Real = SimpleSequence(reshape(lut, 1, :), repetitions, enable)
+SimpleSequence(lut::Array{T}, repetitions::Integer, args...) where T <: Real = SimpleSequence(map(Float32, lut), repetitions, args...)
+SimpleSequence(lut::Vector{T}, repetitions::Integer, args...) where T <: Real = SimpleSequence(reshape(lut, 1, :), repetitions, args...)
 
 enableLUT(seq::SimpleSequence) = seq.enable
+resyncLUT(seq::SimpleSequence) = seq.resync
 valueLUT(seq::SimpleSequence) = seq.lut
 rampUpLUT(seq::SimpleSequence) = nothing
 rampDownLUT(seq::SimpleSequence) = nothing
diff --git a/src/fpga/bd/bd.tcl b/src/fpga/bd/bd.tcl
index 206a1a32..e9ae2bab 100644
--- a/src/fpga/bd/bd.tcl
+++ b/src/fpga/bd/bd.tcl
@@ -402,6 +402,9 @@ proc create_hier_cell_waveform_awg1 { parentCell nameHier } {
   
   # Create instance: xlconcat_0, and set properties
   set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ]
+  set_property -dict [ list \
+   CONFIG.IN0_WIDTH {48} \
+ ] $xlconcat_0
 
   # Create instance: xlconstant_0, and set properties
   set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
@@ -572,6 +575,9 @@ proc create_hier_cell_waveform_awg { parentCell nameHier } {
   
   # Create instance: xlconcat_0, and set properties
   set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ]
+  set_property -dict [ list \
+   CONFIG.IN0_WIDTH {48} \
+ ] $xlconcat_0
 
   # Create instance: xlconstant_0, and set properties
   set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
@@ -3462,6 +3468,7 @@ proc create_root_design { parentCell } {
   # Restore current instance
   current_bd_instance $oldCurInst
 
+  validate_bd_design
   save_bd_design
 }
 # End of create_root_design()
@@ -3474,5 +3481,3 @@ proc create_root_design { parentCell } {
 create_root_design ""
 
 
-common::send_gid_msg -ssname BD::TCL -id 2053 -severity "WARNING" "This Tcl script was generated from a block design that has not been validated. It is possible that design <$design_name> may result in errors during validation."
-
diff --git a/src/fpga/bd/waveform_gen.tcl b/src/fpga/bd/waveform_gen.tcl
index ac9b77b2..8b6070f9 100644
--- a/src/fpga/bd/waveform_gen.tcl
+++ b/src/fpga/bd/waveform_gen.tcl
@@ -127,8 +127,8 @@ pavel-demin:user:axis_variable:1.0\
 xilinx.com:ip:dds_compiler:6.0\
 xilinx.com:ip:mult_gen:12.0\
 jbeuke:user:signal_generator:1.0\
+xilinx.com:ip:util_vector_logic:2.0\
 xilinx.com:ip:xlconcat:2.1\
-xilinx.com:ip:xlconstant:1.1\
 "
 
    set list_ips_missing ""
@@ -210,7 +210,7 @@ proc create_root_design { parentCell } {
   # Create instance: axis_variable_A_channel_1, and set properties
   set axis_variable_A_channel_1 [ create_bd_cell -type ip -vlnv pavel-demin:user:axis_variable:1.0 axis_variable_A_channel_1 ]
   set_property -dict [ list \
-   CONFIG.AXIS_TDATA_WIDTH {104} \
+   CONFIG.AXIS_TDATA_WIDTH {96} \
  ] $axis_variable_A_channel_1
 
   # Create instance: dds_compiler_A_channel_1, and set properties
@@ -220,6 +220,7 @@ proc create_root_design { parentCell } {
    CONFIG.DATA_Has_TLAST {Not_Required} \
    CONFIG.DDS_Clock_Rate {125} \
    CONFIG.Frequency_Resolution {4.440893e-7} \
+   CONFIG.Has_ACLKEN {false} \
    CONFIG.Has_ARESETn {true} \
    CONFIG.Has_Phase_Out {true} \
    CONFIG.Has_TREADY {false} \
@@ -235,11 +236,11 @@ proc create_root_design { parentCell } {
    CONFIG.POFF1 {0} \
    CONFIG.Parameter_Entry {System_Parameters} \
    CONFIG.PartsPresent {Phase_Generator_and_SIN_COS_LUT} \
-   CONFIG.Phase_Increment {Streaming} \
+   CONFIG.Phase_Increment {Programmable} \
    CONFIG.Phase_Offset_Angles1 {0} \
    CONFIG.Phase_Width {48} \
-   CONFIG.Phase_offset {Streaming} \
-   CONFIG.Resync {true} \
+   CONFIG.Phase_offset {Programmable} \
+   CONFIG.Resync {false} \
    CONFIG.S_PHASE_Has_TUSER {Not_Required} \
    CONFIG.Spurious_Free_Dynamic_Range {84} \
  ] $dds_compiler_A_channel_1
@@ -264,8 +265,19 @@ proc create_root_design { parentCell } {
    CONFIG.CFG_DATA_WIDTH {48} \
  ] $signal_generator_0
 
-  # Create instance: xlconcat_0, and set properties
-  set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ]
+  # Create instance: util_vector_logic_0, and set properties
+  set util_vector_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_0 ]
+  set_property -dict [ list \
+   CONFIG.C_OPERATION {not} \
+   CONFIG.C_SIZE {1} \
+   CONFIG.LOGO_FILE {data/sym_notgate.png} \
+ ] $util_vector_logic_0
+
+  # Create instance: util_vector_logic_1, and set properties
+  set util_vector_logic_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_1 ]
+  set_property -dict [ list \
+   CONFIG.C_SIZE {1} \
+ ] $util_vector_logic_1
 
   # Create instance: xlconcat_A_channel_1, and set properties
   set xlconcat_A_channel_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_A_channel_1 ]
@@ -273,35 +285,28 @@ proc create_root_design { parentCell } {
    CONFIG.IN0_WIDTH {48} \
    CONFIG.IN1_WIDTH {48} \
    CONFIG.IN2_WIDTH {8} \
-   CONFIG.NUM_PORTS {3} \
+   CONFIG.NUM_PORTS {2} \
  ] $xlconcat_A_channel_1
 
-  # Create instance: xlconstant_0, and set properties
-  set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
-  set_property -dict [ list \
-   CONFIG.CONST_VAL {0} \
-   CONFIG.CONST_WIDTH {7} \
- ] $xlconstant_0
-
   # Create interface connections
-  connect_bd_intf_net -intf_net axis_variable_A_channel_1_M_AXIS [get_bd_intf_pins axis_variable_A_channel_1/M_AXIS] [get_bd_intf_pins dds_compiler_A_channel_1/S_AXIS_PHASE]
+  connect_bd_intf_net -intf_net axis_variable_A_channel_1_M_AXIS [get_bd_intf_pins axis_variable_A_channel_1/M_AXIS] [get_bd_intf_pins dds_compiler_A_channel_1/S_AXIS_CONFIG]
   connect_bd_intf_net -intf_net dds_compiler_A_channel_1_M_AXIS_DATA [get_bd_intf_pins dds_compiler_A_channel_1/M_AXIS_DATA] [get_bd_intf_pins signal_generator_0/s_axis]
   connect_bd_intf_net -intf_net dds_compiler_A_channel_1_M_AXIS_PHASE [get_bd_intf_pins dds_compiler_A_channel_1/M_AXIS_PHASE] [get_bd_intf_pins signal_generator_0/s_axis_phase]
 
   # Create port connections
   connect_bd_net -net amplitude_A_channel_1_slice1_Dout [get_bd_ports amplitude] [get_bd_pins mult_gen_0/A]
+  connect_bd_net -net aresetn_1 [get_bd_ports aresetn] [get_bd_pins axis_variable_A_channel_1/aresetn] [get_bd_pins signal_generator_0/aresetn] [get_bd_pins util_vector_logic_1/Op2]
   connect_bd_net -net clk_wiz_0_clk_internal [get_bd_ports aclk] [get_bd_pins axis_variable_A_channel_1/aclk] [get_bd_pins dds_compiler_A_channel_1/aclk] [get_bd_pins mult_gen_0/CLK] [get_bd_pins signal_generator_0/clk]
   connect_bd_net -net freq_1 [get_bd_ports freq] [get_bd_pins xlconcat_A_channel_1/In0]
   connect_bd_net -net mult_gen_0_P [get_bd_ports wave] [get_bd_pins mult_gen_0/P]
   connect_bd_net -net phase_1 [get_bd_ports phase] [get_bd_pins xlconcat_A_channel_1/In1]
   connect_bd_net -net phase_A_channel_1_slice1_Dout [get_bd_ports cfg_data] [get_bd_pins signal_generator_0/cfg_data]
-  connect_bd_net -net resync_1 [get_bd_ports resync] [get_bd_pins xlconcat_0/In0]
-  connect_bd_net -net rst_ps7_0_125M_peripheral_aresetn [get_bd_ports aresetn] [get_bd_pins axis_variable_A_channel_1/aresetn] [get_bd_pins dds_compiler_A_channel_1/aresetn] [get_bd_pins signal_generator_0/aresetn]
+  connect_bd_net -net resync_1 [get_bd_ports resync] [get_bd_pins util_vector_logic_0/Op1]
   connect_bd_net -net signal_generator_0_m_axis_tdata [get_bd_pins mult_gen_0/B] [get_bd_pins signal_generator_0/m_axis_tdata]
   connect_bd_net -net signal_generator_0_m_axis_tvalid [get_bd_ports m_axis_data_tvalid_1] [get_bd_pins signal_generator_0/m_axis_tvalid]
-  connect_bd_net -net xlconcat_0_dout [get_bd_pins xlconcat_0/dout] [get_bd_pins xlconcat_A_channel_1/In2]
+  connect_bd_net -net util_vector_logic_0_Res [get_bd_pins util_vector_logic_0/Res] [get_bd_pins util_vector_logic_1/Op1]
+  connect_bd_net -net util_vector_logic_1_Res [get_bd_pins dds_compiler_A_channel_1/aresetn] [get_bd_pins util_vector_logic_1/Res]
   connect_bd_net -net xlconcat_A_channel_1_dout [get_bd_pins axis_variable_A_channel_1/cfg_data] [get_bd_pins xlconcat_A_channel_1/dout]
-  connect_bd_net -net xlconstant_0_dout [get_bd_pins xlconcat_0/In1] [get_bd_pins xlconstant_0/dout]
 
   # Create address segments
 
diff --git a/src/lib/rp-daq-lib.c b/src/lib/rp-daq-lib.c
index 37f26941..0d555380 100644
--- a/src/lib/rp-daq-lib.c
+++ b/src/lib/rp-daq-lib.c
@@ -653,8 +653,8 @@ int setResyncDAC(int8_t value, int channel, int index) {
 		return -1;
 
 	int bitpos = 14 + channel;
-	// Reset bit is in the 2-th channel
-	int offset = 8 * index + 2;
+	// Reset bits are in the 2nd channel -> bitpos 31:30
+	int offset = 8 * index + 1;
 	// clear the bit
 	*((int16_t *)(pdm_cfg + offset)) &= ~(1u << bitpos);
 	// set the bit
@@ -1306,6 +1306,7 @@ void stopTx() {
 	for(int d=0; d<5; d++) {
 		setPDMAllValuesVolt(0.0, d);
 		setEnableDACAll(1,d);
+		setResyncDACAll(0,d);
 	}
 }
 
diff --git a/src/server/control.c b/src/server/control.c
index 0ec9b880..64c7abc8 100644
--- a/src/server/control.c
+++ b/src/server/control.c
@@ -102,9 +102,11 @@ void clearSequence() {
 	setPDMAllValuesVolt(0.0, 2);
 	setPDMAllValuesVolt(0.0, 3);
 
-	for(int d=0; d<4; d++) {
+    for(int d=0; d<6; d++) {
 		setEnableDACAll(1,d);
-	}
+    	setResyncDACAll(0,d);
+    }
+
 }
 
 bool isSequenceConfigurable() {

From 45d19c13ddb9268c8ae66b48e25c8cc1342b8b67 Mon Sep 17 00:00:00 2001
From: Tobias Knopp <tobias.knopp@tuhh.de>
Date: Thu, 26 Sep 2024 07:17:33 +0200
Subject: [PATCH 07/38] fix multi-channel resync issues

---
 src/server/control.c       | 3 ++-
 src/server/scpi_commands.c | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/server/control.c b/src/server/control.c
index 64c7abc8..bfd08aed 100644
--- a/src/server/control.c
+++ b/src/server/control.c
@@ -129,9 +129,10 @@ bool getSequenceEnableValue(sequenceData_t *seqData, int seqStep, int channel) {
 
 bool getSequenceResyncValue(sequenceData_t *seqData, int seqStep, int channel) {
 	bool result = false;
+  int numChan = numSlowDACChan > 2 ? 2 : numSlowDACChan;
 	if (seqData->resyncLUT != NULL) {
 		int localStep = seqStep % seqData->numStepsPerRepetition;
-		result = seqData->resyncLUT[localStep + channel];
+		result = seqData->resyncLUT[localStep * numChan + channel];
 	}
 	return result;
 }
diff --git a/src/server/scpi_commands.c b/src/server/scpi_commands.c
index 6025297e..b7308745 100644
--- a/src/server/scpi_commands.c
+++ b/src/server/scpi_commands.c
@@ -1070,7 +1070,7 @@ static scpi_result_t RP_DAC_SetResyncLUT(scpi_t * context) {
 		printf("Allocating ressyncLUT\n");
 		configSeq->resyncLUT = (bool *)calloc(numChan, configSeq->numStepsPerRepetition * sizeof(bool));
 
-		int n = readAll(newdatasockfd, configSeq->resyncLUT, numSlowDACChan * configSeq->numStepsPerRepetition * sizeof(bool));
+		int n = readAll(newdatasockfd, configSeq->resyncLUT, numChan * configSeq->numStepsPerRepetition * sizeof(bool));
 		seqState = CONFIG;
 		if (n < 0) perror("ERROR reading from socket");
 		return returnSCPIBool(context, true);

From cdb0ae9e8a21654a4c6fc5f7cbe971daa36779f1 Mon Sep 17 00:00:00 2001
From: rp_local <n.a>
Date: Thu, 26 Sep 2024 09:23:01 +0000
Subject: [PATCH 08/38] Move resync flag to bit 14 of each DAC channel

---
 src/fpga/hdl/sequence_slice.v | 5 +++--
 src/lib/rp-daq-lib.c          | 6 +++---
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/src/fpga/hdl/sequence_slice.v b/src/fpga/hdl/sequence_slice.v
index ab2e91a5..3ffc5840 100644
--- a/src/fpga/hdl/sequence_slice.v
+++ b/src/fpga/hdl/sequence_slice.v
@@ -42,8 +42,9 @@ assign pdm_value_3[10:0] = seq_data_int[90:80];
 // Flags
 assign enable_dac[1:0] = seq_data_int[97:96];
 assign enable_pdm[3:0] = seq_data_int[101:98];
-assign resync_dac[1:0] = seq_data_int[31:30];
+assign resync_dac[0] = seq_data_int[14];
+assign resync_dac[1] = seq_data_int[30];
 assign enable_dac_ramp_down[0] = seq_data_int[112];
 assign enable_dac_ramp_down[1] = seq_data_int[113];
 
-endmodule
+endmodule
\ No newline at end of file
diff --git a/src/lib/rp-daq-lib.c b/src/lib/rp-daq-lib.c
index 0d555380..fe6eff16 100644
--- a/src/lib/rp-daq-lib.c
+++ b/src/lib/rp-daq-lib.c
@@ -652,9 +652,9 @@ int setResyncDAC(int8_t value, int channel, int index) {
 	if (value < 0 || value >= 2)
 		return -1;
 
-	int bitpos = 14 + channel;
-	// Reset bits are in the 2nd channel -> bitpos 31:30
-	int offset = 8 * index + 1;
+	int bitpos = 14;
+	// Reset bits are in the 14th bit of the respective DAC channel -> 14 and 30 
+	int offset = 8 * index + channel;
 	// clear the bit
 	*((int16_t *)(pdm_cfg + offset)) &= ~(1u << bitpos);
 	// set the bit

From 823c37e6624f212d832b1184ef0433d5d783bf33 Mon Sep 17 00:00:00 2001
From: rp_local <n.a>
Date: Thu, 26 Sep 2024 09:23:34 +0000
Subject: [PATCH 09/38] Restrict getSequenceResyncValue to DAC channel

---
 src/server/control.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/server/control.c b/src/server/control.c
index bfd08aed..3e662510 100644
--- a/src/server/control.c
+++ b/src/server/control.c
@@ -129,8 +129,8 @@ bool getSequenceEnableValue(sequenceData_t *seqData, int seqStep, int channel) {
 
 bool getSequenceResyncValue(sequenceData_t *seqData, int seqStep, int channel) {
 	bool result = false;
-  int numChan = numSlowDACChan > 2 ? 2 : numSlowDACChan;
-	if (seqData->resyncLUT != NULL) {
+  	int numChan = numSlowDACChan > 2 ? 2 : numSlowDACChan;
+	if (seqData->resyncLUT != NULL && channel < numChan) {
 		int localStep = seqStep % seqData->numStepsPerRepetition;
 		result = seqData->resyncLUT[localStep * numChan + channel];
 	}
@@ -215,6 +215,7 @@ static void setLUTValuesFor(int futureStep, int channel, int currPDMIndex) {
 	if (activeSequence == NULL) {
 		setPDMValueVolt(0.0, channel, currPDMIndex);
 		setEnableDAC(false, channel, currPDMIndex);
+		setResyncDAC(false, channel, currPDMIndex);
 		setRampDownDAC(false, channel, currPDMIndex);
 		return;
 	}

From b79123c0d24e173321b1cab3ca144b0c3ff86d51 Mon Sep 17 00:00:00 2001
From: rp_local <n.a>
Date: Fri, 29 Nov 2024 13:07:08 +0000
Subject: [PATCH 10/38] Init test of step counting with writepointer lowest bit

---
 src/fpga/hdl/sequence_stepper.v | 41 ++++++++++++++++++++-------------
 1 file changed, 25 insertions(+), 16 deletions(-)

diff --git a/src/fpga/hdl/sequence_stepper.v b/src/fpga/hdl/sequence_stepper.v
index 9a28dd9a..25754421 100644
--- a/src/fpga/hdl/sequence_stepper.v
+++ b/src/fpga/hdl/sequence_stepper.v
@@ -1,36 +1,45 @@
 `timescale 1ns / 1ps
 
 module sequence_stepper(
-    input [63:0] writepointer,
+    input [63:0] writePointer,
     input [31:0] stepSize,
     input clk,
     input aresetn,
-    output [31:0] step_counter 
+    output [31:0] seq_counter
 );
 
-reg [63:0] end_of_step, next_end_of_step;
-reg [31:0] step_counter_reg, step_counter_next;
+reg [31:0] stepSize_int;
+reg [31:0] seq_counter_state;
+reg [31:0] sample_counter;
+reg wp_prev, wp_next;
 
 always @(posedge clk)
 begin
+    stepSize_int <= stepSize;
+    wp_next <= writePointer[0];
     if (~aresetn) begin
-        step_counter_reg <= 0;
-        step_counter_next <= 0;
-        end_of_step <= stepSize;
-        next_end_of_step <= stepSize;
+        seq_counter_state <= 0;
+        sample_counter <= stepSize_int;
+        wp_prev <= 0;
     end else begin
-        step_counter_reg <= step_counter_next;
-        end_of_step <= next_end_of_step;
-        if (end_of_step < writepointer) begin
-            next_end_of_step <= end_of_step + stepSize;
-            step_counter_next <= step_counter_reg + 1;
+        wp_prev <= wp_next;
+        if (wp_prev != wp_next) begin
+        
+            if (sample_counter == 0) begin
+                sample_counter <= stepSize_int;
+                seq_counter_state <= seq_counter_state + 1;
+            end else begin
+                sample_counter <= sample_counter - 1;
+                seq_counter_state <= seq_counter_state;
+            end
+        
         end else begin
-            next_end_of_step <= next_end_of_step;
-            step_counter_next <= step_counter_reg;
+            sample_counter <= sample_counter;
+            seq_counter_state <= seq_counter_state;
         end
     end
 end
 
-assign step_counter = step_counter_reg;
+assign seq_counter = seq_counter_state;
 
 endmodule

From 3bada952605943f4a7dfeb63b8732ed54d7c246a Mon Sep 17 00:00:00 2001
From: Tobias Knopp <tobias.knopp@tuhh.de>
Date: Sun, 1 Dec 2024 14:48:28 +0100
Subject: [PATCH 11/38] add sequenceIssue.jl

---
 src/examples/julia/sequenceIssue.jl | 60 +++++++++++++++++++++++++++++
 1 file changed, 60 insertions(+)
 create mode 100644 src/examples/julia/sequenceIssue.jl

diff --git a/src/examples/julia/sequenceIssue.jl b/src/examples/julia/sequenceIssue.jl
new file mode 100644
index 00000000..5d387cb8
--- /dev/null
+++ b/src/examples/julia/sequenceIssue.jl
@@ -0,0 +1,60 @@
+using RedPitayaDAQServer
+using CairoMakie
+
+# obtain the URL of the RedPitaya
+include("config.jl")
+
+rp = RedPitaya(URLs[1])
+serverMode!(rp, CONFIGURATION)
+
+
+dec = 128
+base_frequency = 125000000
+
+samples_per_step = 40 #30*16
+steps_per_frame = 4
+numSamples = steps_per_frame * samples_per_step
+
+decimation!(rp, dec)
+samplesPerPeriod!(rp, 1)
+periodsPerFrame!(rp, numSamples)
+samplesPerStep!(rp, samples_per_step)
+triggerMode!(rp, INTERNAL)
+
+
+amplitudeDAC!(rp, 1, 1, 0.0)
+amplitudeDAC!(rp, 2, 1, 0.0 )
+
+clearSequence!(rp)
+
+# Climbing offset for first channel, fixed offset for second channel
+seqChan!(rp, 6)
+lutB = collect(ones(steps_per_frame))
+lutB[1:2:end] .= 0.0
+lut = collect(cat(-lutB,-lutB*0.3, 0*lutB,0*lutB,0*lutB,0*lutB,dims=2)')
+#lut = collect(cat(-lutB,dims=2)')#,lutB,lutB,lutB,lutB,dims=2)')
+
+lutEnableDACA = ones(Bool, steps_per_frame)
+
+#enableLUT = collect( cat(lutEnableDACA,lutEnableDACA,lutEnableDACA,lutEnableDACA,lutEnableDACA,lutEnableDACA,dims=2)' )
+enableLUT = collect( cat(lutEnableDACA,lutEnableDACA,lutEnableDACA,lutEnableDACA,lutEnableDACA,lutEnableDACA,dims=2)' )
+#enableLUT = collect( cat(lutEnableDACA,dims=2)') #,lutEnableDACA,lutEnableDACA,lutEnableDACA,lutEnableDACA,dims=2)' )
+
+seq = SimpleSequence(lut, 300, enableLUT)
+sequence!(rp, seq)
+
+serverMode!(rp, ACQUISITION)
+masterTrigger!(rp, true)
+
+uCurrentPeriod = readFrames(rp, 1, 3)
+
+masterTrigger!(rp, false)
+serverMode!(rp, CONFIGURATION)
+
+plot = lines(vec(uCurrentPeriod[:,1,:,1]), label = "Rx1")
+lines!(plot.axis, vec(uCurrentPeriod[:,2,:,1]), label = "Rx2")
+lines!(plot.axis, vec(uCurrentPeriod[:,1,:,2]), label = "Rx1_2")
+lines!(plot.axis, vec(uCurrentPeriod[:,2,:,2]), label = "Rx2_2")
+axislegend(plot.axis)
+save(joinpath(@__DIR__(), "images", "sequenceIssue.png"), plot)
+plot
\ No newline at end of file

From f1130c45fc93992b4046f941dd88dee32ee45656 Mon Sep 17 00:00:00 2001
From: Tobias Knopp <tobias@knoppweb.de>
Date: Sun, 1 Dec 2024 17:38:51 +0100
Subject: [PATCH 12/38] fix sequence stepper issue

---
 src/fpga/bd/bd.tcl              |  9 +++----
 src/fpga/hdl/sequence_stepper.v | 42 +++++++++++++--------------------
 src/lib/rp-daq-lib.c            |  4 ++--
 3 files changed, 24 insertions(+), 31 deletions(-)

diff --git a/src/fpga/bd/bd.tcl b/src/fpga/bd/bd.tcl
index e9ae2bab..494b4cfb 100644
--- a/src/fpga/bd/bd.tcl
+++ b/src/fpga/bd/bd.tcl
@@ -2099,7 +2099,6 @@ proc create_hier_cell_sequencer { parentCell nameHier } {
 
   # Create pins
   create_bd_pin -dir I -type clk aclk
-  create_bd_pin -dir I -from 63 -to 0 adc_sts
   create_bd_pin -dir I -type rst aresetn
   create_bd_pin -dir I bram_aresetn
   create_bd_pin -dir I -from 31 -to 0 cfg_data
@@ -2220,6 +2219,9 @@ proc create_hier_cell_sequencer { parentCell nameHier } {
   # Create instance: xlconstant_0, and set properties
   set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
 
+  # Create instance: xlslice_0, and set properties
+  set xlslice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 ]
+
   # Create instance: zero_constant, and set properties
   set zero_constant [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 zero_constant ]
   set_property -dict [ list \
@@ -2240,7 +2242,6 @@ proc create_hier_cell_sequencer { parentCell nameHier } {
 
   # Create port connections
   connect_bd_net -net aclk_1 [get_bd_pins aclk] [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins blk_mem_gen_0/clkb] [get_bd_pins sequence_slice_0/clk] [get_bd_pins sequence_stepper_0/clk]
-  connect_bd_net -net adc_sts_1 [get_bd_pins adc_sts] [get_bd_pins sequence_stepper_0/writepointer]
   connect_bd_net -net aresetn3_1 [get_bd_pins keep_alive_aresetn] [get_bd_pins util_vector_logic_0/Op2]
   connect_bd_net -net blk_mem_gen_0_doutb [get_bd_pins blk_mem_gen_0/doutb] [get_bd_pins sequence_slice_0/seq_data]
   connect_bd_net -net bram_aresetn_1 [get_bd_pins bram_aresetn] [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn]
@@ -2267,7 +2268,7 @@ proc create_hier_cell_sequencer { parentCell nameHier } {
   connect_bd_net -net xlconcat_0_dout [get_bd_pins util_vector_logic_7/Op1] [get_bd_pins xlconcat_0/dout]
   connect_bd_net -net xlconcat_1_dout [get_bd_pins oa_dac] [get_bd_pins xlconcat_1/dout]
   connect_bd_net -net xlconstant_0_dout [get_bd_pins blk_mem_gen_0/enb] [get_bd_pins xlconstant_0/dout]
-  connect_bd_net -net xlslice_1_Dout [get_bd_pins pdm_sts] [get_bd_pins bram_element_slice/Din] [get_bd_pins sequence_stepper_0/step_counter]
+  connect_bd_net -net xlslice_1_Dout [get_bd_pins pdm_sts] [get_bd_pins bram_element_slice/Din] [get_bd_pins sequence_stepper_0/step_counter] [get_bd_pins xlslice_0/Din]
   connect_bd_net -net zero_constant1_dout [get_bd_pins concat_element_addr/In0] [get_bd_pins zero_constant1/dout]
   connect_bd_net -net zero_constant_dout [get_bd_pins concat_element_addr/In2] [get_bd_pins zero_constant/dout]
 
@@ -3436,7 +3437,7 @@ proc create_root_design { parentCell } {
   connect_bd_net -net util_vector_logic_0_Res [get_bd_pins clk_wiz_0/clk_in_sel] [get_bd_pins reset_manager_0/isMaster] [get_bd_pins util_vector_logic_0/Res]
   connect_bd_net -net write_to_ram_adc_out_A [get_bd_pins counter_trigger/adc0] [get_bd_pins write_to_ram/adc_out_A]
   connect_bd_net -net write_to_ram_adc_out_B [get_bd_pins counter_trigger/adc1] [get_bd_pins write_to_ram/adc_out_B]
-  connect_bd_net -net xlconcat_0_dout [get_bd_pins sequencer/adc_sts] [get_bd_pins system/adc_sts] [get_bd_pins write_to_ram/sts_data]
+  connect_bd_net -net xlconcat_0_dout [get_bd_pins system/adc_sts] [get_bd_pins write_to_ram/sts_data]
   connect_bd_net -net xlconcat_0_dout1 [get_bd_ports dac_pwm_o] [get_bd_pins sequencer/dout]
   connect_bd_net -net xlconcat_1_dout [get_bd_pins counter_trigger/counter_trigger_sts] [get_bd_pins system/counter_trigger_sts]
   connect_bd_net -net xlconstant_0_dout [get_bd_ports ext_DIO1_N] [get_bd_pins xlconstant_0/dout]
diff --git a/src/fpga/hdl/sequence_stepper.v b/src/fpga/hdl/sequence_stepper.v
index 25754421..2431364e 100644
--- a/src/fpga/hdl/sequence_stepper.v
+++ b/src/fpga/hdl/sequence_stepper.v
@@ -1,45 +1,37 @@
 `timescale 1ns / 1ps
 
 module sequence_stepper(
-    input [63:0] writePointer,
     input [31:0] stepSize,
     input clk,
     input aresetn,
-    output [31:0] seq_counter
+    output [31:0] step_counter 
 );
 
-reg [31:0] stepSize_int;
-reg [31:0] seq_counter_state;
-reg [31:0] sample_counter;
-reg wp_prev, wp_next;
+reg [63:0] step_counter_local, step_counter_local_next;
+reg [31:0] step_counter_reg, step_counter_next;
+reg [31:0] step_size_local;
 
 always @(posedge clk)
 begin
-    stepSize_int <= stepSize;
-    wp_next <= writePointer[0];
     if (~aresetn) begin
-        seq_counter_state <= 0;
-        sample_counter <= stepSize_int;
-        wp_prev <= 0;
+        step_counter_reg <= 0;
+        step_counter_next <= 0;
+        step_counter_local <= 0;
+        step_counter_local_next <= 0;
+        step_size_local <= stepSize-1;
     end else begin
-        wp_prev <= wp_next;
-        if (wp_prev != wp_next) begin
-        
-            if (sample_counter == 0) begin
-                sample_counter <= stepSize_int;
-                seq_counter_state <= seq_counter_state + 1;
-            end else begin
-                sample_counter <= sample_counter - 1;
-                seq_counter_state <= seq_counter_state;
-            end
-        
+        step_counter_reg <= step_counter_next;
+        step_counter_local <= step_counter_local_next;
+        if (step_counter_local == step_size_local) begin
+            step_counter_local_next <= 0;
+            step_counter_next <= step_counter_reg + 1;
         end else begin
-            sample_counter <= sample_counter;
-            seq_counter_state <= seq_counter_state;
+            step_counter_local_next <= step_counter_local + 1;
+            step_counter_next <= step_counter_reg;
         end
     end
 end
 
-assign seq_counter = seq_counter_state;
+assign step_counter = step_counter_reg;
 
 endmodule
diff --git a/src/lib/rp-daq-lib.c b/src/lib/rp-daq-lib.c
index fe6eff16..2e3ecc12 100644
--- a/src/lib/rp-daq-lib.c
+++ b/src/lib/rp-daq-lib.c
@@ -777,11 +777,11 @@ int setPDMAllValuesVolt(float voltage, int channel) {
 
 int getSamplesPerStep() {
 	int32_t value = *((int32_t *)(cfg + 4));
-	return value;
+	return value*2/getDecimation();
 }
 
 int setSamplesPerStep(int samples) {
-	*((int32_t *)(cfg + 4)) = samples;
+	*((int32_t *)(cfg + 4)) = samples/2*getDecimation();
 	return 0;
 }
 

From d5e364e9230d7b101d87aeb5207cb4ba4d439ca9 Mon Sep 17 00:00:00 2001
From: Tobias Knopp <tobias@knoppweb.de>
Date: Fri, 6 Dec 2024 14:53:27 +0100
Subject: [PATCH 13/38] first version of hbridge

---
 src/client/julia/src/SlowIO.jl      |  40 +++
 src/examples/julia/config.jl        |   2 +
 src/examples/julia/sequenceIssue.jl |  17 +-
 src/fpga/bd/bd.tcl                  | 404 ++++++++++++++++++++++------
 src/fpga/bd/hbridgewaveform.tcl     | 357 ++++++++++++++++++++++++
 src/fpga/build.tcl                  |   1 +
 src/fpga/hdl/hbridge_signalgen.v    |  82 ++++++
 7 files changed, 817 insertions(+), 86 deletions(-)
 create mode 100644 src/fpga/bd/hbridgewaveform.tcl
 create mode 100644 src/fpga/hdl/hbridge_signalgen.v

diff --git a/src/client/julia/src/SlowIO.jl b/src/client/julia/src/SlowIO.jl
index f3c80011..26fcd3f4 100644
--- a/src/client/julia/src/SlowIO.jl
+++ b/src/client/julia/src/SlowIO.jl
@@ -182,3 +182,43 @@ end
 scpiCommand(::typeof(DIO), pin) = string("RP:DIO:", DIOPinToCommand(pin), "?")
 scpiReturn(::typeof(DIO)) = String
 parseReturn(::typeof(DIO), ret) = occursin("ON", ret)
+
+
+
+
+
+
+export DIOHBridge!
+"""
+DIOHBridge!(rp::RedPitaya, pin::DIOPins, val::Bool)
+
+Set the value of DIOHBridge pin `pin` to the value `val`.
+# Example
+```julia
+julia> DIOHBridge!(rp, DIO7_P, true)
+true
+```
+"""
+function DIOHBridge!(rp::RedPitaya, pin, val)
+  return query(rp, scpiCommand(DIOHBridge!, pin, val), scpiReturn(DIOHBridge!))
+end
+scpiCommand(::typeof(DIOHBridge!), pin::DIOPins, val::Bool) = string("RP:DIO:", DIOPinToCommand(pin), ":HBRIDGE ", (val ? "ON" : "OFF"))
+scpiReturn(::typeof(DIOHBridge!)) = Bool
+
+export DIOHBridge
+"""
+  DIOHBridge(rp::RedPitaya, pin::DIOPins)
+
+Get the value of DIOHBridge pin `pin`.
+# Example
+```julia
+julia>DIOHBridge(rp, DIO7_P)
+true
+```
+"""
+function DIOHBridge(rp::RedPitaya, pin)
+  return parseReturn(DIOHBridge, query(rp, scpiCommand(DIOHBridge, pin), scpiReturn(DIOHBridge)))
+end
+scpiCommand(::typeof(DIOHBridge), pin) = string("RP:DIO:", DIOPinToCommand(pin), ":HBRIDGE?")
+scpiReturn(::typeof(DIOHBridge)) = String
+parseReturn(::typeof(DIOHBridge), ret) = occursin("ON", ret)
\ No newline at end of file
diff --git a/src/examples/julia/config.jl b/src/examples/julia/config.jl
index 5ec9b3a0..8d5f511a 100644
--- a/src/examples/julia/config.jl
+++ b/src/examples/julia/config.jl
@@ -1,3 +1,5 @@
 # URLs= ["rp-f08ccb.local", "rp-f08caa.local"]
 URLs= ["192.168.2.22"]#, "192.168.2.17"]
+URLs= ["192.168.178.65"]#, "192.168.178.95"]
+
 mkpath("images")
\ No newline at end of file
diff --git a/src/examples/julia/sequenceIssue.jl b/src/examples/julia/sequenceIssue.jl
index 5d387cb8..021d2a1a 100644
--- a/src/examples/julia/sequenceIssue.jl
+++ b/src/examples/julia/sequenceIssue.jl
@@ -11,7 +11,7 @@ serverMode!(rp, CONFIGURATION)
 dec = 128
 base_frequency = 125000000
 
-samples_per_step = 40 #30*16
+samples_per_step = 4000 #30*16
 steps_per_frame = 4
 numSamples = steps_per_frame * samples_per_step
 
@@ -21,9 +21,10 @@ periodsPerFrame!(rp, numSamples)
 samplesPerStep!(rp, samples_per_step)
 triggerMode!(rp, INTERNAL)
 
-
-amplitudeDAC!(rp, 1, 1, 0.0)
-amplitudeDAC!(rp, 2, 1, 0.0 )
+frequencyDAC!(rp, 1, 1, base_frequency/samples_per_step/dec)
+frequencyDAC!(rp, 2, 1, base_frequency/samples_per_step/dec)
+amplitudeDAC!(rp, 1, 1, 0.2)
+amplitudeDAC!(rp, 2, 1, 0.2 )
 
 clearSequence!(rp)
 
@@ -40,21 +41,21 @@ lutEnableDACA = ones(Bool, steps_per_frame)
 enableLUT = collect( cat(lutEnableDACA,lutEnableDACA,lutEnableDACA,lutEnableDACA,lutEnableDACA,lutEnableDACA,dims=2)' )
 #enableLUT = collect( cat(lutEnableDACA,dims=2)') #,lutEnableDACA,lutEnableDACA,lutEnableDACA,lutEnableDACA,dims=2)' )
 
-seq = SimpleSequence(lut, 300, enableLUT)
+seq = SimpleSequence(lut, 2, enableLUT)
 sequence!(rp, seq)
 
 serverMode!(rp, ACQUISITION)
 masterTrigger!(rp, true)
 
-uCurrentPeriod = readFrames(rp, 1, 3)
+uCurrentPeriod = readFrames(rp, 1, 200)
 
 masterTrigger!(rp, false)
 serverMode!(rp, CONFIGURATION)
 
 plot = lines(vec(uCurrentPeriod[:,1,:,1]), label = "Rx1")
 lines!(plot.axis, vec(uCurrentPeriod[:,2,:,1]), label = "Rx2")
-lines!(plot.axis, vec(uCurrentPeriod[:,1,:,2]), label = "Rx1_2")
-lines!(plot.axis, vec(uCurrentPeriod[:,2,:,2]), label = "Rx2_2")
+#lines!(plot.axis, vec(uCurrentPeriod[:,1,:,2]), label = "Rx1_2")
+#lines!(plot.axis, vec(uCurrentPeriod[:,2,:,2]), label = "Rx2_2")
 axislegend(plot.axis)
 save(joinpath(@__DIR__(), "images", "sequenceIssue.png"), plot)
 plot
\ No newline at end of file
diff --git a/src/fpga/bd/bd.tcl b/src/fpga/bd/bd.tcl
index 494b4cfb..9576f109 100644
--- a/src/fpga/bd/bd.tcl
+++ b/src/fpga/bd/bd.tcl
@@ -47,7 +47,7 @@ if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
 
 # The design that will be created by this Tcl script contains the following 
 # block design container source references:
-# signal_calib, signal_ramp, waveform_gen
+# hbridgewaveform, signal_calib, signal_ramp, waveform_gen
 
 # Please add the sources before sourcing this Tcl script.
 
@@ -227,7 +227,7 @@ wave_awg_composer\
 # CHECK Block Design Container Sources
 ##################################################################
 set bCheckSources 1
-set list_bdc_active "signal_calib, signal_ramp, waveform_gen"
+set list_bdc_active "hbridgewaveform, signal_calib, signal_ramp, waveform_gen"
 
 array set map_bdc_missing {}
 set map_bdc_missing(ACTIVE) ""
@@ -235,6 +235,7 @@ set map_bdc_missing(BDC) ""
 
 if { $bCheckSources == 1 } {
    set list_check_srcs "\ 
+hbridgewaveform \
 signal_calib \
 signal_ramp \
 waveform_gen \
@@ -885,16 +886,8 @@ proc create_hier_cell_signal_compose1 { parentCell nameHier } {
    CONFIG.LOCK_PROPAGATE {0} \
  ] $waveform_gen_2
 
-  # Create instance: waveform_gen_3, and set properties
-  set waveform_gen_3 [ create_bd_cell -type container -reference waveform_gen waveform_gen_3 ]
-  set_property -dict [ list \
-   CONFIG.ACTIVE_SIM_BD {waveform_gen.bd} \
-   CONFIG.ACTIVE_SYNTH_BD {waveform_gen.bd} \
-   CONFIG.ENABLE_DFX {0} \
-   CONFIG.LIST_SIM_BD {waveform_gen.bd} \
-   CONFIG.LIST_SYNTH_BD {waveform_gen.bd} \
-   CONFIG.LOCK_PROPAGATE {0} \
- ] $waveform_gen_3
+  # Create instance: xlconstant_0, and set properties
+  set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
 
   # Create interface connections
   connect_bd_intf_net -intf_net awg_bram_1 [get_bd_intf_pins awg_bram] [get_bd_intf_pins waveform_awg1/S_AXI]
@@ -902,12 +895,12 @@ proc create_hier_cell_signal_compose1 { parentCell nameHier } {
   # Create port connections
   connect_bd_net -net Din_1 [get_bd_pins Din] [get_bd_pins signal_cfg_slice_0/cfg_data]
   connect_bd_net -net bram_aresetn_1 [get_bd_pins bram_aresetn] [get_bd_pins waveform_awg1/bram_aresetn]
-  connect_bd_net -net clk_wiz_0_clk_internal [get_bd_pins aclk] [get_bd_pins signal_calib_0/aclk] [get_bd_pins signal_composer_0/clk] [get_bd_pins signal_ramp_0/aclk] [get_bd_pins waveform_awg1/aclk] [get_bd_pins waveform_gen_0/aclk] [get_bd_pins waveform_gen_1/aclk] [get_bd_pins waveform_gen_2/aclk] [get_bd_pins waveform_gen_3/aclk]
+  connect_bd_net -net clk_wiz_0_clk_internal [get_bd_pins aclk] [get_bd_pins signal_calib_0/aclk] [get_bd_pins signal_composer_0/clk] [get_bd_pins signal_ramp_0/aclk] [get_bd_pins waveform_awg1/aclk] [get_bd_pins waveform_gen_0/aclk] [get_bd_pins waveform_gen_1/aclk] [get_bd_pins waveform_gen_2/aclk]
   connect_bd_net -net disable_dac_1 [get_bd_pins disable_dac] [get_bd_pins signal_composer_0/disable_dac]
   connect_bd_net -net enable_ramping_1 [get_bd_pins enable_ramping] [get_bd_pins signal_ramp_0/enableRamping]
   connect_bd_net -net offset_1 [get_bd_pins offset] [get_bd_pins signal_composer_0/seq]
-  connect_bd_net -net resync_dac_1 [get_bd_pins resync_dac] [get_bd_pins waveform_gen_0/resync] [get_bd_pins waveform_gen_1/resync] [get_bd_pins waveform_gen_2/resync] [get_bd_pins waveform_gen_3/resync]
-  connect_bd_net -net rst_ps7_0_125M_peripheral_aresetn [get_bd_pins aresetn] [get_bd_pins signal_ramp_0/aresetn] [get_bd_pins waveform_awg1/aresetn] [get_bd_pins waveform_gen_0/aresetn] [get_bd_pins waveform_gen_1/aresetn] [get_bd_pins waveform_gen_2/aresetn] [get_bd_pins waveform_gen_3/aresetn]
+  connect_bd_net -net resync_dac_1 [get_bd_pins resync_dac] [get_bd_pins waveform_gen_0/resync] [get_bd_pins waveform_gen_1/resync] [get_bd_pins waveform_gen_2/resync]
+  connect_bd_net -net rst_ps7_0_125M_peripheral_aresetn [get_bd_pins aresetn] [get_bd_pins signal_ramp_0/aresetn] [get_bd_pins waveform_awg1/aresetn] [get_bd_pins waveform_gen_0/aresetn] [get_bd_pins waveform_gen_1/aresetn] [get_bd_pins waveform_gen_2/aresetn]
   connect_bd_net -net signal_calib_0_signal_out [get_bd_pins S] [get_bd_pins signal_calib_0/signal_out]
   connect_bd_net -net signal_cfg_slice_0_calib_limit_lower [get_bd_pins signal_cfg_slice_0/calib_limit_lower]
   connect_bd_net -net signal_cfg_slice_0_calib_limit_upper [get_bd_pins signal_cfg_slice_0/calib_limit_upper]
@@ -925,10 +918,8 @@ proc create_hier_cell_signal_compose1 { parentCell nameHier } {
   connect_bd_net -net signal_cfg_slice_0_comp_2_cfg [get_bd_pins signal_cfg_slice_0/comp_2_cfg] [get_bd_pins waveform_gen_2/cfg_data]
   connect_bd_net -net signal_cfg_slice_0_comp_2_freq [get_bd_pins signal_cfg_slice_0/comp_2_freq] [get_bd_pins waveform_gen_2/freq]
   connect_bd_net -net signal_cfg_slice_0_comp_2_phase [get_bd_pins signal_cfg_slice_0/comp_2_phase] [get_bd_pins waveform_gen_2/phase]
-  connect_bd_net -net signal_cfg_slice_0_comp_3_amp [get_bd_pins signal_cfg_slice_0/comp_3_amp] [get_bd_pins waveform_gen_3/amplitude]
-  connect_bd_net -net signal_cfg_slice_0_comp_3_cfg [get_bd_pins signal_cfg_slice_0/comp_3_cfg] [get_bd_pins waveform_gen_3/cfg_data]
-  connect_bd_net -net signal_cfg_slice_0_comp_3_freq [get_bd_pins signal_cfg_slice_0/comp_3_freq] [get_bd_pins waveform_awg1/freq] [get_bd_pins waveform_gen_3/freq]
-  connect_bd_net -net signal_cfg_slice_0_comp_3_phase [get_bd_pins signal_cfg_slice_0/comp_3_phase] [get_bd_pins waveform_awg1/phase] [get_bd_pins waveform_gen_3/phase]
+  connect_bd_net -net signal_cfg_slice_0_comp_3_freq [get_bd_pins signal_cfg_slice_0/comp_3_freq] [get_bd_pins waveform_awg1/freq]
+  connect_bd_net -net signal_cfg_slice_0_comp_3_phase [get_bd_pins signal_cfg_slice_0/comp_3_phase] [get_bd_pins waveform_awg1/phase]
   connect_bd_net -net signal_cfg_slice_0_offset [get_bd_pins signal_cfg_slice_0/offset] [get_bd_pins signal_composer_0/offset]
   connect_bd_net -net signal_cfg_slice_0_ramp_freq [get_bd_pins signal_cfg_slice_0/ramp_freq] [get_bd_pins signal_ramp_0/freq]
   connect_bd_net -net signal_composer_0_signal_out [get_bd_pins signal_composer_0/signal_out] [get_bd_pins signal_ramp_0/signal_in]
@@ -943,7 +934,7 @@ proc create_hier_cell_signal_compose1 { parentCell nameHier } {
   connect_bd_net -net waveform_gen_1_wave [get_bd_pins signal_composer_0/wave1] [get_bd_pins waveform_gen_1/wave]
   connect_bd_net -net waveform_gen_2_m_axis_data_tvalid_1 [get_bd_pins signal_composer_0/valid2] [get_bd_pins waveform_gen_2/m_axis_data_tvalid_1]
   connect_bd_net -net waveform_gen_2_wave [get_bd_pins signal_composer_0/wave2] [get_bd_pins waveform_gen_2/wave]
-  connect_bd_net -net waveform_gen_3_m_axis_data_tvalid_1 [get_bd_pins signal_composer_0/valid3] [get_bd_pins waveform_gen_3/m_axis_data_tvalid_1]
+  connect_bd_net -net xlconstant_0_dout [get_bd_pins signal_composer_0/valid3] [get_bd_pins xlconstant_0/dout]
 
   # Restore current instance
   current_bd_instance $oldCurInst
@@ -1081,29 +1072,21 @@ proc create_hier_cell_signal_compose { parentCell nameHier } {
    CONFIG.LOCK_PROPAGATE {0} \
  ] $waveform_gen_2
 
-  # Create instance: waveform_gen_3, and set properties
-  set waveform_gen_3 [ create_bd_cell -type container -reference waveform_gen waveform_gen_3 ]
-  set_property -dict [ list \
-   CONFIG.ACTIVE_SIM_BD {waveform_gen.bd} \
-   CONFIG.ACTIVE_SYNTH_BD {waveform_gen.bd} \
-   CONFIG.ENABLE_DFX {0} \
-   CONFIG.LIST_SIM_BD {waveform_gen.bd} \
-   CONFIG.LIST_SYNTH_BD {waveform_gen.bd} \
-   CONFIG.LOCK_PROPAGATE {0} \
- ] $waveform_gen_3
+  # Create instance: xlconstant_0, and set properties
+  set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
 
   # Create interface connections
   connect_bd_intf_net -intf_net awg_bram_1 [get_bd_intf_pins awg_bram] [get_bd_intf_pins waveform_awg/S_AXI]
 
   # Create port connections
   connect_bd_net -net Din_1 [get_bd_pins Din] [get_bd_pins signal_cfg_slice_0/cfg_data]
-  connect_bd_net -net aclk_1 [get_bd_pins aclk] [get_bd_pins signal_calib_0/aclk] [get_bd_pins signal_composer_0/clk] [get_bd_pins signal_ramp/aclk] [get_bd_pins waveform_awg/aclk] [get_bd_pins waveform_gen_0/aclk] [get_bd_pins waveform_gen_1/aclk] [get_bd_pins waveform_gen_2/aclk] [get_bd_pins waveform_gen_3/aclk]
-  connect_bd_net -net aresetn_1 [get_bd_pins aresetn] [get_bd_pins signal_ramp/aresetn] [get_bd_pins waveform_awg/aresetn] [get_bd_pins waveform_gen_0/aresetn] [get_bd_pins waveform_gen_1/aresetn] [get_bd_pins waveform_gen_2/aresetn] [get_bd_pins waveform_gen_3/aresetn]
+  connect_bd_net -net aclk_1 [get_bd_pins aclk] [get_bd_pins signal_calib_0/aclk] [get_bd_pins signal_composer_0/clk] [get_bd_pins signal_ramp/aclk] [get_bd_pins waveform_awg/aclk] [get_bd_pins waveform_gen_0/aclk] [get_bd_pins waveform_gen_1/aclk] [get_bd_pins waveform_gen_2/aclk]
+  connect_bd_net -net aresetn_1 [get_bd_pins aresetn] [get_bd_pins signal_ramp/aresetn] [get_bd_pins waveform_awg/aresetn] [get_bd_pins waveform_gen_0/aresetn] [get_bd_pins waveform_gen_1/aresetn] [get_bd_pins waveform_gen_2/aresetn]
   connect_bd_net -net bram_aresetn_1 [get_bd_pins bram_aresetn] [get_bd_pins waveform_awg/bram_aresetn]
   connect_bd_net -net disable_dac_1 [get_bd_pins disable_dac] [get_bd_pins signal_composer_0/disable_dac]
   connect_bd_net -net offset_1 [get_bd_pins offset] [get_bd_pins signal_composer_0/seq]
   connect_bd_net -net ramping_enable_1 [get_bd_pins enable_ramping] [get_bd_pins signal_ramp/enableRamping]
-  connect_bd_net -net resync_dac_1 [get_bd_pins resync_dac] [get_bd_pins waveform_gen_0/resync] [get_bd_pins waveform_gen_1/resync] [get_bd_pins waveform_gen_2/resync] [get_bd_pins waveform_gen_3/resync]
+  connect_bd_net -net resync_dac_1 [get_bd_pins resync_dac] [get_bd_pins waveform_gen_0/resync] [get_bd_pins waveform_gen_1/resync] [get_bd_pins waveform_gen_2/resync]
   connect_bd_net -net signal_calib_0_signal_out [get_bd_pins S] [get_bd_pins signal_calib_0/signal_out]
   connect_bd_net -net signal_cfg_slice_0_calib_limit_lower [get_bd_pins signal_cfg_slice_0/calib_limit_lower]
   connect_bd_net -net signal_cfg_slice_0_calib_limit_upper [get_bd_pins signal_cfg_slice_0/calib_limit_upper]
@@ -1121,10 +1104,8 @@ proc create_hier_cell_signal_compose { parentCell nameHier } {
   connect_bd_net -net signal_cfg_slice_0_comp_2_cfg [get_bd_pins signal_cfg_slice_0/comp_2_cfg] [get_bd_pins waveform_gen_2/cfg_data]
   connect_bd_net -net signal_cfg_slice_0_comp_2_freq [get_bd_pins signal_cfg_slice_0/comp_2_freq] [get_bd_pins waveform_gen_2/freq]
   connect_bd_net -net signal_cfg_slice_0_comp_2_phase [get_bd_pins signal_cfg_slice_0/comp_2_phase] [get_bd_pins waveform_gen_2/phase]
-  connect_bd_net -net signal_cfg_slice_0_comp_3_amp [get_bd_pins signal_cfg_slice_0/comp_3_amp] [get_bd_pins waveform_gen_3/amplitude]
-  connect_bd_net -net signal_cfg_slice_0_comp_3_cfg [get_bd_pins signal_cfg_slice_0/comp_3_cfg] [get_bd_pins waveform_gen_3/cfg_data]
-  connect_bd_net -net signal_cfg_slice_0_comp_3_freq [get_bd_pins signal_cfg_slice_0/comp_3_freq] [get_bd_pins waveform_awg/freq] [get_bd_pins waveform_gen_3/freq]
-  connect_bd_net -net signal_cfg_slice_0_comp_3_phase [get_bd_pins signal_cfg_slice_0/comp_3_phase] [get_bd_pins waveform_awg/phase] [get_bd_pins waveform_gen_3/phase]
+  connect_bd_net -net signal_cfg_slice_0_comp_3_freq [get_bd_pins signal_cfg_slice_0/comp_3_freq] [get_bd_pins waveform_awg/freq]
+  connect_bd_net -net signal_cfg_slice_0_comp_3_phase [get_bd_pins signal_cfg_slice_0/comp_3_phase] [get_bd_pins waveform_awg/phase]
   connect_bd_net -net signal_cfg_slice_0_offset [get_bd_pins signal_cfg_slice_0/offset] [get_bd_pins signal_composer_0/offset]
   connect_bd_net -net signal_cfg_slice_0_ramp_freq [get_bd_pins signal_cfg_slice_0/ramp_freq] [get_bd_pins signal_ramp/freq]
   connect_bd_net -net signal_composer_0_signal_out [get_bd_pins signal_composer_0/signal_out] [get_bd_pins signal_ramp/signal_in]
@@ -1139,7 +1120,7 @@ proc create_hier_cell_signal_compose { parentCell nameHier } {
   connect_bd_net -net waveform_gen_1_wave [get_bd_pins signal_composer_0/wave1] [get_bd_pins waveform_gen_1/wave]
   connect_bd_net -net waveform_gen_2_m_axis_data_tvalid_1 [get_bd_pins signal_composer_0/valid2] [get_bd_pins waveform_gen_2/m_axis_data_tvalid_1]
   connect_bd_net -net waveform_gen_2_wave [get_bd_pins signal_composer_0/wave2] [get_bd_pins waveform_gen_2/wave]
-  connect_bd_net -net waveform_gen_3_m_axis_data_tvalid_1 [get_bd_pins signal_composer_0/valid3] [get_bd_pins waveform_gen_3/m_axis_data_tvalid_1]
+  connect_bd_net -net xlconstant_0_dout [get_bd_pins signal_composer_0/valid3] [get_bd_pins xlconstant_0/dout]
 
   # Restore current instance
   current_bd_instance $oldCurInst
@@ -2696,9 +2677,12 @@ proc create_hier_cell_DIO { parentCell nameHier } {
   # Create interface pins
 
   # Create pins
+  create_bd_pin -dir I aresetn
+  create_bd_pin -dir I -from 1663 -to 0 cfg_dac
   create_bd_pin -dir I -from 95 -to 0 cfg_in
   create_bd_pin -dir I -type clk clk
   create_bd_pin -dir O -from 31 -to 0 dio_data_clocked
+  create_bd_pin -dir I -from 1 -to 0 enable_dac
   create_bd_pin -dir IO ext_DIO2_N
   create_bd_pin -dir IO ext_DIO3_N
   create_bd_pin -dir IO ext_DIO4_N
@@ -2707,29 +2691,30 @@ proc create_hier_cell_DIO { parentCell nameHier } {
   create_bd_pin -dir IO ext_DIO6_P
   create_bd_pin -dir IO ext_DIO7_N
   create_bd_pin -dir IO ext_DIO7_P
+  create_bd_pin -dir I -from 1 -to 0 resync
+
+  # Create instance: hbridgewaveform_0, and set properties
+  set hbridgewaveform_0 [ create_bd_cell -type container -reference hbridgewaveform hbridgewaveform_0 ]
+  set_property -dict [ list \
+   CONFIG.ACTIVE_SIM_BD {hbridgewaveform.bd} \
+   CONFIG.ACTIVE_SYNTH_BD {hbridgewaveform.bd} \
+   CONFIG.ENABLE_DFX {0} \
+   CONFIG.LIST_SIM_BD {hbridgewaveform.bd} \
+   CONFIG.LIST_SYNTH_BD {hbridgewaveform.bd} \
+   CONFIG.LOCK_PROPAGATE {0} \
+ ] $hbridgewaveform_0
+
+  # Create instance: hbridgewaveform_1, and set properties
+  set hbridgewaveform_1 [ create_bd_cell -type container -reference hbridgewaveform hbridgewaveform_1 ]
+  set_property -dict [ list \
+   CONFIG.ACTIVE_SIM_BD {hbridgewaveform.bd} \
+   CONFIG.ACTIVE_SYNTH_BD {hbridgewaveform.bd} \
+   CONFIG.ENABLE_DFX {0} \
+   CONFIG.LIST_SIM_BD {hbridgewaveform.bd} \
+   CONFIG.LIST_SYNTH_BD {hbridgewaveform.bd} \
+   CONFIG.LOCK_PROPAGATE {0} \
+ ] $hbridgewaveform_1
 
-  # Create instance: rp_iobuf_0, and set properties
-  set block_name rp_iobuf
-  set block_cell_name rp_iobuf_0
-  if { [catch {set rp_iobuf_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
-     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
-     return 1
-   } elseif { $rp_iobuf_0 eq "" } {
-     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
-     return 1
-   }
-  
-  # Create instance: rp_iobuf_1, and set properties
-  set block_name rp_iobuf
-  set block_cell_name rp_iobuf_1
-  if { [catch {set rp_iobuf_1 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
-     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
-     return 1
-   } elseif { $rp_iobuf_1 eq "" } {
-     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
-     return 1
-   }
-  
   # Create instance: rp_iobuf_2, and set properties
   set block_name rp_iobuf
   set block_cell_name rp_iobuf_2
@@ -2796,6 +2781,92 @@ proc create_hier_cell_DIO { parentCell nameHier } {
      return 1
    }
   
+  # Create instance: rp_iobuf_8, and set properties
+  set block_name rp_iobuf
+  set block_cell_name rp_iobuf_8
+  if { [catch {set rp_iobuf_8 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   } elseif { $rp_iobuf_8 eq "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   }
+  
+  # Create instance: rp_iobuf_9, and set properties
+  set block_name rp_iobuf
+  set block_cell_name rp_iobuf_9
+  if { [catch {set rp_iobuf_9 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   } elseif { $rp_iobuf_9 eq "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   }
+  
+  # Create instance: util_vector_logic_0, and set properties
+  set util_vector_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_0 ]
+  set_property -dict [ list \
+   CONFIG.C_OPERATION {and} \
+   CONFIG.C_SIZE {1} \
+   CONFIG.LOGO_FILE {data/sym_andgate.png} \
+ ] $util_vector_logic_0
+
+  # Create instance: util_vector_logic_1, and set properties
+  set util_vector_logic_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_1 ]
+  set_property -dict [ list \
+   CONFIG.C_OPERATION {or} \
+   CONFIG.C_SIZE {1} \
+   CONFIG.LOGO_FILE {data/sym_orgate.png} \
+ ] $util_vector_logic_1
+
+  # Create instance: util_vector_logic_2, and set properties
+  set util_vector_logic_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_2 ]
+  set_property -dict [ list \
+   CONFIG.C_OPERATION {or} \
+   CONFIG.C_SIZE {1} \
+   CONFIG.LOGO_FILE {data/sym_orgate.png} \
+ ] $util_vector_logic_2
+
+  # Create instance: util_vector_logic_3, and set properties
+  set util_vector_logic_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_3 ]
+  set_property -dict [ list \
+   CONFIG.C_OPERATION {or} \
+   CONFIG.C_SIZE {1} \
+   CONFIG.LOGO_FILE {data/sym_orgate.png} \
+ ] $util_vector_logic_3
+
+  # Create instance: util_vector_logic_4, and set properties
+  set util_vector_logic_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_4 ]
+  set_property -dict [ list \
+   CONFIG.C_OPERATION {or} \
+   CONFIG.C_SIZE {1} \
+   CONFIG.LOGO_FILE {data/sym_orgate.png} \
+ ] $util_vector_logic_4
+
+  # Create instance: util_vector_logic_5, and set properties
+  set util_vector_logic_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_5 ]
+  set_property -dict [ list \
+   CONFIG.C_OPERATION {or} \
+   CONFIG.C_SIZE {1} \
+   CONFIG.LOGO_FILE {data/sym_orgate.png} \
+ ] $util_vector_logic_5
+
+  # Create instance: util_vector_logic_6, and set properties
+  set util_vector_logic_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_6 ]
+  set_property -dict [ list \
+   CONFIG.C_OPERATION {and} \
+   CONFIG.C_SIZE {1} \
+   CONFIG.LOGO_FILE {data/sym_andgate.png} \
+ ] $util_vector_logic_6
+
+  # Create instance: util_vector_logic_7, and set properties
+  set util_vector_logic_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_7 ]
+  set_property -dict [ list \
+   CONFIG.C_OPERATION {or} \
+   CONFIG.C_SIZE {1} \
+   CONFIG.LOGO_FILE {data/sym_orgate.png} \
+ ] $util_vector_logic_7
+
   # Create instance: xlconcat_0, and set properties
   set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ]
   set_property -dict [ list \
@@ -2965,6 +3036,150 @@ proc create_hier_cell_DIO { parentCell nameHier } {
    CONFIG.DOUT_WIDTH {1} \
  ] $xlslice_17
 
+  # Create instance: xlslice_18, and set properties
+  set xlslice_18 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_18 ]
+  set_property -dict [ list \
+   CONFIG.DIN_WIDTH {2} \
+ ] $xlslice_18
+
+  # Create instance: xlslice_19, and set properties
+  set xlslice_19 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_19 ]
+  set_property -dict [ list \
+   CONFIG.DIN_FROM {175} \
+   CONFIG.DIN_TO {128} \
+   CONFIG.DIN_WIDTH {832} \
+   CONFIG.DOUT_WIDTH {48} \
+ ] $xlslice_19
+
+  # Create instance: xlslice_20, and set properties
+  set xlslice_20 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_20 ]
+  set_property -dict [ list \
+   CONFIG.DIN_FROM {239} \
+   CONFIG.DIN_TO {192} \
+   CONFIG.DIN_WIDTH {832} \
+   CONFIG.DOUT_WIDTH {48} \
+ ] $xlslice_20
+
+  # Create instance: xlslice_21, and set properties
+  set xlslice_21 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_21 ]
+  set_property -dict [ list \
+   CONFIG.DIN_FROM {127} \
+   CONFIG.DIN_TO {112} \
+   CONFIG.DIN_WIDTH {832} \
+   CONFIG.DOUT_WIDTH {16} \
+ ] $xlslice_21
+
+  # Create instance: xlslice_22, and set properties
+  set xlslice_22 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_22 ]
+  set_property -dict [ list \
+   CONFIG.DIN_WIDTH {2} \
+ ] $xlslice_22
+
+  # Create instance: xlslice_23, and set properties
+  set xlslice_23 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_23 ]
+  set_property -dict [ list \
+   CONFIG.DIN_FROM {95} \
+   CONFIG.DIN_TO {88} \
+   CONFIG.DIN_WIDTH {96} \
+   CONFIG.DOUT_WIDTH {8} \
+ ] $xlslice_23
+
+  # Create instance: xlslice_24, and set properties
+  set xlslice_24 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_24 ]
+  set_property -dict [ list \
+   CONFIG.DIN_WIDTH {8} \
+ ] $xlslice_24
+
+  # Create instance: xlslice_25, and set properties
+  set xlslice_25 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_25 ]
+  set_property -dict [ list \
+   CONFIG.DIN_FROM {1} \
+   CONFIG.DIN_TO {1} \
+   CONFIG.DIN_WIDTH {8} \
+   CONFIG.DOUT_WIDTH {1} \
+ ] $xlslice_25
+
+  # Create instance: xlslice_26, and set properties
+  set xlslice_26 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_26 ]
+  set_property -dict [ list \
+   CONFIG.DIN_FROM {175} \
+   CONFIG.DIN_TO {128} \
+   CONFIG.DIN_WIDTH {832} \
+   CONFIG.DOUT_WIDTH {48} \
+ ] $xlslice_26
+
+  # Create instance: xlslice_27, and set properties
+  set xlslice_27 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_27 ]
+  set_property -dict [ list \
+   CONFIG.DIN_FROM {239} \
+   CONFIG.DIN_TO {192} \
+   CONFIG.DIN_WIDTH {832} \
+   CONFIG.DOUT_WIDTH {48} \
+ ] $xlslice_27
+
+  # Create instance: xlslice_28, and set properties
+  set xlslice_28 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_28 ]
+  set_property -dict [ list \
+   CONFIG.DIN_FROM {127} \
+   CONFIG.DIN_TO {112} \
+   CONFIG.DIN_WIDTH {832} \
+   CONFIG.DOUT_WIDTH {16} \
+ ] $xlslice_28
+
+  # Create instance: xlslice_29, and set properties
+  set xlslice_29 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_29 ]
+  set_property -dict [ list \
+   CONFIG.DIN_FROM {1} \
+   CONFIG.DIN_TO {1} \
+   CONFIG.DIN_WIDTH {2} \
+   CONFIG.DOUT_WIDTH {1} \
+ ] $xlslice_29
+
+  # Create instance: xlslice_30, and set properties
+  set xlslice_30 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_30 ]
+  set_property -dict [ list \
+   CONFIG.DIN_FROM {1663} \
+   CONFIG.DIN_TO {832} \
+   CONFIG.DIN_WIDTH {1664} \
+   CONFIG.DOUT_WIDTH {832} \
+ ] $xlslice_30
+
+  # Create instance: xlslice_31, and set properties
+  set xlslice_31 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_31 ]
+  set_property -dict [ list \
+   CONFIG.DIN_FROM {831} \
+   CONFIG.DIN_TO {0} \
+   CONFIG.DIN_WIDTH {1664} \
+   CONFIG.DOUT_WIDTH {832} \
+ ] $xlslice_31
+
+  # Create instance: xlslice_32, and set properties
+  set xlslice_32 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_32 ]
+  set_property -dict [ list \
+   CONFIG.DIN_FROM {1} \
+   CONFIG.DIN_TO {1} \
+   CONFIG.DIN_WIDTH {2} \
+   CONFIG.DOUT_WIDTH {1} \
+ ] $xlslice_32
+
+  # Create instance: xlslice_33, and set properties
+  set xlslice_33 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_33 ]
+  set_property -dict [ list \
+   CONFIG.DIN_FROM {2} \
+   CONFIG.DIN_TO {2} \
+   CONFIG.DIN_WIDTH {8} \
+   CONFIG.DOUT_WIDTH {1} \
+ ] $xlslice_33
+
+  # Create instance: xlslice_34, and set properties
+  set xlslice_34 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_34 ]
+  set_property -dict [ list \
+   CONFIG.DIN_FROM {3} \
+   CONFIG.DIN_TO {3} \
+   CONFIG.DIN_WIDTH {8} \
+   CONFIG.DOUT_WIDTH {1} \
+ ] $xlslice_34
+
   # Create port connections
   connect_bd_net -net Net [get_bd_pins ext_DIO6_P] [get_bd_pins rp_iobuf_2/val_tri]
   connect_bd_net -net Net1 [get_bd_pins ext_DIO6_N] [get_bd_pins rp_iobuf_3/val_tri]
@@ -2972,38 +3187,71 @@ proc create_hier_cell_DIO { parentCell nameHier } {
   connect_bd_net -net Net3 [get_bd_pins ext_DIO4_N] [get_bd_pins rp_iobuf_5/val_tri]
   connect_bd_net -net Net4 [get_bd_pins ext_DIO3_N] [get_bd_pins rp_iobuf_6/val_tri]
   connect_bd_net -net Net5 [get_bd_pins ext_DIO2_N] [get_bd_pins rp_iobuf_7/val_tri]
-  connect_bd_net -net Net6 [get_bd_pins ext_DIO7_P] [get_bd_pins rp_iobuf_0/val_tri]
-  connect_bd_net -net Net7 [get_bd_pins ext_DIO7_N] [get_bd_pins rp_iobuf_1/val_tri]
-  connect_bd_net -net clk_wiz_0_clk_internal [get_bd_pins clk] [get_bd_pins rp_iobuf_0/clk] [get_bd_pins rp_iobuf_1/clk] [get_bd_pins rp_iobuf_2/clk] [get_bd_pins rp_iobuf_3/clk] [get_bd_pins rp_iobuf_4/clk] [get_bd_pins rp_iobuf_5/clk] [get_bd_pins rp_iobuf_6/clk] [get_bd_pins rp_iobuf_7/clk]
-  connect_bd_net -net rp_iobuf_0_val_in_clocked [get_bd_pins rp_iobuf_0/val_in_clocked] [get_bd_pins xlconcat_0/In0]
-  connect_bd_net -net rp_iobuf_1_val_in_clocked [get_bd_pins rp_iobuf_1/val_in_clocked] [get_bd_pins xlconcat_0/In1]
+  connect_bd_net -net Net6 [get_bd_pins ext_DIO7_P] [get_bd_pins rp_iobuf_8/val_tri]
+  connect_bd_net -net Net7 [get_bd_pins ext_DIO7_N] [get_bd_pins rp_iobuf_9/val_tri]
+  connect_bd_net -net aresetn_1 [get_bd_pins aresetn] [get_bd_pins hbridgewaveform_0/aresetn] [get_bd_pins hbridgewaveform_1/aresetn]
+  connect_bd_net -net cfg_dac_1 [get_bd_pins cfg_dac] [get_bd_pins xlslice_30/Din] [get_bd_pins xlslice_31/Din]
+  connect_bd_net -net clk_wiz_0_clk_internal [get_bd_pins clk] [get_bd_pins hbridgewaveform_0/aclk] [get_bd_pins hbridgewaveform_1/aclk] [get_bd_pins rp_iobuf_2/clk] [get_bd_pins rp_iobuf_3/clk] [get_bd_pins rp_iobuf_4/clk] [get_bd_pins rp_iobuf_5/clk] [get_bd_pins rp_iobuf_6/clk] [get_bd_pins rp_iobuf_7/clk] [get_bd_pins rp_iobuf_8/clk] [get_bd_pins rp_iobuf_9/clk]
+  connect_bd_net -net enable_dac_1 [get_bd_pins enable_dac] [get_bd_pins xlslice_18/Din] [get_bd_pins xlslice_32/Din]
+  connect_bd_net -net enable_dac_2 [get_bd_pins hbridgewaveform_1/enable_dac] [get_bd_pins util_vector_logic_6/Res]
+  connect_bd_net -net hbridgewaveform_0_H1out [get_bd_pins hbridgewaveform_0/H1out] [get_bd_pins util_vector_logic_2/Op2]
+  connect_bd_net -net hbridgewaveform_0_H2out [get_bd_pins hbridgewaveform_0/H2out] [get_bd_pins util_vector_logic_3/Op2]
+  connect_bd_net -net hbridgewaveform_1_H1out [get_bd_pins hbridgewaveform_1/H1out] [get_bd_pins util_vector_logic_4/Op2]
+  connect_bd_net -net hbridgewaveform_1_H2out [get_bd_pins hbridgewaveform_1/H2out] [get_bd_pins util_vector_logic_5/Op2]
+  connect_bd_net -net resync_1 [get_bd_pins resync] [get_bd_pins xlslice_22/Din] [get_bd_pins xlslice_29/Din]
   connect_bd_net -net rp_iobuf_2_val_in_clocked [get_bd_pins rp_iobuf_2/val_in_clocked] [get_bd_pins xlconcat_0/In2]
   connect_bd_net -net rp_iobuf_3_val_in_clocked [get_bd_pins rp_iobuf_3/val_in_clocked] [get_bd_pins xlconcat_0/In3]
   connect_bd_net -net rp_iobuf_4_val_in_clocked [get_bd_pins rp_iobuf_4/val_in_clocked] [get_bd_pins xlconcat_0/In4]
   connect_bd_net -net rp_iobuf_5_val_in_clocked [get_bd_pins rp_iobuf_5/val_in_clocked] [get_bd_pins xlconcat_0/In5]
   connect_bd_net -net rp_iobuf_6_val_in_clocked [get_bd_pins rp_iobuf_6/val_in_clocked] [get_bd_pins xlconcat_0/In6]
   connect_bd_net -net rp_iobuf_7_val_in_clocked [get_bd_pins rp_iobuf_7/val_in_clocked] [get_bd_pins xlconcat_0/In7]
-  connect_bd_net -net system_cfg_data1 [get_bd_pins cfg_in] [get_bd_pins xlslice_4/Din] [get_bd_pins xlslice_5/Din]
+  connect_bd_net -net rp_iobuf_8_val_in_clocked [get_bd_pins rp_iobuf_8/val_in_clocked] [get_bd_pins xlconcat_0/In0]
+  connect_bd_net -net rp_iobuf_9_val_in_clocked [get_bd_pins rp_iobuf_9/val_in_clocked] [get_bd_pins xlconcat_0/In1]
+  connect_bd_net -net system_cfg_data1 [get_bd_pins cfg_in] [get_bd_pins xlslice_23/Din] [get_bd_pins xlslice_4/Din] [get_bd_pins xlslice_5/Din]
+  connect_bd_net -net util_vector_logic_0_Res [get_bd_pins hbridgewaveform_0/enable_dac] [get_bd_pins util_vector_logic_0/Res]
+  connect_bd_net -net util_vector_logic_1_Res [get_bd_pins util_vector_logic_0/Op1] [get_bd_pins util_vector_logic_1/Res]
+  connect_bd_net -net util_vector_logic_2_Res [get_bd_pins rp_iobuf_8/val_out] [get_bd_pins util_vector_logic_2/Res]
+  connect_bd_net -net util_vector_logic_3_Res [get_bd_pins rp_iobuf_9/val_out] [get_bd_pins util_vector_logic_3/Res]
+  connect_bd_net -net util_vector_logic_4_Res [get_bd_pins rp_iobuf_2/val_out] [get_bd_pins util_vector_logic_4/Res]
+  connect_bd_net -net util_vector_logic_5_Res [get_bd_pins rp_iobuf_3/val_out] [get_bd_pins util_vector_logic_5/Res]
+  connect_bd_net -net util_vector_logic_7_Res [get_bd_pins util_vector_logic_6/Op1] [get_bd_pins util_vector_logic_7/Res]
   connect_bd_net -net xlconcat_0_dout2 [get_bd_pins dio_data_clocked] [get_bd_pins xlconcat_0/dout]
   connect_bd_net -net xlconstant_1_dout [get_bd_pins xlconcat_0/In8] [get_bd_pins xlconstant_1/dout]
-  connect_bd_net -net xlslice_0_Dout [get_bd_pins rp_iobuf_0/val_out] [get_bd_pins xlslice_0/Dout]
-  connect_bd_net -net xlslice_10_Dout [get_bd_pins rp_iobuf_2/val_out] [get_bd_pins xlslice_10/Dout]
-  connect_bd_net -net xlslice_11_Dout [get_bd_pins rp_iobuf_3/val_out] [get_bd_pins xlslice_11/Dout]
+  connect_bd_net -net xlslice_0_Dout [get_bd_pins util_vector_logic_2/Op1] [get_bd_pins xlslice_0/Dout]
+  connect_bd_net -net xlslice_10_Dout [get_bd_pins util_vector_logic_4/Op1] [get_bd_pins xlslice_10/Dout]
+  connect_bd_net -net xlslice_11_Dout [get_bd_pins util_vector_logic_5/Op1] [get_bd_pins xlslice_11/Dout]
   connect_bd_net -net xlslice_12_Dout [get_bd_pins rp_iobuf_4/val_out] [get_bd_pins xlslice_12/Dout]
   connect_bd_net -net xlslice_13_Dout [get_bd_pins rp_iobuf_5/direction] [get_bd_pins xlslice_13/Dout]
   connect_bd_net -net xlslice_14_Dout [get_bd_pins rp_iobuf_6/direction] [get_bd_pins xlslice_14/Dout]
   connect_bd_net -net xlslice_15_Dout [get_bd_pins rp_iobuf_6/val_out] [get_bd_pins xlslice_15/Dout]
   connect_bd_net -net xlslice_16_Dout [get_bd_pins rp_iobuf_7/val_out] [get_bd_pins xlslice_16/Dout]
   connect_bd_net -net xlslice_17_Dout [get_bd_pins rp_iobuf_7/direction] [get_bd_pins xlslice_17/Dout]
+  connect_bd_net -net xlslice_18_Dout [get_bd_pins util_vector_logic_0/Op2] [get_bd_pins xlslice_18/Dout]
+  connect_bd_net -net xlslice_19_Dout [get_bd_pins hbridgewaveform_0/freq] [get_bd_pins xlslice_19/Dout]
   connect_bd_net -net xlslice_1_Dout [get_bd_pins rp_iobuf_2/direction] [get_bd_pins xlslice_1/Dout]
+  connect_bd_net -net xlslice_20_Dout [get_bd_pins hbridgewaveform_0/phase] [get_bd_pins xlslice_20/Dout]
+  connect_bd_net -net xlslice_21_Dout [get_bd_pins hbridgewaveform_0/pulswidth] [get_bd_pins xlslice_21/Dout]
+  connect_bd_net -net xlslice_22_Dout [get_bd_pins hbridgewaveform_0/resync] [get_bd_pins xlslice_22/Dout]
+  connect_bd_net -net xlslice_23_Dout [get_bd_pins xlslice_23/Dout] [get_bd_pins xlslice_24/Din] [get_bd_pins xlslice_25/Din] [get_bd_pins xlslice_33/Din] [get_bd_pins xlslice_34/Din]
+  connect_bd_net -net xlslice_24_Dout [get_bd_pins util_vector_logic_1/Op2] [get_bd_pins xlslice_24/Dout]
+  connect_bd_net -net xlslice_25_Dout [get_bd_pins util_vector_logic_1/Op1] [get_bd_pins xlslice_25/Dout]
+  connect_bd_net -net xlslice_26_Dout [get_bd_pins hbridgewaveform_1/phase] [get_bd_pins xlslice_26/Dout]
+  connect_bd_net -net xlslice_27_Dout [get_bd_pins hbridgewaveform_1/freq] [get_bd_pins xlslice_27/Dout]
+  connect_bd_net -net xlslice_28_Dout [get_bd_pins hbridgewaveform_1/pulswidth] [get_bd_pins xlslice_28/Dout]
+  connect_bd_net -net xlslice_29_Dout [get_bd_pins hbridgewaveform_1/resync] [get_bd_pins xlslice_29/Dout]
   connect_bd_net -net xlslice_2_Dout [get_bd_pins rp_iobuf_3/direction] [get_bd_pins xlslice_2/Dout]
+  connect_bd_net -net xlslice_30_Dout [get_bd_pins xlslice_26/Din] [get_bd_pins xlslice_27/Din] [get_bd_pins xlslice_28/Din] [get_bd_pins xlslice_30/Dout]
+  connect_bd_net -net xlslice_31_Dout [get_bd_pins xlslice_19/Din] [get_bd_pins xlslice_20/Din] [get_bd_pins xlslice_21/Din] [get_bd_pins xlslice_31/Dout]
+  connect_bd_net -net xlslice_32_Dout [get_bd_pins util_vector_logic_6/Op2] [get_bd_pins xlslice_32/Dout]
+  connect_bd_net -net xlslice_33_Dout [get_bd_pins util_vector_logic_7/Op1] [get_bd_pins xlslice_33/Dout]
+  connect_bd_net -net xlslice_34_Dout [get_bd_pins util_vector_logic_7/Op2] [get_bd_pins xlslice_34/Dout]
   connect_bd_net -net xlslice_3_Dout [get_bd_pins rp_iobuf_4/direction] [get_bd_pins xlslice_3/Dout]
   connect_bd_net -net xlslice_4_Dout [get_bd_pins xlslice_0/Din] [get_bd_pins xlslice_10/Din] [get_bd_pins xlslice_11/Din] [get_bd_pins xlslice_12/Din] [get_bd_pins xlslice_15/Din] [get_bd_pins xlslice_16/Din] [get_bd_pins xlslice_4/Dout] [get_bd_pins xlslice_6/Din] [get_bd_pins xlslice_9/Din]
   connect_bd_net -net xlslice_5_Dout [get_bd_pins xlslice_1/Din] [get_bd_pins xlslice_13/Din] [get_bd_pins xlslice_14/Din] [get_bd_pins xlslice_17/Din] [get_bd_pins xlslice_2/Din] [get_bd_pins xlslice_3/Din] [get_bd_pins xlslice_5/Dout] [get_bd_pins xlslice_7/Din] [get_bd_pins xlslice_8/Din]
   connect_bd_net -net xlslice_6_Dout [get_bd_pins rp_iobuf_5/val_out] [get_bd_pins xlslice_6/Dout]
-  connect_bd_net -net xlslice_7_Dout [get_bd_pins rp_iobuf_0/direction] [get_bd_pins xlslice_7/Dout]
-  connect_bd_net -net xlslice_8_Dout [get_bd_pins rp_iobuf_1/direction] [get_bd_pins xlslice_8/Dout]
-  connect_bd_net -net xlslice_9_Dout [get_bd_pins rp_iobuf_1/val_out] [get_bd_pins xlslice_9/Dout]
+  connect_bd_net -net xlslice_7_Dout [get_bd_pins rp_iobuf_8/direction] [get_bd_pins xlslice_7/Dout]
+  connect_bd_net -net xlslice_8_Dout [get_bd_pins rp_iobuf_9/direction] [get_bd_pins xlslice_8/Dout]
+  connect_bd_net -net xlslice_9_Dout [get_bd_pins util_vector_logic_3/Op1] [get_bd_pins xlslice_9/Dout]
 
   # Restore current instance
   current_bd_instance $oldCurInst
@@ -3369,8 +3617,8 @@ proc create_root_design { parentCell } {
   connect_bd_net -net Net3 [get_bd_ports ext_DIO3_P] [get_bd_pins reset_manager_0/instant_reset]
   connect_bd_net -net Net4 [get_bd_ports ext_DIO4_P] [get_bd_pins reset_manager_0/alive_signal]
   connect_bd_net -net Net5 [get_bd_ports ext_DIO5_P] [get_bd_pins reset_manager_0/master_trigger]
-  connect_bd_net -net Net6 [get_bd_ports ext_DIO7_P] [get_bd_pins DIO/ext_DIO7_P]
-  connect_bd_net -net Net7 [get_bd_ports ext_DIO7_N] [get_bd_pins DIO/ext_DIO7_N]
+  connect_bd_net -net Net6 [get_bd_ports ext_DIO7_N] [get_bd_pins DIO/ext_DIO7_N]
+  connect_bd_net -net Net7 [get_bd_ports ext_DIO7_P] [get_bd_pins DIO/ext_DIO7_P]
   connect_bd_net -net Net8 [get_bd_ports ext_DIO6_P] [get_bd_pins DIO/ext_DIO6_P]
   connect_bd_net -net Net9 [get_bd_ports ext_DIO6_N] [get_bd_pins DIO/ext_DIO6_N]
   connect_bd_net -net Net10 [get_bd_ports ext_DIO5_N] [get_bd_pins DIO/ext_DIO5_N]
@@ -3407,7 +3655,7 @@ proc create_root_design { parentCell } {
   connect_bd_net -net pdm_oa_dac [get_bd_pins fourier_synth_standard/oa_dac] [get_bd_pins sequencer/oa_dac]
   connect_bd_net -net pdm_pdm_sts [get_bd_pins sequencer/pdm_sts] [get_bd_pins system/curr_pdm_values]
   connect_bd_net -net proc_sys_reset_bram_peripheral_aresetn [get_bd_pins fourier_synth_standard/bram_aresetn] [get_bd_pins proc_sys_reset_bram/peripheral_aresetn] [get_bd_pins sequencer/bram_aresetn]
-  connect_bd_net -net proc_sys_reset_fourier_synth_peripheral_aresetn [get_bd_pins fourier_synth_standard/aresetn] [get_bd_pins proc_sys_reset_fourier_synth/peripheral_aresetn] [get_bd_pins system/aresetn]
+  connect_bd_net -net proc_sys_reset_fourier_synth_peripheral_aresetn [get_bd_pins DIO/aresetn] [get_bd_pins fourier_synth_standard/aresetn] [get_bd_pins proc_sys_reset_fourier_synth/peripheral_aresetn] [get_bd_pins system/aresetn]
   connect_bd_net -net proc_sys_reset_pdm_peripheral_aresetn [get_bd_pins proc_sys_reset_pdm/peripheral_aresetn] [get_bd_pins sequencer/aresetn]
   connect_bd_net -net proc_sys_reset_write_to_ram_peripheral_aresetn [get_bd_pins proc_sys_reset_write_to_ram/peripheral_aresetn] [get_bd_pins write_to_ram/aresetn]
   connect_bd_net -net proc_sys_reset_xadc_peripheral_aresetn [get_bd_pins proc_sys_reset_xadc/peripheral_aresetn] [get_bd_pins xadc_wiz_0/s_axi_aresetn]
@@ -3424,11 +3672,11 @@ proc create_root_design { parentCell } {
   connect_bd_net -net selectio_wiz_1_data_out_to_pins_p [get_bd_ports daisy_p_o] [get_bd_pins selectio_wiz_1/data_out_to_pins_p]
   connect_bd_net -net selectio_wiz_2_clk_out [get_bd_pins clk_wiz_1/clk_in1] [get_bd_pins selectio_wiz_2/clk_out]
   connect_bd_net -net selectio_wiz_2_data_in_to_device [get_bd_pins reset_manager_0/sata_trigger] [get_bd_pins selectio_wiz_2/data_in_to_device]
-  connect_bd_net -net sequencer_enable_dac [get_bd_pins fourier_synth_standard/enable_dac] [get_bd_pins sequencer/enable_dac]
-  connect_bd_net -net sequencer_resync_dac [get_bd_pins fourier_synth_standard/resync_dac] [get_bd_pins sequencer/resync_dac]
+  connect_bd_net -net sequencer_enable_dac [get_bd_pins DIO/enable_dac] [get_bd_pins fourier_synth_standard/enable_dac] [get_bd_pins sequencer/enable_dac]
+  connect_bd_net -net sequencer_resync_dac [get_bd_pins DIO/resync] [get_bd_pins fourier_synth_standard/resync_dac] [get_bd_pins sequencer/resync_dac]
   connect_bd_net -net sequencer_seq_ramp_down [get_bd_pins fourier_synth_standard/seq_ramp_down] [get_bd_pins sequencer/seq_ramp_down]
   connect_bd_net -net system_FCLK_RESET0_N [get_bd_pins system/FCLK_RESET0_N] [get_bd_pins util_vector_logic_1/Op1]
-  connect_bd_net -net system_cfg_data [get_bd_pins fourier_synth_standard/cfg_data] [get_bd_pins system/dac_cfg]
+  connect_bd_net -net system_cfg_data [get_bd_pins DIO/cfg_dac] [get_bd_pins fourier_synth_standard/cfg_data] [get_bd_pins system/dac_cfg]
   connect_bd_net -net system_cfg_data1 [get_bd_pins DIO/cfg_in] [get_bd_pins system/cfg_data] [get_bd_pins xlslice_1/Din] [get_bd_pins xlslice_2/Din] [get_bd_pins xlslice_3/Din] [get_bd_pins xlslice_6/Din]
   connect_bd_net -net system_counter_trigger_cfg [get_bd_pins counter_trigger/counter_trigger_cfg] [get_bd_pins system/counter_trigger_cfg]
   connect_bd_net -net system_peripheral_aresetn [get_bd_pins reset_manager_0/peripheral_aresetn] [get_bd_pins system/peripheral_aresetn]
diff --git a/src/fpga/bd/hbridgewaveform.tcl b/src/fpga/bd/hbridgewaveform.tcl
new file mode 100644
index 00000000..12a2d922
--- /dev/null
+++ b/src/fpga/bd/hbridgewaveform.tcl
@@ -0,0 +1,357 @@
+
+################################################################
+# This is a generated script based on design: hbridgewaveform
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+   set script_path [file normalize [info script]]
+   set script_folder [file dirname $script_path]
+   return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2021.2
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+   puts ""
+   catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+   return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source hbridgewaveform_script.tcl
+
+
+# The design that will be created by this Tcl script contains the following 
+# module references:
+# hbridge_signalgen
+
+# Please add the sources of those modules before sourcing this Tcl script.
+
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+   create_project project_1 myproj -part xc7z010clg400-1
+}
+
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name hbridgewaveform
+
+# This script was generated for a remote BD. To create a non-remote design,
+# change the variable <run_remote_bd_flow> to <0>.
+
+set run_remote_bd_flow 1
+if { $run_remote_bd_flow == 1 } {
+  # Set the reference directory for source file relative paths (by default 
+  # the value is script directory path)
+  set origin_dir ./.julia/dev/RedPitayaDAQServer/src/fpga/bd
+
+  # Use origin directory path location variable, if specified in the tcl shell
+  if { [info exists ::origin_dir_loc] } {
+     set origin_dir $::origin_dir_loc
+  }
+
+  set str_bd_folder [file normalize ${origin_dir}]
+  set str_bd_filepath ${str_bd_folder}/${design_name}/${design_name}.bd
+
+  # Check if remote design exists on disk
+  if { [file exists $str_bd_filepath ] == 1 } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2030 -severity "ERROR" "The remote BD file path <$str_bd_filepath> already exists!"}
+     common::send_gid_msg -ssname BD::TCL -id 2031 -severity "INFO" "To create a non-remote BD, change the variable <run_remote_bd_flow> to <0>."
+     common::send_gid_msg -ssname BD::TCL -id 2032 -severity "INFO" "Also make sure there is no design <$design_name> existing in your current project."
+
+     return 1
+  }
+
+  # Check if design exists in memory
+  set list_existing_designs [get_bd_designs -quiet $design_name]
+  if { $list_existing_designs ne "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2033 -severity "ERROR" "The design <$design_name> already exists in this project! Will not create the remote BD <$design_name> at the folder <$str_bd_folder>."}
+
+     common::send_gid_msg -ssname BD::TCL -id 2034 -severity "INFO" "To create a non-remote BD, change the variable <run_remote_bd_flow> to <0> or please set a different value to variable <design_name>."
+
+     return 1
+  }
+
+  # Check if design exists on disk within project
+  set list_existing_designs [get_files -quiet */${design_name}.bd]
+  if { $list_existing_designs ne "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2035 -severity "ERROR" "The design <$design_name> already exists in this project at location:
+    $list_existing_designs"}
+     catch {common::send_gid_msg -ssname BD::TCL -id 2036 -severity "ERROR" "Will not create the remote BD <$design_name> at the folder <$str_bd_folder>."}
+
+     common::send_gid_msg -ssname BD::TCL -id 2037 -severity "INFO" "To create a non-remote BD, change the variable <run_remote_bd_flow> to <0> or please set a different value to variable <design_name>."
+
+     return 1
+  }
+
+  # Now can create the remote BD
+  # NOTE - usage of <-dir> will create <$str_bd_folder/$design_name/$design_name.bd>
+  create_bd_design -dir $str_bd_folder $design_name
+} else {
+
+  # Create regular design
+  if { [catch {create_bd_design $design_name} errmsg] } {
+     common::send_gid_msg -ssname BD::TCL -id 2038 -severity "INFO" "Please set a different value to variable <design_name>."
+
+     return 1
+  }
+}
+
+current_bd_design $design_name
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+   set list_check_ips "\ 
+pavel-demin:user:axis_variable:1.0\
+xilinx.com:ip:dds_compiler:6.0\
+xilinx.com:ip:util_vector_logic:2.0\
+xilinx.com:ip:xlconcat:2.1\
+xilinx.com:ip:xlslice:1.0\
+"
+
+   set list_ips_missing ""
+   common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+   foreach ip_vlnv $list_check_ips {
+      set ip_obj [get_ipdefs -all $ip_vlnv]
+      if { $ip_obj eq "" } {
+         lappend list_ips_missing $ip_vlnv
+      }
+   }
+
+   if { $list_ips_missing ne "" } {
+      catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+      set bCheckIPsPassed 0
+   }
+
+}
+
+##################################################################
+# CHECK Modules
+##################################################################
+set bCheckModules 1
+if { $bCheckModules == 1 } {
+   set list_check_mods "\ 
+hbridge_signalgen\
+"
+
+   set list_mods_missing ""
+   common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
+
+   foreach mod_vlnv $list_check_mods {
+      if { [can_resolve_reference $mod_vlnv] == 0 } {
+         lappend list_mods_missing $mod_vlnv
+      }
+   }
+
+   if { $list_mods_missing ne "" } {
+      catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
+      common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above."
+      set bCheckIPsPassed 0
+   }
+}
+
+if { $bCheckIPsPassed != 1 } {
+  common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
+  return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+  variable script_folder
+  variable design_name
+
+  if { $parentCell eq "" } {
+     set parentCell [get_bd_cells /]
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+
+  # Create interface ports
+
+  # Create ports
+  set H1out [ create_bd_port -dir O -type data H1out ]
+  set H2out [ create_bd_port -dir O -type data H2out ]
+  set aclk [ create_bd_port -dir I -type clk -freq_hz 125000000 aclk ]
+  set aresetn [ create_bd_port -dir I -type rst aresetn ]
+  set enable_dac [ create_bd_port -dir I enable_dac ]
+  set freq [ create_bd_port -dir I -from 47 -to 0 freq ]
+  set phase [ create_bd_port -dir I -from 47 -to 0 phase ]
+  set pulswidth [ create_bd_port -dir I -from 15 -to 0 pulswidth ]
+  set resync [ create_bd_port -dir I resync ]
+
+  # Create instance: axis_variable_A_channel_1, and set properties
+  set axis_variable_A_channel_1 [ create_bd_cell -type ip -vlnv pavel-demin:user:axis_variable:1.0 axis_variable_A_channel_1 ]
+  set_property -dict [ list \
+   CONFIG.AXIS_TDATA_WIDTH {96} \
+ ] $axis_variable_A_channel_1
+
+  # Create instance: dds_compiler_A_channel_1, and set properties
+  set dds_compiler_A_channel_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:dds_compiler:6.0 dds_compiler_A_channel_1 ]
+  set_property -dict [ list \
+   CONFIG.Amplitude_Mode {Full_Range} \
+   CONFIG.DATA_Has_TLAST {Not_Required} \
+   CONFIG.DDS_Clock_Rate {125} \
+   CONFIG.Frequency_Resolution {4.440893e-7} \
+   CONFIG.Has_ACLKEN {false} \
+   CONFIG.Has_ARESETn {true} \
+   CONFIG.Has_Phase_Out {true} \
+   CONFIG.Has_TREADY {false} \
+   CONFIG.Latency {2} \
+   CONFIG.Latency_Configuration {Auto} \
+   CONFIG.M_DATA_Has_TUSER {Not_Required} \
+   CONFIG.M_PHASE_Has_TUSER {Not_Required} \
+   CONFIG.Noise_Shaping {None} \
+   CONFIG.Output_Frequency1 {0} \
+   CONFIG.Output_Selection {Sine} \
+   CONFIG.Output_Width {3} \
+   CONFIG.PINC1 {0} \
+   CONFIG.POFF1 {0} \
+   CONFIG.Parameter_Entry {Hardware_Parameters} \
+   CONFIG.PartsPresent {Phase_Generator_only} \
+   CONFIG.Phase_Increment {Programmable} \
+   CONFIG.Phase_Offset_Angles1 {0} \
+   CONFIG.Phase_Width {48} \
+   CONFIG.Phase_offset {Programmable} \
+   CONFIG.Resync {false} \
+   CONFIG.S_PHASE_Has_TUSER {Not_Required} \
+   CONFIG.Spurious_Free_Dynamic_Range {88} \
+ ] $dds_compiler_A_channel_1
+
+  # Create instance: hbridge_signalgen_0_upgraded_ipi, and set properties
+  set block_name hbridge_signalgen
+  set block_cell_name hbridge_signalgen_0_upgraded_ipi
+  if { [catch {set hbridge_signalgen_0_upgraded_ipi [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   } elseif { $hbridge_signalgen_0_upgraded_ipi eq "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   }
+    set_property -dict [ list \
+   CONFIG.AXIS_TDATA_PHASE_WIDTH {48} \
+   CONFIG.CFG_DATA_WIDTH {14} \
+ ] $hbridge_signalgen_0_upgraded_ipi
+
+  # Create instance: util_vector_logic_0, and set properties
+  set util_vector_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_0 ]
+  set_property -dict [ list \
+   CONFIG.C_OPERATION {not} \
+   CONFIG.C_SIZE {1} \
+   CONFIG.LOGO_FILE {data/sym_notgate.png} \
+ ] $util_vector_logic_0
+
+  # Create instance: util_vector_logic_1, and set properties
+  set util_vector_logic_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_1 ]
+  set_property -dict [ list \
+   CONFIG.C_SIZE {1} \
+ ] $util_vector_logic_1
+
+  # Create instance: xlconcat_A_channel_1, and set properties
+  set xlconcat_A_channel_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_A_channel_1 ]
+  set_property -dict [ list \
+   CONFIG.IN0_WIDTH {48} \
+   CONFIG.IN1_WIDTH {48} \
+   CONFIG.IN2_WIDTH {8} \
+   CONFIG.NUM_PORTS {2} \
+ ] $xlconcat_A_channel_1
+
+  # Create instance: xlslice_0, and set properties
+  set xlslice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 ]
+  set_property -dict [ list \
+   CONFIG.DIN_FROM {13} \
+   CONFIG.DIN_WIDTH {16} \
+   CONFIG.DOUT_WIDTH {14} \
+ ] $xlslice_0
+
+  # Create interface connections
+  connect_bd_intf_net -intf_net axis_variable_A_channel_1_M_AXIS [get_bd_intf_pins axis_variable_A_channel_1/M_AXIS] [get_bd_intf_pins dds_compiler_A_channel_1/S_AXIS_CONFIG]
+  connect_bd_intf_net -intf_net dds_compiler_A_channel_1_M_AXIS_PHASE [get_bd_intf_pins dds_compiler_A_channel_1/M_AXIS_PHASE] [get_bd_intf_pins hbridge_signalgen_0_upgraded_ipi/s_axis_phase]
+
+  # Create port connections
+  connect_bd_net -net aresetn_1 [get_bd_ports aresetn] [get_bd_pins axis_variable_A_channel_1/aresetn] [get_bd_pins hbridge_signalgen_0_upgraded_ipi/aresetn] [get_bd_pins util_vector_logic_1/Op2]
+  connect_bd_net -net clk_wiz_0_clk_internal [get_bd_ports aclk] [get_bd_pins axis_variable_A_channel_1/aclk] [get_bd_pins dds_compiler_A_channel_1/aclk] [get_bd_pins hbridge_signalgen_0_upgraded_ipi/clk]
+  connect_bd_net -net enable_dac_1 [get_bd_ports enable_dac] [get_bd_pins hbridge_signalgen_0_upgraded_ipi/enable_dac]
+  connect_bd_net -net freq_1 [get_bd_ports freq] [get_bd_pins xlconcat_A_channel_1/In0]
+  connect_bd_net -net hbridge_signalgen_0_upgraded_ipi_H1 [get_bd_ports H1out] [get_bd_pins hbridge_signalgen_0_upgraded_ipi/H1]
+  connect_bd_net -net hbridge_signalgen_0_upgraded_ipi_H2 [get_bd_ports H2out] [get_bd_pins hbridge_signalgen_0_upgraded_ipi/H2]
+  connect_bd_net -net phase_1 [get_bd_ports phase] [get_bd_pins xlconcat_A_channel_1/In1]
+  connect_bd_net -net pulswidth_1 [get_bd_ports pulswidth] [get_bd_pins xlslice_0/Din]
+  connect_bd_net -net resync_1 [get_bd_ports resync] [get_bd_pins util_vector_logic_0/Op1]
+  connect_bd_net -net util_vector_logic_0_Res [get_bd_pins util_vector_logic_0/Res] [get_bd_pins util_vector_logic_1/Op1]
+  connect_bd_net -net util_vector_logic_1_Res [get_bd_pins dds_compiler_A_channel_1/aresetn] [get_bd_pins util_vector_logic_1/Res]
+  connect_bd_net -net xlconcat_A_channel_1_dout [get_bd_pins axis_variable_A_channel_1/cfg_data] [get_bd_pins xlconcat_A_channel_1/dout]
+  connect_bd_net -net xlslice_0_Dout [get_bd_pins hbridge_signalgen_0_upgraded_ipi/cfg_data] [get_bd_pins xlslice_0/Dout]
+
+  # Create address segments
+
+
+  # Restore current instance
+  current_bd_instance $oldCurInst
+
+  validate_bd_design
+  save_bd_design
+}
+# End of create_root_design()
+
+
+##################################################################
+# MAIN FLOW
+##################################################################
+
+create_root_design ""
+
+
diff --git a/src/fpga/build.tcl b/src/fpga/build.tcl
index 84a305a4..e2aded55 100644
--- a/src/fpga/build.tcl
+++ b/src/fpga/build.tcl
@@ -30,6 +30,7 @@ update_ip_catalog
 source src/fpga/bd/signal_calib.tcl
 source src/fpga/bd/signal_ramp.tcl
 source src/fpga/bd/waveform_gen.tcl
+source src/fpga/bd/hbridgewaveform.tcl
 source src/fpga/bd/bd.tcl
 
 # Create HDL wrapper for blockdesign
diff --git a/src/fpga/hdl/hbridge_signalgen.v b/src/fpga/hdl/hbridge_signalgen.v
new file mode 100644
index 00000000..9fedc0c0
--- /dev/null
+++ b/src/fpga/hdl/hbridge_signalgen.v
@@ -0,0 +1,82 @@
+`timescale 1ns / 1ps
+
+module hbridge_signalgen #
+(
+    parameter integer AXIS_TDATA_PHASE_WIDTH = 16,
+    parameter integer CFG_DATA_WIDTH = 16
+)
+(
+    // DDS Input
+    input  wire [AXIS_TDATA_PHASE_WIDTH-1:0] s_axis_tdata_phase,
+    input  wire s_axis_tvalid_phase,
+    
+    input [CFG_DATA_WIDTH-1:0] cfg_data,
+    
+    
+    input clk,
+    input aresetn,
+    input enable_dac,
+    output H1, H2
+);
+
+    reg signed [AXIS_TDATA_PHASE_WIDTH-1:0] phase;
+    reg signed [CFG_DATA_WIDTH-1:0] A;
+    reg h1, h2;
+
+	
+    always @(posedge clk)
+    begin
+        A <= cfg_data>>1;
+        
+        if (~aresetn)
+        begin
+            h1 <= 0;
+            h2 <= 0;
+            phase <= 0;
+        end
+        else
+        begin
+            phase <= s_axis_tdata_phase >>> (AXIS_TDATA_PHASE_WIDTH - CFG_DATA_WIDTH);
+            //4096 = (1<<<(CFG_DATA_WIDTH-2))
+
+            if  (enable_dac)
+            begin
+                if (phase < 4096-A)
+                begin
+                    h1 <= 0;
+                    h2 <= 0;
+                end
+                else if (phase < 4096+A)
+                begin
+                    h1 <= 0;
+                    h2 <= 1;
+                end
+                else if (phase < 12288-A)
+                begin
+                    h1 <= 0;
+                    h2 <= 0;
+                end
+                else if (phase < 12288+A)
+                begin
+                    h1 <= 1;
+                    h2 <= 0;
+                end
+                else
+                begin
+                    h1 <= 0;
+                    h2 <= 0;
+                end
+            end else begin
+                h1 <= 0;
+                h2 <= 0;
+            end
+
+         end
+         
+
+    end
+    
+assign H1 = h1;
+assign H2 = h2;
+
+endmodule
\ No newline at end of file

From 3f5d76122aa2ebea46d8f174c0ea4a7aebdb05c4 Mon Sep 17 00:00:00 2001
From: Tobias Knopp <tobias@knoppweb.de>
Date: Fri, 6 Dec 2024 18:02:09 +0100
Subject: [PATCH 14/38] some fix remaining issues in BD

---
 src/fpga/bd/bd.tcl               | 52 +++++---------------------------
 src/fpga/bd/hbridgewaveform.tcl  | 44 +++++++++++++++++++++++----
 src/fpga/hdl/hbridge_signalgen.v | 50 +++++++++++++-----------------
 3 files changed, 67 insertions(+), 79 deletions(-)

diff --git a/src/fpga/bd/bd.tcl b/src/fpga/bd/bd.tcl
index 9576f109..f85d8cfb 100644
--- a/src/fpga/bd/bd.tcl
+++ b/src/fpga/bd/bd.tcl
@@ -2803,22 +2803,6 @@ proc create_hier_cell_DIO { parentCell nameHier } {
      return 1
    }
   
-  # Create instance: util_vector_logic_0, and set properties
-  set util_vector_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_0 ]
-  set_property -dict [ list \
-   CONFIG.C_OPERATION {and} \
-   CONFIG.C_SIZE {1} \
-   CONFIG.LOGO_FILE {data/sym_andgate.png} \
- ] $util_vector_logic_0
-
-  # Create instance: util_vector_logic_1, and set properties
-  set util_vector_logic_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_1 ]
-  set_property -dict [ list \
-   CONFIG.C_OPERATION {or} \
-   CONFIG.C_SIZE {1} \
-   CONFIG.LOGO_FILE {data/sym_orgate.png} \
- ] $util_vector_logic_1
-
   # Create instance: util_vector_logic_2, and set properties
   set util_vector_logic_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_2 ]
   set_property -dict [ list \
@@ -2851,22 +2835,6 @@ proc create_hier_cell_DIO { parentCell nameHier } {
    CONFIG.LOGO_FILE {data/sym_orgate.png} \
  ] $util_vector_logic_5
 
-  # Create instance: util_vector_logic_6, and set properties
-  set util_vector_logic_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_6 ]
-  set_property -dict [ list \
-   CONFIG.C_OPERATION {and} \
-   CONFIG.C_SIZE {1} \
-   CONFIG.LOGO_FILE {data/sym_andgate.png} \
- ] $util_vector_logic_6
-
-  # Create instance: util_vector_logic_7, and set properties
-  set util_vector_logic_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_7 ]
-  set_property -dict [ list \
-   CONFIG.C_OPERATION {or} \
-   CONFIG.C_SIZE {1} \
-   CONFIG.LOGO_FILE {data/sym_orgate.png} \
- ] $util_vector_logic_7
-
   # Create instance: xlconcat_0, and set properties
   set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ]
   set_property -dict [ list \
@@ -3193,7 +3161,6 @@ proc create_hier_cell_DIO { parentCell nameHier } {
   connect_bd_net -net cfg_dac_1 [get_bd_pins cfg_dac] [get_bd_pins xlslice_30/Din] [get_bd_pins xlslice_31/Din]
   connect_bd_net -net clk_wiz_0_clk_internal [get_bd_pins clk] [get_bd_pins hbridgewaveform_0/aclk] [get_bd_pins hbridgewaveform_1/aclk] [get_bd_pins rp_iobuf_2/clk] [get_bd_pins rp_iobuf_3/clk] [get_bd_pins rp_iobuf_4/clk] [get_bd_pins rp_iobuf_5/clk] [get_bd_pins rp_iobuf_6/clk] [get_bd_pins rp_iobuf_7/clk] [get_bd_pins rp_iobuf_8/clk] [get_bd_pins rp_iobuf_9/clk]
   connect_bd_net -net enable_dac_1 [get_bd_pins enable_dac] [get_bd_pins xlslice_18/Din] [get_bd_pins xlslice_32/Din]
-  connect_bd_net -net enable_dac_2 [get_bd_pins hbridgewaveform_1/enable_dac] [get_bd_pins util_vector_logic_6/Res]
   connect_bd_net -net hbridgewaveform_0_H1out [get_bd_pins hbridgewaveform_0/H1out] [get_bd_pins util_vector_logic_2/Op2]
   connect_bd_net -net hbridgewaveform_0_H2out [get_bd_pins hbridgewaveform_0/H2out] [get_bd_pins util_vector_logic_3/Op2]
   connect_bd_net -net hbridgewaveform_1_H1out [get_bd_pins hbridgewaveform_1/H1out] [get_bd_pins util_vector_logic_4/Op2]
@@ -3208,13 +3175,10 @@ proc create_hier_cell_DIO { parentCell nameHier } {
   connect_bd_net -net rp_iobuf_8_val_in_clocked [get_bd_pins rp_iobuf_8/val_in_clocked] [get_bd_pins xlconcat_0/In0]
   connect_bd_net -net rp_iobuf_9_val_in_clocked [get_bd_pins rp_iobuf_9/val_in_clocked] [get_bd_pins xlconcat_0/In1]
   connect_bd_net -net system_cfg_data1 [get_bd_pins cfg_in] [get_bd_pins xlslice_23/Din] [get_bd_pins xlslice_4/Din] [get_bd_pins xlslice_5/Din]
-  connect_bd_net -net util_vector_logic_0_Res [get_bd_pins hbridgewaveform_0/enable_dac] [get_bd_pins util_vector_logic_0/Res]
-  connect_bd_net -net util_vector_logic_1_Res [get_bd_pins util_vector_logic_0/Op1] [get_bd_pins util_vector_logic_1/Res]
   connect_bd_net -net util_vector_logic_2_Res [get_bd_pins rp_iobuf_8/val_out] [get_bd_pins util_vector_logic_2/Res]
   connect_bd_net -net util_vector_logic_3_Res [get_bd_pins rp_iobuf_9/val_out] [get_bd_pins util_vector_logic_3/Res]
   connect_bd_net -net util_vector_logic_4_Res [get_bd_pins rp_iobuf_2/val_out] [get_bd_pins util_vector_logic_4/Res]
   connect_bd_net -net util_vector_logic_5_Res [get_bd_pins rp_iobuf_3/val_out] [get_bd_pins util_vector_logic_5/Res]
-  connect_bd_net -net util_vector_logic_7_Res [get_bd_pins util_vector_logic_6/Op1] [get_bd_pins util_vector_logic_7/Res]
   connect_bd_net -net xlconcat_0_dout2 [get_bd_pins dio_data_clocked] [get_bd_pins xlconcat_0/dout]
   connect_bd_net -net xlconstant_1_dout [get_bd_pins xlconcat_0/In8] [get_bd_pins xlconstant_1/dout]
   connect_bd_net -net xlslice_0_Dout [get_bd_pins util_vector_logic_2/Op1] [get_bd_pins xlslice_0/Dout]
@@ -3226,25 +3190,25 @@ proc create_hier_cell_DIO { parentCell nameHier } {
   connect_bd_net -net xlslice_15_Dout [get_bd_pins rp_iobuf_6/val_out] [get_bd_pins xlslice_15/Dout]
   connect_bd_net -net xlslice_16_Dout [get_bd_pins rp_iobuf_7/val_out] [get_bd_pins xlslice_16/Dout]
   connect_bd_net -net xlslice_17_Dout [get_bd_pins rp_iobuf_7/direction] [get_bd_pins xlslice_17/Dout]
-  connect_bd_net -net xlslice_18_Dout [get_bd_pins util_vector_logic_0/Op2] [get_bd_pins xlslice_18/Dout]
+  connect_bd_net -net xlslice_18_Dout [get_bd_pins hbridgewaveform_0/enable_All] [get_bd_pins xlslice_18/Dout]
   connect_bd_net -net xlslice_19_Dout [get_bd_pins hbridgewaveform_0/freq] [get_bd_pins xlslice_19/Dout]
   connect_bd_net -net xlslice_1_Dout [get_bd_pins rp_iobuf_2/direction] [get_bd_pins xlslice_1/Dout]
   connect_bd_net -net xlslice_20_Dout [get_bd_pins hbridgewaveform_0/phase] [get_bd_pins xlslice_20/Dout]
   connect_bd_net -net xlslice_21_Dout [get_bd_pins hbridgewaveform_0/pulswidth] [get_bd_pins xlslice_21/Dout]
   connect_bd_net -net xlslice_22_Dout [get_bd_pins hbridgewaveform_0/resync] [get_bd_pins xlslice_22/Dout]
   connect_bd_net -net xlslice_23_Dout [get_bd_pins xlslice_23/Dout] [get_bd_pins xlslice_24/Din] [get_bd_pins xlslice_25/Din] [get_bd_pins xlslice_33/Din] [get_bd_pins xlslice_34/Din]
-  connect_bd_net -net xlslice_24_Dout [get_bd_pins util_vector_logic_1/Op2] [get_bd_pins xlslice_24/Dout]
-  connect_bd_net -net xlslice_25_Dout [get_bd_pins util_vector_logic_1/Op1] [get_bd_pins xlslice_25/Dout]
-  connect_bd_net -net xlslice_26_Dout [get_bd_pins hbridgewaveform_1/phase] [get_bd_pins xlslice_26/Dout]
-  connect_bd_net -net xlslice_27_Dout [get_bd_pins hbridgewaveform_1/freq] [get_bd_pins xlslice_27/Dout]
+  connect_bd_net -net xlslice_24_Dout [get_bd_pins hbridgewaveform_0/enable_H1] [get_bd_pins xlslice_24/Dout]
+  connect_bd_net -net xlslice_25_Dout [get_bd_pins hbridgewaveform_0/enable_H2] [get_bd_pins xlslice_25/Dout]
+  connect_bd_net -net xlslice_26_Dout [get_bd_pins hbridgewaveform_1/freq] [get_bd_pins xlslice_26/Dout]
+  connect_bd_net -net xlslice_27_Dout [get_bd_pins hbridgewaveform_1/phase] [get_bd_pins xlslice_27/Dout]
   connect_bd_net -net xlslice_28_Dout [get_bd_pins hbridgewaveform_1/pulswidth] [get_bd_pins xlslice_28/Dout]
   connect_bd_net -net xlslice_29_Dout [get_bd_pins hbridgewaveform_1/resync] [get_bd_pins xlslice_29/Dout]
   connect_bd_net -net xlslice_2_Dout [get_bd_pins rp_iobuf_3/direction] [get_bd_pins xlslice_2/Dout]
   connect_bd_net -net xlslice_30_Dout [get_bd_pins xlslice_26/Din] [get_bd_pins xlslice_27/Din] [get_bd_pins xlslice_28/Din] [get_bd_pins xlslice_30/Dout]
   connect_bd_net -net xlslice_31_Dout [get_bd_pins xlslice_19/Din] [get_bd_pins xlslice_20/Din] [get_bd_pins xlslice_21/Din] [get_bd_pins xlslice_31/Dout]
-  connect_bd_net -net xlslice_32_Dout [get_bd_pins util_vector_logic_6/Op2] [get_bd_pins xlslice_32/Dout]
-  connect_bd_net -net xlslice_33_Dout [get_bd_pins util_vector_logic_7/Op1] [get_bd_pins xlslice_33/Dout]
-  connect_bd_net -net xlslice_34_Dout [get_bd_pins util_vector_logic_7/Op2] [get_bd_pins xlslice_34/Dout]
+  connect_bd_net -net xlslice_32_Dout [get_bd_pins hbridgewaveform_1/enable_All] [get_bd_pins xlslice_32/Dout]
+  connect_bd_net -net xlslice_33_Dout [get_bd_pins hbridgewaveform_1/enable_H1] [get_bd_pins xlslice_33/Dout]
+  connect_bd_net -net xlslice_34_Dout [get_bd_pins hbridgewaveform_1/enable_H2] [get_bd_pins xlslice_34/Dout]
   connect_bd_net -net xlslice_3_Dout [get_bd_pins rp_iobuf_4/direction] [get_bd_pins xlslice_3/Dout]
   connect_bd_net -net xlslice_4_Dout [get_bd_pins xlslice_0/Din] [get_bd_pins xlslice_10/Din] [get_bd_pins xlslice_11/Din] [get_bd_pins xlslice_12/Din] [get_bd_pins xlslice_15/Din] [get_bd_pins xlslice_16/Din] [get_bd_pins xlslice_4/Dout] [get_bd_pins xlslice_6/Din] [get_bd_pins xlslice_9/Din]
   connect_bd_net -net xlslice_5_Dout [get_bd_pins xlslice_1/Din] [get_bd_pins xlslice_13/Din] [get_bd_pins xlslice_14/Din] [get_bd_pins xlslice_17/Din] [get_bd_pins xlslice_2/Din] [get_bd_pins xlslice_3/Din] [get_bd_pins xlslice_5/Dout] [get_bd_pins xlslice_7/Din] [get_bd_pins xlslice_8/Din]
diff --git a/src/fpga/bd/hbridgewaveform.tcl b/src/fpga/bd/hbridgewaveform.tcl
index 12a2d922..d2f98ab8 100644
--- a/src/fpga/bd/hbridgewaveform.tcl
+++ b/src/fpga/bd/hbridgewaveform.tcl
@@ -223,11 +223,13 @@ proc create_root_design { parentCell } {
   # Create interface ports
 
   # Create ports
-  set H1out [ create_bd_port -dir O -type data H1out ]
-  set H2out [ create_bd_port -dir O -type data H2out ]
+  set H1out [ create_bd_port -dir O -from 0 -to 0 -type data H1out ]
+  set H2out [ create_bd_port -dir O -from 0 -to 0 -type data H2out ]
   set aclk [ create_bd_port -dir I -type clk -freq_hz 125000000 aclk ]
   set aresetn [ create_bd_port -dir I -type rst aresetn ]
-  set enable_dac [ create_bd_port -dir I enable_dac ]
+  set enable_All [ create_bd_port -dir I enable_All ]
+  set enable_H1 [ create_bd_port -dir I -type data enable_H1 ]
+  set enable_H2 [ create_bd_port -dir I -type data enable_H2 ]
   set freq [ create_bd_port -dir I -from 47 -to 0 freq ]
   set phase [ create_bd_port -dir I -from 47 -to 0 phase ]
   set pulswidth [ create_bd_port -dir I -from 15 -to 0 pulswidth ]
@@ -300,6 +302,30 @@ proc create_root_design { parentCell } {
    CONFIG.C_SIZE {1} \
  ] $util_vector_logic_1
 
+  # Create instance: util_vector_logic_2, and set properties
+  set util_vector_logic_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_2 ]
+  set_property -dict [ list \
+   CONFIG.C_SIZE {1} \
+ ] $util_vector_logic_2
+
+  # Create instance: util_vector_logic_3, and set properties
+  set util_vector_logic_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_3 ]
+  set_property -dict [ list \
+   CONFIG.C_SIZE {1} \
+ ] $util_vector_logic_3
+
+  # Create instance: util_vector_logic_4, and set properties
+  set util_vector_logic_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_4 ]
+  set_property -dict [ list \
+   CONFIG.C_SIZE {1} \
+ ] $util_vector_logic_4
+
+  # Create instance: util_vector_logic_5, and set properties
+  set util_vector_logic_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_5 ]
+  set_property -dict [ list \
+   CONFIG.C_SIZE {1} \
+ ] $util_vector_logic_5
+
   # Create instance: xlconcat_A_channel_1, and set properties
   set xlconcat_A_channel_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_A_channel_1 ]
   set_property -dict [ list \
@@ -324,15 +350,21 @@ proc create_root_design { parentCell } {
   # Create port connections
   connect_bd_net -net aresetn_1 [get_bd_ports aresetn] [get_bd_pins axis_variable_A_channel_1/aresetn] [get_bd_pins hbridge_signalgen_0_upgraded_ipi/aresetn] [get_bd_pins util_vector_logic_1/Op2]
   connect_bd_net -net clk_wiz_0_clk_internal [get_bd_ports aclk] [get_bd_pins axis_variable_A_channel_1/aclk] [get_bd_pins dds_compiler_A_channel_1/aclk] [get_bd_pins hbridge_signalgen_0_upgraded_ipi/clk]
-  connect_bd_net -net enable_dac_1 [get_bd_ports enable_dac] [get_bd_pins hbridge_signalgen_0_upgraded_ipi/enable_dac]
+  connect_bd_net -net enable_All_1 [get_bd_ports enable_All] [get_bd_pins util_vector_logic_4/Op1] [get_bd_pins util_vector_logic_5/Op1]
+  connect_bd_net -net enable_H1_1 [get_bd_ports enable_H1] [get_bd_pins util_vector_logic_2/Op1]
+  connect_bd_net -net enable_H2_1 [get_bd_ports enable_H2] [get_bd_pins util_vector_logic_3/Op1]
   connect_bd_net -net freq_1 [get_bd_ports freq] [get_bd_pins xlconcat_A_channel_1/In0]
-  connect_bd_net -net hbridge_signalgen_0_upgraded_ipi_H1 [get_bd_ports H1out] [get_bd_pins hbridge_signalgen_0_upgraded_ipi/H1]
-  connect_bd_net -net hbridge_signalgen_0_upgraded_ipi_H2 [get_bd_ports H2out] [get_bd_pins hbridge_signalgen_0_upgraded_ipi/H2]
+  connect_bd_net -net hbridge_signalgen_0_upgraded_ipi_H1 [get_bd_pins hbridge_signalgen_0_upgraded_ipi/H1] [get_bd_pins util_vector_logic_2/Op2]
+  connect_bd_net -net hbridge_signalgen_0_upgraded_ipi_H2 [get_bd_pins hbridge_signalgen_0_upgraded_ipi/H2] [get_bd_pins util_vector_logic_3/Op2]
   connect_bd_net -net phase_1 [get_bd_ports phase] [get_bd_pins xlconcat_A_channel_1/In1]
   connect_bd_net -net pulswidth_1 [get_bd_ports pulswidth] [get_bd_pins xlslice_0/Din]
   connect_bd_net -net resync_1 [get_bd_ports resync] [get_bd_pins util_vector_logic_0/Op1]
   connect_bd_net -net util_vector_logic_0_Res [get_bd_pins util_vector_logic_0/Res] [get_bd_pins util_vector_logic_1/Op1]
   connect_bd_net -net util_vector_logic_1_Res [get_bd_pins dds_compiler_A_channel_1/aresetn] [get_bd_pins util_vector_logic_1/Res]
+  connect_bd_net -net util_vector_logic_2_Res [get_bd_pins util_vector_logic_2/Res] [get_bd_pins util_vector_logic_4/Op2]
+  connect_bd_net -net util_vector_logic_3_Res [get_bd_pins util_vector_logic_3/Res] [get_bd_pins util_vector_logic_5/Op2]
+  connect_bd_net -net util_vector_logic_4_Res [get_bd_ports H1out] [get_bd_pins util_vector_logic_4/Res]
+  connect_bd_net -net util_vector_logic_5_Res [get_bd_ports H2out] [get_bd_pins util_vector_logic_5/Res]
   connect_bd_net -net xlconcat_A_channel_1_dout [get_bd_pins axis_variable_A_channel_1/cfg_data] [get_bd_pins xlconcat_A_channel_1/dout]
   connect_bd_net -net xlslice_0_Dout [get_bd_pins hbridge_signalgen_0_upgraded_ipi/cfg_data] [get_bd_pins xlslice_0/Dout]
 
diff --git a/src/fpga/hdl/hbridge_signalgen.v b/src/fpga/hdl/hbridge_signalgen.v
index 9fedc0c0..9b5e56eb 100644
--- a/src/fpga/hdl/hbridge_signalgen.v
+++ b/src/fpga/hdl/hbridge_signalgen.v
@@ -15,7 +15,6 @@ module hbridge_signalgen #
     
     input clk,
     input aresetn,
-    input enable_dac,
     output H1, H2
 );
 
@@ -39,41 +38,34 @@ module hbridge_signalgen #
             phase <= s_axis_tdata_phase >>> (AXIS_TDATA_PHASE_WIDTH - CFG_DATA_WIDTH);
             //4096 = (1<<<(CFG_DATA_WIDTH-2))
 
-            if  (enable_dac)
+            if (phase < 4096-A)
+            begin
+                h1 <= 0;
+                h2 <= 0;
+            end
+            else if (phase < 4096+A)
+            begin
+                h1 <= 0;
+                h2 <= 1;
+            end
+            else if (phase < 12288-A)
+            begin
+                h1 <= 0;
+                h2 <= 0;
+            end
+            else if (phase < 12288+A)
+            begin
+                h1 <= 1;
+                h2 <= 0;
+            end
+            else
             begin
-                if (phase < 4096-A)
-                begin
-                    h1 <= 0;
-                    h2 <= 0;
-                end
-                else if (phase < 4096+A)
-                begin
-                    h1 <= 0;
-                    h2 <= 1;
-                end
-                else if (phase < 12288-A)
-                begin
-                    h1 <= 0;
-                    h2 <= 0;
-                end
-                else if (phase < 12288+A)
-                begin
-                    h1 <= 1;
-                    h2 <= 0;
-                end
-                else
-                begin
-                    h1 <= 0;
-                    h2 <= 0;
-                end
-            end else begin
                 h1 <= 0;
                 h2 <= 0;
             end
 
          end
          
-
     end
     
 assign H1 = h1;

From 7d28e35e107e7c1fef9dc374a8374f3321ab2da7 Mon Sep 17 00:00:00 2001
From: Tobias Knopp <tobias@knoppweb.de>
Date: Fri, 6 Dec 2024 19:45:49 +0100
Subject: [PATCH 15/38] update bd

---
 src/fpga/bd/hbridgewaveform.tcl | 96 +++++++++++++++++----------------
 1 file changed, 49 insertions(+), 47 deletions(-)

diff --git a/src/fpga/bd/hbridgewaveform.tcl b/src/fpga/bd/hbridgewaveform.tcl
index d2f98ab8..5e6adbc8 100644
--- a/src/fpga/bd/hbridgewaveform.tcl
+++ b/src/fpga/bd/hbridgewaveform.tcl
@@ -58,68 +58,70 @@ if { $list_projs eq "" } {
 variable design_name
 set design_name hbridgewaveform
 
-# This script was generated for a remote BD. To create a non-remote design,
-# change the variable <run_remote_bd_flow> to <0>.
-
-set run_remote_bd_flow 1
-if { $run_remote_bd_flow == 1 } {
-  # Set the reference directory for source file relative paths (by default 
-  # the value is script directory path)
-  set origin_dir ./.julia/dev/RedPitayaDAQServer/src/fpga/bd
-
-  # Use origin directory path location variable, if specified in the tcl shell
-  if { [info exists ::origin_dir_loc] } {
-     set origin_dir $::origin_dir_loc
-  }
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+#    create_bd_design $design_name
 
-  set str_bd_folder [file normalize ${origin_dir}]
-  set str_bd_filepath ${str_bd_folder}/${design_name}/${design_name}.bd
+# Creating design if needed
+set errMsg ""
+set nRet 0
 
-  # Check if remote design exists on disk
-  if { [file exists $str_bd_filepath ] == 1 } {
-     catch {common::send_gid_msg -ssname BD::TCL -id 2030 -severity "ERROR" "The remote BD file path <$str_bd_filepath> already exists!"}
-     common::send_gid_msg -ssname BD::TCL -id 2031 -severity "INFO" "To create a non-remote BD, change the variable <run_remote_bd_flow> to <0>."
-     common::send_gid_msg -ssname BD::TCL -id 2032 -severity "INFO" "Also make sure there is no design <$design_name> existing in your current project."
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
 
-     return 1
-  }
+if { ${design_name} eq "" } {
+   # USE CASES:
+   #    1) Design_name not set
 
-  # Check if design exists in memory
-  set list_existing_designs [get_bd_designs -quiet $design_name]
-  if { $list_existing_designs ne "" } {
-     catch {common::send_gid_msg -ssname BD::TCL -id 2033 -severity "ERROR" "The design <$design_name> already exists in this project! Will not create the remote BD <$design_name> at the folder <$str_bd_folder>."}
+   set errMsg "Please set the variable <design_name> to a non-empty value."
+   set nRet 1
 
-     common::send_gid_msg -ssname BD::TCL -id 2034 -severity "INFO" "To create a non-remote BD, change the variable <run_remote_bd_flow> to <0> or please set a different value to variable <design_name>."
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+   # USE CASES:
+   #    2): Current design opened AND is empty AND names same.
+   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
+   #    4): Current design opened AND is empty AND names diff; design_name exists in project.
 
-     return 1
-  }
+   if { $cur_design ne $design_name } {
+      common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
+      set design_name [get_property NAME $cur_design]
+   }
+   common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
 
-  # Check if design exists on disk within project
-  set list_existing_designs [get_files -quiet */${design_name}.bd]
-  if { $list_existing_designs ne "" } {
-     catch {common::send_gid_msg -ssname BD::TCL -id 2035 -severity "ERROR" "The design <$design_name> already exists in this project at location:
-    $list_existing_designs"}
-     catch {common::send_gid_msg -ssname BD::TCL -id 2036 -severity "ERROR" "Will not create the remote BD <$design_name> at the folder <$str_bd_folder>."}
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+   # USE CASES:
+   #    5) Current design opened AND has components AND same names.
 
-     common::send_gid_msg -ssname BD::TCL -id 2037 -severity "INFO" "To create a non-remote BD, change the variable <run_remote_bd_flow> to <0> or please set a different value to variable <design_name>."
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+   # USE CASES: 
+   #    6) Current opened design, has components, but diff names, design_name exists in project.
+   #    7) No opened design, design_name exists in project.
 
-     return 1
-  }
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 2
 
-  # Now can create the remote BD
-  # NOTE - usage of <-dir> will create <$str_bd_folder/$design_name/$design_name.bd>
-  create_bd_design -dir $str_bd_folder $design_name
 } else {
+   # USE CASES:
+   #    8) No opened design, design_name not in project.
+   #    9) Current opened design, has components, but diff names, design_name not in project.
 
-  # Create regular design
-  if { [catch {create_bd_design $design_name} errmsg] } {
-     common::send_gid_msg -ssname BD::TCL -id 2038 -severity "INFO" "Please set a different value to variable <design_name>."
+   common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+   create_bd_design $design_name
+
+   common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
+   current_bd_design $design_name
 
-     return 1
-  }
 }
 
-current_bd_design $design_name
+common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
+
+if { $nRet != 0 } {
+   catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
+   return $nRet
+}
 
 set bCheckIPsPassed 1
 ##################################################################

From 691afb933fba9fee5896ea3829c7d1128fb320af Mon Sep 17 00:00:00 2001
From: Tobias Knopp <tobias@knoppweb.de>
Date: Fri, 6 Dec 2024 21:01:02 +0100
Subject: [PATCH 16/38] server changes for hbridge

---
 src/lib/rp-daq-lib.c       | 32 +++++++++++++++++-
 src/lib/rp-daq-lib.h       |  2 ++
 src/server/control.c       |  2 +-
 src/server/scpi_commands.c | 66 ++++++++++++++++++++++++++++++++++++++
 4 files changed, 100 insertions(+), 2 deletions(-)

diff --git a/src/lib/rp-daq-lib.c b/src/lib/rp-daq-lib.c
index 2e3ecc12..821cb013 100644
--- a/src/lib/rp-daq-lib.c
+++ b/src/lib/rp-daq-lib.c
@@ -653,7 +653,7 @@ int setResyncDAC(int8_t value, int channel, int index) {
 		return -1;
 
 	int bitpos = 14;
-	// Reset bits are in the 14th bit of the respective DAC channel -> 14 and 30 
+	// Reset bits are in the 14th bit of the respective DAC channel -> 14 and 30
 	int offset = 8 * index + channel;
 	// clear the bit
 	*((int16_t *)(pdm_cfg + offset)) &= ~(1u << bitpos);
@@ -1225,6 +1225,36 @@ char* getPinFromInternalPINNumber(const uint32_t pinNumber) {
 	}
 }
 
+int getDIOHBridge(const char* pin) {
+	int pinInternal = getInternalPINNumber(pin);
+	if(pinInternal < 0) {
+		return -3;
+	}
+
+	uint32_t register_value = *((uint8_t *)(cfg + 11));
+	register_value = ((register_value & (0x1 << (pinInternal))) >> (pinInternal));
+
+	return register_value;
+}
+
+int setDIOHBridge(const char* pin, int value) {
+	int pinInternal = getInternalPINNumber(pin);
+	if(pinInternal < 0) {
+		return -3;
+	}
+
+	if(value == DIO_OUT) {
+		*((uint8_t *)(cfg + 11)) &= ~(0x1 << (pinInternal));
+	} else if(value == DIO_IN) {
+		*((uint8_t *)(cfg + 11)) |= (0x1 << (pinInternal));
+	} else {
+		return -1;
+	}
+
+	return 0;
+}
+
+
 int getDIODirection(const char* pin) {
 	int pinInternal = getInternalPINNumber(pin);
 	if(pinInternal < 0) {
diff --git a/src/lib/rp-daq-lib.h b/src/lib/rp-daq-lib.h
index 9dc8378f..e608591b 100644
--- a/src/lib/rp-daq-lib.h
+++ b/src/lib/rp-daq-lib.h
@@ -174,6 +174,8 @@ extern int getDIODirection(const char*);
 extern int setDIODirection(const char*, int);
 extern int setDIO(const char*, int);
 extern int getDIO(const char*);
+extern int getDIOHBridge(const char*);
+extern int setDIOHBridge(const char*, int);
 extern int setTriggerMode(int);
 extern int getTriggerMode();
 extern int setTriggerPropagation(int);
diff --git a/src/server/control.c b/src/server/control.c
index 3e662510..d0e86c8c 100644
--- a/src/server/control.c
+++ b/src/server/control.c
@@ -129,7 +129,7 @@ bool getSequenceEnableValue(sequenceData_t *seqData, int seqStep, int channel) {
 
 bool getSequenceResyncValue(sequenceData_t *seqData, int seqStep, int channel) {
 	bool result = false;
-  	int numChan = numSlowDACChan > 2 ? 2 : numSlowDACChan;
+	int numChan = numSlowDACChan > 2 ? 2 : numSlowDACChan;
 	if (seqData->resyncLUT != NULL && channel < numChan) {
 		int localStep = seqStep % seqData->numStepsPerRepetition;
 		result = seqData->resyncLUT[localStep * numChan + channel];
diff --git a/src/server/scpi_commands.c b/src/server/scpi_commands.c
index b7308745..dd31c1f1 100644
--- a/src/server/scpi_commands.c
+++ b/src/server/scpi_commands.c
@@ -722,6 +722,68 @@ static scpi_result_t RP_DIO_GetDIOOutputP(scpi_t * context) {
 	return RP_DIO_GetDIOOutput(context, true);
 }
 
+
+
+
+static scpi_result_t RP_DIO_SetDIOHBridge(scpi_t * context, bool pinSide) {
+	int32_t numbers[1];
+	SCPI_CommandNumbers(context, numbers, 1, 1);
+	int pin_number = numbers[0];
+	char pin[8];
+	pinSide ? sprintf(pin, "DIO%d_P", pin_number) : sprintf(pin, "DIO%d_N", pin_number);
+
+	int32_t DIO_pin_output_selection;
+	if (!SCPI_ParamChoice(context, onoff_modes, &DIO_pin_output_selection, TRUE)) {
+		return returnSCPIBool(context, false);
+	}
+
+	int result = setDIOHBridge(pin, DIO_pin_output_selection);
+	if (result < 0) {
+		return returnSCPIBool(context, false);
+	}
+
+	return returnSCPIBool(context, true);
+}
+
+static scpi_result_t RP_DIO_SetDIOHBridgeN(scpi_t * context) {
+	return RP_DIO_SetDIOHBridge(context, false);
+}
+
+static scpi_result_t RP_DIO_SetDIOHBridgeP(scpi_t * context) {
+	return RP_DIO_SetDIOHBridge(context, true);
+}
+
+static scpi_result_t RP_DIO_GetDIOHBridge(scpi_t * context, bool pinSide) {
+	int32_t numbers[1];
+	SCPI_CommandNumbers(context, numbers, 1, 1);
+	int pin_number = numbers[0];
+	char pin[8];
+	pinSide ? sprintf(pin, "DIO%d_P", pin_number) : sprintf(pin, "DIO%d_N", pin_number);
+	
+	int result = getDIOHBridge(pin);
+
+	if (result < 0) {
+		return returnSCPIBool(context, false);
+	}
+
+	const char* name;
+	SCPI_ChoiceToName(onoff_modes, result,  &name);
+	SCPI_ResultText(context, name);
+
+	return SCPI_RES_OK;
+}
+
+static scpi_result_t RP_DIO_GetDIOHBridgeN(scpi_t * context) {
+	return RP_DIO_GetDIOHBridge(context, false);
+}
+
+static scpi_result_t RP_DIO_GetDIOHBridgeP(scpi_t * context) {
+	return RP_DIO_GetDIOHBridge(context, true);
+}
+
+
+
+
 static scpi_result_t RP_GetWatchdogMode(scpi_t * context) {
 	const char * name;
 
@@ -1791,6 +1853,10 @@ const scpi_command_t scpi_commands[] = {
 	{.pattern = "RP:DIO:Pin#:SideP", .callback = RP_DIO_SetDIOOutputP,}, 
 	{.pattern = "RP:DIO:Pin#:SideN?", .callback = RP_DIO_GetDIOOutputN,},
 	{.pattern = "RP:DIO:Pin#:SideP?", .callback = RP_DIO_GetDIOOutputP,},
+	{.pattern = "RP:DIO:Pin#:SideN:HBridge", .callback = RP_DIO_SetDIOHBridgeN,},
+	{.pattern = "RP:DIO:Pin#:SideP:HBridge", .callback = RP_DIO_SetDIOHBridgeP,},
+	{.pattern = "RP:DIO:Pin#:SideN:HBridge?", .callback = RP_DIO_GetDIOHBridgeN,},
+	{.pattern = "RP:DIO:Pin#:SideP:HBridge?", .callback = RP_DIO_GetDIOHBridgeP,},
 	{.pattern = "RP:WatchDogMode", .callback = RP_SetWatchdogMode,},
 	{.pattern = "RP:WatchDogMode?", .callback = RP_GetWatchdogMode,},
 	{.pattern = "RP:TRIGger:ALiVe", .callback = RP_SetKeepAliveReset,},

From 7b1528439a4a49761057744079301e7f8312b759 Mon Sep 17 00:00:00 2001
From: Tobias Knopp <tobias@knoppweb.de>
Date: Fri, 6 Dec 2024 21:02:21 +0100
Subject: [PATCH 17/38] change version to 10

---
 src/fpga/bd/bd.tcl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/fpga/bd/bd.tcl b/src/fpga/bd/bd.tcl
index f85d8cfb..d6049ccc 100644
--- a/src/fpga/bd/bd.tcl
+++ b/src/fpga/bd/bd.tcl
@@ -1567,7 +1567,7 @@ proc create_hier_cell_system_1 { parentCell nameHier } {
   # Create instance: image_version, and set properties
   set image_version [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 image_version ]
   set_property -dict [ list \
-   CONFIG.CONST_VAL {9} \
+   CONFIG.CONST_VAL {10} \
    CONFIG.CONST_WIDTH {32} \
  ] $image_version
 

From 0828b19f33a62cd2213475bdda93854be79799e2 Mon Sep 17 00:00:00 2001
From: rp_local <n.a>
Date: Tue, 24 Sep 2024 15:42:18 +0000
Subject: [PATCH 18/38] Init Resync FPGA image

---
 src/fpga/bd/bd.tcl            | 41 ++++++++++++++++++++++++++++++-----
 src/fpga/bd/waveform_gen.tcl  | 26 ++++++++++++++++++----
 src/fpga/hdl/sequence_slice.v |  2 ++
 3 files changed, 59 insertions(+), 10 deletions(-)

diff --git a/src/fpga/bd/bd.tcl b/src/fpga/bd/bd.tcl
index 8e2e13fc..206a1a32 100644
--- a/src/fpga/bd/bd.tcl
+++ b/src/fpga/bd/bd.tcl
@@ -796,6 +796,7 @@ proc create_hier_cell_signal_compose1 { parentCell nameHier } {
   create_bd_pin -dir O -from 0 -to 0 m_axis_data_tvalid_1
   create_bd_pin -dir I -from 15 -to 0 offset
   create_bd_pin -dir O -from 1 -to 0 ramp_state_1
+  create_bd_pin -dir I resync_dac
   create_bd_pin -dir I start_ramp_down
 
   # Create instance: signal_calib_0, and set properties
@@ -899,10 +900,11 @@ proc create_hier_cell_signal_compose1 { parentCell nameHier } {
   connect_bd_net -net disable_dac_1 [get_bd_pins disable_dac] [get_bd_pins signal_composer_0/disable_dac]
   connect_bd_net -net enable_ramping_1 [get_bd_pins enable_ramping] [get_bd_pins signal_ramp_0/enableRamping]
   connect_bd_net -net offset_1 [get_bd_pins offset] [get_bd_pins signal_composer_0/seq]
+  connect_bd_net -net resync_dac_1 [get_bd_pins resync_dac] [get_bd_pins waveform_gen_0/resync] [get_bd_pins waveform_gen_1/resync] [get_bd_pins waveform_gen_2/resync] [get_bd_pins waveform_gen_3/resync]
   connect_bd_net -net rst_ps7_0_125M_peripheral_aresetn [get_bd_pins aresetn] [get_bd_pins signal_ramp_0/aresetn] [get_bd_pins waveform_awg1/aresetn] [get_bd_pins waveform_gen_0/aresetn] [get_bd_pins waveform_gen_1/aresetn] [get_bd_pins waveform_gen_2/aresetn] [get_bd_pins waveform_gen_3/aresetn]
   connect_bd_net -net signal_calib_0_signal_out [get_bd_pins S] [get_bd_pins signal_calib_0/signal_out]
-  connect_bd_net -net signal_cfg_slice_0_calib_limit_lower [get_bd_pins signal_calib_0/calib_limit_lower] [get_bd_pins signal_cfg_slice_0/calib_limit_lower]
-  connect_bd_net -net signal_cfg_slice_0_calib_limit_upper [get_bd_pins signal_calib_0/calib_limit_upper] [get_bd_pins signal_cfg_slice_0/calib_limit_upper]
+  connect_bd_net -net signal_cfg_slice_0_calib_limit_lower [get_bd_pins signal_cfg_slice_0/calib_limit_lower]
+  connect_bd_net -net signal_cfg_slice_0_calib_limit_upper [get_bd_pins signal_cfg_slice_0/calib_limit_upper]
   connect_bd_net -net signal_cfg_slice_0_calib_offset [get_bd_pins signal_calib_0/calib_offset] [get_bd_pins signal_cfg_slice_0/calib_offset]
   connect_bd_net -net signal_cfg_slice_0_calib_scale [get_bd_pins signal_calib_0/calib_scale] [get_bd_pins signal_cfg_slice_0/calib_scale]
   connect_bd_net -net signal_cfg_slice_0_comp_0_amp [get_bd_pins signal_cfg_slice_0/comp_0_amp] [get_bd_pins waveform_gen_0/amplitude]
@@ -990,6 +992,7 @@ proc create_hier_cell_signal_compose { parentCell nameHier } {
   create_bd_pin -dir O -from 0 -to 0 m_axis_data_tvalid_1
   create_bd_pin -dir I -from 15 -to 0 offset
   create_bd_pin -dir O -from 1 -to 0 ramp_state_0
+  create_bd_pin -dir I resync_dac
   create_bd_pin -dir I start_ramp_down
 
   # Create instance: signal_calib_0, and set properties
@@ -1094,9 +1097,10 @@ proc create_hier_cell_signal_compose { parentCell nameHier } {
   connect_bd_net -net disable_dac_1 [get_bd_pins disable_dac] [get_bd_pins signal_composer_0/disable_dac]
   connect_bd_net -net offset_1 [get_bd_pins offset] [get_bd_pins signal_composer_0/seq]
   connect_bd_net -net ramping_enable_1 [get_bd_pins enable_ramping] [get_bd_pins signal_ramp/enableRamping]
+  connect_bd_net -net resync_dac_1 [get_bd_pins resync_dac] [get_bd_pins waveform_gen_0/resync] [get_bd_pins waveform_gen_1/resync] [get_bd_pins waveform_gen_2/resync] [get_bd_pins waveform_gen_3/resync]
   connect_bd_net -net signal_calib_0_signal_out [get_bd_pins S] [get_bd_pins signal_calib_0/signal_out]
-  connect_bd_net -net signal_cfg_slice_0_calib_limit_lower [get_bd_pins signal_calib_0/calib_limit_lower] [get_bd_pins signal_cfg_slice_0/calib_limit_lower]
-  connect_bd_net -net signal_cfg_slice_0_calib_limit_upper [get_bd_pins signal_calib_0/calib_limit_upper] [get_bd_pins signal_cfg_slice_0/calib_limit_upper]
+  connect_bd_net -net signal_cfg_slice_0_calib_limit_lower [get_bd_pins signal_cfg_slice_0/calib_limit_lower]
+  connect_bd_net -net signal_cfg_slice_0_calib_limit_upper [get_bd_pins signal_cfg_slice_0/calib_limit_upper]
   connect_bd_net -net signal_cfg_slice_0_calib_offset [get_bd_pins signal_calib_0/calib_offset] [get_bd_pins signal_cfg_slice_0/calib_offset]
   connect_bd_net -net signal_cfg_slice_0_calib_scale [get_bd_pins signal_calib_0/calib_scale] [get_bd_pins signal_cfg_slice_0/calib_scale]
   connect_bd_net -net signal_cfg_slice_0_comp_0_amp [get_bd_pins signal_cfg_slice_0/comp_0_amp] [get_bd_pins waveform_gen_0/amplitude]
@@ -1576,7 +1580,7 @@ proc create_hier_cell_system_1 { parentCell nameHier } {
   # Create instance: image_version, and set properties
   set image_version [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 image_version ]
   set_property -dict [ list \
-   CONFIG.CONST_VAL {8} \
+   CONFIG.CONST_VAL {9} \
    CONFIG.CONST_WIDTH {32} \
  ] $image_version
 
@@ -2099,6 +2103,7 @@ proc create_hier_cell_sequencer { parentCell nameHier } {
   create_bd_pin -dir I -type rst keep_alive_aresetn
   create_bd_pin -dir O -from 31 -to 0 oa_dac
   create_bd_pin -dir O -from 31 -to 0 pdm_sts
+  create_bd_pin -dir O -from 1 -to 0 resync_dac
   create_bd_pin -dir O -from 1 -to 0 seq_ramp_down
 
   # Create instance: axi_bram_ctrl_0, and set properties
@@ -2251,6 +2256,7 @@ proc create_hier_cell_sequencer { parentCell nameHier } {
   connect_bd_net -net sequence_slice_0_pdm_value_1 [get_bd_pins pdm_2/din] [get_bd_pins sequence_slice_0/pdm_value_1]
   connect_bd_net -net sequence_slice_0_pdm_value_2 [get_bd_pins pdm_3/din] [get_bd_pins sequence_slice_0/pdm_value_2]
   connect_bd_net -net sequence_slice_0_pdm_value_3 [get_bd_pins pdm_4/din] [get_bd_pins sequence_slice_0/pdm_value_3]
+  connect_bd_net -net sequence_slice_0_resync_dac [get_bd_pins resync_dac] [get_bd_pins sequence_slice_0/resync_dac]
   connect_bd_net -net util_vector_logic_7_Res [get_bd_pins dout] [get_bd_pins util_vector_logic_7/Res]
   connect_bd_net -net xlconcat_0_dout [get_bd_pins util_vector_logic_7/Op1] [get_bd_pins xlconcat_0/dout]
   connect_bd_net -net xlconcat_1_dout [get_bd_pins oa_dac] [get_bd_pins xlconcat_1/dout]
@@ -2313,6 +2319,7 @@ proc create_hier_cell_fourier_synth_standard { parentCell nameHier } {
   create_bd_pin -dir I -from 31 -to 0 oa_dac
   create_bd_pin -dir O -from 1 -to 0 ramp_state_0
   create_bd_pin -dir O -from 1 -to 0 ramp_state_1
+  create_bd_pin -dir I -from 1 -to 0 resync_dac
   create_bd_pin -dir I -from 1 -to 0 seq_ramp_down
   create_bd_pin -dir I -from 1 -to 0 start_ramp_down
   create_bd_pin -dir O -from 31 -to 0 synth_tdata
@@ -2405,6 +2412,23 @@ proc create_hier_cell_fourier_synth_standard { parentCell nameHier } {
    CONFIG.DOUT_WIDTH {1} \
  ] $xlslice_5
 
+  # Create instance: xlslice_6, and set properties
+  set xlslice_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_6 ]
+  set_property -dict [ list \
+   CONFIG.DIN_FROM {0} \
+   CONFIG.DIN_TO {0} \
+   CONFIG.DIN_WIDTH {2} \
+ ] $xlslice_6
+
+  # Create instance: xlslice_7, and set properties
+  set xlslice_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_7 ]
+  set_property -dict [ list \
+   CONFIG.DIN_FROM {1} \
+   CONFIG.DIN_TO {1} \
+   CONFIG.DIN_WIDTH {2} \
+   CONFIG.DOUT_WIDTH {1} \
+ ] $xlslice_7
+
   # Create interface connections
   connect_bd_intf_net -intf_net awg_0_bram_1 [get_bd_intf_pins awg_0_bram] [get_bd_intf_pins signal_compose/awg_bram]
   connect_bd_intf_net -intf_net awg_1_bram_1 [get_bd_intf_pins awg_1_bram] [get_bd_intf_pins signal_compose1/awg_bram]
@@ -2422,6 +2446,7 @@ proc create_hier_cell_fourier_synth_standard { parentCell nameHier } {
   connect_bd_net -net enable_ramping_slice_0_start_ramp_down_0 [get_bd_pins enable_ramping_slice_0/start_ramp_down_0] [get_bd_pins signal_compose/start_ramp_down]
   connect_bd_net -net enable_ramping_slice_0_start_ramp_down_1 [get_bd_pins enable_ramping_slice_0/start_ramp_down_1] [get_bd_pins signal_compose1/start_ramp_down]
   connect_bd_net -net oa_dac_1 [get_bd_pins oa_dac] [get_bd_pins xlslice_2/Din] [get_bd_pins xlslice_3/Din]
+  connect_bd_net -net resync_dac_1 [get_bd_pins resync_dac] [get_bd_pins xlslice_6/Din] [get_bd_pins xlslice_7/Din]
   connect_bd_net -net seq_ramp_down_1 [get_bd_pins seq_ramp_down] [get_bd_pins enable_ramping_slice_0/seq_ramp_down]
   connect_bd_net -net signal_compose1_S [get_bd_pins signal_compose1/S] [get_bd_pins xlconcat_2/In1]
   connect_bd_net -net signal_compose1_m_axis_data_tvalid_1 [get_bd_pins signal_compose1/m_axis_data_tvalid_1] [get_bd_pins util_vector_logic_1/Op2]
@@ -2438,6 +2463,8 @@ proc create_hier_cell_fourier_synth_standard { parentCell nameHier } {
   connect_bd_net -net xlslice_3_Dout [get_bd_pins signal_compose/offset] [get_bd_pins xlslice_3/Dout]
   connect_bd_net -net xlslice_4_Dout [get_bd_pins signal_compose/disable_dac] [get_bd_pins xlslice_4/Dout]
   connect_bd_net -net xlslice_5_Dout [get_bd_pins signal_compose1/disable_dac] [get_bd_pins xlslice_5/Dout]
+  connect_bd_net -net xlslice_6_Dout [get_bd_pins signal_compose/resync_dac] [get_bd_pins xlslice_6/Dout]
+  connect_bd_net -net xlslice_7_Dout [get_bd_pins signal_compose1/resync_dac] [get_bd_pins xlslice_7/Dout]
 
   # Restore current instance
   current_bd_instance $oldCurInst
@@ -3391,6 +3418,7 @@ proc create_root_design { parentCell } {
   connect_bd_net -net selectio_wiz_2_clk_out [get_bd_pins clk_wiz_1/clk_in1] [get_bd_pins selectio_wiz_2/clk_out]
   connect_bd_net -net selectio_wiz_2_data_in_to_device [get_bd_pins reset_manager_0/sata_trigger] [get_bd_pins selectio_wiz_2/data_in_to_device]
   connect_bd_net -net sequencer_enable_dac [get_bd_pins fourier_synth_standard/enable_dac] [get_bd_pins sequencer/enable_dac]
+  connect_bd_net -net sequencer_resync_dac [get_bd_pins fourier_synth_standard/resync_dac] [get_bd_pins sequencer/resync_dac]
   connect_bd_net -net sequencer_seq_ramp_down [get_bd_pins fourier_synth_standard/seq_ramp_down] [get_bd_pins sequencer/seq_ramp_down]
   connect_bd_net -net system_FCLK_RESET0_N [get_bd_pins system/FCLK_RESET0_N] [get_bd_pins util_vector_logic_1/Op1]
   connect_bd_net -net system_cfg_data [get_bd_pins fourier_synth_standard/cfg_data] [get_bd_pins system/dac_cfg]
@@ -3434,7 +3462,6 @@ proc create_root_design { parentCell } {
   # Restore current instance
   current_bd_instance $oldCurInst
 
-  validate_bd_design
   save_bd_design
 }
 # End of create_root_design()
@@ -3447,3 +3474,5 @@ proc create_root_design { parentCell } {
 create_root_design ""
 
 
+common::send_gid_msg -ssname BD::TCL -id 2053 -severity "WARNING" "This Tcl script was generated from a block design that has not been validated. It is possible that design <$design_name> may result in errors during validation."
+
diff --git a/src/fpga/bd/waveform_gen.tcl b/src/fpga/bd/waveform_gen.tcl
index f56db04a..ac9b77b2 100644
--- a/src/fpga/bd/waveform_gen.tcl
+++ b/src/fpga/bd/waveform_gen.tcl
@@ -128,6 +128,7 @@ xilinx.com:ip:dds_compiler:6.0\
 xilinx.com:ip:mult_gen:12.0\
 jbeuke:user:signal_generator:1.0\
 xilinx.com:ip:xlconcat:2.1\
+xilinx.com:ip:xlconstant:1.1\
 "
 
    set list_ips_missing ""
@@ -203,12 +204,13 @@ proc create_root_design { parentCell } {
   set freq [ create_bd_port -dir I -from 47 -to 0 freq ]
   set m_axis_data_tvalid_1 [ create_bd_port -dir O m_axis_data_tvalid_1 ]
   set phase [ create_bd_port -dir I -from 47 -to 0 phase ]
+  set resync [ create_bd_port -dir I resync ]
   set wave [ create_bd_port -dir O -from 15 -to 0 -type data wave ]
 
   # Create instance: axis_variable_A_channel_1, and set properties
   set axis_variable_A_channel_1 [ create_bd_cell -type ip -vlnv pavel-demin:user:axis_variable:1.0 axis_variable_A_channel_1 ]
   set_property -dict [ list \
-   CONFIG.AXIS_TDATA_WIDTH {96} \
+   CONFIG.AXIS_TDATA_WIDTH {104} \
  ] $axis_variable_A_channel_1
 
   # Create instance: dds_compiler_A_channel_1, and set properties
@@ -233,10 +235,11 @@ proc create_root_design { parentCell } {
    CONFIG.POFF1 {0} \
    CONFIG.Parameter_Entry {System_Parameters} \
    CONFIG.PartsPresent {Phase_Generator_and_SIN_COS_LUT} \
-   CONFIG.Phase_Increment {Programmable} \
+   CONFIG.Phase_Increment {Streaming} \
    CONFIG.Phase_Offset_Angles1 {0} \
    CONFIG.Phase_Width {48} \
-   CONFIG.Phase_offset {Programmable} \
+   CONFIG.Phase_offset {Streaming} \
+   CONFIG.Resync {true} \
    CONFIG.S_PHASE_Has_TUSER {Not_Required} \
    CONFIG.Spurious_Free_Dynamic_Range {84} \
  ] $dds_compiler_A_channel_1
@@ -261,15 +264,27 @@ proc create_root_design { parentCell } {
    CONFIG.CFG_DATA_WIDTH {48} \
  ] $signal_generator_0
 
+  # Create instance: xlconcat_0, and set properties
+  set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ]
+
   # Create instance: xlconcat_A_channel_1, and set properties
   set xlconcat_A_channel_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_A_channel_1 ]
   set_property -dict [ list \
    CONFIG.IN0_WIDTH {48} \
    CONFIG.IN1_WIDTH {48} \
+   CONFIG.IN2_WIDTH {8} \
+   CONFIG.NUM_PORTS {3} \
  ] $xlconcat_A_channel_1
 
+  # Create instance: xlconstant_0, and set properties
+  set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
+  set_property -dict [ list \
+   CONFIG.CONST_VAL {0} \
+   CONFIG.CONST_WIDTH {7} \
+ ] $xlconstant_0
+
   # Create interface connections
-  connect_bd_intf_net -intf_net axis_variable_A_channel_1_M_AXIS [get_bd_intf_pins axis_variable_A_channel_1/M_AXIS] [get_bd_intf_pins dds_compiler_A_channel_1/S_AXIS_CONFIG]
+  connect_bd_intf_net -intf_net axis_variable_A_channel_1_M_AXIS [get_bd_intf_pins axis_variable_A_channel_1/M_AXIS] [get_bd_intf_pins dds_compiler_A_channel_1/S_AXIS_PHASE]
   connect_bd_intf_net -intf_net dds_compiler_A_channel_1_M_AXIS_DATA [get_bd_intf_pins dds_compiler_A_channel_1/M_AXIS_DATA] [get_bd_intf_pins signal_generator_0/s_axis]
   connect_bd_intf_net -intf_net dds_compiler_A_channel_1_M_AXIS_PHASE [get_bd_intf_pins dds_compiler_A_channel_1/M_AXIS_PHASE] [get_bd_intf_pins signal_generator_0/s_axis_phase]
 
@@ -280,10 +295,13 @@ proc create_root_design { parentCell } {
   connect_bd_net -net mult_gen_0_P [get_bd_ports wave] [get_bd_pins mult_gen_0/P]
   connect_bd_net -net phase_1 [get_bd_ports phase] [get_bd_pins xlconcat_A_channel_1/In1]
   connect_bd_net -net phase_A_channel_1_slice1_Dout [get_bd_ports cfg_data] [get_bd_pins signal_generator_0/cfg_data]
+  connect_bd_net -net resync_1 [get_bd_ports resync] [get_bd_pins xlconcat_0/In0]
   connect_bd_net -net rst_ps7_0_125M_peripheral_aresetn [get_bd_ports aresetn] [get_bd_pins axis_variable_A_channel_1/aresetn] [get_bd_pins dds_compiler_A_channel_1/aresetn] [get_bd_pins signal_generator_0/aresetn]
   connect_bd_net -net signal_generator_0_m_axis_tdata [get_bd_pins mult_gen_0/B] [get_bd_pins signal_generator_0/m_axis_tdata]
   connect_bd_net -net signal_generator_0_m_axis_tvalid [get_bd_ports m_axis_data_tvalid_1] [get_bd_pins signal_generator_0/m_axis_tvalid]
+  connect_bd_net -net xlconcat_0_dout [get_bd_pins xlconcat_0/dout] [get_bd_pins xlconcat_A_channel_1/In2]
   connect_bd_net -net xlconcat_A_channel_1_dout [get_bd_pins axis_variable_A_channel_1/cfg_data] [get_bd_pins xlconcat_A_channel_1/dout]
+  connect_bd_net -net xlconstant_0_dout [get_bd_pins xlconcat_0/In1] [get_bd_pins xlconstant_0/dout]
 
   # Create address segments
 
diff --git a/src/fpga/hdl/sequence_slice.v b/src/fpga/hdl/sequence_slice.v
index 7e3f15f8..67b36e07 100644
--- a/src/fpga/hdl/sequence_slice.v
+++ b/src/fpga/hdl/sequence_slice.v
@@ -11,6 +11,7 @@ module sequence_slice(
     output [10:0] pdm_value_2,
     output [10:0] pdm_value_3,
     output [1:0] enable_dac,
+    output [1:0] resync_dac,
     output [3:0] enable_pdm,
     output [1:0] enable_dac_ramp_down
 );
@@ -41,6 +42,7 @@ assign pdm_value_3[10:0] = seq_data_int[90:80];
 // Flags
 assign enable_dac[1:0] = seq_data_int[97:96];
 assign enable_pdm[3:0] = seq_data_int[101:98];
+assign resync_dac[1:0] = seq_data_init[31:30];
 assign enable_dac_ramp_down[0] = seq_data_int[112];
 assign enable_dac_ramp_down[1] = seq_data_int[113];
 

From 49de96b9e3c9fbe7e6719344a39cefb9882df322 Mon Sep 17 00:00:00 2001
From: rp_local <n.a>
Date: Tue, 24 Sep 2024 15:42:44 +0000
Subject: [PATCH 19/38] Init resync rp-lib

---
 src/lib/rp-daq-lib.c | 26 ++++++++++++++++++++++++++
 src/lib/rp-daq-lib.h |  2 ++
 2 files changed, 28 insertions(+)

diff --git a/src/lib/rp-daq-lib.c b/src/lib/rp-daq-lib.c
index c588f7ac..9c495034 100644
--- a/src/lib/rp-daq-lib.c
+++ b/src/lib/rp-daq-lib.c
@@ -637,6 +637,32 @@ int setEnableDAC(int8_t value, int channel, int index) {
 	return 0;
 }
 
+int setResyncDACAll(int8_t value, int channel) {
+	for(int i=0; i<PDM_BUFF_SIZE; i++) {
+		setResyncDAC(value,channel,i);
+	}
+	return 0;
+}
+
+int setResyncDAC(int8_t value, int channel, int index) {
+	if(channel < 0 || channel >= 2) {
+		return -2;
+	}
+
+	if (value < 0 || value >= 2)
+		return -1;
+
+	int bitpos = 14 + channel;
+	// Reset bit is in the 2-th channel
+	int offset = 8 * index + 2;
+	// clear the bit
+	*((int16_t *)(pdm_cfg + offset)) &= ~(1u << bitpos);
+	// set the bit
+	*((int16_t *)(pdm_cfg + offset)) |= (value << bitpos);
+	//printf("%d reset pdm\n", *((int16_t *)(pdm_cfg + 2*(0+4*index))));
+	return 0;
+}
+
 int setResetDAC(int8_t value, int index) {
 	if (value < 0 || value >= 2)
 		return -1;
diff --git a/src/lib/rp-daq-lib.h b/src/lib/rp-daq-lib.h
index 691bd70c..f7cf6bcc 100644
--- a/src/lib/rp-daq-lib.h
+++ b/src/lib/rp-daq-lib.h
@@ -143,6 +143,8 @@ extern uint32_t getXADCValue(int);
 extern float getXADCValueVolt(int);
 extern int setEnableDACAll(int8_t, int);
 extern int setEnableDAC(int8_t, int, int);
+extern int setResyncDACAll(int8_t, int);
+extern int setResyncDAC(int8_t, int, int);
 //extern int setResetDAC(int8_t, int);
 extern int setRampDownDAC(int8_t, int, int);
 extern int setRampDownDACAll(int8_t, int);

From 48635989f31157c56103c7db9a1c364025647cd9 Mon Sep 17 00:00:00 2001
From: rp_local <n.a>
Date: Tue, 24 Sep 2024 15:43:00 +0000
Subject: [PATCH 20/38] Init resync server

---
 src/server/control.c         | 19 +++++++++++++++++++
 src/server/daq_server_scpi.h |  2 ++
 src/server/scpi_commands.c   | 26 ++++++++++++++++++++++++++
 3 files changed, 47 insertions(+)

diff --git a/src/server/control.c b/src/server/control.c
index 05ef096a..07868075 100644
--- a/src/server/control.c
+++ b/src/server/control.c
@@ -46,6 +46,7 @@ sequenceData_t * allocSequence() {
 	seq->enableLUT = NULL;
 	seq->rampUp = NULL;
 	seq->rampDown = NULL;
+	seq->resyncLUT = NULL;
 	return seq; 
 }
 
@@ -66,6 +67,10 @@ void freeSequence(sequenceData_t *seqData) {
 		freeRamping(seqData->rampDown);
 		seqData->rampDown = NULL;
 	}
+	if (seqData->resyncLUT != NULL) {
+		free(seqData->resyncLUT);
+		seqData->resyncLUT = NULL;
+	}
 }
 
 rampingData_t * allocRamping() {
@@ -123,6 +128,15 @@ bool getSequenceEnableValue(sequenceData_t *seqData, int seqStep, int channel) {
 	return result;
 }
 
+bool getSequenceResyncValue(sequenceData_t *seqData, int seqStep, int channel) {
+	bool result = false;
+	if (seqData->resyncLUT != NULL) {
+		int localStep = seqStep % seqData->numStepsPerRepetition;
+		result = seqData->resyncLUT[localStep + channel];
+	}
+	return result;
+}
+
 float getRampingValue(rampingData_t *rampData, int rampStep, int channel) {
 	int localStep = rampStep % rampData->numStepsPerRepetition;
 	return rampData->LUT[localStep * numSlowDACChan + channel];
@@ -219,6 +233,7 @@ static void setLUTValuesFor(int futureStep, int channel, int currPDMIndex) {
 	float val = 0.0;
 	bool enable = true;
 	bool rampDown = false;
+	bool resync = false;
 
 	switch(interval) {
 		case RAMPUP:
@@ -227,6 +242,7 @@ static void setLUTValuesFor(int futureStep, int channel, int currPDMIndex) {
 		case REGULAR:
 			val = getSequenceValue(activeSequence, localStep, channel);
 			enable = getSequenceEnableValue(activeSequence, localStep, channel);
+			resync = getSequenceResyncValue(activeSequence, localStep, channel);
 			break;
 		case RAMPDOWN:
 			val = getRampingValue(activeSequence->rampDown, localStep, channel);
@@ -243,6 +259,9 @@ static void setLUTValuesFor(int futureStep, int channel, int currPDMIndex) {
 		printf("Could not set AO[%d] voltage.\n", channel);	
 	}
 	setEnableDAC(enable, channel, currPDMIndex);
+	if (channel < 2) {
+		setResyncDAC(resync, channel, currPDMIndex);
+	}
 	setRampDownDAC(rampDown, channel, currPDMIndex);
 
 }
diff --git a/src/server/daq_server_scpi.h b/src/server/daq_server_scpi.h
index 4fdf6f08..08e9adf2 100644
--- a/src/server/daq_server_scpi.h
+++ b/src/server/daq_server_scpi.h
@@ -107,6 +107,7 @@ typedef struct {
 	int numStepsPerRepetition; // How many steps per repetition
 	float* LUT; // LUT for value function pointer
 	bool * enableLUT;
+	bool * resyncLUT;
 	rampingData_t* rampUp;
 	rampingData_t* rampDown;
 } sequenceData_t;
@@ -131,6 +132,7 @@ extern sequenceInterval_t computeInterval(sequenceData_t *seqData, int step);
 extern bool isSequenceConfigurable();
 extern float getSequenceValue(sequenceData_t *seqData, int seqStep, int channel);
 extern bool getSequenceEnableValue(sequenceData_t *seqData, int seqStep, int channel);
+extern bool getSequenceResyncValue(sequenceData_t *seqData, int seqStep, int channel);
 extern float getRampingValue(rampingData_t *rampData, int rampStep, int channel);
 extern int getRampUpSteps(sequenceData_t *seqData);
 extern int getRampDownSteps(sequenceData_t *seqData);
diff --git a/src/server/scpi_commands.c b/src/server/scpi_commands.c
index 7629ba5b..6025297e 100644
--- a/src/server/scpi_commands.c
+++ b/src/server/scpi_commands.c
@@ -1056,6 +1056,31 @@ static scpi_result_t RP_DAC_SetEnableLUT(scpi_t * context) {
 	}
 }
 
+static scpi_result_t RP_DAC_SetResyncLUT(scpi_t * context) {
+
+	readyConfigSequence();
+
+	if(configSeq->LUT != NULL && numSlowDACChan > 0 && isSequenceConfigurable()) {
+		if(configSeq->resyncLUT != NULL) {
+			free(configSeq->resyncLUT);
+			configSeq->resyncLUT = NULL;
+		}
+
+		int numChan = numSlowDACChan > 2 ? 2 : numSlowDACChan;
+		printf("Allocating ressyncLUT\n");
+		configSeq->resyncLUT = (bool *)calloc(numChan, configSeq->numStepsPerRepetition * sizeof(bool));
+
+		int n = readAll(newdatasockfd, configSeq->resyncLUT, numSlowDACChan * configSeq->numStepsPerRepetition * sizeof(bool));
+		seqState = CONFIG;
+		if (n < 0) perror("ERROR reading from socket");
+		return returnSCPIBool(context, true);
+	}
+	else {
+		return returnSCPIBool(context, false);
+	}
+
+}
+
 static scpi_result_t RP_DAC_SetUpLUT(scpi_t * context) {
 
 	readyConfigSequence();
@@ -1739,6 +1764,7 @@ const scpi_command_t scpi_commands[] = {
 	{.pattern = "RP:DAC:SEQ:CHan?", .callback = RP_DAC_GetNumSlowDACChan,},
 	{.pattern = "RP:DAC:SEQ:LUT", .callback = RP_DAC_SetValueLUT,},
 	{.pattern = "RP:DAC:SEQ:LUT:ENaBle", .callback = RP_DAC_SetEnableLUT,},
+	{.pattern = "RP:DAC:SEQ:LUT:ReSYNC", .callback = RP_DAC_SetResyncLUT,},
 	{.pattern = "RP:DAC:SEQ:LUT:UP", .callback = RP_DAC_SetUpLUT,},
 	{.pattern = "RP:DAC:SEQ:LUT:DOWN", .callback = RP_DAC_SetDownLUT,},
 	{.pattern = "RP:DAC:SEQ:SET", .callback = RP_DAC_SetSequence,},

From e2685b2daeeea02bf081abef4d62f8d4ea71f96c Mon Sep 17 00:00:00 2001
From: rp_local <n.a>
Date: Tue, 24 Sep 2024 15:43:11 +0000
Subject: [PATCH 21/38] Init resync julia client

---
 src/client/julia/src/Sequence.jl | 52 ++++++++++++++++++++++++--------
 1 file changed, 40 insertions(+), 12 deletions(-)

diff --git a/src/client/julia/src/Sequence.jl b/src/client/julia/src/Sequence.jl
index db223879..25054eef 100644
--- a/src/client/julia/src/Sequence.jl
+++ b/src/client/julia/src/Sequence.jl
@@ -134,17 +134,19 @@ abstract type RampingSequence <: AbstractSequence end
 struct SimpleRampingSequence <: AbstractSequence 
   lut::SequenceLUT
   enable::Union{Array{Bool}, Nothing}
+  resync::Union{Array{Bool}, Nothing}
   rampUp::SequenceLUT
   rampDown::SequenceLUT
-  function SimpleRampingSequencee(lut::SequenceLUT, up::SequenceLUT, down::SequenceLUT, enable::Union{Array{Bool}, Nothing}=nothing)
+  function SimpleRampingSequencee(lut::SequenceLUT, up::SequenceLUT, down::SequenceLUT, enable::Union{Array{Bool}, Nothing}=nothing, resync::Union{Array{Bool}, Nothing}=nothing)
     if !isnothing(enable) && size(values(lut)) != size(enable)
       throw(DimensionMismatch("Size of enable LUT does not match size of value LUT"))
     end
-    return new(SequenceLUT(lut, repetitions), enable, up, down)
+    return new(SequenceLUT(lut, repetitions), enable, resync, up, down)
   end
 end
 
 enableLUT(seq::SimpleRampingSequence) = seq.enable
+resyncLUT(seq::SimpleRampingSequence) = seq.resync
 valueLUT(seq::SimpleRampingSequence) = seq.lut
 rampUpLUT(seq::SimpleRampingSequence) = nothing
 rampDownLUT(seq::SimpleRampingSequence) = nothing
@@ -158,6 +160,7 @@ end
 struct HoldBorderRampingSequence <: RampingSequence
   lut::SequenceLUT
   enable::Union{Array{Bool}, Nothing}
+  resync::Union{Array{Bool}, Nothing}
   rampUp::SequenceLUT
   rampDown::SequenceLUT
 
@@ -170,13 +173,13 @@ struct HoldBorderRampingSequence <: RampingSequence
   - `lut`,`repetitions`,`enable` are used the same as for a `SimpleSequence`
   - `rampingSteps` is the number of steps the first and last value of the given sequence are repeated before the sequence is started
   """
-  function HoldBorderRampingSequence(lut::Array{Float32}, repetitions::Integer, rampingSteps::Integer, enable::Union{Array{Bool}, Nothing}=nothing)
+  function HoldBorderRampingSequence(lut::Array{Float32}, repetitions::Integer, rampingSteps::Integer, enable::Union{Array{Bool}, Nothing}=nothing, resync::Union{Array{Bool}, Nothing}=nothing)
     if !isnothing(enable) && size(lut) != size(enable)
       throw(DimensionMismatch("Size of enable LUT does not match size of value LUT"))
     end
     up = SequenceLUT(lut[:, 1], rampingSteps)
     down = SequenceLUT(lut[:, end], rampingSteps)
-    return new(SequenceLUT(lut, repetitions), enable, up, down)
+    return new(SequenceLUT(lut, repetitions), enable, resync, up, down)
   end
 end
 
@@ -190,6 +193,7 @@ function HoldBorderRampingSequence(rp::RedPitaya, lut, repetitions, enable=nothi
 end
 
 enableLUT(seq::HoldBorderRampingSequence) = seq.enable
+resyncLUT(seq::HoldBorderRampingSequence) = seq.resync
 valueLUT(seq::HoldBorderRampingSequence) = seq.lut
 rampUpLUT(seq::HoldBorderRampingSequence) = seq.rampUp
 rampDownLUT(seq::HoldBorderRampingSequence) = seq.rampDown
@@ -197,14 +201,15 @@ rampDownLUT(seq::HoldBorderRampingSequence) = seq.rampDown
 struct ConstantRampingSequence <: RampingSequence
   lut::SequenceLUT
   enable::Union{Array{Bool}, Nothing}
+  resync::Union{Array{Bool}, Nothing}
   ramping::SequenceLUT
 
-  function ConstantRampingSequence(lut::Array{Float32}, repetitions::Integer, rampingValue::Float32, rampingSteps::Integer, enable::Union{Array{Bool}, Nothing}=nothing)
+  function ConstantRampingSequence(lut::Array{Float32}, repetitions::Integer, rampingValue::Float32, rampingSteps::Integer, enable::Union{Array{Bool}, Nothing}=nothing, resync::Union{Array{Bool}, Nothing}=nothing)
     if !isnothing(enable) && size(lut) != size(enable)
       throw(DimensionMismatch("Size of enable LUT does not match size of value LUT"))
     end
     rampingLut = SequenceLUT([rampingValue for i = 1:size(lut, 1)], rampingSteps)
-    return new(SequenceLUT(lut, repetitions), enable, rampingLut)
+    return new(SequenceLUT(lut, repetitions), enable, resync, rampingLut)
   end
 end
 ConstantRampingSequence(lut::Array{T}, repetitions::Integer, rampingValue::Real, rampingSteps::Integer, enable::Union{Array{Bool}, Nothing}=nothing) where T <: Real = ConstantRampingSequence(map(Float32, lut), repetitions, Float32(rampingValue), rampingSteps, enable)
@@ -212,6 +217,7 @@ ConstantRampingSequence(lut::Vector{Float32}, repetitions::Integer, rampingValue
 ConstantRampingSequence(lut::Vector{T}, repetitions::Integer, rampingValue::Real, rampingSteps::Integer, enable::Union{Array{Bool}, Nothing}=nothing) where T <: Real = ConstantRampingSequence(reshape(lut, 1, :), repetitions, rampingValue, rampingSteps, enable)
 
 enableLUT(seq::ConstantRampingSequence) = seq.enable
+resyncLUT(seq::ConstantRampingSequence) = seq.resync
 valueLUT(seq::ConstantRampingSequence) = seq.lut
 rampUpLUT(seq::ConstantRampingSequence) = seq.ramping
 rampDownLUT(seq::ConstantRampingSequence) = seq.ramping
@@ -219,9 +225,10 @@ rampDownLUT(seq::ConstantRampingSequence) = seq.ramping
 struct StartUpSequence <: RampingSequence
   lut::SequenceLUT
   enable::Union{Array{Bool}, Nothing}
+  resync::Union{Array{Bool}, Nothing}
   rampUp::SequenceLUT
   rampDown::SequenceLUT
-  function StartUpSequence(lut::Array{Float32}, repetitions::Integer, rampingSteps::Integer, startUpSteps::Integer, enable::Union{Array{Bool}, Nothing}=nothing)
+  function StartUpSequence(lut::Array{Float32}, repetitions::Integer, rampingSteps::Integer, startUpSteps::Integer, enable::Union{Array{Bool}, Nothing}=nothing, resync::Union{Array{Bool}, Nothing}=nothing)
     if !isnothing(enable) && size(lut) != size(enable)
       throw(DimensionMismatch("Size of enable LUT does not match size of value LUT"))
     end
@@ -239,7 +246,7 @@ struct StartUpSequence <: RampingSequence
     end
     up = SequenceLUT(upLut, 1)
     down = SequenceLUT(lut[:, end], rampingSteps)
-    return new(SequenceLUT(lut, repetitions), enable, up, down)
+    return new(SequenceLUT(lut, repetitions), enable, resync, up, down)
   end
 end
 StartUpSequence(lut::Array{T}, repetitions::Integer, rampingSteps::Integer, startUpSteps::Integer, enable::Union{Array{Bool}, Nothing}=nothing) where T <: Real = StartUpSequence(map(Float32, lut), repetitions, rampingSteps, startUpSteps, enable)
@@ -247,6 +254,7 @@ StartUpSequence(lut::Array{T}, repetitions::Integer, rampingSteps::Integer, star
 StartUpSequence(lut::Vector{T}, repetitions::Integer, rampingSteps::Integer, startUpSteps::Integer, enable::Union{Array{Bool}, Nothing}=nothing) where T <: Real = StartUpSequence(reshape(lut, 1, :), repetitions, rampingSteps, startUpSteps, enable)
 
 enableLUT(seq::StartUpSequence) = seq.enable
+resyncLUT(seq::StartUpSequence) = seq.resync
 valueLUT(seq::StartUpSequence) = seq.lut
 rampUpLUT(seq::StartUpSequence) = seq.rampUp
 rampDownLUT(seq::StartUpSequence) = seq.rampDown
@@ -269,10 +277,11 @@ Transmit the client-side representation `seq` to the server and append it to the
 """
 function sequence!(rp::RedPitaya, seq::AbstractSequence)
   result = true
-  result &= valueLUT!(rp, valueLUT(seq))
-  result &= enableLUT!(rp, enableLUT(seq))
-  result &= rampUpLUT!(rp, rampUpLUT(seq))
-  result &= rampDownLUT!(rp, rampDownLUT(seq))
+  result &= valueLUT!(rp, seq)
+  result &= enableLUT!(rp, seq)
+  result &= resyncLUT!(rp, seq)
+  result &= rampUpLUT!(rp, seq)
+  result &= rampDownLUT!(rp, seq)
   result &= setSequence!(rp)
   return result
 end
@@ -283,11 +292,13 @@ function transmitLUT!(rp::RedPitaya, lut::Array{Float32}, cmd::String, repetitio
   return parse(Bool, receive(rp))
 end
 
+valueLUT!(rp::RedPitaya, lut::AbstractSequence) = valueLUT!(rp, valueLUT(lut))
 function valueLUT!(rp::RedPitaya, lut::SequenceLUT)
   lutFloat32 = map(Float32, values(lut))
   return transmitLUT!(rp, lutFloat32, "RP:DAC:SEQ:LUT", repetitions(lut))
 end
 
+rampUpLUT!(rp::RedPitaya, lut::AbstractSequence) = rampUpLUT!(rp, rampUpLUT(lut))
 function rampUpLUT!(rp::RedPitaya, lut::SequenceLUT)
   lutFloat32 = map(Float32, values(lut))
   return transmitLUT!(rp, lutFloat32, "RP:DAC:SEQ:LUT:UP", repetitions(lut))
@@ -298,6 +309,7 @@ function rampUpLUT!(rp::RedPitaya, lut::Nothing)
   return true
 end
 
+rampDownLUT!(rp::RedPitaya, lut::AbstractSequence) = rampDownLUT!(rp, rampDownLUT(lut))
 function rampDownLUT!(rp::RedPitaya, lut::SequenceLUT)
   lutFloat32 = map(Float32, values(lut))
   return transmitLUT!(rp, lutFloat32, "RP:DAC:SEQ:LUT:DOWN", repetitions(lut))
@@ -308,6 +320,7 @@ function rampDownLUT!(rp::RedPitaya, lut::Nothing)
   return true
 end
 
+enableLUT!(rp::RedPitaya, lut::AbstractSequence) = enableLUT!(rp, enableLUT(lut))
 function enableLUT!(rp::RedPitaya, lut::Array)
   lutBool = map(Bool, lut)
   send(rp, string("RP:DAC:SEQ:LUT:ENaBle"))
@@ -322,6 +335,21 @@ function enableLUT!(rp::RedPitaya, lut::Nothing)
   return true
 end
 
+resyncLUT!(rp::RedPitaya, lut::AbstractSequence) = resyncLUT!(rp, resyncLUT(lut))
+function resyncLUT!(rp::RedPitaya, lut::Array)
+  lutBool = map(Bool, lut)
+  send(rp, string("RP:DAC:SEQ:LUT:ReSYNC"))
+  @debug "Writing resync DAC LUT"
+  write(rp.dataSocket, lutBool)
+  reply = receive(rp)
+  return parse(Bool, reply)
+end
+
+function resyncLUT!(rp::RedPitaya, lut::Nothing)
+  # NOP
+  return true
+end
+
 function seqTiming(seq::AbstractSequence)
   up = 0
   if !isnothing(rampUpLUT(seq)) 

From b78f39db2fda4f91ae771cb76fae63a59b37429e Mon Sep 17 00:00:00 2001
From: rp_local <n.a>
Date: Tue, 24 Sep 2024 15:54:25 +0000
Subject: [PATCH 22/38] Fix variable name in seq_data_int

---
 src/fpga/hdl/sequence_slice.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/fpga/hdl/sequence_slice.v b/src/fpga/hdl/sequence_slice.v
index 67b36e07..ab2e91a5 100644
--- a/src/fpga/hdl/sequence_slice.v
+++ b/src/fpga/hdl/sequence_slice.v
@@ -42,7 +42,7 @@ assign pdm_value_3[10:0] = seq_data_int[90:80];
 // Flags
 assign enable_dac[1:0] = seq_data_int[97:96];
 assign enable_pdm[3:0] = seq_data_int[101:98];
-assign resync_dac[1:0] = seq_data_init[31:30];
+assign resync_dac[1:0] = seq_data_int[31:30];
 assign enable_dac_ramp_down[0] = seq_data_int[112];
 assign enable_dac_ramp_down[1] = seq_data_int[113];
 

From 06353ea3d1c2a61ffad5d0e25c0b9571a309b867 Mon Sep 17 00:00:00 2001
From: rp_local <n.a>
Date: Wed, 25 Sep 2024 16:05:18 +0000
Subject: [PATCH 23/38] Init working resync based on aresetn

---
 src/client/julia/Project.toml    |  2 +-
 src/client/julia/src/Sequence.jl | 12 +++++----
 src/fpga/bd/bd.tcl               |  9 +++++--
 src/fpga/bd/waveform_gen.tcl     | 45 ++++++++++++++++++--------------
 src/lib/rp-daq-lib.c             |  5 ++--
 src/server/control.c             |  1 +
 6 files changed, 44 insertions(+), 30 deletions(-)

diff --git a/src/client/julia/Project.toml b/src/client/julia/Project.toml
index 654c97b0..26393c4d 100644
--- a/src/client/julia/Project.toml
+++ b/src/client/julia/Project.toml
@@ -1,7 +1,7 @@
 name = "RedPitayaDAQServer"
 uuid = "c544963a-496b-56d4-a5fe-f99a3f174c8f"
 authors = ["Tobias Knopp <tobias@knoppweb.de>"]
-version = "0.8.2"
+version = "0.9.0"
 
 [deps]
 LinearAlgebra = "37e2e46d-f89d-539d-b4ee-838fcccc9c8e"
diff --git a/src/client/julia/src/Sequence.jl b/src/client/julia/src/Sequence.jl
index 25054eef..7b197ed5 100644
--- a/src/client/julia/src/Sequence.jl
+++ b/src/client/julia/src/Sequence.jl
@@ -103,7 +103,8 @@ Struct representing a sequence in which the server directly takes the values fro
 """
 struct SimpleSequence <: AbstractSequence
   lut::SequenceLUT
-  enable::Union{Array{Bool}, Nothing}
+  enable::Union{Matrix{Bool}, Nothing}
+  resync::Union{Matrix{Bool}, Nothing}
   """
     SimpleSequence(lut, repetitions, enable=nothing)
 
@@ -114,17 +115,18 @@ struct SimpleSequence <: AbstractSequence
   - `repetitions::Int32`: the number of times the sequence should be repeated
   - `emable::Union{Array{Bool}, Nothing}`: matrix containing enable flags
   """
-  function SimpleSequence(lut::Array{Float32}, repetitions::Integer, enable::Union{Array{Bool}, Nothing}=nothing)
+  function SimpleSequence(lut::Matrix{Float32}, repetitions::Integer, enable::Union{Matrix{Bool}, Nothing}=nothing, resync::Union{Matrix{Bool}, Nothing} = nothing)
     if !isnothing(enable) && size(lut) != size(enable)
       throw(DimensionMismatch("Size of enable LUT does not match size of value LUT"))
     end
-    return new(SequenceLUT(lut, repetitions), enable)
+    return new(SequenceLUT(lut, repetitions), enable, resync)
   end
 end
-SimpleSequence(lut::Array{T}, repetitions::Integer, enable::Union{Array{Bool}, Nothing}=nothing) where T <: Real = SimpleSequence(map(Float32, lut), repetitions, enable)
-SimpleSequence(lut::Vector{T}, repetitions::Integer, enable::Union{Array{Bool}, Nothing}=nothing) where T <: Real = SimpleSequence(reshape(lut, 1, :), repetitions, enable)
+SimpleSequence(lut::Array{T}, repetitions::Integer, args...) where T <: Real = SimpleSequence(map(Float32, lut), repetitions, args...)
+SimpleSequence(lut::Vector{T}, repetitions::Integer, args...) where T <: Real = SimpleSequence(reshape(lut, 1, :), repetitions, args...)
 
 enableLUT(seq::SimpleSequence) = seq.enable
+resyncLUT(seq::SimpleSequence) = seq.resync
 valueLUT(seq::SimpleSequence) = seq.lut
 rampUpLUT(seq::SimpleSequence) = nothing
 rampDownLUT(seq::SimpleSequence) = nothing
diff --git a/src/fpga/bd/bd.tcl b/src/fpga/bd/bd.tcl
index 206a1a32..e9ae2bab 100644
--- a/src/fpga/bd/bd.tcl
+++ b/src/fpga/bd/bd.tcl
@@ -402,6 +402,9 @@ proc create_hier_cell_waveform_awg1 { parentCell nameHier } {
   
   # Create instance: xlconcat_0, and set properties
   set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ]
+  set_property -dict [ list \
+   CONFIG.IN0_WIDTH {48} \
+ ] $xlconcat_0
 
   # Create instance: xlconstant_0, and set properties
   set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
@@ -572,6 +575,9 @@ proc create_hier_cell_waveform_awg { parentCell nameHier } {
   
   # Create instance: xlconcat_0, and set properties
   set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ]
+  set_property -dict [ list \
+   CONFIG.IN0_WIDTH {48} \
+ ] $xlconcat_0
 
   # Create instance: xlconstant_0, and set properties
   set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
@@ -3462,6 +3468,7 @@ proc create_root_design { parentCell } {
   # Restore current instance
   current_bd_instance $oldCurInst
 
+  validate_bd_design
   save_bd_design
 }
 # End of create_root_design()
@@ -3474,5 +3481,3 @@ proc create_root_design { parentCell } {
 create_root_design ""
 
 
-common::send_gid_msg -ssname BD::TCL -id 2053 -severity "WARNING" "This Tcl script was generated from a block design that has not been validated. It is possible that design <$design_name> may result in errors during validation."
-
diff --git a/src/fpga/bd/waveform_gen.tcl b/src/fpga/bd/waveform_gen.tcl
index ac9b77b2..8b6070f9 100644
--- a/src/fpga/bd/waveform_gen.tcl
+++ b/src/fpga/bd/waveform_gen.tcl
@@ -127,8 +127,8 @@ pavel-demin:user:axis_variable:1.0\
 xilinx.com:ip:dds_compiler:6.0\
 xilinx.com:ip:mult_gen:12.0\
 jbeuke:user:signal_generator:1.0\
+xilinx.com:ip:util_vector_logic:2.0\
 xilinx.com:ip:xlconcat:2.1\
-xilinx.com:ip:xlconstant:1.1\
 "
 
    set list_ips_missing ""
@@ -210,7 +210,7 @@ proc create_root_design { parentCell } {
   # Create instance: axis_variable_A_channel_1, and set properties
   set axis_variable_A_channel_1 [ create_bd_cell -type ip -vlnv pavel-demin:user:axis_variable:1.0 axis_variable_A_channel_1 ]
   set_property -dict [ list \
-   CONFIG.AXIS_TDATA_WIDTH {104} \
+   CONFIG.AXIS_TDATA_WIDTH {96} \
  ] $axis_variable_A_channel_1
 
   # Create instance: dds_compiler_A_channel_1, and set properties
@@ -220,6 +220,7 @@ proc create_root_design { parentCell } {
    CONFIG.DATA_Has_TLAST {Not_Required} \
    CONFIG.DDS_Clock_Rate {125} \
    CONFIG.Frequency_Resolution {4.440893e-7} \
+   CONFIG.Has_ACLKEN {false} \
    CONFIG.Has_ARESETn {true} \
    CONFIG.Has_Phase_Out {true} \
    CONFIG.Has_TREADY {false} \
@@ -235,11 +236,11 @@ proc create_root_design { parentCell } {
    CONFIG.POFF1 {0} \
    CONFIG.Parameter_Entry {System_Parameters} \
    CONFIG.PartsPresent {Phase_Generator_and_SIN_COS_LUT} \
-   CONFIG.Phase_Increment {Streaming} \
+   CONFIG.Phase_Increment {Programmable} \
    CONFIG.Phase_Offset_Angles1 {0} \
    CONFIG.Phase_Width {48} \
-   CONFIG.Phase_offset {Streaming} \
-   CONFIG.Resync {true} \
+   CONFIG.Phase_offset {Programmable} \
+   CONFIG.Resync {false} \
    CONFIG.S_PHASE_Has_TUSER {Not_Required} \
    CONFIG.Spurious_Free_Dynamic_Range {84} \
  ] $dds_compiler_A_channel_1
@@ -264,8 +265,19 @@ proc create_root_design { parentCell } {
    CONFIG.CFG_DATA_WIDTH {48} \
  ] $signal_generator_0
 
-  # Create instance: xlconcat_0, and set properties
-  set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ]
+  # Create instance: util_vector_logic_0, and set properties
+  set util_vector_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_0 ]
+  set_property -dict [ list \
+   CONFIG.C_OPERATION {not} \
+   CONFIG.C_SIZE {1} \
+   CONFIG.LOGO_FILE {data/sym_notgate.png} \
+ ] $util_vector_logic_0
+
+  # Create instance: util_vector_logic_1, and set properties
+  set util_vector_logic_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_1 ]
+  set_property -dict [ list \
+   CONFIG.C_SIZE {1} \
+ ] $util_vector_logic_1
 
   # Create instance: xlconcat_A_channel_1, and set properties
   set xlconcat_A_channel_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_A_channel_1 ]
@@ -273,35 +285,28 @@ proc create_root_design { parentCell } {
    CONFIG.IN0_WIDTH {48} \
    CONFIG.IN1_WIDTH {48} \
    CONFIG.IN2_WIDTH {8} \
-   CONFIG.NUM_PORTS {3} \
+   CONFIG.NUM_PORTS {2} \
  ] $xlconcat_A_channel_1
 
-  # Create instance: xlconstant_0, and set properties
-  set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
-  set_property -dict [ list \
-   CONFIG.CONST_VAL {0} \
-   CONFIG.CONST_WIDTH {7} \
- ] $xlconstant_0
-
   # Create interface connections
-  connect_bd_intf_net -intf_net axis_variable_A_channel_1_M_AXIS [get_bd_intf_pins axis_variable_A_channel_1/M_AXIS] [get_bd_intf_pins dds_compiler_A_channel_1/S_AXIS_PHASE]
+  connect_bd_intf_net -intf_net axis_variable_A_channel_1_M_AXIS [get_bd_intf_pins axis_variable_A_channel_1/M_AXIS] [get_bd_intf_pins dds_compiler_A_channel_1/S_AXIS_CONFIG]
   connect_bd_intf_net -intf_net dds_compiler_A_channel_1_M_AXIS_DATA [get_bd_intf_pins dds_compiler_A_channel_1/M_AXIS_DATA] [get_bd_intf_pins signal_generator_0/s_axis]
   connect_bd_intf_net -intf_net dds_compiler_A_channel_1_M_AXIS_PHASE [get_bd_intf_pins dds_compiler_A_channel_1/M_AXIS_PHASE] [get_bd_intf_pins signal_generator_0/s_axis_phase]
 
   # Create port connections
   connect_bd_net -net amplitude_A_channel_1_slice1_Dout [get_bd_ports amplitude] [get_bd_pins mult_gen_0/A]
+  connect_bd_net -net aresetn_1 [get_bd_ports aresetn] [get_bd_pins axis_variable_A_channel_1/aresetn] [get_bd_pins signal_generator_0/aresetn] [get_bd_pins util_vector_logic_1/Op2]
   connect_bd_net -net clk_wiz_0_clk_internal [get_bd_ports aclk] [get_bd_pins axis_variable_A_channel_1/aclk] [get_bd_pins dds_compiler_A_channel_1/aclk] [get_bd_pins mult_gen_0/CLK] [get_bd_pins signal_generator_0/clk]
   connect_bd_net -net freq_1 [get_bd_ports freq] [get_bd_pins xlconcat_A_channel_1/In0]
   connect_bd_net -net mult_gen_0_P [get_bd_ports wave] [get_bd_pins mult_gen_0/P]
   connect_bd_net -net phase_1 [get_bd_ports phase] [get_bd_pins xlconcat_A_channel_1/In1]
   connect_bd_net -net phase_A_channel_1_slice1_Dout [get_bd_ports cfg_data] [get_bd_pins signal_generator_0/cfg_data]
-  connect_bd_net -net resync_1 [get_bd_ports resync] [get_bd_pins xlconcat_0/In0]
-  connect_bd_net -net rst_ps7_0_125M_peripheral_aresetn [get_bd_ports aresetn] [get_bd_pins axis_variable_A_channel_1/aresetn] [get_bd_pins dds_compiler_A_channel_1/aresetn] [get_bd_pins signal_generator_0/aresetn]
+  connect_bd_net -net resync_1 [get_bd_ports resync] [get_bd_pins util_vector_logic_0/Op1]
   connect_bd_net -net signal_generator_0_m_axis_tdata [get_bd_pins mult_gen_0/B] [get_bd_pins signal_generator_0/m_axis_tdata]
   connect_bd_net -net signal_generator_0_m_axis_tvalid [get_bd_ports m_axis_data_tvalid_1] [get_bd_pins signal_generator_0/m_axis_tvalid]
-  connect_bd_net -net xlconcat_0_dout [get_bd_pins xlconcat_0/dout] [get_bd_pins xlconcat_A_channel_1/In2]
+  connect_bd_net -net util_vector_logic_0_Res [get_bd_pins util_vector_logic_0/Res] [get_bd_pins util_vector_logic_1/Op1]
+  connect_bd_net -net util_vector_logic_1_Res [get_bd_pins dds_compiler_A_channel_1/aresetn] [get_bd_pins util_vector_logic_1/Res]
   connect_bd_net -net xlconcat_A_channel_1_dout [get_bd_pins axis_variable_A_channel_1/cfg_data] [get_bd_pins xlconcat_A_channel_1/dout]
-  connect_bd_net -net xlconstant_0_dout [get_bd_pins xlconcat_0/In1] [get_bd_pins xlconstant_0/dout]
 
   # Create address segments
 
diff --git a/src/lib/rp-daq-lib.c b/src/lib/rp-daq-lib.c
index 9c495034..842cc84b 100644
--- a/src/lib/rp-daq-lib.c
+++ b/src/lib/rp-daq-lib.c
@@ -653,8 +653,8 @@ int setResyncDAC(int8_t value, int channel, int index) {
 		return -1;
 
 	int bitpos = 14 + channel;
-	// Reset bit is in the 2-th channel
-	int offset = 8 * index + 2;
+	// Reset bits are in the 2nd channel -> bitpos 31:30
+	int offset = 8 * index + 1;
 	// clear the bit
 	*((int16_t *)(pdm_cfg + offset)) &= ~(1u << bitpos);
 	// set the bit
@@ -1313,6 +1313,7 @@ void stopTx() {
 	for(int d=0; d<5; d++) {
 		setPDMAllValuesVolt(0.0, d);
 		setEnableDACAll(1,d);
+		setResyncDACAll(0,d);
 	}
 }
 
diff --git a/src/server/control.c b/src/server/control.c
index 07868075..db92500b 100644
--- a/src/server/control.c
+++ b/src/server/control.c
@@ -104,6 +104,7 @@ void clearSequence() {
 
 	for(int d=0; d<6; d++) {
 		setEnableDACAll(1,d);
+    setResyncDACAll(0,d);
 	}
 	for(int d=0; d<2; d++) {
 		setRampDownDACAll(false,d);

From a2c090141c3fb16a2042bda990464e842723e704 Mon Sep 17 00:00:00 2001
From: Tobias Knopp <tobias.knopp@tuhh.de>
Date: Thu, 26 Sep 2024 07:17:33 +0200
Subject: [PATCH 24/38] fix multi-channel resync issues

---
 src/server/control.c       | 3 ++-
 src/server/scpi_commands.c | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/server/control.c b/src/server/control.c
index db92500b..8762ba41 100644
--- a/src/server/control.c
+++ b/src/server/control.c
@@ -131,9 +131,10 @@ bool getSequenceEnableValue(sequenceData_t *seqData, int seqStep, int channel) {
 
 bool getSequenceResyncValue(sequenceData_t *seqData, int seqStep, int channel) {
 	bool result = false;
+  int numChan = numSlowDACChan > 2 ? 2 : numSlowDACChan;
 	if (seqData->resyncLUT != NULL) {
 		int localStep = seqStep % seqData->numStepsPerRepetition;
-		result = seqData->resyncLUT[localStep + channel];
+		result = seqData->resyncLUT[localStep * numChan + channel];
 	}
 	return result;
 }
diff --git a/src/server/scpi_commands.c b/src/server/scpi_commands.c
index 6025297e..b7308745 100644
--- a/src/server/scpi_commands.c
+++ b/src/server/scpi_commands.c
@@ -1070,7 +1070,7 @@ static scpi_result_t RP_DAC_SetResyncLUT(scpi_t * context) {
 		printf("Allocating ressyncLUT\n");
 		configSeq->resyncLUT = (bool *)calloc(numChan, configSeq->numStepsPerRepetition * sizeof(bool));
 
-		int n = readAll(newdatasockfd, configSeq->resyncLUT, numSlowDACChan * configSeq->numStepsPerRepetition * sizeof(bool));
+		int n = readAll(newdatasockfd, configSeq->resyncLUT, numChan * configSeq->numStepsPerRepetition * sizeof(bool));
 		seqState = CONFIG;
 		if (n < 0) perror("ERROR reading from socket");
 		return returnSCPIBool(context, true);

From 14ab693086acfc1fc343de68b98b3942cb69ac4b Mon Sep 17 00:00:00 2001
From: rp_local <n.a>
Date: Thu, 26 Sep 2024 09:23:01 +0000
Subject: [PATCH 25/38] Move resync flag to bit 14 of each DAC channel

---
 src/fpga/hdl/sequence_slice.v | 5 +++--
 src/lib/rp-daq-lib.c          | 6 +++---
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/src/fpga/hdl/sequence_slice.v b/src/fpga/hdl/sequence_slice.v
index ab2e91a5..3ffc5840 100644
--- a/src/fpga/hdl/sequence_slice.v
+++ b/src/fpga/hdl/sequence_slice.v
@@ -42,8 +42,9 @@ assign pdm_value_3[10:0] = seq_data_int[90:80];
 // Flags
 assign enable_dac[1:0] = seq_data_int[97:96];
 assign enable_pdm[3:0] = seq_data_int[101:98];
-assign resync_dac[1:0] = seq_data_int[31:30];
+assign resync_dac[0] = seq_data_int[14];
+assign resync_dac[1] = seq_data_int[30];
 assign enable_dac_ramp_down[0] = seq_data_int[112];
 assign enable_dac_ramp_down[1] = seq_data_int[113];
 
-endmodule
+endmodule
\ No newline at end of file
diff --git a/src/lib/rp-daq-lib.c b/src/lib/rp-daq-lib.c
index 842cc84b..28f85cf0 100644
--- a/src/lib/rp-daq-lib.c
+++ b/src/lib/rp-daq-lib.c
@@ -652,9 +652,9 @@ int setResyncDAC(int8_t value, int channel, int index) {
 	if (value < 0 || value >= 2)
 		return -1;
 
-	int bitpos = 14 + channel;
-	// Reset bits are in the 2nd channel -> bitpos 31:30
-	int offset = 8 * index + 1;
+	int bitpos = 14;
+	// Reset bits are in the 14th bit of the respective DAC channel -> 14 and 30 
+	int offset = 8 * index + channel;
 	// clear the bit
 	*((int16_t *)(pdm_cfg + offset)) &= ~(1u << bitpos);
 	// set the bit

From 5d4f42d492d13c7f08795e1cc7f95f72dff9e694 Mon Sep 17 00:00:00 2001
From: rp_local <n.a>
Date: Thu, 26 Sep 2024 09:23:34 +0000
Subject: [PATCH 26/38] Restrict getSequenceResyncValue to DAC channel

---
 src/server/control.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/server/control.c b/src/server/control.c
index 8762ba41..1b6b422c 100644
--- a/src/server/control.c
+++ b/src/server/control.c
@@ -131,8 +131,8 @@ bool getSequenceEnableValue(sequenceData_t *seqData, int seqStep, int channel) {
 
 bool getSequenceResyncValue(sequenceData_t *seqData, int seqStep, int channel) {
 	bool result = false;
-  int numChan = numSlowDACChan > 2 ? 2 : numSlowDACChan;
-	if (seqData->resyncLUT != NULL) {
+  	int numChan = numSlowDACChan > 2 ? 2 : numSlowDACChan;
+	if (seqData->resyncLUT != NULL && channel < numChan) {
 		int localStep = seqStep % seqData->numStepsPerRepetition;
 		result = seqData->resyncLUT[localStep * numChan + channel];
 	}
@@ -217,6 +217,7 @@ static void setLUTValuesFor(int futureStep, int channel, int currPDMIndex) {
 	if (activeSequence == NULL) {
 		setPDMValueVolt(0.0, channel, currPDMIndex);
 		setEnableDAC(false, channel, currPDMIndex);
+		setResyncDAC(false, channel, currPDMIndex);
 		setRampDownDAC(false, channel, currPDMIndex);
 		return;
 	}

From 3c627929cfd1d1b57e0ec554157fc64a41593672 Mon Sep 17 00:00:00 2001
From: rp_local <n.a>
Date: Fri, 29 Nov 2024 13:07:08 +0000
Subject: [PATCH 27/38] Init test of step counting with writepointer lowest bit

---
 src/fpga/hdl/sequence_stepper.v | 41 ++++++++++++++++++++-------------
 1 file changed, 25 insertions(+), 16 deletions(-)

diff --git a/src/fpga/hdl/sequence_stepper.v b/src/fpga/hdl/sequence_stepper.v
index 9a28dd9a..25754421 100644
--- a/src/fpga/hdl/sequence_stepper.v
+++ b/src/fpga/hdl/sequence_stepper.v
@@ -1,36 +1,45 @@
 `timescale 1ns / 1ps
 
 module sequence_stepper(
-    input [63:0] writepointer,
+    input [63:0] writePointer,
     input [31:0] stepSize,
     input clk,
     input aresetn,
-    output [31:0] step_counter 
+    output [31:0] seq_counter
 );
 
-reg [63:0] end_of_step, next_end_of_step;
-reg [31:0] step_counter_reg, step_counter_next;
+reg [31:0] stepSize_int;
+reg [31:0] seq_counter_state;
+reg [31:0] sample_counter;
+reg wp_prev, wp_next;
 
 always @(posedge clk)
 begin
+    stepSize_int <= stepSize;
+    wp_next <= writePointer[0];
     if (~aresetn) begin
-        step_counter_reg <= 0;
-        step_counter_next <= 0;
-        end_of_step <= stepSize;
-        next_end_of_step <= stepSize;
+        seq_counter_state <= 0;
+        sample_counter <= stepSize_int;
+        wp_prev <= 0;
     end else begin
-        step_counter_reg <= step_counter_next;
-        end_of_step <= next_end_of_step;
-        if (end_of_step < writepointer) begin
-            next_end_of_step <= end_of_step + stepSize;
-            step_counter_next <= step_counter_reg + 1;
+        wp_prev <= wp_next;
+        if (wp_prev != wp_next) begin
+        
+            if (sample_counter == 0) begin
+                sample_counter <= stepSize_int;
+                seq_counter_state <= seq_counter_state + 1;
+            end else begin
+                sample_counter <= sample_counter - 1;
+                seq_counter_state <= seq_counter_state;
+            end
+        
         end else begin
-            next_end_of_step <= next_end_of_step;
-            step_counter_next <= step_counter_reg;
+            sample_counter <= sample_counter;
+            seq_counter_state <= seq_counter_state;
         end
     end
 end
 
-assign step_counter = step_counter_reg;
+assign seq_counter = seq_counter_state;
 
 endmodule

From b7a82592def6c8f64d7df9a9576c00b19382fa90 Mon Sep 17 00:00:00 2001
From: Tobias Knopp <tobias.knopp@tuhh.de>
Date: Sun, 1 Dec 2024 14:48:28 +0100
Subject: [PATCH 28/38] add sequenceIssue.jl

---
 src/examples/julia/sequenceIssue.jl | 60 +++++++++++++++++++++++++++++
 1 file changed, 60 insertions(+)
 create mode 100644 src/examples/julia/sequenceIssue.jl

diff --git a/src/examples/julia/sequenceIssue.jl b/src/examples/julia/sequenceIssue.jl
new file mode 100644
index 00000000..5d387cb8
--- /dev/null
+++ b/src/examples/julia/sequenceIssue.jl
@@ -0,0 +1,60 @@
+using RedPitayaDAQServer
+using CairoMakie
+
+# obtain the URL of the RedPitaya
+include("config.jl")
+
+rp = RedPitaya(URLs[1])
+serverMode!(rp, CONFIGURATION)
+
+
+dec = 128
+base_frequency = 125000000
+
+samples_per_step = 40 #30*16
+steps_per_frame = 4
+numSamples = steps_per_frame * samples_per_step
+
+decimation!(rp, dec)
+samplesPerPeriod!(rp, 1)
+periodsPerFrame!(rp, numSamples)
+samplesPerStep!(rp, samples_per_step)
+triggerMode!(rp, INTERNAL)
+
+
+amplitudeDAC!(rp, 1, 1, 0.0)
+amplitudeDAC!(rp, 2, 1, 0.0 )
+
+clearSequence!(rp)
+
+# Climbing offset for first channel, fixed offset for second channel
+seqChan!(rp, 6)
+lutB = collect(ones(steps_per_frame))
+lutB[1:2:end] .= 0.0
+lut = collect(cat(-lutB,-lutB*0.3, 0*lutB,0*lutB,0*lutB,0*lutB,dims=2)')
+#lut = collect(cat(-lutB,dims=2)')#,lutB,lutB,lutB,lutB,dims=2)')
+
+lutEnableDACA = ones(Bool, steps_per_frame)
+
+#enableLUT = collect( cat(lutEnableDACA,lutEnableDACA,lutEnableDACA,lutEnableDACA,lutEnableDACA,lutEnableDACA,dims=2)' )
+enableLUT = collect( cat(lutEnableDACA,lutEnableDACA,lutEnableDACA,lutEnableDACA,lutEnableDACA,lutEnableDACA,dims=2)' )
+#enableLUT = collect( cat(lutEnableDACA,dims=2)') #,lutEnableDACA,lutEnableDACA,lutEnableDACA,lutEnableDACA,dims=2)' )
+
+seq = SimpleSequence(lut, 300, enableLUT)
+sequence!(rp, seq)
+
+serverMode!(rp, ACQUISITION)
+masterTrigger!(rp, true)
+
+uCurrentPeriod = readFrames(rp, 1, 3)
+
+masterTrigger!(rp, false)
+serverMode!(rp, CONFIGURATION)
+
+plot = lines(vec(uCurrentPeriod[:,1,:,1]), label = "Rx1")
+lines!(plot.axis, vec(uCurrentPeriod[:,2,:,1]), label = "Rx2")
+lines!(plot.axis, vec(uCurrentPeriod[:,1,:,2]), label = "Rx1_2")
+lines!(plot.axis, vec(uCurrentPeriod[:,2,:,2]), label = "Rx2_2")
+axislegend(plot.axis)
+save(joinpath(@__DIR__(), "images", "sequenceIssue.png"), plot)
+plot
\ No newline at end of file

From 731826b5bab6776b1669eb4466088f7bd532de3f Mon Sep 17 00:00:00 2001
From: Tobias Knopp <tobias@knoppweb.de>
Date: Sun, 1 Dec 2024 17:38:51 +0100
Subject: [PATCH 29/38] fix sequence stepper issue

---
 src/fpga/bd/bd.tcl              |  9 +++----
 src/fpga/hdl/sequence_stepper.v | 42 +++++++++++++--------------------
 src/lib/rp-daq-lib.c            |  4 ++--
 3 files changed, 24 insertions(+), 31 deletions(-)

diff --git a/src/fpga/bd/bd.tcl b/src/fpga/bd/bd.tcl
index e9ae2bab..494b4cfb 100644
--- a/src/fpga/bd/bd.tcl
+++ b/src/fpga/bd/bd.tcl
@@ -2099,7 +2099,6 @@ proc create_hier_cell_sequencer { parentCell nameHier } {
 
   # Create pins
   create_bd_pin -dir I -type clk aclk
-  create_bd_pin -dir I -from 63 -to 0 adc_sts
   create_bd_pin -dir I -type rst aresetn
   create_bd_pin -dir I bram_aresetn
   create_bd_pin -dir I -from 31 -to 0 cfg_data
@@ -2220,6 +2219,9 @@ proc create_hier_cell_sequencer { parentCell nameHier } {
   # Create instance: xlconstant_0, and set properties
   set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
 
+  # Create instance: xlslice_0, and set properties
+  set xlslice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 ]
+
   # Create instance: zero_constant, and set properties
   set zero_constant [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 zero_constant ]
   set_property -dict [ list \
@@ -2240,7 +2242,6 @@ proc create_hier_cell_sequencer { parentCell nameHier } {
 
   # Create port connections
   connect_bd_net -net aclk_1 [get_bd_pins aclk] [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins blk_mem_gen_0/clkb] [get_bd_pins sequence_slice_0/clk] [get_bd_pins sequence_stepper_0/clk]
-  connect_bd_net -net adc_sts_1 [get_bd_pins adc_sts] [get_bd_pins sequence_stepper_0/writepointer]
   connect_bd_net -net aresetn3_1 [get_bd_pins keep_alive_aresetn] [get_bd_pins util_vector_logic_0/Op2]
   connect_bd_net -net blk_mem_gen_0_doutb [get_bd_pins blk_mem_gen_0/doutb] [get_bd_pins sequence_slice_0/seq_data]
   connect_bd_net -net bram_aresetn_1 [get_bd_pins bram_aresetn] [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn]
@@ -2267,7 +2268,7 @@ proc create_hier_cell_sequencer { parentCell nameHier } {
   connect_bd_net -net xlconcat_0_dout [get_bd_pins util_vector_logic_7/Op1] [get_bd_pins xlconcat_0/dout]
   connect_bd_net -net xlconcat_1_dout [get_bd_pins oa_dac] [get_bd_pins xlconcat_1/dout]
   connect_bd_net -net xlconstant_0_dout [get_bd_pins blk_mem_gen_0/enb] [get_bd_pins xlconstant_0/dout]
-  connect_bd_net -net xlslice_1_Dout [get_bd_pins pdm_sts] [get_bd_pins bram_element_slice/Din] [get_bd_pins sequence_stepper_0/step_counter]
+  connect_bd_net -net xlslice_1_Dout [get_bd_pins pdm_sts] [get_bd_pins bram_element_slice/Din] [get_bd_pins sequence_stepper_0/step_counter] [get_bd_pins xlslice_0/Din]
   connect_bd_net -net zero_constant1_dout [get_bd_pins concat_element_addr/In0] [get_bd_pins zero_constant1/dout]
   connect_bd_net -net zero_constant_dout [get_bd_pins concat_element_addr/In2] [get_bd_pins zero_constant/dout]
 
@@ -3436,7 +3437,7 @@ proc create_root_design { parentCell } {
   connect_bd_net -net util_vector_logic_0_Res [get_bd_pins clk_wiz_0/clk_in_sel] [get_bd_pins reset_manager_0/isMaster] [get_bd_pins util_vector_logic_0/Res]
   connect_bd_net -net write_to_ram_adc_out_A [get_bd_pins counter_trigger/adc0] [get_bd_pins write_to_ram/adc_out_A]
   connect_bd_net -net write_to_ram_adc_out_B [get_bd_pins counter_trigger/adc1] [get_bd_pins write_to_ram/adc_out_B]
-  connect_bd_net -net xlconcat_0_dout [get_bd_pins sequencer/adc_sts] [get_bd_pins system/adc_sts] [get_bd_pins write_to_ram/sts_data]
+  connect_bd_net -net xlconcat_0_dout [get_bd_pins system/adc_sts] [get_bd_pins write_to_ram/sts_data]
   connect_bd_net -net xlconcat_0_dout1 [get_bd_ports dac_pwm_o] [get_bd_pins sequencer/dout]
   connect_bd_net -net xlconcat_1_dout [get_bd_pins counter_trigger/counter_trigger_sts] [get_bd_pins system/counter_trigger_sts]
   connect_bd_net -net xlconstant_0_dout [get_bd_ports ext_DIO1_N] [get_bd_pins xlconstant_0/dout]
diff --git a/src/fpga/hdl/sequence_stepper.v b/src/fpga/hdl/sequence_stepper.v
index 25754421..2431364e 100644
--- a/src/fpga/hdl/sequence_stepper.v
+++ b/src/fpga/hdl/sequence_stepper.v
@@ -1,45 +1,37 @@
 `timescale 1ns / 1ps
 
 module sequence_stepper(
-    input [63:0] writePointer,
     input [31:0] stepSize,
     input clk,
     input aresetn,
-    output [31:0] seq_counter
+    output [31:0] step_counter 
 );
 
-reg [31:0] stepSize_int;
-reg [31:0] seq_counter_state;
-reg [31:0] sample_counter;
-reg wp_prev, wp_next;
+reg [63:0] step_counter_local, step_counter_local_next;
+reg [31:0] step_counter_reg, step_counter_next;
+reg [31:0] step_size_local;
 
 always @(posedge clk)
 begin
-    stepSize_int <= stepSize;
-    wp_next <= writePointer[0];
     if (~aresetn) begin
-        seq_counter_state <= 0;
-        sample_counter <= stepSize_int;
-        wp_prev <= 0;
+        step_counter_reg <= 0;
+        step_counter_next <= 0;
+        step_counter_local <= 0;
+        step_counter_local_next <= 0;
+        step_size_local <= stepSize-1;
     end else begin
-        wp_prev <= wp_next;
-        if (wp_prev != wp_next) begin
-        
-            if (sample_counter == 0) begin
-                sample_counter <= stepSize_int;
-                seq_counter_state <= seq_counter_state + 1;
-            end else begin
-                sample_counter <= sample_counter - 1;
-                seq_counter_state <= seq_counter_state;
-            end
-        
+        step_counter_reg <= step_counter_next;
+        step_counter_local <= step_counter_local_next;
+        if (step_counter_local == step_size_local) begin
+            step_counter_local_next <= 0;
+            step_counter_next <= step_counter_reg + 1;
         end else begin
-            sample_counter <= sample_counter;
-            seq_counter_state <= seq_counter_state;
+            step_counter_local_next <= step_counter_local + 1;
+            step_counter_next <= step_counter_reg;
         end
     end
 end
 
-assign seq_counter = seq_counter_state;
+assign step_counter = step_counter_reg;
 
 endmodule
diff --git a/src/lib/rp-daq-lib.c b/src/lib/rp-daq-lib.c
index 28f85cf0..3cef3572 100644
--- a/src/lib/rp-daq-lib.c
+++ b/src/lib/rp-daq-lib.c
@@ -784,11 +784,11 @@ int setPDMAllValuesVolt(float voltage, int channel) {
 
 int getSamplesPerStep() {
 	int32_t value = *((int32_t *)(cfg + 4));
-	return value;
+	return value*2/getDecimation();
 }
 
 int setSamplesPerStep(int samples) {
-	*((int32_t *)(cfg + 4)) = samples;
+	*((int32_t *)(cfg + 4)) = samples/2*getDecimation();
 	return 0;
 }
 

From cc911a91095dcea37f71d85a01f8ac0f0df9d71b Mon Sep 17 00:00:00 2001
From: Tobias Knopp <tobias@knoppweb.de>
Date: Fri, 6 Dec 2024 14:53:27 +0100
Subject: [PATCH 30/38] first version of hbridge

---
 src/client/julia/src/SlowIO.jl      |  40 +++
 src/examples/julia/config.jl        |   1 +
 src/examples/julia/sequenceIssue.jl |  17 +-
 src/fpga/bd/bd.tcl                  | 404 ++++++++++++++++++++++------
 src/fpga/bd/hbridgewaveform.tcl     | 357 ++++++++++++++++++++++++
 src/fpga/build.tcl                  |   1 +
 src/fpga/hdl/hbridge_signalgen.v    |  82 ++++++
 7 files changed, 816 insertions(+), 86 deletions(-)
 create mode 100644 src/fpga/bd/hbridgewaveform.tcl
 create mode 100644 src/fpga/hdl/hbridge_signalgen.v

diff --git a/src/client/julia/src/SlowIO.jl b/src/client/julia/src/SlowIO.jl
index f3c80011..26fcd3f4 100644
--- a/src/client/julia/src/SlowIO.jl
+++ b/src/client/julia/src/SlowIO.jl
@@ -182,3 +182,43 @@ end
 scpiCommand(::typeof(DIO), pin) = string("RP:DIO:", DIOPinToCommand(pin), "?")
 scpiReturn(::typeof(DIO)) = String
 parseReturn(::typeof(DIO), ret) = occursin("ON", ret)
+
+
+
+
+
+
+export DIOHBridge!
+"""
+DIOHBridge!(rp::RedPitaya, pin::DIOPins, val::Bool)
+
+Set the value of DIOHBridge pin `pin` to the value `val`.
+# Example
+```julia
+julia> DIOHBridge!(rp, DIO7_P, true)
+true
+```
+"""
+function DIOHBridge!(rp::RedPitaya, pin, val)
+  return query(rp, scpiCommand(DIOHBridge!, pin, val), scpiReturn(DIOHBridge!))
+end
+scpiCommand(::typeof(DIOHBridge!), pin::DIOPins, val::Bool) = string("RP:DIO:", DIOPinToCommand(pin), ":HBRIDGE ", (val ? "ON" : "OFF"))
+scpiReturn(::typeof(DIOHBridge!)) = Bool
+
+export DIOHBridge
+"""
+  DIOHBridge(rp::RedPitaya, pin::DIOPins)
+
+Get the value of DIOHBridge pin `pin`.
+# Example
+```julia
+julia>DIOHBridge(rp, DIO7_P)
+true
+```
+"""
+function DIOHBridge(rp::RedPitaya, pin)
+  return parseReturn(DIOHBridge, query(rp, scpiCommand(DIOHBridge, pin), scpiReturn(DIOHBridge)))
+end
+scpiCommand(::typeof(DIOHBridge), pin) = string("RP:DIO:", DIOPinToCommand(pin), ":HBRIDGE?")
+scpiReturn(::typeof(DIOHBridge)) = String
+parseReturn(::typeof(DIOHBridge), ret) = occursin("ON", ret)
\ No newline at end of file
diff --git a/src/examples/julia/config.jl b/src/examples/julia/config.jl
index ec096412..6e2da7e9 100644
--- a/src/examples/julia/config.jl
+++ b/src/examples/julia/config.jl
@@ -1,3 +1,4 @@
 # URLs= ["rp-f08ccb.local", "rp-f08caa.local"]
 URLs= ["192.168.1.100"]#, "192.168.2.17"]
+# URLs= ["192.168.178.65"]#, "192.168.178.95"]
 mkpath("images")
\ No newline at end of file
diff --git a/src/examples/julia/sequenceIssue.jl b/src/examples/julia/sequenceIssue.jl
index 5d387cb8..021d2a1a 100644
--- a/src/examples/julia/sequenceIssue.jl
+++ b/src/examples/julia/sequenceIssue.jl
@@ -11,7 +11,7 @@ serverMode!(rp, CONFIGURATION)
 dec = 128
 base_frequency = 125000000
 
-samples_per_step = 40 #30*16
+samples_per_step = 4000 #30*16
 steps_per_frame = 4
 numSamples = steps_per_frame * samples_per_step
 
@@ -21,9 +21,10 @@ periodsPerFrame!(rp, numSamples)
 samplesPerStep!(rp, samples_per_step)
 triggerMode!(rp, INTERNAL)
 
-
-amplitudeDAC!(rp, 1, 1, 0.0)
-amplitudeDAC!(rp, 2, 1, 0.0 )
+frequencyDAC!(rp, 1, 1, base_frequency/samples_per_step/dec)
+frequencyDAC!(rp, 2, 1, base_frequency/samples_per_step/dec)
+amplitudeDAC!(rp, 1, 1, 0.2)
+amplitudeDAC!(rp, 2, 1, 0.2 )
 
 clearSequence!(rp)
 
@@ -40,21 +41,21 @@ lutEnableDACA = ones(Bool, steps_per_frame)
 enableLUT = collect( cat(lutEnableDACA,lutEnableDACA,lutEnableDACA,lutEnableDACA,lutEnableDACA,lutEnableDACA,dims=2)' )
 #enableLUT = collect( cat(lutEnableDACA,dims=2)') #,lutEnableDACA,lutEnableDACA,lutEnableDACA,lutEnableDACA,dims=2)' )
 
-seq = SimpleSequence(lut, 300, enableLUT)
+seq = SimpleSequence(lut, 2, enableLUT)
 sequence!(rp, seq)
 
 serverMode!(rp, ACQUISITION)
 masterTrigger!(rp, true)
 
-uCurrentPeriod = readFrames(rp, 1, 3)
+uCurrentPeriod = readFrames(rp, 1, 200)
 
 masterTrigger!(rp, false)
 serverMode!(rp, CONFIGURATION)
 
 plot = lines(vec(uCurrentPeriod[:,1,:,1]), label = "Rx1")
 lines!(plot.axis, vec(uCurrentPeriod[:,2,:,1]), label = "Rx2")
-lines!(plot.axis, vec(uCurrentPeriod[:,1,:,2]), label = "Rx1_2")
-lines!(plot.axis, vec(uCurrentPeriod[:,2,:,2]), label = "Rx2_2")
+#lines!(plot.axis, vec(uCurrentPeriod[:,1,:,2]), label = "Rx1_2")
+#lines!(plot.axis, vec(uCurrentPeriod[:,2,:,2]), label = "Rx2_2")
 axislegend(plot.axis)
 save(joinpath(@__DIR__(), "images", "sequenceIssue.png"), plot)
 plot
\ No newline at end of file
diff --git a/src/fpga/bd/bd.tcl b/src/fpga/bd/bd.tcl
index 494b4cfb..9576f109 100644
--- a/src/fpga/bd/bd.tcl
+++ b/src/fpga/bd/bd.tcl
@@ -47,7 +47,7 @@ if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
 
 # The design that will be created by this Tcl script contains the following 
 # block design container source references:
-# signal_calib, signal_ramp, waveform_gen
+# hbridgewaveform, signal_calib, signal_ramp, waveform_gen
 
 # Please add the sources before sourcing this Tcl script.
 
@@ -227,7 +227,7 @@ wave_awg_composer\
 # CHECK Block Design Container Sources
 ##################################################################
 set bCheckSources 1
-set list_bdc_active "signal_calib, signal_ramp, waveform_gen"
+set list_bdc_active "hbridgewaveform, signal_calib, signal_ramp, waveform_gen"
 
 array set map_bdc_missing {}
 set map_bdc_missing(ACTIVE) ""
@@ -235,6 +235,7 @@ set map_bdc_missing(BDC) ""
 
 if { $bCheckSources == 1 } {
    set list_check_srcs "\ 
+hbridgewaveform \
 signal_calib \
 signal_ramp \
 waveform_gen \
@@ -885,16 +886,8 @@ proc create_hier_cell_signal_compose1 { parentCell nameHier } {
    CONFIG.LOCK_PROPAGATE {0} \
  ] $waveform_gen_2
 
-  # Create instance: waveform_gen_3, and set properties
-  set waveform_gen_3 [ create_bd_cell -type container -reference waveform_gen waveform_gen_3 ]
-  set_property -dict [ list \
-   CONFIG.ACTIVE_SIM_BD {waveform_gen.bd} \
-   CONFIG.ACTIVE_SYNTH_BD {waveform_gen.bd} \
-   CONFIG.ENABLE_DFX {0} \
-   CONFIG.LIST_SIM_BD {waveform_gen.bd} \
-   CONFIG.LIST_SYNTH_BD {waveform_gen.bd} \
-   CONFIG.LOCK_PROPAGATE {0} \
- ] $waveform_gen_3
+  # Create instance: xlconstant_0, and set properties
+  set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
 
   # Create interface connections
   connect_bd_intf_net -intf_net awg_bram_1 [get_bd_intf_pins awg_bram] [get_bd_intf_pins waveform_awg1/S_AXI]
@@ -902,12 +895,12 @@ proc create_hier_cell_signal_compose1 { parentCell nameHier } {
   # Create port connections
   connect_bd_net -net Din_1 [get_bd_pins Din] [get_bd_pins signal_cfg_slice_0/cfg_data]
   connect_bd_net -net bram_aresetn_1 [get_bd_pins bram_aresetn] [get_bd_pins waveform_awg1/bram_aresetn]
-  connect_bd_net -net clk_wiz_0_clk_internal [get_bd_pins aclk] [get_bd_pins signal_calib_0/aclk] [get_bd_pins signal_composer_0/clk] [get_bd_pins signal_ramp_0/aclk] [get_bd_pins waveform_awg1/aclk] [get_bd_pins waveform_gen_0/aclk] [get_bd_pins waveform_gen_1/aclk] [get_bd_pins waveform_gen_2/aclk] [get_bd_pins waveform_gen_3/aclk]
+  connect_bd_net -net clk_wiz_0_clk_internal [get_bd_pins aclk] [get_bd_pins signal_calib_0/aclk] [get_bd_pins signal_composer_0/clk] [get_bd_pins signal_ramp_0/aclk] [get_bd_pins waveform_awg1/aclk] [get_bd_pins waveform_gen_0/aclk] [get_bd_pins waveform_gen_1/aclk] [get_bd_pins waveform_gen_2/aclk]
   connect_bd_net -net disable_dac_1 [get_bd_pins disable_dac] [get_bd_pins signal_composer_0/disable_dac]
   connect_bd_net -net enable_ramping_1 [get_bd_pins enable_ramping] [get_bd_pins signal_ramp_0/enableRamping]
   connect_bd_net -net offset_1 [get_bd_pins offset] [get_bd_pins signal_composer_0/seq]
-  connect_bd_net -net resync_dac_1 [get_bd_pins resync_dac] [get_bd_pins waveform_gen_0/resync] [get_bd_pins waveform_gen_1/resync] [get_bd_pins waveform_gen_2/resync] [get_bd_pins waveform_gen_3/resync]
-  connect_bd_net -net rst_ps7_0_125M_peripheral_aresetn [get_bd_pins aresetn] [get_bd_pins signal_ramp_0/aresetn] [get_bd_pins waveform_awg1/aresetn] [get_bd_pins waveform_gen_0/aresetn] [get_bd_pins waveform_gen_1/aresetn] [get_bd_pins waveform_gen_2/aresetn] [get_bd_pins waveform_gen_3/aresetn]
+  connect_bd_net -net resync_dac_1 [get_bd_pins resync_dac] [get_bd_pins waveform_gen_0/resync] [get_bd_pins waveform_gen_1/resync] [get_bd_pins waveform_gen_2/resync]
+  connect_bd_net -net rst_ps7_0_125M_peripheral_aresetn [get_bd_pins aresetn] [get_bd_pins signal_ramp_0/aresetn] [get_bd_pins waveform_awg1/aresetn] [get_bd_pins waveform_gen_0/aresetn] [get_bd_pins waveform_gen_1/aresetn] [get_bd_pins waveform_gen_2/aresetn]
   connect_bd_net -net signal_calib_0_signal_out [get_bd_pins S] [get_bd_pins signal_calib_0/signal_out]
   connect_bd_net -net signal_cfg_slice_0_calib_limit_lower [get_bd_pins signal_cfg_slice_0/calib_limit_lower]
   connect_bd_net -net signal_cfg_slice_0_calib_limit_upper [get_bd_pins signal_cfg_slice_0/calib_limit_upper]
@@ -925,10 +918,8 @@ proc create_hier_cell_signal_compose1 { parentCell nameHier } {
   connect_bd_net -net signal_cfg_slice_0_comp_2_cfg [get_bd_pins signal_cfg_slice_0/comp_2_cfg] [get_bd_pins waveform_gen_2/cfg_data]
   connect_bd_net -net signal_cfg_slice_0_comp_2_freq [get_bd_pins signal_cfg_slice_0/comp_2_freq] [get_bd_pins waveform_gen_2/freq]
   connect_bd_net -net signal_cfg_slice_0_comp_2_phase [get_bd_pins signal_cfg_slice_0/comp_2_phase] [get_bd_pins waveform_gen_2/phase]
-  connect_bd_net -net signal_cfg_slice_0_comp_3_amp [get_bd_pins signal_cfg_slice_0/comp_3_amp] [get_bd_pins waveform_gen_3/amplitude]
-  connect_bd_net -net signal_cfg_slice_0_comp_3_cfg [get_bd_pins signal_cfg_slice_0/comp_3_cfg] [get_bd_pins waveform_gen_3/cfg_data]
-  connect_bd_net -net signal_cfg_slice_0_comp_3_freq [get_bd_pins signal_cfg_slice_0/comp_3_freq] [get_bd_pins waveform_awg1/freq] [get_bd_pins waveform_gen_3/freq]
-  connect_bd_net -net signal_cfg_slice_0_comp_3_phase [get_bd_pins signal_cfg_slice_0/comp_3_phase] [get_bd_pins waveform_awg1/phase] [get_bd_pins waveform_gen_3/phase]
+  connect_bd_net -net signal_cfg_slice_0_comp_3_freq [get_bd_pins signal_cfg_slice_0/comp_3_freq] [get_bd_pins waveform_awg1/freq]
+  connect_bd_net -net signal_cfg_slice_0_comp_3_phase [get_bd_pins signal_cfg_slice_0/comp_3_phase] [get_bd_pins waveform_awg1/phase]
   connect_bd_net -net signal_cfg_slice_0_offset [get_bd_pins signal_cfg_slice_0/offset] [get_bd_pins signal_composer_0/offset]
   connect_bd_net -net signal_cfg_slice_0_ramp_freq [get_bd_pins signal_cfg_slice_0/ramp_freq] [get_bd_pins signal_ramp_0/freq]
   connect_bd_net -net signal_composer_0_signal_out [get_bd_pins signal_composer_0/signal_out] [get_bd_pins signal_ramp_0/signal_in]
@@ -943,7 +934,7 @@ proc create_hier_cell_signal_compose1 { parentCell nameHier } {
   connect_bd_net -net waveform_gen_1_wave [get_bd_pins signal_composer_0/wave1] [get_bd_pins waveform_gen_1/wave]
   connect_bd_net -net waveform_gen_2_m_axis_data_tvalid_1 [get_bd_pins signal_composer_0/valid2] [get_bd_pins waveform_gen_2/m_axis_data_tvalid_1]
   connect_bd_net -net waveform_gen_2_wave [get_bd_pins signal_composer_0/wave2] [get_bd_pins waveform_gen_2/wave]
-  connect_bd_net -net waveform_gen_3_m_axis_data_tvalid_1 [get_bd_pins signal_composer_0/valid3] [get_bd_pins waveform_gen_3/m_axis_data_tvalid_1]
+  connect_bd_net -net xlconstant_0_dout [get_bd_pins signal_composer_0/valid3] [get_bd_pins xlconstant_0/dout]
 
   # Restore current instance
   current_bd_instance $oldCurInst
@@ -1081,29 +1072,21 @@ proc create_hier_cell_signal_compose { parentCell nameHier } {
    CONFIG.LOCK_PROPAGATE {0} \
  ] $waveform_gen_2
 
-  # Create instance: waveform_gen_3, and set properties
-  set waveform_gen_3 [ create_bd_cell -type container -reference waveform_gen waveform_gen_3 ]
-  set_property -dict [ list \
-   CONFIG.ACTIVE_SIM_BD {waveform_gen.bd} \
-   CONFIG.ACTIVE_SYNTH_BD {waveform_gen.bd} \
-   CONFIG.ENABLE_DFX {0} \
-   CONFIG.LIST_SIM_BD {waveform_gen.bd} \
-   CONFIG.LIST_SYNTH_BD {waveform_gen.bd} \
-   CONFIG.LOCK_PROPAGATE {0} \
- ] $waveform_gen_3
+  # Create instance: xlconstant_0, and set properties
+  set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
 
   # Create interface connections
   connect_bd_intf_net -intf_net awg_bram_1 [get_bd_intf_pins awg_bram] [get_bd_intf_pins waveform_awg/S_AXI]
 
   # Create port connections
   connect_bd_net -net Din_1 [get_bd_pins Din] [get_bd_pins signal_cfg_slice_0/cfg_data]
-  connect_bd_net -net aclk_1 [get_bd_pins aclk] [get_bd_pins signal_calib_0/aclk] [get_bd_pins signal_composer_0/clk] [get_bd_pins signal_ramp/aclk] [get_bd_pins waveform_awg/aclk] [get_bd_pins waveform_gen_0/aclk] [get_bd_pins waveform_gen_1/aclk] [get_bd_pins waveform_gen_2/aclk] [get_bd_pins waveform_gen_3/aclk]
-  connect_bd_net -net aresetn_1 [get_bd_pins aresetn] [get_bd_pins signal_ramp/aresetn] [get_bd_pins waveform_awg/aresetn] [get_bd_pins waveform_gen_0/aresetn] [get_bd_pins waveform_gen_1/aresetn] [get_bd_pins waveform_gen_2/aresetn] [get_bd_pins waveform_gen_3/aresetn]
+  connect_bd_net -net aclk_1 [get_bd_pins aclk] [get_bd_pins signal_calib_0/aclk] [get_bd_pins signal_composer_0/clk] [get_bd_pins signal_ramp/aclk] [get_bd_pins waveform_awg/aclk] [get_bd_pins waveform_gen_0/aclk] [get_bd_pins waveform_gen_1/aclk] [get_bd_pins waveform_gen_2/aclk]
+  connect_bd_net -net aresetn_1 [get_bd_pins aresetn] [get_bd_pins signal_ramp/aresetn] [get_bd_pins waveform_awg/aresetn] [get_bd_pins waveform_gen_0/aresetn] [get_bd_pins waveform_gen_1/aresetn] [get_bd_pins waveform_gen_2/aresetn]
   connect_bd_net -net bram_aresetn_1 [get_bd_pins bram_aresetn] [get_bd_pins waveform_awg/bram_aresetn]
   connect_bd_net -net disable_dac_1 [get_bd_pins disable_dac] [get_bd_pins signal_composer_0/disable_dac]
   connect_bd_net -net offset_1 [get_bd_pins offset] [get_bd_pins signal_composer_0/seq]
   connect_bd_net -net ramping_enable_1 [get_bd_pins enable_ramping] [get_bd_pins signal_ramp/enableRamping]
-  connect_bd_net -net resync_dac_1 [get_bd_pins resync_dac] [get_bd_pins waveform_gen_0/resync] [get_bd_pins waveform_gen_1/resync] [get_bd_pins waveform_gen_2/resync] [get_bd_pins waveform_gen_3/resync]
+  connect_bd_net -net resync_dac_1 [get_bd_pins resync_dac] [get_bd_pins waveform_gen_0/resync] [get_bd_pins waveform_gen_1/resync] [get_bd_pins waveform_gen_2/resync]
   connect_bd_net -net signal_calib_0_signal_out [get_bd_pins S] [get_bd_pins signal_calib_0/signal_out]
   connect_bd_net -net signal_cfg_slice_0_calib_limit_lower [get_bd_pins signal_cfg_slice_0/calib_limit_lower]
   connect_bd_net -net signal_cfg_slice_0_calib_limit_upper [get_bd_pins signal_cfg_slice_0/calib_limit_upper]
@@ -1121,10 +1104,8 @@ proc create_hier_cell_signal_compose { parentCell nameHier } {
   connect_bd_net -net signal_cfg_slice_0_comp_2_cfg [get_bd_pins signal_cfg_slice_0/comp_2_cfg] [get_bd_pins waveform_gen_2/cfg_data]
   connect_bd_net -net signal_cfg_slice_0_comp_2_freq [get_bd_pins signal_cfg_slice_0/comp_2_freq] [get_bd_pins waveform_gen_2/freq]
   connect_bd_net -net signal_cfg_slice_0_comp_2_phase [get_bd_pins signal_cfg_slice_0/comp_2_phase] [get_bd_pins waveform_gen_2/phase]
-  connect_bd_net -net signal_cfg_slice_0_comp_3_amp [get_bd_pins signal_cfg_slice_0/comp_3_amp] [get_bd_pins waveform_gen_3/amplitude]
-  connect_bd_net -net signal_cfg_slice_0_comp_3_cfg [get_bd_pins signal_cfg_slice_0/comp_3_cfg] [get_bd_pins waveform_gen_3/cfg_data]
-  connect_bd_net -net signal_cfg_slice_0_comp_3_freq [get_bd_pins signal_cfg_slice_0/comp_3_freq] [get_bd_pins waveform_awg/freq] [get_bd_pins waveform_gen_3/freq]
-  connect_bd_net -net signal_cfg_slice_0_comp_3_phase [get_bd_pins signal_cfg_slice_0/comp_3_phase] [get_bd_pins waveform_awg/phase] [get_bd_pins waveform_gen_3/phase]
+  connect_bd_net -net signal_cfg_slice_0_comp_3_freq [get_bd_pins signal_cfg_slice_0/comp_3_freq] [get_bd_pins waveform_awg/freq]
+  connect_bd_net -net signal_cfg_slice_0_comp_3_phase [get_bd_pins signal_cfg_slice_0/comp_3_phase] [get_bd_pins waveform_awg/phase]
   connect_bd_net -net signal_cfg_slice_0_offset [get_bd_pins signal_cfg_slice_0/offset] [get_bd_pins signal_composer_0/offset]
   connect_bd_net -net signal_cfg_slice_0_ramp_freq [get_bd_pins signal_cfg_slice_0/ramp_freq] [get_bd_pins signal_ramp/freq]
   connect_bd_net -net signal_composer_0_signal_out [get_bd_pins signal_composer_0/signal_out] [get_bd_pins signal_ramp/signal_in]
@@ -1139,7 +1120,7 @@ proc create_hier_cell_signal_compose { parentCell nameHier } {
   connect_bd_net -net waveform_gen_1_wave [get_bd_pins signal_composer_0/wave1] [get_bd_pins waveform_gen_1/wave]
   connect_bd_net -net waveform_gen_2_m_axis_data_tvalid_1 [get_bd_pins signal_composer_0/valid2] [get_bd_pins waveform_gen_2/m_axis_data_tvalid_1]
   connect_bd_net -net waveform_gen_2_wave [get_bd_pins signal_composer_0/wave2] [get_bd_pins waveform_gen_2/wave]
-  connect_bd_net -net waveform_gen_3_m_axis_data_tvalid_1 [get_bd_pins signal_composer_0/valid3] [get_bd_pins waveform_gen_3/m_axis_data_tvalid_1]
+  connect_bd_net -net xlconstant_0_dout [get_bd_pins signal_composer_0/valid3] [get_bd_pins xlconstant_0/dout]
 
   # Restore current instance
   current_bd_instance $oldCurInst
@@ -2696,9 +2677,12 @@ proc create_hier_cell_DIO { parentCell nameHier } {
   # Create interface pins
 
   # Create pins
+  create_bd_pin -dir I aresetn
+  create_bd_pin -dir I -from 1663 -to 0 cfg_dac
   create_bd_pin -dir I -from 95 -to 0 cfg_in
   create_bd_pin -dir I -type clk clk
   create_bd_pin -dir O -from 31 -to 0 dio_data_clocked
+  create_bd_pin -dir I -from 1 -to 0 enable_dac
   create_bd_pin -dir IO ext_DIO2_N
   create_bd_pin -dir IO ext_DIO3_N
   create_bd_pin -dir IO ext_DIO4_N
@@ -2707,29 +2691,30 @@ proc create_hier_cell_DIO { parentCell nameHier } {
   create_bd_pin -dir IO ext_DIO6_P
   create_bd_pin -dir IO ext_DIO7_N
   create_bd_pin -dir IO ext_DIO7_P
+  create_bd_pin -dir I -from 1 -to 0 resync
+
+  # Create instance: hbridgewaveform_0, and set properties
+  set hbridgewaveform_0 [ create_bd_cell -type container -reference hbridgewaveform hbridgewaveform_0 ]
+  set_property -dict [ list \
+   CONFIG.ACTIVE_SIM_BD {hbridgewaveform.bd} \
+   CONFIG.ACTIVE_SYNTH_BD {hbridgewaveform.bd} \
+   CONFIG.ENABLE_DFX {0} \
+   CONFIG.LIST_SIM_BD {hbridgewaveform.bd} \
+   CONFIG.LIST_SYNTH_BD {hbridgewaveform.bd} \
+   CONFIG.LOCK_PROPAGATE {0} \
+ ] $hbridgewaveform_0
+
+  # Create instance: hbridgewaveform_1, and set properties
+  set hbridgewaveform_1 [ create_bd_cell -type container -reference hbridgewaveform hbridgewaveform_1 ]
+  set_property -dict [ list \
+   CONFIG.ACTIVE_SIM_BD {hbridgewaveform.bd} \
+   CONFIG.ACTIVE_SYNTH_BD {hbridgewaveform.bd} \
+   CONFIG.ENABLE_DFX {0} \
+   CONFIG.LIST_SIM_BD {hbridgewaveform.bd} \
+   CONFIG.LIST_SYNTH_BD {hbridgewaveform.bd} \
+   CONFIG.LOCK_PROPAGATE {0} \
+ ] $hbridgewaveform_1
 
-  # Create instance: rp_iobuf_0, and set properties
-  set block_name rp_iobuf
-  set block_cell_name rp_iobuf_0
-  if { [catch {set rp_iobuf_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
-     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
-     return 1
-   } elseif { $rp_iobuf_0 eq "" } {
-     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
-     return 1
-   }
-  
-  # Create instance: rp_iobuf_1, and set properties
-  set block_name rp_iobuf
-  set block_cell_name rp_iobuf_1
-  if { [catch {set rp_iobuf_1 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
-     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
-     return 1
-   } elseif { $rp_iobuf_1 eq "" } {
-     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
-     return 1
-   }
-  
   # Create instance: rp_iobuf_2, and set properties
   set block_name rp_iobuf
   set block_cell_name rp_iobuf_2
@@ -2796,6 +2781,92 @@ proc create_hier_cell_DIO { parentCell nameHier } {
      return 1
    }
   
+  # Create instance: rp_iobuf_8, and set properties
+  set block_name rp_iobuf
+  set block_cell_name rp_iobuf_8
+  if { [catch {set rp_iobuf_8 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   } elseif { $rp_iobuf_8 eq "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   }
+  
+  # Create instance: rp_iobuf_9, and set properties
+  set block_name rp_iobuf
+  set block_cell_name rp_iobuf_9
+  if { [catch {set rp_iobuf_9 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   } elseif { $rp_iobuf_9 eq "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   }
+  
+  # Create instance: util_vector_logic_0, and set properties
+  set util_vector_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_0 ]
+  set_property -dict [ list \
+   CONFIG.C_OPERATION {and} \
+   CONFIG.C_SIZE {1} \
+   CONFIG.LOGO_FILE {data/sym_andgate.png} \
+ ] $util_vector_logic_0
+
+  # Create instance: util_vector_logic_1, and set properties
+  set util_vector_logic_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_1 ]
+  set_property -dict [ list \
+   CONFIG.C_OPERATION {or} \
+   CONFIG.C_SIZE {1} \
+   CONFIG.LOGO_FILE {data/sym_orgate.png} \
+ ] $util_vector_logic_1
+
+  # Create instance: util_vector_logic_2, and set properties
+  set util_vector_logic_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_2 ]
+  set_property -dict [ list \
+   CONFIG.C_OPERATION {or} \
+   CONFIG.C_SIZE {1} \
+   CONFIG.LOGO_FILE {data/sym_orgate.png} \
+ ] $util_vector_logic_2
+
+  # Create instance: util_vector_logic_3, and set properties
+  set util_vector_logic_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_3 ]
+  set_property -dict [ list \
+   CONFIG.C_OPERATION {or} \
+   CONFIG.C_SIZE {1} \
+   CONFIG.LOGO_FILE {data/sym_orgate.png} \
+ ] $util_vector_logic_3
+
+  # Create instance: util_vector_logic_4, and set properties
+  set util_vector_logic_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_4 ]
+  set_property -dict [ list \
+   CONFIG.C_OPERATION {or} \
+   CONFIG.C_SIZE {1} \
+   CONFIG.LOGO_FILE {data/sym_orgate.png} \
+ ] $util_vector_logic_4
+
+  # Create instance: util_vector_logic_5, and set properties
+  set util_vector_logic_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_5 ]
+  set_property -dict [ list \
+   CONFIG.C_OPERATION {or} \
+   CONFIG.C_SIZE {1} \
+   CONFIG.LOGO_FILE {data/sym_orgate.png} \
+ ] $util_vector_logic_5
+
+  # Create instance: util_vector_logic_6, and set properties
+  set util_vector_logic_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_6 ]
+  set_property -dict [ list \
+   CONFIG.C_OPERATION {and} \
+   CONFIG.C_SIZE {1} \
+   CONFIG.LOGO_FILE {data/sym_andgate.png} \
+ ] $util_vector_logic_6
+
+  # Create instance: util_vector_logic_7, and set properties
+  set util_vector_logic_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_7 ]
+  set_property -dict [ list \
+   CONFIG.C_OPERATION {or} \
+   CONFIG.C_SIZE {1} \
+   CONFIG.LOGO_FILE {data/sym_orgate.png} \
+ ] $util_vector_logic_7
+
   # Create instance: xlconcat_0, and set properties
   set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ]
   set_property -dict [ list \
@@ -2965,6 +3036,150 @@ proc create_hier_cell_DIO { parentCell nameHier } {
    CONFIG.DOUT_WIDTH {1} \
  ] $xlslice_17
 
+  # Create instance: xlslice_18, and set properties
+  set xlslice_18 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_18 ]
+  set_property -dict [ list \
+   CONFIG.DIN_WIDTH {2} \
+ ] $xlslice_18
+
+  # Create instance: xlslice_19, and set properties
+  set xlslice_19 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_19 ]
+  set_property -dict [ list \
+   CONFIG.DIN_FROM {175} \
+   CONFIG.DIN_TO {128} \
+   CONFIG.DIN_WIDTH {832} \
+   CONFIG.DOUT_WIDTH {48} \
+ ] $xlslice_19
+
+  # Create instance: xlslice_20, and set properties
+  set xlslice_20 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_20 ]
+  set_property -dict [ list \
+   CONFIG.DIN_FROM {239} \
+   CONFIG.DIN_TO {192} \
+   CONFIG.DIN_WIDTH {832} \
+   CONFIG.DOUT_WIDTH {48} \
+ ] $xlslice_20
+
+  # Create instance: xlslice_21, and set properties
+  set xlslice_21 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_21 ]
+  set_property -dict [ list \
+   CONFIG.DIN_FROM {127} \
+   CONFIG.DIN_TO {112} \
+   CONFIG.DIN_WIDTH {832} \
+   CONFIG.DOUT_WIDTH {16} \
+ ] $xlslice_21
+
+  # Create instance: xlslice_22, and set properties
+  set xlslice_22 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_22 ]
+  set_property -dict [ list \
+   CONFIG.DIN_WIDTH {2} \
+ ] $xlslice_22
+
+  # Create instance: xlslice_23, and set properties
+  set xlslice_23 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_23 ]
+  set_property -dict [ list \
+   CONFIG.DIN_FROM {95} \
+   CONFIG.DIN_TO {88} \
+   CONFIG.DIN_WIDTH {96} \
+   CONFIG.DOUT_WIDTH {8} \
+ ] $xlslice_23
+
+  # Create instance: xlslice_24, and set properties
+  set xlslice_24 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_24 ]
+  set_property -dict [ list \
+   CONFIG.DIN_WIDTH {8} \
+ ] $xlslice_24
+
+  # Create instance: xlslice_25, and set properties
+  set xlslice_25 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_25 ]
+  set_property -dict [ list \
+   CONFIG.DIN_FROM {1} \
+   CONFIG.DIN_TO {1} \
+   CONFIG.DIN_WIDTH {8} \
+   CONFIG.DOUT_WIDTH {1} \
+ ] $xlslice_25
+
+  # Create instance: xlslice_26, and set properties
+  set xlslice_26 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_26 ]
+  set_property -dict [ list \
+   CONFIG.DIN_FROM {175} \
+   CONFIG.DIN_TO {128} \
+   CONFIG.DIN_WIDTH {832} \
+   CONFIG.DOUT_WIDTH {48} \
+ ] $xlslice_26
+
+  # Create instance: xlslice_27, and set properties
+  set xlslice_27 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_27 ]
+  set_property -dict [ list \
+   CONFIG.DIN_FROM {239} \
+   CONFIG.DIN_TO {192} \
+   CONFIG.DIN_WIDTH {832} \
+   CONFIG.DOUT_WIDTH {48} \
+ ] $xlslice_27
+
+  # Create instance: xlslice_28, and set properties
+  set xlslice_28 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_28 ]
+  set_property -dict [ list \
+   CONFIG.DIN_FROM {127} \
+   CONFIG.DIN_TO {112} \
+   CONFIG.DIN_WIDTH {832} \
+   CONFIG.DOUT_WIDTH {16} \
+ ] $xlslice_28
+
+  # Create instance: xlslice_29, and set properties
+  set xlslice_29 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_29 ]
+  set_property -dict [ list \
+   CONFIG.DIN_FROM {1} \
+   CONFIG.DIN_TO {1} \
+   CONFIG.DIN_WIDTH {2} \
+   CONFIG.DOUT_WIDTH {1} \
+ ] $xlslice_29
+
+  # Create instance: xlslice_30, and set properties
+  set xlslice_30 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_30 ]
+  set_property -dict [ list \
+   CONFIG.DIN_FROM {1663} \
+   CONFIG.DIN_TO {832} \
+   CONFIG.DIN_WIDTH {1664} \
+   CONFIG.DOUT_WIDTH {832} \
+ ] $xlslice_30
+
+  # Create instance: xlslice_31, and set properties
+  set xlslice_31 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_31 ]
+  set_property -dict [ list \
+   CONFIG.DIN_FROM {831} \
+   CONFIG.DIN_TO {0} \
+   CONFIG.DIN_WIDTH {1664} \
+   CONFIG.DOUT_WIDTH {832} \
+ ] $xlslice_31
+
+  # Create instance: xlslice_32, and set properties
+  set xlslice_32 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_32 ]
+  set_property -dict [ list \
+   CONFIG.DIN_FROM {1} \
+   CONFIG.DIN_TO {1} \
+   CONFIG.DIN_WIDTH {2} \
+   CONFIG.DOUT_WIDTH {1} \
+ ] $xlslice_32
+
+  # Create instance: xlslice_33, and set properties
+  set xlslice_33 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_33 ]
+  set_property -dict [ list \
+   CONFIG.DIN_FROM {2} \
+   CONFIG.DIN_TO {2} \
+   CONFIG.DIN_WIDTH {8} \
+   CONFIG.DOUT_WIDTH {1} \
+ ] $xlslice_33
+
+  # Create instance: xlslice_34, and set properties
+  set xlslice_34 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_34 ]
+  set_property -dict [ list \
+   CONFIG.DIN_FROM {3} \
+   CONFIG.DIN_TO {3} \
+   CONFIG.DIN_WIDTH {8} \
+   CONFIG.DOUT_WIDTH {1} \
+ ] $xlslice_34
+
   # Create port connections
   connect_bd_net -net Net [get_bd_pins ext_DIO6_P] [get_bd_pins rp_iobuf_2/val_tri]
   connect_bd_net -net Net1 [get_bd_pins ext_DIO6_N] [get_bd_pins rp_iobuf_3/val_tri]
@@ -2972,38 +3187,71 @@ proc create_hier_cell_DIO { parentCell nameHier } {
   connect_bd_net -net Net3 [get_bd_pins ext_DIO4_N] [get_bd_pins rp_iobuf_5/val_tri]
   connect_bd_net -net Net4 [get_bd_pins ext_DIO3_N] [get_bd_pins rp_iobuf_6/val_tri]
   connect_bd_net -net Net5 [get_bd_pins ext_DIO2_N] [get_bd_pins rp_iobuf_7/val_tri]
-  connect_bd_net -net Net6 [get_bd_pins ext_DIO7_P] [get_bd_pins rp_iobuf_0/val_tri]
-  connect_bd_net -net Net7 [get_bd_pins ext_DIO7_N] [get_bd_pins rp_iobuf_1/val_tri]
-  connect_bd_net -net clk_wiz_0_clk_internal [get_bd_pins clk] [get_bd_pins rp_iobuf_0/clk] [get_bd_pins rp_iobuf_1/clk] [get_bd_pins rp_iobuf_2/clk] [get_bd_pins rp_iobuf_3/clk] [get_bd_pins rp_iobuf_4/clk] [get_bd_pins rp_iobuf_5/clk] [get_bd_pins rp_iobuf_6/clk] [get_bd_pins rp_iobuf_7/clk]
-  connect_bd_net -net rp_iobuf_0_val_in_clocked [get_bd_pins rp_iobuf_0/val_in_clocked] [get_bd_pins xlconcat_0/In0]
-  connect_bd_net -net rp_iobuf_1_val_in_clocked [get_bd_pins rp_iobuf_1/val_in_clocked] [get_bd_pins xlconcat_0/In1]
+  connect_bd_net -net Net6 [get_bd_pins ext_DIO7_P] [get_bd_pins rp_iobuf_8/val_tri]
+  connect_bd_net -net Net7 [get_bd_pins ext_DIO7_N] [get_bd_pins rp_iobuf_9/val_tri]
+  connect_bd_net -net aresetn_1 [get_bd_pins aresetn] [get_bd_pins hbridgewaveform_0/aresetn] [get_bd_pins hbridgewaveform_1/aresetn]
+  connect_bd_net -net cfg_dac_1 [get_bd_pins cfg_dac] [get_bd_pins xlslice_30/Din] [get_bd_pins xlslice_31/Din]
+  connect_bd_net -net clk_wiz_0_clk_internal [get_bd_pins clk] [get_bd_pins hbridgewaveform_0/aclk] [get_bd_pins hbridgewaveform_1/aclk] [get_bd_pins rp_iobuf_2/clk] [get_bd_pins rp_iobuf_3/clk] [get_bd_pins rp_iobuf_4/clk] [get_bd_pins rp_iobuf_5/clk] [get_bd_pins rp_iobuf_6/clk] [get_bd_pins rp_iobuf_7/clk] [get_bd_pins rp_iobuf_8/clk] [get_bd_pins rp_iobuf_9/clk]
+  connect_bd_net -net enable_dac_1 [get_bd_pins enable_dac] [get_bd_pins xlslice_18/Din] [get_bd_pins xlslice_32/Din]
+  connect_bd_net -net enable_dac_2 [get_bd_pins hbridgewaveform_1/enable_dac] [get_bd_pins util_vector_logic_6/Res]
+  connect_bd_net -net hbridgewaveform_0_H1out [get_bd_pins hbridgewaveform_0/H1out] [get_bd_pins util_vector_logic_2/Op2]
+  connect_bd_net -net hbridgewaveform_0_H2out [get_bd_pins hbridgewaveform_0/H2out] [get_bd_pins util_vector_logic_3/Op2]
+  connect_bd_net -net hbridgewaveform_1_H1out [get_bd_pins hbridgewaveform_1/H1out] [get_bd_pins util_vector_logic_4/Op2]
+  connect_bd_net -net hbridgewaveform_1_H2out [get_bd_pins hbridgewaveform_1/H2out] [get_bd_pins util_vector_logic_5/Op2]
+  connect_bd_net -net resync_1 [get_bd_pins resync] [get_bd_pins xlslice_22/Din] [get_bd_pins xlslice_29/Din]
   connect_bd_net -net rp_iobuf_2_val_in_clocked [get_bd_pins rp_iobuf_2/val_in_clocked] [get_bd_pins xlconcat_0/In2]
   connect_bd_net -net rp_iobuf_3_val_in_clocked [get_bd_pins rp_iobuf_3/val_in_clocked] [get_bd_pins xlconcat_0/In3]
   connect_bd_net -net rp_iobuf_4_val_in_clocked [get_bd_pins rp_iobuf_4/val_in_clocked] [get_bd_pins xlconcat_0/In4]
   connect_bd_net -net rp_iobuf_5_val_in_clocked [get_bd_pins rp_iobuf_5/val_in_clocked] [get_bd_pins xlconcat_0/In5]
   connect_bd_net -net rp_iobuf_6_val_in_clocked [get_bd_pins rp_iobuf_6/val_in_clocked] [get_bd_pins xlconcat_0/In6]
   connect_bd_net -net rp_iobuf_7_val_in_clocked [get_bd_pins rp_iobuf_7/val_in_clocked] [get_bd_pins xlconcat_0/In7]
-  connect_bd_net -net system_cfg_data1 [get_bd_pins cfg_in] [get_bd_pins xlslice_4/Din] [get_bd_pins xlslice_5/Din]
+  connect_bd_net -net rp_iobuf_8_val_in_clocked [get_bd_pins rp_iobuf_8/val_in_clocked] [get_bd_pins xlconcat_0/In0]
+  connect_bd_net -net rp_iobuf_9_val_in_clocked [get_bd_pins rp_iobuf_9/val_in_clocked] [get_bd_pins xlconcat_0/In1]
+  connect_bd_net -net system_cfg_data1 [get_bd_pins cfg_in] [get_bd_pins xlslice_23/Din] [get_bd_pins xlslice_4/Din] [get_bd_pins xlslice_5/Din]
+  connect_bd_net -net util_vector_logic_0_Res [get_bd_pins hbridgewaveform_0/enable_dac] [get_bd_pins util_vector_logic_0/Res]
+  connect_bd_net -net util_vector_logic_1_Res [get_bd_pins util_vector_logic_0/Op1] [get_bd_pins util_vector_logic_1/Res]
+  connect_bd_net -net util_vector_logic_2_Res [get_bd_pins rp_iobuf_8/val_out] [get_bd_pins util_vector_logic_2/Res]
+  connect_bd_net -net util_vector_logic_3_Res [get_bd_pins rp_iobuf_9/val_out] [get_bd_pins util_vector_logic_3/Res]
+  connect_bd_net -net util_vector_logic_4_Res [get_bd_pins rp_iobuf_2/val_out] [get_bd_pins util_vector_logic_4/Res]
+  connect_bd_net -net util_vector_logic_5_Res [get_bd_pins rp_iobuf_3/val_out] [get_bd_pins util_vector_logic_5/Res]
+  connect_bd_net -net util_vector_logic_7_Res [get_bd_pins util_vector_logic_6/Op1] [get_bd_pins util_vector_logic_7/Res]
   connect_bd_net -net xlconcat_0_dout2 [get_bd_pins dio_data_clocked] [get_bd_pins xlconcat_0/dout]
   connect_bd_net -net xlconstant_1_dout [get_bd_pins xlconcat_0/In8] [get_bd_pins xlconstant_1/dout]
-  connect_bd_net -net xlslice_0_Dout [get_bd_pins rp_iobuf_0/val_out] [get_bd_pins xlslice_0/Dout]
-  connect_bd_net -net xlslice_10_Dout [get_bd_pins rp_iobuf_2/val_out] [get_bd_pins xlslice_10/Dout]
-  connect_bd_net -net xlslice_11_Dout [get_bd_pins rp_iobuf_3/val_out] [get_bd_pins xlslice_11/Dout]
+  connect_bd_net -net xlslice_0_Dout [get_bd_pins util_vector_logic_2/Op1] [get_bd_pins xlslice_0/Dout]
+  connect_bd_net -net xlslice_10_Dout [get_bd_pins util_vector_logic_4/Op1] [get_bd_pins xlslice_10/Dout]
+  connect_bd_net -net xlslice_11_Dout [get_bd_pins util_vector_logic_5/Op1] [get_bd_pins xlslice_11/Dout]
   connect_bd_net -net xlslice_12_Dout [get_bd_pins rp_iobuf_4/val_out] [get_bd_pins xlslice_12/Dout]
   connect_bd_net -net xlslice_13_Dout [get_bd_pins rp_iobuf_5/direction] [get_bd_pins xlslice_13/Dout]
   connect_bd_net -net xlslice_14_Dout [get_bd_pins rp_iobuf_6/direction] [get_bd_pins xlslice_14/Dout]
   connect_bd_net -net xlslice_15_Dout [get_bd_pins rp_iobuf_6/val_out] [get_bd_pins xlslice_15/Dout]
   connect_bd_net -net xlslice_16_Dout [get_bd_pins rp_iobuf_7/val_out] [get_bd_pins xlslice_16/Dout]
   connect_bd_net -net xlslice_17_Dout [get_bd_pins rp_iobuf_7/direction] [get_bd_pins xlslice_17/Dout]
+  connect_bd_net -net xlslice_18_Dout [get_bd_pins util_vector_logic_0/Op2] [get_bd_pins xlslice_18/Dout]
+  connect_bd_net -net xlslice_19_Dout [get_bd_pins hbridgewaveform_0/freq] [get_bd_pins xlslice_19/Dout]
   connect_bd_net -net xlslice_1_Dout [get_bd_pins rp_iobuf_2/direction] [get_bd_pins xlslice_1/Dout]
+  connect_bd_net -net xlslice_20_Dout [get_bd_pins hbridgewaveform_0/phase] [get_bd_pins xlslice_20/Dout]
+  connect_bd_net -net xlslice_21_Dout [get_bd_pins hbridgewaveform_0/pulswidth] [get_bd_pins xlslice_21/Dout]
+  connect_bd_net -net xlslice_22_Dout [get_bd_pins hbridgewaveform_0/resync] [get_bd_pins xlslice_22/Dout]
+  connect_bd_net -net xlslice_23_Dout [get_bd_pins xlslice_23/Dout] [get_bd_pins xlslice_24/Din] [get_bd_pins xlslice_25/Din] [get_bd_pins xlslice_33/Din] [get_bd_pins xlslice_34/Din]
+  connect_bd_net -net xlslice_24_Dout [get_bd_pins util_vector_logic_1/Op2] [get_bd_pins xlslice_24/Dout]
+  connect_bd_net -net xlslice_25_Dout [get_bd_pins util_vector_logic_1/Op1] [get_bd_pins xlslice_25/Dout]
+  connect_bd_net -net xlslice_26_Dout [get_bd_pins hbridgewaveform_1/phase] [get_bd_pins xlslice_26/Dout]
+  connect_bd_net -net xlslice_27_Dout [get_bd_pins hbridgewaveform_1/freq] [get_bd_pins xlslice_27/Dout]
+  connect_bd_net -net xlslice_28_Dout [get_bd_pins hbridgewaveform_1/pulswidth] [get_bd_pins xlslice_28/Dout]
+  connect_bd_net -net xlslice_29_Dout [get_bd_pins hbridgewaveform_1/resync] [get_bd_pins xlslice_29/Dout]
   connect_bd_net -net xlslice_2_Dout [get_bd_pins rp_iobuf_3/direction] [get_bd_pins xlslice_2/Dout]
+  connect_bd_net -net xlslice_30_Dout [get_bd_pins xlslice_26/Din] [get_bd_pins xlslice_27/Din] [get_bd_pins xlslice_28/Din] [get_bd_pins xlslice_30/Dout]
+  connect_bd_net -net xlslice_31_Dout [get_bd_pins xlslice_19/Din] [get_bd_pins xlslice_20/Din] [get_bd_pins xlslice_21/Din] [get_bd_pins xlslice_31/Dout]
+  connect_bd_net -net xlslice_32_Dout [get_bd_pins util_vector_logic_6/Op2] [get_bd_pins xlslice_32/Dout]
+  connect_bd_net -net xlslice_33_Dout [get_bd_pins util_vector_logic_7/Op1] [get_bd_pins xlslice_33/Dout]
+  connect_bd_net -net xlslice_34_Dout [get_bd_pins util_vector_logic_7/Op2] [get_bd_pins xlslice_34/Dout]
   connect_bd_net -net xlslice_3_Dout [get_bd_pins rp_iobuf_4/direction] [get_bd_pins xlslice_3/Dout]
   connect_bd_net -net xlslice_4_Dout [get_bd_pins xlslice_0/Din] [get_bd_pins xlslice_10/Din] [get_bd_pins xlslice_11/Din] [get_bd_pins xlslice_12/Din] [get_bd_pins xlslice_15/Din] [get_bd_pins xlslice_16/Din] [get_bd_pins xlslice_4/Dout] [get_bd_pins xlslice_6/Din] [get_bd_pins xlslice_9/Din]
   connect_bd_net -net xlslice_5_Dout [get_bd_pins xlslice_1/Din] [get_bd_pins xlslice_13/Din] [get_bd_pins xlslice_14/Din] [get_bd_pins xlslice_17/Din] [get_bd_pins xlslice_2/Din] [get_bd_pins xlslice_3/Din] [get_bd_pins xlslice_5/Dout] [get_bd_pins xlslice_7/Din] [get_bd_pins xlslice_8/Din]
   connect_bd_net -net xlslice_6_Dout [get_bd_pins rp_iobuf_5/val_out] [get_bd_pins xlslice_6/Dout]
-  connect_bd_net -net xlslice_7_Dout [get_bd_pins rp_iobuf_0/direction] [get_bd_pins xlslice_7/Dout]
-  connect_bd_net -net xlslice_8_Dout [get_bd_pins rp_iobuf_1/direction] [get_bd_pins xlslice_8/Dout]
-  connect_bd_net -net xlslice_9_Dout [get_bd_pins rp_iobuf_1/val_out] [get_bd_pins xlslice_9/Dout]
+  connect_bd_net -net xlslice_7_Dout [get_bd_pins rp_iobuf_8/direction] [get_bd_pins xlslice_7/Dout]
+  connect_bd_net -net xlslice_8_Dout [get_bd_pins rp_iobuf_9/direction] [get_bd_pins xlslice_8/Dout]
+  connect_bd_net -net xlslice_9_Dout [get_bd_pins util_vector_logic_3/Op1] [get_bd_pins xlslice_9/Dout]
 
   # Restore current instance
   current_bd_instance $oldCurInst
@@ -3369,8 +3617,8 @@ proc create_root_design { parentCell } {
   connect_bd_net -net Net3 [get_bd_ports ext_DIO3_P] [get_bd_pins reset_manager_0/instant_reset]
   connect_bd_net -net Net4 [get_bd_ports ext_DIO4_P] [get_bd_pins reset_manager_0/alive_signal]
   connect_bd_net -net Net5 [get_bd_ports ext_DIO5_P] [get_bd_pins reset_manager_0/master_trigger]
-  connect_bd_net -net Net6 [get_bd_ports ext_DIO7_P] [get_bd_pins DIO/ext_DIO7_P]
-  connect_bd_net -net Net7 [get_bd_ports ext_DIO7_N] [get_bd_pins DIO/ext_DIO7_N]
+  connect_bd_net -net Net6 [get_bd_ports ext_DIO7_N] [get_bd_pins DIO/ext_DIO7_N]
+  connect_bd_net -net Net7 [get_bd_ports ext_DIO7_P] [get_bd_pins DIO/ext_DIO7_P]
   connect_bd_net -net Net8 [get_bd_ports ext_DIO6_P] [get_bd_pins DIO/ext_DIO6_P]
   connect_bd_net -net Net9 [get_bd_ports ext_DIO6_N] [get_bd_pins DIO/ext_DIO6_N]
   connect_bd_net -net Net10 [get_bd_ports ext_DIO5_N] [get_bd_pins DIO/ext_DIO5_N]
@@ -3407,7 +3655,7 @@ proc create_root_design { parentCell } {
   connect_bd_net -net pdm_oa_dac [get_bd_pins fourier_synth_standard/oa_dac] [get_bd_pins sequencer/oa_dac]
   connect_bd_net -net pdm_pdm_sts [get_bd_pins sequencer/pdm_sts] [get_bd_pins system/curr_pdm_values]
   connect_bd_net -net proc_sys_reset_bram_peripheral_aresetn [get_bd_pins fourier_synth_standard/bram_aresetn] [get_bd_pins proc_sys_reset_bram/peripheral_aresetn] [get_bd_pins sequencer/bram_aresetn]
-  connect_bd_net -net proc_sys_reset_fourier_synth_peripheral_aresetn [get_bd_pins fourier_synth_standard/aresetn] [get_bd_pins proc_sys_reset_fourier_synth/peripheral_aresetn] [get_bd_pins system/aresetn]
+  connect_bd_net -net proc_sys_reset_fourier_synth_peripheral_aresetn [get_bd_pins DIO/aresetn] [get_bd_pins fourier_synth_standard/aresetn] [get_bd_pins proc_sys_reset_fourier_synth/peripheral_aresetn] [get_bd_pins system/aresetn]
   connect_bd_net -net proc_sys_reset_pdm_peripheral_aresetn [get_bd_pins proc_sys_reset_pdm/peripheral_aresetn] [get_bd_pins sequencer/aresetn]
   connect_bd_net -net proc_sys_reset_write_to_ram_peripheral_aresetn [get_bd_pins proc_sys_reset_write_to_ram/peripheral_aresetn] [get_bd_pins write_to_ram/aresetn]
   connect_bd_net -net proc_sys_reset_xadc_peripheral_aresetn [get_bd_pins proc_sys_reset_xadc/peripheral_aresetn] [get_bd_pins xadc_wiz_0/s_axi_aresetn]
@@ -3424,11 +3672,11 @@ proc create_root_design { parentCell } {
   connect_bd_net -net selectio_wiz_1_data_out_to_pins_p [get_bd_ports daisy_p_o] [get_bd_pins selectio_wiz_1/data_out_to_pins_p]
   connect_bd_net -net selectio_wiz_2_clk_out [get_bd_pins clk_wiz_1/clk_in1] [get_bd_pins selectio_wiz_2/clk_out]
   connect_bd_net -net selectio_wiz_2_data_in_to_device [get_bd_pins reset_manager_0/sata_trigger] [get_bd_pins selectio_wiz_2/data_in_to_device]
-  connect_bd_net -net sequencer_enable_dac [get_bd_pins fourier_synth_standard/enable_dac] [get_bd_pins sequencer/enable_dac]
-  connect_bd_net -net sequencer_resync_dac [get_bd_pins fourier_synth_standard/resync_dac] [get_bd_pins sequencer/resync_dac]
+  connect_bd_net -net sequencer_enable_dac [get_bd_pins DIO/enable_dac] [get_bd_pins fourier_synth_standard/enable_dac] [get_bd_pins sequencer/enable_dac]
+  connect_bd_net -net sequencer_resync_dac [get_bd_pins DIO/resync] [get_bd_pins fourier_synth_standard/resync_dac] [get_bd_pins sequencer/resync_dac]
   connect_bd_net -net sequencer_seq_ramp_down [get_bd_pins fourier_synth_standard/seq_ramp_down] [get_bd_pins sequencer/seq_ramp_down]
   connect_bd_net -net system_FCLK_RESET0_N [get_bd_pins system/FCLK_RESET0_N] [get_bd_pins util_vector_logic_1/Op1]
-  connect_bd_net -net system_cfg_data [get_bd_pins fourier_synth_standard/cfg_data] [get_bd_pins system/dac_cfg]
+  connect_bd_net -net system_cfg_data [get_bd_pins DIO/cfg_dac] [get_bd_pins fourier_synth_standard/cfg_data] [get_bd_pins system/dac_cfg]
   connect_bd_net -net system_cfg_data1 [get_bd_pins DIO/cfg_in] [get_bd_pins system/cfg_data] [get_bd_pins xlslice_1/Din] [get_bd_pins xlslice_2/Din] [get_bd_pins xlslice_3/Din] [get_bd_pins xlslice_6/Din]
   connect_bd_net -net system_counter_trigger_cfg [get_bd_pins counter_trigger/counter_trigger_cfg] [get_bd_pins system/counter_trigger_cfg]
   connect_bd_net -net system_peripheral_aresetn [get_bd_pins reset_manager_0/peripheral_aresetn] [get_bd_pins system/peripheral_aresetn]
diff --git a/src/fpga/bd/hbridgewaveform.tcl b/src/fpga/bd/hbridgewaveform.tcl
new file mode 100644
index 00000000..12a2d922
--- /dev/null
+++ b/src/fpga/bd/hbridgewaveform.tcl
@@ -0,0 +1,357 @@
+
+################################################################
+# This is a generated script based on design: hbridgewaveform
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+   set script_path [file normalize [info script]]
+   set script_folder [file dirname $script_path]
+   return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2021.2
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+   puts ""
+   catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+   return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source hbridgewaveform_script.tcl
+
+
+# The design that will be created by this Tcl script contains the following 
+# module references:
+# hbridge_signalgen
+
+# Please add the sources of those modules before sourcing this Tcl script.
+
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+   create_project project_1 myproj -part xc7z010clg400-1
+}
+
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name hbridgewaveform
+
+# This script was generated for a remote BD. To create a non-remote design,
+# change the variable <run_remote_bd_flow> to <0>.
+
+set run_remote_bd_flow 1
+if { $run_remote_bd_flow == 1 } {
+  # Set the reference directory for source file relative paths (by default 
+  # the value is script directory path)
+  set origin_dir ./.julia/dev/RedPitayaDAQServer/src/fpga/bd
+
+  # Use origin directory path location variable, if specified in the tcl shell
+  if { [info exists ::origin_dir_loc] } {
+     set origin_dir $::origin_dir_loc
+  }
+
+  set str_bd_folder [file normalize ${origin_dir}]
+  set str_bd_filepath ${str_bd_folder}/${design_name}/${design_name}.bd
+
+  # Check if remote design exists on disk
+  if { [file exists $str_bd_filepath ] == 1 } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2030 -severity "ERROR" "The remote BD file path <$str_bd_filepath> already exists!"}
+     common::send_gid_msg -ssname BD::TCL -id 2031 -severity "INFO" "To create a non-remote BD, change the variable <run_remote_bd_flow> to <0>."
+     common::send_gid_msg -ssname BD::TCL -id 2032 -severity "INFO" "Also make sure there is no design <$design_name> existing in your current project."
+
+     return 1
+  }
+
+  # Check if design exists in memory
+  set list_existing_designs [get_bd_designs -quiet $design_name]
+  if { $list_existing_designs ne "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2033 -severity "ERROR" "The design <$design_name> already exists in this project! Will not create the remote BD <$design_name> at the folder <$str_bd_folder>."}
+
+     common::send_gid_msg -ssname BD::TCL -id 2034 -severity "INFO" "To create a non-remote BD, change the variable <run_remote_bd_flow> to <0> or please set a different value to variable <design_name>."
+
+     return 1
+  }
+
+  # Check if design exists on disk within project
+  set list_existing_designs [get_files -quiet */${design_name}.bd]
+  if { $list_existing_designs ne "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2035 -severity "ERROR" "The design <$design_name> already exists in this project at location:
+    $list_existing_designs"}
+     catch {common::send_gid_msg -ssname BD::TCL -id 2036 -severity "ERROR" "Will not create the remote BD <$design_name> at the folder <$str_bd_folder>."}
+
+     common::send_gid_msg -ssname BD::TCL -id 2037 -severity "INFO" "To create a non-remote BD, change the variable <run_remote_bd_flow> to <0> or please set a different value to variable <design_name>."
+
+     return 1
+  }
+
+  # Now can create the remote BD
+  # NOTE - usage of <-dir> will create <$str_bd_folder/$design_name/$design_name.bd>
+  create_bd_design -dir $str_bd_folder $design_name
+} else {
+
+  # Create regular design
+  if { [catch {create_bd_design $design_name} errmsg] } {
+     common::send_gid_msg -ssname BD::TCL -id 2038 -severity "INFO" "Please set a different value to variable <design_name>."
+
+     return 1
+  }
+}
+
+current_bd_design $design_name
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+   set list_check_ips "\ 
+pavel-demin:user:axis_variable:1.0\
+xilinx.com:ip:dds_compiler:6.0\
+xilinx.com:ip:util_vector_logic:2.0\
+xilinx.com:ip:xlconcat:2.1\
+xilinx.com:ip:xlslice:1.0\
+"
+
+   set list_ips_missing ""
+   common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+   foreach ip_vlnv $list_check_ips {
+      set ip_obj [get_ipdefs -all $ip_vlnv]
+      if { $ip_obj eq "" } {
+         lappend list_ips_missing $ip_vlnv
+      }
+   }
+
+   if { $list_ips_missing ne "" } {
+      catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+      set bCheckIPsPassed 0
+   }
+
+}
+
+##################################################################
+# CHECK Modules
+##################################################################
+set bCheckModules 1
+if { $bCheckModules == 1 } {
+   set list_check_mods "\ 
+hbridge_signalgen\
+"
+
+   set list_mods_missing ""
+   common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
+
+   foreach mod_vlnv $list_check_mods {
+      if { [can_resolve_reference $mod_vlnv] == 0 } {
+         lappend list_mods_missing $mod_vlnv
+      }
+   }
+
+   if { $list_mods_missing ne "" } {
+      catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
+      common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above."
+      set bCheckIPsPassed 0
+   }
+}
+
+if { $bCheckIPsPassed != 1 } {
+  common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
+  return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+  variable script_folder
+  variable design_name
+
+  if { $parentCell eq "" } {
+     set parentCell [get_bd_cells /]
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+
+  # Create interface ports
+
+  # Create ports
+  set H1out [ create_bd_port -dir O -type data H1out ]
+  set H2out [ create_bd_port -dir O -type data H2out ]
+  set aclk [ create_bd_port -dir I -type clk -freq_hz 125000000 aclk ]
+  set aresetn [ create_bd_port -dir I -type rst aresetn ]
+  set enable_dac [ create_bd_port -dir I enable_dac ]
+  set freq [ create_bd_port -dir I -from 47 -to 0 freq ]
+  set phase [ create_bd_port -dir I -from 47 -to 0 phase ]
+  set pulswidth [ create_bd_port -dir I -from 15 -to 0 pulswidth ]
+  set resync [ create_bd_port -dir I resync ]
+
+  # Create instance: axis_variable_A_channel_1, and set properties
+  set axis_variable_A_channel_1 [ create_bd_cell -type ip -vlnv pavel-demin:user:axis_variable:1.0 axis_variable_A_channel_1 ]
+  set_property -dict [ list \
+   CONFIG.AXIS_TDATA_WIDTH {96} \
+ ] $axis_variable_A_channel_1
+
+  # Create instance: dds_compiler_A_channel_1, and set properties
+  set dds_compiler_A_channel_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:dds_compiler:6.0 dds_compiler_A_channel_1 ]
+  set_property -dict [ list \
+   CONFIG.Amplitude_Mode {Full_Range} \
+   CONFIG.DATA_Has_TLAST {Not_Required} \
+   CONFIG.DDS_Clock_Rate {125} \
+   CONFIG.Frequency_Resolution {4.440893e-7} \
+   CONFIG.Has_ACLKEN {false} \
+   CONFIG.Has_ARESETn {true} \
+   CONFIG.Has_Phase_Out {true} \
+   CONFIG.Has_TREADY {false} \
+   CONFIG.Latency {2} \
+   CONFIG.Latency_Configuration {Auto} \
+   CONFIG.M_DATA_Has_TUSER {Not_Required} \
+   CONFIG.M_PHASE_Has_TUSER {Not_Required} \
+   CONFIG.Noise_Shaping {None} \
+   CONFIG.Output_Frequency1 {0} \
+   CONFIG.Output_Selection {Sine} \
+   CONFIG.Output_Width {3} \
+   CONFIG.PINC1 {0} \
+   CONFIG.POFF1 {0} \
+   CONFIG.Parameter_Entry {Hardware_Parameters} \
+   CONFIG.PartsPresent {Phase_Generator_only} \
+   CONFIG.Phase_Increment {Programmable} \
+   CONFIG.Phase_Offset_Angles1 {0} \
+   CONFIG.Phase_Width {48} \
+   CONFIG.Phase_offset {Programmable} \
+   CONFIG.Resync {false} \
+   CONFIG.S_PHASE_Has_TUSER {Not_Required} \
+   CONFIG.Spurious_Free_Dynamic_Range {88} \
+ ] $dds_compiler_A_channel_1
+
+  # Create instance: hbridge_signalgen_0_upgraded_ipi, and set properties
+  set block_name hbridge_signalgen
+  set block_cell_name hbridge_signalgen_0_upgraded_ipi
+  if { [catch {set hbridge_signalgen_0_upgraded_ipi [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   } elseif { $hbridge_signalgen_0_upgraded_ipi eq "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
+     return 1
+   }
+    set_property -dict [ list \
+   CONFIG.AXIS_TDATA_PHASE_WIDTH {48} \
+   CONFIG.CFG_DATA_WIDTH {14} \
+ ] $hbridge_signalgen_0_upgraded_ipi
+
+  # Create instance: util_vector_logic_0, and set properties
+  set util_vector_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_0 ]
+  set_property -dict [ list \
+   CONFIG.C_OPERATION {not} \
+   CONFIG.C_SIZE {1} \
+   CONFIG.LOGO_FILE {data/sym_notgate.png} \
+ ] $util_vector_logic_0
+
+  # Create instance: util_vector_logic_1, and set properties
+  set util_vector_logic_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_1 ]
+  set_property -dict [ list \
+   CONFIG.C_SIZE {1} \
+ ] $util_vector_logic_1
+
+  # Create instance: xlconcat_A_channel_1, and set properties
+  set xlconcat_A_channel_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_A_channel_1 ]
+  set_property -dict [ list \
+   CONFIG.IN0_WIDTH {48} \
+   CONFIG.IN1_WIDTH {48} \
+   CONFIG.IN2_WIDTH {8} \
+   CONFIG.NUM_PORTS {2} \
+ ] $xlconcat_A_channel_1
+
+  # Create instance: xlslice_0, and set properties
+  set xlslice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 ]
+  set_property -dict [ list \
+   CONFIG.DIN_FROM {13} \
+   CONFIG.DIN_WIDTH {16} \
+   CONFIG.DOUT_WIDTH {14} \
+ ] $xlslice_0
+
+  # Create interface connections
+  connect_bd_intf_net -intf_net axis_variable_A_channel_1_M_AXIS [get_bd_intf_pins axis_variable_A_channel_1/M_AXIS] [get_bd_intf_pins dds_compiler_A_channel_1/S_AXIS_CONFIG]
+  connect_bd_intf_net -intf_net dds_compiler_A_channel_1_M_AXIS_PHASE [get_bd_intf_pins dds_compiler_A_channel_1/M_AXIS_PHASE] [get_bd_intf_pins hbridge_signalgen_0_upgraded_ipi/s_axis_phase]
+
+  # Create port connections
+  connect_bd_net -net aresetn_1 [get_bd_ports aresetn] [get_bd_pins axis_variable_A_channel_1/aresetn] [get_bd_pins hbridge_signalgen_0_upgraded_ipi/aresetn] [get_bd_pins util_vector_logic_1/Op2]
+  connect_bd_net -net clk_wiz_0_clk_internal [get_bd_ports aclk] [get_bd_pins axis_variable_A_channel_1/aclk] [get_bd_pins dds_compiler_A_channel_1/aclk] [get_bd_pins hbridge_signalgen_0_upgraded_ipi/clk]
+  connect_bd_net -net enable_dac_1 [get_bd_ports enable_dac] [get_bd_pins hbridge_signalgen_0_upgraded_ipi/enable_dac]
+  connect_bd_net -net freq_1 [get_bd_ports freq] [get_bd_pins xlconcat_A_channel_1/In0]
+  connect_bd_net -net hbridge_signalgen_0_upgraded_ipi_H1 [get_bd_ports H1out] [get_bd_pins hbridge_signalgen_0_upgraded_ipi/H1]
+  connect_bd_net -net hbridge_signalgen_0_upgraded_ipi_H2 [get_bd_ports H2out] [get_bd_pins hbridge_signalgen_0_upgraded_ipi/H2]
+  connect_bd_net -net phase_1 [get_bd_ports phase] [get_bd_pins xlconcat_A_channel_1/In1]
+  connect_bd_net -net pulswidth_1 [get_bd_ports pulswidth] [get_bd_pins xlslice_0/Din]
+  connect_bd_net -net resync_1 [get_bd_ports resync] [get_bd_pins util_vector_logic_0/Op1]
+  connect_bd_net -net util_vector_logic_0_Res [get_bd_pins util_vector_logic_0/Res] [get_bd_pins util_vector_logic_1/Op1]
+  connect_bd_net -net util_vector_logic_1_Res [get_bd_pins dds_compiler_A_channel_1/aresetn] [get_bd_pins util_vector_logic_1/Res]
+  connect_bd_net -net xlconcat_A_channel_1_dout [get_bd_pins axis_variable_A_channel_1/cfg_data] [get_bd_pins xlconcat_A_channel_1/dout]
+  connect_bd_net -net xlslice_0_Dout [get_bd_pins hbridge_signalgen_0_upgraded_ipi/cfg_data] [get_bd_pins xlslice_0/Dout]
+
+  # Create address segments
+
+
+  # Restore current instance
+  current_bd_instance $oldCurInst
+
+  validate_bd_design
+  save_bd_design
+}
+# End of create_root_design()
+
+
+##################################################################
+# MAIN FLOW
+##################################################################
+
+create_root_design ""
+
+
diff --git a/src/fpga/build.tcl b/src/fpga/build.tcl
index 84a305a4..e2aded55 100644
--- a/src/fpga/build.tcl
+++ b/src/fpga/build.tcl
@@ -30,6 +30,7 @@ update_ip_catalog
 source src/fpga/bd/signal_calib.tcl
 source src/fpga/bd/signal_ramp.tcl
 source src/fpga/bd/waveform_gen.tcl
+source src/fpga/bd/hbridgewaveform.tcl
 source src/fpga/bd/bd.tcl
 
 # Create HDL wrapper for blockdesign
diff --git a/src/fpga/hdl/hbridge_signalgen.v b/src/fpga/hdl/hbridge_signalgen.v
new file mode 100644
index 00000000..9fedc0c0
--- /dev/null
+++ b/src/fpga/hdl/hbridge_signalgen.v
@@ -0,0 +1,82 @@
+`timescale 1ns / 1ps
+
+module hbridge_signalgen #
+(
+    parameter integer AXIS_TDATA_PHASE_WIDTH = 16,
+    parameter integer CFG_DATA_WIDTH = 16
+)
+(
+    // DDS Input
+    input  wire [AXIS_TDATA_PHASE_WIDTH-1:0] s_axis_tdata_phase,
+    input  wire s_axis_tvalid_phase,
+    
+    input [CFG_DATA_WIDTH-1:0] cfg_data,
+    
+    
+    input clk,
+    input aresetn,
+    input enable_dac,
+    output H1, H2
+);
+
+    reg signed [AXIS_TDATA_PHASE_WIDTH-1:0] phase;
+    reg signed [CFG_DATA_WIDTH-1:0] A;
+    reg h1, h2;
+
+	
+    always @(posedge clk)
+    begin
+        A <= cfg_data>>1;
+        
+        if (~aresetn)
+        begin
+            h1 <= 0;
+            h2 <= 0;
+            phase <= 0;
+        end
+        else
+        begin
+            phase <= s_axis_tdata_phase >>> (AXIS_TDATA_PHASE_WIDTH - CFG_DATA_WIDTH);
+            //4096 = (1<<<(CFG_DATA_WIDTH-2))
+
+            if  (enable_dac)
+            begin
+                if (phase < 4096-A)
+                begin
+                    h1 <= 0;
+                    h2 <= 0;
+                end
+                else if (phase < 4096+A)
+                begin
+                    h1 <= 0;
+                    h2 <= 1;
+                end
+                else if (phase < 12288-A)
+                begin
+                    h1 <= 0;
+                    h2 <= 0;
+                end
+                else if (phase < 12288+A)
+                begin
+                    h1 <= 1;
+                    h2 <= 0;
+                end
+                else
+                begin
+                    h1 <= 0;
+                    h2 <= 0;
+                end
+            end else begin
+                h1 <= 0;
+                h2 <= 0;
+            end
+
+         end
+         
+
+    end
+    
+assign H1 = h1;
+assign H2 = h2;
+
+endmodule
\ No newline at end of file

From c2088de8e9f31ca66794ca7f2312b98faaaabefc Mon Sep 17 00:00:00 2001
From: Tobias Knopp <tobias@knoppweb.de>
Date: Fri, 6 Dec 2024 18:02:09 +0100
Subject: [PATCH 31/38] some fix remaining issues in BD

---
 src/fpga/bd/bd.tcl               | 52 +++++---------------------------
 src/fpga/bd/hbridgewaveform.tcl  | 44 +++++++++++++++++++++++----
 src/fpga/hdl/hbridge_signalgen.v | 50 +++++++++++++-----------------
 3 files changed, 67 insertions(+), 79 deletions(-)

diff --git a/src/fpga/bd/bd.tcl b/src/fpga/bd/bd.tcl
index 9576f109..f85d8cfb 100644
--- a/src/fpga/bd/bd.tcl
+++ b/src/fpga/bd/bd.tcl
@@ -2803,22 +2803,6 @@ proc create_hier_cell_DIO { parentCell nameHier } {
      return 1
    }
   
-  # Create instance: util_vector_logic_0, and set properties
-  set util_vector_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_0 ]
-  set_property -dict [ list \
-   CONFIG.C_OPERATION {and} \
-   CONFIG.C_SIZE {1} \
-   CONFIG.LOGO_FILE {data/sym_andgate.png} \
- ] $util_vector_logic_0
-
-  # Create instance: util_vector_logic_1, and set properties
-  set util_vector_logic_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_1 ]
-  set_property -dict [ list \
-   CONFIG.C_OPERATION {or} \
-   CONFIG.C_SIZE {1} \
-   CONFIG.LOGO_FILE {data/sym_orgate.png} \
- ] $util_vector_logic_1
-
   # Create instance: util_vector_logic_2, and set properties
   set util_vector_logic_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_2 ]
   set_property -dict [ list \
@@ -2851,22 +2835,6 @@ proc create_hier_cell_DIO { parentCell nameHier } {
    CONFIG.LOGO_FILE {data/sym_orgate.png} \
  ] $util_vector_logic_5
 
-  # Create instance: util_vector_logic_6, and set properties
-  set util_vector_logic_6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_6 ]
-  set_property -dict [ list \
-   CONFIG.C_OPERATION {and} \
-   CONFIG.C_SIZE {1} \
-   CONFIG.LOGO_FILE {data/sym_andgate.png} \
- ] $util_vector_logic_6
-
-  # Create instance: util_vector_logic_7, and set properties
-  set util_vector_logic_7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_7 ]
-  set_property -dict [ list \
-   CONFIG.C_OPERATION {or} \
-   CONFIG.C_SIZE {1} \
-   CONFIG.LOGO_FILE {data/sym_orgate.png} \
- ] $util_vector_logic_7
-
   # Create instance: xlconcat_0, and set properties
   set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ]
   set_property -dict [ list \
@@ -3193,7 +3161,6 @@ proc create_hier_cell_DIO { parentCell nameHier } {
   connect_bd_net -net cfg_dac_1 [get_bd_pins cfg_dac] [get_bd_pins xlslice_30/Din] [get_bd_pins xlslice_31/Din]
   connect_bd_net -net clk_wiz_0_clk_internal [get_bd_pins clk] [get_bd_pins hbridgewaveform_0/aclk] [get_bd_pins hbridgewaveform_1/aclk] [get_bd_pins rp_iobuf_2/clk] [get_bd_pins rp_iobuf_3/clk] [get_bd_pins rp_iobuf_4/clk] [get_bd_pins rp_iobuf_5/clk] [get_bd_pins rp_iobuf_6/clk] [get_bd_pins rp_iobuf_7/clk] [get_bd_pins rp_iobuf_8/clk] [get_bd_pins rp_iobuf_9/clk]
   connect_bd_net -net enable_dac_1 [get_bd_pins enable_dac] [get_bd_pins xlslice_18/Din] [get_bd_pins xlslice_32/Din]
-  connect_bd_net -net enable_dac_2 [get_bd_pins hbridgewaveform_1/enable_dac] [get_bd_pins util_vector_logic_6/Res]
   connect_bd_net -net hbridgewaveform_0_H1out [get_bd_pins hbridgewaveform_0/H1out] [get_bd_pins util_vector_logic_2/Op2]
   connect_bd_net -net hbridgewaveform_0_H2out [get_bd_pins hbridgewaveform_0/H2out] [get_bd_pins util_vector_logic_3/Op2]
   connect_bd_net -net hbridgewaveform_1_H1out [get_bd_pins hbridgewaveform_1/H1out] [get_bd_pins util_vector_logic_4/Op2]
@@ -3208,13 +3175,10 @@ proc create_hier_cell_DIO { parentCell nameHier } {
   connect_bd_net -net rp_iobuf_8_val_in_clocked [get_bd_pins rp_iobuf_8/val_in_clocked] [get_bd_pins xlconcat_0/In0]
   connect_bd_net -net rp_iobuf_9_val_in_clocked [get_bd_pins rp_iobuf_9/val_in_clocked] [get_bd_pins xlconcat_0/In1]
   connect_bd_net -net system_cfg_data1 [get_bd_pins cfg_in] [get_bd_pins xlslice_23/Din] [get_bd_pins xlslice_4/Din] [get_bd_pins xlslice_5/Din]
-  connect_bd_net -net util_vector_logic_0_Res [get_bd_pins hbridgewaveform_0/enable_dac] [get_bd_pins util_vector_logic_0/Res]
-  connect_bd_net -net util_vector_logic_1_Res [get_bd_pins util_vector_logic_0/Op1] [get_bd_pins util_vector_logic_1/Res]
   connect_bd_net -net util_vector_logic_2_Res [get_bd_pins rp_iobuf_8/val_out] [get_bd_pins util_vector_logic_2/Res]
   connect_bd_net -net util_vector_logic_3_Res [get_bd_pins rp_iobuf_9/val_out] [get_bd_pins util_vector_logic_3/Res]
   connect_bd_net -net util_vector_logic_4_Res [get_bd_pins rp_iobuf_2/val_out] [get_bd_pins util_vector_logic_4/Res]
   connect_bd_net -net util_vector_logic_5_Res [get_bd_pins rp_iobuf_3/val_out] [get_bd_pins util_vector_logic_5/Res]
-  connect_bd_net -net util_vector_logic_7_Res [get_bd_pins util_vector_logic_6/Op1] [get_bd_pins util_vector_logic_7/Res]
   connect_bd_net -net xlconcat_0_dout2 [get_bd_pins dio_data_clocked] [get_bd_pins xlconcat_0/dout]
   connect_bd_net -net xlconstant_1_dout [get_bd_pins xlconcat_0/In8] [get_bd_pins xlconstant_1/dout]
   connect_bd_net -net xlslice_0_Dout [get_bd_pins util_vector_logic_2/Op1] [get_bd_pins xlslice_0/Dout]
@@ -3226,25 +3190,25 @@ proc create_hier_cell_DIO { parentCell nameHier } {
   connect_bd_net -net xlslice_15_Dout [get_bd_pins rp_iobuf_6/val_out] [get_bd_pins xlslice_15/Dout]
   connect_bd_net -net xlslice_16_Dout [get_bd_pins rp_iobuf_7/val_out] [get_bd_pins xlslice_16/Dout]
   connect_bd_net -net xlslice_17_Dout [get_bd_pins rp_iobuf_7/direction] [get_bd_pins xlslice_17/Dout]
-  connect_bd_net -net xlslice_18_Dout [get_bd_pins util_vector_logic_0/Op2] [get_bd_pins xlslice_18/Dout]
+  connect_bd_net -net xlslice_18_Dout [get_bd_pins hbridgewaveform_0/enable_All] [get_bd_pins xlslice_18/Dout]
   connect_bd_net -net xlslice_19_Dout [get_bd_pins hbridgewaveform_0/freq] [get_bd_pins xlslice_19/Dout]
   connect_bd_net -net xlslice_1_Dout [get_bd_pins rp_iobuf_2/direction] [get_bd_pins xlslice_1/Dout]
   connect_bd_net -net xlslice_20_Dout [get_bd_pins hbridgewaveform_0/phase] [get_bd_pins xlslice_20/Dout]
   connect_bd_net -net xlslice_21_Dout [get_bd_pins hbridgewaveform_0/pulswidth] [get_bd_pins xlslice_21/Dout]
   connect_bd_net -net xlslice_22_Dout [get_bd_pins hbridgewaveform_0/resync] [get_bd_pins xlslice_22/Dout]
   connect_bd_net -net xlslice_23_Dout [get_bd_pins xlslice_23/Dout] [get_bd_pins xlslice_24/Din] [get_bd_pins xlslice_25/Din] [get_bd_pins xlslice_33/Din] [get_bd_pins xlslice_34/Din]
-  connect_bd_net -net xlslice_24_Dout [get_bd_pins util_vector_logic_1/Op2] [get_bd_pins xlslice_24/Dout]
-  connect_bd_net -net xlslice_25_Dout [get_bd_pins util_vector_logic_1/Op1] [get_bd_pins xlslice_25/Dout]
-  connect_bd_net -net xlslice_26_Dout [get_bd_pins hbridgewaveform_1/phase] [get_bd_pins xlslice_26/Dout]
-  connect_bd_net -net xlslice_27_Dout [get_bd_pins hbridgewaveform_1/freq] [get_bd_pins xlslice_27/Dout]
+  connect_bd_net -net xlslice_24_Dout [get_bd_pins hbridgewaveform_0/enable_H1] [get_bd_pins xlslice_24/Dout]
+  connect_bd_net -net xlslice_25_Dout [get_bd_pins hbridgewaveform_0/enable_H2] [get_bd_pins xlslice_25/Dout]
+  connect_bd_net -net xlslice_26_Dout [get_bd_pins hbridgewaveform_1/freq] [get_bd_pins xlslice_26/Dout]
+  connect_bd_net -net xlslice_27_Dout [get_bd_pins hbridgewaveform_1/phase] [get_bd_pins xlslice_27/Dout]
   connect_bd_net -net xlslice_28_Dout [get_bd_pins hbridgewaveform_1/pulswidth] [get_bd_pins xlslice_28/Dout]
   connect_bd_net -net xlslice_29_Dout [get_bd_pins hbridgewaveform_1/resync] [get_bd_pins xlslice_29/Dout]
   connect_bd_net -net xlslice_2_Dout [get_bd_pins rp_iobuf_3/direction] [get_bd_pins xlslice_2/Dout]
   connect_bd_net -net xlslice_30_Dout [get_bd_pins xlslice_26/Din] [get_bd_pins xlslice_27/Din] [get_bd_pins xlslice_28/Din] [get_bd_pins xlslice_30/Dout]
   connect_bd_net -net xlslice_31_Dout [get_bd_pins xlslice_19/Din] [get_bd_pins xlslice_20/Din] [get_bd_pins xlslice_21/Din] [get_bd_pins xlslice_31/Dout]
-  connect_bd_net -net xlslice_32_Dout [get_bd_pins util_vector_logic_6/Op2] [get_bd_pins xlslice_32/Dout]
-  connect_bd_net -net xlslice_33_Dout [get_bd_pins util_vector_logic_7/Op1] [get_bd_pins xlslice_33/Dout]
-  connect_bd_net -net xlslice_34_Dout [get_bd_pins util_vector_logic_7/Op2] [get_bd_pins xlslice_34/Dout]
+  connect_bd_net -net xlslice_32_Dout [get_bd_pins hbridgewaveform_1/enable_All] [get_bd_pins xlslice_32/Dout]
+  connect_bd_net -net xlslice_33_Dout [get_bd_pins hbridgewaveform_1/enable_H1] [get_bd_pins xlslice_33/Dout]
+  connect_bd_net -net xlslice_34_Dout [get_bd_pins hbridgewaveform_1/enable_H2] [get_bd_pins xlslice_34/Dout]
   connect_bd_net -net xlslice_3_Dout [get_bd_pins rp_iobuf_4/direction] [get_bd_pins xlslice_3/Dout]
   connect_bd_net -net xlslice_4_Dout [get_bd_pins xlslice_0/Din] [get_bd_pins xlslice_10/Din] [get_bd_pins xlslice_11/Din] [get_bd_pins xlslice_12/Din] [get_bd_pins xlslice_15/Din] [get_bd_pins xlslice_16/Din] [get_bd_pins xlslice_4/Dout] [get_bd_pins xlslice_6/Din] [get_bd_pins xlslice_9/Din]
   connect_bd_net -net xlslice_5_Dout [get_bd_pins xlslice_1/Din] [get_bd_pins xlslice_13/Din] [get_bd_pins xlslice_14/Din] [get_bd_pins xlslice_17/Din] [get_bd_pins xlslice_2/Din] [get_bd_pins xlslice_3/Din] [get_bd_pins xlslice_5/Dout] [get_bd_pins xlslice_7/Din] [get_bd_pins xlslice_8/Din]
diff --git a/src/fpga/bd/hbridgewaveform.tcl b/src/fpga/bd/hbridgewaveform.tcl
index 12a2d922..d2f98ab8 100644
--- a/src/fpga/bd/hbridgewaveform.tcl
+++ b/src/fpga/bd/hbridgewaveform.tcl
@@ -223,11 +223,13 @@ proc create_root_design { parentCell } {
   # Create interface ports
 
   # Create ports
-  set H1out [ create_bd_port -dir O -type data H1out ]
-  set H2out [ create_bd_port -dir O -type data H2out ]
+  set H1out [ create_bd_port -dir O -from 0 -to 0 -type data H1out ]
+  set H2out [ create_bd_port -dir O -from 0 -to 0 -type data H2out ]
   set aclk [ create_bd_port -dir I -type clk -freq_hz 125000000 aclk ]
   set aresetn [ create_bd_port -dir I -type rst aresetn ]
-  set enable_dac [ create_bd_port -dir I enable_dac ]
+  set enable_All [ create_bd_port -dir I enable_All ]
+  set enable_H1 [ create_bd_port -dir I -type data enable_H1 ]
+  set enable_H2 [ create_bd_port -dir I -type data enable_H2 ]
   set freq [ create_bd_port -dir I -from 47 -to 0 freq ]
   set phase [ create_bd_port -dir I -from 47 -to 0 phase ]
   set pulswidth [ create_bd_port -dir I -from 15 -to 0 pulswidth ]
@@ -300,6 +302,30 @@ proc create_root_design { parentCell } {
    CONFIG.C_SIZE {1} \
  ] $util_vector_logic_1
 
+  # Create instance: util_vector_logic_2, and set properties
+  set util_vector_logic_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_2 ]
+  set_property -dict [ list \
+   CONFIG.C_SIZE {1} \
+ ] $util_vector_logic_2
+
+  # Create instance: util_vector_logic_3, and set properties
+  set util_vector_logic_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_3 ]
+  set_property -dict [ list \
+   CONFIG.C_SIZE {1} \
+ ] $util_vector_logic_3
+
+  # Create instance: util_vector_logic_4, and set properties
+  set util_vector_logic_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_4 ]
+  set_property -dict [ list \
+   CONFIG.C_SIZE {1} \
+ ] $util_vector_logic_4
+
+  # Create instance: util_vector_logic_5, and set properties
+  set util_vector_logic_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_5 ]
+  set_property -dict [ list \
+   CONFIG.C_SIZE {1} \
+ ] $util_vector_logic_5
+
   # Create instance: xlconcat_A_channel_1, and set properties
   set xlconcat_A_channel_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_A_channel_1 ]
   set_property -dict [ list \
@@ -324,15 +350,21 @@ proc create_root_design { parentCell } {
   # Create port connections
   connect_bd_net -net aresetn_1 [get_bd_ports aresetn] [get_bd_pins axis_variable_A_channel_1/aresetn] [get_bd_pins hbridge_signalgen_0_upgraded_ipi/aresetn] [get_bd_pins util_vector_logic_1/Op2]
   connect_bd_net -net clk_wiz_0_clk_internal [get_bd_ports aclk] [get_bd_pins axis_variable_A_channel_1/aclk] [get_bd_pins dds_compiler_A_channel_1/aclk] [get_bd_pins hbridge_signalgen_0_upgraded_ipi/clk]
-  connect_bd_net -net enable_dac_1 [get_bd_ports enable_dac] [get_bd_pins hbridge_signalgen_0_upgraded_ipi/enable_dac]
+  connect_bd_net -net enable_All_1 [get_bd_ports enable_All] [get_bd_pins util_vector_logic_4/Op1] [get_bd_pins util_vector_logic_5/Op1]
+  connect_bd_net -net enable_H1_1 [get_bd_ports enable_H1] [get_bd_pins util_vector_logic_2/Op1]
+  connect_bd_net -net enable_H2_1 [get_bd_ports enable_H2] [get_bd_pins util_vector_logic_3/Op1]
   connect_bd_net -net freq_1 [get_bd_ports freq] [get_bd_pins xlconcat_A_channel_1/In0]
-  connect_bd_net -net hbridge_signalgen_0_upgraded_ipi_H1 [get_bd_ports H1out] [get_bd_pins hbridge_signalgen_0_upgraded_ipi/H1]
-  connect_bd_net -net hbridge_signalgen_0_upgraded_ipi_H2 [get_bd_ports H2out] [get_bd_pins hbridge_signalgen_0_upgraded_ipi/H2]
+  connect_bd_net -net hbridge_signalgen_0_upgraded_ipi_H1 [get_bd_pins hbridge_signalgen_0_upgraded_ipi/H1] [get_bd_pins util_vector_logic_2/Op2]
+  connect_bd_net -net hbridge_signalgen_0_upgraded_ipi_H2 [get_bd_pins hbridge_signalgen_0_upgraded_ipi/H2] [get_bd_pins util_vector_logic_3/Op2]
   connect_bd_net -net phase_1 [get_bd_ports phase] [get_bd_pins xlconcat_A_channel_1/In1]
   connect_bd_net -net pulswidth_1 [get_bd_ports pulswidth] [get_bd_pins xlslice_0/Din]
   connect_bd_net -net resync_1 [get_bd_ports resync] [get_bd_pins util_vector_logic_0/Op1]
   connect_bd_net -net util_vector_logic_0_Res [get_bd_pins util_vector_logic_0/Res] [get_bd_pins util_vector_logic_1/Op1]
   connect_bd_net -net util_vector_logic_1_Res [get_bd_pins dds_compiler_A_channel_1/aresetn] [get_bd_pins util_vector_logic_1/Res]
+  connect_bd_net -net util_vector_logic_2_Res [get_bd_pins util_vector_logic_2/Res] [get_bd_pins util_vector_logic_4/Op2]
+  connect_bd_net -net util_vector_logic_3_Res [get_bd_pins util_vector_logic_3/Res] [get_bd_pins util_vector_logic_5/Op2]
+  connect_bd_net -net util_vector_logic_4_Res [get_bd_ports H1out] [get_bd_pins util_vector_logic_4/Res]
+  connect_bd_net -net util_vector_logic_5_Res [get_bd_ports H2out] [get_bd_pins util_vector_logic_5/Res]
   connect_bd_net -net xlconcat_A_channel_1_dout [get_bd_pins axis_variable_A_channel_1/cfg_data] [get_bd_pins xlconcat_A_channel_1/dout]
   connect_bd_net -net xlslice_0_Dout [get_bd_pins hbridge_signalgen_0_upgraded_ipi/cfg_data] [get_bd_pins xlslice_0/Dout]
 
diff --git a/src/fpga/hdl/hbridge_signalgen.v b/src/fpga/hdl/hbridge_signalgen.v
index 9fedc0c0..9b5e56eb 100644
--- a/src/fpga/hdl/hbridge_signalgen.v
+++ b/src/fpga/hdl/hbridge_signalgen.v
@@ -15,7 +15,6 @@ module hbridge_signalgen #
     
     input clk,
     input aresetn,
-    input enable_dac,
     output H1, H2
 );
 
@@ -39,41 +38,34 @@ module hbridge_signalgen #
             phase <= s_axis_tdata_phase >>> (AXIS_TDATA_PHASE_WIDTH - CFG_DATA_WIDTH);
             //4096 = (1<<<(CFG_DATA_WIDTH-2))
 
-            if  (enable_dac)
+            if (phase < 4096-A)
+            begin
+                h1 <= 0;
+                h2 <= 0;
+            end
+            else if (phase < 4096+A)
+            begin
+                h1 <= 0;
+                h2 <= 1;
+            end
+            else if (phase < 12288-A)
+            begin
+                h1 <= 0;
+                h2 <= 0;
+            end
+            else if (phase < 12288+A)
+            begin
+                h1 <= 1;
+                h2 <= 0;
+            end
+            else
             begin
-                if (phase < 4096-A)
-                begin
-                    h1 <= 0;
-                    h2 <= 0;
-                end
-                else if (phase < 4096+A)
-                begin
-                    h1 <= 0;
-                    h2 <= 1;
-                end
-                else if (phase < 12288-A)
-                begin
-                    h1 <= 0;
-                    h2 <= 0;
-                end
-                else if (phase < 12288+A)
-                begin
-                    h1 <= 1;
-                    h2 <= 0;
-                end
-                else
-                begin
-                    h1 <= 0;
-                    h2 <= 0;
-                end
-            end else begin
                 h1 <= 0;
                 h2 <= 0;
             end
 
          end
          
-
     end
     
 assign H1 = h1;

From 1503123deae17aa64ec287d22ac789c51c1c75f3 Mon Sep 17 00:00:00 2001
From: Tobias Knopp <tobias@knoppweb.de>
Date: Fri, 6 Dec 2024 19:45:49 +0100
Subject: [PATCH 32/38] update bd

---
 src/fpga/bd/hbridgewaveform.tcl | 96 +++++++++++++++++----------------
 1 file changed, 49 insertions(+), 47 deletions(-)

diff --git a/src/fpga/bd/hbridgewaveform.tcl b/src/fpga/bd/hbridgewaveform.tcl
index d2f98ab8..5e6adbc8 100644
--- a/src/fpga/bd/hbridgewaveform.tcl
+++ b/src/fpga/bd/hbridgewaveform.tcl
@@ -58,68 +58,70 @@ if { $list_projs eq "" } {
 variable design_name
 set design_name hbridgewaveform
 
-# This script was generated for a remote BD. To create a non-remote design,
-# change the variable <run_remote_bd_flow> to <0>.
-
-set run_remote_bd_flow 1
-if { $run_remote_bd_flow == 1 } {
-  # Set the reference directory for source file relative paths (by default 
-  # the value is script directory path)
-  set origin_dir ./.julia/dev/RedPitayaDAQServer/src/fpga/bd
-
-  # Use origin directory path location variable, if specified in the tcl shell
-  if { [info exists ::origin_dir_loc] } {
-     set origin_dir $::origin_dir_loc
-  }
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+#    create_bd_design $design_name
 
-  set str_bd_folder [file normalize ${origin_dir}]
-  set str_bd_filepath ${str_bd_folder}/${design_name}/${design_name}.bd
+# Creating design if needed
+set errMsg ""
+set nRet 0
 
-  # Check if remote design exists on disk
-  if { [file exists $str_bd_filepath ] == 1 } {
-     catch {common::send_gid_msg -ssname BD::TCL -id 2030 -severity "ERROR" "The remote BD file path <$str_bd_filepath> already exists!"}
-     common::send_gid_msg -ssname BD::TCL -id 2031 -severity "INFO" "To create a non-remote BD, change the variable <run_remote_bd_flow> to <0>."
-     common::send_gid_msg -ssname BD::TCL -id 2032 -severity "INFO" "Also make sure there is no design <$design_name> existing in your current project."
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
 
-     return 1
-  }
+if { ${design_name} eq "" } {
+   # USE CASES:
+   #    1) Design_name not set
 
-  # Check if design exists in memory
-  set list_existing_designs [get_bd_designs -quiet $design_name]
-  if { $list_existing_designs ne "" } {
-     catch {common::send_gid_msg -ssname BD::TCL -id 2033 -severity "ERROR" "The design <$design_name> already exists in this project! Will not create the remote BD <$design_name> at the folder <$str_bd_folder>."}
+   set errMsg "Please set the variable <design_name> to a non-empty value."
+   set nRet 1
 
-     common::send_gid_msg -ssname BD::TCL -id 2034 -severity "INFO" "To create a non-remote BD, change the variable <run_remote_bd_flow> to <0> or please set a different value to variable <design_name>."
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+   # USE CASES:
+   #    2): Current design opened AND is empty AND names same.
+   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
+   #    4): Current design opened AND is empty AND names diff; design_name exists in project.
 
-     return 1
-  }
+   if { $cur_design ne $design_name } {
+      common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
+      set design_name [get_property NAME $cur_design]
+   }
+   common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
 
-  # Check if design exists on disk within project
-  set list_existing_designs [get_files -quiet */${design_name}.bd]
-  if { $list_existing_designs ne "" } {
-     catch {common::send_gid_msg -ssname BD::TCL -id 2035 -severity "ERROR" "The design <$design_name> already exists in this project at location:
-    $list_existing_designs"}
-     catch {common::send_gid_msg -ssname BD::TCL -id 2036 -severity "ERROR" "Will not create the remote BD <$design_name> at the folder <$str_bd_folder>."}
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+   # USE CASES:
+   #    5) Current design opened AND has components AND same names.
 
-     common::send_gid_msg -ssname BD::TCL -id 2037 -severity "INFO" "To create a non-remote BD, change the variable <run_remote_bd_flow> to <0> or please set a different value to variable <design_name>."
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+   # USE CASES: 
+   #    6) Current opened design, has components, but diff names, design_name exists in project.
+   #    7) No opened design, design_name exists in project.
 
-     return 1
-  }
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 2
 
-  # Now can create the remote BD
-  # NOTE - usage of <-dir> will create <$str_bd_folder/$design_name/$design_name.bd>
-  create_bd_design -dir $str_bd_folder $design_name
 } else {
+   # USE CASES:
+   #    8) No opened design, design_name not in project.
+   #    9) Current opened design, has components, but diff names, design_name not in project.
 
-  # Create regular design
-  if { [catch {create_bd_design $design_name} errmsg] } {
-     common::send_gid_msg -ssname BD::TCL -id 2038 -severity "INFO" "Please set a different value to variable <design_name>."
+   common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+   create_bd_design $design_name
+
+   common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
+   current_bd_design $design_name
 
-     return 1
-  }
 }
 
-current_bd_design $design_name
+common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
+
+if { $nRet != 0 } {
+   catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
+   return $nRet
+}
 
 set bCheckIPsPassed 1
 ##################################################################

From 03b55110f28ea140e716470f9b465af61eaa8da7 Mon Sep 17 00:00:00 2001
From: Tobias Knopp <tobias@knoppweb.de>
Date: Fri, 6 Dec 2024 21:01:02 +0100
Subject: [PATCH 33/38] server changes for hbridge

---
 src/lib/rp-daq-lib.c       | 32 +++++++++++++++++-
 src/lib/rp-daq-lib.h       |  2 ++
 src/server/control.c       |  2 +-
 src/server/scpi_commands.c | 66 ++++++++++++++++++++++++++++++++++++++
 4 files changed, 100 insertions(+), 2 deletions(-)

diff --git a/src/lib/rp-daq-lib.c b/src/lib/rp-daq-lib.c
index 3cef3572..5393cac2 100644
--- a/src/lib/rp-daq-lib.c
+++ b/src/lib/rp-daq-lib.c
@@ -653,7 +653,7 @@ int setResyncDAC(int8_t value, int channel, int index) {
 		return -1;
 
 	int bitpos = 14;
-	// Reset bits are in the 14th bit of the respective DAC channel -> 14 and 30 
+	// Reset bits are in the 14th bit of the respective DAC channel -> 14 and 30
 	int offset = 8 * index + channel;
 	// clear the bit
 	*((int16_t *)(pdm_cfg + offset)) &= ~(1u << bitpos);
@@ -1232,6 +1232,36 @@ char* getPinFromInternalPINNumber(const uint32_t pinNumber) {
 	}
 }
 
+int getDIOHBridge(const char* pin) {
+	int pinInternal = getInternalPINNumber(pin);
+	if(pinInternal < 0) {
+		return -3;
+	}
+
+	uint32_t register_value = *((uint8_t *)(cfg + 11));
+	register_value = ((register_value & (0x1 << (pinInternal))) >> (pinInternal));
+
+	return register_value;
+}
+
+int setDIOHBridge(const char* pin, int value) {
+	int pinInternal = getInternalPINNumber(pin);
+	if(pinInternal < 0) {
+		return -3;
+	}
+
+	if(value == DIO_OUT) {
+		*((uint8_t *)(cfg + 11)) &= ~(0x1 << (pinInternal));
+	} else if(value == DIO_IN) {
+		*((uint8_t *)(cfg + 11)) |= (0x1 << (pinInternal));
+	} else {
+		return -1;
+	}
+
+	return 0;
+}
+
+
 int getDIODirection(const char* pin) {
 	int pinInternal = getInternalPINNumber(pin);
 	if(pinInternal < 0) {
diff --git a/src/lib/rp-daq-lib.h b/src/lib/rp-daq-lib.h
index f7cf6bcc..74628671 100644
--- a/src/lib/rp-daq-lib.h
+++ b/src/lib/rp-daq-lib.h
@@ -175,6 +175,8 @@ extern int getDIODirection(const char*);
 extern int setDIODirection(const char*, int);
 extern int setDIO(const char*, int);
 extern int getDIO(const char*);
+extern int getDIOHBridge(const char*);
+extern int setDIOHBridge(const char*, int);
 extern int setTriggerMode(int);
 extern int getTriggerMode();
 extern int setTriggerPropagation(int);
diff --git a/src/server/control.c b/src/server/control.c
index 1b6b422c..4b95eca7 100644
--- a/src/server/control.c
+++ b/src/server/control.c
@@ -131,7 +131,7 @@ bool getSequenceEnableValue(sequenceData_t *seqData, int seqStep, int channel) {
 
 bool getSequenceResyncValue(sequenceData_t *seqData, int seqStep, int channel) {
 	bool result = false;
-  	int numChan = numSlowDACChan > 2 ? 2 : numSlowDACChan;
+	int numChan = numSlowDACChan > 2 ? 2 : numSlowDACChan;
 	if (seqData->resyncLUT != NULL && channel < numChan) {
 		int localStep = seqStep % seqData->numStepsPerRepetition;
 		result = seqData->resyncLUT[localStep * numChan + channel];
diff --git a/src/server/scpi_commands.c b/src/server/scpi_commands.c
index b7308745..dd31c1f1 100644
--- a/src/server/scpi_commands.c
+++ b/src/server/scpi_commands.c
@@ -722,6 +722,68 @@ static scpi_result_t RP_DIO_GetDIOOutputP(scpi_t * context) {
 	return RP_DIO_GetDIOOutput(context, true);
 }
 
+
+
+
+static scpi_result_t RP_DIO_SetDIOHBridge(scpi_t * context, bool pinSide) {
+	int32_t numbers[1];
+	SCPI_CommandNumbers(context, numbers, 1, 1);
+	int pin_number = numbers[0];
+	char pin[8];
+	pinSide ? sprintf(pin, "DIO%d_P", pin_number) : sprintf(pin, "DIO%d_N", pin_number);
+
+	int32_t DIO_pin_output_selection;
+	if (!SCPI_ParamChoice(context, onoff_modes, &DIO_pin_output_selection, TRUE)) {
+		return returnSCPIBool(context, false);
+	}
+
+	int result = setDIOHBridge(pin, DIO_pin_output_selection);
+	if (result < 0) {
+		return returnSCPIBool(context, false);
+	}
+
+	return returnSCPIBool(context, true);
+}
+
+static scpi_result_t RP_DIO_SetDIOHBridgeN(scpi_t * context) {
+	return RP_DIO_SetDIOHBridge(context, false);
+}
+
+static scpi_result_t RP_DIO_SetDIOHBridgeP(scpi_t * context) {
+	return RP_DIO_SetDIOHBridge(context, true);
+}
+
+static scpi_result_t RP_DIO_GetDIOHBridge(scpi_t * context, bool pinSide) {
+	int32_t numbers[1];
+	SCPI_CommandNumbers(context, numbers, 1, 1);
+	int pin_number = numbers[0];
+	char pin[8];
+	pinSide ? sprintf(pin, "DIO%d_P", pin_number) : sprintf(pin, "DIO%d_N", pin_number);
+	
+	int result = getDIOHBridge(pin);
+
+	if (result < 0) {
+		return returnSCPIBool(context, false);
+	}
+
+	const char* name;
+	SCPI_ChoiceToName(onoff_modes, result,  &name);
+	SCPI_ResultText(context, name);
+
+	return SCPI_RES_OK;
+}
+
+static scpi_result_t RP_DIO_GetDIOHBridgeN(scpi_t * context) {
+	return RP_DIO_GetDIOHBridge(context, false);
+}
+
+static scpi_result_t RP_DIO_GetDIOHBridgeP(scpi_t * context) {
+	return RP_DIO_GetDIOHBridge(context, true);
+}
+
+
+
+
 static scpi_result_t RP_GetWatchdogMode(scpi_t * context) {
 	const char * name;
 
@@ -1791,6 +1853,10 @@ const scpi_command_t scpi_commands[] = {
 	{.pattern = "RP:DIO:Pin#:SideP", .callback = RP_DIO_SetDIOOutputP,}, 
 	{.pattern = "RP:DIO:Pin#:SideN?", .callback = RP_DIO_GetDIOOutputN,},
 	{.pattern = "RP:DIO:Pin#:SideP?", .callback = RP_DIO_GetDIOOutputP,},
+	{.pattern = "RP:DIO:Pin#:SideN:HBridge", .callback = RP_DIO_SetDIOHBridgeN,},
+	{.pattern = "RP:DIO:Pin#:SideP:HBridge", .callback = RP_DIO_SetDIOHBridgeP,},
+	{.pattern = "RP:DIO:Pin#:SideN:HBridge?", .callback = RP_DIO_GetDIOHBridgeN,},
+	{.pattern = "RP:DIO:Pin#:SideP:HBridge?", .callback = RP_DIO_GetDIOHBridgeP,},
 	{.pattern = "RP:WatchDogMode", .callback = RP_SetWatchdogMode,},
 	{.pattern = "RP:WatchDogMode?", .callback = RP_GetWatchdogMode,},
 	{.pattern = "RP:TRIGger:ALiVe", .callback = RP_SetKeepAliveReset,},

From 8d4f9ebc782befc5531676146606fe27d8dd7186 Mon Sep 17 00:00:00 2001
From: Tobias Knopp <tobias@knoppweb.de>
Date: Fri, 6 Dec 2024 21:02:21 +0100
Subject: [PATCH 34/38] change version to 10

---
 src/fpga/bd/bd.tcl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/fpga/bd/bd.tcl b/src/fpga/bd/bd.tcl
index f85d8cfb..d6049ccc 100644
--- a/src/fpga/bd/bd.tcl
+++ b/src/fpga/bd/bd.tcl
@@ -1567,7 +1567,7 @@ proc create_hier_cell_system_1 { parentCell nameHier } {
   # Create instance: image_version, and set properties
   set image_version [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 image_version ]
   set_property -dict [ list \
-   CONFIG.CONST_VAL {9} \
+   CONFIG.CONST_VAL {10} \
    CONFIG.CONST_WIDTH {32} \
  ] $image_version
 

From 3f89cc151bdc7cd8766aa8034085d2dbd4f3d4be Mon Sep 17 00:00:00 2001
From: root <root@rp-f04972.fritz.box>
Date: Mon, 9 Dec 2024 21:06:52 +0000
Subject: [PATCH 35/38] fix issue with sequence stepper

---
 src/lib/rp-daq-lib.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/lib/rp-daq-lib.c b/src/lib/rp-daq-lib.c
index 5393cac2..d84335f0 100644
--- a/src/lib/rp-daq-lib.c
+++ b/src/lib/rp-daq-lib.c
@@ -784,11 +784,11 @@ int setPDMAllValuesVolt(float voltage, int channel) {
 
 int getSamplesPerStep() {
 	int32_t value = *((int32_t *)(cfg + 4));
-	return value*2/getDecimation();
+	return value/getDecimation();
 }
 
 int setSamplesPerStep(int samples) {
-	*((int32_t *)(cfg + 4)) = samples/2*getDecimation();
+	*((int32_t *)(cfg + 4)) = samples*getDecimation();
 	return 0;
 }
 

From 5b565917e17d0e39a28b7ee717487c56e934f89d Mon Sep 17 00:00:00 2001
From: Tobias Knopp <tobias@knoppweb.de>
Date: Mon, 9 Dec 2024 22:08:10 +0100
Subject: [PATCH 36/38] fix sequence stepper issue

---
 src/fpga/hdl/sequence_stepper.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/fpga/hdl/sequence_stepper.v b/src/fpga/hdl/sequence_stepper.v
index 2431364e..4c1a77dc 100644
--- a/src/fpga/hdl/sequence_stepper.v
+++ b/src/fpga/hdl/sequence_stepper.v
@@ -18,7 +18,7 @@ begin
         step_counter_next <= 0;
         step_counter_local <= 0;
         step_counter_local_next <= 0;
-        step_size_local <= stepSize-1;
+        step_size_local <= (stepSize>>1)-1;
     end else begin
         step_counter_reg <= step_counter_next;
         step_counter_local <= step_counter_local_next;

From cefe2378c7851cc3c6e6efa88470be36a194f2d0 Mon Sep 17 00:00:00 2001
From: nHackel <nHackel@users.noreply.github.com>
Date: Fri, 13 Dec 2024 14:29:49 +0100
Subject: [PATCH 37/38] Add resync example and docs

---
 docs/make.jl                 |   3 +-
 docs/src/assets/resync.png   | Bin 0 -> 124857 bytes
 docs/src/examples/resync.md  |  21 ++++++++++
 docs/src/generation.md       |   2 +-
 docs/src/scpi.md             |   1 +
 src/examples/julia/resync.jl |  78 +++++++++++++++++++++++++++++++++++
 6 files changed, 103 insertions(+), 2 deletions(-)
 create mode 100644 docs/src/assets/resync.png
 create mode 100644 docs/src/examples/resync.md
 create mode 100644 src/examples/julia/resync.jl

diff --git a/docs/make.jl b/docs/make.jl
index 085f2756..5e4a0765 100644
--- a/docs/make.jl
+++ b/docs/make.jl
@@ -23,7 +23,8 @@ makedocs(
                           "Sequence Ramping" => "examples/seqRamping.md",
                           "Cluster" => "examples/cluster.md",
                           "Batch" => "examples/batch.md",
-                          "Continous Signal Acquisition" => "examples/producerConsumer.md"],
+                          "Continous Signal Acquisition" => "examples/producerConsumer.md", 
+                          "Resync" => "examples/resync.md",],
         "FPGA Development" => "fpga.md",
         "Development Tips" => "devtips.md",
         #"Getting Started" => "overview.md",
diff --git a/docs/src/assets/resync.png b/docs/src/assets/resync.png
new file mode 100644
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diff --git a/docs/src/examples/resync.md b/docs/src/examples/resync.md
new file mode 100644
index 00000000..63aa636f
--- /dev/null
+++ b/docs/src/examples/resync.md
@@ -0,0 +1,21 @@
+# Resync Example
+
+In this example we add a resync signal to a [sequence](sequence.md) to create a signal that resynchronizes phase and frequency of the DACs after every frame. This can be used to change the frequency and phase of a signal during measurement. While the resynchronization is synchronous due to the sequences, the actual new frequency and phase information is asynchronous as they are transmitted via SCPI.
+
+The example constructs a sequence with no offset and the very last step has the resync flag enabled. Note that during the resync-step the DAC outputs zero.
+
+## Julia Client
+
+This and all other examples are located in the ```examples``` [directory](https://github.com/tknopp/RedPitayaDAQServer/tree/master/src/examples/julia)
+
+````@eval
+# Adapted from https://github.com/JuliaDocs/Documenter.jl/issues/499
+using Markdown
+Markdown.parse("""
+```julia
+$(open(f->read(f, String), "../../../src/examples/julia/resync.jl"))
+```
+""")
+````
+
+![Resync Example Results](../assets/resync.png)
diff --git a/docs/src/generation.md b/docs/src/generation.md
index d57cfce4..e9b785a4 100644
--- a/docs/src/generation.md
+++ b/docs/src/generation.md
@@ -25,7 +25,7 @@ As the LUT used by the FPGA image is small in comparison with the main memory an
 
 Comparable to the sample transmission of the acquisition, this updating of the LUT is also a process with timing uncertainty as it is affected by the scheduling and execution of the RedPitayas CPU. While during the sample transmission samples could be lost because they were overwritten, in the signal generation wrong signals could be output because the server was too slow in updating the values. Here, the server tracks similar performance metrics and also features a status flag `lostSteps` for exactly this case. In its current implementation a safe step rate is at 12 kHz.
 
-Sequences and their steps also have additional features. A step can be marked such that during its duration the signal is set to 0. Furthermore, a step can be marked such that it triggers the ramp down. To make this easier to manage the server actually manages three sequences, that can be set individually: A ramp up, regular and ramp down sequence. The ramp up sequence is moved to the FPGA LUT at the acquisition start, followed by the regular sequence. Afterwards the ramp down sequence is started and during its execution the ramp down flag is set.
+Sequences and their steps also have additional features. A step can be marked such that during its duration the signal is set to 0. Furthermore, a step can be marked such that it triggers the ramp down. To make this easier to manage the server actually manages three sequences, that can be set individually: A ramp up, regular and ramp down sequence. The ramp up sequence is moved to the FPGA LUT at the acquisition start, followed by the regular sequence. Afterwards the ramp down sequence is started and during its execution the ramp down flag is set. Steps can also be marked to resync the fast DACs. During a resync, the signals are set to 0 and afterwards start again with their set phase and frequency. This can be used to change frequency and phase during measurements and s.t. the new phase and frequency is synchronous to the steps.
 
 ## Calibration
 Similar to the signal acquisition, there are also calibration scale ``c_{i, scale}`` and offset ``c_{i, offset}`` values  for the signal generation. These are stored in the EEPROM of the RedPitaya and can be updated by a client. The calibration values are always applied, even when the master trigger is off.
diff --git a/docs/src/scpi.md b/docs/src/scpi.md
index 9af44dbd..3ca6c1d2 100644
--- a/docs/src/scpi.md
+++ b/docs/src/scpi.md
@@ -53,6 +53,7 @@ During an active trigger the buffer is periodically updated by the server. If th
 | RP:DAC:SEQ:CHan? |  | Return the number of sequence channel |  | |
 | RP:DAC:SEQ:LUT | steps, repetitions | Instruct the server to receive a LUT over the data socket | C | RP:DAC:SEQ:LUT 10,2 |
 | RP:DAC:SEQ:LUT:ENaBle |  | Instruct the server to receive an enable LUT over the data socket of the same shape as the regular LUT| C | |
+| RP:DAC:SEQ:LUT:ReSYNC |  | Instruct the server to receive a resync LUT over the data socket of the same shape as the regular LUT| C | |
 | RP:DAC:SEQ:LUT:UP | steps, repetitions | Instruct the server to receive a ramp up LUT over the data socket | C | |
 | RP:DAC:SEQ:LUT:DOWN | steps, repetitions | Instruct the server to receive a ramp down LUT over the data socket | C | |
 | RP:DAC:SEQ:CLEAR |  | Clear the set sequence values from the FPGA buffer | C | |
diff --git a/src/examples/julia/resync.jl b/src/examples/julia/resync.jl
new file mode 100644
index 00000000..9759d411
--- /dev/null
+++ b/src/examples/julia/resync.jl
@@ -0,0 +1,78 @@
+using RedPitayaDAQServer
+using CairoMakie
+
+# obtain the URL of the RedPitaya
+include("config.jl")
+
+rp = RedPitaya(URLs[1])
+serverMode!(rp, CONFIGURATION)
+
+dec = 32
+modulus = 124800
+base_frequency = 125000000
+periods_per_step = 5
+samples_per_period = div(modulus, dec)
+periods_per_frame = 50
+frame_period = dec*samples_per_period*periods_per_frame / base_frequency
+steps_per_frame = div(50, periods_per_step)
+
+decimation!(rp, dec)
+samplesPerPeriod!(rp, samples_per_period)
+periodsPerFrame!(rp, periods_per_frame)
+
+for i in 1:2
+  frequencyDAC!(rp, i, 1, base_frequency / modulus)
+  signalTypeDAC!(rp, i, 1, "SINE")
+  amplitudeDAC!(rp, i, 1, 0.2)
+  phaseDAC!(rp, i, 1, 0)
+end
+triggerMode!(rp, INTERNAL)
+
+# Sequence Configuration
+clearSequence!(rp)
+stepsPerFrame!(rp, steps_per_frame)
+seqChan!(rp, 2)
+lut = reshape(fill(0.0f0, steps_per_frame), 1, :)
+lut = repeat(lut, outer = 2)
+enable = collect(fill(true, steps_per_frame))
+enable = reshape(enable, 1, :)
+enable = repeat(enable, outer = 2)
+# In the last step of each frame we resync the DACs 
+resync = vcat(fill(false, steps_per_frame - 1), [true])
+resync = reshape(resync, 1, :)
+resync = repeat(resync, outer = 2)
+seq = SimpleSequence(lut, 2, enable, resync)
+sequence!(rp, seq)
+
+samples_per_frame = samples_per_period * periods_per_frame
+target = samples_per_frame * 0.3 # After a third of a frame we want to switch frequency
+
+serverMode!(rp, ACQUISITION)
+masterTrigger!(rp, true)
+
+# Wait until we reach the target sample
+curr = currentWP(rp)
+while curr < target
+  # NOP
+  global curr = currentWP(rp)
+  sleep(0.01)
+end
+
+# Update the phase and frequency of the second channel
+frequencyDAC!(rp, 2, 1, base_frequency / (2*modulus))
+phaseDAC!(rp, 2, 1, pi)
+
+data = readFrames(rp, 0, 2)
+
+masterTrigger!(rp, false)
+serverMode!(rp, CONFIGURATION)
+
+
+fig = Figure()
+lines(fig[1, 1], vec(data[:, 2, :, 1]), axis = (ylabel = "First Frame", title = "All Periods"))
+lines(fig[1, 2], vec(data[:, 2, 1:5, 1]), axis = (ylabel = "First Frame", title = "First Periods"))
+lines(fig[2, 1], vec(data[:, 2, :, 2]), axis = (ylabel = "Second Frame",))
+lines(fig[2, 2], vec(data[:, 2, 1:5, 2]), axis = (ylabel = "Second Frame",))
+
+save(joinpath(@__DIR__(), "images", "resync.png"), fig)
+fig
\ No newline at end of file

From 34a932c1e76a1717d8c4d8dc838d3eca5fab70f0 Mon Sep 17 00:00:00 2001
From: nHackel <nHackel@users.noreply.github.com>
Date: Fri, 13 Dec 2024 14:30:16 +0100
Subject: [PATCH 38/38] Update Julia version to match 0.10 FPGA image

---
 src/client/julia/Project.toml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/client/julia/Project.toml b/src/client/julia/Project.toml
index 26393c4d..8637f193 100644
--- a/src/client/julia/Project.toml
+++ b/src/client/julia/Project.toml
@@ -1,7 +1,7 @@
 name = "RedPitayaDAQServer"
 uuid = "c544963a-496b-56d4-a5fe-f99a3f174c8f"
 authors = ["Tobias Knopp <tobias@knoppweb.de>"]
-version = "0.9.0"
+version = "0.10.0"
 
 [deps]
 LinearAlgebra = "37e2e46d-f89d-539d-b4ee-838fcccc9c8e"