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Create a driver for the LiteX/MiSoC UART #1
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Current status as of 13th April.
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@futaris - Once you have accepted the invite to the TimVideos organisation I can assign this task to you. |
As I mentioned on IRC (on 14 April 2017), http://www.spinics.net/lists/linux-serial/msg22724.html Linux UARTs need to be driven by an IRQ. The current qemu-litex serial hardware doesn't generate TXFULL and RXEMPTY Interrupts. We could hack around this using timers or something, but really the qemu hardware needs to be fixed. |
CONFIG_CONSOLE_POLL is only used for kgdb and the like: |
For most UARTs, like the uartlite (https://www.xilinx.com/support/documentation/ip_documentation/opb_uartlite.pdf) : If interrupts are enabled, an interrupt is generated when one of the following conditions is true:
Not sure if we are the same, as we only have TXFULL and RXEMPTY events. |
https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/uart/core.py#L163 https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/uart/core.py#L176 There's a typo in the python, but they mean tx_fifo becomes non-full and rx_fifo becomes non-empty. |
So as long as TX IRQ isn't active, we can TX. And if there are any bytes in RX buffer, the RX IRQ is active. Seems like we still might have to set up the IRQs (in linux), so that: !TX_IRQ - means we can TX But reading the python, it seems that self.ev / Event Manager just ORs ( || ) together the two events into one IRQ? https://github.com/m-labs/misoc/blob/master/misoc/interconnect/csr_eventmanager.py So theoretically, no IRQ will happen, until we get a TXFULL or a RX event. |
This is what I get for writing comments at night: The last comment doesn't make sense. It should be: So as long as TX IRQ isn't active, we can TX. And if there are any bytes in RX buffer, the RX IRQ is active. Seems like we still might have to set up the IRQs (in linux), so that: TX_IRQ - means we can TX But reading the python, it seems that self.ev / Event Manager just ORs ( || ) together the two events into one IRQ? https://github.com/m-labs/misoc/blob/master/misoc/interconnect/csr_eventmanager.py So theoretically, an IRQ will always happen, until the TX FIFO is full and RX FIFO is empty. Having the TX IRQ trigger off non full tx_fifo just means that we can't stuff as many bytes into the FIFO. |
A really hacked up version has now been committed!
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It's a simple MMIO FIFO object.
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