From 5ce29ae84db340244c3c3299f84713a88dec5171 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Fri, 19 May 2023 23:44:12 +0200 Subject: [PATCH] ArmPkg/ArmMmuLib AARCH64: Add missing ISB after page table update The helper that updates live page table entries writes a zero entry, invalidates the covered address range from the TLBs, and finally writes the actual entry. This ensures that no TLB conflicts can occur. Writing the final entry needs to complete before any translations can be performed, as otherwise, the zero entry, which describes an invalid translation, may be observed by the page table walker, resulting in a translation fault. For this reason, the final write is followed by a DSB barrier instruction. However, this barrier will not stall the pipeline, and instruction fetches may still hit this invalid translation, as has been observed and reported by Oliver. To ensure that the new translation is fully active before returning from this helper, we have to insert an ISB barrier as well. Reported-by: Oliver Steffen Tested-by: Oliver Steffen Reviewed-by: Leif Lindholm Acked-by: Michael D Kinney Signed-off-by: Ard Biesheuvel --- ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S | 1 + 1 file changed, 1 insertion(+) diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S index 887439bc042..1f0d8057926 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S @@ -65,6 +65,7 @@ // write updated entry str x1, [x0] dsb nshst + isb .L2_\@: .endm