diff --git a/Platform/AMD/TurinBoard/Apcb/ApcbToken.h b/Platform/AMD/TurinBoard/Apcb/ApcbToken.h new file mode 100644 index 0000000000..db0459126d --- /dev/null +++ b/Platform/AMD/TurinBoard/Apcb/ApcbToken.h @@ -0,0 +1,41 @@ +//***************************************************************************** +// +// Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All rights reserved. +// +//***************************************************************************** + +// Add override tokens here + +#ifdef ESPI_UART +#ifdef APCB_TOKEN_UID_FCH_CONSOLE_OUT_SERIAL_PORT_VALUE + #undef APCB_TOKEN_UID_FCH_CONSOLE_OUT_SERIAL_PORT_VALUE +#endif +#define APCB_TOKEN_UID_FCH_CONSOLE_OUT_SERIAL_PORT_VALUE 0 + +#ifdef APCB_TOKEN_UID_FCH_CONSOLE_OUT_SERIAL_PORT_IO_VALUE + #undef APCB_TOKEN_UID_FCH_CONSOLE_OUT_SERIAL_PORT_IO_VALUE +#endif +#define APCB_TOKEN_UID_FCH_CONSOLE_OUT_SERIAL_PORT_IO_VALUE 0 +#endif /// end of ESPI_UART + +#ifdef PCIE_MULTI_SEGMENT + #define APCB_TOKEN_UID_DF_PCI_MMIO_BASE_VALUE 0x0 + #define APCB_TOKEN_UID_DF_PCI_MMIO_HI_BASE_VALUE 0x3FFB +#endif /// end of PCIE_MULTI_SEGMENT + +#ifdef SATA_OVERRIDE + #define APCB_TOKEN_UID_FCH_SATA_0_ENABLE_VALUE 0 + #define APCB_TOKEN_UID_FCH_SATA_1_ENABLE_VALUE 0 + #define APCB_TOKEN_UID_FCH_SATA_2_ENABLE_VALUE 0 + #define APCB_TOKEN_UID_FCH_SATA_3_ENABLE_VALUE 0 + #define APCB_TOKEN_UID_FCH_SATA_4_ENABLE_VALUE 1 + #define APCB_TOKEN_UID_FCH_SATA_5_ENABLE_VALUE 1 + #define APCB_TOKEN_UID_FCH_SATA_6_ENABLE_VALUE 0 + #define APCB_TOKEN_UID_FCH_SATA_7_ENABLE_VALUE 0 +#endif + +#ifdef ROM3_1TB_REMAP + #define APCB_TOKEN_UID_FCH_ROM3_BASE_HIGH_VALUE 0x3FFC +#else + #define APCB_TOKEN_UID_FCH_ROM3_BASE_HIGH_VALUE 0 +#endif diff --git a/Platform/AMD/TurinBoard/Binaries/EarlyVgaProg.bin b/Platform/AMD/TurinBoard/Binaries/EarlyVgaProg.bin new file mode 100644 index 0000000000..27535ee85a Binary files /dev/null and b/Platform/AMD/TurinBoard/Binaries/EarlyVgaProg.bin differ diff --git a/Platform/AMD/TurinBoard/Binaries/earlyVgaProgOnly.bin b/Platform/AMD/TurinBoard/Binaries/earlyVgaProgOnly.bin new file mode 100644 index 0000000000..fbf4b4ef76 Binary files /dev/null and b/Platform/AMD/TurinBoard/Binaries/earlyVgaProgOnly.bin differ diff --git a/Platform/AMD/TurinBoard/Binaries/epyc2_image.bin b/Platform/AMD/TurinBoard/Binaries/epyc2_image.bin new file mode 100644 index 0000000000..20c20491e3 Binary files /dev/null and b/Platform/AMD/TurinBoard/Binaries/epyc2_image.bin differ diff --git a/Platform/AMD/TurinBoard/ChalupaBoardPkg/Include/Dsc/Smbios.dsc b/Platform/AMD/TurinBoard/ChalupaBoardPkg/Include/Dsc/Smbios.dsc new file mode 100644 index 0000000000..f1d4b6e1c5 --- /dev/null +++ b/Platform/AMD/TurinBoard/ChalupaBoardPkg/Include/Dsc/Smbios.dsc @@ -0,0 +1,204 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All rights reserved. +#; +#;****************************************************************************** +# +## @file +# Smbios Platform description. +# +## + +[PcdsFixedAtBuild] + #**************************************************************************** + # COMMON SMBIOS + #**************************************************************************** + # + # IPMI Interface Type + # + # 0 - Unknown + # 1 - KCS + # 2 - SMIC + # 3 - BT + # 4 - SSIF + gAmdPlatformPkgTokenSpaceGuid.PcdIpmiInterfaceType|1 + + # SMBIOS Type 4 Processor Information + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSerialNumberSocket0|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosAssetTagSocket0|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosPartNumberSocket0|"To be filled by O.E.M." + + # AMD SMBIOS Type 8 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8Number|10 + + # AMD SMBIOS Type 9 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics1.Provides33Volts|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics2.BifurcationSupported|1 + + # Port #0 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.IntDesiganatorStr|"J11" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.ExtDesiganatorStr|"USB3-R" + + # Port #1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.IntDesiganatorStr|"J20" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.ExtDesiganatorStr|"USB3-R" + + # Port #2 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].DesinatorStr.IntDesiganatorStr|"J1F" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].DesinatorStr.ExtDesiganatorStr|"USB3-F" + + # Port #3 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].DesinatorStr.IntDesiganatorStr|"J2F" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].DesinatorStr.ExtDesiganatorStr|"USB3-F" + + # Port #4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalConnectorType|PortConnectorTypeDB15Female + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.PortType|PortTypeVideoPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.IntDesiganatorStr|"J2" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.ExtDesiganatorStr|"VGA-R" + + # Port #5 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalConnectorType|PortConnectorTypeDB15Female + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.PortType|PortTypeVideoPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.IntDesiganatorStr|"J3-F" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.ExtDesiganatorStr|"VGA-F" + + # Port #6 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.ExternalConnectorType|PortConnectorTypeDB9Female + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.PortType|PortTypeSerial16550ACompatible + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].DesinatorStr.IntDesiganatorStr|"J1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].DesinatorStr.ExtDesiganatorStr|"Serial Port Header" + + # Port #7 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.ExternalConnectorType|PortConnectorTypeRJ45 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.PortType|PortTypeNetworkPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].DesinatorStr.IntDesiganatorStr|"J15" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].DesinatorStr.ExtDesiganatorStr|"MGMT RJ45 Port" + + # Port #8 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.InternalConnectorType|PortConnectorTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.PortType|PortTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].DesinatorStr.IntDesiganatorStr|"J75 M2_0" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].DesinatorStr.ExtDesiganatorStr|{0} + + # Port #9 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.InternalConnectorType|PortConnectorTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.PortType|PortTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].DesinatorStr.IntDesiganatorStr|"J77 M2_1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].DesinatorStr.ExtDesiganatorStr|{0} + + # AMD SMBIOS Type 41 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41Number|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].ReferenceDesignation|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceType|OnBoardDeviceExtendedTypeEthernet + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceEnabled|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceTypeInstance|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].VendorId|0x14E4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceId|0x165F + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].RefDesignationStr|"Onboard Ethernet" + +[PcdsDynamicDefault] + #**************************************************************************** + # BASIC SMBIOS + #**************************************************************************** + # + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0305 + # SMBIOS Type 0 BIOS Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosReleaseDate|"$(RELEASE_DATE)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosVersion|"$(FIRMWARE_VERSION_STR)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Size|32 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Unit|0x00 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PlugAndPlayIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.EDDSpecificationIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy525_12IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_720IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_288IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrintScreenIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Keyboard8042IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.SerialIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrinterIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.CgaMonoIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[0]|0x01 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[1]|0x0C + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringVendor|"AMD Corporation" + + # SMBIOS Type 1 System Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringFamily|$(AMD_PROCESSOR) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1SystemInformation.Uuid|{GUID("069F7A75-1155-455F-81E9-2D778481D7EF")} + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringSerialNumber|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringVersion|"To be filled by O.E.M." + + # SMBIOS Type 2 Baseboard Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringVersion|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringAssetTag|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringLocationInChassis|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringSerialNumber|"To be filled by O.E.M." + + # SMBIOS Type 3 System Enclosure Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringVersion|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringAssetTag|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSKUNumber|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSerialNumber|"To be filled by O.E.M." + + # SMBIOS Type 11 OEM Strings + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStringsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStrings|{"To be filled by O.E.M."} + + # SMBIOS Type 12 System Configuration Options + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptionsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptions|{"To be filled by O.E.M."} + +[Components.X64] + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + SystemInformation/SmbiosFeaturePkg/SmbiosBasicDxe/SmbiosBasicDxe.inf + AmdPlatformPkg/Universal/SmbiosCommonDxe/SmbiosCommonDxe.inf { + + PciSegmentLib|MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.inf + PciSegmentInfoLib|AgesaPkg/Addendum/PciSegments/PciExpressPciSegmentInfoLib/PciExpressPciSegmentInfoLib.inf + } diff --git a/Platform/AMD/TurinBoard/ChalupaBoardPkg/Project.dsc b/Platform/AMD/TurinBoard/ChalupaBoardPkg/Project.dsc new file mode 100644 index 0000000000..550941fd66 --- /dev/null +++ b/Platform/AMD/TurinBoard/ChalupaBoardPkg/Project.dsc @@ -0,0 +1,200 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All rights reserved. +#; +#;****************************************************************************** + +# ***************************************************************************** +# Defines passed into build +# RELEASE_DATE +# FIRMWARE_REVISION_NUM +# FIRMWARE_VERSION_STR +# PLATFORM_CRB +# AMD_PROCESSOR +# CBS_INCLUDE +# INTERNAL_IDS +# SIMNOW_SUPPORT +# EMULATION +# ***************************************************************************** + +[Defines] +!ifndef AMD_PROCESSOR + AMD_PROCESSOR = Turin +!endif + PROCESSOR_PATH = $(AMD_PROCESSOR)Board +!ifndef PLATFORM_CRB + PLATFORM_CRB = Chalupa +!endif + PLATFORM_NAME = $(PLATFORM_CRB)BoardPkg + PLATFORM_GUID = 481A9339-68CD-4EBF-A656-857B3B9FE89B + PLATFORM_VERSION = 0.01 + DSC_SPECIFICATION = 1.30 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)_$(AMD_PROCESSOR) +!ifdef $(INTERNAL_IDS) + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_INTERNAL +!else + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_EXTERNAL +!endif + SUPPORTED_ARCHITECTURES = IA32|X64 + BUILD_TARGETS = DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = $(PLATFORM_NAME)/Project.fdf + + DEFINE PEI_ARCH = IA32 + DEFINE DXE_ARCH = X64 + PREBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py prebuild" + POSTBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py postbuild" + + # + # Platform On/Off features are defined here + # + DEFINE SOURCE_DEBUG_ENABLE = FALSE + DEFINE DEBUG_DISPATCH_ENABLE = FALSE + DEFINE DISABLE_SMT = FALSE + + # AGESA Defines to skip Cf9Reset Driver + DEFINE AMD_RESET_DXE_DRIVER_SUPPORT_DISABLED = TRUE + + DEFINE PLATFORM_CRB_TABLE_ID = "CHALUPA " + + DEFINE SATA_OVERRIDE = FALSE + + !ifdef $(INTERNAL_IDS) + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = FALSE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = TRUE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE + !else + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = FALSE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = FALSE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE + !endif + + # Predefined Fabric Resource + DEFINE PREDEFINED_FABRIC_RESOURCES = TRUE + # use emulated variable store instead of real spirom + # use this flag for early brigup when there is issue + # with accessing the spirom + DEFINE USE_EMULATED_VARIABLE_STORE = $(EMULATION) + + # Multisegment support + DEFINE PCIE_MULTI_SEGMENT = TRUE + + # EDK2 components are starting to use PLATFORMX64_ENABLE in their include + # DSC/FDF files + DEFINE PLATFORMX64_ENABLE = TRUE + + # MACRO used by AGESA FCH include DSC/FDF to exclude legacy CSM support + DEFINE AMD_CSM_SUPPORT_DISABLED = TRUE + + DEFINE ROM3_1TB_REMAP = FALSE + + !ifndef SOC_FAMILY_2 + DEFINE SOC_FAMILY_2 = $(SOC_FAMILY) + !endif + !ifndef SOC_SKU_2 + DEFINE SOC_SKU_2 = $(SOC_SKU) + !endif + !ifndef SOC2_2 + DEFINE SOC2_2 = $(SOC2) + !endif + !ifndef SOC_SKU_TITLE + DEFINE SOC_SKU_TITLE = Brh + !endif + + # Console settings + # + # Background info: + # As per Turin PPR vol7 17.4.10 UART Registers + # There are 3 physical UARTS available for SBIOS. + # UART0 supports flow controls. + # UART1 doest support flow controls. + # UART2 is disabled by AGESA/CPM to enable flow control for UART0. + # Hence only two UARTs (UART0 and UART1) are available for SBIOS. + # MMIO addresses for 4 UART as FEDCF000,FEDCE000,FEDCA000 and FEDC9000 + # + # Platform settings: + # AGESA/CPM enables UART0 and UART1 by setting BIT11 and BIT12 of FchRTDeviceEnableMap. + # If SBIOS wants to use MMIO space then above mentioned reserved MMIO can be used. + # If SBIOS wants UART in legacy mode(to use 0x3F8/0x2F8) then need to set below PCD for + # for respective UART. + # FchUart0LegacyEnable, FchUart1LegacyEnable and FchUart2LegacyEnable + # + # SERIAL_PORT Options: + # NONE + # FCH_MMIO UART0, MMIO + # FCH_IO UART0, 0x3F8 + # BMC_SOL UART1, MMIO + # BMC_SOL_IO UART1, 0x3F8 + # BMC_ESPI eSPI0, 0x3F8 + DEFINE SERIAL_PORT = "BMC_SOL_IO" + DEFINE ESPI_UART = FALSE # Define ESPI_UART to modify APCB tokens + + # + # Simnow Options + # + DEFINE SIMNOW_PORT80_DEBUG = $(EMULATION) + DEFINE USB_SUPPORT = TRUE + DEFINE SATA_SUPPORT = TRUE + DEFINE NVME_SUPPORT = TRUE + + # + # Check undefined variables + # +!ifndef RELEASE_DATE + RELEASE_DATE = 01/01/2023 +!endif +!ifndef FIRMWARE_VERSION_STR + FIRMWARE_VERSION_STR = NONE +!endif +!ifndef FIRMWARE_REVISION_NUM + FIRMWARE_REVISION_NUM = 0x00000000 +!endif + +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +# Add platform includes AGESA, CPM etc +!include $(PROCESSOR_PATH)/Include/Dsc/Platform.inc.dsc + +# Board specific SMBIOS defines +!include $(PLATFORM_NAME)/Include/Dsc/Smbios.dsc + +# Platform Common PCDs +!include $(PROCESSOR_PATH)/Include/Dsc/PlatformCommonPcd.dsc.inc + +# Board specific PCDs +[PcdsFixedAtBuild] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSocketDesignationSocket0|"P0" + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSocketDesignationSocket1|"P1" + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x204150554C414843 # "CHALUPA " + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|768 + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|2 + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|768 + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicCount|16 + +[PcdsDynamicDefault] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdEarlyBmcLinkLaneNum|134 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdCfgPlatformPPT|500 + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0xFFFF + +[PcdsFeatureFlag] + !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 5 + !if $(SIMNOW_SUPPORT) == FALSE || $(EMULATION) == FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|TRUE + !endif + !endif + +####################################### +# Library Includes +####################################### +!include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc +!include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc +!include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc +# do not change the order of include +!include $(PROCESSOR_PATH)/Include/Dsc/ProjectCommon.inc.dsc diff --git a/Platform/AMD/TurinBoard/ChalupaBoardPkg/Project.fdf b/Platform/AMD/TurinBoard/ChalupaBoardPkg/Project.fdf new file mode 100644 index 0000000000..dce6a7e5f6 --- /dev/null +++ b/Platform/AMD/TurinBoard/ChalupaBoardPkg/Project.fdf @@ -0,0 +1,36 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All rights reserved. +#; +#;***************************************************************************** + + +############################################################################## +# +# Turin reference board - 2 SPI FLash devices accessible by x86 (selected by DIP-switch): +# 1) 32MB Flash with 10-pin header next to the VGA connector. +# 2) 64MB Flash with 10-pin header at 90-degrees from VGA connector, and also accessible by the BMC. +# +############################################################################## + +[Defines] + # Platform.inc.fdf can contain custom DEFINES, consumed by FlashmMapInclude.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/Platform.inc.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/FlashMapInclude.fdf + + DEFINE EFS_ESPI_BYTE0 = 0x0E + DEFINE EFS_ESPI_BYTE1 = 0xFF +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +!include $(PROCESSOR_PATH)/Include/Fdf/ProjectCommon.inc.fdf + +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ +!include MinPlatformPkg/Include/Fdf/RuleInclude.fdf diff --git a/Platform/AMD/TurinBoard/EmulationBoardPkg/Include/Dsc/Smbios.dsc b/Platform/AMD/TurinBoard/EmulationBoardPkg/Include/Dsc/Smbios.dsc new file mode 100644 index 0000000000..83796fd26a --- /dev/null +++ b/Platform/AMD/TurinBoard/EmulationBoardPkg/Include/Dsc/Smbios.dsc @@ -0,0 +1,202 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All rights reserved. +#; +#;****************************************************************************** +# +## @file +# Smbios Platform description. +# +## + +[PcdsFixedAtBuild] + #**************************************************************************** + # COMMON SMBIOS + #**************************************************************************** + # + # IPMI Interface Type + # + # 0 - Unknown + # 1 - KCS + # 2 - SMIC + # 3 - BT + # 4 - SSIF + gAmdPlatformPkgTokenSpaceGuid.PcdIpmiInterfaceType|1 + + # SMBIOS Type 4 Processor Information + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSerialNumberSocket0|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosAssetTagSocket0|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosPartNumberSocket0|"To be filled by O.E.M." + +# AMD SMBIOS Type 8 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8Number|10 + + # AMD SMBIOS Type 9 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics1.Provides33Volts|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics2.BifurcationSupported|1 + + # Port #0 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.IntDesiganatorStr|"J11" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.ExtDesiganatorStr|"USB3-R" + + # Port #1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.IntDesiganatorStr|"J20" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.ExtDesiganatorStr|"USB3-R" + + # Port #2 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].DesinatorStr.IntDesiganatorStr|"J1F" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].DesinatorStr.ExtDesiganatorStr|"USB3-F" + + # Port #3 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].DesinatorStr.IntDesiganatorStr|"J2F" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].DesinatorStr.ExtDesiganatorStr|"USB3-F" + + # Port #4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalConnectorType|PortConnectorTypeDB15Female + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.PortType|PortTypeVideoPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.IntDesiganatorStr|"J2" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.ExtDesiganatorStr|"VGA-R" + + # Port #5 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalConnectorType|PortConnectorTypeDB15Female + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.PortType|PortTypeVideoPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.IntDesiganatorStr|"J3-F" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.ExtDesiganatorStr|"VGA-F" + + # Port #6 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.ExternalConnectorType|PortConnectorTypeDB9Female + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.PortType|PortTypeSerial16550ACompatible + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].DesinatorStr.IntDesiganatorStr|"J1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].DesinatorStr.ExtDesiganatorStr|"Serial Port Header" + + # Port #7 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.ExternalConnectorType|PortConnectorTypeRJ45 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.PortType|PortTypeNetworkPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].DesinatorStr.IntDesiganatorStr|"J15" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].DesinatorStr.ExtDesiganatorStr|"MGMT RJ45 Port" + + # Port #8 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.InternalConnectorType|PortConnectorTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.PortType|PortTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].DesinatorStr.IntDesiganatorStr|"J75 M2_0" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].DesinatorStr.ExtDesiganatorStr|{0} + + # Port #9 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.InternalConnectorType|PortConnectorTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.PortType|PortTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].DesinatorStr.IntDesiganatorStr|"J77 M2_1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].DesinatorStr.ExtDesiganatorStr|{0} + + # AMD SMBIOS Type 41 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41Number|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].ReferenceDesignation|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceType|OnBoardDeviceExtendedTypeEthernet + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceEnabled|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceTypeInstance|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].VendorId|0x14E4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceId|0x165F + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].RefDesignationStr|"Onboard Ethernet" + +[PcdsDynamicDefault] + #**************************************************************************** + # BASIC SMBIOS + #**************************************************************************** + # + # SMBIOS Type 0 BIOS Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosReleaseDate|"$(RELEASE_DATE)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosVersion|"$(FIRMWARE_VERSION_STR)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Size|32 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Unit|0x00 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PlugAndPlayIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.EDDSpecificationIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy525_12IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_720IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_288IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrintScreenIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Keyboard8042IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.SerialIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrinterIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.CgaMonoIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[0]|0x01 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[1]|0x0C + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringVendor|"AMD Corporation" + + # SMBIOS Type 1 System Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringFamily|$(AMD_PROCESSOR) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1SystemInformation.Uuid|{GUID("069F7A75-1155-455F-81E9-2D778481D7EF")} + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringSerialNumber|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringVersion|"To be filled by O.E.M." + + # SMBIOS Type 2 Baseboard Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringVersion|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringAssetTag|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringLocationInChassis|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringSerialNumber|"To be filled by O.E.M." + + # SMBIOS Type 3 System Enclosure Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringVersion|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringAssetTag|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSKUNumber|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSerialNumber|"To be filled by O.E.M." + + # SMBIOS Type 11 OEM Strings + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStringsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStrings|{"To be filled by O.E.M."} + + # SMBIOS Type 12 System Configuration Options + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptionsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptions|{"To be filled by O.E.M."} + +[Components.X64] + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + SystemInformation/SmbiosFeaturePkg/SmbiosBasicDxe/SmbiosBasicDxe.inf + AmdPlatformPkg/Universal/SmbiosCommonDxe/SmbiosCommonDxe.inf { + + PciSegmentLib|MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.inf + PciSegmentInfoLib|AgesaPkg/Addendum/PciSegments/PciExpressPciSegmentInfoLib/PciExpressPciSegmentInfoLib.inf + } diff --git a/Platform/AMD/TurinBoard/EmulationBoardPkg/Project.dsc b/Platform/AMD/TurinBoard/EmulationBoardPkg/Project.dsc new file mode 100644 index 0000000000..6aad0bf167 --- /dev/null +++ b/Platform/AMD/TurinBoard/EmulationBoardPkg/Project.dsc @@ -0,0 +1,199 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All rights reserved. +#; +#;****************************************************************************** + +# ***************************************************************************** +# Defines passed into build +# RELEASE_DATE +# FIRMWARE_REVISION_NUM +# FIRMWARE_VERSION_STR +# PLATFORM_CRB +# AMD_PROCESSOR +# CBS_INCLUDE +# INTERNAL_IDS +# SIMNOW_SUPPORT +# EMULATION +# ***************************************************************************** + +[Defines] +!ifndef AMD_PROCESSOR + AMD_PROCESSOR = Turin +!endif + PROCESSOR_PATH = $(AMD_PROCESSOR)Board +!ifndef PLATFORM_CRB + # emulation is based on Chalupa including all PCDs and reference settings + PLATFORM_CRB = Chalupa +!endif + PLATFORM_NAME = EmulationBoardPkg + PLATFORM_GUID = C305E1F5-98FA-447D-846F-0863BBE8796A + PLATFORM_VERSION = 0.01 + DSC_SPECIFICATION = 1.30 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)_$(AMD_PROCESSOR) +!ifdef $(INTERNAL_IDS) + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_INTERNAL +!else + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_EXTERNAL +!endif + SUPPORTED_ARCHITECTURES = IA32|X64 + BUILD_TARGETS = DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = $(PLATFORM_NAME)/Project.fdf + + DEFINE PEI_ARCH = IA32 + DEFINE DXE_ARCH = X64 + PREBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py prebuild" + POSTBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py postbuild" + + # + # Platform On/Off features are defined here + # + DEFINE SOURCE_DEBUG_ENABLE = FALSE + DEFINE DEBUG_DISPATCH_ENABLE = FALSE + DEFINE DISABLE_SMT = FALSE + + # AGESA Defines to skip Cf9Reset Driver + DEFINE AMD_RESET_DXE_DRIVER_SUPPORT_DISABLED = TRUE + + DEFINE PLATFORM_CRB_TABLE_ID = "EMULATE " + + DEFINE SATA_OVERRIDE = FALSE + + !ifdef $(INTERNAL_IDS) + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = FALSE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = TRUE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE + !else + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = FALSE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = FALSE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE + !endif + + # Predefined Fabric Resource + DEFINE PREDEFINED_FABRIC_RESOURCES = TRUE + # use emulated variable store instead of real spirom + # use this flag for early brigup when there is issue + # with accessing the spirom + DEFINE USE_EMULATED_VARIABLE_STORE = $(EMULATION) + + # Multisegment support + DEFINE PCIE_MULTI_SEGMENT = TRUE + + # EDK2 components are starting to use PLATFORMX64_ENABLE in their include + # DSC/FDF files + DEFINE PLATFORMX64_ENABLE = TRUE + + # MACRO used by AGESA FCH include DSC/FDF to exclude legacy CSM support + DEFINE AMD_CSM_SUPPORT_DISABLED = TRUE + + # DRAM boot for emulation, set this flag to TRUE for pure Emulation environment + DEFINE DRAM_BOOT = TRUE + + DEFINE ROM3_1TB_REMAP = FALSE + + !ifndef SOC_FAMILY_2 + DEFINE SOC_FAMILY_2 = $(SOC_FAMILY) + !endif + !ifndef SOC_SKU_2 + DEFINE SOC_SKU_2 = $(SOC_SKU) + !endif + !ifndef SOC2_2 + DEFINE SOC2_2 = $(SOC2) + !endif + !ifndef SOC_SKU_TITLE + DEFINE SOC_SKU_TITLE = Brh + !endif + + # Console settings + # + # Background info: + # As per Turin PPR vol7 17.4.10 UART Registers + # There are 3 physical UARTS available for SBIOS. + # UART0 supports flow controls. + # UART1 doest support flow controls. + # UART2 is disabled by AGESA/CPM to enable flow control for UART0. + # Hence only two UARTs (UART0 and UART1) are available for SBIOS. + # MMIO addresses for 4 UART as FEDCF000,FEDCE000,FEDCA000 and FEDC9000 + # + # Platform settings: + # AGESA/CPM enables UART0 and UART1 by setting BIT11 and BIT12 of FchRTDeviceEnableMap. + # If SBIOS wants to use MMIO space then above mentioned reserved MMIO can be used. + # If SBIOS wants UART in legacy mode(to use 0x3F8/0x2F8) then need to set below PCD for + # for respective UART. + # FchUart0LegacyEnable, FchUart1LegacyEnable and FchUart2LegacyEnable + # + # SERIAL_PORT Options: + # NONE + # FCH_MMIO UART0, MMIO + # FCH_IO UART0, 0x3F8 + # BMC_SOL UART1, MMIO + # BMC_SOL_IO UART1, 0x3F8 + # BMC_ESPI eSPI0, 0x3F8 + DEFINE SERIAL_PORT = "BMC_SOL_IO" + DEFINE ESPI_UART = FALSE # Define ESPI_UART to modify APCB tokens + + # + # Simnow Options + # + DEFINE SIMNOW_PORT80_DEBUG = $(EMULATION) + DEFINE USB_SUPPORT = TRUE + DEFINE SATA_SUPPORT = TRUE + DEFINE NVME_SUPPORT = TRUE + + # + # Check undefined variables + # +!ifndef RELEASE_DATE + RELEASE_DATE = 01/01/2023 +!endif +!ifndef FIRMWARE_VERSION_STR + FIRMWARE_VERSION_STR = NONE +!endif +!ifndef FIRMWARE_REVISION_NUM + FIRMWARE_REVISION_NUM = 0x00000000 +!endif + +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +# Add platform includes AGESA, CPM etc +!include $(PROCESSOR_PATH)/Include/Dsc/Platform.inc.dsc + +# Board specific SMBIOS defines +!include $(PLATFORM_NAME)/Include/Dsc/Smbios.dsc + +# Platform Common PCDs +!include $(PROCESSOR_PATH)/Include/Dsc/PlatformCommonPcd.dsc.inc + +# Board specific PCDs +[PcdsFixedAtBuild] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSocketDesignationSocket0|"P0" + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSocketDesignationSocket1|"P1" + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x204151554C414843 # "CHALUPA " + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|768 + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|2 + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|768 + +[PcdsDynamicDefault] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdEarlyBmcLinkLaneNum|134 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdTransparentErrorLoggingEnable|TRUE + !if $(USB_SUPPORT) + ### USB 3.0 controller0 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdXhci0Enable|FALSE + !endif + +####################################### +# Library Includes +####################################### +!include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc +!include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc +!include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc +# do not change the order of include +!include $(PROCESSOR_PATH)/Include/Dsc/ProjectCommon.inc.dsc diff --git a/Platform/AMD/TurinBoard/EmulationBoardPkg/Project.fdf b/Platform/AMD/TurinBoard/EmulationBoardPkg/Project.fdf new file mode 100644 index 0000000000..45a03af344 --- /dev/null +++ b/Platform/AMD/TurinBoard/EmulationBoardPkg/Project.fdf @@ -0,0 +1,46 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All rights reserved. +#; +#;***************************************************************************** + + +############################################################################## +# +# Turin reference board - 2 SPI FLash devices accessible by x86 (selected by DIP-switch): +# 1) 32MB Flash with 10-pin header next to the VGA connector. +# 2) 64MB Flash with 10-pin header at 90-degrees from VGA connector, and also accessible by the BMC. +# +############################################################################## + +[Defines] + # Platform.inc.fdf can contain custom DEFINES, consumed by FlashmMapInclude.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/Platform.inc.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/FlashMapInclude.fdf + + DEFINE EFS_ESPI_BYTE0 = 0x0E + DEFINE EFS_ESPI_BYTE1 = 0xFF + + # Emulation BIOS can only be 16MB in size + DEFINE BUILD_16MB_IMAGE = TRUE + + !if $(BUILD_16MB_IMAGE) == TRUE + DEFINE SPI_NUM_BLOCKS = 0x1000 + !else + DEFINE SPI_NUM_BLOCKS = 0x2000 + !endif + +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +!include $(PROCESSOR_PATH)/Include/Fdf/ProjectCommon.inc.fdf + +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ +!include MinPlatformPkg/Include/Fdf/RuleInclude.fdf diff --git a/Platform/AMD/TurinBoard/GalenaBoardPkg/Include/Dsc/Smbios.dsc b/Platform/AMD/TurinBoard/GalenaBoardPkg/Include/Dsc/Smbios.dsc new file mode 100644 index 0000000000..a0383d25f0 --- /dev/null +++ b/Platform/AMD/TurinBoard/GalenaBoardPkg/Include/Dsc/Smbios.dsc @@ -0,0 +1,204 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All rights reserved. +#; +#;****************************************************************************** +# +## @file +# Smbios Platform description. +# +## + +[PcdsFixedAtBuild] + #**************************************************************************** + # COMMON SMBIOS + #**************************************************************************** + # + # IPMI Interface Type + # + # 0 - Unknown + # 1 - KCS + # 2 - SMIC + # 3 - BT + # 4 - SSIF + gAmdPlatformPkgTokenSpaceGuid.PcdIpmiInterfaceType|1 + + # SMBIOS Type 4 Processor Information + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSerialNumberSocket0|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosAssetTagSocket0|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosPartNumberSocket0|"To be filled by O.E.M." + +# AMD SMBIOS Type 8 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8Number|10 + + # AMD SMBIOS Type 9 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics1.Provides33Volts|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics2.BifurcationSupported|1 + + # Port #0 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.IntDesiganatorStr|"J11" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.ExtDesiganatorStr|"USB3-R" + + # Port #1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.IntDesiganatorStr|"J20" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.ExtDesiganatorStr|"USB3-R" + + # Port #2 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].DesinatorStr.IntDesiganatorStr|"J1F" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].DesinatorStr.ExtDesiganatorStr|"USB3-F" + + # Port #3 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].DesinatorStr.IntDesiganatorStr|"J2F" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].DesinatorStr.ExtDesiganatorStr|"USB3-F" + + # Port #4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalConnectorType|PortConnectorTypeDB15Female + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.PortType|PortTypeVideoPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.IntDesiganatorStr|"J2" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.ExtDesiganatorStr|"VGA-R" + + # Port #5 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalConnectorType|PortConnectorTypeDB15Female + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.PortType|PortTypeVideoPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.IntDesiganatorStr|"J3-F" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.ExtDesiganatorStr|"VGA-F" + + # Port #6 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.ExternalConnectorType|PortConnectorTypeDB9Female + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.PortType|PortTypeSerial16550ACompatible + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].DesinatorStr.IntDesiganatorStr|"J1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].DesinatorStr.ExtDesiganatorStr|"Serial Port Header" + + # Port #7 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.ExternalConnectorType|PortConnectorTypeRJ45 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.PortType|PortTypeNetworkPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].DesinatorStr.IntDesiganatorStr|"J15" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].DesinatorStr.ExtDesiganatorStr|"MGMT RJ45 Port" + + # Port #8 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.InternalConnectorType|PortConnectorTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.PortType|PortTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].DesinatorStr.IntDesiganatorStr|"J75 M2_0" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].DesinatorStr.ExtDesiganatorStr|{0} + + # Port #9 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.InternalConnectorType|PortConnectorTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.PortType|PortTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].DesinatorStr.IntDesiganatorStr|"J77 M2_1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].DesinatorStr.ExtDesiganatorStr|{0} + + # AMD SMBIOS Type 41 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41Number|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].ReferenceDesignation|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceType|OnBoardDeviceExtendedTypeEthernet + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceEnabled|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceTypeInstance|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].VendorId|0x14E4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceId|0x165F + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].RefDesignationStr|"Onboard Ethernet" + +[PcdsDynamicDefault] + #**************************************************************************** + # BASIC SMBIOS + #**************************************************************************** + # + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0305 + # SMBIOS Type 0 BIOS Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosReleaseDate|"$(RELEASE_DATE)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosVersion|"$(FIRMWARE_VERSION_STR)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Size|32 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Unit|0x00 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PlugAndPlayIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.EDDSpecificationIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy525_12IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_720IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_288IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrintScreenIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Keyboard8042IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.SerialIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrinterIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.CgaMonoIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[0]|0x01 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[1]|0x0C + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringVendor|"AMD Corporation" + + # SMBIOS Type 1 System Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringFamily|$(AMD_PROCESSOR) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1SystemInformation.Uuid|{GUID("3E35E28F-C98B-481B-BA7C-97C712982509")} + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringSerialNumber|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringVersion|"To be filled by O.E.M." + + # SMBIOS Type 2 Baseboard Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringVersion|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringAssetTag|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringLocationInChassis|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringSerialNumber|"To be filled by O.E.M." + + # SMBIOS Type 3 System Enclosure Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringVersion|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringAssetTag|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSKUNumber|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSerialNumber|"To be filled by O.E.M." + + # SMBIOS Type 11 OEM Strings + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStringsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStrings|{"To be filled by O.E.M."} + + # SMBIOS Type 12 System Configuration Options + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptionsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptions|{"To be filled by O.E.M."} + +[Components.X64] + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + SystemInformation/SmbiosFeaturePkg/SmbiosBasicDxe/SmbiosBasicDxe.inf + AmdPlatformPkg/Universal/SmbiosCommonDxe/SmbiosCommonDxe.inf { + + PciSegmentLib|MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.inf + PciSegmentInfoLib|AgesaPkg/Addendum/PciSegments/PciExpressPciSegmentInfoLib/PciExpressPciSegmentInfoLib.inf + } diff --git a/Platform/AMD/TurinBoard/GalenaBoardPkg/Project.dsc b/Platform/AMD/TurinBoard/GalenaBoardPkg/Project.dsc new file mode 100644 index 0000000000..89a403767a --- /dev/null +++ b/Platform/AMD/TurinBoard/GalenaBoardPkg/Project.dsc @@ -0,0 +1,200 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All rights reserved. +#; +#;****************************************************************************** + +# ***************************************************************************** +# Defines passed into build +# RELEASE_DATE +# FIRMWARE_REVISION_NUM +# FIRMWARE_VERSION_STR +# PLATFORM_CRB +# AMD_PROCESSOR +# CBS_INCLUDE +# INTERNAL_IDS +# SIMNOW_SUPPORT +# EMULATION +# ***************************************************************************** + +[Defines] +!ifndef AMD_PROCESSOR + AMD_PROCESSOR = Turin +!endif + PROCESSOR_PATH = $(AMD_PROCESSOR)Board +!ifndef PLATFORM_CRB + PLATFORM_CRB = Galena +!endif + PLATFORM_NAME = $(PLATFORM_CRB)BoardPkg + PLATFORM_GUID = C3851035-490E-485E-8941-DFFDBDB45F69 + PLATFORM_VERSION = 0.01 + DSC_SPECIFICATION = 1.30 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)_$(AMD_PROCESSOR) +!ifdef $(INTERNAL_IDS) + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_INTERNAL +!else + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_EXTERNAL +!endif + SUPPORTED_ARCHITECTURES = IA32|X64 + BUILD_TARGETS = DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = $(PLATFORM_NAME)/Project.fdf + + DEFINE PEI_ARCH = IA32 + DEFINE DXE_ARCH = X64 + PREBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py prebuild" + POSTBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py postbuild" + + # + # Platform On/Off features are defined here + # + DEFINE SOURCE_DEBUG_ENABLE = FALSE + DEFINE DEBUG_DISPATCH_ENABLE = FALSE + DEFINE DISABLE_SMT = FALSE + + # AGESA Defines to skip Cf9Reset Driver + DEFINE AMD_RESET_DXE_DRIVER_SUPPORT_DISABLED = TRUE + + DEFINE PLATFORM_CRB_TABLE_ID = "GALENA " + + DEFINE SATA_OVERRIDE = FALSE + + !ifdef $(INTERNAL_IDS) + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = FALSE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = TRUE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE + !else + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = FALSE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = FALSE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE + !endif + + # Predefined Fabric Resource + DEFINE PREDEFINED_FABRIC_RESOURCES = TRUE + # use emulated variable store instead of real spirom + # use this flag for early brigup when there is issue + # with accessing the spirom + DEFINE USE_EMULATED_VARIABLE_STORE = $(EMULATION) + + # Multisegment support + DEFINE PCIE_MULTI_SEGMENT = TRUE + + # EDK2 components are starting to use PLATFORMX64_ENABLE in their include + # DSC/FDF files + DEFINE PLATFORMX64_ENABLE = TRUE + + # MACRO used by AGESA FCH include DSC/FDF to exclude legacy CSM support + DEFINE AMD_CSM_SUPPORT_DISABLED = TRUE + + DEFINE ROM3_1TB_REMAP = FALSE + + !ifndef SOC_FAMILY_2 + DEFINE SOC_FAMILY_2 = $(SOC_FAMILY) + !endif + !ifndef SOC_SKU_2 + DEFINE SOC_SKU_2 = $(SOC_SKU) + !endif + !ifndef SOC2_2 + DEFINE SOC2_2 = $(SOC2) + !endif + !ifndef SOC_SKU_TITLE + DEFINE SOC_SKU_TITLE = Brh + !endif + + # Console settings + # + # Background info: + # As per Turin PPR vol7 17.4.10 UART Registers + # There are 3 physical UARTS available for SBIOS. + # UART0 supports flow controls. + # UART1 doest support flow controls. + # UART2 is disabled by AGESA/CPM to enable flow control for UART0. + # Hence only two UARTs (UART0 and UART1) are available for SBIOS. + # MMIO addresses for 4 UART as FEDCF000,FEDCE000,FEDCA000 and FEDC9000 + # + # Platform settings: + # AGESA/CPM enables UART0 and UART1 by setting BIT11 and BIT12 of FchRTDeviceEnableMap. + # If SBIOS wants to use MMIO space then above mentioned reserved MMIO can be used. + # If SBIOS wants UART in legacy mode(to use 0x3F8/0x2F8) then need to set below PCD for + # for respective UART. + # FchUart0LegacyEnable, FchUart1LegacyEnable and FchUart2LegacyEnable + # + # SERIAL_PORT Options: + # NONE + # FCH_MMIO UART0, MMIO + # FCH_IO UART0, 0x3F8 + # BMC_SOL UART1, MMIO + # BMC_SOL_IO UART1, 0x3F8 + # BMC_ESPI eSPI0, 0x3F8 + DEFINE SERIAL_PORT = "BMC_SOL_IO" + DEFINE ESPI_UART = FALSE # Define ESPI_UART to modify APCB tokens + + # + # Simnow Options + # + DEFINE SIMNOW_PORT80_DEBUG = $(EMULATION) + DEFINE USB_SUPPORT = TRUE + DEFINE SATA_SUPPORT = TRUE + DEFINE NVME_SUPPORT = TRUE + + # + # Check undefined variables + # +!ifndef RELEASE_DATE + RELEASE_DATE = 01/01/2023 +!endif +!ifndef FIRMWARE_VERSION_STR + FIRMWARE_VERSION_STR = NONE +!endif +!ifndef FIRMWARE_REVISION_NUM + FIRMWARE_REVISION_NUM = 0x00000000 +!endif + +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +# Add platform includes AGESA, CPM etc +!include $(PROCESSOR_PATH)/Include/Dsc/Platform.inc.dsc + +# Board specific SMBIOS defines +!include $(PLATFORM_NAME)/Include/Dsc/Smbios.dsc + +# Platform Common PCDs +!include $(PROCESSOR_PATH)/Include/Dsc/PlatformCommonPcd.dsc.inc + +# Board specific PCDs +[PcdsFixedAtBuild] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSocketDesignationSocket0|"P0" + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x2020414E454C4147 # "GALENA " + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|384 + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1 + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|384 + +[PcdsDynamicDefault] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdEarlyBmcLinkLaneNum|134 + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdXhciOcPolarityCfgLow|TRUE + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdXhciUsb31OcPinSelect|0xFFFF1010 + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdXhciUsb20OcPinSelect|0xFFFFFFFFFFFF1010 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdCfgPlatformPPT|500 + +[PcdsFeatureFlag] + !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 5 + !if $(SIMNOW_SUPPORT) == FALSE || $(EMULATION) == FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|TRUE + !endif + !endif + +####################################### +# Library Includes +####################################### +!include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc +!include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc +!include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc +# do not change the order of include +!include $(PROCESSOR_PATH)/Include/Dsc/ProjectCommon.inc.dsc diff --git a/Platform/AMD/TurinBoard/GalenaBoardPkg/Project.fdf b/Platform/AMD/TurinBoard/GalenaBoardPkg/Project.fdf new file mode 100644 index 0000000000..d3c90f27ec --- /dev/null +++ b/Platform/AMD/TurinBoard/GalenaBoardPkg/Project.fdf @@ -0,0 +1,36 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All rights reserved. +#; +#;***************************************************************************** + + +############################################################################## +# +# Turin reference board - 2 SPI FLash devices accessible by x86 (selected by DIP-switch): +# 1) 32MB Flash with 10-pin header next to the VGA connector. +# 2) 64MB Flash with 10-pin header at 90-degrees from VGA connector, and also accessible by the BMC. +# +############################################################################## + +[Defines] + # Platform.inc.fdf can contain custom DEFINES, consumed by FlashmMapInclude.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/Platform.inc.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/FlashMapInclude.fdf + + DEFINE EFS_ESPI_BYTE0 = 0x0E + DEFINE EFS_ESPI_BYTE1 = 0xFF +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +!include $(PROCESSOR_PATH)/Include/Fdf/ProjectCommon.inc.fdf + +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ +!include MinPlatformPkg/Include/Fdf/RuleInclude.fdf diff --git a/Platform/AMD/TurinBoard/Include/AgesaInc/AgesaExt.dxe.inc.fdf b/Platform/AMD/TurinBoard/Include/AgesaInc/AgesaExt.dxe.inc.fdf new file mode 100644 index 0000000000..efafac0b6c --- /dev/null +++ b/Platform/AMD/TurinBoard/Include/AgesaInc/AgesaExt.dxe.inc.fdf @@ -0,0 +1,19 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All rights reserved. +#; +#;***************************************************************************** +# +## @file +# CRB specific - External AGESA DXE build. +# +## + # + # AMD AGESA DXE Includes - External + # + !include AgesaModulePkg/AgesaSp5$(SOC_SKU_TITLE)ModulePkg.dxe.inc.fdf + !if $(CBS_INCLUDE) == TRUE + !if $(SOC_FAMILY) != $(SOC_FAMILY_2) + !include AmdCbsPkg/Library/Family/$(SOC_FAMILY_2)/$(SOC_SKU_2)/External/Cbs$(SOC2_2).dxe.inc.fdf + !endif + !include AmdCbsPkg/Library/Family/$(SOC_FAMILY)/$(SOC_SKU)/External/Cbs$(SOC2).dxe.inc.fdf + !endif diff --git a/Platform/AMD/TurinBoard/Include/AgesaInc/AgesaExt.inc.dsc b/Platform/AMD/TurinBoard/Include/AgesaInc/AgesaExt.inc.dsc new file mode 100644 index 0000000000..cbb5c0d2d7 --- /dev/null +++ b/Platform/AMD/TurinBoard/Include/AgesaInc/AgesaExt.inc.dsc @@ -0,0 +1,19 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All rights reserved. +#; +#;****************************************************************************** +# +## @file +# CRB specific - External AGESA build. +# +## + # + # AMD AGESA Includes - External + # + !include AgesaModulePkg/AgesaSp5$(SOC_SKU_TITLE)ModulePkg.inc.dsc + !if $(CBS_INCLUDE) == TRUE + !if $(SOC_FAMILY) != $(SOC_FAMILY_2) + !include AmdCbsPkg/Library/Family/$(SOC_FAMILY_2)/$(SOC_SKU_2)/External/Cbs$(SOC2_2).inc.dsc + !endif + !include AmdCbsPkg/Library/Family/$(SOC_FAMILY)/$(SOC_SKU)/External/Cbs$(SOC2).inc.dsc + !endif diff --git a/Platform/AMD/TurinBoard/Include/AgesaInc/AgesaExt.pei.inc.fdf b/Platform/AMD/TurinBoard/Include/AgesaInc/AgesaExt.pei.inc.fdf new file mode 100644 index 0000000000..a6e138cdd5 --- /dev/null +++ b/Platform/AMD/TurinBoard/Include/AgesaInc/AgesaExt.pei.inc.fdf @@ -0,0 +1,19 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All rights reserved. +#; +#;***************************************************************************** +# +## @file +# CRB specific - External AGESA PEI build. +# +## + # + # AMD AGESA PEI Includes - External + # + !include AgesaModulePkg/AgesaSp5$(SOC_SKU_TITLE)ModulePkg.pei.inc.fdf + !if $(CBS_INCLUDE) == TRUE + !if $(SOC_FAMILY) != $(SOC_FAMILY_2) + !include AmdCbsPkg/Library/Family/$(SOC_FAMILY_2)/$(SOC_SKU_2)/External/Cbs$(SOC2_2).pei.inc.fdf + !endif + !include AmdCbsPkg/Library/Family/$(SOC_FAMILY)/$(SOC_SKU)/External/Cbs$(SOC2).pei.inc.fdf + !endif diff --git a/Platform/AMD/TurinBoard/Include/AgesaInc/AgesaInt.dxe.inc.fdf b/Platform/AMD/TurinBoard/Include/AgesaInc/AgesaInt.dxe.inc.fdf new file mode 100644 index 0000000000..b62be7dd23 --- /dev/null +++ b/Platform/AMD/TurinBoard/Include/AgesaInc/AgesaInt.dxe.inc.fdf @@ -0,0 +1,21 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All rights reserved. +#; +#;***************************************************************************** +# +## @file +# CRB specific - Internal AGESA DXE build. +# +## + # + # AMD AGESA DXE Includes - Internal + # + !include AgesaModulePkg/AgesaSp5$(SOC_SKU_TITLE)ModulePkg.dxe.inc.fdf + !if $(CBS_INCLUDE) == TRUE + !if $(SOC_FAMILY) != $(SOC_FAMILY_2) + !include AmdCbsPkg/Library/Family/$(SOC_FAMILY_2)/$(SOC_SKU_2)/Internal/Cbs$(SOC2_2).dxe.inc.fdf + !endif + !include AmdCbsPkg/Library/Family/$(SOC_FAMILY)/$(SOC_SKU)/Internal/Cbs$(SOC2).dxe.inc.fdf + !else + !include AmdCbsPkg/Library/CbsInstanceNull/CbsInstanceNull.dxe.inc.fdf + !endif diff --git a/Platform/AMD/TurinBoard/Include/AgesaInc/AgesaInt.inc.dsc b/Platform/AMD/TurinBoard/Include/AgesaInc/AgesaInt.inc.dsc new file mode 100644 index 0000000000..d2e6ec58ec --- /dev/null +++ b/Platform/AMD/TurinBoard/Include/AgesaInc/AgesaInt.inc.dsc @@ -0,0 +1,22 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All rights reserved. +#; +#;****************************************************************************** +# +## @file +# CRB specific - Internal AGESA build. +# +## + # + # AMD AGESA Includes - Internal + # + !include AgesaModulePkg/AgesaSp5$(SOC_SKU_TITLE)ModulePkg.inc.dsc + !include AgesaModulePkg/AgesaIdsIntBrh.inc.dsc + !if $(CBS_INCLUDE) == TRUE + !if $(SOC_FAMILY) != $(SOC_FAMILY_2) + !include AmdCbsPkg/Library/Family/$(SOC_FAMILY_2)/$(SOC_SKU_2)/Internal/Cbs$(SOC2_2).inc.dsc + !endif + !include AmdCbsPkg/Library/Family/$(SOC_FAMILY)/$(SOC_SKU)/Internal/Cbs$(SOC2).inc.dsc + !else + !include AmdCbsPkg/Library/CbsInstanceNull/CbsInstanceNull.inc.dsc + !endif diff --git a/Platform/AMD/TurinBoard/Include/AgesaInc/AgesaInt.pei.inc.fdf b/Platform/AMD/TurinBoard/Include/AgesaInc/AgesaInt.pei.inc.fdf new file mode 100644 index 0000000000..aa4ce0e0ca --- /dev/null +++ b/Platform/AMD/TurinBoard/Include/AgesaInc/AgesaInt.pei.inc.fdf @@ -0,0 +1,21 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All rights reserved. +#; +#;***************************************************************************** +# +## @file +# CRB specific - Internal AGESA PEI build. +# +## + # + # AMD AGESA PEI Includes - Internal + # + !include AgesaModulePkg/AgesaSp5$(SOC_SKU_TITLE)ModulePkg.pei.inc.fdf + !if $(CBS_INCLUDE) == TRUE + !if $(SOC_FAMILY) != $(SOC_FAMILY_2) + !include AmdCbsPkg/Library/Family/$(SOC_FAMILY_2)/$(SOC_SKU_2)/Internal/Cbs$(SOC2_2).pei.inc.fdf + !endif + !include AmdCbsPkg/Library/Family/$(SOC_FAMILY)/$(SOC_SKU)/Internal/Cbs$(SOC2).pei.inc.fdf + !else + !include AmdCbsPkg/Library/CbsInstanceNull/CbsInstanceNull.pei.inc.fdf + !endif diff --git a/Platform/AMD/TurinBoard/Include/Dsc/Platform.inc.dsc b/Platform/AMD/TurinBoard/Include/Dsc/Platform.inc.dsc new file mode 100644 index 0000000000..98c708abe3 --- /dev/null +++ b/Platform/AMD/TurinBoard/Include/Dsc/Platform.inc.dsc @@ -0,0 +1,16 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All rights reserved. +#;***************************************************************************** + +# CPM path +!ifndef CPM_DIR_PATH + CPM_DIR_PATH = $(AMD_PROCESSOR)/AmdCpm$(AMD_PROCESSOR) +!endif +!include AmdCpmPkg/Addendum/Oem/$(PLATFORM_CRB)/Processor/$(CPM_DIR_PATH)$(PLATFORM_CRB)Pkg.inc.dsc + +# AMD AGESA Include Path +!ifdef $(INTERNAL_IDS) + !include $(PROCESSOR_PATH)/Include/AgesaInc/AgesaInt.inc.dsc +!else + !include $(PROCESSOR_PATH)/Include/AgesaInc/AgesaExt.inc.dsc +!endif diff --git a/Platform/AMD/TurinBoard/Include/Dsc/PlatformCommonPcd.dsc.inc b/Platform/AMD/TurinBoard/Include/Dsc/PlatformCommonPcd.dsc.inc new file mode 100644 index 0000000000..3f0e65979a --- /dev/null +++ b/Platform/AMD/TurinBoard/Include/Dsc/PlatformCommonPcd.dsc.inc @@ -0,0 +1,715 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All rights reserved. +#;***************************************************************************** + +[Defines] +!ifndef SECURE_BOOT_ENABLE + DEFINE SECURE_BOOT_ENABLE = TRUE +!endif +!ifndef PLATFORM_SECURE + DEFINE PLATFORM_SECURE = FALSE +!endif + DEFINE NETWORK_IP6_ENABLE = FALSE + + # + # Redfish support + # + DEFINE REDFISH_ENABLE = FALSE + + # + # Set Platform Redfish configuration + # +!if $(REDFISH_ENABLE) == TRUE + + # Enable BMC USB NIC as the Redfish transport interface + DEFINE USB_NETWORK_SUPPORT = TRUE + + # Allow HTTP connection for Redfish + DEFINE NETWORK_SNP_ENABLE = TRUE + DEFINE NETWORK_IP6_ENABLE = TRUE + DEFINE NETWORK_IP4_ENABLE = TRUE + DEFINE NETWORK_HTTP_ENABLE = TRUE + DEFINE NETWORK_ALLOW_HTTP_CONNECTIONS = TRUE +!endif + +[Packages] + AmdCpmPkg/AmdCpmPkg.dec + AmdMinBoardPkg/AmdMinBoardPkg.dec + AmdPlatformPkg/AmdPlatformPkg.dec + ManageabilityPkg/ManageabilityPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + Network/NetworkFeaturePkg/NetworkFeaturePkg.dec + PcAtChipsetPkg/PcAtChipsetPkg.dec + SecurityPkg/SecurityPkg.dec + SpcrFeaturePkg/SpcrFeaturePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +# MinPlatformPkg includes +!include AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc + +[PcdsFixedAtBuild] + # + # Key Boot Stage + # + # Please select the Boot Stage here. + # Stage 1 - enable debug (system deadloop after debug init) + # Stage 2 - mem init (system deadloop after mem init) + # Stage 3 - boot to shell only + # Stage 4 - boot to OS + # Stage 5 - boot to OS with security boot enabled + # Stage 6 - boot with advanced features enabled + # + gMinPlatformPkgTokenSpaceGuid.PcdBootStage|6 + gAmdCpmPkgTokenSpaceGuid.PcdAmdAcpiBertTableHeaderOemTableId|$(PLATFORM_CRB_TABLE_ID) + gAmdCpmPkgTokenSpaceGuid.PcdAmdAcpiHestTableHeaderOemTableId|$(PLATFORM_CRB_TABLE_ID) + gAmdCpmPkgTokenSpaceGuid.PcdAmdAcpiEinjTableHeaderOemTableId|$(PLATFORM_CRB_TABLE_ID) + + # Set ROM Armor Selection + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdPspRomArmorSelection|1 + + # + # Set EFI Shell file description + # + gMinPlatformPkgTokenSpaceGuid.PcdShellFileDesc|L"Internal UEFI Shell 2.2" + + # + # BSP Broadcast Method for the first-time wakeup of APs + # + gUefiCpuPkgTokenSpaceGuid.PcdFirstTimeWakeUpAPsBySipi|FALSE + +[PcdsFeatureFlag] + # + # MinPlatformPkg Configuration + # + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdSerialTerminalEnable|TRUE + + gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|FALSE + + !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 1 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE + !endif + + !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 2 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE + !endif + + !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 3 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE + !endif + + !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 4 + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE + !endif + + !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 5 + !if $(SIMNOW_SUPPORT) == FALSE || $(EMULATION) == FALSE + gNetworkFeaturePkgTokenSpaceGuid.PcdNetworkFeatureEnable|TRUE + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|$(SECURE_BOOT_ENABLE) + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE + !endif + gSpcrFeaturePkgTokenSpaceGuid.PcdSpcrFeatureEnable|TRUE + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosFeatureEnable|TRUE + !endif + +# Below include file should be here +# after PcdBootStage is set. +# and after respective features are enabled/disabled depends on PcdBootStage +!include AdvancedFeaturePkg/Include/AdvancedFeatures.dsc + + # + # Below are Manageability feature knobs. + # + gManageabilityPkgTokenSpaceGuid.PcdManageabilityDxeIpmiBmcAcpi|FALSE + gManageabilityPkgTokenSpaceGuid.PcdManageabilityDxeIpmiBmcElog|FALSE + gManageabilityPkgTokenSpaceGuid.PcdManageabilityDxeIpmiEnable|FALSE + gManageabilityPkgTokenSpaceGuid.PcdManageabilityDxeIpmiFrb|FALSE + gManageabilityPkgTokenSpaceGuid.PcdManageabilityDxeIpmiFru|FALSE + gManageabilityPkgTokenSpaceGuid.PcdManageabilityDxeIpmiOsWdt|FALSE + gManageabilityPkgTokenSpaceGuid.PcdManageabilityDxeIpmiSolStatus|FALSE + gManageabilityPkgTokenSpaceGuid.PcdManageabilityDxeMctpEnable|FALSE + gManageabilityPkgTokenSpaceGuid.PcdManageabilityDxePldmEnable|FALSE + gManageabilityPkgTokenSpaceGuid.PcdManageabilityDxePldmSmbiosTransferEnable|FALSE + gManageabilityPkgTokenSpaceGuid.PcdManageabilityPeiIpmiEnable|FALSE + gManageabilityPkgTokenSpaceGuid.PcdManageabilityPeiIpmiFrb|FALSE + gManageabilityPkgTokenSpaceGuid.PcdManageabilitySmmIpmiEnable|FALSE + # Enable IPMI feature for boot stage >=5 and only for real SoC + !if (gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 5) && ($(SIMNOW_SUPPORT) == FALSE || $(EMULATION) == FALSE) + gManageabilityPkgTokenSpaceGuid.PcdManageabilityDxeIpmiEnable|TRUE + !endif + + !if $(SIMNOW_SUPPORT) == TRUE || $(EMULATION) == TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|FALSE + !endif + + # MdeModulePkg + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwarePerformanceDataTableS3Support|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdPciDegradeResourceForOptionRom|FALSE + gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE + gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE + + # Uefi Cpu Package + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmBlockStartupThisAp|TRUE + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard|FALSE + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmFeatureControlMsrLock|FALSE + + # ACPI + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE + + # Enable ROM Armor + gAmdPlatformPkgTokenSpaceGuid.PcdRomArmorEnable|TRUE + +[PcdsFixedAtBuild.IA32] + # + # Temporary DRAM space for SEC->PEI transition (256KB) + # AMD_ENABLE_UEFI_STACK (Flat32.asm) divides: 1/2 Heap + 1/2 Stack + # + gAmdMinBoardPkgTokenSpaceGuid.PcdTempRamBase|0x00100000 + gAmdMinBoardPkgTokenSpaceGuid.PcdTempRamSize|0x00100000 + + gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x80000 + +[PcdsFixedAtBuild] + # Console/Uart settings + !if $(SERIAL_PORT) == "FCH_MMIO" + # MMIO based flow control UART0, this option is ideal for physical serial cable attached + gAmdCpmPkgTokenSpaceGuid.PcdFchUartPort|0 + ## Base address of 16550 serial port registers in MMIO or I/O space. + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0xFEDC9000 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride|4 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate|48000000 + # Cannot assign PCD to PCD, hence setting the SPCR IRQ here + gSpcrFeaturePkgTokenSpaceGuid.PcdSpcrInterrupt|3 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdIdsDebugPrintSerialPortSelect|0x0001 + !endif + + !if $(SERIAL_PORT) == "FCH_IO" + # Legacy based flow control UART0, this option is ideal for physical serial cable attached + gAmdCpmPkgTokenSpaceGuid.PcdFchUartPort|0 + ## Base address of 16550 serial port registers in MMIO or I/O space. + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x3F8 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|0x00 + # Cannot assign PCD to PCD, hence setting the SPCR IRQ here + gSpcrFeaturePkgTokenSpaceGuid.PcdSpcrInterrupt|3 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdIdsDebugPrintSerialPortSelect|0x0100 + !endif + + !if $(SERIAL_PORT) == "BMC_SOL" + # MMIO based non-flow control UART1, this option is ideal for physical serial cable attached + gAmdCpmPkgTokenSpaceGuid.PcdFchUartPort|1 + ## Base address of 16550 serial port registers in MMIO or I/O space. + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0xFEDCA000 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride|4 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate|48000000 + # Cannot assign PCD to PCD, hence setting the SPCR IRQ here + gSpcrFeaturePkgTokenSpaceGuid.PcdSpcrInterrupt|0xE + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdIdsDebugPrintSerialPortSelect|0x0002 + !endif + + !if $(SERIAL_PORT) == "BMC_SOL_IO" + # Legacy based non-flow control UART1, this option is ideal for physical serial cable attached + gAmdCpmPkgTokenSpaceGuid.PcdFchUartPort|1 + ## Base address of 16550 serial port registers in MMIO or I/O space. + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x3F8 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|0x00 + # Cannot assign PCD to PCD, hence setting the SPCR IRQ here + gSpcrFeaturePkgTokenSpaceGuid.PcdSpcrInterrupt|0xE + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdIdsDebugPrintSerialPortSelect|0x0200 + !endif + + !if $(SERIAL_PORT) == "BMC_ESPI" + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x3F8 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|0x00 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdIdsDebugPrintSerialPortSelect|0x0000 + !endif + + # Indicates the receive FIFO depth of UART controller. + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|64 + + # Default Value of PlatformLangCodes Variable. + gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLangCodes|"en-US" + + ## The mask is used to control ReportStatusCodeLib behavior. + # BIT0 - Enable Progress Code. + # BIT1 - Enable Error Code. + # BIT2 - Enable Debug Code. + !ifdef $(INTERNAL_IDS) + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 + !else + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x00 + !endif + + # + # Debug Masks + # + # // + # // Declare bits for PcdDebugPropertyMask + # // + # DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED 0x01 + # DEBUG_PROPERTY_DEBUG_PRINT_ENABLED 0x02 + # DEBUG_PROPERTY_DEBUG_CODE_ENABLED 0x04 + # DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED 0x08 + # DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED 0x10 + # DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED 0x20 + # // + # // Declare bits for PcdFixedDebugPrintErrorLevel and the ErrorLevel parameter of DebugPrint() + # // + # DEBUG_INIT 0x00000001 // Initialization + # DEBUG_WARN 0x00000002 // Warnings + # DEBUG_LOAD 0x00000004 // Load events + # DEBUG_FS 0x00000008 // EFI File system + # DEBUG_POOL 0x00000010 // Alloc & Free's + # DEBUG_PAGE 0x00000020 // Alloc & Free's + # DEBUG_INFO 0x00000040 // Informational debug messages + # DEBUG_DISPATCH 0x00000080 // PEI/DXE/SMM Dispatchers + # DEBUG_VARIABLE 0x00000100 // Variable + # DEBUG_BM 0x00000400 // Boot Manager + # DEBUG_BLKIO 0x00001000 // BlkIo Driver + # DEBUG_NET 0x00004000 // SNI Driver + # DEBUG_UNDI 0x00010000 // UNDI Driver + # DEBUG_LOADFILE 0x00020000 // UNDI Driver + # DEBUG_EVENT 0x00080000 // Event messages + # DEBUG_GCD 0x00100000 // Global Coherency Database changes + # DEBUG_CACHE 0x00200000 // Memory range cachability changes + # DEBUG_VERBOSE 0x00400000 // Detailed debug messages that may significantly impact boot performance + # DEBUG_MANAGEABILITY 0x00800000 // Detailed debug and payload message of manageability + # // related modules, such Redfish, IPMI, MCTP and etc. + # DEBUG_ERROR 0x80000000 // Error + + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27 + !if $(DEBUG_DISPATCH_ENABLE) + gEfiMdePkgTokenSpaceGuid.PcdFixedDebugPrintErrorLevel|0x808000CF + !else + gEfiMdePkgTokenSpaceGuid.PcdFixedDebugPrintErrorLevel|0x8080004F + !endif + + # + # AGESA Debug + # + !if ($(IDS_DEBUG_ENABLE) == TRUE) AND ($(SERIAL_PORT) != "NONE") + # IdsDebugPrint Filter. Refer to Library/IdsLib.h for details. + # 0x100401008A30042C (GNB_TRACE | PCIE_MISC | NB_MISC | GFX_MISC | CPU_TRACE | MEM_FLOW | + # MEM_STATUS | MEM_PMU | FCH_TRACE | MAIN_FLOW | TEST_POINT | PSP_TRACE) + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdIdsDebugPrintFilter|0x1004010300300400 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdIdsDebugPrintEnable|TRUE + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdIdsDebugPrintSerialPortEnable|TRUE + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdIdsDebugPrintSerialPortDetectCableConnection|FALSE + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdIdsDebugPrintSerialPort|gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + !else + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdIdsDebugPrintEnable|FALSE + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdIdsDebugPrintSerialPortEnable|FALSE + !endif + + !if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|80 + !else + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x00 + !endif + + # + # Specifies the initial value for Register_D in RTC. + # Reason for change: + # PcRtc.c wants to see register D bit 7 (VRT) high almost immediately after writing the below value, + # which clears it with the default UEFI value of zero. The AMD FCH updates this bit only once per 4-1020ms (1020ms default). + # This causes function RtcWaitToUpdate to return an error. Preset VRT to 1 to avoid this. + # + gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterD|0x80 + + # + # SMBIOS + # + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosT16MaximumCapacity|0x80000000 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSocketDesignationSocket0|"P0" + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSocketDesignationSocket1|"P1" + + # + # PCIe Config-space MMIO (1MB per bus, 256MB) + # + !if $(SIMNOW_SUPPORT) == FALSE || $(EMULATION) == FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdPcieResizableBarSupport|TRUE + !endif + + !if $(PCIE_MULTI_SEGMENT) == TRUE + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x3FFB00000000 + gAmdMinBoardPkgTokenSpaceGuid.PcdPciExpressBaseAddressLow|0x0 + gAmdMinBoardPkgTokenSpaceGuid.PcdPciExpressBaseAddressHi|0x3FFB + !else + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 + gAmdMinBoardPkgTokenSpaceGuid.PcdPciExpressBaseAddressLow|0xE0000000 + gAmdMinBoardPkgTokenSpaceGuid.PcdPciExpressBaseAddressHi|0x0 + !endif + + # + # Boot + # + # PCDs to set the default size of the different UEFI memory types to promote + # contiguous UEFI memory allocation. These values are used by + # AmdCommon/Pei/PlatformInitPei/MemoryInitPei.c to reserve + # default chunks for each memory type when gEfiMemoryTypeInformationGuid + # variable is not set. These values can be updated to prevent reboot because + # MdeModulePkg/Library/UefiBootManagerLib/BmMisc.c: + # BmSetMemoryTypeInformationVariable() sets gEfiMemoryTypeInformationGuid at + # the end of post to reserve more memory. Serial output from this code will + # display sizes required, which can then be updated in these PCDs. + # Memory Type 09 + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize | 0x400 + # Memory Type 0A + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize | 0x400 + # Memory Type 00 + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize | 0x5000 + # Memory Type 06 + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize | 0x800 + # Memory Type 05 + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize | 0x100 + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|10 + !if $(EMULATION) == TRUE + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|0 + !endif + # 462CAA21-7614-4503-836E-8AB6F4662331 (UiApp FILE_GUID) + gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ GUID("462CAA21-7614-4503-836E-8AB6F4662331") } + + # 1GB page support + gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable|TRUE + + # + # ACPI + # + gEfiAmdAgesaPkgTokenSpaceGuid.PcdFchOemEnableAcpiSwSmi|0xA0 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdFchOemDisableAcpiSwSmi|0xA1 + + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId|"AMD " + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x00000000 + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x20444D41 + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|0x00000001 + + gMinPlatformPkgTokenSpaceGuid.PcdFadtPreferredPmProfile|4 + gMinPlatformPkgTokenSpaceGuid.PcdFadtIaPcBootArch|0x0000 + gMinPlatformPkgTokenSpaceGuid.PcdFadtFlags|0x0002052D + gPcAtChipsetPkgTokenSpaceGuid.PcdHpetBaseAddress|0xFED00000 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdAcpiCpuSsdtProcessorScopeInSb|TRUE + + # NOTE, below PCD should match with gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdCfgFchIoapicId + gMinPlatformPkgTokenSpaceGuid.PcdIoApicId|0x80 + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicCount|8 + # NOTE, below PCD should match with gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdCfgIoApicIdBase + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicIdBase|0xF0 + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicAddressBase|0xFEC00000 + gMinPlatformPkgTokenSpaceGuid.PcdLocalApicAddress|0xFEE00000 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiEnableSwSmi|gEfiAmdAgesaPkgTokenSpaceGuid.PcdFchOemEnableAcpiSwSmi + gMinPlatformPkgTokenSpaceGuid.PcdAcpiDisableSwSmi|gEfiAmdAgesaPkgTokenSpaceGuid.PcdFchOemDisableAcpiSwSmi + !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE + gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07 + !endif + + # Max Cpu constraints + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2 + + # + # EFI NV Storage + # + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0xA000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0xA000 + + # + # AGESA NBIO + # + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdCfgIommuMMIOAddressReservedEnable|TRUE + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdCfgIoApicMMIOAddressReservedEnable|TRUE + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdCfgIoApicIdPreDefineEn|TRUE #### Makes PEI assign IOAPIC IDs + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdCfgIoApicIdBase|0xF0 + + gEfiAmdAgesaPkgTokenSpaceGuid.PcdCompliantEdkIIAcpiSdtProtocol|TRUE + + # AGESA FCH + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFchCfgAcpiPm1EvtBlkAddr|0x800 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFchCfgAcpiPm1CntBlkAddr|0x804 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFchCfgAcpiPmTmrBlkAddr|0x808 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFchCfgCpuControlBlkAddr|0x810 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFchCfgAcpiGpe0BlkAddr|0x820 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdFchOemBeforePciRestoreSwSmi|0xB3 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdFchOemAfterPciRestoreSwSmi|0xB4 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdFchOemSpiUnlockSwSmi|0xB7 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdFchOemSpiLockSwSmi|0xB8 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdNumberOfPhysicalSocket|gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdAmdMemCfgMaxPostPackageRepairEntries|0x3F + + # Disable S3 support + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable|FALSE + + ## Toggle for whether the VariablePolicy engine should allow disabling. + # The engine is enabled at power-on, but the interface allows the platform to + # disable enforcement for servicing flexibility. If this PCD is disabled, it will block the ability to + # disable the enforcement and VariablePolicy enforcement will always be ON. + # TRUE - VariablePolicy can be disabled by request through the interface (until interface is locked) + # FALSE - VariablePolicy interface will not accept requests to disable and is ALWAYS ON + # @Prompt Allow VariablePolicy enforcement to be disabled. + gEfiMdeModulePkgTokenSpaceGuid.PcdAllowVariablePolicyEnforcementDisable|TRUE + + # + # FALSE: The board is not a FSP wrapper (FSP binary not used) + # TRUE: The board is a FSP wrapper (FSP binary is used) + # + gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|FALSE + + # TRUE - 5-Level Paging will be enabled. + # FALSE - 5-Level Paging will not be enabled. + gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable|FALSE + + # Specifies stack size in bytes for each processor in SMM. + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x10000 + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmShadowStackSize|0x10000 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdAcpiTableHeaderOemId|gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId + !if $(EMULATION) == TRUE + # enable IDS prints for emulation to port80 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdIdsDebugPrintEmulationAutoDetect|$(IDS_DEBUG_ENABLE) + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdAmdPspRecoveryFlagDetectEnable|FALSE + !endif + + # Secureboot + !if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable == TRUE + gEfiSecurityPkgTokenSpaceGuid.PcdUserPhysicalPresence|TRUE + !endif + gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe0BlockAddress|gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFchCfgAcpiGpe0BlkAddr + gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe1BlockAddress|0 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AControlBlockAddress|gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFchCfgAcpiPm1CntBlkAddr + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AEventBlockAddress|gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFchCfgAcpiPm1EvtBlkAddr + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BControlBlockAddress|0 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BEventBlockAddress|0 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm2ControlBlockAddress|0 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPmTimerBlockAddress|gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFchCfgAcpiPmTmrBlkAddr + gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe0BlockLength|0x8 + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiXPm1aEvtBlkAccessSize|0x2 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiXPm1aCntBlkAccessSize|0x2 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiXPmTmrBlkAccessSize|0x03 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiXGpe0BlkAccessSize|0x1 + + # + # The base address of temporary page table for accessing PCIE MMIO base address above 4G in PEI phase. + # + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdPeiTempPageTableBaseAddress|0x60000000 + !if $(DRAM_BOOT) == TRUE + gMinPlatformPkgTokenSpaceGuid.PcdShellFile|{GUID(68198A68-D249-4826-BC5E-45DF0CCA2A53)} + gMinPlatformPkgTokenSpaceGuid.PcdShellFileDesc|L"Emulation Linux Loader" + !endif + + # To create MPDMA devices under RB named as PCIx + gAmdCpmPkgTokenSpaceGuid.UsePciXAslName|TRUE + + # + # edk2 Redfish foundation + # + !if $(REDFISH_ENABLE) == TRUE + gEfiRedfishPkgTokenSpaceGuid.PcdRedfishRestExServiceDevicePath.DevicePathMatchMode|DEVICE_PATH_MATCH_MAC_NODE + gEfiRedfishPkgTokenSpaceGuid.PcdRedfishRestExServiceDevicePath.DevicePathNum|1 + # + # Below is the MAC address of network adapter on EDK2 Emulator platform. + # You can use ifconfig under EFI shell to get the MAC address of network adapter on EDK2 Emulator platform. + # + gEfiRedfishPkgTokenSpaceGuid.PcdRedfishRestExServiceDevicePath.DevicePath|{DEVICE_PATH("MAC(005056c00009,0x1)")} + gEfiRedfishPkgTokenSpaceGuid.PcdRedfishRestExServiceAccessModeInBand|True + gEfiRedfishPkgTokenSpaceGuid.PcdRedfishDiscoverAccessModeInBand|True + !endif + + # + # USB Network (Communication Device Class) drivers + # + !if $(USB_NETWORK_SUPPORT) == TRUE + # Set USB NIC Rate Limiting + gEfiMdeModulePkgTokenSpaceGuid.PcdEnableUsbNetworkRateLimiting|TRUE + !endif + +[PcdsDynamicDefault.common] + # + # Set MMIO Above4GB at the 1TB boundary + # + !if $(PCIE_MULTI_SEGMENT) == TRUE + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdMmioAbove4GLimit|0x3FFBFFFFFFFF + !else + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdMmioAbove4GLimit|0x7FBFFFFFFFF + !endif + + # IO Resource padding in bytes, default 4KB, override to 0. + gAmdMinBoardPkgTokenSpaceGuid.PcdPciHotPlugResourcePadIo|0x00 + + # + # Flash NV Storage + # + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0 + + # + # AGESA FCH + # + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdHpetEnable|TRUE + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdHpetMsiDis|FALSE + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdNoneSioKbcSupport|TRUE + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdCfgFchIoapicId|gMinPlatformPkgTokenSpaceGuid.PcdIoApicId + + # Tell AGESA how you want the UART configured for serial output + # FchRTDeviceEnableMap + # < BIT4 - LPC : PcdLpcEnable + # < BIT5 - I2C0 : FchRTDeviceEnableMap[BIT5] + # < BIT6 - I2C1 : FchRTDeviceEnableMap[BIT6] + # < BIT7 - I2C2 : FchRTDeviceEnableMap[BIT7] + # < BIT8 - I2C3 : FchRTDeviceEnableMap[BIT8] + # < BIT9 - I2C4 : FchRTDeviceEnableMap[BIT9] + # < BIT10 - I2C5 : FchRTDeviceEnableMap[BIT10] + # < BIT11 - UART0 : FchRTDeviceEnableMap[BIT11] + # < BIT12 - UART1 : FchRTDeviceEnableMap[BIT12] + # < BIT16 - UART2 : FchRTDeviceEnableMap[BIT13] + # < BIT18 - SD : PcdEmmcEnable and PcdEmmcType < 5 + # < BIT26 - UART3 : FchRTDeviceEnableMap[BIT26] + # < BIT27 - eSPI : PcdEspiEnable - read-only. + # < BIT28 - eMMC : PcdEmmcEnable - read-only. + gEfiAmdAgesaModulePkgTokenSpaceGuid.FchRTDeviceEnableMap|0x00001F60 + # FchUartLegacyEnable + # 0-disable, 1- 0x2E8/2EF, 2 - 0x2F8/2FF, 3 - 0x3E8/3EF, 4 - 0x3F8/3FF + !if $(SERIAL_PORT) == "FCH_IO" + gEfiAmdAgesaPkgTokenSpaceGuid.FchUart0LegacyEnable|0x04 + gEfiAmdAgesaPkgTokenSpaceGuid.FchUart1LegacyEnable|0x03 + !elseif $(SERIAL_PORT) == "BMC_SOL_IO" + gEfiAmdAgesaPkgTokenSpaceGuid.FchUart0LegacyEnable|0x03 + gEfiAmdAgesaPkgTokenSpaceGuid.FchUart1LegacyEnable|0x04 + !endif + + # + # AGESA APCB Recovery + # + # TO-DO: Temporarily disable Apcb Recovery, to suppress debug ASSERT. + !if $(SIMNOW_SUPPORT) == TRUE || $(EMULATION) == TRUE + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdPspApcbRecoveryEnable|FALSE + !endif + + # + # AGESA NBIO + # + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdCfgGnbIoapicId|gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdCfgIoApicIdBase + + # + # AGESA BMC (NBIO) + # + gEfiAmdAgesaPkgTokenSpaceGuid.PcdEarlyBmcLinkTraining|TRUE + gEfiAmdAgesaPkgTokenSpaceGuid.PcdEarlyBmcLinkSocket|0 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdEarlyBmcLinkDie|0 + + !if $(USB_SUPPORT) + ### USB 3.0 controller0 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdXhci0Enable|TRUE + ### USB 3.0 controller1 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdXhci1Enable|TRUE + ### USB3.0 controller0 on MCM-1 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdXhci2Enable|FALSE + ### USB3.0 controller1 on MCM-1 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdXhci3Enable|FALSE + + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdXhciSsid|0x00000000 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdXhciECCDedErrRptEn|FALSE + !else + ### USB 3.0 controller0 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdXhci0Enable|FALSE + ### USB 3.0 controller1 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdXhci1Enable|FALSE + ### USB3.0 controller0 on MCM-1 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdXhci2Enable|FALSE + ### USB3.0 controller1 on MCM-1 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdXhci3Enable|FALSE + !endif + +!if $(SATA_SUPPORT) + ### @brief FCH-SATA enables + ### @details Select whether or not the FCH Sata controller is active. + ### @li TRUE - This option is active. + ### @li FALSE - This option is turned off. + gEfiAmdAgesaPkgTokenSpaceGuid.PcdSataEnable|TRUE + gEfiAmdAgesaPkgTokenSpaceGuid.PcdSataStaggeredSpinup|TRUE +!else + ### @brief FCH-SATA enables + ### @details Select whether or not the FCH Sata controller is active. + ### @li TRUE - This option is active. + ### @li FALSE - This option is turned off. + gEfiAmdAgesaPkgTokenSpaceGuid.PcdSataEnable|FALSE +!endif + + # NVDIMM feature + gEfiAmdAgesaPkgTokenSpaceGuid.PcdNvdimmEnable|FALSE + + # + # Firmware Revision + # + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor|L"AMD" + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareRevision|$(FIRMWARE_REVISION_NUM) + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VERSION_STR)" + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareReleaseDateString|L"$(RELEASE_DATE)" + + # MinPlatformPkg, 1's position enables respective ioapic + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0xFF + +[PcdsPatchableInModule] + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|gEfiMdePkgTokenSpaceGuid.PcdFixedDebugPrintErrorLevel + +[PcdsDynamicHii.X64.DEFAULT] + !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE + gEfiSecurityPkgTokenSpaceGuid.PcdTcgPhysicalPresenceInterfaceVer|L"TCG2_VERSION"|gTcg2ConfigFormSetGuid|0x0|"1.3"|NV,BS + gEfiSecurityPkgTokenSpaceGuid.PcdTpm2AcpiTableRev|L"TCG2_VERSION"|gTcg2ConfigFormSetGuid|0x8|4|NV,BS + !endif + +[PcdsDynamicDefault] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdCcxCfgPFEHEnable|TRUE + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdLegacyFree|TRUE + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdCxlProtocolErrorReporting|1 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdCxlComponentErrorReporting|1 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdEgressPoisonSeverityLo|0 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdEgressPoisonSeverityHi|0 + + !ifdef $(INTERNAL_IDS) + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdAmdCcxSingleBitErrLogging|TRUE + !endif + + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdAmdS3LibTableSize|0x100000 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdPspAntiRollbackLateSplFuse|TRUE + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdUsbRSOemConfigurationTable|{0x0D,0x10,0xB1,0x00,0x00,0x03,0x03,0x03,0x03,0x00,0x01,0x06,0x03,0x01,0x03,0x03,0x03,0x03,0x00,0x01,0x06,0x03,0x01,0x03,0x03,0x03,0x03,0x00,0x01,0x06,0x03,0x01,0x03,0x03,0x03,0x03,0x00,0x01,0x06,0x03,0x01,0x00,0x00,0x03,0x03,0x03,0x03,0x00,0x01,0x06,0x03,0x01,0x03,0x03,0x03,0x03,0x00,0x01,0x06,0x03,0x01,0x03,0x03,0x03,0x03,0x00,0x01,0x06,0x03,0x01,0x03,0x03,0x03,0x03,0x00,0x01,0x06,0x03,0x01,0x01,0x07,0x00,0x00,0x07,0x01,0x05,0x00,0x05,0x00,0x05,0x00,0x05,0x07,0x00,0x00,0x07,0x01,0x05,0x00,0x05,0x00,0x05,0x00,0x05,0x07,0x00,0x00,0x07,0x01,0x05,0x00,0x05,0x00,0x05,0x00,0x05,0x07,0x00,0x00,0x07,0x01,0x05,0x00,0x05,0x00,0x05,0x00,0x05,0x01,0x07,0x00,0x00,0x07,0x01,0x05,0x00,0x05,0x00,0x05,0x00,0x05,0x07,0x00,0x00,0x07,0x01,0x05,0x00,0x05,0x00,0x05,0x00,0x05,0x07,0x00,0x00,0x07,0x01,0x05,0x00,0x05,0x00,0x05,0x00,0x05,0x07,0x00,0x00,0x07,0x01,0x05,0x00,0x05,0x00,0x05,0x00,0x05} + + # Enable/Disable IOMMU (default TRUE) + # gEfiAmdAgesaPkgTokenSpaceGuid.PcdCfgIommuSupport|FALSE + + gEfiAmdAgesaPkgTokenSpaceGuid.PcdIvInfoDmaReMap|FALSE + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdCStateIoBaseAddress|0x813 + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdResetMode|0x07 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFchCfgSmiCmdPortAddr|0xB2 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdTelemetry_VddcrSocfull_Scale_Current|0x50 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdTelemetry_VddcrVddfull_Scale_Current|0xFF + + !if $(SIMNOW_SUPPORT) == TRUE + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdSmuFeatureControlDefines|0x00030000 + !endif + + !if $(SIMNOW_SUPPORT) == TRUE || $(EMULATION) == TRUE + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdMemPostPackageRepair|FALSE + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdMemBootTimePostPackageRepair|FALSE + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdMemRuntimePostPackageRepair|FALSE + !endif + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdLpcEnable|FALSE + +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInitializationPolicy|1 + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{GUID({ 0x286bf25a, 0xc2c3, 0x408c, { 0xb3, 0xb4, 0x25, 0xe6, 0x75, 0x8b, 0x73, 0x17 } })} + gEfiSecurityPkgTokenSpaceGuid.PcdActiveTpmInterfaceType|0x00 + gEfiSecurityPkgTokenSpaceGuid.PcdTcg2PhysicalPresenceFlags|0x700E0 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdPspSystemTpmConfig|0x00 +!endif + + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize|0x10000000 diff --git a/Platform/AMD/TurinBoard/Include/Dsc/ProjectCommon.inc.dsc b/Platform/AMD/TurinBoard/Include/Dsc/ProjectCommon.inc.dsc new file mode 100644 index 0000000000..6855a28be4 --- /dev/null +++ b/Platform/AMD/TurinBoard/Include/Dsc/ProjectCommon.inc.dsc @@ -0,0 +1,546 @@ +#;***************************************************************************** +#; Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. +#; +#;****************************************************************************** + +[LibraryClasses] + # AML library + AmlLib|DynamicTablesPkg/Library/Common/AmlLib/AmlLib.inf + AcpiHelperLib|DynamicTablesPkg/Library/Common/AcpiHelperLib/AcpiHelperLib.inf + + # AMD AGESA + AmdCalloutLib|AgesaModulePkg/Library/AmdCalloutLib/AmdCalloutLib.inf + AmlGenerationLib|AgesaModulePkg/Library/DxeAmlGenerationLib/AmlGenerationLib.inf + OemAgesaCcxPlatformLib|AgesaPkg/Addendum/Ccx/OemAgesaCcxPlatformLibNull/OemAgesaCcxPlatformLibNull.inf + PciHostBridgeLib|AgesaModulePkg/Library/DxeAmdPciHostBridgeLib/PciHostBridgeLib.inf + PciSegmentInfoLib|AgesaPkg/Addendum/PciSegments/PciExpressPciSegmentInfoLib/PciExpressPciSegmentInfoLib.inf + ResetSystemLib|AgesaModulePkg/Library/FchBaseResetSystemLib/FchBaseResetSystemLib.inf + TimerLib|AgesaModulePkg/Library/CcxTscTimerLib/DxeTscTimerLib.inf + !if $(SIMNOW_SUPPORT) == TRUE + AmdPostCodeLib|AgesaModulePkg/Library/AmdPostCodeEmuLib2/AmdPostCodeEmuLib.inf + !endif + + # EDKII Generic + BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf + PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf + PciSegmentLib|MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.inf + SmbusLib|MdePkg/Library/DxeSmbusLib/DxeSmbusLib.inf + + # MinPlatformPkg + AslUpdateLib|MinPlatformPkg/Acpi/Library/DxeAslUpdateLib/DxeAslUpdateLib.inf + BoardAcpiTableLib|MinPlatformPkg/Acpi/Library/BoardAcpiTableLibNull/BoardAcpiTableLibNull.inf + PlatformBootManagerLib|MinPlatformPkg/Bds/Library/DxePlatformBootManagerLib/DxePlatformBootManagerLib.inf + TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLibNull/TestPointCheckLibNull.inf + + # AMD Platform + PlatformSecLib|AmdMinBoardPkg/Library/PlatformSecLib/PlatformSecLib.inf + ReportFvLib|AmdMinBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.inf + FchEspiCmdLib|AgesaModulePkg/Library/FchEspiCmdLib/FchEspiCmdLib.inf + + # Manageability + IpmiCommandLib|ManageabilityPkg/Library/IpmiCommandLib/IpmiCommandLib.inf + + # SPCR Device + SpcrDeviceLib|AmdMinBoardPkg/Library/SpcrDeviceLib/SpcrDeviceLib.inf + + !if $(LOGGING_ENABLE) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + !else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + !endif + + !if $(SOURCE_DEBUG_ENABLE) + DebugCommunicationLib|SourceLevelDebugPkg/Library/DebugCommunicationLibSerialPort/DebugCommunicationLibSerialPort.inf + PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraActionLibDebug.inf + !else + PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf + !endif + + !if $(SERIAL_PORT) == "NONE" + SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf + !endif + + !if $(SIMNOW_PORT80_DEBUG) == TRUE + SerialPortLib|AmdPlatformPkg/Library/SimulatorSerialPortLibPort80/SimulatorSerialPortLibPort80.inf + !endif + + PlatformHookLib|AmdCpmPkg/Library/CommonLib/BasePlatformHookLibAmdFchUart/BasePlatformHookLibAmdFchUart.inf + +!if $(REDFISH_ENABLE) == TRUE + # + # edk2 Redfish foundation + # + !include RedfishPkg/RedfishLibs.dsc.inc + # + # edk2 Redfish foundation platform libraries + # + RedfishPlatformHostInterfaceLib|RedfishPkg/Library/PlatformHostInterfaceBmcUsbNicLib/PlatformHostInterfaceBmcUsbNicLib.inf + RedfishPlatformCredentialLib|RedfishPkg/Library/PlatformCredentialLibNull/PlatformCredentialLibNull.inf + RedfishContentCodingLib|RedfishPkg/Library/RedfishContentCodingLibNull/RedfishContentCodingLibNull.inf +!endif + +[LibraryClasses.IA32.SEC] + # AGESA + TimerLib|AgesaModulePkg/Library/CcxTscTimerLib/BaseTscTimerLib.inf + + # MinPlatformPkg + SetCacheMtrrLib|MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLibNull.inf + +[LibraryClasses.IA32.PEIM, LibraryClasses.IA32.PEI_CORE] + # AGESA + TimerLib|AgesaModulePkg/Library/CcxTscTimerLib/PeiTscTimerLib.inf + +[LibraryClasses.common.PEIM] + + # MinPlatformPkg + ReportCpuHobLib|MinPlatformPkg/PlatformInit/Library/ReportCpuHobLib/ReportCpuHobLib.inf + TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/PeiTestPointLib.inf + !if $(TARGET) == DEBUG + TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/PeiTestPointCheckLib.inf + !endif + ReportCpuHobLib|MinPlatformPkg/PlatformInit/Library/ReportCpuHobLib/ReportCpuHobLib.inf + + # AMD Platform + SetCacheMtrrLib|AmdMinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf + +[LibraryClasses.common.SEC, LibraryClasses.common.PEIM, LibraryClasses.common.PEI_CORE] + PciLib|MdePkg/Library/PeiPciLibPciCfg2/PeiPciLibPciCfg2.inf + PciSegmentLib|MdePkg/Library/PeiPciSegmentLibPciCfg2/PeiPciSegmentLibPciCfg2.inf + +[LibraryClasses.common.DXE_CORE, LibraryClasses.common.DXE_SMM_DRIVER, LibraryClasses.common.SMM_CORE, LibraryClasses.common.DXE_DRIVER, LibraryClasses.common.DXE_RUNTIME_DRIVER, LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION] + TimerLib|AgesaModulePkg/Library/CcxTscTimerLib/DxeTscTimerLib.inf + +[LibraryClasses.Common.DXE_DRIVER] + PlatformSocLib|TurinBoard/Library/DxePlatformSocLib/DxePlatformSocLib.inf + # MinPlatformPkg + TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/DxeTestPointLib.inf + + !if gAmdPlatformPkgTokenSpaceGuid.PcdRomArmorEnable == TRUE + SpiHcPlatformLib|TurinBoard/Library/SpiHcRomArmorPlatformLib/SpiHcPlatformLibDxe.inf + !else + SpiHcPlatformLib|AmdPlatformPkg/Library/SpiHcPlatformLib/SpiHcPlatformLibDxe.inf + !endif + + !if $(TARGET) == DEBUG + TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/DxeTestPointCheckLib.inf + !endif + + # IPMI Library for invoking IPMI protocol + IpmiLib|MdeModulePkg/Library/DxeIpmiLibIpmiProtocol/DxeIpmiLibIpmiProtocol.inf + +[LibraryClasses.Common.DXE_CORE, LibraryClasses.Common.DXE_DRIVER, LibraryClasses.Common.DXE_SMM_DRIVER] + # MinPlatformPkg + BoardBootManagerLib|BoardModulePkg/Library/BoardBootManagerLib/BoardBootManagerLib.inf + BoardBdsHookLib|AmdMinBoardPkg/Library/BoardBdsHookLib/BoardBdsHookLib.inf + +[LibraryClasses.Common.DXE_SMM_DRIVER] + # EDKII Generic + !if $(RUNTIME_LOGGING_ENABLE) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + !else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + !endif + TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/SmmTestPointLib.inf + !if $(TARGET) == DEBUG + TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/SmmTestPointCheckLib.inf + !endif + + # AMD Platform + AmdPspFlashAccLib|AgesaPkg/Addendum/Psp/AmdPspFlashAccSpiNorLibSmm/AmdPspFlashAccSpiNorLibSmm.inf + PlatformPspRomArmorWhitelistLib|AgesaPkg/Addendum/Psp/PspRomArmorWhitelistLib/PspRomArmorWhitelistLib.inf + + !if gAmdPlatformPkgTokenSpaceGuid.PcdRomArmorEnable == TRUE + SpiHcPlatformLib|TurinBoard/Library/SpiHcRomArmorPlatformLib/SpiHcPlatformLibSmm.inf + !else + SpiHcPlatformLib|AmdPlatformPkg/Library/SpiHcPlatformLib/SpiHcPlatformLibSmm.inf + !endif +[LibraryClasses.Common.SMM_CORE] + # EDKII Generic + !if $(RUNTIME_LOGGING_ENABLE) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + !else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + !endif + +[LibraryClasses.Common.DXE_RUNTIME_DRIVER] + PciSegmentLib|MdePkg/Library/PciSegmentLibSegmentInfo/DxeRuntimePciSegmentLibSegmentInfo.inf + + !if $(RUNTIME_LOGGING_ENABLE) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + !else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + !endif + +[Components.IA32] + !include MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc + + # AGESA + AgesaPkg/Addendum/PciSegments/PciExpressPciCfg2/PciExpressPciCfg2.inf { + + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + } + + # AGESA FCH Platform initialization + !if $(EMULATION) == FALSE + TurinBoard/Universal/FchPlatformInitPei/FchPlatformInitPei.inf + !endif + + # EDKII Generic + # SEC Core + UefiCpuPkg/SecCore/SecCore.inf { + + SecBoardInitLib|MinPlatformPkg/PlatformInit/Library/SecBoardInitLibNull/SecBoardInitLibNull.inf + } + + # PEIM + MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf { + + !if $(LOGGING_ENABLE) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + !else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + !endif + } + MdeModulePkg/Universal/PcatSingleSegmentPciCfg2Pei/PcatSingleSegmentPciCfg2Pei.inf { + + NULL|AmdPlatformPkg/Library/BaseAlwaysFalseDepexLib/BaseAlwaysFalseDepexLib.inf + } + + # MinPlatformPkg + MinPlatformPkg/PlatformInit/ReportFv/ReportFvPei.inf + MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf { + + BoardInitLib|AmdMinBoardPkg/Library/PeiBoardInitPreMemLib/PeiBoardInitPreMemLib.inf + } + MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf { + + BoardInitLib|MinPlatformPkg/PlatformInit/Library/BoardInitLibNull/BoardInitLibNull.inf + } + !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE + MinPlatformPkg/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf + !endif + + # AMD Platform + !if $(PREDEFINED_FABRIC_RESOURCES) == TRUE + $(PROCESSOR_PATH)/Universal/DfResourcesPei/DfResourcesPei.inf + !endif + +[Components.X64] + !include MinPlatformPkg/Include/Dsc/CoreDxeInclude.dsc + + # CPM + AgesaModulePkg/Universal/AmdAutoDynamicCommand/BRH/AmdAutoDynamicCommand.inf { + + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + } + AgesaModulePkg/Universal/AmdAutoDynamicCommand/BRH/AmdAutoToolApp.inf + AmdCpmPkg/Addendum/Oem/$(PLATFORM_CRB)/Dxe/PspPlatformDriver/PspPlatform.inf + + # MinPlatformPkg + MinPlatformPkg/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf { + + BoardInitLib|AmdMinBoardPkg/Library/DxeBoardInitLib/DxeBoardInitLib.inf + } + BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf { + + NULL|AmdPlatformPkg/Library/AmdBdsBootConfigLib/AmdBdsBootConfigLib.inf + } + MinPlatformPkg/Test/TestPointDumpApp/TestPointDumpApp.inf + MinPlatformPkg/Test/TestPointStubDxe/TestPointStubDxe.inf + + # EDKII Generic + UefiCpuPkg/CpuDxe/CpuDxe.inf + MdeModulePkg/Universal/SectionExtractionDxe/SectionExtractionDxe.inf + !if $(SOURCE_DEBUG_ENABLE) + SourceLevelDebugPkg/DebugAgentDxe/DebugAgentDxe.inf { + + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf + } + !endif + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + + # USB + !if $(USB_SUPPORT) + MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf + !endif + + # NVME + !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE && $(NVME_SUPPORT) == TRUE + MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + !endif + + # SATA + !if $(SATA_SUPPORT) + MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf + MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf + !endif + + # SMM + UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf { + + MmSaveStateLib|UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveStateLib.inf + SmmCpuFeaturesLib|UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf + SmmCpuPlatformHookLib|UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCpuPlatformHookLibNull.inf + !if $(LOGGING_ENABLE) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + !else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + !endif + !if $(SOURCE_DEBUG_ENABLE) + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SmmDebugAgentLib.inf + !endif + + # + # Disable DEBUG_CACHE because SMI entry/exit may change MTRRs + # + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x801000C7 + } + + MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf { + + # AMD Platform SMM Core hook + SmmCorePlatformHookLib|AmdPlatformPkg/Library/SmmCorePlatformHookLib/SmmCorePlatformHookLib.inf + # SMM core hook for SPI host controller + NULL|AmdPlatformPkg/Library/SmmCoreAmdSpiHcHookLib/SmmCoreAmdSpiHcHookLib.inf + } + + # File System Modules + !if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE + MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf + !endif + + # EFI Shell + ShellPkg/Application/Shell/Shell.inf { + + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewCommandLib.inf + ## NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + + + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|16000 + } + + # Security + !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE + MinPlatformPkg/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf { + + TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.inf + } + UefiCpuPkg/MicrocodeMeasurementDxe/MicrocodeMeasurementDxe.inf + MdeModulePkg/Universal/SmbiosMeasurementDxe/SmbiosMeasurementDxe.inf + !endif + + !if $(USE_EMULATED_VARIABLE_STORE) == TRUE + # these modules are included in MinPlatformPkg in + # edk2-platforms\Platform\Intel\MinPlatformPkg\Include\Dsc\CoreDxeInclude.dsc + # removing these modules being loaded by adding depex condition which is + # always false + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf { + + NULL|AmdPlatformPkg/Library/BaseAlwaysFalseDepexLib/BaseAlwaysFalseDepexLib.inf + } + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.inf { + + NULL|AmdPlatformPkg/Library/BaseAlwaysFalseDepexLib/BaseAlwaysFalseDepexLib.inf + } + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf { + + NULL|AmdPlatformPkg/Library/BaseAlwaysFalseDepexLib/BaseAlwaysFalseDepexLib.inf + } + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { + + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE + } + # emulation bios uses emulated variable store + # hence turning off the variable protection feature + AmdCpmPkg/Features/AmdVariableProtection/AmdVariableProtection.inf { + + NULL|AmdPlatformPkg/Library/BaseAlwaysFalseDepexLib/BaseAlwaysFalseDepexLib.inf + } + !else + !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 4 + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + !endif + !endif + + !if $(SIMNOW_SUPPORT) == FALSE || $(EMULATION) == FALSE + Drivers/ASpeed/ASpeedGopBinPkg/ASpeedAst2600GopDxe.inf + !endif + + # ACPI + !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE + MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf + $(PROCESSOR_PATH)/Universal/BoardAcpiDxe/BoardAcpiDxe.inf + AmdPlatformPkg/Universal/Acpi/AcpiCommon/AcpiCommon.inf + !endif + + # SPI + MdeModulePkg/Bus/Spi/SpiHc/SpiHcDxe.inf + MdeModulePkg/Bus/Spi/SpiBus/SpiBusDxe.inf + AmdPlatformPkg/Universal/Spi/BoardSpiConfig/BoardSpiConfigDxe.inf + + !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE && $(USE_EMULATED_VARIABLE_STORE) == FALSE + AmdPlatformPkg/Universal/Spi/BoardSpiConfig/BoardSpiConfigSmm.inf + MdeModulePkg/Bus/Spi/SpiHc/SpiHcSmm.inf + MdeModulePkg/Bus/Spi/SpiBus/SpiBusSmm.inf + MdeModulePkg/Bus/Spi/SpiNorFlashJedecSfdp/SpiNorFlashJedecSfdpSmm.inf + AmdPlatformPkg/Universal/Spi/AmdSpiFvb/AmdSpiFvbSmm.inf + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmmDxe.inf + AmdPlatformPkg/Universal/Spi/EspiNorFlash/EspiNorFlashSmm.inf + !else + AmdPlatformPkg/Universal/Spi/AmdSpiFvb/AmdSpiFvbDxe.inf + !endif + + # HII + AmdPlatformPkg/Universal/HiiConfigRouting/AmdConfigRouting.inf + + # LOGO + AmdPlatformPkg/Universal/LogoDxe/LogoDxe.inf + + # PCI HotPlug + !if gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport == TRUE + AmdMinBoardPkg/PciHotPlug/PciHotPlugInit.inf + AmdCpmPkg/Addendum/Oem/$(PLATFORM_CRB)/Dxe/ServerHotplugDxe/ServerHotplugDxe.inf + !endif + + !if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable == TRUE + AmdPlatformPkg/Universal/SecureBoot/SecureBootDefaultKeysInit/SecureBootDefaultKeysInit.inf + !endif + + # Turn off post package repair for emulation + !if $(EMULATION) == TRUE + AgesaModulePkg/Mem/AmdMemPprSmmDriver/AmdMemPprSmmDriver.inf { + + NULL|AmdPlatformPkg/Library/BaseAlwaysFalseDepexLib/BaseAlwaysFalseDepexLib.inf + } + EmulationToolsPkg/EmuLinuxLoader/EmuLinuxLoader.inf + !endif + + !include ManageabilityPkg/Include/Manageability.dsc + ManageabilityPkg/Universal/IpmiProtocol/Dxe/IpmiProtocolDxe.inf { + + ManageabilityTransportLib|ManageabilityPkg/Library/ManageabilityTransportKcsLib/Dxe/DxeManageabilityTransportKcs.inf + } + + # + # edk2 Redfish foundation + # +!if $(REDFISH_ENABLE) == TRUE + !include RedfishPkg/RedfishComponents.dsc.inc +!endif + + # + # USB Network (Communication Device Class) drivers + # +!if $(USB_NETWORK_SUPPORT) == TRUE + MdeModulePkg/Bus/Usb/UsbNetwork/NetworkCommon/NetworkCommon.inf + MdeModulePkg/Bus/Usb/UsbNetwork/UsbCdcEcm/UsbCdcEcm.inf +!endif + +!if $(SIMNOW_SUPPORT) == FALSE && $(EMULATION) == FALSE + AmdCpmPkg/Addendum/Oem/OobPprDxe/OobPprDxe.inf +!endif + + # + ##For AMD PRM Feature Support## + # + + # + # PRM Libraries + # + PrmPkg/Library/DxePrmContextBufferLib/DxePrmContextBufferLib.inf + + # + # PRM Module Discovery Library + # + PrmPkg/Library/DxePrmModuleDiscoveryLib/DxePrmModuleDiscoveryLib.inf + + # + # PRM PE/COFF Library + # + PrmPkg/Library/DxePrmPeCoffLib/DxePrmPeCoffLib.inf + + # + # PRM Module Loader Driver + # + PrmPkg/PrmLoaderDxe/PrmLoaderDxe.inf + + # + # AMD DICE Protection Environment driver + # + AgesaPkg/Addendum/Psp/AmdPspDpeDxe/AmdPspDpeDxe.inf + + # Adds secure boot dependency to AmdVariableProtection feature + !if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable == FALSE + AmdCpmPkg/Features/AmdVariableProtection/AmdVariableProtection.inf { + + NULL|AmdPlatformPkg/Library/BaseAlwaysFalseDepexLib/BaseAlwaysFalseDepexLib.inf + } + !endif + +[LibraryClasses.common.DXE_DRIVER, LibraryClasses.common.DXE_RUNTIME_DRIVER, LibraryClasses.common.UEFI_APPLICATION] + # + # PRM Package + # + PrmContextBufferLib|PrmPkg/Library/DxePrmContextBufferLib/DxePrmContextBufferLib.inf + PrmModuleDiscoveryLib|PrmPkg/Library/DxePrmModuleDiscoveryLib/DxePrmModuleDiscoveryLib.inf + PrmPeCoffLib|PrmPkg/Library/DxePrmPeCoffLib/DxePrmPeCoffLib.inf + +[LibraryClasses.common.DXE_SMM_DRIVER,LibraryClasses.common.SMM_CORE] + PciExpressLib|MdePkg/Library/SmmPciExpressLib/SmmPciExpressLib.inf + +[BuildOptions] + GCC:*_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES + INTEL:*_*_*_CC_FLAGS = /D DISABLE_NEW_DEPRECATED_INTERFACES + MSFT:*_*_*_CC_FLAGS = /D DISABLE_NEW_DEPRECATED_INTERFACES + + GCC:*_*_*_CC_FLAGS = -D USE_EDKII_HEADER_FILE + + # Turn off DEBUG messages for Release Builds + GCC:RELEASE_*_*_CC_FLAGS = -D MDEPKG_NDEBUG + INTEL:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG + MSFT:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG + + !ifdef $(INTERNAL_IDS) + GCC:*_*_*_CC_FLAGS = -DINTERNAL_IDS + INTEL:*_*_*_CC_FLAGS = /D INTERNAL_IDS + MSFT:*_*_*_CC_FLAGS = /D INTERNAL_IDS + MSFT:*_*_*_VFRPP_FLAGS = /D INTERNAL_IDS + MSFT:*_*_*_ASLCC_FLAGS = /D INTERNAL_IDS + MSFT:*_*_*_ASLPP_FLAGS = /D INTERNAL_IDS + MSFT:*_*_*_PP_FLAGS = /D INTERNAL_IDS + MSFT:*_*_*_APP_FLAGS = /D INTERNAL_IDS + !endif + + !if $(EMULATION) == TRUE + GCC:*_*_*_CC_FLAGS = -D IDSOPT_PRESILICON_ENABLED=1 + INTEL:*_*_*_CC_FLAGS = /D IDSOPT_PRESILICON_ENABLED=1 + MSFT:*_*_*_CC_FLAGS = /D IDSOPT_PRESILICON_ENABLED=1 + !endif + +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER, BuildOptions.common.EDKII.DXE_SMM_DRIVER, BuildOptions.common.EDKII.SMM_CORE] + #Force modules to 4K alignment + MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096 + GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000 + +[BuildOptions.common.EDKII.DXE_DRIVER, BuildOptions.common.EDKII.DXE_CORE, BuildOptions.common.EDKII.UEFI_DRIVER] + #Force modules to 4K alignment + MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096 + GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000 + diff --git a/Platform/AMD/TurinBoard/Include/Fdf/FlashMapInclude.fdf b/Platform/AMD/TurinBoard/Include/Fdf/FlashMapInclude.fdf new file mode 100644 index 0000000000..d6aa98d7cf --- /dev/null +++ b/Platform/AMD/TurinBoard/Include/Fdf/FlashMapInclude.fdf @@ -0,0 +1,229 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All rights reserved. +#; +#;***************************************************************************** + + +############################################################################## +# +# Turin reference board - 2 SPI FLash devices accessible by x86 (selected by DIP-switch): +# 1) 32MB Flash with 10-pin header next to the VGA connector. +# 2) 64MB Flash with 10-pin header at 90-degrees from VGA connector, and also accessible by the BMC. +# +################################################################################ + +################################################################################ +# +# BIOS image layout +# +################################################################################ +### Flash layout, 16MB and 32MB iamge size with ROM3_FLASH_ENABLE = FALSE +################################################################################ +# Start End Size FV Name +################################################################################ +# 0x00000000 0x0001ffff 0x00020000 None Unused +# 0x00020000 0x00020fff 0x00001000 DATA EFS +# 0x00021000 0x0005efff 0x0003e000 DATA NVRAM +# 0x0005f000 0x0005ffff 0x00001000 DATA NVRAM FTW +# 0x00060000 0x000a0fff 0x00041000 None NVRAM Reserved +# 0x000a1000 0x002e2fff 0x00242000 None PSPDirectory +# 0x002e3000 0x0033efff 0x0005c000 None BIOSDirectory +# 0x0033f000 0x005adfff 0x0026f000 None PSPDirectory +# 0x005ae000 0x006fffff 0x00152000 None BIOSDirectory +# 0x00700000 0x007d7fff 0x000d8000 FV FVADVANCED +# 0x007d8000 0x0085ffff 0x00088000 FV FVADVANCEDSECURITY +# 0x00860000 0x0090dfff 0x000ae000 FV FVOSBOOT +# 0x0090e000 0x00bfbfff 0x002ee000 FV FVUEFIBOOT +# 0x00bfc000 0x00c27fff 0x0002c000 FV FVSECURITY +# 0x00c28000 0x00c37fff 0x00010000 FV FVPOSTMEMORY +# 0x00c38000 0x00c3ffff 0x00008000 FV FVADVANCEDPREMEMORY +# 0x00c40000 0x00ffffff 0x003c0000 FV FVPREMEMORY +################################################################################ +# Extra padding for 32MB image size +# 0x01000000 0x01ffffff 0x01000000 None unused +################################################################################ +### Flash layout, 32MB with ROM3_FLASH_ENABLE = TRUE +################################################################################ +# Start End Size FV Name +################################################################################ +# 0x00000000 0x0001ffff 0x00020000 None Unused +# 0x00020000 0x00020fff 0x00001000 DATA EFS +# 0x00021000 0x0005efff 0x0003e000 DATA NVRAM +# 0x0005f000 0x0005ffff 0x00001000 DATA NVRAM FTW +# 0x00060000 0x000a0fff 0x00041000 None NVRAM Reserved +# 0x000a1000 0x002e2fff 0x00242000 None PSPDirectory +# 0x002e3000 0x0033efff 0x0005c000 None BIOSDirectory +# 0x0033f000 0x005adfff 0x0026f000 None PSPDirectory +# 0x005ae000 0x006fffff 0x00152000 None BIOSDirectory +# 0x00bec000 0x00c17fff 0x0002c000 FV FVSECURITY +# 0x00c18000 0x00c37fff 0x00020000 FV FVPOSTMEMORY +# 0x00c38000 0x00c3ffff 0x00008000 FV FVADVANCEDPREMEMORY +# 0x00c40000 0x00ffffff 0x003c0000 FV FVPREMEMORY +# 0x01000000 0x010d7fff 0x000d8000 FV FVADVANCED +# 0x010d8000 0x0115ffff 0x00088000 FV FVADVANCEDSECURITY +# 0x01160000 0x0120dfff 0x000ae000 FV FVOSBOOT +# 0x0120e000 0x014fbfff 0x002ee000 FV FVUEFIBOOT +# 0x01fff000 0x01ffffff 0x00001000 None Unused +################################################################################ + + DEFINE ROM2_FLASH_BASE = 0xFF000000 + DEFINE ROM2_FLASH_SIZE = 0x01000000 + DEFINE ROM3_FLASH_SIZE = 0x02000000 + DEFINE SPI_BLOCK_SIZE = 0x1000 + + !ifndef BUILD_16MB_IMAGE + DEFINE BUILD_16MB_IMAGE = FALSE + !endif + !ifndef ROM3_FLASH_ENABLE + DEFINE ROM3_FLASH_ENABLE = FALSE + !endif + !ifndef ROM3_FLASH_BASE + DEFINE ROM3_FLASH_BASE = 0xFD02000000 + !endif + + !if $(BUILD_16MB_IMAGE) == TRUE + DEFINE SPI_NUM_BLOCKS = 0x1000 + !else + DEFINE SPI_NUM_BLOCKS = 0x2000 + !endif + !if ($(ROM3_FLASH_ENABLE) == TRUE) && ($(BUILD_16MB_IMAGE) == TRUE) + !error "ROM3 cannot be enabled on 16MB image" + !endif + + !ifndef FV_PRE_MEMORY_SIZE + # requires changes in PspData also + DEFINE FV_PRE_MEMORY_SIZE = 0x003C0000 + !endif + !ifndef FV_ADVANCED_PRE_MEMORY_SIZE + DEFINE FV_ADVANCED_PRE_MEMORY_SIZE = 0x00008000 + !endif + !ifndef FV_POST_MEMORY_SIZE + !if ($(ROM3_FLASH_ENABLE) == TRUE) + # Need extra space for DxeMain + DEFINE FV_POST_MEMORY_SIZE = 0x00020000 + !else + DEFINE FV_POST_MEMORY_SIZE = 0x00010000 + !endif + !endif + !ifndef FV_SECURITY_SIZE + DEFINE FV_SECURITY_SIZE = 0x0002C000 + !endif + !ifndef FV_UEFI_BOOT_SIZE + DEFINE FV_UEFI_BOOT_SIZE = 0x002EE000 + !endif + !ifndef FV_OS_BOOT_SIZE + DEFINE FV_OS_BOOT_SIZE = 0x000AE000 + !endif + !ifndef FV_ADVANCED_SECURITY_SIZE + DEFINE FV_ADVANCED_SECURITY_SIZE = 0x00088000 + !endif + !ifndef FV_ADVANCED_SIZE + DEFINE FV_ADVANCED_SIZE = 0x000D8000 + !endif + + DEFINE FV_FW_SIG_OFFSET = 0x00020000 + DEFINE FV_FW_SIG_SIZE = 0x00001000 + + DEFINE NVRAM_AREA_VAR_OFFSET = 0x00021000 + DEFINE NVRAM_AREA_VAR_SIZE = 0x0003E000 + DEFINE NVRAM_AREA_SIZE = 0x00080000 + + DEFINE FTW_WORKING_OFFSET = $(NVRAM_AREA_VAR_OFFSET) + $(NVRAM_AREA_VAR_SIZE) + DEFINE FTW_WORKING_SIZE = $(SPI_BLOCK_SIZE) + + DEFINE FTW_SPARE_OFFSET = $(FTW_WORKING_OFFSET) + $(FTW_WORKING_SIZE) + DEFINE FTW_SPARE_SIZE = $(NVRAM_AREA_SIZE) - $(NVRAM_AREA_VAR_SIZE) - $(FTW_WORKING_SIZE) +# NOTE: +# +# BOOT_FV_BASE value should match with the PspData.xml ResetImage address +# e.g. +# +# +# +# +# Also note that C40000 from 0x76C40000 came from PcdFlashFvPreMemoryOffset +# if PcdFlashFvPreMemoryOffset gets changed then the below value should also +# need to be change. +# +!ifndef BOOT_FV_BASE + DEFINE BOOT_FV_BASE = 0x76C40000 +!endif + +SET gEfiAmdAgesaPkgTokenSpaceGuid.PcdAgesaFlashNvStorageBlockSize = $(SPI_BLOCK_SIZE) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress = 0xFF000000 +SET gEfiAmdAgesaPkgTokenSpaceGuid.PcdAgesaFlashAreaBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress + +# SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset = 0x00000000 +# SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize = 0x00040000 +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset = $(NVRAM_AREA_VAR_OFFSET) +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize = $(NVRAM_AREA_VAR_SIZE) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset = $(FTW_WORKING_OFFSET) +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize = $(FTW_WORKING_SIZE) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset = $(FTW_SPARE_OFFSET) +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize = $(FTW_SPARE_SIZE) + +# +# FV offset and size assignment +# +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize = $(FV_PRE_MEMORY_SIZE) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset = ($(ROM2_FLASH_SIZE) - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize) + +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize = $(FV_ADVANCED_PRE_MEMORY_SIZE) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryOffset = (gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize) + +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize = $(FV_POST_MEMORY_SIZE) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset = (gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryOffset - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize) + +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize = $(FV_SECURITY_SIZE) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize + +!if $(ROM3_FLASH_ENABLE) == FALSE + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize = $(FV_UEFI_BOOT_SIZE) + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset = (gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize) + + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize = $(FV_OS_BOOT_SIZE) + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset = (gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize) + + SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecuritySize = $(FV_ADVANCED_SECURITY_SIZE) + SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityOffset = (gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset - gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecuritySize) + + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize = $(FV_ADVANCED_SIZE) + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset = (gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityOffset - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize) + # NOTE: + # for ROM3_FLASH_ENABLE disabled BIOS image max address (PcdFlashFvAdvancedSize + PcdFlashFvAdvancedOffset) + # should not overlap with BIOS DIR2 offset + size in PspData.xml + # e.g + # + # +!endif + +!if $(ROM3_FLASH_ENABLE) == TRUE + # if ROM3 is enabled then continue the offset update + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset = $(ROM2_FLASH_SIZE) + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize = $(FV_ADVANCED_SIZE) + + SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityOffset = (gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize) + SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecuritySize = $(FV_ADVANCED_SECURITY_SIZE) + + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset = (gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityOffset + gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecuritySize) + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize = $(FV_OS_BOOT_SIZE) + + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset = (gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize) + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize = $(FV_UEFI_BOOT_SIZE) + # NOTE: + # for ROM3_FLASH_ENABLE enabled BIOS image max address (PcdFlashFvSecuritySize + PcdFlashFvSecurityOffset) + # should not overlap with BIOS DIR2 offset + size in PspData.xml + # e.g + # +!endif + +SET gAmdMinBoardPkgTokenSpaceGuid.PcdBootFvBase = $(BOOT_FV_BASE) + +!if $(ROM3_FLASH_ENABLE) == TRUE + SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedBase = $(ROM3_FLASH_BASE) + SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityBase = (gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize) + SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvOsBootBase = (gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityBase + gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecuritySize) + SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvUefiBootBase = (gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvOsBootBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize) +!endif + + diff --git a/Platform/AMD/TurinBoard/Include/Fdf/Platform.inc.fdf b/Platform/AMD/TurinBoard/Include/Fdf/Platform.inc.fdf new file mode 100644 index 0000000000..d469fcf5dc --- /dev/null +++ b/Platform/AMD/TurinBoard/Include/Fdf/Platform.inc.fdf @@ -0,0 +1,17 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All rights reserved. +#; +#;***************************************************************************** + +!ifdef $(INTERNAL_IDS) + DEFINE AGESA_PEI_INC_FDF = $(PROCESSOR_PATH)/Include/AgesaInc/AgesaInt.pei.inc.fdf + DEFINE AGESA_DXE_INC_FDF = $(PROCESSOR_PATH)/Include/AgesaInc/AgesaInt.dxe.inc.fdf +!else + DEFINE AGESA_PEI_INC_FDF = $(PROCESSOR_PATH)/Include/AgesaInc/AgesaExt.pei.inc.fdf + DEFINE AGESA_DXE_INC_FDF = $(PROCESSOR_PATH)/Include/AgesaInc/AgesaExt.dxe.inc.fdf +!endif +!ifndef CPM_DIR_PATH + CPM_DIR_PATH = $(AMD_PROCESSOR)/AmdCpm$(AMD_PROCESSOR) +!endif +DEFINE CPM_PEI_INC_FDF = AmdCpmPkg/Addendum/Oem/$(PLATFORM_CRB)/Processor/$(CPM_DIR_PATH)$(PLATFORM_CRB)Pkg.pei.inc.fdf +DEFINE CPM_DXE_INC_FDF = AmdCpmPkg/Addendum/Oem/$(PLATFORM_CRB)/Processor/$(CPM_DIR_PATH)$(PLATFORM_CRB)Pkg.dxe.inc.fdf diff --git a/Platform/AMD/TurinBoard/Include/Fdf/PlatformEfs.inc.fdf b/Platform/AMD/TurinBoard/Include/Fdf/PlatformEfs.inc.fdf new file mode 100644 index 0000000000..2adbecf6c1 --- /dev/null +++ b/Platform/AMD/TurinBoard/Include/Fdf/PlatformEfs.inc.fdf @@ -0,0 +1,5 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All rights reserved. +#; +#;***************************************************************************** + diff --git a/Platform/AMD/TurinBoard/Include/Fdf/ProjectCommon.inc.fdf b/Platform/AMD/TurinBoard/Include/Fdf/ProjectCommon.inc.fdf new file mode 100644 index 0000000000..2ba0db86ab --- /dev/null +++ b/Platform/AMD/TurinBoard/Include/Fdf/ProjectCommon.inc.fdf @@ -0,0 +1,905 @@ +#;***************************************************************************** +#; Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. +#; +#;***************************************************************************** + +# EFS multi gen is 32bit value +!ifndef EFS_MULTI_GEN_BYTE0 + DEFINE EFS_MULTI_GEN_BYTE0 = 0xE3 +!endif + +# EFS PSP address, 32-bit value, 0x000A1000 +!ifndef EFS_PSP_ADDR_BYTE0 + DEFINE EFS_PSP_ADDR_BYTE0 = 0x00 +!endif +!ifndef EFS_PSP_ADDR_BYTE1 + DEFINE EFS_PSP_ADDR_BYTE1 = 0x10 +!endif +!ifndef EFS_PSP_ADDR_BYTE2 + DEFINE EFS_PSP_ADDR_BYTE2 = 0x0A +!endif +!ifndef EFS_PSP_ADDR_BYTE3 + DEFINE EFS_PSP_ADDR_BYTE3 = 0x00 +!endif + +# EFS BIOS address, 32-bit value, 0x002E3000 +!ifndef EFS_BIOS_ADDR_BYTE0 + DEFINE EFS_BIOS_ADDR_BYTE0 = 0x00 +!endif +!ifndef EFS_BIOS_ADDR_BYTE1 + DEFINE EFS_BIOS_ADDR_BYTE1 = 0x30 +!endif +!ifndef EFS_BIOS_ADDR_BYTE2 + DEFINE EFS_BIOS_ADDR_BYTE2 = 0x2E +!endif +!ifndef EFS_BIOS_ADDR_BYTE3 + DEFINE EFS_BIOS_ADDR_BYTE3 = 0x00 +!endif + +# EFS ESPI defination +!ifndef EFS_ESPI_BYTE0 + DEFINE EFS_ESPI_BYTE0 = 0x0E +!endif +!ifndef EFS_ESPI_BYTE1 + DEFINE EFS_ESPI_BYTE1 = 0xFF +!endif + +[FD.Platform] + # Need ROM 2 flash base for calculated Addresses of FVs below 4GB + BaseAddress = $(ROM2_FLASH_BASE)|gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress + # Need full flash size for FD Image size + !if $(BUILD_16MB_IMAGE) == TRUE + Size = $(ROM2_FLASH_SIZE) + !else + Size = $(ROM3_FLASH_SIZE) + !endif + ErasePolarity = 1 + BlockSize = $(SPI_BLOCK_SIZE) + NumBlocks = $(SPI_NUM_BLOCKS) + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = $(ROM2_FLASH_SIZE) + SET gAmdPlatformPkgTokenSpaceGuid.PcdRom3FlashAreaBase = $(ROM3_FLASH_BASE) + SET gAmdPlatformPkgTokenSpaceGuid.PcdRom3FlashAreaSize = $(ROM3_FLASH_SIZE) + + # + # Embedded Firmware Signature + # + $(FV_FW_SIG_OFFSET)|$(FV_FW_SIG_SIZE) +!ifdef EMBEDDED_FIRMWARE_SIGNATURE + !include $(PROCESSOR_PATH)/Include/Fdf/PlatformEfs.inc.fdf +!else + DATA = { + 0xAA, 0x55, 0xAA, 0x55, # 0x00: Signature + 0x00, 0x00, 0x00, 0x00, # + 0x00, 0x00, 0x00, 0x00, # + 0x00, 0x00, 0x00, 0x00, # + 0x00, 0x00, 0x00, 0x00, # + $(EFS_PSP_ADDR_BYTE0), # + $(EFS_PSP_ADDR_BYTE1), # + $(EFS_PSP_ADDR_BYTE2), # + $(EFS_PSP_ADDR_BYTE3), # 0x14: PSP Dir1 + 0x00, 0x00, 0x00, 0x00, # + 0x00, 0x00, 0x00, 0x00, # + 0x00, 0x00, 0x00, 0x00, # + $(EFS_MULTI_GEN_BYTE0), # + 0xFF, 0xFF, 0xFF, # 0x24: BRH 4:0 as 00011b + $(EFS_BIOS_ADDR_BYTE0), # + $(EFS_BIOS_ADDR_BYTE1), # + $(EFS_BIOS_ADDR_BYTE2), # + $(EFS_BIOS_ADDR_BYTE3), # 0x28: BIOS Dir1 + 0x00, 0x00, 0x00, 0x00, # + 0x00, 0x00, 0x00, 0x00, # + 0x00, 0x00, 0x00, 0x00, # + 0x00, 0x00, 0x00, 0x00, # + 0x00, 0x00, 0x00, 0x00, # + 0x00, 0x00, 0x00, 0x00, # 0x40 + 0xFF, 0xFF, 0xFF, 0xFF, # + 0xFF, 0xFF, 0xFF, 0xFF, # + 0x00, 0x00, 0x00, 0x00, # + $(EFS_ESPI_BYTE0), # + $(EFS_ESPI_BYTE1), # + 0xFF, 0xFF # 0x50: eSPI0 Configuration + # Default value = 0x0E (eSPI0, bus1, Alert mode, Port 80h, CLK1) + # + # bit[0]: eSPI PSP configuration valid bit. + # 0-Valid, 1-Not Valid + # bit[1]: enable 80h port. + # 0-disable, 1-enable + # bit[2]: Alert mode. + # 0-non-Alert, 1-dedicated Alert Pin. + # bit[3]: Data Bus, + # 0-bus0, 1-bus1. + # bit[4]: Clock pin. ignore for controller0 (always CLK0). + # for controller1, 0-CLK1, 1-CLK2 + # bit[7:5]: reserved + # 0x51: eSPI1 Configuration + # bit[0]: eSPI PSP configuration valid bit. + # 0-Valid, 1-Not Valid + # bit[1]: enable 80h port. + # 0-disable, 1-enable + # bit[2]: Alert mode. + # 0-non-Alert, 1-dedicated Alert Pin. + # bit[3]: Data Bus, + # 0-bus0, 1-bus1. + # bit[4]: Clock pin. ignore for controller0 (always CLK0). + # for controller1, 0-CLK1, 1-CLK2 + # bit[7:5]: reserved + } +!endif + # + # PSP NVRAM: NV Storage Area + # NV_VARIABLE_STORE + # + gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + DATA = { + ## This is the EFI_FIRMWARE_VOLUME_HEADER + # ZeroVector [] + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + # FileSystemGuid: gEfiSystemNvDataFvGuid = + # { 0xFFF12B8D, 0x7696, 0x4C8B, + # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }} + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, + # FvLength: 0x80000 + 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, + # Signature "_FVH" # Attributes + 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00, + # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision + 0x48, 0x00, 0x19, 0xF9, 0x00, 0x00, 0x00, 0x02, + # Blockmap[0]: 0x80 Blocks * 0x1000 Bytes / Block + 0x80, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, + # Blockmap[1]: End (null-terminated) + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + ## This is the VARIABLE_STORE_HEADER + !if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable == TRUE + # Signature: gEfiAuthenticatedVariableGuid = + # { 0xaaf32c78, 0x947b, 0x439a, + # { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }} + 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43, + 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92, + !else + # Signature: gEfiVariableGuid = + # { 0xddcf3616, 0x3275, 0x4164, + # { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }} + 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41, + 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d, + !endif + # Size: 0x3E000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - + # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x3DFB8 + # This can speed up the Variable Dispatch a bit. + 0xB8, 0xDF, 0x03, 0x00, + # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + } + + # + # NV_FTW_WORKING + # + gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize + DATA = { + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid = + # { 0x9e58292b, 0x7c68, 0x497d, + # { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }} + 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49, + 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95, + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved + 0x2C, 0xAF, 0x2C, 0x64, 0xFE, 0xFF, 0xFF, 0xFF, + # WriteQueueSize: UINT64 #Size: 0x1000(SPI_BLOCK_SIZE) - 0x20 (FTW_WORKING_HEADER) = 0x0FE0 + 0xE0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + } + + # + # NV_FTW_SPARE + # + gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize + + # Advance firmware volume where advance Board features are enabled. + !if $(ROM3_FLASH_ENABLE) == FALSE + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize + gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize + FV = FvAdvanced + + gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityOffset|gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecuritySize + gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityBase|gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecuritySize + FV = FvAdvancedSecurity + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize + gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvOsBootBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize + FV = FvOsBoot + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize + gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvUefiBootBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize + FV = FvUefiBoot + !endif + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize + FV = FvSecurity + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize + FV = FvPostMemory + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize + FV = FvAdvancedPreMemory + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize + FV = FvPreMemory + + !if $(ROM3_FLASH_ENABLE) == TRUE + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize + FV = FvAdvanced + + gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityOffset|gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecuritySize + FV = FvAdvancedSecurity + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize + FV = FvOsBoot + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize + FV = FvUefiBoot + + # Fill unused space to create 32 MB FD image + $(ROM3_FLASH_SIZE) - 0x1000|0x1000 + + !elseif $(BUILD_16MB_IMAGE) == FALSE + # Fill unused space to create 32 MB FD image + 0x01000000|0x01000000 + !endif + +[FV.FvPreMemory] + FvNameGuid = 1BD2AB8A-BD04-4ee1-83B0-B05E5500121D + FvBaseAddress = $(BOOT_FV_BASE) + FvForceRebase = TRUE + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + + APRIORI PEI { + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf + INF AgesaPkg/Addendum/PciSegments/PciExpressPciCfg2/PciExpressPciCfg2.inf + INF MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf + INF MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf + } + + # SEC Core + INF UefiCpuPkg/SecCore/SecCore.inf + + # PEI Core + INF MdeModulePkg/Core/Pei/PeiMain.inf + + !include MinPlatformPkg/Include/Fdf/CorePreMemoryInclude.fdf + INF AgesaPkg/Addendum/PciSegments/PciExpressPciCfg2/PciExpressPciCfg2.inf + + !if $(PREDEFINED_FABRIC_RESOURCES) == TRUE + INF $(PROCESSOR_PATH)/Universal/DfResourcesPei/DfResourcesPei.inf + !endif + + !if $(EMULATION) == FALSE + INF TurinBoard/Universal/FchPlatformInitPei/FchPlatformInitPei.inf + !endif + + # PEIM + INF MinPlatformPkg/PlatformInit/ReportFv/ReportFvPei.inf + INF MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf + # INF $(PLATFORM_BOARD_PACKAGE)/BiosInfo/BiosInfo.inf + # INF MdeModulePkg/Universal/ResetSystemPei/ResetSystemPei.inf + + # AMD AGESA, CPM PEI Includes + !include $(CPM_PEI_INC_FDF) + !include $(AGESA_PEI_INC_FDF) + +[FV.FvAdvancedPreMemory] + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = 87F76F65-4128-4B77-85D8-DE0F757B40F8 + + # !include AdvancedFeaturePkg/Include/PreMemory.fdf + +[FV.FvPostMemoryUncompact] + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = 09F55EB9-7181-4919-8755-9185E3E35CA9 + + !include MinPlatformPkg/Include/Fdf/CorePostMemoryInclude.fdf + + # Init Board Config PCD + INF MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf + +[FV.FvPostMemory] + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = 3445B977-C771-4928-9851-2EFBD55CAACD + + FILE FV_IMAGE = F38D7A3E-35F1-4CE4-ACC8-AA059ABEA622{ + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvPostMemoryUncompact + } + } + !if $(ROM3_FLASH_ENABLE) == TRUE + FILE FV_IMAGE = 8DA879CE-D6D0-4687-8025-0EA967F506BD { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvDxeMain + } + } + !endif + +[FV.FvUefiBootUncompact] + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = E889A6E3-385B-4DAF-A19A-E9B1D41EB046 + + APRIORI DXE { + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf + INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf + } + !include MinPlatformPkg/Include/Fdf/CoreUefiBootInclude.fdf + + # AMD AGESA, CPM DXE Includes + !include $(CPM_DXE_INC_FDF) + !include $(AGESA_DXE_INC_FDF) + + + # AMD PRM feature support + INF PrmPkg/PrmLoaderDxe/PrmLoaderDxe.inf + + # EDK Core modules + INF UefiCpuPkg/CpuDxe/CpuDxe.inf + INF MdeModulePkg/Universal/SectionExtractionDxe/SectionExtractionDxe.inf + !if $(SOURCE_DEBUG_ENABLE) + INF SourceLevelDebugPkg/DebugAgentDxe/DebugAgentDxe.inf + !endif + + # File System Modules + !if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE + INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf + !endif + + # Console + !if $(SIMNOW_SUPPORT) == FALSE || $(EMULATION) == FALSE + INF Drivers/ASpeed/ASpeedGopBinPkg/ASpeedAst2600GopDxe.inf + !endif + + INF AgesaModulePkg/Universal/AmdAutoDynamicCommand/BRH/AmdAutoDynamicCommand.inf + INF AgesaModulePkg/Universal/AmdAutoDynamicCommand/BRH/AmdAutoToolApp.inf + + INF AmdCpmPkg/Addendum/Oem/$(PLATFORM_CRB)/Dxe/PspPlatformDriver/PspPlatform.inf + + # UEFI Shell + !if $(SHELL_BIN_PACKAGE) + INF ShellBinPkg/UefiShell/UefiShell.inf + !else + INF ShellPkg/Application/Shell/Shell.inf + !endif + + # AmdHiiConfigRouting + INF AmdPlatformPkg/Universal/HiiConfigRouting/AmdConfigRouting.inf + + # PCI + INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + + # SATA + !if $(SATA_SUPPORT) + INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf + INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf + INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf + !endif + + # NVME + !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE && $(NVME_SUPPORT) == TRUE + INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + !endif + + # USB + !if $(USB_SUPPORT) + INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf + !endif + + # SMBIOS + INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + INF SystemInformation/SmbiosFeaturePkg/SmbiosBasicDxe/SmbiosBasicDxe.inf + INF AmdPlatformPkg/Universal/SmbiosCommonDxe/SmbiosCommonDxe.inf + + # Board + INF BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf + INF MinPlatformPkg/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf + INF MinPlatformPkg/Test/TestPointStubDxe/TestPointStubDxe.inf + + # Spi Flash Drivers + INF AmdPlatformPkg/Universal/Spi/BoardSpiConfig/BoardSpiConfigDxe.inf + INF MdeModulePkg/Bus/Spi/SpiBus/SpiBusDxe.inf + INF MdeModulePkg/Bus/Spi/SpiHc/SpiHcDxe.inf + !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE && $(USE_EMULATED_VARIABLE_STORE) == FALSE + INF AmdPlatformPkg/Universal/Spi/BoardSpiConfig/BoardSpiConfigSmm.inf + INF MdeModulePkg/Bus/Spi/SpiBus/SpiBusSmm.inf + INF MdeModulePkg/Bus/Spi/SpiHc/SpiHcSmm.inf + INF AmdPlatformPkg/Universal/Spi/AmdSpiFvb/AmdSpiFvbSmm.inf + INF MdeModulePkg/Bus/Spi/SpiNorFlashJedecSfdp/SpiNorFlashJedecSfdpSmm.inf + INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmmDxe.inf + INF AmdPlatformPkg/Universal/Spi/EspiNorFlash/EspiNorFlashSmm.inf + + !else + INF AmdPlatformPkg/Universal/Spi/AmdSpiFvb/AmdSpiFvbDxe.inf + !endif + + # SMM Modules + !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == TRUE + # putting under conditional flag to avoid loading modules again(second time). + # MinPlatformPkg already has these modules included if + # gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE + # in CoreOsBootInclude.fdf + INF MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf + INF MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf + INF MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouterSmm.inf + INF MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandlerSmm.inf + INF UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf + INF MdeModulePkg/Universal/SmmCommunicationBufferDxe/SmmCommunicationBufferDxe.inf + !endif + INF UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf + + !if $(EMULATION) == TRUE + INF EmulationToolsPkg/EmuLinuxLoader/EmuLinuxLoader.inf + !endif + + !if $(USE_EMULATED_VARIABLE_STORE) == TRUE && gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + !endif + + # + # edk2 Redfish Foundation + # +!if $(REDFISH_ENABLE) == TRUE + !include RedfishPkg/Redfish.fdf.inc +!endif + + # + # USB Network (Communication Device Class) drivers + # +!if $(USB_NETWORK_SUPPORT) == TRUE + INF MdeModulePkg/Bus/Usb/UsbNetwork/NetworkCommon/NetworkCommon.inf + INF MdeModulePkg/Bus/Usb/UsbNetwork/UsbCdcEcm/UsbCdcEcm.inf +!endif +!if $(SIMNOW_SUPPORT) == FALSE && $(EMULATION) == FALSE + INF AmdCpmPkg/Addendum/Oem/OobPprDxe/OobPprDxe.inf +!endif + + # + # DICE Protection Environment driver + # + INF AgesaPkg/Addendum/Psp/AmdPspDpeDxe/AmdPspDpeDxe.inf + +[FV.FvUefiBoot] + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = 5489442E-30C6-479F-9CA4-BAAAEE279A20 + + FILE FV_IMAGE = B5733BA8-C486-4B0F-889C-0815F483450A { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvUefiBootUncompact + } + } + +[FV.FvOsBootUncompact] + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = 48FD70BC-3389-4B90-A364-EF829F41DB70 + + !include MinPlatformPkg/Include/Fdf/CoreOsBootInclude.fdf + + !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE + INF MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf + INF RuleOverride = DRIVER_ACPITABLE $(PROCESSOR_PATH)/Universal/BoardAcpiDxe/BoardAcpiDxe.inf + INF AmdPlatformPkg/Universal/Acpi/AcpiCommon/AcpiCommon.inf + !endif + +[FV.FvLateSilicon] + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = C3740903-41CC-4C7E-B9A1-7A4B59C0CEC2 + +[FV.FvOsBoot] + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = 7E097F4E-A40F-47D4-93FB-8802BB9051C0 + + FILE FV_IMAGE = B975908C-6ECF-4413-A87A-199DDA11AB37 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvOsBootUncompact + } + } + FILE FV_IMAGE = 41077C2D-331A-4188-809A-E5278A534E51 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvLateSilicon + } + } + +[FV.FvSecurityPreMemory] + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = 87E97057-5DEF-4EB3-ACC5-063AC68AA7B7 + + !include MinPlatformPkg/Include/Fdf/CoreSecurityPreMemoryInclude.fdf + +[FV.FvSecurityPostMemory] + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = FBA1BC9C-66FD-4B05-887C-C00AB6DDEE1F + + !include MinPlatformPkg/Include/Fdf/CoreSecurityPostMemoryInclude.fdf + + !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE + INF MinPlatformPkg/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf + !endif + +[FV.FvSecurityLate] + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = 79045073-CB0E-4E28-BC31-4AE00FBF4907 + + !include MinPlatformPkg/Include/Fdf/CoreSecurityLateInclude.fdf + + !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE + !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE + INF MinPlatformPkg/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf + INF UefiCpuPkg/MicrocodeMeasurementDxe/MicrocodeMeasurementDxe.inf + INF MdeModulePkg/Universal/SmbiosMeasurementDxe/SmbiosMeasurementDxe.inf + !endif + !endif + + !if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable == TRUE + INF AmdPlatformPkg/Universal/SecureBoot/SecureBootDefaultKeysInit/SecureBootDefaultKeysInit.inf + + FILE FREEFORM = 85254ea7-4759-4fc4-82d4-5eed5fb0a4a0 { + SECTION RAW = SecurebootKeys/PK/PK.cer + } + + FILE FREEFORM = 6f64916e-9f7a-4c35-b952-cd041efb05a3 { + SECTION RAW = SecurebootKeys/KEK/MicCorKEKCA2011_2011-06-24.crt + } + + FILE FREEFORM = c491d352-7623-4843-accc-2791a7574421 { + SECTION RAW = SecurebootKeys/db/MicWinProPCA2011_2011-10-19.crt + SECTION RAW = SecurebootKeys/db/MicCorUEFCA2011_2011-06-27.crt + } + + FILE FREEFORM = 5740766a-718e-4dc0-9935-c36f7d3f884f { + SECTION RAW = SecurebootKeys/dbx/dbxupdate_x64.bin + } + + !endif + +[FV.FvSecurity] + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = 2D25F4E7-50AB-442C-B2AE-9C48F3116E62 + + !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE + FILE FV_IMAGE = 757CC075-1428-423D-A73C-22639706C119 { + SECTION FV_IMAGE = FvSecurityPreMemory + } + !endif + + FILE FV_IMAGE = 7E21EF3C-D813-40C0-BE9E-A5F739CA88AC { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvSecurityPostMemory + } + } + +[FV.FvAdvancedSecurity] + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = 2FFD72AF-4917-4430-8A46-97BD74816264 + + FILE FV_IMAGE = B431E18D-A610-4A65-8D81-A4E482354EF8 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvSecurityLate + } + } + +[FV.FvAdvancedUncompact] + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = 9DC9F824-7D1E-4A81-A410-CE3CA6ABA779 + + # Enable Manageabilty modules, such as IPMI Driver + !include ManageabilityPkg/Include/PostMemory.fdf + + # + # Network Advanced Features + # + !if gNetworkFeaturePkgTokenSpaceGuid.PcdNetworkFeatureEnable == TRUE + !include Network/NetworkFeaturePkg/Include/PostMemory.fdf + !endif + + # LOGO + INF AmdPlatformPkg/Universal/LogoDxe/LogoDxe.inf + + # PCI HotPlug + !if gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport == TRUE + INF AmdMinBoardPkg/PciHotPlug/PciHotPlugInit.inf + INF AmdCpmPkg/Addendum/Oem/$(PLATFORM_CRB)/Dxe/ServerHotplugDxe/ServerHotplugDxe.inf + !endif + + # SPCR + !if gSpcrFeaturePkgTokenSpaceGuid.PcdSpcrFeatureEnable == TRUE + !include SpcrFeaturePkg/Include/PostMemory.fdf + !endif + +[FV.FvAdvanced] + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = FC5D42FA-964F-47D5-9D53-35D997F1B83E + + FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvAdvancedUncompact + } + } + +[FV.FvDxeMain] + BlockSize = $(SPI_BLOCK_SIZE) + FvAlignment = 64 + ERASE_POLARITY = 1 + MEMORY_MAPPED = TRUE + STICKY_WRITE = TRUE + LOCK_CAP = TRUE + LOCK_STATUS = TRUE + WRITE_DISABLED_CAP = TRUE + WRITE_ENABLED_CAP = TRUE + WRITE_STATUS = TRUE + WRITE_LOCK_CAP = TRUE + WRITE_LOCK_STATUS = TRUE + READ_DISABLED_CAP = TRUE + READ_ENABLED_CAP = TRUE + READ_STATUS = TRUE + READ_LOCK_CAP = TRUE + READ_LOCK_STATUS = TRUE + FvNameGuid = AF85B2E1-DC13-445A-AF0F-C7659E39BBAC + + INF MdeModulePkg/Core/Dxe/DxeMain.inf diff --git a/Platform/AMD/TurinBoard/Library/DxePlatformSocLib/DxePlatformSocLib.c b/Platform/AMD/TurinBoard/Library/DxePlatformSocLib/DxePlatformSocLib.c new file mode 100644 index 0000000000..006076a332 --- /dev/null +++ b/Platform/AMD/TurinBoard/Library/DxePlatformSocLib/DxePlatformSocLib.c @@ -0,0 +1,937 @@ +/** @file + Implements AMD Turin Platform SoC Library. + Provides interface to Get/Set platform specific data. + + Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAX_IOAPIC_NUM 0x20 + +/** + Obtains proximity domain for given PciAddress, + provided in BDF format. + + Calls AGESA fabric service to obtain domain information. + + @param[in] SocketID - SocketID of the provided PciAddress + @param[in] PciAddress - PCI Address of the device + + @retval SocketID, if fails to get data from fabric service, else + PXM value. +**/ +UINTN +GetPxmDomain ( + IN UINT8 SocketId, + IN PCI_ADDR PciAddress + ) +{ + FABRIC_NUMA_SERVICES2_PROTOCOL *FabricNumaServices; + EFI_STATUS Status; + PXM_DOMAIN_INFO PxmDomainInfo; + + Status = gBS->LocateProtocol (&gAmdFabricNumaServices2ProtocolGuid, NULL, (VOID **)&FabricNumaServices); + if (EFI_ERROR (Status)) { + return SocketId; + } + + ZeroMem ((VOID *)&PxmDomainInfo, sizeof (PxmDomainInfo)); + Status = FabricNumaServices->GetPxmDomainInfo (FabricNumaServices, PciAddress, &PxmDomainInfo); + if (EFI_ERROR (Status)) { + return SocketId; + } + + ASSERT (PxmDomainInfo.Count == 1); + return PxmDomainInfo.Domain[0]; +} + +/** + @brief Get the PCIe CXL2 Info object + + NOTE: Caller will need to free structure once finished. + + @param[in, out] CxlPortInfo The CXL port information + @param[in, out] CxlCount Number of CXL port present + + @retval EFI_SUCCESS Successfully retrieve the CXL port information. + EFI_INVALID_PARAMETERS Incorrect parameters provided. + EFI_UNSUPPORTED Platform do not support this function. + Other value Returns other EFI_STATUS in case of failure. + +**/ +EFI_STATUS +GetPcieCxl2Info ( + IN OUT AMD_CXL_PORT_INFO **CxlPortInfo, + IN OUT UINTN *CxlCount + ) +{ + UINTN CxlRbSupportCount; + EFI_STATUS Status; + PCIE_PLATFORM_CONFIG *Pcie; + GNB_HANDLE *GnbHandle; + AMD_CXL_PORT_INFO *LocalCxlPortInfoHead; + AMD_CXL_PORT_INFO *LocalCxlPortInfo; + + if ((CxlPortInfo == NULL) || (CxlCount == NULL)) { + return EFI_INVALID_PARAMETER; + } + + CxlRbSupportCount = 0; + LocalCxlPortInfoHead = NULL; + + // Collecting Pcie information from Hob + Status = PcieGetPcieDxe (&Pcie); + if (!EFI_ERROR (Status)) { + GnbHandle = NbioGetHandle (Pcie); + while (GnbHandle != NULL) { + if ((GnbHandle->Header.DescriptorFlags & SILICON_CXL_CAPABLE) == SILICON_CXL_CAPABLE) { + CxlRbSupportCount++; + } + + GnbHandle = GnbGetNextHandle (GnbHandle); + } + + if (CxlRbSupportCount > 0) { + LocalCxlPortInfoHead = AllocateZeroPool (sizeof (AMD_CXL_PORT_INFO) * CxlRbSupportCount); + if (LocalCxlPortInfoHead == NULL) { + ASSERT_EFI_ERROR (EFI_OUT_OF_RESOURCES); + return EFI_OUT_OF_RESOURCES; + } + + GnbHandle = NbioGetHandle (Pcie); + // + // The code below will get all the root bridges with CXL 2.0 support + // We need to add the CXL ACPI method to all of them + // + LocalCxlPortInfo = LocalCxlPortInfoHead; + while (GnbHandle != NULL) { + if ((GnbHandle->Header.DescriptorFlags & SILICON_CXL_CAPABLE) == SILICON_CXL_CAPABLE) { + LocalCxlPortInfo->EndPointBDF.AddressValue = GnbHandle->Address.AddressValue; + LocalCxlPortInfo->IsCxl2 = TRUE; + LocalCxlPortInfo++; + } + + GnbHandle = GnbGetNextHandle (GnbHandle); + } + } + + *CxlCount = CxlRbSupportCount; + *CxlPortInfo = LocalCxlPortInfoHead; + if (CxlRbSupportCount == 0) { + return EFI_NOT_FOUND; + } + } else { + ASSERT_EFI_ERROR (Status); + } + + return Status; +} + +/** + @brief Get the Pcie Cxl Info object + + NOTE: Caller will need to free structure once finished. + + @param[in, out] CxlPortInfo The CXL port information + @param[in, out] CxlCount Number of CXL port present + + @retval EFI_SUCCESS Successfully retrieve the CXL port information. + EFI_INVALID_PARAMETERS Incorrect parameters provided. + EFI_UNSUPPORTED Platform do not support this function. + Other value Returns other EFI_STATUS in case of failure. + +**/ +EFI_STATUS +EFIAPI +GetPcieCxlInfo ( + IN OUT AMD_CXL_PORT_INFO **CxlPortInfo, + IN OUT UINTN *CxlCount + ) +{ + EFI_STATUS Status; + AMD_NBIO_CXL_SERVICES_PROTOCOL *AmdNbioCxlServicesProtocol; + UINT8 Index; + AMD_CXL_PORT_INFO *CxlPortInfoHead; + AMD_CXL_PORT_INFO *LocalCxlPortInfo; + AMD_CXL_PORT_INFO_STRUCT NbioPortInfo; + + DEBUG ((DEBUG_INFO, "%a: Entry\n", __func__)); + + // Check for CXL 2.0 first + Status = GetPcieCxl2Info (CxlPortInfo, CxlCount); + if (!EFI_ERROR (Status) && (*CxlCount > 0)) { + return Status; + } + + AmdNbioCxlServicesProtocol = NULL; + + Status = gBS->LocateProtocol ( + &gAmdNbioCxlServicesProtocolGuid, + NULL, + (VOID **)&AmdNbioCxlServicesProtocol + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_INFO, "%a: Failed to locate AmdNbioCxlServices Protocol: %r\n", __func__, Status)); + Status = EFI_SUCCESS; + return Status; + } + + CxlPortInfoHead = AllocateZeroPool (sizeof (AMD_CXL_PORT_INFO) * AmdNbioCxlServicesProtocol->CxlCount); + if (CxlPortInfoHead == NULL) { + ASSERT_EFI_ERROR (EFI_OUT_OF_RESOURCES); + return EFI_OUT_OF_RESOURCES; + } + + // + // Populate the data structure for the CXL devices in the system to add to + // the ACPI Table + // + for (Index = 0, LocalCxlPortInfo = CxlPortInfoHead; Index < AmdNbioCxlServicesProtocol->CxlCount; Index++, LocalCxlPortInfo++) { + Status = AmdNbioCxlServicesProtocol->CxlGetRootPortInformation ( + AmdNbioCxlServicesProtocol, + Index, + &NbioPortInfo + ); + if (Status != EFI_SUCCESS) { + break; + } + + LocalCxlPortInfo->EndPointBDF.AddressValue = NbioPortInfo.EndPointBDF.AddressValue; + if (NbioPortInfo.DsRcrb == 0) { + LocalCxlPortInfo->IsCxl2 = TRUE; + } else { + LocalCxlPortInfo->IsCxl2 = FALSE; + } + } + + *CxlPortInfo = CxlPortInfoHead; + *CxlCount = AmdNbioCxlServicesProtocol->CxlCount; + return EFI_SUCCESS; +} + +/** + Get the platform specific IOAPIC information. + + NOTE: Caller will need to free structure once finished. + + @param[in, out] IoApicInfo The IOAPIC information + @param[in, out] IoApicCount Number of IOAPIC present + + @retval EFI_SUCCESS Successfully retrieve the IOAPIC information. + EFI_INVALID_PARAMETERS Incorrect parameters provided. + EFI_UNSUPPORTED Platform do not support this function. + Other value Returns other EFI_STATUS in case of failure. + +**/ +EFI_STATUS +EFIAPI +GetIoApicInfo ( + IN OUT EFI_ACPI_6_5_IO_APIC_STRUCTURE **IoApicInfo, + IN OUT UINT8 *IoApicCount + ) +{ + EFI_STATUS Status; + DXE_AMD_NBIO_PCIE_SERVICES_PROTOCOL *PcieServicesProtocol; + PCIE_PLATFORM_CONFIG *Pcie; + GNB_HANDLE *GnbHandle; + GNB_PCIE_INFORMATION_DATA_HOB *PciePlatformConfigHobData; + UINT32 Value32; + EFI_ACPI_6_5_IO_APIC_STRUCTURE *IoApic; + UINT8 LocalIoApicCount; + IO_APIC_IDENTIFICATION_REGISTER IoApicIdentificationRegister; + UINT32 GlobalSystemInterruptBase; + IO_APIC_VERSION_REGISTER IoApicVersionRegister; + + if ((IoApicCount == NULL) || (IoApicInfo == NULL)) { + return EFI_INVALID_PARAMETER; + } + + IoApic = AllocateZeroPool (sizeof (EFI_ACPI_6_5_IO_APIC_STRUCTURE) * MAX_IOAPIC_NUM); + if (IoApic == NULL) { + DEBUG (( + DEBUG_ERROR, + "%a:%d Not enough memory to allocate EFI_ACPI_6_5_IO_APIC_STRUCTURE\n", + __func__, + __LINE__ + )); + ASSERT_EFI_ERROR (EFI_OUT_OF_RESOURCES); + return EFI_OUT_OF_RESOURCES; + } + + // FCH IO APIC + GlobalSystemInterruptBase = 0; + MmioWrite8 ( + PcdGet32 (PcdIoApicAddress) + IOAPIC_INDEX_OFFSET, + IO_APIC_VERSION_REGISTER_INDEX + ); + IoApicVersionRegister.Uint32 = MmioRead32 (PcdGet32 (PcdIoApicAddress) + IOAPIC_DATA_OFFSET); + GlobalSystemInterruptBase += IoApicVersionRegister.Bits.MaximumRedirectionEntry + 1; + Status = gBS->LocateProtocol ( + &gAmdNbioPcieServicesProtocolGuid, + NULL, + (VOID **)&PcieServicesProtocol + ); + if (!EFI_ERROR (Status)) { + PcieServicesProtocol->PcieGetTopology (PcieServicesProtocol, (UINT32 **)&PciePlatformConfigHobData); + Pcie = &(PciePlatformConfigHobData->PciePlatformConfigHob); + GnbHandle = NbioGetHandle (Pcie); + LocalIoApicCount = 0; + IoApic[LocalIoApicCount].Type = EFI_ACPI_6_5_IO_APIC; + IoApic[LocalIoApicCount].Length = sizeof (EFI_ACPI_6_5_IO_APIC_STRUCTURE); + IoApic[LocalIoApicCount].IoApicId = PcdGet8 (PcdIoApicId); + IoApic[LocalIoApicCount].Reserved = 0; + IoApic[LocalIoApicCount].IoApicAddress = PcdGet32 (PcdIoApicAddress); + IoApic[LocalIoApicCount].GlobalSystemInterruptBase = 0; + LocalIoApicCount++; + while (GnbHandle != NULL) { + // Fill the header + IoApic[LocalIoApicCount].Type = EFI_ACPI_6_5_IO_APIC; + IoApic[LocalIoApicCount].Length = sizeof (EFI_ACPI_6_5_IO_APIC_STRUCTURE); + IoApic[LocalIoApicCount].Reserved = 0; + // Read IOAPIC Address + if (GnbHandle->RBIndex < 4) { + SmnRegisterReadS ( + GnbHandle->Address.Address.Segment, + GnbHandle->Address.Address.Bus, + NBIO_SPACE (GnbHandle, SMN_IOHUB0NBIO0_IOAPIC_BASE_ADDR_LO_ADDRESS), + &Value32 + ); + } else { + SmnRegisterReadS ( + GnbHandle->Address.Address.Segment, + GnbHandle->Address.Address.Bus, + NBIO_SPACE (GnbHandle, SMN_IOHUB1NBIO0_IOAPIC_BASE_ADDR_LO_ADDRESS), + &Value32 + ); + } + + IoApic[LocalIoApicCount].IoApicAddress = Value32 & IOAPIC_BASE_ADDR_LO_IOAPIC_BASE_ADDR_LO_MASK; + + // Set APIC ID + MmioWrite8 ( + IoApic[LocalIoApicCount].IoApicAddress + IOAPIC_INDEX_OFFSET, + IO_APIC_IDENTIFICATION_REGISTER_INDEX + ); + IoApicIdentificationRegister.Uint32 = MmioRead32 (IoApic[LocalIoApicCount].IoApicAddress + IOAPIC_DATA_OFFSET); + IoApic[LocalIoApicCount].IoApicId = (UINT8)IoApicIdentificationRegister.Bits.Identification; + + // Get Read the number of redirection entries in this IOAPIC + MmioWrite8 ( + IoApic[LocalIoApicCount].IoApicAddress + IOAPIC_INDEX_OFFSET, + IO_APIC_VERSION_REGISTER_INDEX + ); + IoApicVersionRegister.Uint32 = MmioRead32 ( + IoApic[LocalIoApicCount].IoApicAddress + IOAPIC_DATA_OFFSET + ); + // Set Global System Interrupt Base + IoApic[LocalIoApicCount].GlobalSystemInterruptBase = GlobalSystemInterruptBase; + GlobalSystemInterruptBase += IoApicVersionRegister.Bits.MaximumRedirectionEntry + 1; + + LocalIoApicCount++; + GnbHandle = GnbGetNextHandle (GnbHandle); + } + } + + *IoApicInfo = IoApic; + *IoApicCount = LocalIoApicCount; + return EFI_SUCCESS; +} + +/** + Get the platform PCIe configuration information. + + NOTE: Caller will need to free structure once finished. + + @param[in, out] RootBridge The root bridge information + @param[in, out] RootBridgeCount Number of root bridges present + + @retval EFI_SUCCESS Successfully retrieve the root bridge information. + EFI_INVALID_PARAMETERS Incorrect parameters provided. + EFI_UNSUPPORTED Platform do not support this function. + Other value Returns other EFI_STATUS in case of failure. + +**/ +EFI_STATUS +EFIAPI +GetPcieInfo ( + IN OUT AMD_PCI_ROOT_BRIDGE_OBJECT_INSTANCE **RootBridge, + IN OUT UINTN *RootBridgeCount + ) +{ + EFI_STATUS Status; + UINTN NumberOfRootBridges; + UINTN RbIndex; + UINTN Index; + UINTN CxlIndex; + AMD_PCI_RESOURCES_PROTOCOL *AmdPciResources; + AMD_PCI_ROOT_BRIDGE_OBJECT_INSTANCE *LocalRootBridgeArray; // do not free + EFI_ACPI_6_5_IO_APIC_STRUCTURE *IoApicInfo; + UINT8 IoApicCount; + AMD_CXL_PORT_INFO *CxlPortInfoHead; + AMD_CXL_PORT_INFO *CxlPortInfo; + UINTN CxlCount; + PCI_ADDR PciAddr; + + IoApicInfo = NULL; + IoApicCount = 0; + Status = GetIoApicInfo (&IoApicInfo, &IoApicCount); + if (EFI_ERROR (Status) || (IoApicInfo == NULL) || (IoApicCount == 0)) { + DEBUG ((DEBUG_ERROR, "%a:%d Cannot obtain NBIO IOAPIC information.\n", __func__, __LINE__)); + return EFI_NOT_FOUND; + } + + Status = gBS->LocateProtocol ( + &gAmdPciResourceProtocolGuid, + NULL, + (VOID **)&AmdPciResources + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "%a: Failed to locate AMD PCIe Resource Protocol: %r\n", + __func__, + Status + )); + return Status; + } + + Status = AmdPciResources->AmdPciResourcesGetNumberOfRootBridges ( + AmdPciResources, + &NumberOfRootBridges + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "%a: Failed to get Number Of Root Bridges: %r\n", + __func__, + Status + )); + return Status; + } + + LocalRootBridgeArray = AllocateZeroPool (sizeof (AMD_PCI_ROOT_BRIDGE_OBJECT_INSTANCE) * NumberOfRootBridges); + if (LocalRootBridgeArray == NULL) { + ASSERT_EFI_ERROR (EFI_OUT_OF_RESOURCES); + return EFI_OUT_OF_RESOURCES; + } + + // Collect CXL info + CxlPortInfoHead = NULL; + CxlCount = 0; + Status = GetPcieCxlInfo (&CxlPortInfoHead, &CxlCount); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_INFO, "[INFO] Cannot find CXL device.\n")); + } + + // Collect Root Bridges to be sorted + for (RbIndex = 1; RbIndex <= NumberOfRootBridges; RbIndex++) { + Status = AmdPciResources->AmdPciResourcesGetRootBridgeInfo (AmdPciResources, RbIndex, (PCI_ROOT_BRIDGE_OBJECT **)&LocalRootBridgeArray[RbIndex - 1].Object); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "%a: Failed to get Root Bridges information : %r\n", + __func__, + Status + )); + FreePool (LocalRootBridgeArray); + if (CxlPortInfoHead != NULL) { + FreePool (CxlPortInfoHead); + } + + *RootBridge = NULL; + *RootBridgeCount = 0; + return Status; + } + + // Assign GSI values + LocalRootBridgeArray[RbIndex - 1].GlobalInterruptStart = IoApicInfo[RbIndex].GlobalSystemInterruptBase; + + // Get PXM info + ZeroMem ((VOID *)&PciAddr, sizeof (PciAddr)); + PciAddr.Address.Bus = (UINT32)LocalRootBridgeArray[RbIndex - 1].Object->BaseBusNumber; + PciAddr.Address.Segment = (UINT32)LocalRootBridgeArray[RbIndex - 1].Object->Segment; + LocalRootBridgeArray[RbIndex - 1].PxmDomain = GetPxmDomain (LocalRootBridgeArray[RbIndex - 1].Object->SocketId, PciAddr); + + // check for CXL port + if (CxlCount > 0) { + for (CxlIndex = 0, CxlPortInfo = CxlPortInfoHead; CxlIndex < CxlCount; CxlIndex++, CxlPortInfo++) { + if ((CxlPortInfo->EndPointBDF.Address.Segment == LocalRootBridgeArray[RbIndex - 1].Object->Segment) && + (CxlPortInfo->EndPointBDF.Address.Bus == LocalRootBridgeArray[RbIndex - 1].Object->BaseBusNumber)) + { + LocalRootBridgeArray[RbIndex - 1].CxlCount = 1; + LocalRootBridgeArray[RbIndex - 1].CxlPortInfo.IsCxl2 = CxlPortInfo->IsCxl2; + LocalRootBridgeArray[RbIndex - 1].CxlPortInfo.EndPointBDF.AddressValue = CxlPortInfo->EndPointBDF.AddressValue; + break; + } + } + } + + Status = AmdPciResources->AmdPciResourcesGetNumberOfRootPorts ( + AmdPciResources, + LocalRootBridgeArray[RbIndex - 1].Object->Index, + &LocalRootBridgeArray[RbIndex - 1].RootPortCount + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "%a: ERROR: GetNumberOfRootPorts Failed: %r\n", + __func__, + Status + )); + FreePool (LocalRootBridgeArray); + *RootBridge = NULL; + *RootBridgeCount = 0; + return Status; + } + + for (Index = 1; Index <= LocalRootBridgeArray[RbIndex - 1].RootPortCount; Index++) { + Status = AmdPciResources->AmdPciResourcesGetRootPortInfo ( + AmdPciResources, + LocalRootBridgeArray[RbIndex - 1].Object->Index, + Index, + (PCI_ROOT_PORT_OBJECT **)&LocalRootBridgeArray[RbIndex - 1].RootPort[Index] + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "%a: ERROR: AmdPciResourcesGetRootPortInfo Failed: %r\n", + __func__, + Status + )); + FreePool (LocalRootBridgeArray); + *RootBridge = NULL; + *RootBridgeCount = 0; + return Status; + } + } + } + + FreePool (IoApicInfo); + if (CxlPortInfoHead != NULL) { + FreePool (CxlPortInfoHead); + } + + *RootBridge = LocalRootBridgeArray; + *RootBridgeCount = NumberOfRootBridges; + return Status; +} + +/** + This function returns SBDF information for a given slot number. + + @param[in] SlotNumInfo Slot number to be provided. + @param[out] SegInfo Segment number. + @param[out] BusInfo Bus number. + @param[out] DevFunInfo Bits 0-2 corresponds to function number & bits 3-7 corresponds + to device number. + + @retval EFI_SUCCESS All parameters were valid. + @retval EFI_INVALID_PARAMETER One or many parameters are invalid. + @retval EFI_NOT_FOUND SBDF information is not found for the given slot number. + +**/ +EFI_STATUS +SlotBdfInfo ( + IN UINT16 *SlotNumInfo, + OUT UINT16 *SegInfo, + OUT UINT8 *BusInfo, + OUT UINT8 *DevFunInfo + ) +{ + EFI_STATUS Status; + PCIE_PLATFORM_CONFIG *Pcie; + PCIE_COMPLEX_CONFIG *ComplexList; + PCIE_SILICON_CONFIG *SiliconList; + PCIE_WRAPPER_CONFIG *WrapperList; + PCIE_ENGINE_CONFIG *EngineList; + + if ((SlotNumInfo == NULL) || (SegInfo == NULL) || (BusInfo == NULL) || (DevFunInfo == NULL)) { + return EFI_INVALID_PARAMETER; + } + + Pcie = NULL; + Status = PcieGetPcieDxe (&Pcie); + if (EFI_ERROR (Status)) { + return Status; + } + + ComplexList = (PCIE_COMPLEX_CONFIG *)PcieConfigGetChild (DESCRIPTOR_COMPLEX, &Pcie->Header); + + while (ComplexList != NULL) { + SiliconList = PcieConfigGetChildSilicon (ComplexList); + while (SiliconList != NULL) { + WrapperList = PcieConfigGetChildWrapper (SiliconList); + while (WrapperList != NULL) { + EngineList = PcieConfigGetChildEngine (WrapperList); + while (EngineList != NULL) { + if (EngineList->Type.Port.PortData.SlotNum == *SlotNumInfo) { + *SegInfo = EngineList->Type.Port.Address.Address.Segment & 0xFFFF; + *BusInfo = EngineList->Type.Port.Address.Address.Bus & 0xFF; + *DevFunInfo = (((EngineList->Type.Port.Address.Address.Device) & 0x1F) << 3) | + ((EngineList->Type.Port.Address.Address.Function) & 0x7); + return EFI_SUCCESS; + } + + EngineList = PcieLibGetNextDescriptor (EngineList); + } + + WrapperList = PcieLibGetNextDescriptor (WrapperList); + } + + SiliconList = PcieLibGetNextDescriptor (SiliconList); + } + + if ((ComplexList->Header.DescriptorFlags & DESCRIPTOR_TERMINATE_TOPOLOGY) == 0) { + ComplexList++; + } else { + ComplexList = NULL; + } + } + + return EFI_NOT_FOUND; +} + +/** + This function allocates and populate system slot smbios record (Type 9). + + @param DxioPortPtr Pointer to DXIO port descriptor. + @param SmbiosRecordPtr Pointer to smbios type 9 record. + + @retval EFI_SUCCESS All parameters were valid. + @retval EFI_INVALID_PARAMETER One or many parameters are invalid. + @retval EFI_OUT_OF_RESOURCES Resource not available. + +**/ +EFI_STATUS +CreateSmbiosSystemSlotRecord ( + IN DXIO_PORT_DESCRIPTOR *DxioPortPtr, + IN OUT SMBIOS_TABLE_TYPE9 **SmbiosRecordPtr + ) +{ + EFI_STATUS Status; + SMBIOS_TABLE_TYPE9 *SmbiosRecord; + UINT16 SlotNumInfo; + UINT16 SegInfo; + UINT8 BusInfo; + UINT8 DevFunInfo; + UINT8 PortWidth; + + Status = EFI_SUCCESS; + SegInfo = 0xFFFF; + BusInfo = 0xFF; + DevFunInfo = 0xFF; + + if ((DxioPortPtr == NULL) || (SmbiosRecordPtr == NULL)) { + return EFI_INVALID_PARAMETER; + } + + SmbiosRecord = NULL; + SmbiosRecord = AllocateZeroPool (sizeof (SMBIOS_TABLE_TYPE9)); + if (SmbiosRecord == NULL) { + Status = EFI_OUT_OF_RESOURCES; + return Status; + } else { + // Currently only map PCIE slots in system slot table. + if (DxioPortPtr->EngineData.EngineType == DxioPcieEngine) { + switch (DxioPortPtr->Port.LinkSpeedCapability) { + case DxioGenMaxSupported: + SmbiosRecord->SlotType = SlotTypePCIExpressGen5; + break; + case DxioGen1: + SmbiosRecord->SlotType = SlotTypePciExpress; + break; + case DxioGen2: + SmbiosRecord->SlotType = SlotTypePciExpressGen2; + break; + case DxioGen3: + SmbiosRecord->SlotType = SlotTypePciExpressGen3; + break; + case DxioGen4: + SmbiosRecord->SlotType = SlotTypePciExpressGen4; + break; + case DxioGen5: + SmbiosRecord->SlotType = SlotTypePCIExpressGen5; + break; + default: + SmbiosRecord->SlotType = SlotTypePCIExpressGen5; + break; + } + } else { + SmbiosRecord->SlotType = SlotTypeOther; + } + + if (DxioPortPtr->EngineData.EndLane >= DxioPortPtr->EngineData.StartLane) { + PortWidth = DxioPortPtr->EngineData.EndLane - DxioPortPtr->EngineData.StartLane + 1; + } else { + PortWidth = DxioPortPtr->EngineData.StartLane - DxioPortPtr->EngineData.EndLane + 1; + } + + switch (PortWidth) + { + case 16: + SmbiosRecord->SlotDataBusWidth = SlotDataBusWidth16X; + SmbiosRecord->DataBusWidth = 16; + break; + case 8: + SmbiosRecord->SlotDataBusWidth = SlotDataBusWidth8X; + SmbiosRecord->DataBusWidth = 8; + break; + case 4: + SmbiosRecord->SlotDataBusWidth = SlotDataBusWidth4X; + SmbiosRecord->DataBusWidth = 4; + break; + case 2: + SmbiosRecord->SlotDataBusWidth = SlotDataBusWidth2X; + SmbiosRecord->DataBusWidth = 2; + break; + default: + SmbiosRecord->SlotDataBusWidth = SlotDataBusWidth1X; + SmbiosRecord->DataBusWidth = 1; + break; + } + + if (DxioPortPtr->Port.EndpointStatus == (DXIO_ENDPOINT_STATUS)EndpointDetect) { + SmbiosRecord->CurrentUsage = SlotUsageInUse; + } else if (DxioPortPtr->Port.EndpointStatus == (DXIO_ENDPOINT_STATUS)EndpointNotPresent) { + SmbiosRecord->CurrentUsage = SlotUsageAvailable; + } else { + SmbiosRecord->CurrentUsage = SlotUsageUnknown; + } + + SlotNumInfo = DxioPortPtr->Port.SlotNum; + Status = SlotBdfInfo ( + &SlotNumInfo, + &SegInfo, + &BusInfo, + &DevFunInfo + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Could not get SBDF information %r\n", Status)); + } + + SmbiosRecord->SlotLength = SlotLengthLong; + SmbiosRecord->SlotID = DxioPortPtr->Port.SlotNum; + SmbiosRecord->SegmentGroupNum = SegInfo; + SmbiosRecord->BusNum = BusInfo; + SmbiosRecord->DevFuncNum = DevFunInfo; + SmbiosRecord->PeerGroupingCount = 0; + + *SmbiosRecordPtr = SmbiosRecord; + } + + return Status; +} + +/** + Parse the port parameters and update their slot numbers + + @param[in, out] PortDescriptor Port descriptor to update + + @retval VOID +**/ +VOID +GetSlotNumber ( + IN OUT DXIO_PORT_DESCRIPTOR *PortDescriptor + ) +{ + PORT_PARAM *PortParam; + + PortParam = (PORT_PARAM *) &(PortDescriptor->PortParams); + while (PortParam != NULL && PortParam->ParamType != 0) { + if (PortParam->ParamType == PP_SLOT_NUM) { + PortDescriptor->Port.SlotNum = PortParam->ParamValue; + } + PortParam++; + } +} + +/** + Parse the DXIO topology table for PcieEngine's and update + their slot number + + @param[in, out] DxioTopologyTablePtr DXIO Topology Table pointer + + @retval VOID +**/ +VOID +UpdateSlotNum ( + IN OUT AMD_CPM_DXIO_TOPOLOGY_TABLE *DxioTopologyTablePtr + ) +{ + UINTN Count; + + for (Count = 0; Count < AMD_DXIO_PORT_DESCRIPTOR_SIZE; Count++) { + if (DxioTopologyTablePtr->Port[Count].Flags == DESCRIPTOR_TERMINATE_LIST) { + break; + } + if (!(DxioTopologyTablePtr->Port[Count].EngineData.EngineType == DxioPcieEngine && + DxioTopologyTablePtr->Port[Count].Port.PortPresent != DxioPortDisabled)) { + continue; + } + GetSlotNumber (&DxioTopologyTablePtr->Port[Count]); + } +} + +/** + Get the platform specific System Slot information. + + NOTE: Caller will need to free structure once finished. + + @param[in, out] SystemSlotInfo The System Slot information + @param[in, out] SystemSlotCount Number of System Slot present + + @retval EFI_UNSUPPORTED Platform do not support this function. +**/ +EFI_STATUS +EFIAPI +GetSystemSlotInfo ( + IN OUT SMBIOS_TABLE_TYPE9 **SystemSlotInfo, + IN OUT UINTN *SystemSlotCount + ) +{ + AMD_CPM_TABLE_PROTOCOL *CpmTableProtocolPtr; + AMD_CPM_DXIO_TOPOLOGY_TABLE *DxioTopologyTablePtr2[2]; + AMD_CPM_DXIO_TOPOLOGY_TABLE *DxioTopologyTableCopyPtr[2]; + EFI_STATUS Status; + UINTN SocketIdx; + UINTN DxioPortIdx; + UINTN SlotCount; + SMBIOS_TABLE_TYPE9 *SlotInfo; + SMBIOS_TABLE_TYPE9 *SmbiosRecord; + + if ((SystemSlotInfo == NULL) || (SystemSlotCount == NULL)) { + return EFI_INVALID_PARAMETER; + } + + Status = gBS->LocateProtocol ( + &gAmdCpmTableProtocolGuid, + NULL, + (VOID **)&CpmTableProtocolPtr + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Failed to locate AmdCpmTableProtocol: %r\n", Status)); + return Status; + } + + DxioTopologyTablePtr2[0] = NULL; + DxioTopologyTablePtr2[0] = CpmTableProtocolPtr->CommonFunction.GetTablePtr2 ( + CpmTableProtocolPtr, + CPM_SIGNATURE_DXIO_TOPOLOGY + ); + + DxioTopologyTablePtr2[1] = NULL; + DxioTopologyTablePtr2[1] = CpmTableProtocolPtr->CommonFunction.GetTablePtr2 ( + CpmTableProtocolPtr, + CPM_SIGNATURE_DXIO_TOPOLOGY_S1 + ); + + //Shouldn't modify CPM table, so make a copy that we can edit + DxioTopologyTableCopyPtr[0] = AllocateZeroPool (sizeof(AMD_CPM_DXIO_TOPOLOGY_TABLE)); + DxioTopologyTableCopyPtr[1] = AllocateZeroPool (sizeof(AMD_CPM_DXIO_TOPOLOGY_TABLE)); + + CopyMem (DxioTopologyTableCopyPtr[0], (VOID*) DxioTopologyTablePtr2[0], sizeof (AMD_CPM_DXIO_TOPOLOGY_TABLE)); + CopyMem (DxioTopologyTableCopyPtr[1], (VOID*) DxioTopologyTablePtr2[1], sizeof (AMD_CPM_DXIO_TOPOLOGY_TABLE)); + + //Update Slot Numbers from port params + for (SocketIdx = 0; SocketIdx < FixedPcdGet32 (PcdAmdNumberOfPhysicalSocket); SocketIdx++ ) { + if (DxioTopologyTableCopyPtr[SocketIdx] != NULL) { + UpdateSlotNum (DxioTopologyTableCopyPtr[SocketIdx]); + } + } + + // Add Smbios System Slot information for all sockets present. + SlotCount = 0; + for (SocketIdx = 0; SocketIdx < FixedPcdGet32 (PcdAmdNumberOfPhysicalSocket); SocketIdx++ ) { + if (DxioTopologyTableCopyPtr[SocketIdx] != NULL) { + for (DxioPortIdx = 0; DxioPortIdx < AMD_DXIO_PORT_DESCRIPTOR_SIZE; + DxioPortIdx++) + { + // Check if Slot is present + if ((DxioTopologyTableCopyPtr[SocketIdx]->Port[DxioPortIdx].Port.SlotNum > 0) && + (DxioTopologyTableCopyPtr[SocketIdx]->Port[DxioPortIdx].Port.PortPresent == 1)) + { + SlotCount++; + } + + // Terminate if last port found. + if ((DxioTopologyTableCopyPtr[SocketIdx]->Port[DxioPortIdx].Flags & DESCRIPTOR_TERMINATE_LIST)) { + break; + } + } + } + } + + if (SlotCount == 0) { + return EFI_NOT_FOUND; + } + + SlotInfo = AllocateZeroPool (sizeof (SMBIOS_TABLE_TYPE9) * SlotCount); + if (SlotInfo == NULL) { + ASSERT_EFI_ERROR (EFI_OUT_OF_RESOURCES); + return EFI_OUT_OF_RESOURCES; + } + + SlotCount = 0; + for (SocketIdx = 0; SocketIdx < FixedPcdGet32 (PcdAmdNumberOfPhysicalSocket); SocketIdx++ ) { + if (DxioTopologyTableCopyPtr[SocketIdx] != NULL) { + for (DxioPortIdx = 0; DxioPortIdx < AMD_DXIO_PORT_DESCRIPTOR_SIZE; + DxioPortIdx++) + { + // Check if Slot is present + if ((DxioTopologyTableCopyPtr[SocketIdx]->Port[DxioPortIdx].Port.SlotNum > 0) && + (DxioTopologyTableCopyPtr[SocketIdx]->Port[DxioPortIdx].Port.PortPresent == 1)) + { + SmbiosRecord = NULL; + Status = CreateSmbiosSystemSlotRecord ( + &DxioTopologyTableCopyPtr[SocketIdx]->Port[DxioPortIdx], + &SmbiosRecord + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_VERBOSE, "Slot (%d) information not found. Status = %r\n", + DxioTopologyTableCopyPtr[SocketIdx]->Port[DxioPortIdx].Port.SlotNum, + Status + )); + } else { + CopyMem (&SlotInfo[SlotCount], SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE9)); + SlotCount++; + } + } + + // Terminate if last port found. + if ((DxioTopologyTableCopyPtr[SocketIdx]->Port[DxioPortIdx].Flags & 0x80000000)) { + break; + } + } + } + } + + FreePool (DxioTopologyTableCopyPtr[0]); + FreePool (DxioTopologyTableCopyPtr[1]); + + *SystemSlotInfo = SlotInfo; + *SystemSlotCount = SlotCount; + return EFI_SUCCESS; +} diff --git a/Platform/AMD/TurinBoard/Library/DxePlatformSocLib/DxePlatformSocLib.inf b/Platform/AMD/TurinBoard/Library/DxePlatformSocLib/DxePlatformSocLib.inf new file mode 100644 index 0000000000..821c77a571 --- /dev/null +++ b/Platform/AMD/TurinBoard/Library/DxePlatformSocLib/DxePlatformSocLib.inf @@ -0,0 +1,55 @@ +## @file +# INF file of AMD Platform SoC library +# +# Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved. +# +## + +[Defines] + INF_VERSION = 1.29 + BASE_NAME = DxePlatformSocLib + MODULE_UNI_FILE = DxePlatformSocLib.uni + FILE_GUID = 27F805CC-7724-48CE-935F-6FBBC7B17BCE + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = PlatformSocLib + +[Sources] + DxePlatformSocLib.c + +[Packages] + AgesaModulePkg/AgesaCommonModulePkg.dec + AgesaModulePkg/AgesaModuleDfPkg.dec + AgesaModulePkg/AgesaModuleNbioPkg.dec + AgesaPkg/AgesaPkg.dec + AmdCpmPkg/AmdCpmPkg.dec + AmdPlatformPkg/AmdPlatformPkg.dec + MdePkg/MdePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + HobLib + NbioCommonDxeLib + NbioHandleLib + PcdLib + PcieConfigLib + SmnAccessLib + +[Pcd] + gMinPlatformPkgTokenSpaceGuid.PcdIoApicAddress + gMinPlatformPkgTokenSpaceGuid.PcdIoApicId + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdNumberOfPhysicalSocket ## CONSUMES + +[Protocols] + gAmdFabricNumaServices2ProtocolGuid + gAmdNbioCxlServicesProtocolGuid + gAmdNbioPcieServicesProtocolGuid + gAmdPciResourceProtocolGuid + gAmdSocLogicalIdProtocolGuid + gAmdCpmTableProtocolGuid + +[Depex] + gAmdNbioPcieServicesProtocolGuid diff --git a/Platform/AMD/TurinBoard/Library/DxePlatformSocLib/DxePlatformSocLib.uni b/Platform/AMD/TurinBoard/Library/DxePlatformSocLib/DxePlatformSocLib.uni new file mode 100644 index 0000000000..78a7d907e7 --- /dev/null +++ b/Platform/AMD/TurinBoard/Library/DxePlatformSocLib/DxePlatformSocLib.uni @@ -0,0 +1,11 @@ +## @file +# UNI file of AMD Turin Platform SoC library +# +# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved. +# +## + +#string STR_MODULE_ABSTRACT #language en-US "AMD DXE Turin SoC library instance." + +#string STR_MODULE_DESCRIPTION #language en-US "AMD DXE Turin SoC library instance." + diff --git a/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/AmdSpiHcInternal.c b/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/AmdSpiHcInternal.c new file mode 100644 index 0000000000..f8996d51f6 --- /dev/null +++ b/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/AmdSpiHcInternal.c @@ -0,0 +1,299 @@ +/** @file + + Internal functions used by platform SPI HC library that includes ROM armor + + Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. + +**/ +#include +#include +#include +#include +#include +#include +#include +#include +#include "AmdSpiHcInternal.h" + +extern BOOLEAN mPspMailboxSpiMode; +extern SPI_COMMUNICATION_BUFFER mSpiCommunicationBuffer; +extern EFI_PHYSICAL_ADDRESS mHcAddress; + +/** + Check that SPI Conroller is Not Busy + + @retval EFI_SUCCESS Spi Execute command executed properly + @retval EFI_DEVICE_ERROR Spi Execute command failed +**/ +EFI_STATUS +EFIAPI +FchSpiControllerNotBusy ( + ) +{ + UINT32 SpiReg00; + UINT32 LpcDmaStatus; + UINT32 RetryCount; + UINTN DelayMicroseconds; + + if (mPspMailboxSpiMode) { + return EFI_DEVICE_ERROR; + } + + DelayMicroseconds = FixedPcdGet32 (PcdSpiNorFlashOperationDelayMicroseconds); + SpiReg00 = FCH_SPI_BUSY; + RetryCount = FixedPcdGet32 (PcdAmdSpiRetryCount); + do { + SpiReg00 = MmioRead32 (mHcAddress + FCH_SPI_MMIO_REG4C_SPISTATUS); + LpcDmaStatus = PciSegmentRead32 ( + PCI_SEGMENT_LIB_ADDRESS ( + 0x00, + FCH_LPC_BUS, + FCH_LPC_DEV, + FCH_LPC_FUNC, + FCH_LPC_REGB8 + ) + ); + if ( ((SpiReg00 & FCH_SPI_BUSY) == 0) + && ((LpcDmaStatus & FCH_LPC_DMA_SPI_BUSY) == 0)) + { + break; + } + + MicroSecondDelay (DelayMicroseconds); + RetryCount--; + } while (RetryCount > 0); + + if (RetryCount == 0) { + return EFI_DEVICE_ERROR; + } + + return EFI_SUCCESS; +} + +/** + Check for SPI transaction failure(s) + + @retval EFI_SUCCESS Spi Execute command executed properly + @retval others Spi Execute command failed +**/ +EFI_STATUS +EFIAPI +FchSpiTransactionCheckFailure ( + ) +{ + EFI_STATUS Status; + UINT32 Data; + + if (mPspMailboxSpiMode) { + return EFI_DEVICE_ERROR; + } + + Status = FchSpiControllerNotBusy (); + if (!EFI_ERROR (Status)) { + Data = MmioRead32 (mHcAddress + FCH_SPI_MMIO_REG00); + if ((Data & FCH_SPI_FIFO_PTR_CRL) != 0) { + Status = EFI_ACCESS_DENIED; + } + } + + return Status; +} + +/** + If SPI controller is not busy, execute SPI command. Then wait until SPI + controller is not busy. + + @retval EFI_SUCCESS Spi Execute command executed properly + @retval others Spi Execute command failed +**/ +EFI_STATUS +EFIAPI +FchSpiExecute ( + ) +{ + EFI_STATUS Status; + + if (mPspMailboxSpiMode) { + return EFI_DEVICE_ERROR; + } + + Status = FchSpiControllerNotBusy (); + if (!EFI_ERROR (Status)) { + MmioOr8 (mHcAddress + FCH_SPI_MMIO_REG47_CMDTRIGGER, BIT7); + Status = FchSpiControllerNotBusy (); + if (!EFI_ERROR (Status)) { + Status = FchSpiTransactionCheckFailure (); + } + } + + return Status; +} + +/** + Block SPI Flash Write Enable Opcode. This will block anything that requires + the Opcode equivalent to the SPI Flash Memory Write Enable Opcode. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) + + Calls during DXE will only work until the SPI controller is locked. + + Calls to these functions from SMM will only be valid during SMM, restore state + will wipe out any changes. +**/ +EFI_STATUS +EFIAPI +InternalFchSpiBlockOpcode ( + IN CONST EFI_PHYSICAL_ADDRESS HcAddress, + IN UINT8 Opcode + ) +{ + EFI_STATUS Status; + BOOLEAN OpcodeBlocked; + UINTN RestrictedCmd; + UINT8 Data; + + Status = EFI_OUT_OF_RESOURCES; + OpcodeBlocked = FALSE; + + // Allow only one copy of Opcode in RestrictedCmd register + for (RestrictedCmd = 0; RestrictedCmd <= 3; RestrictedCmd++) { + Data = MmioRead8 (HcAddress + FCH_SPI_MMIO_REG04 + RestrictedCmd); + + if ((Data == Opcode) && (OpcodeBlocked == FALSE)) { + OpcodeBlocked = TRUE; + } else if ((Data == Opcode) && (OpcodeBlocked == TRUE)) { + MmioWrite8 (HcAddress + FCH_SPI_MMIO_REG04 + RestrictedCmd, 0x00); + } else if ((Data == 0x00) && (OpcodeBlocked == FALSE)) { + MmioWrite8 (HcAddress + FCH_SPI_MMIO_REG04 + RestrictedCmd, Opcode); + OpcodeBlocked = TRUE; + } + } + + if (OpcodeBlocked) { + Status = EFI_SUCCESS; + } + + return Status; +} + +/** + Un-Block SPI Flash Write Enable Opcode. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) + + Calls during DXE will only work until the SPI controller is locked. + + Calls to these functions from SMM will only be valid during SMM, restore state + will wipe out any changes. +**/ +EFI_STATUS +EFIAPI +InternalFchSpiUnblockOpcode ( + IN CONST EFI_PHYSICAL_ADDRESS HcAddress, + IN UINT8 Opcode + ) +{ + UINTN RestrictedCmd; + + // Unblock any copies of the Opcode + for (RestrictedCmd = 0; RestrictedCmd <= 3; RestrictedCmd++) { + if (MmioRead8 (HcAddress + FCH_SPI_MMIO_REG04 + RestrictedCmd) == Opcode) { + MmioWrite8 (HcAddress + FCH_SPI_MMIO_REG04 + RestrictedCmd, 0x00); + } + } + + return EFI_SUCCESS; +} + +/** + Un-Block any blocked SPI Opcodes. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) + + Calls during DXE will only work until the SPI controller is locked. + + Calls to these functions from SMM will only be valid during SMM, restore state + will wipe out any changes. +**/ +EFI_STATUS +EFIAPI +InternalFchSpiUnblockAllOpcodes ( + IN CONST EFI_PHYSICAL_ADDRESS HcAddress + ) +{ + MmioWrite32 (HcAddress + FCH_SPI_MMIO_REG04, 0x00); + return EFI_SUCCESS; +} + +/** + Lock SPI host controller registers. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +InternalFchSpiLockSpiHostControllerRegisters ( + IN CONST EFI_PHYSICAL_ADDRESS HcAddress + ) +{ + MmioBitFieldAnd32 ( + HcAddress + FCH_SPI_MMIO_REG00, + 22, + 23, + 0x0 + ); + if (MmioBitFieldRead32 (HcAddress + FCH_SPI_MMIO_REG00, 22, 23) + == 0x0) + { + return EFI_SUCCESS; + } + + return EFI_DEVICE_ERROR; +} + +/** + Unlock SPI host controller registers. This unlock function will only work in + SMM. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +InternalFchSpiUnlockSpiHostControllerRegisters ( + IN CONST EFI_PHYSICAL_ADDRESS HcAddress + ) +{ + MmioBitFieldOr32 ( + HcAddress + FCH_SPI_MMIO_REG00, + 22, + 23, + BIT0 | BIT1 + ); + if (MmioBitFieldRead32 (HcAddress + FCH_SPI_MMIO_REG00, 22, 23) + == (BIT0 | BIT1)) + { + return EFI_SUCCESS; + } + + return EFI_DEVICE_ERROR; +} diff --git a/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/AmdSpiHcInternal.h b/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/AmdSpiHcInternal.h new file mode 100644 index 0000000000..0e00fe8d65 --- /dev/null +++ b/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/AmdSpiHcInternal.h @@ -0,0 +1,127 @@ +/** @file + + Internal functions used by platform SPI HC library + + Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. + +**/ + +#ifndef AMD_SPI_HC_INTERNAL_H_ +#define AMD_SPI_HC_INTERNAL_H_ + +#include +#include +#include +#include +#include +#include +#include + +#define FCH_LPC_DMA_SPI_BUSY BIT0 +#define FCH_SPI_MMIO_REG04 0x04// SPI_RestrictedCmd +#define FCH_SPI_FRAME_SIZE_SUPPORT_MASK (1 << (8 - 1)) +#define FCH_SPI_LOCK_CONTROLLER 0x00 +#define FCH_SPI_UNLOCK_CONTROLLER BIT0 | BIT1 + +/** + Check that SPI Conroller is Not Busy + + @retval EFI_SUCCESS Spi Execute command executed properly + @retval EFI_DEVICE_ERROR Spi Execute command failed +**/ +EFI_STATUS +EFIAPI +FchSpiControllerNotBusy ( + ); + +/** + Execute SPI command + + @retval EFI_SUCCESS Spi Execute command executed properly + @retval others Spi Execute command failed +**/ +EFI_STATUS +EFIAPI +FchSpiExecute ( + ); + +/** + Block SPI Flash Write Enable Opcode. This will block anything that requires + the Opcode equivalent to the SPI Flash Memory Write Enable Opcode. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +InternalFchSpiBlockOpcode ( + IN CONST EFI_PHYSICAL_ADDRESS HcAddress, + IN UINT8 Opcode + ); + +/** + Un-Block SPI Flash Write Enable Opcode. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +InternalFchSpiUnblockOpcode ( + IN CONST EFI_PHYSICAL_ADDRESS HcAddress, + IN UINT8 Opcode + ); + +/** + Un-Block any blocked SPI Opcodes. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +InternalFchSpiUnblockAllOpcodes ( + IN CONST EFI_PHYSICAL_ADDRESS HcAddress + ); + +/** + Lock SPI host controller registers. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +InternalFchSpiLockSpiHostControllerRegisters ( + IN CONST EFI_PHYSICAL_ADDRESS HcAddress + ); + +/** + Unlock SPI host controller registers. This unlock function will only work in + SMM. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +InternalFchSpiUnlockSpiHostControllerRegisters ( + IN CONST EFI_PHYSICAL_ADDRESS HcAddress + ); + +#endif // __AMD_SPI_HC_INTERNAL_H__ diff --git a/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/AmdSpiHcSmmState.c b/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/AmdSpiHcSmmState.c new file mode 100644 index 0000000000..8a7a12dcb7 --- /dev/null +++ b/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/AmdSpiHcSmmState.c @@ -0,0 +1,365 @@ +/** @file + + SPI HC SMM state registration function definitions + + Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. + +**/ +#include +#include +#include +#include +#include +#include +#include "AmdSpiHcSmmState.h" +#include "AmdSpiHcInternal.h" + +extern BOOLEAN mPspMailboxSpiMode; +extern EFI_PHYSICAL_ADDRESS mHcAddress; +extern BOOLEAN mSmmAlreadySavedState; +extern VOID *mState; +extern UINT32 mStateSize; +extern UINT32 mStateRecordCount; + +CONST struct SpiHcRegisterState mSpiHcState[] = { + // {Register, Size, Count} + { 0x04, 0x4, 0x1 }, // SPI_RestrictedCmd + { 0x08, 0x4, 0x1 }, // SPI_RestrictedCmd2 + { 0x0D, 0x1, 0x1 }, // SPI_Cntrl1[15:8] + { 0x0E, 0x2, 0x1 }, // SPI_Cntrl1[31:16] + { 0x10, 0x4, 0x1 }, // SPI_CmdValue0 + { 0x14, 0x4, 0x1 }, // SPI_CmdValue1 + { 0x18, 0x4, 0x1 }, // SPI_CmdValue2 + { 0x1D, 0x1, 0x1 }, // Alt_SPI_CS + { 0x20, 0x1, 0x1 }, // SPI100 Enable + { 0x22, 0x2, 0x1 }, // SPI100 Speed Config + { 0x24, 0x4, 0x1 }, // SPI100 Clock Config + { 0x32, 0x2, 0x1 }, // SPI100 Dummy Cycle Config + { 0x34, 0x2, 0x1 }, // SPI100 RX Timing Config 1 + { 0x44, 0x1, 0x1 }, // ModeByte + { 0x45, 0x1, 0x1 }, // CmdCode + { 0x48, 0x1, 0x1 }, // TxByteCount + { 0x4B, 0x1, 0x1 }, // RxByteCount + { 0x80, 0x1, 70 }, // FIFO [70:0] + { 0x00, 0x4, 0x1 } // SpiCntrl0 ** Save last so restore last ** +}; + +/** + Allocate the save state space and update the instance structure + + @retval EFI_SUCCESS The Save State space was allocated + @retval EFI_OUT_OF_RESOURCES The Save State space failed to allocate +**/ +EFI_STATUS +EFIAPI +AllocateState ( + ) +{ + EFI_STATUS Status; + UINT32 NumRecords; + UINT32 Record; + + NumRecords = sizeof (mSpiHcState) / sizeof (struct SpiHcRegisterState); + + // If PSP is in control, cannot save state + if (mPspMailboxSpiMode) { + return EFI_SUCCESS; + } + + // calculate space needed + mStateSize = 0; + for (Record = 0; Record < NumRecords; Record++) { + mStateSize += mSpiHcState[Record].Size + * mSpiHcState[Record].Count; + } + + mStateRecordCount = NumRecords; + mState = AllocateZeroPool (mStateSize); + if (mState == NULL) { + mStateRecordCount = 0; + Status = EFI_OUT_OF_RESOURCES; + } else { + Status = EFI_SUCCESS; + } + + return Status; +} + +/** + Save the Host controler state to restore after transaction is complete + + @param[in] This SPI host controller Preserve State Protocol; + + @retval EFI_SUCCESS Spi Execute command executed properly + @retval EFI_DEVICE_ERROR Spi Execute command failed +**/ +EFI_STATUS +EFIAPI +SaveState ( + IN CONST SMM_EFI_SPI_HC_STATE_PROTOCOL *This + ) +{ + EFI_STATUS Status; + UINT32 NumRecords; + UINT32 Record; + UINT32 Count; + UINT8 *State; + + Status = EFI_SUCCESS; + + // If PSP is in control, cannot save state + if (mPspMailboxSpiMode) { + return Status; + } + + Status = FchSpiControllerNotBusy (); + if (!EFI_ERROR (Status)) { + State = mState; + NumRecords = mStateRecordCount; + if (!mSmmAlreadySavedState) { + for (Record = 0; Record < NumRecords; Record++) { + switch (mSpiHcState[Record].Size) { + case 0x1: + for (Count = 0; Count < mSpiHcState[Record].Count; Count++) { + *(UINT8 *)State = MmioRead8 ( + mHcAddress + + mSpiHcState[Record].Register + ); + State += 1; + } + + break; + case 0x2: + for (Count = 0; Count < mSpiHcState[Record].Count; Count++) { + *(UINT16 *)State = MmioRead16 ( + mHcAddress + + mSpiHcState[Record].Register + ); + State += 2; + } + + break; + case 0x4: + for (Count = 0; Count < mSpiHcState[Record].Count; Count++) { + *(UINT32 *)State = MmioRead32 ( + mHcAddress + + mSpiHcState[Record].Register + ); + State += 4; + } + + break; + } + } + + mSmmAlreadySavedState = TRUE; + } + } + + return Status; +} + +/** + Restore the Host Controller state + + @param[in] This SPI host controller Preserve State Protocol; + + @retval EFI_SUCCESS Spi Execute command executed properly + @retval EFI_DEVICE_ERROR Spi Execute command failed +**/ +EFI_STATUS +EFIAPI +RestoreState ( + IN CONST SMM_EFI_SPI_HC_STATE_PROTOCOL *This + ) +{ + EFI_STATUS Status; + UINT32 NumRecords; + UINT32 Record; + UINT32 Count; + UINT8 *State; + + Status = EFI_SUCCESS; + + // If PSP is in control, cannot save state + if (mPspMailboxSpiMode) { + return Status; + } + + State = mState; + NumRecords = mStateRecordCount; + if (mSmmAlreadySavedState) { + for (Record = 0; Record < NumRecords; Record++) { + switch (mSpiHcState[Record].Size) { + case 0x1: + for (Count = 0; Count < mSpiHcState[Record].Count; Count++) { + MmioWrite8 ( + mHcAddress + mSpiHcState[Record].Register, + *(UINT8 *)State + ); + State += 1; + } + + break; + case 0x2: + for (Count = 0; Count < mSpiHcState[Record].Count; Count++) { + MmioWrite16 ( + mHcAddress + mSpiHcState[Record].Register, + *(UINT16 *)State + ); + State += 2; + } + + break; + case 0x4: + for (Count = 0; Count < mSpiHcState[Record].Count; Count++) { + MmioWrite32 ( + mHcAddress + mSpiHcState[Record].Register, + *(UINT32 *)State + ); + State += 4; + } + + break; + } + } + + mSmmAlreadySavedState = FALSE; + } + + return Status; +} + +/** + Block SPI Flash Write Enable Opcode. This will block anything that requires + the Opcode equivalent to the SPI Flash Memory Write Enable Opcode. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +FchSpiBlockOpcode ( + IN CONST SMM_EFI_SPI_HC_STATE_PROTOCOL *This, + IN UINT8 Opcode + ) +{ + EFI_STATUS Status; + + // If PSP is in control, cannot save state + if (mPspMailboxSpiMode) { + return EFI_SUCCESS; + } + + Status = InternalFchSpiBlockOpcode (mHcAddress, Opcode); + return Status; +} + +/** + Un-Block SPI Flash Write Enable Opcode. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +FchSpiUnblockOpcode ( + IN CONST SMM_EFI_SPI_HC_STATE_PROTOCOL *This, + IN UINT8 Opcode + ) +{ + EFI_STATUS Status; + + // If PSP is in control, cannot save state + if (mPspMailboxSpiMode) { + return EFI_SUCCESS; + } + + Status = InternalFchSpiUnblockOpcode (mHcAddress, Opcode); + return Status; +} + +/** + Un-Block any blocked SPI Opcodes. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +FchSpiUnblockAllOpcodes ( + IN CONST SMM_EFI_SPI_HC_STATE_PROTOCOL *This + ) +{ + EFI_STATUS Status; + + // If PSP is in control, cannot save state + if (mPspMailboxSpiMode) { + return EFI_SUCCESS; + } + + Status = InternalFchSpiUnblockAllOpcodes (mHcAddress); + return Status; +} + +/** + Lock SPI host controller registers. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +FchSpiLockSpiHostControllerRegisters ( + IN CONST SMM_EFI_SPI_HC_STATE_PROTOCOL *This + ) +{ + EFI_STATUS Status; + + // If PSP is in control, cannot save state + if (mPspMailboxSpiMode) { + return EFI_SUCCESS; + } + + Status = InternalFchSpiLockSpiHostControllerRegisters (mHcAddress); + return Status; +} + +/** + Unlock SPI host controller registers. This unlock function will only work in + SMM. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +FchSpiUnlockSpiHostControllerRegisters ( + IN CONST SMM_EFI_SPI_HC_STATE_PROTOCOL *This + ) +{ + EFI_STATUS Status; + + // If PSP is in control, cannot save state + if (mPspMailboxSpiMode) { + return EFI_SUCCESS; + } + + Status = InternalFchSpiUnlockSpiHostControllerRegisters (mHcAddress); + return Status; +} diff --git a/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/AmdSpiHcSmmState.h b/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/AmdSpiHcSmmState.h new file mode 100644 index 0000000000..12b2fe4ae9 --- /dev/null +++ b/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/AmdSpiHcSmmState.h @@ -0,0 +1,141 @@ +/** @file + + SPI HC SMM state registration function declarations + + Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. + +**/ + +#ifndef AMD_SPI_HC_SMM_STATE_H_ +#define AMD_SPI_HC_SMM_STATE_H_ + +#include +#include +#include +#include "AmdSpiHcInternal.h" + +struct SpiHcRegisterState { + UINT32 Register; + UINT8 Size; // Size in Bytes + UINT8 Count; // Number of contiguous registers to store +}; + +/** + Allocate the save state space and update the instance structure + + @retval EFI_SUCCESS The Save State space was allocated + @retval EFI_OUT_OF_RESOURCES The Save State space failed to allocate +**/ +EFI_STATUS +EFIAPI +AllocateState ( + ); + +/** + Save the Host Controller state to restore after transaction is complete + + @param[in] This SPI host controller Preserve State Protocol; + + @retval EFI_SUCCESS Spi Execute command executed properly + @retval EFI_DEVICE_ERROR Spi Execute command failed +**/ +EFI_STATUS +EFIAPI +SaveState ( + IN CONST SMM_EFI_SPI_HC_STATE_PROTOCOL *This + ); + +/** + Restore the Host Controller state + + @param[in] This SPI host controller Preserve State Protocol; + + @retval EFI_SUCCESS Spi Execute command executed properly + @retval EFI_DEVICE_ERROR Spi Execute command failed +**/ +EFI_STATUS +EFIAPI +RestoreState ( + IN CONST SMM_EFI_SPI_HC_STATE_PROTOCOL *This + ); + +/** + Block SPI Flash Write Enable Opcode. This will block anything that requires + the Opcode equivalent to the SPI Flash Memory Write Enable Opcode. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +FchSpiBlockOpcode ( + IN CONST SMM_EFI_SPI_HC_STATE_PROTOCOL *This, + IN UINT8 Opcode + ); + +/** + Un-Block SPI Flash Write Enable Opcode. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +FchSpiUnblockOpcode ( + IN CONST SMM_EFI_SPI_HC_STATE_PROTOCOL *This, + IN UINT8 Opcode + ); + +/** + Un-Block any blocked SPI Opcodes. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +FchSpiUnblockAllOpcodes ( + IN CONST SMM_EFI_SPI_HC_STATE_PROTOCOL *This + ); + +/** + Lock SPI host controller registers. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +FchSpiLockSpiHostControllerRegisters ( + IN CONST SMM_EFI_SPI_HC_STATE_PROTOCOL *This + ); + +/** + Unlock SPI host controller registers. This unlock function will only work in + SMM. + + RestrictedCmd0..3 (SPIx04[31:0]) will be locked (write protected) when + SPIx00[23:22] not equal 11b, so you can write SPIx00[23:22]=00b to lock them. + Once SPIx00[23:22] = 00b, they can only be written in SMM, + to clear RestrictedCmd0..3, get into SMM, write SPIx00[23:22]=11b, + then you can clear RestrictedCmd0..3 (SPIx04) +**/ +EFI_STATUS +EFIAPI +FchSpiUnlockSpiHostControllerRegisters ( + IN CONST SMM_EFI_SPI_HC_STATE_PROTOCOL *This + ); + +#endif // __AMD_SPI_HC_SMM_STATE_H__ diff --git a/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/SpiHcPlatformLib.c b/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/SpiHcPlatformLib.c new file mode 100644 index 0000000000..d16ad502ff --- /dev/null +++ b/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/SpiHcPlatformLib.c @@ -0,0 +1,362 @@ +/** @file + + SPI HC platform library implementation. This code touches the SPI controllers and performs + the hardware transaction + + Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "AmdSpiHcInternal.h" +#include +#include + +extern BOOLEAN mPspMailboxSpiMode; +extern SPI_COMMUNICATION_BUFFER mSpiCommunicationBuffer; +extern EFI_PHYSICAL_ADDRESS mHcAddress; + +/** + This function reports the device path of SPI host controller. This is needed in order for the SpiBus + to match the correct SPI_BUS to the SPI host controller + + @param[out] DevicePath The device path for this SPI HC is returned in this variable + + @retval EFI_SUCCESS +*/ +EFI_STATUS +EFIAPI +GetSpiHcDevicePath ( + OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath + ) +{ + *DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)&mFchDevicePath; + return EFI_SUCCESS; +} + +/** + This is the platform specific Spi Chip select function. + Assert or deassert the SPI chip select. + + This routine is called at TPL_NOTIFY. + Update the value of the chip select line for a SPI peripheral. The SPI bus + layer calls this routine either in the board layer or in the SPI controller + to manipulate the chip select pin at the start and end of a SPI transaction. + + @param[in] This Pointer to an EFI_SPI_HC_PROTOCOL structure. + @param[in] SpiPeripheral The address of an EFI_SPI_PERIPHERAL data structure + describing the SPI peripheral whose chip select pin + is to be manipulated. The routine may access the + ChipSelectParameter field to gain sufficient + context to complete the operati on. + @param[in] PinValue The value to be applied to the chip select line of + the SPI peripheral. + + @retval EFI_SUCCESS The chip select was set as requested + @retval EFI_NOT_READY Support for the chip select is not properly + initialized + @retval EFI_INVALID_PARAMETER The ChipSelect value or its contents are + invalid + +**/ +EFI_STATUS +EFIAPI +PlatformSpiHcChipSelect ( + IN CONST EFI_SPI_HC_PROTOCOL *This, + IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral, + IN BOOLEAN PinValue + ) +{ + EFI_STATUS Status; + CHIP_SELECT_PARAMETERS *ChipSelectParameter; + + Status = EFI_DEVICE_ERROR; + ChipSelectParameter = SpiPeripheral->ChipSelectParameter; + + if (ChipSelectParameter->OrValue <= 1) { + if (!mPspMailboxSpiMode) { + MmioAndThenOr8 ( + mHcAddress + FCH_SPI_MMIO_REG1D, + ChipSelectParameter->AndValue, + ChipSelectParameter->OrValue + ); + Status = EFI_SUCCESS; + } else { + mSpiCommunicationBuffer.SpiCommand[0].ChipSelect = + ChipSelectParameter->OrValue + 1; + Status = EFI_SUCCESS; + } + } else { + Status = EFI_INVALID_PARAMETER; + } + + return Status; +} + +/** + This function is the platform specific SPI clock function. + Set up the clock generator to produce the correct clock frequency, phase and + polarity for a SPI chip. + + This routine is called at TPL_NOTIFY. + This routine updates the clock generator to generate the correct frequency + and polarity for the SPI clock. + + @param[in] This Pointer to an EFI_SPI_HC_PROTOCOL structure. + @param[in] SpiPeripheral Pointer to a EFI_SPI_PERIPHERAL data structure from + which the routine can access the ClockParameter, + ClockPhase and ClockPolarity fields. The routine + also has access to the names for the SPI bus and + chip which can be used during debugging. + @param[in] ClockHz Pointer to the requested clock frequency. The SPI + host controller will choose a supported clock + frequency which is less then or equal to this + value. Specify zero to turn the clock generator + off. The actual clock frequency supported by the + SPI host controller will be returned. + + @retval EFI_SUCCESS The clock was set up successfully + @retval EFI_UNSUPPORTED The SPI controller was not able to support the + frequency requested by ClockHz + +**/ +EFI_STATUS +EFIAPI +PlatformSpiHcClock ( + IN CONST EFI_SPI_HC_PROTOCOL *This, + IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral, + IN UINT32 *ClockHz + ) +{ + EFI_STATUS Status; + UINT32 InternalClockHz; + UINT16 InternalClockValue; + + Status = EFI_SUCCESS; + InternalClockHz = *ClockHz; + InternalClockValue = 0x00; + if ((SpiPeripheral->MaxClockHz != 0) && + (SpiPeripheral->MaxClockHz < InternalClockHz)) + { + InternalClockHz = SpiPeripheral->MaxClockHz; + } + + if ((SpiPeripheral->SpiPart->MaxClockHz != 0) && + (SpiPeripheral->SpiPart->MaxClockHz < InternalClockHz)) + { + InternalClockHz = SpiPeripheral->SpiPart->MaxClockHz; + } + + if ((SpiPeripheral->SpiPart->MinClockHz != 0) && + (SpiPeripheral->SpiPart->MinClockHz > InternalClockHz)) + { + Status = EFI_UNSUPPORTED; + } + + if (!EFI_ERROR (Status)) { + if (InternalClockHz >= MHz (100)) { + InternalClockValue = 0x4; + } else if (InternalClockHz >= MHz (66)) { + InternalClockValue = 0x0; + } else if (InternalClockHz >= MHz (33)) { + InternalClockValue = 0x1; + } else if (InternalClockHz >= MHz (22)) { + InternalClockValue = 0x2; + } else if (InternalClockHz >= MHz (16)) { + InternalClockValue = 0x3; + } else if (InternalClockHz >= KHz (800)) { + InternalClockValue = 0x5; + } else { + Status = EFI_UNSUPPORTED; + } + + if (!EFI_ERROR (Status)) { + if (!mPspMailboxSpiMode) { + // Enable UseSpi100 + MmioOr8 ( + mHcAddress + FCH_SPI_MMIO_REG20, + BIT0 + ); + // Set the Value for NormSpeed and FastSpeed + InternalClockValue = InternalClockValue << 12 | InternalClockValue << 8; + MmioAndThenOr16 ( + mHcAddress + FCH_SPI_MMIO_REG22, + 0x00FF, + InternalClockValue + ); + } else { + mSpiCommunicationBuffer.SpiCommand[0].Frequency = + (UINT8)InternalClockValue; + } + } + } + + return Status; +} + +/** + This function is the platform specific SPI transaction function + Perform the SPI transaction on the SPI peripheral using the SPI host + controller. + + This routine is called at TPL_NOTIFY. + This routine synchronously returns EFI_SUCCESS indicating that the + asynchronous SPI transaction was started. The routine then waits for + completion of the SPI transaction prior to returning the final transaction + status. + + @param[in] This Pointer to an EFI_SPI_HC_PROTOCOL structure. + @param[in] BusTransaction Pointer to a EFI_SPI_BUS_ TRANSACTION containing + the description of the SPI transaction to perform. + + @retval EFI_SUCCESS The transaction completed successfully + @retval EFI_BAD_BUFFER_SIZE The BusTransaction->WriteBytes value is invalid, + or the BusTransaction->ReadinBytes value is + invalid + @retval EFI_UNSUPPORTED The BusTransaction-> Transaction Type is + unsupported + @retval EFI_DEVICE_ERROR SPI Host Controller failed transaction + +**/ +EFI_STATUS +EFIAPI +PlatformSpiHcTransaction ( + IN CONST EFI_SPI_HC_PROTOCOL *This, + IN EFI_SPI_BUS_TRANSACTION *BusTransaction + ) +{ + EFI_STATUS Status; + UINT8 Opcode; + UINT32 WriteBytes; + UINT8 *WriteBuffer; + UINT32 ReadBytes; + UINT8 *ReadBuffer; + EFI_PHYSICAL_ADDRESS HcAddress; + + WriteBytes = BusTransaction->WriteBytes; + WriteBuffer = BusTransaction->WriteBuffer; + + ReadBytes = BusTransaction->ReadBytes; + ReadBuffer = BusTransaction->ReadBuffer; + + if ( (WriteBytes > This->MaximumTransferBytes + 6) + || (ReadBytes > (This->MaximumTransferBytes + 6 - WriteBytes)) + || ((WriteBytes != 0) && (WriteBuffer == NULL)) + || ((ReadBytes != 0) && (ReadBuffer == NULL))) + { + return EFI_BAD_BUFFER_SIZE; + } + + Opcode = 0; + if (WriteBytes >= 1) { + Opcode = WriteBuffer[0]; + // Skip Opcode + WriteBytes -= 1; + WriteBuffer += 1; + } + + Status = EFI_SUCCESS; + HcAddress = mHcAddress; + + if (!mPspMailboxSpiMode) { + Status = FchSpiControllerNotBusy (); + if (!EFI_ERROR (Status)) { + MmioWrite8 ( + HcAddress + FCH_SPI_MMIO_REG48_TXBYTECOUNT, + (UINT8)WriteBytes + ); + MmioWrite8 ( + HcAddress + FCH_SPI_MMIO_REG4B_RXBYTECOUNT, + (UINT8)ReadBytes + ); + + // Fill in Write Data including Address + if (WriteBytes != 0) { + MmioWriteBuffer8 ( + HcAddress + FCH_SPI_MMIO_REG80_FIFO, + WriteBytes, + WriteBuffer + ); + } + + // Set Opcode + MmioWrite8 ( + HcAddress + FCH_SPI_MMIO_REG45_CMDCODE, + Opcode + ); + + // Execute the Transaction + Status = FchSpiExecute (); + if (!EFI_ERROR (Status)) { + if (ReadBytes != 0) { + MmioReadBuffer8 ( + HcAddress + + FCH_SPI_MMIO_REG80_FIFO + + WriteBytes, + ReadBytes, + ReadBuffer + ); + } + } + } + } else { + // Execute SPI transaction through PSP Mailbox + mSpiCommunicationBuffer.SpiCommand[0].OpCode = Opcode; + mSpiCommunicationBuffer.SpiCommand[0].BytesToTx = (UINT8)WriteBytes; + if (WriteBytes != 0) { + CopyMem ( + &mSpiCommunicationBuffer.SpiCommand[0].Buffer, + WriteBuffer, + WriteBytes + ); + } + + mSpiCommunicationBuffer.SpiCommand[0].BytesToRx = (UINT8)ReadBytes; + mSpiCommunicationBuffer.CommandCount = 1; + mSpiCommunicationBuffer.SpiCommunicationResult.Value = 0x0; + mSpiCommunicationBuffer.ReadyToRun = TRUE; + Status = PspExecuteSpiCommand (); + if (!EFI_ERROR (Status)) { + if (mSpiCommunicationBuffer.SpiCommunicationResult.Value == 0x1000) { + Status = EFI_INVALID_PARAMETER; + } else { + switch (mSpiCommunicationBuffer.SpiCommunicationResult.Field.Command0Result) { + case SPI_COMMAND_MALFORMED: + Status = EFI_INVALID_PARAMETER; + break; + case SPI_COMMAND_COMPLETED: + Status = EFI_SUCCESS; + if (ReadBytes > 0) { + CopyMem ( + ReadBuffer, + &mSpiCommunicationBuffer.SpiCommand[0].Buffer[0] + WriteBytes, + ReadBytes + ); + } + + break; + case SPI_COMMAND_NOT_ALLOWED: + Status = EFI_WRITE_PROTECTED; + break; + default: + Status = EFI_DEVICE_ERROR; + break; + } + } + } + } + + return Status; +} diff --git a/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/SpiHcPlatformLib.uni b/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/SpiHcPlatformLib.uni new file mode 100644 index 0000000000..6dc0364266 --- /dev/null +++ b/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/SpiHcPlatformLib.uni @@ -0,0 +1,8 @@ +// /***************************************************************************** +// * +// * Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. +// * +// * + +#string STR_PROPERTIES_MODULE_NAME +#language en-US "AMD SPI Host controller library" diff --git a/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/SpiHcPlatformLibDxe.c b/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/SpiHcPlatformLibDxe.c new file mode 100644 index 0000000000..9c97d25e69 --- /dev/null +++ b/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/SpiHcPlatformLibDxe.c @@ -0,0 +1,63 @@ +/** @file + + Implementation of SpiHcPlatformLibrary for DXE + + Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. + +**/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "AmdSpiHcInternal.h" +#include +#include + +#define SPI_HC_MAXIMUM_TRANSFER_BYTES 64 + +// Global variables to manage the platform-dependent SPI host controller +BOOLEAN mPspMailboxSpiMode; +SPI_COMMUNICATION_BUFFER mSpiCommunicationBuffer; +EFI_PHYSICAL_ADDRESS mHcAddress; + +/** + This function reports the details of the SPI Host Controller to the SpiHc driver. + + @param[out] Attributes The suported attributes of the SPI host controller + @param[out] FrameSizeSupportMask The suported FrameSizeSupportMask of the SPI host controller + @param[out] MaximumTransferBytes The suported MaximumTransferBytes of the SPI host controller + + @retval EFI_SUCCESS SPI_HOST_CONTROLLER_INSTANCE was allocated properly + @retval EFI_OUT_OF_RESOURCES The SPI_HOST_CONTROLLER_INSTANCE could not be allocated +*/ +EFI_STATUS +EFIAPI +GetPlatformSpiHcDetails ( + OUT UINT32 *Attributes, + OUT UINT32 *FrameSizeSupportMask, + OUT UINT32 *MaximumTransferBytes + ) +{ + // Fill in the SPI Host Controller Protocol + *Attributes = HC_SUPPORTS_WRITE_THEN_READ_OPERATIONS | + HC_SUPPORTS_READ_ONLY_OPERATIONS | + HC_SUPPORTS_WRITE_ONLY_OPERATIONS; + *FrameSizeSupportMask = FCH_SPI_FRAME_SIZE_SUPPORT_MASK; + *MaximumTransferBytes = SPI_HC_MAXIMUM_TRANSFER_BYTES; + + // fill in Platform specific global variables + mHcAddress = ( + PciSegmentRead32 ( + PCI_SEGMENT_LIB_ADDRESS (0x00, FCH_LPC_BUS, FCH_LPC_DEV, FCH_LPC_FUNC, FCH_LPC_REGA0) + ) + ) & 0xFFFFFF00; + mPspMailboxSpiMode = TRUE; + return EFI_SUCCESS; +} diff --git a/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/SpiHcPlatformLibDxe.inf b/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/SpiHcPlatformLibDxe.inf new file mode 100644 index 0000000000..c5a9e3b6a1 --- /dev/null +++ b/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/SpiHcPlatformLibDxe.inf @@ -0,0 +1,59 @@ +#/** @file +# +# SpiHcPlatformLibrary DXE_DRIVER inf +# +# Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. +# +#**/ +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = SpiHcPlatformLibDxe + FILE_GUID = 3C230948-6DF5-4802-8177-967A190579CF + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 0.1 + PI_SPECIFICATION_VERSION = 0x0001000A + LIBRARY_CLASS = SpiHcPlatformLib + +[Packages] + AgesaModulePkg/AgesaCommonModulePkg.dec + AgesaPkg/AgesaPkg.dec + AmdPlatformPkg/AmdPlatformPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[LibraryClasses] + AmdPspRomArmorLib + BaseLib + BaseMemoryLib + DebugLib + IoLib + MemoryAllocationLib + PcdLib + PciSegmentLib + TimerLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiLib + UefiRuntimeServicesTableLib + +[Sources] + SpiHcPlatformLibDxe.c + SpiHcPlatformLib.c + AmdSpiHcInternal.h + AmdSpiHcInternal.c + +[Protocols] + gEfiSpiHcProtocolGuid + +[FeaturePcd] + gAmdPlatformPkgTokenSpaceGuid.PcdRomArmorEnable + +[FixedPcd] + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSpiRetryCount + gEfiMdePkgTokenSpaceGuid.PcdSpiNorFlashOperationDelayMicroseconds + +[Depex] + TRUE + +[UserExtensions.TianoCore."ExtraFiles"] + SpiHcPlatformLib.uni diff --git a/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/SpiHcPlatformLibSmm.c b/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/SpiHcPlatformLibSmm.c new file mode 100644 index 0000000000..e904f13e69 --- /dev/null +++ b/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/SpiHcPlatformLibSmm.c @@ -0,0 +1,182 @@ +/** @file + + Implementation of SpiHcPlatformLibrary for SMM + + Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. + +**/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "AmdSpiHcInternal.h" +#include "AmdSpiHcSmmState.h" + +#define SPI_HC_MAXIMUM_TRANSFER_BYTES 64 + +EFI_HANDLE mSpiStateHandle = 0; + +// Global variables to manage the platform-dependent SPI host controller when in DXE or SMM +BOOLEAN mPspMailboxSpiMode; +SPI_COMMUNICATION_BUFFER mSpiCommunicationBuffer; +VOID *mRegistration; +EFI_PHYSICAL_ADDRESS mHcAddress; + +// SMM specific global variables to manage the platform-dependent SPI host controller +SMM_EFI_SPI_HC_STATE_PROTOCOL mStateProtocol; +BOOLEAN mSmmAlreadySavedState; +VOID *mState; +UINT32 mStateSize; +UINT32 mStateRecordCount; + +/** + SPI host controller event notify callback to lock down the SPI chipset + + @param + @param + + @retval +**/ +EFI_STATUS +EFIAPI +AmdSpiHcEventNotify ( + IN CONST EFI_GUID *Protocol, + IN VOID *Interface, + IN EFI_HANDLE Handle + ) +{ + EFI_STATUS Status; + EFI_SPI_HC_PROTOCOL *SpiHc; + SPI_WHITE_LIST *SpiWhitelist; + SMM_EFI_SPI_HC_STATE_PROTOCOL *SpiStateProtocol; + + // There can only be one SPI host controller driver in SMM + Status = gMmst->MmLocateProtocol ( + &gEfiSpiSmmHcProtocolGuid, + NULL, + (VOID **)&SpiHc + ); + + // Call PSP MailBox to change to PSP SPI mode + Status = gMmst->MmLocateProtocol ( + &gAmdSpiHcStateProtocolGuid, + NULL, + (VOID **)&SpiStateProtocol + ); + + SpiStateProtocol->Lock (SpiStateProtocol); + Status = PspEnterSmmOnlyMode (&mSpiCommunicationBuffer); + + if (!EFI_ERROR (Status)) { + mPspMailboxSpiMode = TRUE; + } else { + return EFI_DEVICE_ERROR; + } + + if (FeaturePcdGet (PcdRomArmorWhitelistEnable)) { + // Retrieve allocated Whitelist table + Status = GetPspRomArmorWhitelist (&SpiWhitelist); + if (EFI_ERROR (Status)) { + if (SpiWhitelist != NULL) { + FreePool (SpiWhitelist); + } + + return Status; + } + + // Send Whitelist to PSP + Status = PspEnforceWhitelist (SpiWhitelist); + if (SpiWhitelist != NULL) { + FreePool (SpiWhitelist); + } + } + + return Status; +} + +/** + This function reports the details of the SPI Host Controller to the SpiHc driver. + + @param[out] Attributes The suported attributes of the SPI host controller + @param[out] FrameSizeSupportMask The suported FrameSizeSupportMask of the SPI host controller + @param[out] MaximumTransferBytes The suported MaximumTransferBytes of the SPI host controller + + @retval EFI_SUCCESS SPI_HOST_CONTROLLER_INSTANCE was allocated properly + @retval EFI_OUT_OF_RESOURCES The SPI_HOST_CONTROLLER_INSTANCE could not be allocated +*/ +EFI_STATUS +EFIAPI +GetPlatformSpiHcDetails ( + OUT UINT32 *Attributes, + OUT UINT32 *FrameSizeSupportMask, + OUT UINT32 *MaximumTransferBytes + ) +{ + EFI_STATUS Status; + + // Fill in the SPI Host Controller Protocol + *Attributes = HC_SUPPORTS_WRITE_THEN_READ_OPERATIONS | + HC_SUPPORTS_READ_ONLY_OPERATIONS | + HC_SUPPORTS_WRITE_ONLY_OPERATIONS; + *FrameSizeSupportMask = FCH_SPI_FRAME_SIZE_SUPPORT_MASK; + *MaximumTransferBytes = SPI_HC_MAXIMUM_TRANSFER_BYTES; + + // Set platform specific global variables + mPspMailboxSpiMode = FALSE; // not supported in SMM + mHcAddress = ( + PciSegmentRead32 ( + PCI_SEGMENT_LIB_ADDRESS (0x00, FCH_LPC_BUS, FCH_LPC_DEV, FCH_LPC_FUNC, FCH_LPC_REGA0) + ) + ) & 0xFFFFFF00; + + // Allocate Host Controller save state space + Status = AllocateState (); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + return EFI_OUT_OF_RESOURCES; + } + + // Fill in the SPI HC Save State Protocol + mStateProtocol.SaveState = SaveState; + mStateProtocol.RestoreState = RestoreState; + mStateProtocol.Lock = FchSpiLockSpiHostControllerRegisters; + mStateProtocol.Unlock = FchSpiUnlockSpiHostControllerRegisters; + mStateProtocol.BlockOpcode = FchSpiBlockOpcode; + mStateProtocol.UnblockOpcode = FchSpiUnblockOpcode; + mStateProtocol.UnblockAllOpcodes = FchSpiUnblockAllOpcodes; + + Status = gMmst->MmInstallProtocolInterface ( + &mSpiStateHandle, + &gAmdSpiHcStateProtocolGuid, + EFI_NATIVE_INTERFACE, + &mStateProtocol + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_VERBOSE, "Error installing gAmdSpiHcStateProtocolGuid\n")); + } + + Status = gMmst->MmRegisterProtocolNotify ( + &gEfiMmReadyToLockProtocolGuid, + AmdSpiHcEventNotify, + &mRegistration + ); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_VERBOSE, "Error registering gEfiMmReadyToLockProtocolGuid\n")); + } + + return Status; +} diff --git a/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/SpiHcPlatformLibSmm.inf b/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/SpiHcPlatformLibSmm.inf new file mode 100644 index 0000000000..158bf5fa1f --- /dev/null +++ b/Platform/AMD/TurinBoard/Library/SpiHcRomArmorPlatformLib/SpiHcPlatformLibSmm.inf @@ -0,0 +1,64 @@ +#/** @file +# +# SpiHcPlatformLibrary DXE_SMM_DRIVER inf +# +# Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. +# +#**/ +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = SpiHcPlatformLibSmm + FILE_GUID = 6D856A06-B502-49D5-80D5-10A0BA4EDB4D + MODULE_TYPE = DXE_SMM_DRIVER + VERSION_STRING = 0.1 + PI_SPECIFICATION_VERSION = 0x0001000A + LIBRARY_CLASS = SpiHcPlatformLib + +[Packages] + AgesaModulePkg/AgesaCommonModulePkg.dec + AgesaPkg/AgesaPkg.dec + AmdPlatformPkg/AmdPlatformPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[LibraryClasses] + AmdPspRomArmorLib + BaseLib + BaseMemoryLib + DebugLib + IoLib + MemoryAllocationLib + MmServicesTableLib + PcdLib + PciSegmentLib + PlatformPspRomArmorWhitelistLib + TimerLib + UefiDriverEntryPoint + +[Sources] + SpiHcPlatformLibSmm.c + SpiHcPlatformLib.c + AmdSpiHcInternal.h + AmdSpiHcInternal.c + AmdSpiHcSmmState.h + AmdSpiHcSmmState.c + +[Protocols] + gEfiSmmVariableProtocolGuid + gEfiSpiSmmHcProtocolGuid + gAmdSpiHcStateProtocolGuid + gEfiMmReadyToLockProtocolGuid + +[FeaturePcd] + gAmdPlatformPkgTokenSpaceGuid.PcdRomArmorEnable + gAmdPlatformPkgTokenSpaceGuid.PcdRomArmorWhitelistEnable + +[FixedPcd] + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSpiRetryCount + gEfiMdePkgTokenSpaceGuid.PcdSpiNorFlashOperationDelayMicroseconds + +[Depex] + TRUE + +[UserExtensions.TianoCore."ExtraFiles"] + SpiHcPlatformLib.uni diff --git a/Platform/AMD/TurinBoard/OnyxBoardPkg/Include/Dsc/Smbios.dsc b/Platform/AMD/TurinBoard/OnyxBoardPkg/Include/Dsc/Smbios.dsc new file mode 100644 index 0000000000..be56488d73 --- /dev/null +++ b/Platform/AMD/TurinBoard/OnyxBoardPkg/Include/Dsc/Smbios.dsc @@ -0,0 +1,204 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All rights reserved. +#; +#;****************************************************************************** +# +## @file +# Smbios Platform description. +# +## + +[PcdsFixedAtBuild] + #**************************************************************************** + # COMMON SMBIOS + #**************************************************************************** + # + # IPMI Interface Type + # + # 0 - Unknown + # 1 - KCS + # 2 - SMIC + # 3 - BT + # 4 - SSIF + gAmdPlatformPkgTokenSpaceGuid.PcdIpmiInterfaceType|1 + + # SMBIOS Type 4 Processor Information + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSerialNumberSocket0|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosAssetTagSocket0|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosPartNumberSocket0|"To be filled by O.E.M." + +# AMD SMBIOS Type 8 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8Number|10 + + # AMD SMBIOS Type 9 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics1.Provides33Volts|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics2.BifurcationSupported|1 + + # Port #0 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.IntDesiganatorStr|"J11" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.ExtDesiganatorStr|"USB3-R" + + # Port #1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.IntDesiganatorStr|"J20" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.ExtDesiganatorStr|"USB3-R" + + # Port #2 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].DesinatorStr.IntDesiganatorStr|"J1F" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].DesinatorStr.ExtDesiganatorStr|"USB3-F" + + # Port #3 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].DesinatorStr.IntDesiganatorStr|"J2F" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].DesinatorStr.ExtDesiganatorStr|"USB3-F" + + # Port #4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalConnectorType|PortConnectorTypeDB15Female + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.PortType|PortTypeVideoPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.IntDesiganatorStr|"J2" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.ExtDesiganatorStr|"VGA-R" + + # Port #5 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalConnectorType|PortConnectorTypeDB15Female + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.PortType|PortTypeVideoPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.IntDesiganatorStr|"J3-F" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.ExtDesiganatorStr|"VGA-F" + + # Port #6 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.ExternalConnectorType|PortConnectorTypeDB9Female + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.PortType|PortTypeSerial16550ACompatible + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].DesinatorStr.IntDesiganatorStr|"J1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].DesinatorStr.ExtDesiganatorStr|"Serial Port Header" + + # Port #7 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.ExternalConnectorType|PortConnectorTypeRJ45 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.PortType|PortTypeNetworkPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].DesinatorStr.IntDesiganatorStr|"J15" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].DesinatorStr.ExtDesiganatorStr|"MGMT RJ45 Port" + + # Port #8 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.InternalConnectorType|PortConnectorTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.PortType|PortTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].DesinatorStr.IntDesiganatorStr|"J75 M2_0" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].DesinatorStr.ExtDesiganatorStr|{0} + + # Port #9 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.InternalConnectorType|PortConnectorTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.PortType|PortTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].DesinatorStr.IntDesiganatorStr|"J77 M2_1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].DesinatorStr.ExtDesiganatorStr|{0} + + # AMD SMBIOS Type 41 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41Number|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].ReferenceDesignation|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceType|OnBoardDeviceExtendedTypeEthernet + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceEnabled|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceTypeInstance|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].VendorId|0x14E4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceId|0x165F + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].RefDesignationStr|"Onboard Ethernet" + +[PcdsDynamicDefault] + #**************************************************************************** + # BASIC SMBIOS + #**************************************************************************** + # + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0305 + # SMBIOS Type 0 BIOS Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosReleaseDate|"$(RELEASE_DATE)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosVersion|"$(FIRMWARE_VERSION_STR)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Size|32 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Unit|0x00 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PlugAndPlayIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.EDDSpecificationIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy525_12IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_720IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_288IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrintScreenIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Keyboard8042IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.SerialIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrinterIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.CgaMonoIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[0]|0x01 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[1]|0x0C + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringVendor|"AMD Corporation" + + # SMBIOS Type 1 System Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringFamily|$(AMD_PROCESSOR) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1SystemInformation.Uuid|{GUID("3E35E28F-C98B-481B-BA7C-97C712982509")} + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringSerialNumber|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringVersion|"To be filled by O.E.M." + + # SMBIOS Type 2 Baseboard Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringVersion|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringAssetTag|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringLocationInChassis|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringSerialNumber|"To be filled by O.E.M." + + # SMBIOS Type 3 System Enclosure Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringVersion|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringAssetTag|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSKUNumber|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSerialNumber|"To be filled by O.E.M." + + # SMBIOS Type 11 OEM Strings + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStringsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStrings|{"To be filled by O.E.M."} + + # SMBIOS Type 12 System Configuration Options + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptionsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptions|{"To be filled by O.E.M."} + +[Components.X64] + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + SystemInformation/SmbiosFeaturePkg/SmbiosBasicDxe/SmbiosBasicDxe.inf + AmdPlatformPkg/Universal/SmbiosCommonDxe/SmbiosCommonDxe.inf{ + + PciSegmentLib|MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.inf + PciSegmentInfoLib|AgesaPkg/Addendum/PciSegments/PciExpressPciSegmentInfoLib/PciExpressPciSegmentInfoLib.inf + } diff --git a/Platform/AMD/TurinBoard/OnyxBoardPkg/Project.dsc b/Platform/AMD/TurinBoard/OnyxBoardPkg/Project.dsc new file mode 100644 index 0000000000..354e14610e --- /dev/null +++ b/Platform/AMD/TurinBoard/OnyxBoardPkg/Project.dsc @@ -0,0 +1,201 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All rights reserved. +#; +#;****************************************************************************** + +# ***************************************************************************** +# Defines passed into build +# RELEASE_DATE +# FIRMWARE_REVISION_NUM +# FIRMWARE_VERSION_STR +# PLATFORM_CRB +# AMD_PROCESSOR +# CBS_INCLUDE +# INTERNAL_IDS +# SIMNOW_SUPPORT +# EMULATION +# ***************************************************************************** + +[Defines] +!ifndef AMD_PROCESSOR + AMD_PROCESSOR = Turin +!endif + PROCESSOR_PATH = $(AMD_PROCESSOR)Board +!ifndef PLATFORM_CRB + PLATFORM_CRB = Onyx +!endif + PLATFORM_NAME = $(PLATFORM_CRB)BoardPkg + PLATFORM_GUID = C3851035-490E-485E-8941-DFFDBDB45F69 + PLATFORM_VERSION = 0.01 + DSC_SPECIFICATION = 1.30 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)_$(AMD_PROCESSOR) +!ifdef $(INTERNAL_IDS) + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_INTERNAL +!else + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_EXTERNAL +!endif + SUPPORTED_ARCHITECTURES = IA32|X64 + BUILD_TARGETS = DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = $(PLATFORM_NAME)/Project.fdf + + DEFINE PEI_ARCH = IA32 + DEFINE DXE_ARCH = X64 + PREBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py prebuild" + POSTBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py postbuild" + + # + # Platform On/Off features are defined here + # + DEFINE SOURCE_DEBUG_ENABLE = FALSE + DEFINE DEBUG_DISPATCH_ENABLE = FALSE + DEFINE DISABLE_SMT = FALSE + + # AGESA Defines to skip Cf9Reset Driver + DEFINE AMD_RESET_DXE_DRIVER_SUPPORT_DISABLED = TRUE + + DEFINE PLATFORM_CRB_TABLE_ID = "ONYX " + + DEFINE SATA_OVERRIDE = FALSE + + !ifdef $(INTERNAL_IDS) + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = FALSE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = TRUE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE + !else + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = FALSE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = FALSE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE + !endif + + # Predefined Fabric Resource + DEFINE PREDEFINED_FABRIC_RESOURCES = TRUE + # use emulated variable store instead of real spirom + # use this flag for early brigup when there is issue + # with accessing the spirom + DEFINE USE_EMULATED_VARIABLE_STORE = $(EMULATION) + + # Multisegment support + DEFINE PCIE_MULTI_SEGMENT = TRUE + + # EDK2 components are starting to use PLATFORMX64_ENABLE in their include + # DSC/FDF files + DEFINE PLATFORMX64_ENABLE = TRUE + + # MACRO used by AGESA FCH include DSC/FDF to exclude legacy CSM support + DEFINE AMD_CSM_SUPPORT_DISABLED = TRUE + + DEFINE ROM3_1TB_REMAP = FALSE + + !ifndef SOC_FAMILY_2 + DEFINE SOC_FAMILY_2 = $(SOC_FAMILY) + !endif + !ifndef SOC_SKU_2 + DEFINE SOC_SKU_2 = $(SOC_SKU) + !endif + !ifndef SOC2_2 + DEFINE SOC2_2 = $(SOC2) + !endif + !ifndef SOC_SKU_TITLE + DEFINE SOC_SKU_TITLE = Brh + !endif + + # Console settings + # + # Background info: + # As per Turin PPR vol7 17.4.10 UART Registers + # There are 3 physical UARTS available for SBIOS. + # UART0 supports flow controls. + # UART1 doest support flow controls. + # UART2 is disabled by AGESA/CPM to enable flow control for UART0. + # Hence only two UARTs (UART0 and UART1) are available for SBIOS. + # MMIO addresses for 4 UART as FEDCF000,FEDCE000,FEDCA000 and FEDC9000 + # + # Platform settings: + # AGESA/CPM enables UART0 and UART1 by setting BIT11 and BIT12 of FchRTDeviceEnableMap. + # If SBIOS wants to use MMIO space then above mentioned reserved MMIO can be used. + # If SBIOS wants UART in legacy mode(to use 0x3F8/0x2F8) then need to set below PCD for + # for respective UART. + # FchUart0LegacyEnable, FchUart1LegacyEnable and FchUart2LegacyEnable + # + # SERIAL_PORT Options: + # NONE + # FCH_MMIO UART0, MMIO + # FCH_IO UART0, 0x3F8 + # BMC_SOL UART1, MMIO + # BMC_SOL_IO UART1, 0x3F8 + # BMC_ESPI eSPI0, 0x3F8 + DEFINE SERIAL_PORT = "BMC_SOL_IO" + DEFINE ESPI_UART = FALSE # Define ESPI_UART to modify APCB tokens + + # + # Simnow Options + # + DEFINE SIMNOW_PORT80_DEBUG = $(EMULATION) + DEFINE USB_SUPPORT = TRUE + DEFINE SATA_SUPPORT = TRUE + DEFINE NVME_SUPPORT = TRUE + + # + # Check undefined variables + # +!ifndef RELEASE_DATE + RELEASE_DATE = 01/01/2023 +!endif +!ifndef FIRMWARE_VERSION_STR + FIRMWARE_VERSION_STR = NONE +!endif +!ifndef FIRMWARE_REVISION_NUM + FIRMWARE_REVISION_NUM = 0x00000000 +!endif + +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +# Add platform includes AGESA, CPM etc +!include $(PROCESSOR_PATH)/Include/Dsc/Platform.inc.dsc + +# Board specific SMBIOS defines +!include $(PLATFORM_NAME)/Include/Dsc/Smbios.dsc + +# Platform Common PCDs +!include $(PROCESSOR_PATH)/Include/Dsc/PlatformCommonPcd.dsc.inc + +# Board specific PCDs +[PcdsFixedAtBuild] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSocketDesignationSocket0|"P0" + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x2020202058594E4F # "ONYX " + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|384 + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1 + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|384 + +[PcdsDynamicDefault] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdEarlyBmcLinkLaneNum|134 + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdXhciOcPolarityCfgLow|TRUE + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdXhciUsb31OcPinSelect|0xFFFF1010 + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdXhciUsb20OcPinSelect|0xFFFFFFFFFFFF1010 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdCfgPlatformPPT|400 + +[PcdsFeatureFlag] + !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 5 + !if $(SIMNOW_SUPPORT) == FALSE || $(EMULATION) == FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|TRUE + !endif + !endif + +####################################### +# Library Includes +####################################### +!include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc +!include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc +!include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc +# do not change the order of include +!include $(PROCESSOR_PATH)/Include/Dsc/ProjectCommon.inc.dsc + diff --git a/Platform/AMD/TurinBoard/OnyxBoardPkg/Project.fdf b/Platform/AMD/TurinBoard/OnyxBoardPkg/Project.fdf new file mode 100644 index 0000000000..d3c90f27ec --- /dev/null +++ b/Platform/AMD/TurinBoard/OnyxBoardPkg/Project.fdf @@ -0,0 +1,36 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All rights reserved. +#; +#;***************************************************************************** + + +############################################################################## +# +# Turin reference board - 2 SPI FLash devices accessible by x86 (selected by DIP-switch): +# 1) 32MB Flash with 10-pin header next to the VGA connector. +# 2) 64MB Flash with 10-pin header at 90-degrees from VGA connector, and also accessible by the BMC. +# +############################################################################## + +[Defines] + # Platform.inc.fdf can contain custom DEFINES, consumed by FlashmMapInclude.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/Platform.inc.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/FlashMapInclude.fdf + + DEFINE EFS_ESPI_BYTE0 = 0x0E + DEFINE EFS_ESPI_BYTE1 = 0xFF +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +!include $(PROCESSOR_PATH)/Include/Fdf/ProjectCommon.inc.fdf + +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ +!include MinPlatformPkg/Include/Fdf/RuleInclude.fdf diff --git a/Platform/AMD/TurinBoard/Override/edk2-platforms/Platform/Intel/MinPlatformPkg/Test/Library/TestPointCheckLib/DxeTestPointCheckLib.c b/Platform/AMD/TurinBoard/Override/edk2-platforms/Platform/Intel/MinPlatformPkg/Test/Library/TestPointCheckLib/DxeTestPointCheckLib.c new file mode 100644 index 0000000000..bb83c3a357 --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2-platforms/Platform/Intel/MinPlatformPkg/Test/Library/TestPointCheckLib/DxeTestPointCheckLib.c @@ -0,0 +1,1315 @@ +/** + Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved. +**/ + +/** @file +Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "TestPointInternal.h" + +GLOBAL_REMOVE_IF_UNREFERENCED EFI_GUID mTestPointSmmCommunciationGuid = TEST_POINT_SMM_COMMUNICATION_GUID; + +VOID +TestPointDumpGcd ( + OUT EFI_GCD_MEMORY_SPACE_DESCRIPTOR **GcdMemoryMap, OPTIONAL + OUT UINTN *GcdMemoryMapNumberOfDescriptors, OPTIONAL + OUT EFI_GCD_IO_SPACE_DESCRIPTOR **GcdIoMap, OPTIONAL + OUT UINTN *GcdIoMapNumberOfDescriptors, OPTIONAL + IN BOOLEAN DumpPrint + ); + +VOID +TestPointDumpUefiMemoryMap ( + OUT EFI_MEMORY_DESCRIPTOR **UefiMemoryMap, OPTIONAL + OUT UINTN *UefiMemoryMapSize, OPTIONAL + OUT UINTN *UefiDescriptorSize, OPTIONAL + IN BOOLEAN DumpPrint + ); + +EFI_STATUS +TestPointCheckUefiMemoryMap ( + VOID + ); + +EFI_STATUS +TestPointCheckUefiMemAttribute ( + VOID + ); + +EFI_STATUS +TestPointCheckPciResource ( + VOID + ); + +EFI_STATUS +TestPointCheckConsoleVariable ( + VOID + ); + +EFI_STATUS +TestPointCheckBootVariable ( + VOID + ); + +VOID +TestPointDumpDevicePath ( + VOID + ); + +EFI_STATUS +TestPointCheckMemoryTypeInformation ( + VOID + ); + +EFI_STATUS +TestPointCheckAcpi ( + VOID + ); + +EFI_STATUS +TestPointCheckAcpiGcdResource ( + VOID + ); + +EFI_STATUS +TestPointCheckHsti ( + VOID + ); + +VOID +TestPointDumpVariable ( + VOID + ); + +EFI_STATUS +TestPointCheckEsrt ( + VOID + ); + +EFI_STATUS +TestPointCheckSmmInfo ( + VOID + ); + +EFI_STATUS +TestPointCheckPciBusMaster ( + VOID + ); + +EFI_STATUS +TestPointCheckLoadedImage ( + VOID + ); + +EFI_STATUS +EFIAPI +TestPointCheckSmiHandlerInstrument ( + VOID + ); + +EFI_STATUS +TestPointCheckUefiSecureBoot ( + VOID + ); + +EFI_STATUS +TestPointCheckPiSignedFvBoot ( + VOID + ); + +EFI_STATUS +TestPointCheckTcgTrustedBoot ( + VOID + ); + +EFI_STATUS +TestPointCheckTcgMor ( + VOID + ); + +EFI_STATUS +TestPointVtdEngine ( + VOID + ); + +VOID * +TestPointGetAcpi ( + IN UINT32 Signature + ); + +GLOBAL_REMOVE_IF_UNREFERENCED ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT mTestPointStruct = { + PLATFORM_TEST_POINT_VERSION, + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + {TEST_POINT_IMPLEMENTATION_ID_PLATFORM_DXE}, + TEST_POINT_FEATURE_SIZE, + {0}, // FeaturesImplemented + {0}, // FeaturesVerified + 0, +}; + +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mFeatureImplemented[TEST_POINT_FEATURE_SIZE]; + +/** + This service verifies bus master enable (BME) is disabled after PCI enumeration. + + Test subject: PCI device BME. + Test overview: Verify BME is cleared. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps results to the debug log. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointPciEnumerationDonePciBusMasterDisabled ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[3] & TEST_POINT_BYTE3_PCI_ENUMERATION_DONE_BUS_MASTER_DISABLED) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointPciEnumerationDonePciBusMasterDisabled - Enter\n")); + + Result = TRUE; + Status = TestPointCheckPciBusMaster (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 3, + TEST_POINT_BYTE3_PCI_ENUMERATION_DONE_BUS_MASTER_DISABLED + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointPciEnumerationDonePciBusMasterDisabled - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies PCI device resource assignment after PCI enumeration. + + Test subject: PCI device resources. + Test overview: Verify all PCI devices have been assigned proper resources. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps PCI resource assignments to the debug log. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointPciEnumerationDonePciResourceAllocated ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[3] & TEST_POINT_BYTE3_PCI_ENUMERATION_DONE_RESOURCE_ALLOCATED) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointPciEnumerationDonePciResourceAllocated - Enter\n")); + + Result = TRUE; + Status = TestPointCheckPciResource (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 3, + TEST_POINT_BYTE3_PCI_ENUMERATION_DONE_RESOURCE_ALLOCATED + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointPciEnumerationDonePciResourceAllocated - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies the DMA ACPI table is reported at the end of DXE. + + Test subject: DMA protection. + Test overview: DMA ACPI table is reported. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the DMA ACPI table to the debug log. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointEndOfDxeDmaAcpiTableFunctional ( + VOID + ) +{ + EFI_STATUS Status; + VOID *Acpi; + + if ((mFeatureImplemented[3] & TEST_POINT_BYTE3_END_OF_DXE_DMA_ACPI_TABLE_FUNCTIONAL) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointEndOfDxeDmaAcpiTableFunctional - Enter\n")); + + Acpi = TestPointGetAcpi (EFI_ACPI_6_5_DMA_REMAPPING_TABLE_SIGNATURE); + if (Acpi == NULL) { + DEBUG ((DEBUG_ERROR, "No DMAR table\n")); + TestPointLibAppendErrorString ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + TEST_POINT_BYTE3_END_OF_DXE_DMA_ACPI_TABLE_FUNCTIONAL_ERROR_CODE \ + TEST_POINT_END_OF_DXE \ + TEST_POINT_BYTE3_END_OF_DXE_DMA_ACPI_TABLE_FUNCTIONAL_ERROR_STRING + ); + Status = EFI_INVALID_PARAMETER; + } else { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 3, + TEST_POINT_BYTE3_END_OF_DXE_DMA_ACPI_TABLE_FUNCTIONAL + ); + Status = EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointEndOfDxeDmaAcpiTableFunctional - Exit\n")); + return Status; +} + +/** + This service verifies DMA protection configuration at the end of DXE. + + Test subject: DMA protection. + Test overview: DMA protection in DXE. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the DMA ACPI table to the debug log. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointEndOfDxeDmaProtectionEnabled ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[3] & TEST_POINT_BYTE3_END_OF_DXE_DMA_PROTECTION_ENABLED) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointEndOfDxeDmaProtectionEnabled - Enter\n")); + + Result = TRUE; + Status = TestPointVtdEngine (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 3, + TEST_POINT_BYTE3_END_OF_DXE_DMA_PROTECTION_ENABLED + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointEndOfDxeDmaProtectionEnabled - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies no 3rd party PCI option ROMs (OPROMs) were dispatched prior to the end of DXE. + + Test subject: 3rd party OPROMs. + Test overview: Verify no 3rd party PCI OPROMs were . + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps PCI resource assignments to the debug log. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointEndOfDxeNoThirdPartyPciOptionRom ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[3] & TEST_POINT_BYTE3_END_OF_DXE_NO_THIRD_PARTY_PCI_OPTION_ROM) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointEndOfDxeNoThirdPartyPciOptionRom - Enter\n")); + + Result = TRUE; + Status = TestPointCheckLoadedImage (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 3, + TEST_POINT_BYTE3_END_OF_DXE_NO_THIRD_PARTY_PCI_OPTION_ROM + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointEndOfDxeNoThirdPartyPciOptionRom - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies the validity of System Management RAM (SMRAM) alignment at SMM Ready To Lock. + + Test subject: SMRAM Information. + Test overview: SMRAM is aligned. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the SMRAM region table to the debug log. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointDxeSmmReadyToLockSmramAligned ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[7] & TEST_POINT_BYTE7_DXE_SMM_READY_TO_LOCK_SMRAM_ALIGNED) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointDxeSmmReadyToLockSmramAligned - Enter\n")); + + Result = TRUE; + Status = TestPointCheckSmmInfo (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 7, + TEST_POINT_BYTE7_DXE_SMM_READY_TO_LOCK_SMRAM_ALIGNED + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointDxeSmmReadyToLockSmramAligned - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies the validity of the Windows SMM Security Mitigation Table (WSMT) at SMM Ready To Lock. + + Test subject: Windows Security SMM Mitigation Table. + Test overview: The table is reported in compliance with the Windows SMM Security Mitigations Table + ACPI table specification. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the WSMT to the debug log. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointDxeSmmReadyToLockWsmtTableFunctional ( + VOID + ) +{ + EFI_STATUS Status; + VOID *Acpi; + + if ((mFeatureImplemented[7] & TEST_POINT_BYTE7_DXE_SMM_READY_TO_LOCK_WSMT_TABLE_FUNCTIONAL) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointDxeSmmReadyToLockWsmtTableFunctional - Enter\n")); + + Acpi = TestPointGetAcpi (EFI_ACPI_WINDOWS_SMM_SECURITY_MITIGATION_TABLE_SIGNATURE); + if (Acpi == NULL) { + DEBUG ((DEBUG_ERROR, "No WSMT table\n")); + TestPointLibAppendErrorString ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + TEST_POINT_BYTE7_DXE_SMM_READY_TO_LOCK_WSMT_TABLE_FUNCTIONAL_ERROR_CODE \ + TEST_POINT_DXE_SMM_READY_TO_LOCK \ + TEST_POINT_BYTE7_DXE_SMM_READY_TO_LOCK_WSMT_TABLE_FUNCTIONAL_ERROR_STRING + ); + Status = EFI_INVALID_PARAMETER; + } else { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 7, + TEST_POINT_BYTE7_DXE_SMM_READY_TO_LOCK_WSMT_TABLE_FUNCTIONAL + ); + Status = EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointDxeSmmReadyToLockWsmtTableFunctional - Exit\n")); + return Status; +} + +/** + This service verifies the validity of the SMM page table at Ready To Boot. + + Test subject: SMM page table. + Test overview: The SMM page table settings matches the SmmMemoryAttribute table. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Reports an error if verification fails. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointDxeSmmReadyToBootSmmPageProtection ( + VOID + ) +{ + EFI_MEMORY_DESCRIPTOR *UefiMemoryMap; + UINTN UefiMemoryMapSize; + UINTN UefiDescriptorSize; + EFI_GCD_MEMORY_SPACE_DESCRIPTOR *GcdMemoryMap; + EFI_GCD_IO_SPACE_DESCRIPTOR *GcdIoMap; + UINTN GcdMemoryMapNumberOfDescriptors; + UINTN GcdIoMapNumberOfDescriptors; + EFI_MEMORY_ATTRIBUTES_TABLE *MemoryAttributesTable; + UINTN MemoryAttributesTableSize; + EFI_STATUS Status; + UINTN CommSize; + UINT64 LongCommSize; + UINT8 *CommBuffer; + EFI_SMM_COMMUNICATE_HEADER *CommHeader; + EFI_SMM_COMMUNICATION_PROTOCOL *SmmCommunication; + UINTN MinimalSizeNeeded; + EDKII_PI_SMM_COMMUNICATION_REGION_TABLE *PiSmmCommunicationRegionTable; + UINT32 Index; + EFI_MEMORY_DESCRIPTOR *Entry; + UINTN Size; + TEST_POINT_SMM_COMMUNICATION_UEFI_GCD_MAP_INFO *CommData; + + if ((mFeatureImplemented[6] & TEST_POINT_BYTE6_SMM_READY_TO_BOOT_SMM_PAGE_LEVEL_PROTECTION) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointDxeSmmReadyToBootSmmPageProtection - Enter\n")); + + TestPointDumpUefiMemoryMap (&UefiMemoryMap, &UefiMemoryMapSize, &UefiDescriptorSize, FALSE); + TestPointDumpGcd (&GcdMemoryMap, &GcdMemoryMapNumberOfDescriptors, &GcdIoMap, &GcdIoMapNumberOfDescriptors, FALSE); + + MemoryAttributesTable = NULL; + MemoryAttributesTableSize = 0; + Status = EfiGetSystemConfigurationTable (&gEfiMemoryAttributesTableGuid, (VOID **)&MemoryAttributesTable); + if (!EFI_ERROR (Status)) { + MemoryAttributesTableSize = sizeof(EFI_MEMORY_ATTRIBUTES_TABLE) + MemoryAttributesTable->DescriptorSize * MemoryAttributesTable->NumberOfEntries; + } + + Status = gBS->LocateProtocol(&gEfiSmmCommunicationProtocolGuid, NULL, (VOID **)&SmmCommunication); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_INFO, "TestPointDxeSmmReadyToBootSmmPageProtection: Locate SmmCommunication protocol - %r\n", Status)); + return EFI_SUCCESS; + } + + MinimalSizeNeeded = OFFSET_OF(EFI_SMM_COMMUNICATE_HEADER, Data) + + sizeof(TEST_POINT_SMM_COMMUNICATION_UEFI_GCD_MAP_INFO) + + UefiMemoryMapSize + + GcdMemoryMapNumberOfDescriptors * sizeof(EFI_GCD_MEMORY_SPACE_DESCRIPTOR) + + GcdIoMapNumberOfDescriptors * sizeof(EFI_GCD_IO_SPACE_DESCRIPTOR) + + MemoryAttributesTableSize; + + Status = EfiGetSystemConfigurationTable( + &gEdkiiPiSmmCommunicationRegionTableGuid, + (VOID **)&PiSmmCommunicationRegionTable + ); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_INFO, "TestPointDxeSmmReadyToBootSmmPageProtection: Get PiSmmCommunicationRegionTable - %r\n", Status)); + return EFI_SUCCESS; + } + ASSERT(PiSmmCommunicationRegionTable != NULL); + Entry = (EFI_MEMORY_DESCRIPTOR *)(PiSmmCommunicationRegionTable + 1); + Size = 0; + for (Index = 0; Index < PiSmmCommunicationRegionTable->NumberOfEntries; Index++) { + if (Entry->Type == EfiConventionalMemory) { + Size = EFI_PAGES_TO_SIZE((UINTN)Entry->NumberOfPages); + if (Size >= MinimalSizeNeeded) { + break; + } + } + Entry = (EFI_MEMORY_DESCRIPTOR *)((UINT8 *)Entry + PiSmmCommunicationRegionTable->DescriptorSize); + } + // EDKII_BIOS_OVERRIDE START + // WA, REVISIT disable the assert + // ASSERT(Index < PiSmmCommunicationRegionTable->NumberOfEntries); + // EDKII_BIOS_OVERRIDE END + + CommBuffer = (UINT8 *)(UINTN)Entry->PhysicalStart; + + CommHeader = (EFI_SMM_COMMUNICATE_HEADER *)&CommBuffer[0]; + CopyMem(&CommHeader->HeaderGuid, &mTestPointSmmCommunciationGuid, sizeof(mTestPointSmmCommunciationGuid)); + CommHeader->MessageLength = MinimalSizeNeeded - OFFSET_OF(EFI_SMM_COMMUNICATE_HEADER, Data); + + CommData = (TEST_POINT_SMM_COMMUNICATION_UEFI_GCD_MAP_INFO *)&CommBuffer[OFFSET_OF(EFI_SMM_COMMUNICATE_HEADER, Data)]; + CommData->Header.Version = TEST_POINT_SMM_COMMUNICATION_VERSION; + CommData->Header.FuncId = TEST_POINT_SMM_COMMUNICATION_FUNC_ID_UEFI_GCD_MAP_INFO; + CommData->Header.Size = CommHeader->MessageLength; + CommData->UefiMemoryMapOffset = sizeof(TEST_POINT_SMM_COMMUNICATION_UEFI_GCD_MAP_INFO); + CommData->UefiMemoryMapSize = UefiMemoryMapSize; + CommData->GcdMemoryMapOffset = CommData->UefiMemoryMapOffset + CommData->UefiMemoryMapSize; + CommData->GcdMemoryMapSize = GcdMemoryMapNumberOfDescriptors * sizeof(EFI_GCD_MEMORY_SPACE_DESCRIPTOR); + CommData->GcdIoMapOffset = CommData->GcdMemoryMapOffset + CommData->GcdMemoryMapSize; + CommData->GcdIoMapSize = GcdIoMapNumberOfDescriptors * sizeof(EFI_GCD_IO_SPACE_DESCRIPTOR); + CommData->UefiMemoryAttributeTableOffset = CommData->GcdIoMapOffset + CommData->GcdIoMapSize; + CommData->UefiMemoryAttributeTableSize = MemoryAttributesTableSize; + + CopyMem ( + (VOID *)(UINTN)((UINTN)CommData + CommData->UefiMemoryMapOffset), + UefiMemoryMap, + (UINTN)CommData->UefiMemoryMapSize + ); + CopyMem ( + (VOID *)(UINTN)((UINTN)CommData + CommData->GcdMemoryMapOffset), + GcdMemoryMap, + (UINTN)CommData->GcdMemoryMapSize + ); + CopyMem ( + (VOID *)(UINTN)((UINTN)CommData + CommData->GcdIoMapOffset), + GcdIoMap, + (UINTN)CommData->GcdIoMapSize + ); + CopyMem ( + (VOID *)(UINTN)((UINTN)CommData + CommData->UefiMemoryAttributeTableOffset), + MemoryAttributesTable, + (UINTN)CommData->UefiMemoryAttributeTableSize + ); + + Status = SafeUint64Add (OFFSET_OF (EFI_SMM_COMMUNICATE_HEADER, Data), CommHeader->MessageLength, &LongCommSize); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_INFO, "TestPointDxeSmmReadyToBootSmmPageProtection: LongCommSize calculation - %r\n", Status)); + return EFI_SUCCESS; + } + + Status = SafeUint64ToUintn (LongCommSize, &CommSize); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_INFO, "TestPointDxeSmmReadyToBootSmmPageProtection: CommSize conversion - %r\n", Status)); + return EFI_SUCCESS; + } + + Status = SmmCommunication->Communicate(SmmCommunication, CommBuffer, &CommSize); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_INFO, "TestPointDxeSmmReadyToBootSmmPageProtection: SmmCommunication - %r\n", Status)); + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointDxeSmmReadyToBootSmmPageProtection - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies SMI handler profiling. + + Test subject: SMI handler profiling. + Test overview: + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the SMI handler profile. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointDxeSmmReadyToBootSmiHandlerInstrument ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[7] & TEST_POINT_BYTE7_DXE_SMM_READY_TO_BOOT_SMI_HANDLER_INSTRUMENT) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointDxeSmmReadyToBootSmiHandlerInstrument - Enter\n")); + + Result = TRUE; + Status = TestPointCheckSmiHandlerInstrument (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 7, + TEST_POINT_BYTE7_DXE_SMM_READY_TO_BOOT_SMI_HANDLER_INSTRUMENT + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointDxeSmmReadyToBootSmiHandlerInstrument - Exit\n")); + return EFI_SUCCESS; +} + +/** + This services verifies the validity of installed ACPI tables at Ready To Boot. + + Test subject: ACPI tables. + Test overview: The ACPI table settings are valid. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the installed ACPI tables. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointReadyToBootAcpiTableFunctional ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[4] & TEST_POINT_BYTE4_READY_TO_BOOT_ACPI_TABLE_FUNCTIONAL) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootAcpiTableFunctional - Enter\n")); + + Result = TRUE; + Status = TestPointCheckAcpi (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 4, + TEST_POINT_BYTE4_READY_TO_BOOT_ACPI_TABLE_FUNCTIONAL + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootAcpiTableFunctional - Exit\n")); + return EFI_SUCCESS; +} + +/** + This services verifies ACPI table resources are in the GCD. + + Test subject: ACPI memory resources. + Test overview: Memory resources are in both ACPI and GCD. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the installed ACPI tables and GCD. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointReadyToBootGcdResourceFunctional ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[4] & TEST_POINT_BYTE4_READY_TO_BOOT_GCD_RESOURCE_FUNCTIONAL) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootGcdResourceFunctional - Enter\n")); + + Result = TRUE; + Status = TestPointCheckAcpiGcdResource (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 4, + TEST_POINT_BYTE4_READY_TO_BOOT_GCD_RESOURCE_FUNCTIONAL + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootGcdResourceFunctional - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies the validity of the memory type information settings. + + Test subject: Memory type information. + Test overview: Inspect an verify memory type information is correct. + Confirm no fragmentation exists in the ACPI/Reserved/Runtime regions. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the memory type information settings to the debug log. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointReadyToBootMemoryTypeInformationFunctional ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[4] & TEST_POINT_BYTE4_READY_TO_BOOT_MEMORY_TYPE_INFORMATION_FUNCTIONAL) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootMemoryTypeInformationFunctional - Enter\n")); + + Result = TRUE; + Status = TestPointCheckMemoryTypeInformation (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + TestPointDumpUefiMemoryMap (NULL, NULL, NULL, TRUE); + Status = TestPointCheckUefiMemoryMap (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 4, + TEST_POINT_BYTE4_READY_TO_BOOT_MEMORY_TYPE_INFORMATION_FUNCTIONAL + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootMemoryTypeInformationFunctional - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies the validity of the memory type information settings. + + Test subject: Memory type information. + Test overview: Inspect an verify memory type information is correct. + Confirm no fragmentation exists in the ACPI/Reserved/Runtime regions. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the memory type information settings to the debug log. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointReadyToBootUefiMemoryAttributeTableFunctional ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[4] & TEST_POINT_BYTE4_READY_TO_BOOT_UEFI_MEMORY_ATTRIBUTE_TABLE_FUNCTIONAL) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootUefiMemoryAttributeTableFunctional - Enter\n")); + + Result = TRUE; + TestPointDumpUefiMemoryMap (NULL, NULL, NULL, TRUE); + TestPointDumpGcd (NULL, NULL, NULL, NULL, TRUE); + Status = TestPointCheckUefiMemAttribute (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 4, + TEST_POINT_BYTE4_READY_TO_BOOT_UEFI_MEMORY_ATTRIBUTE_TABLE_FUNCTIONAL + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootUefiMemoryAttributeTableFunctional - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies the validity of the UEFI memory attribute table. + + Test subject: UEFI memory attribute table. + Test overview: The UEFI memeory attribute table is reported. The image code/data is consistent with the table. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the UEFI image information and the UEFI memory attribute table. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointReadyToBootUefiBootVariableFunctional ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[4] & TEST_POINT_BYTE4_READY_TO_BOOT_UEFI_BOOT_VARIABLE_FUNCTIONAL) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootUefiBootVariableFunctional - Enter\n")); + + Result = TRUE; + TestPointDumpDevicePath (); + TestPointDumpVariable (); + Status = TestPointCheckBootVariable (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 4, + TEST_POINT_BYTE4_READY_TO_BOOT_UEFI_BOOT_VARIABLE_FUNCTIONAL + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootUefiBootVariableFunctional - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies the consle variable information. + + Test subject: Console. + Test overview: Inspect and verify the console variable information is correct. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the console variable information. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointReadyToBootUefiConsoleVariableFunctional ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[4] & TEST_POINT_BYTE4_READY_TO_BOOT_UEFI_CONSOLE_VARIABLE_FUNCTIONAL) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootUefiConsoleVariableFunctional - Enter\n")); + + Result = TRUE; + TestPointDumpDevicePath (); + TestPointDumpVariable (); + Status = TestPointCheckConsoleVariable (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 4, + TEST_POINT_BYTE4_READY_TO_BOOT_UEFI_CONSOLE_VARIABLE_FUNCTIONAL + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootUefiConsoleVariableFunctional - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies the HSTI table. + + Test subject: HSTI table. + Test overview: Verify the HSTI table is reported. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the HSTI table. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointReadyToBootHstiTableFunctional ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[8] & TEST_POINT_BYTE8_READY_TO_BOOT_HSTI_TABLE_FUNCTIONAL) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootHstiTableFunctional - Enter\n")); + + Result = TRUE; + Status = TestPointCheckHsti (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 8, + TEST_POINT_BYTE8_READY_TO_BOOT_HSTI_TABLE_FUNCTIONAL + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootHstiTableFunctional - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies the ESRT table. + + Test subject: ESRT table. + Test overview: Verify the ESRT table is reported. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the ESRT table. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointReadyToBootEsrtTableFunctional ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[8] & TEST_POINT_BYTE8_READY_TO_BOOT_ESRT_TABLE_FUNCTIONAL) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootEsrtTableFunctional - Enter\n")); + + Result = TRUE; + Status = TestPointCheckEsrt (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 8, + TEST_POINT_BYTE8_READY_TO_BOOT_ESRT_TABLE_FUNCTIONAL + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootEsrtTableFunctional - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies UEFI Secure Boot is enabled. + + Test subject: UEFI Secure Boot. + Test overview: Verify the SecureBoot variable is set. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the SecureBoot variable. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointReadyToBootUefiSecureBootEnabled ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[5] & TEST_POINT_BYTE5_READY_TO_BOOT_UEFI_SECURE_BOOT_ENABLED) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootUefiSecureBootEnabled - Enter\n")); + + Result = TRUE; + Status = TestPointCheckUefiSecureBoot (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 5, + TEST_POINT_BYTE5_READY_TO_BOOT_UEFI_SECURE_BOOT_ENABLED + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootUefiSecureBootEnabled - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies Platform Initialization (PI) Signed FV Boot is enabled. + + Test subject: PI Signed FV Boot. + Test overview: Verify PI signed FV boot is enabled. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointReadyToBootPiSignedFvBootEnabled ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[5] & TEST_POINT_BYTE5_READY_TO_BOOT_PI_SIGNED_FV_BOOT_ENABLED) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootPiSignedFvBootEnabled - Enter\n")); + + Result = TRUE; + Status = TestPointCheckPiSignedFvBoot (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 5, + TEST_POINT_BYTE5_READY_TO_BOOT_PI_SIGNED_FV_BOOT_ENABLED + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootPiSignedFvBootEnabled - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies TCG Trusted Boot is enabled. + + Test subject: TCG Trusted Boot. + Test overview: Verify the TCG protocol is installed. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the TCG protocol capability. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointReadyToBootTcgTrustedBootEnabled ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[5] & TEST_POINT_BYTE5_READY_TO_BOOT_TCG_TRUSTED_BOOT_ENABLED) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootTcgTrustedBootEnabled - Enter\n")); + + Result = TRUE; + Status = TestPointCheckTcgTrustedBoot (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 5, + TEST_POINT_BYTE5_READY_TO_BOOT_TCG_TRUSTED_BOOT_ENABLED + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootTcgTrustedBootEnabled - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies TCG Memory Overwrite Request (MOR) is enabled. + + Test subject: TCG MOR. + Test overview: Verify the MOR UEFI variable is set. + Reporting mechanism: Set ADAPTER_INFO_PLATFORM_TEST_POINT_STRUCT. + Dumps the MOR UEFI variable. + + @retval EFI_SUCCESS The test point check was performed successfully. + @retval EFI_UNSUPPORTED The test point check is not supported on this platform. +**/ +EFI_STATUS +EFIAPI +TestPointReadyToBootTcgMorEnabled ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN Result; + + if ((mFeatureImplemented[5] & TEST_POINT_BYTE5_READY_TO_BOOT_TCG_MOR_ENABLED) == 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootTcgMorEnabled - Enter\n")); + + Result = TRUE; + Status = TestPointCheckTcgMor (); + if (EFI_ERROR(Status)) { + Result = FALSE; + } + + if (Result) { + TestPointLibSetFeaturesVerified ( + PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV, + NULL, + 5, + TEST_POINT_BYTE5_READY_TO_BOOT_TCG_MOR_ENABLED + ); + } + + DEBUG ((DEBUG_INFO, "======== TestPointReadyToBootTcgMorEnabled - Exit\n")); + return EFI_SUCCESS; +} + +/** + This service verifies the system state after Exit Boot Services is invoked. + + @retval EFI_SUCCESS The test point check was performed successfully. +**/ +EFI_STATUS +EFIAPI +TestPointExitBootServices ( + VOID + ) +{ + DEBUG ((DEBUG_INFO, "======== TestPointExitBootServices - Enter\n")); + + DEBUG ((DEBUG_INFO, "======== TestPointExitBootServices - Exit\n")); + + return EFI_SUCCESS; +} + +/** + Initialize feature data. + + @param[in] Role The test point role being requested. +**/ +VOID +InitData ( + IN UINT32 Role + ) +{ + EFI_STATUS Status; + + ASSERT (PcdGetSize(PcdTestPointIbvPlatformFeature) == sizeof(mFeatureImplemented)); + CopyMem (mFeatureImplemented, PcdGetPtr(PcdTestPointIbvPlatformFeature), sizeof(mFeatureImplemented)); + + mTestPointStruct.Role = Role; + CopyMem (mTestPointStruct.FeaturesImplemented, mFeatureImplemented, sizeof(mFeatureImplemented)); + Status = TestPointLibSetTable ( + &mTestPointStruct, + sizeof(mTestPointStruct) + ); + if (EFI_ERROR (Status)) { + if (Status != EFI_ALREADY_STARTED) { + ASSERT_EFI_ERROR (Status); + } + } +} + +/** + The library constructor. + + @param ImageHandle The firmware allocated handle for the EFI image. + @param SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The function always return EFI_SUCCESS. +**/ +EFI_STATUS +EFIAPI +DxeTestPointCheckLibConstructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + InitData (PLATFORM_TEST_POINT_ROLE_PLATFORM_IBV); + + return EFI_SUCCESS; +} diff --git a/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassBot.h b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassBot.h new file mode 100644 index 0000000000..066d0e9a31 --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassBot.h @@ -0,0 +1,194 @@ +/** + Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved. +**/ + +/** @file + Definition for the USB mass storage Bulk-Only Transport protocol, + based on the "Universal Serial Bus Mass Storage Class Bulk-Only + Transport" Revision 1.0, September 31, 1999. + +Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+ +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _EFI_USBMASS_BOT_H_ +#define _EFI_USBMASS_BOT_H_ + +extern USB_MASS_TRANSPORT mUsbBotTransport; + +// +// Usb Bulk-Only class specific request +// +#define USB_BOT_RESET_REQUEST 0xFF ///< Bulk-Only Mass Storage Reset +#define USB_BOT_GETLUN_REQUEST 0xFE ///< Get Max Lun +#define USB_BOT_CBW_SIGNATURE 0x43425355 ///< dCBWSignature, tag the packet as CBW +#define USB_BOT_CSW_SIGNATURE 0x53425355 ///< dCSWSignature, tag the packet as CSW +#define USB_BOT_MAX_LUN 0x0F ///< Lun number is from 0 to 15 +#define USB_BOT_MAX_CMDLEN 16 ///< Maximum number of command from command set + +// +// Usb BOT command block status values +// +#define USB_BOT_COMMAND_OK 0x00 ///< Command passed, good status +#define USB_BOT_COMMAND_FAILED 0x01 ///< Command failed +#define USB_BOT_COMMAND_ERROR 0x02 ///< Phase error, need to reset the device + +// +// Usb Bot retry to get CSW, refers to specification[BOT10-5.3, it says 2 times] +// +#define USB_BOT_RECV_CSW_RETRY 3 + +// +// Usb Bot wait device reset complete, set by experience +// +// AMD_EDKII_OVERRIDE START +#define USB_BOT_RESET_DEVICE_STALL (60 * USB_MASS_1_SECOND) +// AMD_EDKII_OVERRIDE END + +// +// Usb Bot transport timeout, set by experience +// +#define USB_BOT_SEND_CBW_TIMEOUT (3 * USB_MASS_1_SECOND) +#define USB_BOT_RECV_CSW_TIMEOUT (3 * USB_MASS_1_SECOND) +#define USB_BOT_RESET_DEVICE_TIMEOUT (3 * USB_MASS_1_SECOND) + +#pragma pack(1) +/// +/// The CBW (Command Block Wrapper) structures used by the USB BOT protocol. +/// +typedef struct { + UINT32 Signature; + UINT32 Tag; + UINT32 DataLen; ///< Length of data between CBW and CSW + UINT8 Flag; ///< Bit 7, 0 ~ Data-Out, 1 ~ Data-In + UINT8 Lun; ///< Lun number. Bits 0~3 are used + UINT8 CmdLen; ///< Length of the command. Bits 0~4 are used + UINT8 CmdBlock[USB_BOT_MAX_CMDLEN]; +} USB_BOT_CBW; + +/// +/// The and CSW (Command Status Wrapper) structures used by the USB BOT protocol. +/// +typedef struct { + UINT32 Signature; + UINT32 Tag; + UINT32 DataResidue; + UINT8 CmdStatus; +} USB_BOT_CSW; +#pragma pack() + +typedef struct { + // + // Put Interface at the first field to make it easy to distinguish BOT/CBI Protocol instance + // + EFI_USB_INTERFACE_DESCRIPTOR Interface; + EFI_USB_ENDPOINT_DESCRIPTOR *BulkInEndpoint; + EFI_USB_ENDPOINT_DESCRIPTOR *BulkOutEndpoint; + UINT32 CbwTag; + EFI_USB_IO_PROTOCOL *UsbIo; +} USB_BOT_PROTOCOL; + +/** + Initializes USB BOT protocol. + + This function initializes the USB mass storage class BOT protocol. + It will save its context which is a USB_BOT_PROTOCOL structure + in the Context if Context isn't NULL. + + @param UsbIo The USB I/O Protocol instance + @param Context The buffer to save the context to + + @retval EFI_SUCCESS The device is successfully initialized. + @retval EFI_UNSUPPORTED The transport protocol doesn't support the device. + @retval Other The USB BOT initialization fails. + +**/ +EFI_STATUS +UsbBotInit ( + IN EFI_USB_IO_PROTOCOL *UsbIo, + OUT VOID **Context OPTIONAL + ); + +/** + Call the USB Mass Storage Class BOT protocol to issue + the command/data/status circle to execute the commands. + + @param Context The context of the BOT protocol, that is, + USB_BOT_PROTOCOL + @param Cmd The high level command + @param CmdLen The command length + @param DataDir The direction of the data transfer + @param Data The buffer to hold data + @param DataLen The length of the data + @param Lun The number of logic unit + @param Timeout The time to wait command + @param CmdStatus The result of high level command execution + + @retval EFI_SUCCESS The command is executed successfully. + @retval Other Failed to execute command + +**/ +EFI_STATUS +UsbBotExecCommand ( + IN VOID *Context, + IN VOID *Cmd, + IN UINT8 CmdLen, + IN EFI_USB_DATA_DIRECTION DataDir, + IN VOID *Data, + IN UINT32 DataLen, + IN UINT8 Lun, + IN UINT32 Timeout, + OUT UINT32 *CmdStatus + ); + +/** + Reset the USB mass storage device by BOT protocol. + + @param Context The context of the BOT protocol, that is, + USB_BOT_PROTOCOL. + @param ExtendedVerification If FALSE, just issue Bulk-Only Mass Storage Reset request. + If TRUE, additionally reset parent hub port. + + @retval EFI_SUCCESS The device is reset. + @retval Others Failed to reset the device.. + +**/ +EFI_STATUS +UsbBotResetDevice ( + IN VOID *Context, + IN BOOLEAN ExtendedVerification + ); + +/** + Get the max LUN (Logical Unit Number) of USB mass storage device. + + @param Context The context of the BOT protocol, that is, USB_BOT_PROTOCOL + @param MaxLun Return pointer to the max number of LUN. (e.g. MaxLun=1 means LUN0 and + LUN1 in all.) + + @retval EFI_SUCCESS Max LUN is got successfully. + @retval Others Fail to execute this request. + +**/ +EFI_STATUS +UsbBotGetMaxLun ( + IN VOID *Context, + OUT UINT8 *MaxLun + ); + +/** + Clean up the resource used by this BOT protocol. + + @param Context The context of the BOT protocol, that is, USB_BOT_PROTOCOL. + + @retval EFI_SUCCESS The resource is cleaned up. + +**/ +EFI_STATUS +UsbBotCleanUp ( + IN VOID *Context + ); + +#endif diff --git a/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassImpl.c b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassImpl.c new file mode 100644 index 0000000000..3686d9fce9 --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassImpl.c @@ -0,0 +1,1136 @@ +/** + Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved. +**/ + +/** @file + USB Mass Storage Driver that manages USB Mass Storage Device and produces Block I/O Protocol. + +Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "UsbMass.h" + +#define USB_MASS_TRANSPORT_COUNT 3 +// +// Array of USB transport interfaces. +// +USB_MASS_TRANSPORT *mUsbMassTransport[USB_MASS_TRANSPORT_COUNT] = { + &mUsbCbi0Transport, + &mUsbCbi1Transport, + &mUsbBotTransport, +}; + +EFI_DRIVER_BINDING_PROTOCOL gUSBMassDriverBinding = { + USBMassDriverBindingSupported, + USBMassDriverBindingStart, + USBMassDriverBindingStop, + 0x11, + NULL, + NULL +}; + +/** + Reset the block device. + + This function implements EFI_BLOCK_IO_PROTOCOL.Reset(). + It resets the block device hardware. + ExtendedVerification is ignored in this implementation. + + @param This Indicates a pointer to the calling context. + @param ExtendedVerification Indicates that the driver may perform a more exhaustive + verification operation of the device during reset. + + @retval EFI_SUCCESS The block device was reset. + @retval EFI_DEVICE_ERROR The block device is not functioning correctly and could not be reset. + +**/ +EFI_STATUS +EFIAPI +UsbMassReset ( + IN EFI_BLOCK_IO_PROTOCOL *This, + IN BOOLEAN ExtendedVerification + ) +{ + USB_MASS_DEVICE *UsbMass; + EFI_TPL OldTpl; + EFI_STATUS Status; + + // + // Raise TPL to TPL_CALLBACK to serialize all its operations + // to protect shared data structures. + // + OldTpl = gBS->RaiseTPL (TPL_CALLBACK); + + UsbMass = USB_MASS_DEVICE_FROM_BLOCK_IO (This); + Status = UsbMass->Transport->Reset (UsbMass->Context, ExtendedVerification); + + gBS->RestoreTPL (OldTpl); + + return Status; +} + +/** + Reads the requested number of blocks from the device. + + This function implements EFI_BLOCK_IO_PROTOCOL.ReadBlocks(). + It reads the requested number of blocks from the device. + All the blocks are read, or an error is returned. + + @param This Indicates a pointer to the calling context. + @param MediaId The media ID that the read request is for. + @param Lba The starting logical block address to read from on the device. + @param BufferSize The size of the Buffer in bytes. + This must be a multiple of the intrinsic block size of the device. + @param Buffer A pointer to the destination buffer for the data. The caller is + responsible for either having implicit or explicit ownership of the buffer. + + @retval EFI_SUCCESS The data was read correctly from the device. + @retval EFI_DEVICE_ERROR The device reported an error while attempting to perform the read operation. + @retval EFI_NO_MEDIA There is no media in the device. + @retval EFI_MEDIA_CHANGED The MediaId is not for the current media. + @retval EFI_BAD_BUFFER_SIZE The BufferSize parameter is not a multiple of the intrinsic block size of the device. + @retval EFI_INVALID_PARAMETER The read request contains LBAs that are not valid, + or the buffer is not on proper alignment. + +**/ +EFI_STATUS +EFIAPI +UsbMassReadBlocks ( + IN EFI_BLOCK_IO_PROTOCOL *This, + IN UINT32 MediaId, + IN EFI_LBA Lba, + IN UINTN BufferSize, + OUT VOID *Buffer + ) +{ + USB_MASS_DEVICE *UsbMass; + EFI_BLOCK_IO_MEDIA *Media; + EFI_STATUS Status; + EFI_TPL OldTpl; + UINTN TotalBlock; + + // AMD_EDKII_OVERRIDE START + INT8 ResetRetryCount; + VOID *OriginalBuffer; + EFI_LBA OriginalLba; + UINTN OriginalBufferSize; + + // + // Raise TPL to TPL_CALLBACK to serialize all its operations + // to protect shared data structures. + // + OldTpl = gBS->RaiseTPL (TPL_CALLBACK); + UsbMass = USB_MASS_DEVICE_FROM_BLOCK_IO (This); + Media = &UsbMass->BlockIoMedia; + + ResetRetryCount = 3; + OriginalBuffer = Buffer; + OriginalBufferSize = BufferSize; + OriginalLba = Lba; + + while (ResetRetryCount >= 0) { + + Buffer = OriginalBuffer; + Lba = OriginalLba; + BufferSize = OriginalBufferSize; + + // + // If it is a removable media, such as CD-Rom or Usb-Floppy, + // need to detect the media before each read/write. While some of + // Usb-Flash is marked as removable media. + // + if (Media->RemovableMedia) { + Status = UsbBootDetectMedia (UsbMass); + if (EFI_ERROR (Status)) { + goto ON_EXIT; + } + } + + if (!(Media->MediaPresent)) { + Status = EFI_NO_MEDIA; + goto ON_EXIT; + } + + if (MediaId != Media->MediaId) { + Status = EFI_MEDIA_CHANGED; + goto ON_EXIT; + } + + if (BufferSize == 0) { + Status = EFI_SUCCESS; + goto ON_EXIT; + } + + if (Buffer == NULL) { + Status = EFI_INVALID_PARAMETER; + goto ON_EXIT; + } + + // + // BufferSize must be a multiple of the intrinsic block size of the device. + // + if ((BufferSize % Media->BlockSize) != 0) { + Status = EFI_BAD_BUFFER_SIZE; + goto ON_EXIT; + } + + TotalBlock = BufferSize / Media->BlockSize; + + // + // Make sure the range to read is valid. + // + if (Lba + TotalBlock - 1 > Media->LastBlock) { + Status = EFI_INVALID_PARAMETER; + goto ON_EXIT; + } + + if (UsbMass->Cdb16Byte) { + Status = UsbBootReadWriteBlocks16 (UsbMass, FALSE, Lba, TotalBlock, Buffer); + } else { + Status = UsbBootReadWriteBlocks (UsbMass, FALSE, (UINT32)Lba, TotalBlock, Buffer); + } + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "UsbMassReadBlocks: UsbBootReadBlocks (%r) -> Reset\n", Status)); + UsbMassReset (This, TRUE); + ResetRetryCount--; + } + else { + break; + } + } + // AMD_EDKII_OVERRIDE END +ON_EXIT: + gBS->RestoreTPL (OldTpl); + return Status; +} + +/** + Writes a specified number of blocks to the device. + + This function implements EFI_BLOCK_IO_PROTOCOL.WriteBlocks(). + It writes a specified number of blocks to the device. + All blocks are written, or an error is returned. + + @param This Indicates a pointer to the calling context. + @param MediaId The media ID that the write request is for. + @param Lba The starting logical block address to be written. + @param BufferSize The size of the Buffer in bytes. + This must be a multiple of the intrinsic block size of the device. + @param Buffer Pointer to the source buffer for the data. + + @retval EFI_SUCCESS The data were written correctly to the device. + @retval EFI_WRITE_PROTECTED The device cannot be written to. + @retval EFI_NO_MEDIA There is no media in the device. + @retval EFI_MEDIA_CHANGED The MediaId is not for the current media. + @retval EFI_DEVICE_ERROR The device reported an error while attempting to perform the write operation. + @retval EFI_BAD_BUFFER_SIZE The BufferSize parameter is not a multiple of the intrinsic + block size of the device. + @retval EFI_INVALID_PARAMETER The write request contains LBAs that are not valid, + or the buffer is not on proper alignment. + +**/ +EFI_STATUS +EFIAPI +UsbMassWriteBlocks ( + IN EFI_BLOCK_IO_PROTOCOL *This, + IN UINT32 MediaId, + IN EFI_LBA Lba, + IN UINTN BufferSize, + IN VOID *Buffer + ) +{ + USB_MASS_DEVICE *UsbMass; + EFI_BLOCK_IO_MEDIA *Media; + EFI_STATUS Status; + EFI_TPL OldTpl; + UINTN TotalBlock; + + // + // Raise TPL to TPL_CALLBACK to serialize all its operations + // to protect shared data structures. + // + OldTpl = gBS->RaiseTPL (TPL_CALLBACK); + UsbMass = USB_MASS_DEVICE_FROM_BLOCK_IO (This); + Media = &UsbMass->BlockIoMedia; + + // + // If it is a removable media, such as CD-Rom or Usb-Floppy, + // need to detect the media before each read/write. Some of + // USB Flash is marked as removable media. + // + if (Media->RemovableMedia) { + Status = UsbBootDetectMedia (UsbMass); + if (EFI_ERROR (Status)) { + goto ON_EXIT; + } + } + + if (!(Media->MediaPresent)) { + Status = EFI_NO_MEDIA; + goto ON_EXIT; + } + + if (MediaId != Media->MediaId) { + Status = EFI_MEDIA_CHANGED; + goto ON_EXIT; + } + + if (BufferSize == 0) { + Status = EFI_SUCCESS; + goto ON_EXIT; + } + + if (Buffer == NULL) { + Status = EFI_INVALID_PARAMETER; + goto ON_EXIT; + } + + // + // BufferSize must be a multiple of the intrinsic block size of the device. + // + if ((BufferSize % Media->BlockSize) != 0) { + Status = EFI_BAD_BUFFER_SIZE; + goto ON_EXIT; + } + + TotalBlock = BufferSize / Media->BlockSize; + + // + // Make sure the range to write is valid. + // + if (Lba + TotalBlock - 1 > Media->LastBlock) { + Status = EFI_INVALID_PARAMETER; + goto ON_EXIT; + } + + // + // Try to write the data even the device is marked as ReadOnly, + // and clear the status should the write succeed. + // + if (UsbMass->Cdb16Byte) { + Status = UsbBootReadWriteBlocks16 (UsbMass, TRUE, Lba, TotalBlock, Buffer); + } else { + Status = UsbBootReadWriteBlocks (UsbMass, TRUE, (UINT32)Lba, TotalBlock, Buffer); + } + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "UsbMassWriteBlocks: UsbBootWriteBlocks (%r) -> Reset\n", Status)); + UsbMassReset (This, TRUE); + } + +ON_EXIT: + gBS->RestoreTPL (OldTpl); + return Status; +} + +/** + Flushes all modified data to a physical block device. + + This function implements EFI_BLOCK_IO_PROTOCOL.FlushBlocks(). + USB mass storage device doesn't support write cache, + so return EFI_SUCCESS directly. + + @param This Indicates a pointer to the calling context. + + @retval EFI_SUCCESS All outstanding data were written correctly to the device. + @retval EFI_DEVICE_ERROR The device reported an error while attempting to write data. + @retval EFI_NO_MEDIA There is no media in the device. + +**/ +EFI_STATUS +EFIAPI +UsbMassFlushBlocks ( + IN EFI_BLOCK_IO_PROTOCOL *This + ) +{ + return EFI_SUCCESS; +} + +/** + Initialize the media parameter data for EFI_BLOCK_IO_MEDIA of Block I/O Protocol. + + @param UsbMass The USB mass storage device + + @retval EFI_SUCCESS The media parameters are updated successfully. + @retval Others Failed to get the media parameters. + +**/ +EFI_STATUS +UsbMassInitMedia ( + IN USB_MASS_DEVICE *UsbMass + ) +{ + EFI_BLOCK_IO_MEDIA *Media; + EFI_STATUS Status; + + Media = &UsbMass->BlockIoMedia; + + // + // Fields of EFI_BLOCK_IO_MEDIA are defined in UEFI 2.0 spec, + // section for Block I/O Protocol. + // + Media->MediaPresent = FALSE; + Media->LogicalPartition = FALSE; + Media->ReadOnly = FALSE; + Media->WriteCaching = FALSE; + Media->IoAlign = 0; + Media->MediaId = 1; + + Status = UsbBootGetParams (UsbMass); + DEBUG ((DEBUG_INFO, "UsbMassInitMedia: UsbBootGetParams (%r)\n", Status)); + if (Status == EFI_MEDIA_CHANGED) { + // + // Some USB storage devices may report MEDIA_CHANGED sense key when hot-plugged. + // Treat it as SUCCESS + // + Status = EFI_SUCCESS; + } + + return Status; +} + +/** + Initialize the USB Mass Storage transport. + + This function tries to find the matching USB Mass Storage transport + protocol for USB device. If found, initializes the matching transport. + + @param This The USB mass driver's driver binding. + @param Controller The device to test. + @param Transport The pointer to pointer to USB_MASS_TRANSPORT. + @param Context The parameter for USB_MASS_DEVICE.Context. + @param MaxLun Get the MaxLun if is BOT dev. + + @retval EFI_SUCCESS The initialization is successful. + @retval EFI_UNSUPPORTED No matching transport protocol is found. + @retval Others Failed to initialize dev. + +**/ +EFI_STATUS +UsbMassInitTransport ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE Controller, + OUT USB_MASS_TRANSPORT **Transport, + OUT VOID **Context, + OUT UINT8 *MaxLun + ) +{ + EFI_USB_IO_PROTOCOL *UsbIo; + EFI_USB_INTERFACE_DESCRIPTOR Interface; + UINT8 Index; + EFI_STATUS Status; + + Status = gBS->OpenProtocol ( + Controller, + &gEfiUsbIoProtocolGuid, + (VOID **)&UsbIo, + This->DriverBindingHandle, + Controller, + EFI_OPEN_PROTOCOL_BY_DRIVER + ); + + if (EFI_ERROR (Status)) { + return Status; + } + + Status = UsbIo->UsbGetInterfaceDescriptor (UsbIo, &Interface); + if (EFI_ERROR (Status)) { + goto ON_EXIT; + } + + Status = EFI_UNSUPPORTED; + + // + // Traverse the USB_MASS_TRANSPORT arrary and try to find the + // matching transport protocol. + // If not found, return EFI_UNSUPPORTED. + // If found, execute USB_MASS_TRANSPORT.Init() to initialize the transport context. + // + for (Index = 0; Index < USB_MASS_TRANSPORT_COUNT; Index++) { + *Transport = mUsbMassTransport[Index]; + + if (Interface.InterfaceProtocol == (*Transport)->Protocol) { + Status = (*Transport)->Init (UsbIo, Context); + break; + } + } + + if (EFI_ERROR (Status)) { + goto ON_EXIT; + } + + // + // For BOT device, try to get its max LUN. + // If max LUN is 0, then it is a non-lun device. + // Otherwise, it is a multi-lun device. + // + if ((*Transport)->Protocol == USB_MASS_STORE_BOT) { + (*Transport)->GetMaxLun (*Context, MaxLun); + } + +ON_EXIT: + gBS->CloseProtocol ( + Controller, + &gEfiUsbIoProtocolGuid, + This->DriverBindingHandle, + Controller + ); + return Status; +} + +/** + Initialize data for device that supports multiple LUNSs. + + @param This The Driver Binding Protocol instance. + @param Controller The device to initialize. + @param Transport Pointer to USB_MASS_TRANSPORT. + @param Context Parameter for USB_MASS_DEVICE.Context. + @param DevicePath The remaining device path. + @param MaxLun The max LUN number. + + @retval EFI_SUCCESS At least one LUN is initialized successfully. + @retval EFI_NOT_FOUND Fail to initialize any of multiple LUNs. + +**/ +EFI_STATUS +UsbMassInitMultiLun ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE Controller, + IN USB_MASS_TRANSPORT *Transport, + IN VOID *Context, + IN EFI_DEVICE_PATH_PROTOCOL *DevicePath, + IN UINT8 MaxLun + ) +{ + USB_MASS_DEVICE *UsbMass; + EFI_USB_IO_PROTOCOL *UsbIo; + DEVICE_LOGICAL_UNIT_DEVICE_PATH LunNode; + UINT8 Index; + EFI_STATUS Status; + EFI_STATUS ReturnStatus; + + ASSERT (MaxLun > 0); + ReturnStatus = EFI_NOT_FOUND; + + for (Index = 0; Index <= MaxLun; Index++) { + DEBUG ((DEBUG_INFO, "UsbMassInitMultiLun: Start to initialize No.%d logic unit\n", Index)); + + UsbIo = NULL; + UsbMass = AllocateZeroPool (sizeof (USB_MASS_DEVICE)); + ASSERT (UsbMass != NULL); + + UsbMass->Signature = USB_MASS_SIGNATURE; + UsbMass->UsbIo = UsbIo; + UsbMass->BlockIo.Media = &UsbMass->BlockIoMedia; + UsbMass->BlockIo.Reset = UsbMassReset; + UsbMass->BlockIo.ReadBlocks = UsbMassReadBlocks; + UsbMass->BlockIo.WriteBlocks = UsbMassWriteBlocks; + UsbMass->BlockIo.FlushBlocks = UsbMassFlushBlocks; + UsbMass->OpticalStorage = FALSE; + UsbMass->Transport = Transport; + UsbMass->Context = Context; + UsbMass->Lun = Index; + + // + // Initialize the media parameter data for EFI_BLOCK_IO_MEDIA of Block I/O Protocol. + // + Status = UsbMassInitMedia (UsbMass); + if ((EFI_ERROR (Status)) && (Status != EFI_NO_MEDIA)) { + DEBUG ((DEBUG_ERROR, "UsbMassInitMultiLun: UsbMassInitMedia (%r)\n", Status)); + FreePool (UsbMass); + continue; + } + + // + // Create a device path node for device logic unit, and append it. + // + LunNode.Header.Type = MESSAGING_DEVICE_PATH; + LunNode.Header.SubType = MSG_DEVICE_LOGICAL_UNIT_DP; + LunNode.Lun = UsbMass->Lun; + + SetDevicePathNodeLength (&LunNode.Header, sizeof (LunNode)); + + UsbMass->DevicePath = AppendDevicePathNode (DevicePath, &LunNode.Header); + + if (UsbMass->DevicePath == NULL) { + DEBUG ((DEBUG_ERROR, "UsbMassInitMultiLun: failed to create device logic unit device path\n")); + Status = EFI_OUT_OF_RESOURCES; + FreePool (UsbMass); + continue; + } + + InitializeDiskInfo (UsbMass); + + // + // Create a new handle for each LUN, and install Block I/O Protocol and Device Path Protocol. + // + Status = gBS->InstallMultipleProtocolInterfaces ( + &UsbMass->Controller, + &gEfiDevicePathProtocolGuid, + UsbMass->DevicePath, + &gEfiBlockIoProtocolGuid, + &UsbMass->BlockIo, + &gEfiDiskInfoProtocolGuid, + &UsbMass->DiskInfo, + NULL + ); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "UsbMassInitMultiLun: InstallMultipleProtocolInterfaces (%r)\n", Status)); + FreePool (UsbMass->DevicePath); + FreePool (UsbMass); + continue; + } + + // + // Open USB I/O Protocol by child to setup a parent-child relationship. + // + Status = gBS->OpenProtocol ( + Controller, + &gEfiUsbIoProtocolGuid, + (VOID **)&UsbIo, + This->DriverBindingHandle, + UsbMass->Controller, + EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER + ); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "UsbMassInitMultiLun: OpenUsbIoProtocol By Child (%r)\n", Status)); + gBS->UninstallMultipleProtocolInterfaces ( + UsbMass->Controller, + &gEfiDevicePathProtocolGuid, + UsbMass->DevicePath, + &gEfiBlockIoProtocolGuid, + &UsbMass->BlockIo, + &gEfiDiskInfoProtocolGuid, + &UsbMass->DiskInfo, + NULL + ); + FreePool (UsbMass->DevicePath); + FreePool (UsbMass); + continue; + } + + ReturnStatus = EFI_SUCCESS; + DEBUG ((DEBUG_INFO, "UsbMassInitMultiLun: Success to initialize No.%d logic unit\n", Index)); + } + + return ReturnStatus; +} + +/** + Initialize data for device that does not support multiple LUNSs. + + @param This The Driver Binding Protocol instance. + @param Controller The device to initialize. + @param Transport Pointer to USB_MASS_TRANSPORT. + @param Context Parameter for USB_MASS_DEVICE.Context. + + @retval EFI_SUCCESS Initialization succeeds. + @retval Other Initialization fails. + +**/ +EFI_STATUS +UsbMassInitNonLun ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE Controller, + IN USB_MASS_TRANSPORT *Transport, + IN VOID *Context + ) +{ + USB_MASS_DEVICE *UsbMass; + EFI_USB_IO_PROTOCOL *UsbIo; + EFI_STATUS Status; + + UsbIo = NULL; + UsbMass = AllocateZeroPool (sizeof (USB_MASS_DEVICE)); + ASSERT (UsbMass != NULL); + + Status = gBS->OpenProtocol ( + Controller, + &gEfiUsbIoProtocolGuid, + (VOID **)&UsbIo, + This->DriverBindingHandle, + Controller, + EFI_OPEN_PROTOCOL_BY_DRIVER + ); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "UsbMassInitNonLun: OpenUsbIoProtocol By Driver (%r)\n", Status)); + goto ON_ERROR; + } + + UsbMass->Signature = USB_MASS_SIGNATURE; + UsbMass->Controller = Controller; + UsbMass->UsbIo = UsbIo; + UsbMass->BlockIo.Media = &UsbMass->BlockIoMedia; + UsbMass->BlockIo.Reset = UsbMassReset; + UsbMass->BlockIo.ReadBlocks = UsbMassReadBlocks; + UsbMass->BlockIo.WriteBlocks = UsbMassWriteBlocks; + UsbMass->BlockIo.FlushBlocks = UsbMassFlushBlocks; + UsbMass->OpticalStorage = FALSE; + UsbMass->Transport = Transport; + UsbMass->Context = Context; + + // + // Initialize the media parameter data for EFI_BLOCK_IO_MEDIA of Block I/O Protocol. + // + Status = UsbMassInitMedia (UsbMass); + if ((EFI_ERROR (Status)) && (Status != EFI_NO_MEDIA)) { + DEBUG ((DEBUG_ERROR, "UsbMassInitNonLun: UsbMassInitMedia (%r)\n", Status)); + goto ON_ERROR; + } + + InitializeDiskInfo (UsbMass); + + Status = gBS->InstallMultipleProtocolInterfaces ( + &Controller, + &gEfiBlockIoProtocolGuid, + &UsbMass->BlockIo, + &gEfiDiskInfoProtocolGuid, + &UsbMass->DiskInfo, + NULL + ); + if (EFI_ERROR (Status)) { + goto ON_ERROR; + } + + return EFI_SUCCESS; + +ON_ERROR: + if (UsbMass != NULL) { + FreePool (UsbMass); + } + + if (UsbIo != NULL) { + gBS->CloseProtocol ( + Controller, + &gEfiUsbIoProtocolGuid, + This->DriverBindingHandle, + Controller + ); + } + + return Status; +} + +/** + Check whether the controller is a supported USB mass storage. + + @param This The USB mass storage driver binding protocol. + @param Controller The controller handle to check. + @param RemainingDevicePath The remaining device path. + + @retval EFI_SUCCESS The driver supports this controller. + @retval other This device isn't supported. + +**/ +EFI_STATUS +EFIAPI +USBMassDriverBindingSupported ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE Controller, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath + ) +{ + EFI_USB_IO_PROTOCOL *UsbIo; + EFI_USB_INTERFACE_DESCRIPTOR Interface; + USB_MASS_TRANSPORT *Transport; + EFI_STATUS Status; + UINTN Index; + + Status = gBS->OpenProtocol ( + Controller, + &gEfiUsbIoProtocolGuid, + (VOID **)&UsbIo, + This->DriverBindingHandle, + Controller, + EFI_OPEN_PROTOCOL_BY_DRIVER + ); + if (EFI_ERROR (Status)) { + return Status; + } + + // + // Get the interface descriptor to check the USB class and find a transport + // protocol handler. + // + Status = UsbIo->UsbGetInterfaceDescriptor (UsbIo, &Interface); + if (EFI_ERROR (Status)) { + goto ON_EXIT; + } + + Status = EFI_UNSUPPORTED; + + if (Interface.InterfaceClass != USB_MASS_STORE_CLASS) { + goto ON_EXIT; + } + + // + // Traverse the USB_MASS_TRANSPORT arrary and try to find the + // matching transport method. + // If not found, return EFI_UNSUPPORTED. + // If found, execute USB_MASS_TRANSPORT.Init() to initialize the transport context. + // + for (Index = 0; Index < USB_MASS_TRANSPORT_COUNT; Index++) { + Transport = mUsbMassTransport[Index]; + if (Interface.InterfaceProtocol == Transport->Protocol) { + Status = Transport->Init (UsbIo, NULL); + break; + } + } + +ON_EXIT: + gBS->CloseProtocol ( + Controller, + &gEfiUsbIoProtocolGuid, + This->DriverBindingHandle, + Controller + ); + + return Status; +} + +/** + Starts the USB mass storage device with this driver. + + This function consumes USB I/O Protocol, initializes USB mass storage device, + installs Block I/O Protocol, and submits Asynchronous Interrupt + Transfer to manage the USB mass storage device. + + @param This The USB mass storage driver binding protocol. + @param Controller The USB mass storage device to start on + @param RemainingDevicePath The remaining device path. + + @retval EFI_SUCCESS This driver supports this device. + @retval EFI_UNSUPPORTED This driver does not support this device. + @retval EFI_DEVICE_ERROR This driver cannot be started due to device Error. + @retval EFI_OUT_OF_RESOURCES Can't allocate memory resources. + @retval EFI_ALREADY_STARTED This driver has been started. + +**/ +EFI_STATUS +EFIAPI +USBMassDriverBindingStart ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE Controller, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath + ) +{ + USB_MASS_TRANSPORT *Transport; + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + VOID *Context; + UINT8 MaxLun; + EFI_STATUS Status; + EFI_USB_IO_PROTOCOL *UsbIo; + EFI_TPL OldTpl; + + OldTpl = gBS->RaiseTPL (TPL_CALLBACK); + + Transport = NULL; + Context = NULL; + MaxLun = 0; + + Status = UsbMassInitTransport (This, Controller, &Transport, &Context, &MaxLun); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "USBMassDriverBindingStart: UsbMassInitTransport (%r)\n", Status)); + goto Exit; + } + + if (MaxLun == 0) { + // + // Initialize data for device that does not support multiple LUNSs. + // + Status = UsbMassInitNonLun (This, Controller, Transport, Context); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "USBMassDriverBindingStart: UsbMassInitNonLun (%r)\n", Status)); + } + } else { + // + // Open device path to prepare for appending Device Logic Unit node. + // + Status = gBS->OpenProtocol ( + Controller, + &gEfiDevicePathProtocolGuid, + (VOID **)&DevicePath, + This->DriverBindingHandle, + Controller, + EFI_OPEN_PROTOCOL_BY_DRIVER + ); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "USBMassDriverBindingStart: OpenDevicePathProtocol By Driver (%r)\n", Status)); + goto Exit; + } + + Status = gBS->OpenProtocol ( + Controller, + &gEfiUsbIoProtocolGuid, + (VOID **)&UsbIo, + This->DriverBindingHandle, + Controller, + EFI_OPEN_PROTOCOL_BY_DRIVER + ); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "USBMassDriverBindingStart: OpenUsbIoProtocol By Driver (%r)\n", Status)); + gBS->CloseProtocol ( + Controller, + &gEfiDevicePathProtocolGuid, + This->DriverBindingHandle, + Controller + ); + goto Exit; + } + + // + // Initialize data for device that supports multiple LUNs. + // EFI_SUCCESS is returned if at least 1 LUN is initialized successfully. + // + Status = UsbMassInitMultiLun (This, Controller, Transport, Context, DevicePath, MaxLun); + if (EFI_ERROR (Status)) { + gBS->CloseProtocol ( + Controller, + &gEfiDevicePathProtocolGuid, + This->DriverBindingHandle, + Controller + ); + gBS->CloseProtocol ( + Controller, + &gEfiUsbIoProtocolGuid, + This->DriverBindingHandle, + Controller + ); + DEBUG ((DEBUG_ERROR, "USBMassDriverBindingStart: UsbMassInitMultiLun (%r) with Maxlun=%d\n", Status, MaxLun)); + } + } + +Exit: + gBS->RestoreTPL (OldTpl); + return Status; +} + +/** + Stop controlling the device. + + @param This The USB mass storage driver binding + @param Controller The device controller controlled by the driver. + @param NumberOfChildren The number of children of this device + @param ChildHandleBuffer The buffer of children handle. + + @retval EFI_SUCCESS The driver stopped from controlling the device. + @retval EFI_DEVICE_ERROR The device could not be stopped due to a device error. + @retval EFI_UNSUPPORTED Block I/O Protocol is not installed on Controller. + @retval Others Failed to stop the driver + +**/ +EFI_STATUS +EFIAPI +USBMassDriverBindingStop ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE Controller, + IN UINTN NumberOfChildren, + IN EFI_HANDLE *ChildHandleBuffer + ) +{ + EFI_STATUS Status; + USB_MASS_DEVICE *UsbMass; + EFI_USB_IO_PROTOCOL *UsbIo; + EFI_BLOCK_IO_PROTOCOL *BlockIo; + UINTN Index; + BOOLEAN AllChildrenStopped; + + // + // This is a bus driver stop function since multi-lun is supported. + // There are three kinds of device handles that might be passed: + // 1st is a handle with USB I/O & Block I/O installed (non-multi-lun) + // 2nd is a handle with Device Path & USB I/O installed (multi-lun root) + // 3rd is a handle with Device Path & USB I/O & Block I/O installed (multi-lun). + // + if (NumberOfChildren == 0) { + // + // A handle without any children, might be 1st and 2nd type. + // + Status = gBS->OpenProtocol ( + Controller, + &gEfiBlockIoProtocolGuid, + (VOID **)&BlockIo, + This->DriverBindingHandle, + Controller, + EFI_OPEN_PROTOCOL_GET_PROTOCOL + ); + + if (EFI_ERROR (Status)) { + // + // This is a 2nd type handle(multi-lun root), it needs to close devicepath + // and usbio protocol. + // + gBS->CloseProtocol ( + Controller, + &gEfiDevicePathProtocolGuid, + This->DriverBindingHandle, + Controller + ); + gBS->CloseProtocol ( + Controller, + &gEfiUsbIoProtocolGuid, + This->DriverBindingHandle, + Controller + ); + DEBUG ((DEBUG_INFO, "Success to stop multi-lun root handle\n")); + return EFI_SUCCESS; + } + + // + // This is a 1st type handle(non-multi-lun), which only needs to uninstall + // Block I/O Protocol, close USB I/O Protocol and free mass device. + // + UsbMass = USB_MASS_DEVICE_FROM_BLOCK_IO (BlockIo); + + // + // Uninstall Block I/O protocol from the device handle, + // then call the transport protocol to stop itself. + // + Status = gBS->UninstallMultipleProtocolInterfaces ( + Controller, + &gEfiBlockIoProtocolGuid, + &UsbMass->BlockIo, + &gEfiDiskInfoProtocolGuid, + &UsbMass->DiskInfo, + NULL + ); + if (EFI_ERROR (Status)) { + return Status; + } + + gBS->CloseProtocol ( + Controller, + &gEfiUsbIoProtocolGuid, + This->DriverBindingHandle, + Controller + ); + + UsbMass->Transport->CleanUp (UsbMass->Context); + FreePool (UsbMass); + + DEBUG ((DEBUG_INFO, "Success to stop non-multi-lun root handle\n")); + return EFI_SUCCESS; + } + + // + // This is a 3rd type handle(multi-lun), which needs uninstall + // Block I/O Protocol and Device Path Protocol, close USB I/O Protocol and + // free mass device for all children. + // + AllChildrenStopped = TRUE; + + for (Index = 0; Index < NumberOfChildren; Index++) { + Status = gBS->OpenProtocol ( + ChildHandleBuffer[Index], + &gEfiBlockIoProtocolGuid, + (VOID **)&BlockIo, + This->DriverBindingHandle, + Controller, + EFI_OPEN_PROTOCOL_GET_PROTOCOL + ); + if (EFI_ERROR (Status)) { + AllChildrenStopped = FALSE; + DEBUG ((DEBUG_ERROR, "Fail to stop No.%d multi-lun child handle when opening blockio\n", (UINT32)Index)); + continue; + } + + UsbMass = USB_MASS_DEVICE_FROM_BLOCK_IO (BlockIo); + + gBS->CloseProtocol ( + Controller, + &gEfiUsbIoProtocolGuid, + This->DriverBindingHandle, + ChildHandleBuffer[Index] + ); + + Status = gBS->UninstallMultipleProtocolInterfaces ( + ChildHandleBuffer[Index], + &gEfiDevicePathProtocolGuid, + UsbMass->DevicePath, + &gEfiBlockIoProtocolGuid, + &UsbMass->BlockIo, + &gEfiDiskInfoProtocolGuid, + &UsbMass->DiskInfo, + NULL + ); + + if (EFI_ERROR (Status)) { + // + // Fail to uninstall Block I/O Protocol and Device Path Protocol, so re-open USB I/O Protocol by child. + // + AllChildrenStopped = FALSE; + DEBUG ((DEBUG_ERROR, "Fail to stop No.%d multi-lun child handle when uninstalling blockio and devicepath\n", (UINT32)Index)); + + gBS->OpenProtocol ( + Controller, + &gEfiUsbIoProtocolGuid, + (VOID **)&UsbIo, + This->DriverBindingHandle, + ChildHandleBuffer[Index], + EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER + ); + } else { + // + // Succeed to stop this multi-lun handle, so go on with next child. + // + if (((Index + 1) == NumberOfChildren) && AllChildrenStopped) { + UsbMass->Transport->CleanUp (UsbMass->Context); + } + + FreePool (UsbMass); + } + } + + if (!AllChildrenStopped) { + return EFI_DEVICE_ERROR; + } + + DEBUG ((DEBUG_INFO, "Success to stop all %d multi-lun children handles\n", (UINT32)NumberOfChildren)); + return EFI_SUCCESS; +} + +/** + Entrypoint of USB Mass Storage Driver. + + This function is the entrypoint of USB Mass Storage Driver. It installs Driver Binding + Protocol together with Component Name Protocols. + + @param ImageHandle The firmware allocated handle for the EFI image. + @param SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The entry point is executed successfully. + +**/ +EFI_STATUS +EFIAPI +USBMassStorageEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + // + // Install driver binding protocol + // + Status = EfiLibInstallDriverBindingComponentName2 ( + ImageHandle, + SystemTable, + &gUSBMassDriverBinding, + ImageHandle, + &gUsbMassStorageComponentName, + &gUsbMassStorageComponentName2 + ); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} diff --git a/Platform/AMD/TurinBoard/Override/edk2/MdePkg/Library/SmmPciExpressLib/SmmPciExpressLib.inf b/Platform/AMD/TurinBoard/Override/edk2/MdePkg/Library/SmmPciExpressLib/SmmPciExpressLib.inf new file mode 100644 index 0000000000..09875c9b00 --- /dev/null +++ b/Platform/AMD/TurinBoard/Override/edk2/MdePkg/Library/SmmPciExpressLib/SmmPciExpressLib.inf @@ -0,0 +1,43 @@ +# +# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved. +# + +## @file +# Instance of PCI Express Library using the 256 MB PCI Express MMIO window. +# +# PCI Express Library that uses the 256 MB PCI Express MMIO window to perform +# PCI Configuration cycles. Layers on top of an I/O Library instance. +# +# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved. +# Portions copyright (c) 2016, American Megatrends, Inc. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = SmmPciExpressLib + FILE_GUID = 00D24382-8231-4B18-A4F0-2D94D8FE2E81 + MODULE_TYPE = DXE_SMM_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = PciExpressLib|DXE_SMM_DRIVER SMM_CORE + CONSTRUCTOR = SmmPciExpressLibConstructor + +[Sources] + PciExpressLib.c + +[Packages] + MdePkg/MdePkg.dec + +[LibraryClasses] + UefiBootServicesTableLib + BaseLib + PcdLib + DebugLib + IoLib + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize ## CONSUMES diff --git a/Platform/AMD/TurinBoard/PuricoBoardPkg/Include/Dsc/Smbios.dsc b/Platform/AMD/TurinBoard/PuricoBoardPkg/Include/Dsc/Smbios.dsc new file mode 100644 index 0000000000..1c784e134d --- /dev/null +++ b/Platform/AMD/TurinBoard/PuricoBoardPkg/Include/Dsc/Smbios.dsc @@ -0,0 +1,177 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All rights reserved. +#; +#;****************************************************************************** +# +## @file +# Smbios Platform description. +# +## + +[PcdsFixedAtBuild] + #**************************************************************************** + # COMMON SMBIOS + #**************************************************************************** + # + # IPMI Interface Type + # + # 0 - Unknown + # 1 - KCS + # 2 - SMIC + # 3 - BT + # 4 - SSIF + gAmdPlatformPkgTokenSpaceGuid.PcdIpmiInterfaceType|1 + + # SMBIOS Type 4 Processor Information + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSerialNumberSocket0|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosAssetTagSocket0|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosPartNumberSocket0|"To be filled by O.E.M." + +# AMD SMBIOS Type 8 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8Number|7 + + # AMD SMBIOS Type 9 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics1.Provides33Volts|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics2.BifurcationSupported|1 + + # Port #0 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.IntDesiganatorStr|"USB1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.ExtDesiganatorStr|"USB-Rear 1" + + # Port #1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.IntDesiganatorStr|"USB1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.ExtDesiganatorStr|"USB-Rear 2" + + # Port #2 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].DesinatorStr.IntDesiganatorStr|"F_USB1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].DesinatorStr.ExtDesiganatorStr|"USB-Front 1" + + # Port #3 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].DesinatorStr.IntDesiganatorStr|"F_USB1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].DesinatorStr.ExtDesiganatorStr|"USB-Front 2" + + # Port #4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalConnectorType|PortConnectorTypeRJ45 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.PortType|PortTypeNetworkPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.IntDesiganatorStr|"LAN0" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.ExtDesiganatorStr|"LAN0" + + # Port #5 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalConnectorType|PortConnectorTypeRJ45 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.PortType|PortTypeNetworkPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.IntDesiganatorStr|"LAN1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.ExtDesiganatorStr|"LAN1" + + # Port #6 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.ExternalConnectorType|PortConnectorTypeDB15Female + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.PortType|PortTypeVideoPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].DesinatorStr.IntDesiganatorStr|"J129" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].DesinatorStr.ExtDesiganatorStr|"VGA" + + # AMD SMBIOS Type 41 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41Number|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].ReferenceDesignation|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceType|OnBoardDeviceExtendedTypeEthernet + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceEnabled|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceTypeInstance|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].VendorId|0x14E4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceId|0x165F + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].RefDesignationStr|"Onboard Ethernet" + +[PcdsDynamicDefault] + #**************************************************************************** + # BASIC SMBIOS + #**************************************************************************** + # + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0305 + # SMBIOS Type 0 BIOS Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosReleaseDate|"$(RELEASE_DATE)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosVersion|"$(FIRMWARE_VERSION_STR)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Size|32 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Unit|0x00 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PlugAndPlayIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.EDDSpecificationIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy525_12IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_720IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_288IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrintScreenIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Keyboard8042IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.SerialIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrinterIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.CgaMonoIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[0]|0x01 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[1]|0x0C + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringVendor|"AMD Corporation" + + # SMBIOS Type 1 System Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringFamily|$(AMD_PROCESSOR) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1SystemInformation.Uuid|{GUID("4462C5BB-B061-4771-85D3-674849AB82E0")} + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringSerialNumber|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringVersion|"To be filled by O.E.M." + + # SMBIOS Type 2 Baseboard Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringVersion|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringAssetTag|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringLocationInChassis|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringSerialNumber|"To be filled by O.E.M." + + # SMBIOS Type 3 System Enclosure Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringVersion|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringAssetTag|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSKUNumber|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSerialNumber|"To be filled by O.E.M." + + # SMBIOS Type 11 OEM Strings + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStringsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStrings|{"To be filled by O.E.M."} + + # SMBIOS Type 12 System Configuration Options + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptionsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptions|{"To be filled by O.E.M."} + +[Components.X64] + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + SystemInformation/SmbiosFeaturePkg/SmbiosBasicDxe/SmbiosBasicDxe.inf + AmdPlatformPkg/Universal/SmbiosCommonDxe/SmbiosCommonDxe.inf { + + PciSegmentLib|MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.inf + PciSegmentInfoLib|AgesaPkg/Addendum/PciSegments/PciExpressPciSegmentInfoLib/PciExpressPciSegmentInfoLib.inf + } diff --git a/Platform/AMD/TurinBoard/PuricoBoardPkg/Project.dsc b/Platform/AMD/TurinBoard/PuricoBoardPkg/Project.dsc new file mode 100644 index 0000000000..74ad0d25e4 --- /dev/null +++ b/Platform/AMD/TurinBoard/PuricoBoardPkg/Project.dsc @@ -0,0 +1,193 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All rights reserved. +#; +#;****************************************************************************** + +# ***************************************************************************** +# Defines passed into build +# RELEASE_DATE +# FIRMWARE_REVISION_NUM +# FIRMWARE_VERSION_STR +# PLATFORM_CRB +# AMD_PROCESSOR +# CBS_INCLUDE +# INTERNAL_IDS +# SIMNOW_SUPPORT +# EMULATION +# ***************************************************************************** + +[Defines] +!ifndef AMD_PROCESSOR + AMD_PROCESSOR = Turin +!endif + PROCESSOR_PATH = $(AMD_PROCESSOR)Board +!ifndef PLATFORM_CRB + PLATFORM_CRB = Purico +!endif + PLATFORM_NAME = $(PLATFORM_CRB)BoardPkg + PLATFORM_GUID = C3851035-490E-485E-8941-DFFDBDB45F69 + PLATFORM_VERSION = 0.01 + DSC_SPECIFICATION = 1.30 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)_$(AMD_PROCESSOR) +!ifdef $(INTERNAL_IDS) + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_INTERNAL +!else + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_EXTERNAL +!endif + SUPPORTED_ARCHITECTURES = IA32|X64 + BUILD_TARGETS = DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = $(PLATFORM_NAME)/Project.fdf + + DEFINE PEI_ARCH = IA32 + DEFINE DXE_ARCH = X64 + PREBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py prebuild" + POSTBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py postbuild" + + # + # Platform On/Off features are defined here + # + DEFINE SOURCE_DEBUG_ENABLE = FALSE + DEFINE DEBUG_DISPATCH_ENABLE = FALSE + DEFINE DISABLE_SMT = FALSE + + # AGESA Defines to skip Cf9Reset Driver + DEFINE AMD_RESET_DXE_DRIVER_SUPPORT_DISABLED = TRUE + + DEFINE PLATFORM_CRB_TABLE_ID = "PURICO " + + DEFINE SATA_OVERRIDE = FALSE + + !ifdef $(INTERNAL_IDS) + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = FALSE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = TRUE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE + !else + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = FALSE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = FALSE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE + !endif + + # Predefined Fabric Resource + DEFINE PREDEFINED_FABRIC_RESOURCES = TRUE + # use emulated variable store instead of real spirom + # use this flag for early brigup when there is issue + # with accessing the spirom + DEFINE USE_EMULATED_VARIABLE_STORE = $(EMULATION) + + # Multisegment support + DEFINE PCIE_MULTI_SEGMENT = TRUE + + # EDK2 components are starting to use PLATFORMX64_ENABLE in their include + # DSC/FDF files + DEFINE PLATFORMX64_ENABLE = TRUE + + # MACRO used by AGESA FCH include DSC/FDF to exclude legacy CSM support + DEFINE AMD_CSM_SUPPORT_DISABLED = TRUE + + DEFINE ROM3_1TB_REMAP = FALSE + + !ifndef SOC_FAMILY_2 + DEFINE SOC_FAMILY_2 = $(SOC_FAMILY) + !endif + !ifndef SOC_SKU_2 + DEFINE SOC_SKU_2 = $(SOC_SKU) + !endif + !ifndef SOC2_2 + DEFINE SOC2_2 = $(SOC2) + !endif + !ifndef SOC_SKU_TITLE + DEFINE SOC_SKU_TITLE = Brh + !endif + + # Console settings + # + # Background info: + # As per Turin PPR vol7 17.4.10 UART Registers + # There are 3 physical UARTS available for SBIOS. + # UART0 supports flow controls. + # UART1 doest support flow controls. + # UART2 is disabled by AGESA/CPM to enable flow control for UART0. + # Hence only two UARTs (UART0 and UART1) are available for SBIOS. + # MMIO addresses for 4 UART as FEDCF000,FEDCE000,FEDCA000 and FEDC9000 + # + # Platform settings: + # AGESA/CPM enables UART0 and UART1 by setting BIT11 and BIT12 of FchRTDeviceEnableMap. + # If SBIOS wants to use MMIO space then above mentioned reserved MMIO can be used. + # If SBIOS wants UART in legacy mode(to use 0x3F8/0x2F8) then need to set below PCD for + # for respective UART. + # FchUart0LegacyEnable, FchUart1LegacyEnable and FchUart2LegacyEnable + # + # SERIAL_PORT Options: + # NONE + # FCH_MMIO UART0, MMIO + # FCH_IO UART0, 0x3F8 + # BMC_SOL UART1, MMIO + # BMC_SOL_IO UART1, 0x3F8 + # BMC_ESPI eSPI0, 0x3F8 + DEFINE SERIAL_PORT = "BMC_SOL_IO" + DEFINE ESPI_UART = FALSE # Define ESPI_UART to modify APCB tokens + + # + # Simnow Options + # + DEFINE SIMNOW_PORT80_DEBUG = $(EMULATION) + DEFINE USB_SUPPORT = TRUE + DEFINE SATA_SUPPORT = TRUE + DEFINE NVME_SUPPORT = TRUE + + # + # Check undefined variables + # +!ifndef RELEASE_DATE + RELEASE_DATE = 01/01/2023 +!endif +!ifndef FIRMWARE_VERSION_STR + FIRMWARE_VERSION_STR = NONE +!endif +!ifndef FIRMWARE_REVISION_NUM + FIRMWARE_REVISION_NUM = 0x00000000 +!endif + +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +# Add platform includes AGESA, CPM etc +!include $(PROCESSOR_PATH)/Include/Dsc/Platform.inc.dsc + +# Board specific SMBIOS defines +!include $(PLATFORM_NAME)/Include/Dsc/Smbios.dsc + +# Platform Common PCDs +!include $(PROCESSOR_PATH)/Include/Dsc/PlatformCommonPcd.dsc.inc + +# Board specific PCDs +[PcdsFixedAtBuild] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSocketDesignationSocket0|"P0" + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x20204F4349525550 # "PURICO " + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|384 + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1 + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|384 + +[PcdsDynamicDefault] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdEarlyBmcLinkLaneNum|135 + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdXhciOcPolarityCfgLow|TRUE + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdXhciUsb31OcPinSelect|0xFFFF1010 + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdXhciUsb20OcPinSelect|0xFFFFFFFFFFFF1010 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdCfgPlatformPPT|500 + +####################################### +# Library Includes +####################################### +!include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc +!include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc +!include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc +# do not change the order of include +!include $(PROCESSOR_PATH)/Include/Dsc/ProjectCommon.inc.dsc diff --git a/Platform/AMD/TurinBoard/PuricoBoardPkg/Project.fdf b/Platform/AMD/TurinBoard/PuricoBoardPkg/Project.fdf new file mode 100644 index 0000000000..d3c90f27ec --- /dev/null +++ b/Platform/AMD/TurinBoard/PuricoBoardPkg/Project.fdf @@ -0,0 +1,36 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All rights reserved. +#; +#;***************************************************************************** + + +############################################################################## +# +# Turin reference board - 2 SPI FLash devices accessible by x86 (selected by DIP-switch): +# 1) 32MB Flash with 10-pin header next to the VGA connector. +# 2) 64MB Flash with 10-pin header at 90-degrees from VGA connector, and also accessible by the BMC. +# +############################################################################## + +[Defines] + # Platform.inc.fdf can contain custom DEFINES, consumed by FlashmMapInclude.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/Platform.inc.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/FlashMapInclude.fdf + + DEFINE EFS_ESPI_BYTE0 = 0x0E + DEFINE EFS_ESPI_BYTE1 = 0xFF +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +!include $(PROCESSOR_PATH)/Include/Fdf/ProjectCommon.inc.fdf + +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ +!include MinPlatformPkg/Include/Fdf/RuleInclude.fdf diff --git a/Platform/AMD/TurinBoard/QuartzBoardPkg/Include/Dsc/Smbios.dsc b/Platform/AMD/TurinBoard/QuartzBoardPkg/Include/Dsc/Smbios.dsc new file mode 100644 index 0000000000..9ceb38f1c7 --- /dev/null +++ b/Platform/AMD/TurinBoard/QuartzBoardPkg/Include/Dsc/Smbios.dsc @@ -0,0 +1,243 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All rights reserved. +#; +#;****************************************************************************** +# +## @file +# Smbios Platform description. +# +## + +[PcdsFixedAtBuild] + #**************************************************************************** + # COMMON SMBIOS + #**************************************************************************** + # + # IPMI Interface Type + # + # 0 - Unknown + # 1 - KCS + # 2 - SMIC + # 3 - BT + # 4 - SSIF + gAmdPlatformPkgTokenSpaceGuid.PcdIpmiInterfaceType|1 + + # SMBIOS Type 4 Processor Information + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSerialNumberSocket0|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSerialNumberSocket1|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosAssetTagSocket0|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosAssetTagSocket1|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosPartNumberSocket0|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosPartNumberSocket1|"To be filled by O.E.M." + + # AMD SMBIOS Type 8 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8Number|14 + + # AMD SMBIOS Type 9 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics1.Provides33Volts|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics2.BifurcationSupported|1 + + # Port #0 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.IntDesiganatorStr|"J145" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.ExtDesiganatorStr|"USB3" + + # Port #1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.IntDesiganatorStr|"J3" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.ExtDesiganatorStr|"USB3" + + # Port #2 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalConnectorType|PortConnectorTypeRJ45 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.PortType|PortTypeNetworkPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.IntDesiganatorStr|"J15" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.ExtDesiganatorStr|"MGMT RJ45 Port" + + # Port #3 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalConnectorType|PortConnectorTypeDB15Female + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.PortType|PortTypeVideoPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.IntDesiganatorStr|"J129" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.ExtDesiganatorStr|"VGA" + + # Port #4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.InternalConnectorType|PortConnectorTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.ExternalReferenceDesignator|0x0 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.PortType|PortTypeSerial16550ACompatible + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].DesinatorStr.IntDesiganatorStr|"J133 - Serial Port Header" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].DesinatorStr.ExtDesiganatorStr|{0} + + # Port #5 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.InternalConnectorType|PortConnectorTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.ExternalReferenceDesignator|0x0 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.PortType|PortTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].DesinatorStr.IntDesiganatorStr|"J5 - LPC Header" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].DesinatorStr.ExtDesiganatorStr|{0} + + # Port #6 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].DesinatorStr.IntDesiganatorStr|"SATA8 - SATA Port 8" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[8].DesinatorStr.ExtDesiganatorStr|{0} + + # Port #7 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].DesinatorStr.IntDesiganatorStr|"SATA9 - SATA Port 9" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].DesinatorStr.ExtDesiganatorStr|{0} + + # Port #8 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].DesinatorStr.IntDesiganatorStr|"SATA10 - SATA Port 10" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].DesinatorStr.ExtDesiganatorStr|{0} + + # Port #9 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].DesinatorStr.IntDesiganatorStr|"SATA11 - SATA Port 11" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].DesinatorStr.ExtDesiganatorStr|{0} + + # Port #10 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].DesinatorStr.IntDesiganatorStr|"SATA12 - SATA Port 12" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].DesinatorStr.ExtDesiganatorStr|{0} + + # Port #11 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].DesinatorStr.IntDesiganatorStr|"SATA13 - SATA Port 13" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].DesinatorStr.ExtDesiganatorStr|{0} + + # Port #12 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].DesinatorStr.IntDesiganatorStr|"SATA14 - SATA Port 14" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].DesinatorStr.ExtDesiganatorStr|{0} + + # Port #13 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].DesinatorStr.IntDesiganatorStr|"SATA15 - SATA Port 15" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[9].DesinatorStr.ExtDesiganatorStr|{0} + + # AMD SMBIOS Type 41 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41Number|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].ReferenceDesignation|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceType|OnBoardDeviceExtendedTypeEthernet + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceEnabled|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceTypeInstance|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].VendorId|0x14E4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceId|0x165F + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].RefDesignationStr|"Onboard Ethernet" + +[PcdsDynamicDefault] + #**************************************************************************** + # BASIC SMBIOS + #**************************************************************************** + # + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0305 + # SMBIOS Type 0 BIOS Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosReleaseDate|"$(RELEASE_DATE)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosVersion|"$(FIRMWARE_VERSION_STR)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Size|32 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Unit|0x00 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PlugAndPlayIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.EDDSpecificationIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy525_12IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_720IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_288IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrintScreenIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Keyboard8042IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.SerialIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrinterIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.CgaMonoIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[0]|0x01 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[1]|0x0C + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringVendor|"AMD Corporation" + + # SMBIOS Type 1 System Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringFamily|$(AMD_PROCESSOR) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1SystemInformation.Uuid|{GUID("5879B2F2-E823-4C6D-830A-6F52935EA561")} + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringSerialNumber|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringVersion|"To be filled by O.E.M." + + # SMBIOS Type 2 Baseboard Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringVersion|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringAssetTag|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringLocationInChassis|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringSerialNumber|"To be filled by O.E.M." + + # SMBIOS Type 3 System Enclosure Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringVersion|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringAssetTag|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSKUNumber|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSerialNumber|"To be filled by O.E.M." + + # SMBIOS Type 11 OEM Strings + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStringsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStrings|{"To be filled by O.E.M."} + + # SMBIOS Type 12 System Configuration Options + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptionsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptions|{"To be filled by O.E.M."} + +[Components.X64] + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + SystemInformation/SmbiosFeaturePkg/SmbiosBasicDxe/SmbiosBasicDxe.inf + AmdPlatformPkg/Universal/SmbiosCommonDxe/SmbiosCommonDxe.inf { + + PciSegmentLib|MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.inf + PciSegmentInfoLib|AgesaPkg/Addendum/PciSegments/PciExpressPciSegmentInfoLib/PciExpressPciSegmentInfoLib.inf + } diff --git a/Platform/AMD/TurinBoard/QuartzBoardPkg/Project.dsc b/Platform/AMD/TurinBoard/QuartzBoardPkg/Project.dsc new file mode 100644 index 0000000000..a4f0a2be69 --- /dev/null +++ b/Platform/AMD/TurinBoard/QuartzBoardPkg/Project.dsc @@ -0,0 +1,201 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All rights reserved. +#; +#;****************************************************************************** + +# ***************************************************************************** +# Defines passed into build +# RELEASE_DATE +# FIRMWARE_REVISION_NUM +# FIRMWARE_VERSION_STR +# PLATFORM_CRB +# AMD_PROCESSOR +# CBS_INCLUDE +# INTERNAL_IDS +# SIMNOW_SUPPORT +# EMULATION +# ***************************************************************************** + +[Defines] +!ifndef AMD_PROCESSOR + AMD_PROCESSOR = Turin +!endif + PROCESSOR_PATH = $(AMD_PROCESSOR)Board +!ifndef PLATFORM_CRB + PLATFORM_CRB = Quartz +!endif + PLATFORM_NAME = $(PLATFORM_CRB)BoardPkg + PLATFORM_GUID = C3851035-490E-485E-8941-DFFDBDB45F69 + PLATFORM_VERSION = 0.01 + DSC_SPECIFICATION = 1.30 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)_$(AMD_PROCESSOR) +!ifdef $(INTERNAL_IDS) + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_INTERNAL +!else + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_EXTERNAL +!endif + SUPPORTED_ARCHITECTURES = IA32|X64 + BUILD_TARGETS = DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = $(PLATFORM_NAME)/Project.fdf + + DEFINE PEI_ARCH = IA32 + DEFINE DXE_ARCH = X64 + PREBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py prebuild" + POSTBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py postbuild" + + # + # Platform On/Off features are defined here + # + DEFINE SOURCE_DEBUG_ENABLE = FALSE + DEFINE DEBUG_DISPATCH_ENABLE = FALSE + DEFINE DISABLE_SMT = FALSE + + # AGESA Defines to skip Cf9Reset Driver + DEFINE AMD_RESET_DXE_DRIVER_SUPPORT_DISABLED = TRUE + + DEFINE PLATFORM_CRB_TABLE_ID = "QUARTZ " + + DEFINE SATA_OVERRIDE = FALSE + + !ifdef $(INTERNAL_IDS) + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = FALSE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = TRUE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE + !else + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = FALSE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = FALSE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE + !endif + + # Predefined Fabric Resource + DEFINE PREDEFINED_FABRIC_RESOURCES = TRUE + # use emulated variable store instead of real spirom + # use this flag for early brigup when there is issue + # with accessing the spirom + DEFINE USE_EMULATED_VARIABLE_STORE = $(EMULATION) + + # Multisegment support + DEFINE PCIE_MULTI_SEGMENT = TRUE + + # EDK2 components are starting to use PLATFORMX64_ENABLE in their include + # DSC/FDF files + DEFINE PLATFORMX64_ENABLE = TRUE + + # MACRO used by AGESA FCH include DSC/FDF to exclude legacy CSM support + DEFINE AMD_CSM_SUPPORT_DISABLED = TRUE + + DEFINE ROM3_1TB_REMAP = FALSE + + !ifndef SOC_FAMILY_2 + DEFINE SOC_FAMILY_2 = $(SOC_FAMILY) + !endif + !ifndef SOC_SKU_2 + DEFINE SOC_SKU_2 = $(SOC_SKU) + !endif + !ifndef SOC2_2 + DEFINE SOC2_2 = $(SOC2) + !endif + !ifndef SOC_SKU_TITLE + DEFINE SOC_SKU_TITLE = Brh + !endif + + # Console settings + # + # Background info: + # As per Turin PPR vol7 17.4.10 UART Registers + # There are 3 physical UARTS available for SBIOS. + # UART0 supports flow controls. + # UART1 doest support flow controls. + # UART2 is disabled by AGESA/CPM to enable flow control for UART0. + # Hence only two UARTs (UART0 and UART1) are available for SBIOS. + # MMIO addresses for 4 UART as FEDCF000,FEDCE000,FEDCA000 and FEDC9000 + # + # Platform settings: + # AGESA/CPM enables UART0 and UART1 by setting BIT11 and BIT12 of FchRTDeviceEnableMap. + # If SBIOS wants to use MMIO space then above mentioned reserved MMIO can be used. + # If SBIOS wants UART in legacy mode(to use 0x3F8/0x2F8) then need to set below PCD for + # for respective UART. + # FchUart0LegacyEnable, FchUart1LegacyEnable and FchUart2LegacyEnable + # + # SERIAL_PORT Options: + # NONE + # FCH_MMIO UART0, MMIO + # FCH_IO UART0, 0x3F8 + # BMC_SOL UART1, MMIO + # BMC_SOL_IO UART1, 0x3F8 + # BMC_ESPI eSPI0, 0x3F8 + DEFINE SERIAL_PORT = "BMC_SOL_IO" + DEFINE ESPI_UART = FALSE # Define ESPI_UART to modify APCB tokens + + # + # Simnow Options + # + DEFINE SIMNOW_PORT80_DEBUG = $(EMULATION) + DEFINE USB_SUPPORT = TRUE + DEFINE SATA_SUPPORT = TRUE + DEFINE NVME_SUPPORT = TRUE + + # + # Check undefined variables + # +!ifndef RELEASE_DATE + RELEASE_DATE = 01/01/2023 +!endif +!ifndef FIRMWARE_VERSION_STR + FIRMWARE_VERSION_STR = NONE +!endif +!ifndef FIRMWARE_REVISION_NUM + FIRMWARE_REVISION_NUM = 0x00000000 +!endif + +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +# Add platform includes AGESA, CPM etc +!include $(PROCESSOR_PATH)/Include/Dsc/Platform.inc.dsc + +# Board specific SMBIOS defines +!include $(PLATFORM_NAME)/Include/Dsc/Smbios.dsc + +# Platform Common PCDs +!include $(PROCESSOR_PATH)/Include/Dsc/PlatformCommonPcd.dsc.inc + +# Board specific PCDs +[PcdsFixedAtBuild] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSocketDesignationSocket0|"P0" + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSocketDesignationSocket1|"P1" + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x20205A5452415551 # "QUARTZ " + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|768 + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|2 + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|768 + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicCount|16 + +[PcdsDynamicDefault] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdEarlyBmcLinkLaneNum|134 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdCfgPlatformPPT|400 + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0xFFFF + +[PcdsFeatureFlag] + !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 5 + !if $(SIMNOW_SUPPORT) == FALSE || $(EMULATION) == FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|TRUE + !endif + !endif + +####################################### +# Library Includes +####################################### +!include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc +!include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc +!include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc +# do not change the order of include +!include $(PROCESSOR_PATH)/Include/Dsc/ProjectCommon.inc.dsc + diff --git a/Platform/AMD/TurinBoard/QuartzBoardPkg/Project.fdf b/Platform/AMD/TurinBoard/QuartzBoardPkg/Project.fdf new file mode 100644 index 0000000000..d3c90f27ec --- /dev/null +++ b/Platform/AMD/TurinBoard/QuartzBoardPkg/Project.fdf @@ -0,0 +1,36 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All rights reserved. +#; +#;***************************************************************************** + + +############################################################################## +# +# Turin reference board - 2 SPI FLash devices accessible by x86 (selected by DIP-switch): +# 1) 32MB Flash with 10-pin header next to the VGA connector. +# 2) 64MB Flash with 10-pin header at 90-degrees from VGA connector, and also accessible by the BMC. +# +############################################################################## + +[Defines] + # Platform.inc.fdf can contain custom DEFINES, consumed by FlashmMapInclude.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/Platform.inc.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/FlashMapInclude.fdf + + DEFINE EFS_ESPI_BYTE0 = 0x0E + DEFINE EFS_ESPI_BYTE1 = 0xFF +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +!include $(PROCESSOR_PATH)/Include/Fdf/ProjectCommon.inc.fdf + +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ +!include MinPlatformPkg/Include/Fdf/RuleInclude.fdf diff --git a/Platform/AMD/TurinBoard/RubyBoardPkg/Include/Dsc/Smbios.dsc b/Platform/AMD/TurinBoard/RubyBoardPkg/Include/Dsc/Smbios.dsc new file mode 100644 index 0000000000..90cfe983a2 --- /dev/null +++ b/Platform/AMD/TurinBoard/RubyBoardPkg/Include/Dsc/Smbios.dsc @@ -0,0 +1,177 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All rights reserved. +#; +#;****************************************************************************** +# +## @file +# Smbios Platform description. +# +## + +[PcdsFixedAtBuild] + #**************************************************************************** + # COMMON SMBIOS + #**************************************************************************** + # + # IPMI Interface Type + # + # 0 - Unknown + # 1 - KCS + # 2 - SMIC + # 3 - BT + # 4 - SSIF + gAmdPlatformPkgTokenSpaceGuid.PcdIpmiInterfaceType|1 + + # SMBIOS Type 4 Processor Information + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSerialNumberSocket0|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosAssetTagSocket0|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosPartNumberSocket0|"To be filled by O.E.M." + + # AMD SMBIOS Type 8 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8Number|7 + + # AMD SMBIOS Type 9 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics1.Provides33Volts|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics2.BifurcationSupported|1 + + # Port #0 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.IntDesiganatorStr|"USB1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.ExtDesiganatorStr|"USB-Rear 1" + + # Port #1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.IntDesiganatorStr|"USB1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.ExtDesiganatorStr|"USB-Rear 2" + + # Port #2 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].DesinatorStr.IntDesiganatorStr|"F_USB1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[2].DesinatorStr.ExtDesiganatorStr|"USB-Front 1" + + # Port #3 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].DesinatorStr.IntDesiganatorStr|"F_USB1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[3].DesinatorStr.ExtDesiganatorStr|"USB-Front 2" + + # Port #4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalConnectorType|PortConnectorTypeRJ45 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.PortType|PortTypeNetworkPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.IntDesiganatorStr|"LAN0" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.ExtDesiganatorStr|"LAN0" + + # Port #5 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalConnectorType|PortConnectorTypeRJ45 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.PortType|PortTypeNetworkPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.IntDesiganatorStr|"LAN1" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.ExtDesiganatorStr|"LAN1" + + # Port #6 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.ExternalConnectorType|PortConnectorTypeDB15Female + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].Type8Data.PortType|PortTypeVideoPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].DesinatorStr.IntDesiganatorStr|"J129" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[6].DesinatorStr.ExtDesiganatorStr|"VGA" + + # AMD SMBIOS Type 41 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41Number|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].ReferenceDesignation|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceType|OnBoardDeviceExtendedTypeEthernet + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceEnabled|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceTypeInstance|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].VendorId|0x14E4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceId|0x165F + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].RefDesignationStr|"Onboard Ethernet" + +[PcdsDynamicDefault] + #**************************************************************************** + # BASIC SMBIOS + #**************************************************************************** + # + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0305 + # SMBIOS Type 0 BIOS Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosReleaseDate|"$(RELEASE_DATE)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosVersion|"$(FIRMWARE_VERSION_STR)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Size|32 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Unit|0x00 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PlugAndPlayIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.EDDSpecificationIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy525_12IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_720IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_288IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrintScreenIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Keyboard8042IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.SerialIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrinterIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.CgaMonoIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[0]|0x01 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[1]|0x0C + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringVendor|"AMD Corporation" + + # SMBIOS Type 1 System Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringFamily|$(AMD_PROCESSOR) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1SystemInformation.Uuid|{GUID("4462C5BB-B061-4771-85D3-674849AB82E0")} + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringSerialNumber|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringVersion|"To be filled by O.E.M." + + # SMBIOS Type 2 Baseboard Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringVersion|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringAssetTag|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringLocationInChassis|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringSerialNumber|"To be filled by O.E.M." + + # SMBIOS Type 3 System Enclosure Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringVersion|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringAssetTag|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSKUNumber|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSerialNumber|"To be filled by O.E.M." + + # SMBIOS Type 11 OEM Strings + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStringsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStrings|{"To be filled by O.E.M."} + + # SMBIOS Type 12 System Configuration Options + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptionsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptions|{"To be filled by O.E.M."} + +[Components.X64] + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + SystemInformation/SmbiosFeaturePkg/SmbiosBasicDxe/SmbiosBasicDxe.inf + AmdPlatformPkg/Universal/SmbiosCommonDxe/SmbiosCommonDxe.inf { + + PciSegmentLib|MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.inf + PciSegmentInfoLib|AgesaPkg/Addendum/PciSegments/PciExpressPciSegmentInfoLib/PciExpressPciSegmentInfoLib.inf + } diff --git a/Platform/AMD/TurinBoard/RubyBoardPkg/Project.dsc b/Platform/AMD/TurinBoard/RubyBoardPkg/Project.dsc new file mode 100644 index 0000000000..2ad13a6933 --- /dev/null +++ b/Platform/AMD/TurinBoard/RubyBoardPkg/Project.dsc @@ -0,0 +1,193 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All rights reserved. +#; +#;****************************************************************************** + +# ***************************************************************************** +# Defines passed into build +# RELEASE_DATE +# FIRMWARE_REVISION_NUM +# FIRMWARE_VERSION_STR +# PLATFORM_CRB +# AMD_PROCESSOR +# CBS_INCLUDE +# INTERNAL_IDS +# SIMNOW_SUPPORT +# EMULATION +# ***************************************************************************** + +[Defines] +!ifndef AMD_PROCESSOR + AMD_PROCESSOR = Turin +!endif + PROCESSOR_PATH = $(AMD_PROCESSOR)Board +!ifndef PLATFORM_CRB + PLATFORM_CRB = Ruby +!endif + PLATFORM_NAME = $(PLATFORM_CRB)BoardPkg + PLATFORM_GUID = C3851035-490E-485E-8941-DFFDBDB45F69 + PLATFORM_VERSION = 0.01 + DSC_SPECIFICATION = 1.30 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)_$(AMD_PROCESSOR) +!ifdef $(INTERNAL_IDS) + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_INTERNAL +!else + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_EXTERNAL +!endif + SUPPORTED_ARCHITECTURES = IA32|X64 + BUILD_TARGETS = DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = $(PLATFORM_NAME)/Project.fdf + + DEFINE PEI_ARCH = IA32 + DEFINE DXE_ARCH = X64 + PREBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py prebuild" + POSTBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py postbuild" + + # + # Platform On/Off features are defined here + # + DEFINE SOURCE_DEBUG_ENABLE = FALSE + DEFINE DEBUG_DISPATCH_ENABLE = FALSE + DEFINE DISABLE_SMT = FALSE + + # AGESA Defines to skip Cf9Reset Driver + DEFINE AMD_RESET_DXE_DRIVER_SUPPORT_DISABLED = TRUE + + DEFINE PLATFORM_CRB_TABLE_ID = "RUBY " + + DEFINE SATA_OVERRIDE = FALSE + + !ifdef $(INTERNAL_IDS) + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = FALSE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = TRUE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE + !else + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = FALSE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = FALSE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE + !endif + + # Predefined Fabric Resource + DEFINE PREDEFINED_FABRIC_RESOURCES = TRUE + # use emulated variable store instead of real spirom + # use this flag for early brigup when there is issue + # with accessing the spirom + DEFINE USE_EMULATED_VARIABLE_STORE = $(EMULATION) + + # Multisegment support + DEFINE PCIE_MULTI_SEGMENT = TRUE + + # EDK2 components are starting to use PLATFORMX64_ENABLE in their include + # DSC/FDF files + DEFINE PLATFORMX64_ENABLE = TRUE + + # MACRO used by AGESA FCH include DSC/FDF to exclude legacy CSM support + DEFINE AMD_CSM_SUPPORT_DISABLED = TRUE + + DEFINE ROM3_1TB_REMAP = FALSE + + !ifndef SOC_FAMILY_2 + DEFINE SOC_FAMILY_2 = $(SOC_FAMILY) + !endif + !ifndef SOC_SKU_2 + DEFINE SOC_SKU_2 = $(SOC_SKU) + !endif + !ifndef SOC2_2 + DEFINE SOC2_2 = $(SOC2) + !endif + !ifndef SOC_SKU_TITLE + DEFINE SOC_SKU_TITLE = Brh + !endif + + # Console settings + # + # Background info: + # As per Turin PPR vol7 17.4.10 UART Registers + # There are 3 physical UARTS available for SBIOS. + # UART0 supports flow controls. + # UART1 doest support flow controls. + # UART2 is disabled by AGESA/CPM to enable flow control for UART0. + # Hence only two UARTs (UART0 and UART1) are available for SBIOS. + # MMIO addresses for 4 UART as FEDCF000,FEDCE000,FEDCA000 and FEDC9000 + # + # Platform settings: + # AGESA/CPM enables UART0 and UART1 by setting BIT11 and BIT12 of FchRTDeviceEnableMap. + # If SBIOS wants to use MMIO space then above mentioned reserved MMIO can be used. + # If SBIOS wants UART in legacy mode(to use 0x3F8/0x2F8) then need to set below PCD for + # for respective UART. + # FchUart0LegacyEnable, FchUart1LegacyEnable and FchUart2LegacyEnable + # + # SERIAL_PORT Options: + # NONE + # FCH_MMIO UART0, MMIO + # FCH_IO UART0, 0x3F8 + # BMC_SOL UART1, MMIO + # BMC_SOL_IO UART1, 0x3F8 + # BMC_ESPI eSPI0, 0x3F8 + DEFINE SERIAL_PORT = "BMC_SOL_IO" + DEFINE ESPI_UART = FALSE # Define ESPI_UART to modify APCB tokens + + # + # Simnow Options + # + DEFINE SIMNOW_PORT80_DEBUG = $(EMULATION) + DEFINE USB_SUPPORT = TRUE + DEFINE SATA_SUPPORT = TRUE + DEFINE NVME_SUPPORT = TRUE + + # + # Check undefined variables + # +!ifndef RELEASE_DATE + RELEASE_DATE = 01/01/2023 +!endif +!ifndef FIRMWARE_VERSION_STR + FIRMWARE_VERSION_STR = NONE +!endif +!ifndef FIRMWARE_REVISION_NUM + FIRMWARE_REVISION_NUM = 0x00000000 +!endif + +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +# Add platform includes AGESA, CPM etc +!include $(PROCESSOR_PATH)/Include/Dsc/Platform.inc.dsc + +# Board specific SMBIOS defines +!include $(PLATFORM_NAME)/Include/Dsc/Smbios.dsc + +# Platform Common PCDs +!include $(PROCESSOR_PATH)/Include/Dsc/PlatformCommonPcd.dsc.inc + +# Board specific PCDs +[PcdsFixedAtBuild] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSocketDesignationSocket0|"P0" + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x2020202059425552 # "RUBY " + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|384 + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1 + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|384 + +[PcdsDynamicDefault] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdEarlyBmcLinkLaneNum|134 + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdXhciOcPolarityCfgLow|TRUE + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdXhciUsb31OcPinSelect|0xFFFF1010 + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdXhciUsb20OcPinSelect|0xFFFFFFFFFFFF1010 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdCfgPlatformPPT|400 + +####################################### +# Library Includes +####################################### +!include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc +!include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc +!include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc +# do not change the order of include +!include $(PROCESSOR_PATH)/Include/Dsc/ProjectCommon.inc.dsc diff --git a/Platform/AMD/TurinBoard/RubyBoardPkg/Project.fdf b/Platform/AMD/TurinBoard/RubyBoardPkg/Project.fdf new file mode 100644 index 0000000000..d3c90f27ec --- /dev/null +++ b/Platform/AMD/TurinBoard/RubyBoardPkg/Project.fdf @@ -0,0 +1,36 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All rights reserved. +#; +#;***************************************************************************** + + +############################################################################## +# +# Turin reference board - 2 SPI FLash devices accessible by x86 (selected by DIP-switch): +# 1) 32MB Flash with 10-pin header next to the VGA connector. +# 2) 64MB Flash with 10-pin header at 90-degrees from VGA connector, and also accessible by the BMC. +# +############################################################################## + +[Defines] + # Platform.inc.fdf can contain custom DEFINES, consumed by FlashmMapInclude.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/Platform.inc.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/FlashMapInclude.fdf + + DEFINE EFS_ESPI_BYTE0 = 0x0E + DEFINE EFS_ESPI_BYTE1 = 0xFF +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +!include $(PROCESSOR_PATH)/Include/Fdf/ProjectCommon.inc.fdf + +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ +!include MinPlatformPkg/Include/Fdf/RuleInclude.fdf diff --git a/Platform/AMD/TurinBoard/TitaniteBoardPkg/Include/Dsc/Smbios.dsc b/Platform/AMD/TurinBoard/TitaniteBoardPkg/Include/Dsc/Smbios.dsc new file mode 100644 index 0000000000..7689a6f13a --- /dev/null +++ b/Platform/AMD/TurinBoard/TitaniteBoardPkg/Include/Dsc/Smbios.dsc @@ -0,0 +1,243 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All rights reserved. +#; +#;****************************************************************************** +# +## @file +# Smbios Platform description. +# +## + +[PcdsFixedAtBuild] + #**************************************************************************** + # COMMON SMBIOS + #**************************************************************************** + # + # IPMI Interface Type + # + # 0 - Unknown + # 1 - KCS + # 2 - SMIC + # 3 - BT + # 4 - SSIF + gAmdPlatformPkgTokenSpaceGuid.PcdIpmiInterfaceType|1 + + # SMBIOS Type 4 Processor Information + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSerialNumberSocket0|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSerialNumberSocket1|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosAssetTagSocket0|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosAssetTagSocket1|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosPartNumberSocket0|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosPartNumberSocket1|"To be filled by O.E.M." + + # AMD SMBIOS Type 8 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8Number|14 + + # AMD SMBIOS Type 9 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics1.Provides33Volts|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics2.BifurcationSupported|1 + + # Port #0 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.IntDesiganatorStr|"J145" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.ExtDesiganatorStr|"USB3" + + # Port #1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.IntDesiganatorStr|"J3" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.ExtDesiganatorStr|"USB3" + + # Port #2 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.ExternalConnectorType|PortConnectorTypeRJ45 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.PortType|PortTypeNetworkPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].DesinatorStr.IntDesiganatorStr|"J15" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].DesinatorStr.ExtDesiganatorStr|"MGMT RJ45 Port" + + # Port #3 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalConnectorType|PortConnectorTypeDB15Female + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.PortType|PortTypeVideoPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.IntDesiganatorStr|"J129" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.ExtDesiganatorStr|"VGA" + + # Port #4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalConnectorType|PortConnectorTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.PortType|PortTypeSerial16550ACompatible + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.IntDesiganatorStr|"J133 - Serial Port Header" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.ExtDesiganatorStr|{0} + + # Port #5 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalConnectorType|PortConnectorTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalReferenceDesignator|0x0 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.PortType|PortTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.IntDesiganatorStr|"J5 - LPC Header" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.ExtDesiganatorStr|{0} + + # Port #6 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.IntDesiganatorStr|"SATA8 - SATA Port 8" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.ExtDesiganatorStr|{0} + + # Port #7 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.IntDesiganatorStr|"SATA9 - SATA Port 9" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.ExtDesiganatorStr|{0} + + # Port #8 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.IntDesiganatorStr|"SATA10 - SATA Port 10" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.ExtDesiganatorStr|{0} + + # Port #9 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.IntDesiganatorStr|"SATA11 - SATA Port 11" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.ExtDesiganatorStr|{0} + + # Port #10 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.IntDesiganatorStr|"SATA12 - SATA Port 12" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.ExtDesiganatorStr|{0} + + # Port #11 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.IntDesiganatorStr|"SATA13 - SATA Port 13" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.ExtDesiganatorStr|{0} + + # Port #12 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.IntDesiganatorStr|"SATA14 - SATA Port 14" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.ExtDesiganatorStr|{0} + + # Port #13 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.IntDesiganatorStr|"SATA15 - SATA Port 15" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.ExtDesiganatorStr|{0} + + # AMD SMBIOS Type 41 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41Number|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].ReferenceDesignation|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceType|OnBoardDeviceExtendedTypeEthernet + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceEnabled|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceTypeInstance|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].VendorId|0x14E4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceId|0x165F + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].RefDesignationStr|"Onboard Ethernet" + +[PcdsDynamicDefault] + #**************************************************************************** + # BASIC SMBIOS + #**************************************************************************** + # + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0305 + # SMBIOS Type 0 BIOS Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosReleaseDate|"$(RELEASE_DATE)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosVersion|"$(FIRMWARE_VERSION_STR)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Size|32 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Unit|0x00 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PlugAndPlayIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.EDDSpecificationIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy525_12IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_720IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_288IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrintScreenIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Keyboard8042IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.SerialIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrinterIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.CgaMonoIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[0]|0x01 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[1]|0x0C + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringVendor|"AMD Corporation" + + # SMBIOS Type 1 System Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringFamily|$(AMD_PROCESSOR) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1SystemInformation.Uuid|{GUID("5879B2F2-E823-4C6D-830A-6F52935EA561")} + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringSerialNumber|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringVersion|"To be filled by O.E.M." + + # SMBIOS Type 2 Baseboard Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringVersion|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringAssetTag|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringLocationInChassis|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringSerialNumber|"To be filled by O.E.M." + + # SMBIOS Type 3 System Enclosure Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringVersion|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringAssetTag|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSKUNumber|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSerialNumber|"To be filled by O.E.M." + + # SMBIOS Type 11 OEM Strings + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStringsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStrings|{"To be filled by O.E.M."} + + # SMBIOS Type 12 System Configuration Options + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptionsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptions|{"To be filled by O.E.M."} + +[Components.X64] + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + SystemInformation/SmbiosFeaturePkg/SmbiosBasicDxe/SmbiosBasicDxe.inf + AmdPlatformPkg/Universal/SmbiosCommonDxe/SmbiosCommonDxe.inf { + + PciSegmentLib|MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.inf + PciSegmentInfoLib|AgesaPkg/Addendum/PciSegments/PciExpressPciSegmentInfoLib/PciExpressPciSegmentInfoLib.inf + } diff --git a/Platform/AMD/TurinBoard/TitaniteBoardPkg/Project.dsc b/Platform/AMD/TurinBoard/TitaniteBoardPkg/Project.dsc new file mode 100644 index 0000000000..dd870f0243 --- /dev/null +++ b/Platform/AMD/TurinBoard/TitaniteBoardPkg/Project.dsc @@ -0,0 +1,197 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All rights reserved. +#; +#;****************************************************************************** + +# ***************************************************************************** +# Defines passed into build +# RELEASE_DATE +# FIRMWARE_REVISION_NUM +# FIRMWARE_VERSION_STR +# PLATFORM_CRB +# AMD_PROCESSOR +# CBS_INCLUDE +# INTERNAL_IDS +# SIMNOW_SUPPORT +# EMULATION +# ***************************************************************************** + +[Defines] +!ifndef AMD_PROCESSOR + AMD_PROCESSOR = Turin +!endif + PROCESSOR_PATH = $(AMD_PROCESSOR)Board +!ifndef PLATFORM_CRB + PLATFORM_CRB = Titanite +!endif + PLATFORM_NAME = $(PLATFORM_CRB)BoardPkg + PLATFORM_GUID = C3851035-490E-485E-8941-DFFDBDB45F69 + PLATFORM_VERSION = 0.01 + DSC_SPECIFICATION = 1.30 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)_$(AMD_PROCESSOR) +!ifdef $(INTERNAL_IDS) + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_INTERNAL +!else + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_EXTERNAL +!endif + SUPPORTED_ARCHITECTURES = IA32|X64 + BUILD_TARGETS = DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = $(PLATFORM_NAME)/Project.fdf + + DEFINE PEI_ARCH = IA32 + DEFINE DXE_ARCH = X64 + PREBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py prebuild" + POSTBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py postbuild" + + # + # Platform On/Off features are defined here + # + DEFINE SOURCE_DEBUG_ENABLE = FALSE + DEFINE DEBUG_DISPATCH_ENABLE = FALSE + DEFINE DISABLE_SMT = FALSE + + # AGESA Defines to skip Cf9Reset Driver + DEFINE AMD_RESET_DXE_DRIVER_SUPPORT_DISABLED = TRUE + + DEFINE PLATFORM_CRB_TABLE_ID = "TITANITE" + + DEFINE SATA_OVERRIDE = TRUE + + !ifdef $(INTERNAL_IDS) + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = FALSE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = TRUE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE + !else + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = FALSE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = FALSE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE + !endif + + # Predefined Fabric Resource + DEFINE PREDEFINED_FABRIC_RESOURCES = TRUE + # use emulated variable store instead of real spirom + # use this flag for early brigup when there is issue + # with accessing the spirom + DEFINE USE_EMULATED_VARIABLE_STORE = $(EMULATION) + + # Multisegment support + DEFINE PCIE_MULTI_SEGMENT = TRUE + + # EDK2 components are starting to use PLATFORMX64_ENABLE in their include + # DSC/FDF files + DEFINE PLATFORMX64_ENABLE = TRUE + + # MACRO used by AGESA FCH include DSC/FDF to exclude legacy CSM support + DEFINE AMD_CSM_SUPPORT_DISABLED = TRUE + + DEFINE ROM3_1TB_REMAP = FALSE + + !ifndef SOC_FAMILY_2 + DEFINE SOC_FAMILY_2 = $(SOC_FAMILY) + !endif + !ifndef SOC_SKU_2 + DEFINE SOC_SKU_2 = $(SOC_SKU) + !endif + !ifndef SOC2_2 + DEFINE SOC2_2 = $(SOC2) + !endif + !ifndef SOC_SKU_TITLE + DEFINE SOC_SKU_TITLE = Brh + !endif + + # Console settings + # + # Background info: + # As per Turin PPR vol7 17.4.10 UART Registers + # There are 3 physical UARTS available for SBIOS. + # UART0 supports flow controls. + # UART1 doest support flow controls. + # UART2 is disabled by AGESA/CPM to enable flow control for UART0. + # Hence only two UARTs (UART0 and UART1) are available for SBIOS. + # MMIO addresses for 4 UART as FEDCF000,FEDCE000,FEDCA000 and FEDC9000 + # + # Platform settings: + # AGESA/CPM enables UART0 and UART1 by setting BIT11 and BIT12 of FchRTDeviceEnableMap. + # If SBIOS wants to use MMIO space then above mentioned reserved MMIO can be used. + # If SBIOS wants UART in legacy mode(to use 0x3F8/0x2F8) then need to set below PCD for + # for respective UART. + # FchUart0LegacyEnable, FchUart1LegacyEnable and FchUart2LegacyEnable + # + # SERIAL_PORT Options: + # NONE + # FCH_MMIO UART0, MMIO + # FCH_IO UART0, 0x3F8 + # BMC_SOL UART1, MMIO + # BMC_SOL_IO UART1, 0x3F8 + # BMC_ESPI eSPI0, 0x3F8 + DEFINE SERIAL_PORT = "BMC_SOL_IO" + DEFINE ESPI_UART = FALSE # Define ESPI_UART to modify APCB tokens + + # + # Simnow Options + # + DEFINE SIMNOW_PORT80_DEBUG = $(EMULATION) + DEFINE USB_SUPPORT = TRUE + DEFINE SATA_SUPPORT = TRUE + DEFINE NVME_SUPPORT = TRUE + + # + # Check undefined variables + # +!ifndef RELEASE_DATE + RELEASE_DATE = 01/01/2023 +!endif +!ifndef FIRMWARE_VERSION_STR + FIRMWARE_VERSION_STR = NONE +!endif +!ifndef FIRMWARE_REVISION_NUM + FIRMWARE_REVISION_NUM = 0x00000000 +!endif + +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +# Add platform includes AGESA, CPM etc +!include $(PROCESSOR_PATH)/Include/Dsc/Platform.inc.dsc + +# Board specific SMBIOS defines +!include $(PLATFORM_NAME)/Include/Dsc/Smbios.dsc + +# Platform Common PCDs +!include $(PROCESSOR_PATH)/Include/Dsc/PlatformCommonPcd.dsc.inc + +# Board specific PCDs +[PcdsFixedAtBuild] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSocketDesignationSocket0|"A0" + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSocketDesignationSocket1|"A1" + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x4554494E41544954 # "TITANITE" + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|768 + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|2 + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|768 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdEspiOffset|0x20000 + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdAmdMemMaxDimmPerChannelV2|1 + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicCount|16 + +[PcdsDynamicDefault] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdEarlyBmcLinkLaneNum|135 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdCfgPlatformPPT|400 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdSataEnable2|0x30 + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0xFFFF + + +####################################### +# Library Includes +####################################### +!include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc +!include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc +!include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc +# do not change the order of include +!include $(PROCESSOR_PATH)/Include/Dsc/ProjectCommon.inc.dsc diff --git a/Platform/AMD/TurinBoard/TitaniteBoardPkg/Project.fdf b/Platform/AMD/TurinBoard/TitaniteBoardPkg/Project.fdf new file mode 100644 index 0000000000..8e53006685 --- /dev/null +++ b/Platform/AMD/TurinBoard/TitaniteBoardPkg/Project.fdf @@ -0,0 +1,36 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All rights reserved. +#; +#;***************************************************************************** + + +############################################################################## +# +# Turin reference board - 2 SPI FLash devices accessible by x86 (selected by DIP-switch): +# 1) 32MB Flash with 10-pin header next to the VGA connector. +# 2) 64MB Flash with 10-pin header at 90-degrees from VGA connector, and also accessible by the BMC. +# +############################################################################## + +[Defines] + # Platform.inc.fdf can contain custom DEFINES, consumed by FlashmMapInclude.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/Platform.inc.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/FlashMapInclude.fdf + + DEFINE EFS_ESPI_BYTE0 = 0xFF + DEFINE EFS_ESPI_BYTE1 = 0x0E +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +!include $(PROCESSOR_PATH)/Include/Fdf/ProjectCommon.inc.fdf + +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ +!include MinPlatformPkg/Include/Fdf/RuleInclude.fdf diff --git a/Platform/AMD/TurinBoard/Universal/BoardAcpiDxe/BoardAcpiDxe.c b/Platform/AMD/TurinBoard/Universal/BoardAcpiDxe/BoardAcpiDxe.c new file mode 100644 index 0000000000..1936d2151a --- /dev/null +++ b/Platform/AMD/TurinBoard/Universal/BoardAcpiDxe/BoardAcpiDxe.c @@ -0,0 +1,235 @@ +/** + Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. +**/ + +/** @file + This file implements BoardAcpiDxe driver. + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Locate the first instance of a protocol. If the protocol requested is an + FV protocol, then it will return the first FV that contains the ACPI table + storage file. + + @param[in] Protocol The protocol to find. + @param[in] FfsGuid The FFS that contains the ACPI table. + @param[out] Instance Return pointer to the first instance of the protocol. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_NOT_FOUND The protocol could not be located. + @retval EFI_OUT_OF_RESOURCES There are not enough resources to find the protocol. +**/ +EFI_STATUS +LocateSupportProtocol ( + IN EFI_GUID *Protocol, + IN EFI_GUID *FfsGuid, + OUT VOID **Instance + ) +{ + EFI_STATUS Status; + EFI_HANDLE *HandleBuffer; + UINTN NumberOfHandles; + EFI_FV_FILETYPE FileType; + UINT32 FvStatus; + EFI_FV_FILE_ATTRIBUTES Attributes; + UINTN Size; + UINTN Index; + + // + // Locate protocol. + // + Status = gBS->LocateHandleBuffer ( + ByProtocol, + Protocol, + NULL, + &NumberOfHandles, + &HandleBuffer + ); + if (EFI_ERROR (Status)) { + // + // Defined errors at this time are not found and out of resources. + // + return Status; + } + + // + // Looking for FV with ACPI storage file + // + for (Index = 0; Index < NumberOfHandles; Index++) { + // + // Get the protocol on this handle + // This should not fail because of LocateHandleBuffer + // + Status = gBS->HandleProtocol ( + HandleBuffer[Index], + Protocol, + Instance + ); + ASSERT_EFI_ERROR (Status); + + // + // See if it has the ACPI storage file + // + Size = 0; + FvStatus = 0; + Status = ((EFI_FIRMWARE_VOLUME2_PROTOCOL *)(*Instance))->ReadFile ( + *Instance, + FfsGuid, + NULL, + &Size, + &FileType, + &Attributes, + &FvStatus + ); + + // + // If we found it, then we are done + // + if (Status == EFI_SUCCESS) { + break; + } + } + + // + // Our exit status is determined by the success of the previous operations + // If the protocol was found, Instance already points to it. + // + // + // Free any allocated buffers + // + FreePool (HandleBuffer); + + return Status; +} + +/** + Publish ACPI table from FV. + + @param[in] FfsGuid The FFS that contains the ACPI table. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +PublishAcpiTablesFromFv ( + IN EFI_GUID *FfsGuid + ) +{ + EFI_STATUS Status; + EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol; + EFI_ACPI_COMMON_HEADER *CurrentTable; + UINT32 FvStatus; + UINTN Size; + UINTN TableHandle; + INTN Instance; + EFI_ACPI_TABLE_PROTOCOL *AcpiTable; + EFI_ACPI_TABLE_VERSION Version; + + Instance = 0; + TableHandle = 0; + CurrentTable = NULL; + FwVol = NULL; + + Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID **)&AcpiTable); + ASSERT_EFI_ERROR (Status); + + DEBUG ((DEBUG_INFO, " Looking for Platform ACPI table: %g\n", FfsGuid)); + + // + // Locate the firmware volume protocol + // + Status = LocateSupportProtocol ( + &gEfiFirmwareVolume2ProtocolGuid, + FfsGuid, + (VOID **)&FwVol + ); + ASSERT_EFI_ERROR (Status); + + // + // Read tables from the FV. + // + while (Status == EFI_SUCCESS) { + Status = FwVol->ReadSection ( + FwVol, + FfsGuid, + EFI_SECTION_RAW, + Instance, + (VOID **)&CurrentTable, + &Size, + &FvStatus + ); + if (!EFI_ERROR (Status)) { + BoardUpdateAcpiTable (CurrentTable, &Version); + // + // Add the table + // + TableHandle = 0; + Status = AcpiTable->InstallAcpiTable ( + AcpiTable, + CurrentTable, + CurrentTable->Length, + &TableHandle + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, " Failed to install ACPI table.\n")); + continue; + } + + Status = gBS->FreePool (CurrentTable); + CurrentTable = NULL; + // + // Increment the instance + // + Instance++; + } + } + + // + // Finished + // + return Status; +} + +/** + ACPI Platform driver installation function. + + @param[in] ImageHandle Handle for this drivers loaded image protocol. + @param[in] SystemTable EFI system table. + + @retval EFI_SUCCESS The driver installed without error. + @retval EFI_ABORTED The driver encountered an error and could not complete installation of + the ACPI tables. + +**/ +EFI_STATUS +EFIAPI +InstallAcpiBoard ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "%a: Entry\n", __func__)); + Status = PublishAcpiTablesFromFv (&gEfiCallerIdGuid); + if (EFI_ERROR (Status) && (Status != EFI_NOT_FOUND)) { + DEBUG ((DEBUG_ERROR, " Failed to publish platform ACPI table.\n")); + ASSERT (FALSE); + } + + return EFI_SUCCESS; +} diff --git a/Platform/AMD/TurinBoard/Universal/BoardAcpiDxe/BoardAcpiDxe.inf b/Platform/AMD/TurinBoard/Universal/BoardAcpiDxe/BoardAcpiDxe.inf new file mode 100644 index 0000000000..86b08b0481 --- /dev/null +++ b/Platform/AMD/TurinBoard/Universal/BoardAcpiDxe/BoardAcpiDxe.inf @@ -0,0 +1,54 @@ +## @file +# BoardAcpiDxe friver to install common ACPI tables. +# +# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved +## + +[Defines] + INF_VERSION = 1.29 + BASE_NAME = BoardAcpiDxe + FILE_GUID = D62E99B5-42F1-4A98-8D21-7B4F6F739C16 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = InstallAcpiBoard + +[Sources.common] + BoardAcpiDxe.c + Dsdt/Dsdt.asl + Dsdt/PciSsdt.asl + Dsdt/AmdPci.asi + +[Packages] + AgesaPkg/AgesaPkg.dec + AmdPlatformPkg/AmdPlatformPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + BoardAcpiTableLib + DebugLib + MemoryAllocationLib + PcdLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[Protocols] + gEfiAcpiTableProtocolGuid ## CONSUMES + gEfiFirmwareVolume2ProtocolGuid ## CONSUMES + +[FixedPcd] + gAmdPlatformPkgTokenSpaceGuid.PcdIpmiInterfaceType + gEfiMdePkgTokenSpaceGuid.PcdIpmiKcsIoBaseAddress + gEfiAmdAgesaPkgTokenSpaceGuid.PcdFchUart0Irq + gEfiAmdAgesaPkgTokenSpaceGuid.PcdFchUart1Irq + gEfiAmdAgesaPkgTokenSpaceGuid.PcdFchUart2Irq + gEfiAmdAgesaPkgTokenSpaceGuid.PcdFchUart3Irq + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize + +[Depex] + gEfiAcpiTableProtocolGuid AND + gEfiFirmwareVolume2ProtocolGuid diff --git a/Platform/AMD/TurinBoard/Universal/BoardAcpiDxe/Dsdt/AmdPci.asi b/Platform/AMD/TurinBoard/Universal/BoardAcpiDxe/Dsdt/AmdPci.asi new file mode 100644 index 0000000000..b5c48e2500 --- /dev/null +++ b/Platform/AMD/TurinBoard/Universal/BoardAcpiDxe/Dsdt/AmdPci.asi @@ -0,0 +1,410 @@ +/***************************************************************************** + * + * Copyright (C) 2020-2023 Advanced Micro Devices, Inc. All rights reserved. + * + *****************************************************************************/ +External (PCI0, DeviceObj) +External (\_SB.PCI0.RP71, DeviceObj) +External (PCI3, DeviceObj) +External (\_SB.PCI3.RP71, DeviceObj) +External (POSS, FieldUnitObj) +External (POSC, FieldUnitObj) + +Name (SS1, Zero) +Name (SS2, Zero) +Name (SS3, One) +Name (SS4, Zero) +Name (PRWP, Package (0x02) +{ + Zero, + Zero +}) +Method (GPRW, 2, NotSerialized) +{ + PRWP [Zero] = Arg0 + Local0 = (SS1 << One) + Local0 |= (SS2 << 0x02) + Local0 |= (SS3 << 0x03) + Local0 |= (SS4 << 0x04) + If (((One << Arg1) & Local0)) + { + PRWP [One] = Arg1 + } + Else + { + Local0 >>= One + FindSetRightBit (Local0, PRWP [One]) + } + + Return (PRWP) +} + +Scope (PCI0) { + Device (AL2A) { + Name (_HID, EISAID ("PNP0C02")) + Name (_UID, "AL2AHB") + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadOnly, 0xFEDC0000, 0x00001000) + }) + OperationRegion (LUIE, SystemMemory, 0xFEDC0020, 0x4) + Field(LUIE, AnyAcc, NoLock, Preserve) { + IER0, 1, // IO_Enable_Range_0 + IER1, 1, // IO_Enable_Range_1 + IER2, 1, // IO_Enable_Range_2 + IER3, 1, // IO_Enable_Range_3 + LUR1, 4, // Reserved + WUR0, 2, // Which_UART_RANGE_0 + WUR1, 2, // Which_UART_RANGE_0 + WUR2, 2, // Which_UART_RANGE_0 + WUR3, 2, // Which_UART_RANGE_0 + LUR2, 16, // Reserved + } + // Return _STA Disable value if Legacy Resources Enabled + // Otherwise return _STA Enabled valude (0xF) + // ARG0 = UART number 0-3 + Method (USTA, 1) { + If (LAnd (LEqual(IER0, One), LEqual (WUR0, Arg0))) { + Return (Zero) + } + ElseIf (LAnd (LEqual(IER1, One), LEqual (WUR1, Arg0))) { + Return (Zero) + } + ElseIf (LAnd (LEqual(IER2, One), LEqual (WUR2, Arg0))) { + Return (Zero) + } + ElseIf (LAnd (LEqual(IER3, One), LEqual (WUR3, Arg0))) { + Return (Zero) + } + Else { + Return (0xF) + } + } + + // Return _STA Enable value (0xF) if COMx address is being decoded + // Else return _STA Disable value (0x0) + // ARG0 = COM port number 1-4 + Method (CSTA, 1) { + If (LAnd (LEqual (Arg0, 1), LEqual (IER3, 1))) { + Return (0xF) + } + ElseIf (LAnd (LEqual (Arg0, 2), LEqual (IER1, 1))) { + Return (0xF) + } + ElseIf (LAnd (LEqual (Arg0, 3), LEqual (IER2, 1))) { + Return (0xF) + } + ElseIf (LAnd (LEqual (Arg0, 4), LEqual (IER0, 1))) { + Return (0xF) + } + Else { + Return (Zero) + } + } + } + Device (URT0) { + Name (_HID, "AMDI0020") + Name (_UID, Zero) + Method (_STA) { + Store (^^AL2A.USTA (_UID), Local0) + Return (Local0) + } + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0xFEDC9000, 0x1000) + Memory32Fixed (ReadWrite, 0xFEDC7000, 0x1000) + IRQ (Edge, ActiveLow, Shared) {FixedPcdGet8(PcdFchUart0Irq)} + }) + } + + Device (URT1) { + Name (_HID, "AMDI0020") + Name (_UID, One) + Method (_STA) { + Store (^^AL2A.USTA (_UID), Local0) + Return (Local0) + } + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0xFEDCA000, 0x1000) + Memory32Fixed (ReadWrite, 0xFEDC8000, 0x1000) + IRQ (Edge, ActiveLow, Shared) {FixedPcdGet8(PcdFchUart1Irq)} + }) + } + + // UART 2 always disabled + Device (URT2) { + Name (_HID, "AMDI0020") + Name (_UID, 0x2) + Name (_STA, Zero) + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0xFEDCE000, 0x1000) + Memory32Fixed (ReadWrite, 0xFEDCC000, 0x1000) + IRQ (Edge, ActiveLow, Shared) {FixedPcdGet8(PcdFchUart2Irq)} + }) + } + + // UART 3 always disabled + Device (URT3) { + Name (_HID, "AMDI0020") + Name (_UID, 0x3) + Name (_STA, Zero) + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0xFEDCF000, 0x1000) + Memory32Fixed (ReadWrite, 0xFEDCD000, 0x1000) + IRQ (Edge, ActiveLow, Shared) {FixedPcdGet8(PcdFchUart3Irq)} + }) + } + + Device (LPC0) { + Name (_ADR, 0x140003) + + // UARTx -> COM1: I/O port 0x3F8, IRQ PcdFchUart1Irq + Device (COM1) { + Name (_HID, EISAID ("PNP0501")) + Name (_DDN, "COM1") + Name (_UID, One) + Method (_STA) { + Store (^^^AL2A.CSTA (_UID), Local0) + Return (Local0) + } + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x03F8, 0x03F8, 0x01, 0x08) + IRQ (Edge, ActiveLow, Shared) {FixedPcdGet8(PcdFchUart1Irq)} + UARTSerialBusV2 (115200, // InitialBaudRate + DataBitsEight, // BitsPerByte + StopBitsOne, // StopBits + 0x00, // LinesInUse + , // IsBigEndian + ParityTypeNone, // Parity + FlowControlNone, // FlowControl + 1, // ReceiveBufferSize + 1, // TransimitBufferSize + "COM1", // ResourceSource + , // ResourceSourceIndex + , // ResourceUsage + , // DescrpitorName + , // Shared + // VendorData + ) + }) + } + + // UARTx -> COM2: I/O port 0x2F8, IRQ PcdFchUart0Irq + Device (COM2) { + Name (_HID, EISAID ("PNP0501")) + Name (_DDN, "COM2") + Name (_UID, 2) + Method (_STA) { + Store (^^^AL2A.CSTA (_UID), Local0) + Return (Local0) + } + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x02F8, 0x02F8, 0x01, 0x08) + IRQ (Edge, ActiveLow, Shared) {FixedPcdGet8(PcdFchUart0Irq)} + UARTSerialBusV2 (115200, // InitialBaudRate + DataBitsEight, // BitsPerByte + StopBitsOne, // StopBits + 0x00, // LinesInUse + , // IsBigEndian + ParityTypeNone, // Parity + FlowControlNone, // FlowControl + 1, // ReceiveBufferSize + 1, // TransimitBufferSize + "COM2", // ResourceSource + , // ResourceSourceIndex + , // ResourceUsage + , // DescrpitorName + , // Shared + // VendorData + ) + }) + } + + // UARTx -> COM3: I/O port 0x3E8, IRQ PcdFchUart2Irq + Device (COM3) { + Name (_HID, EISAID ("PNP0501")) + Name (_DDN, "COM3") + Name (_UID, 3) + Method (_STA) { + Store (^^^AL2A.CSTA (_UID), Local0) + Return (Local0) + } + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x03E8, 0x03E8, 0x01, 0x08) + IRQ (Edge, ActiveLow, Shared) {FixedPcdGet8(PcdFchUart2Irq)} + UARTSerialBusV2 (115200, // InitialBaudRate + DataBitsEight, // BitsPerByte + StopBitsOne, // StopBits + 0x00, // LinesInUse + , // IsBigEndian + ParityTypeNone, // Parity + FlowControlNone, // FlowControl + 1, // ReceiveBufferSize + 1, // TransimitBufferSize + "COM3", // ResourceSource + , // ResourceSourceIndex + , // ResourceUsage + , // DescrpitorName + , // Shared + // VendorData + ) + }) + } + + // UARTx -> COM4: I/O port 0x2E8, IRQ PcdFchUart3Irq + Device (COM4) { + Name (_HID, EISAID ("PNP0501")) + Name (_DDN, "COM4") + Name (_UID, 4) + Method (_STA) { + Store (^^^AL2A.CSTA (_UID), Local0) + Return (Local0) + } + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x02E8, 0x02E8, 0x01, 0x08) + IRQ (Edge, ActiveLow, Shared) {FixedPcdGet8(PcdFchUart3Irq)} + UARTSerialBusV2 (115200, // InitialBaudRate + DataBitsEight, // BitsPerByte + StopBitsOne, // StopBits + 0x00, // LinesInUse + , // IsBigEndian + ParityTypeNone, // Parity + FlowControlNone, // FlowControl + 1, // ReceiveBufferSize + 1, // TransimitBufferSize + "COM4", // ResourceSource + , // ResourceSourceIndex + , // ResourceUsage + , // DescrpitorName + , // Shared + // VendorData + ) + }) + } + + Device (DMAC) { + Name (_HID, EISAID ("PNP0200")) + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x0, 0x0, 0x1, 0x10) + IO (Decode16, 0x81, 0x81, 0x1, 0xF) + IO (Decode16, 0xC0, 0xC0, 0x1, 0x20) + DMA (Compatibility, NotBusMaster, Transfer8_16) {4} + }) + } // Device (DMAC) + + Device (RTC) { + Name (_HID, EISAID ("PNP0B00")) + Name (_FIX, Package () {EISAID ("PNP0B00")}) + Name (_CRS, ResourceTemplate () { + IO (Decode16,0x70,0x70,0x01,0x02) + IO (Decode16,0x72,0x72,0x01,0x02) + }) + } // Device (RTC) + + Device (SPKR) { + Name (_HID, EISAID ("PNP0800")) + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x61, 0x61, 0x1, 0x1) + }) + } // Device (SPKR) + + Device (TMR) { + Name (_HID, EISAID ("PNP0100")) + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x40, 0x40, 0x1, 0x4) + }) + } // Device (TMR) + + Device (SYSR) { + Name (_HID, EISAID ("PNP0C02")) + Name (_UID, 1) + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x10, 0x10, 0x1, 0x10) + IO (Decode16, 0x20, 0x20, 0x1, 0x2) + IO (Decode16, 0xA0, 0xA0, 0x1, 0x2) + IO (Decode16, 0x72, 0x72, 0x1, 0x2) + IO (Decode16, 0x80, 0x80, 0x1, 0x1) + IO (Decode16, 0xB0, 0xB0, 0x1, 0x2) + IO (Decode16, 0x92, 0x92, 0x1, 0x1) + IO (Decode16, 0xF0, 0xF0, 0x1, 0x1) + IO (Decode16, 0x400, 0x400, 0x01,0xd0) + IO (Decode16, 0x4D0, 0x4D0, 0x1, 0x2) + IO (Decode16, 0x4D6, 0x4D6, 0x1, 0x1) + IO (Decode16, 0xC00, 0xC00, 0x1, 0x2) + IO (Decode16, 0xC14, 0xC14, 0x1, 0x1) + IO (Decode16, 0xC50, 0xC50, 0x1, 0x3) + IO (Decode16, 0xC6C, 0xC6C, 0x1, 0x1) + IO (Decode16, 0xC6F, 0xC6F, 0x1, 0x1) + IO (Decode16, 0xCD0, 0xCD0, 0x1, 0xc) + }) + } // Device (SYSR) + + Device (SPIR) { // SPI ROM + Name (_HID, EISAID ("PNP0C01")) + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadOnly, + FixedPcdGet32 (PcdFlashAreaBaseAddress), + FixedPcdGet32 (PcdFlashAreaSize) + ) + }) + } // Device (SPIR) + +#if FixedPcdGet8 (PcdIpmiInterfaceType) != 0 + Device (IPMK) { // IPMI KCS Device + Name (_HID, EisaId ("IPI0001")) // _HID: Hardware ID + Name (_STR, Unicode ("IPMI_KCS")) // _STR: Description String + Name (_UID, Zero) // _UID: Unique ID + Name (_IFT, One) // _IFT: IPMI Interface Type + Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings + IO (Decode16, + FixedPcdGet16 (PcdIpmiKcsIoBaseAddress), // Range Minimum + FixedPcdGet16 (PcdIpmiKcsIoBaseAddress), // Range Maximum + 0x00, // Alignment + 0x02 // Length + ) + }) + Method (_SRV, 0, NotSerialized) { // _SRV: IPMI Spec Revision + Return (0x0200) + } + Method (_STA, 0, NotSerialized) { // _STA: Status + If (FixedPcdGet8 (PcdIpmiInterfaceType) == _IFT) { + Return (0x0F) + } + Else { + Return (Zero) + } + } // Method (_STA) + } // Device (IPMK) +#endif + + } // Device (LPC0) +} // Device (PCI0) + + Scope (\_SB.PCI0.RP71) { + Device (XHC0) + { + Name (_ADR, 0x00000004) + Method (_PRW, 0, NotSerialized) + { + Return (GPRW (0x0B, 0x04)) + } + } + } +Scope (\_SB.PCI3.RP71) { + Device (XHC0) + { + Name (_ADR, 0x00000004) + Method (_PRW, 0, NotSerialized) + { + Return (GPRW (0x0B, 0x04)) + } + } + } + + +Scope (_GPE) +{ + Method (_L0B, 0, NotSerialized) // _Lxx: Level-Triggered GPE, xx=0x00-0xFF + { + Notify (\_SB.PCI0.RP71.XHC0, 0x02) // Device Wake + Notify (\_SB.PCI3.RP71.XHC0, 0x02) // Device Wake + } +} diff --git a/Platform/AMD/TurinBoard/Universal/BoardAcpiDxe/Dsdt/Dsdt.asl b/Platform/AMD/TurinBoard/Universal/BoardAcpiDxe/Dsdt/Dsdt.asl new file mode 100644 index 0000000000..a1d5847dce --- /dev/null +++ b/Platform/AMD/TurinBoard/Universal/BoardAcpiDxe/Dsdt/Dsdt.asl @@ -0,0 +1,239 @@ +/***************************************************************************** + * + * Copyright (C) 2023-2024 Advanced Micro Devices, Inc. All rights reserved. + * + *****************************************************************************/ + +DefinitionBlock ( + "DSDT.aml", + "DSDT", + 0x02, + "AMD ", + "AmdTable", + 0x00 +) + +// BEGIN OF ASL SCOPE +{ + Name (\_S0, Package(4) { + 0x00, 0x00, 0x00, 0x00 // PM1a_CNT.SLP_TYP = 0, PM1b_CNT.SLP_TYP = 0 + }) + Name (\_S5, Package(4) { + 0x05, 0x00, 0x00, 0x00 // PM1a_CNT.SLP_TYP = 5, PM1b_CNT.SLP_TYP = 0 + }) + + External (POSS, FieldUnitObj) + External (POSC, FieldUnitObj) + External (SMIR, FieldUnitObj) + External (DSMI, FieldUnitObj) + External (DRPB, FieldUnitObj) + External (DRPA, FieldUnitObj) + External (DIDX, FieldUnitObj) + External (DFIN, FieldUnitObj) + External (DOUT, FieldUnitObj) + External (DRPN, FieldUnitObj) + External (OSMI, FieldUnitObj) + External (ORPB, FieldUnitObj) + External (ORPA, FieldUnitObj) + External (OAG1, FieldUnitObj) + External (HSMI, FieldUnitObj) + External (HRPB, FieldUnitObj) + External (HRPA, FieldUnitObj) + External (HPCK, FieldUnitObj) + External (HPHM, FieldUnitObj) + External (AERM, FieldUnitObj) + + Scope (\_SB) { + Name (SUPP, 0) + Name (CTRL, 0) + Name (SUPC, Zero) + Name (CTRC, Zero) + Name (BUF, Buffer() {0x00, 0x00}) + Method (OSCI, 6, NotSerialized) + { + CreateDWordField (Arg3, 0, CDW1) + // Check for proper UUID + If (LOr(LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")), + // The _OSC interface for a CXL Host Bridge UUID + (LEqual(Arg0, ToUUID("68F2D50B-C469-4D8A-BD3D-941A103FD3FC"))))) + { + // Create DWord-adressable fields from the Capabilities Buffer + CreateDWordField (Arg3, 4, CDW2) + CreateDWordField (Arg3, 8, CDW3) + // Save Capabilities DWord2 & 3 + Store (CDW2, SUPP) + Store (CDW3 ,CTRL) + // Only allow native hot plug control if OS supports: + // \* ASPM + // \* Clock PM + // \* MSI/MSI-X + If (LNotEqual (And (SUPP, 0x16), 0x16)) + { + And (CTRL, 0x1E, CTRL) // Mask bit 0 (and undefined bits) + } + If (LNotEqual (Arg1, One)) + { + // Unknown revision + Or (CDW1, 0x08, CDW1) + } + + If(LAnd(LEqual(HPHM,6), LEqual(AERM,3))) + { + If(LEqual(And(CTRL,0x80), 0x80)) //OS request PCI Express Downstream Port Containment configuration control? + { + If(LEqual(And(CTRL,0x08), 0x08)) //OS request PCI Express Advanced Error Reporting control? + { + Store(0x0F,Local0) + If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + { + Store (Arg5, HRPB) + Store (Arg4, HRPA) + // Trigger OSC SMI + Store (HSMI, SMIR) + } + } Else { + Store (0xDEADBABE, HRPA) + Store (HSMI, SMIR) + } + } Else { + Store (0xDEADBABE, HRPA) + Store (HSMI, SMIR) + } + } + + If(LEqual(Local0,0x0F)) + { + And(CTRL,POSC,CTRL) //Mask undefined bits + Or(CTRL,0x88,CTRL) //Restore the OS requst bit setting + Store(CTRL,POSC) + } Else { + And(CTRL,POSC,CTRL) + } + + If (LNotEqual (CDW3, CTRL)) + { + // Capabilities bits were masked + Or (CDW1, 0x10, CDW1) + } + // Update DWORD3 in the buffer + Store (CTRL, CDW3) + // Update to RASD oreration region. + Store (SUPP, POSS) //Store SUPP (DWORD 2) to Platform RASD + // If CXL Host Bridge + If (LEqual (Arg0, ToUUID ("68F2D50B-C469-4D8A-BD3D-941A103FD3FC"))) { + CreateDWordField (Arg3, 12, CDW4) // CXL Support Field: + CreateDWordField (Arg3, 16, CDW5) // CXL Control Field: + Store(CDW4,SUPC) + Store(CDW5,CTRC) + // + // The firmware clear bit 0 to deny control over CXL Memory CXL + // Error Reporting if bit 0 or 1 are not set + // + // Check bit 0 + // RCD and RCH Port Register Access Supported + // + If (LNotEqual (And (SUPC, 0x01), 0x01)) + { + And (CTRC, 0xFE, CTRC) + } + // + // Check bit 1 + // CXL VH Register Access Supported + // + If (LNotEqual (And (SUPC, 0x02), 0x01)) + { + And (CTRC, 0xFE, CTRC) + } + // Update DWORD5 in the buffer + Store (CTRC, CDW5) + } + Return (Arg3) + } Else { + Or (CDW1, 4, CDW1) // Unrecognized UUID + Return (Arg3) + } + } + + Method (HDSM, 7, Serialized) { + CreateWordField(BUF, 0, SUPF) + Store(0, SUPF) + // check for GUID and revision match + If (LEqual (Arg0, ToUUID("E5C937D0-3553-4D7A-9117-EA4D19C3434D"))) { + If (LEqual(Arg1, 0x05)) { + Store (Arg2, DIDX) + Store (0x00, DFIN) + If (LEqual(Arg2, 0x0C)) { + Store (ObjectType(Arg3), Local0) + If (LEqual (Local0, 4)) { // Arg3 is a package obj + Store (DeRefOf (Index (Arg3, 0)), Local1) + } Else { // Assume Arg3 is an Integer obj + Store (Arg3, Local1) + } + Store (Local1, DFIN) + Store (Arg6, DRPN) + } + Store (Arg4, DRPB) + Store (Arg5, DRPA) + // Trigger EDR DSM SMI + Store (DSMI, SMIR) + // Function 0 + If (LEqual(Arg2, 0)) { + Store(DOUT, SUPF) + Return(BUF) + } + // Functions 0x0C, 0x0D + Return(DOUT) + } + } + // + // The OSPM can request the firmware to determine the optimum QoS Throttling Group (QTG) + // to which a device HDM range should be assigned, based on its performance characteristics. + // The OSPM evaluate this _DSM Function to retrieve QTG recommendations and map the device + // HDM range to an HPA range that is described by a CFMWS entry that follows the + // platform recommendations (CXL Revision 3.1) + // + If (LEqual (Arg0, ToUUID("f365f9a6-a7de-4071-a66a-b40c0b4f8e52"))) { + Name(MQTG, 1) //Max supported QoS Throttling Group (QTG) ID + Name(QTGR, Package(){0,1}) // QoS Throttling Group (QTG) Recommendations + + // + // Revision ID: 1 + // + If (LEqual(Arg1, 1)) + { + // + // Function Index: 01h + // + If (LEqual(Arg2, 1)) + { + // + // Package: Max Supported QTG ID and QTG Recommendations + // + Return + ( + Package(0x02){MQTG, QTGR} + ) + } + } + } + Return(BUF) // Failed + } // end HDSM + + Method (HOST, 4, Serialized) { + // OSPM calls this method after processing ErrorDisconnectRecover notification from firmware + Switch(And(Arg0,0xFF)) { // Mask to retain low byte + Case(0x0F) { // Error Disconnect Recover request + Store (Arg2, ORPB) + Store (Arg3, ORPA) + Store (Arg1, OAG1) + // Trigger EDR OST SMI + Store (OSMI, SMIR) + } // End Case(0xF) + } // End Switch + } // end HOST + + } + + Include ("../../../../../../../AGESA/AgesaModulePkg/Fch/Kunlun/FchKunlunCore/Kunlun/FchBreithorn.asi") + +}// End of ASL File diff --git a/Platform/AMD/TurinBoard/Universal/BoardAcpiDxe/Dsdt/PciSsdt.asl b/Platform/AMD/TurinBoard/Universal/BoardAcpiDxe/Dsdt/PciSsdt.asl new file mode 100644 index 0000000000..ecf0f2320f --- /dev/null +++ b/Platform/AMD/TurinBoard/Universal/BoardAcpiDxe/Dsdt/PciSsdt.asl @@ -0,0 +1,28 @@ +/***************************************************************************** + * + * Copyright (C) 2020-2023 Advanced Micro Devices, Inc. All rights reserved. + * + *****************************************************************************/ + +/* + ACPI FCH device resources +*/ + +DefinitionBlock ( + "PciSsdt.aml", + "SSDT", + 0x02, // SSDT revision. + // A Revision field value greater than or equal to 2 signifies that integers + // declared within the Definition Block are to be evaluated as 64-bit values + "AMD ", // OEM ID (6 byte string) + "AmdTable",// OEM table ID (8 byte string) + 0x00 // OEM version of SSDT table (4 byte Integer) +) + +// BEGIN OF ASL SCOPE +{ + Scope (\_SB) { + Include ("AmdPci.asi") + } +}// End of ASL File + diff --git a/Platform/AMD/TurinBoard/Universal/DfResourcesPei/DfResourcesPei.c b/Platform/AMD/TurinBoard/Universal/DfResourcesPei/DfResourcesPei.c new file mode 100644 index 0000000000..d8e7064f92 --- /dev/null +++ b/Platform/AMD/TurinBoard/Universal/DfResourcesPei/DfResourcesPei.c @@ -0,0 +1,152 @@ +/** @file + + Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved. + +**/ + +#include +#include +#include +#include +#include +#include + +/** + Entry point for Data Fabric Resouces PEIM. + + @param FileHandle Pointer to the FFS file header. + @param PeiServices Pointer to the PEI services table. + + @retval EFI_STATUS EFI_SUCCESS + EFI_STATUS respective failure status. +**/ +EFI_STATUS +EFIAPI +PeiDfResourcesInit ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + FABRIC_RESOURCE_FOR_EACH_RB *FabricResourceForEachRb; + UINT8 SocPresent; + UINT8 RbPerSocketPresent; + UINTN BusLength; + UINT8 i; + UINT8 j; + + DEBUG ((DEBUG_INFO, "Entered - %a\n", __func__)); + Status = (*PeiServices)->AllocatePool ( + PeiServices, + sizeof (FABRIC_RESOURCE_FOR_EACH_RB), + (VOID **)&FabricResourceForEachRb + ); + + if (!EFI_ERROR (Status)) { + SocPresent = (UINT8)FabricTopologyGetNumberOfProcessorsPresent (); + RbPerSocketPresent = (UINT8)FabricTopologyGetNumberOfRootBridgesOnSocket (0); + DEBUG ((DEBUG_INFO, "SoC count - %d\n", SocPresent)); + DEBUG ((DEBUG_INFO, "RB count - %d\n", RbPerSocketPresent * SocPresent)); + + // + // Mapping of resources for 1P system + // + // Logical Socket 0, Rb 0 is Physical Socket0, Rb 4 ---> PCI(0), FabricResourceForEachRb [0][4] + // Logical Socket 0, Rb 1 is Physical Socket0, Rb 7 ---> PCI(1), FabricResourceForEachRb [0][7] + // Logical Socket 0, Rb 2 is Physical Socket0, Rb 6 ---> PCI(2), FabricResourceForEachRb [0][6] + // Logical Socket 0, Rb 3 is Physical Socket0, Rb 5 ---> PCI(3), FabricResourceForEachRb [0][5] + // Logical Socket 0, Rb 4 is Physical Socket0, Rb 3 ---> PCI(4), FabricResourceForEachRb [0][3] + // Logical Socket 0, Rb 5 is Physical Socket0, Rb 2 ---> PCI(5), FabricResourceForEachRb [0][2] + // Logical Socket 0, Rb 6 is Physical Socket0, Rb 1 ---> PCI(6), FabricResourceForEachRb [0][1] + // Logical Socket 0, Rb 7 is Physical Socket0, Rb 0 ---> PCI(7), FabricResourceForEachRb [0][0] + // + + // + // Mapping of resources for 2P system, with 8 root bridges + // + // Logical Socket 0, Rb 0 is Physical Socket0, Rb 2 ---> PCI(0), FabricResourceForEachRb [0][2] + // Logical Socket 0, Rb 1 is Physical Socket0, Rb 3 ---> PCI(1), FabricResourceForEachRb [0][3] + // Logical Socket 0, Rb 2 is Physical Socket0, Rb 1 ---> PCI(2), FabricResourceForEachRb [0][1] + // Logical Socket 0, Rb 3 is Physical Socket0, Rb 0 ---> PCI(3), FabricResourceForEachRb [0][0] + // Logical Socket 1, Rb 0 is Physical Socket1, Rb 2 ---> PCI(4), FabricResourceForEachRb [1][2] + // Logical Socket 1, Rb 1 is Physical Socket1, Rb 3 ---> PCI(5), FabricResourceForEachRb [1][3] + // Logical Socket 1, Rb 2 is Physical Socket1, Rb 1 ---> PCI(6), FabricResourceForEachRb [1][1] + // Logical Socket 1, Rb 3 is Physical Socket1, Rb 0 ---> PCI(7), FabricResourceForEachRb [1][0] + // + + for (i = 0; i < 2; i++) { + for (j = 0; j < 8; j++) { + FabricResourceForEachRb->NonPrefetchableMmioSizeAbove4G[i][j].Size = 0x0; + FabricResourceForEachRb->NonPrefetchableMmioSizeAbove4G[i][j].Alignment = 1; + + FabricResourceForEachRb->PrefetchableMmioSizeAbove4G[i][j].Size = SIZE_64GB; + FabricResourceForEachRb->PrefetchableMmioSizeAbove4G[i][j].Alignment = 1; + + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[i][j].Alignment = 1; + + FabricResourceForEachRb->PrefetchableMmioSizeBelow4G[i][j].Size = SIZE_16MB; + FabricResourceForEachRb->PrefetchableMmioSizeBelow4G[i][j].Alignment = 0xffffff; + } + } + + // Adjust IO SPACE, MAX available size is 64KB + // FabricResourceForEachRb->IO[0][0].Size = SIZE_8KB + SIZE_4KB; + + if (SocPresent == 1) { + FabricResourceForEachRb->IO[0][4].Size = SIZE_8KB; + FabricResourceForEachRb->IO[0][2].Size = SIZE_4KB; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[0][4].Size = SIZE_2MB; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[0][5].Size = SIZE_1MB; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[0][6].Size = SIZE_1MB; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[0][0].Size = SIZE_8MB; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[0][2].Size = SIZE_16MB + SIZE_8MB; + } else { + FabricResourceForEachRb->IO[0][4].Size = SIZE_8KB; + FabricResourceForEachRb->IO[0][2].Size = SIZE_8KB; + FabricResourceForEachRb->IO[0][1].Size = SIZE_4KB; + FabricResourceForEachRb->IO[0][0].Size = SIZE_4KB; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[0][2].Size = SIZE_2MB; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[0][3].Size = SIZE_2MB; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[0][1].Size = SIZE_32MB; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[0][0].Size = SIZE_32MB; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[1][2].Size = SIZE_1MB; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[1][3].Size = SIZE_1MB; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[1][1].Size = SIZE_2MB + SIZE_1MB; + FabricResourceForEachRb->NonPrefetchableMmioSizeBelow4G[1][0].Size = SIZE_1MB; + } + + // Above 4G, PMem + FabricResourceForEachRb->PrefetchableMmioSizeAbove4G[0][0].Size = SIZE_512GB; + FabricResourceForEachRb->PrefetchableMmioSizeAbove4G[0][1].Size = SIZE_512GB; + FabricResourceForEachRb->PrefetchableMmioSizeAbove4G[0][2].Size = SIZE_512GB; + FabricResourceForEachRb->PrefetchableMmioSizeAbove4G[0][3].Size = SIZE_1TB; + + // Below 4G, PMem + FabricResourceForEachRb->PrefetchableMmioSizeBelow4G[0][0].Size = SIZE_256MB + SIZE_32MB; + FabricResourceForEachRb->PrefetchableMmioSizeBelow4G[0][1].Size = SIZE_128MB; + FabricResourceForEachRb->PrefetchableMmioSizeBelow4G[0][2].Size = SIZE_128MB; + FabricResourceForEachRb->PrefetchableMmioSizeBelow4G[0][3].Size = SIZE_128MB; + FabricResourceForEachRb->PrefetchableMmioSizeBelow4G[0][4].Size = SIZE_64MB; + FabricResourceForEachRb->PrefetchableMmioSizeBelow4G[1][0].Size = SIZE_64MB; + FabricResourceForEachRb->PrefetchableMmioSizeBelow4G[1][4].Size = SIZE_64MB; + + // Primary RootBridge 2nd MMIO + // if NonP is 0 and PMem is non-zero, all available size would be assigned to PMem + FabricResourceForEachRb->PrimaryRbSecondNonPrefetchableMmioSizeBelow4G.Size = 0; + FabricResourceForEachRb->PrimaryRbSecondNonPrefetchableMmioSizeBelow4G.Alignment = 1; + FabricResourceForEachRb->PrimaryRbSecondPrefetchableMmioSizeBelow4G.Size = 1; + FabricResourceForEachRb->PrimaryRbSecondPrefetchableMmioSizeBelow4G.Alignment = 1; + + // Program bus numbers based on topology info + BusLength = (UINTN)LShiftU64 (1, (UINTN)(RShiftU64 (AsmReadMsr64 (0xC0010058), 2) & 0xF)); + for (i = 0; i < SocPresent; i++) { + for (j = 0; j < RbPerSocketPresent; j++) { + FabricResourceForEachRb->PciBusNumber[i][j] = (UINT16)(BusLength / (SocPresent * RbPerSocketPresent)); + } + } + + PcdSet64S (PcdAmdFabricResourceDefaultSizePtr, (UINT64)(UINTN)FabricResourceForEachRb); + } + + return Status; +} diff --git a/Platform/AMD/TurinBoard/Universal/DfResourcesPei/DfResourcesPei.inf b/Platform/AMD/TurinBoard/Universal/DfResourcesPei/DfResourcesPei.inf new file mode 100644 index 0000000000..0d05d21a99 --- /dev/null +++ b/Platform/AMD/TurinBoard/Universal/DfResourcesPei/DfResourcesPei.inf @@ -0,0 +1,34 @@ +# +### @file +# Component information file for Pre-defined Data Fabric resources module. +# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved. +# + +[Defines] + INF_VERSION = 1.29 + BASE_NAME = DfResourcesPei + FILE_GUID = A09C83C1-A653-461B-8761-6E91443B9D78 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = PeiDfResourcesInit + +[Sources] + DfResourcesPei.c + +[Packages] + MdePkg/MdePkg.dec + AgesaPkg/AgesaPkg.dec + AgesaModulePkg/AgesaModuleNbioPkg.dec + +[LibraryClasses] + BaseLib + BaseFabricTopologyLib + PcdLib + PeimEntryPoint + PeiServicesLib + +[Pcd] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFabricResourceDefaultSizePtr + +[Depex] + TRUE diff --git a/Platform/AMD/TurinBoard/Universal/FchPlatformInitPei/FchPlatformInit.h b/Platform/AMD/TurinBoard/Universal/FchPlatformInitPei/FchPlatformInit.h new file mode 100644 index 0000000000..4d8425affa --- /dev/null +++ b/Platform/AMD/TurinBoard/Universal/FchPlatformInitPei/FchPlatformInit.h @@ -0,0 +1,22 @@ +/** @file + Header file of AMD FCH platform initialization library. + + Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved. + +**/ + +#ifndef FCH_PLATFORM_INIT_H_ +#define FCH_PLATFORM_INIT_H_ + +#include +#include +#include +#include +#include +#include + +#include + +#define SPI_BASE 0xFEC10000ul + +#endif // FCH_PLATFORM_INIT_H_ diff --git a/Platform/AMD/TurinBoard/Universal/FchPlatformInitPei/FchPlatformInitPei.c b/Platform/AMD/TurinBoard/Universal/FchPlatformInitPei/FchPlatformInitPei.c new file mode 100644 index 0000000000..6a1515958d --- /dev/null +++ b/Platform/AMD/TurinBoard/Universal/FchPlatformInitPei/FchPlatformInitPei.c @@ -0,0 +1,140 @@ +/** @file + FCH initialization hook PEI. + + Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved. + +**/ + +#include +#include +#include "FchPlatformInit.h" + +/** + Enable LPC IO Port for IPMI KCS interface. + +**/ +VOID +EnableLpcWideIoPort2 ( + IN VOID + ) +{ + if (FixedPcdGet8 (PcdIpmiInterfaceType) == IPMIDeviceInfoInterfaceTypeKCS) { + DEBUG ((DEBUG_INFO, "Enabling wide io port 2.\n")); + // + // Pleaser refer AMD PPR Vol 3 for respective Family/Model SoC + // for detail information. + // + + // + // Offset 0x090 (FCH::ITF::LPC::WIDE_IO_2) + // IO_Base_Address_2. 16-bit PCI I/O base address for + // wide generic port range. + // + PciWrite16 ( + PCI_SEGMENT_LIB_ADDRESS ( + 0, + FCH_LPC_BUS, + FCH_LPC_DEV, + FCH_LPC_FUNC, + 0x90 + ), + FixedPcdGet16 (PcdIpmiKcsIoBaseAddress) + ); + + // + // Offset 0x048 (FCH::ITF::LPC::IO_MEM_PORT_DECODE_ENABLE) + // Enables Wide IO port 2 (defined in registers 90/91h) enable. + // + PciWrite8 ( + PCI_SEGMENT_LIB_ADDRESS ( + 0, + FCH_LPC_BUS, + FCH_LPC_DEV, + FCH_LPC_FUNC, + (FCH_LPC_REG48 + 3) + ), + 0x2 + ); + + // + // Offset 0x074 (FCH::ITF::LPC::ALTERNATIVE_WIDE_IO_RANGE_ENABLE) + // Alternative_Wide_Io_2_Range_Enable to I/O address defined in + // reg0x90 and reg0x91. + // + PciWrite8 ( + PCI_SEGMENT_LIB_ADDRESS ( + 0, + FCH_LPC_BUS, + FCH_LPC_DEV, + FCH_LPC_FUNC, + FCH_LPC_REG74 + ), + 0x8 + ); // Enable BIT3 for Alternative_Wide_Io_2_Range_Enable + } +} + +/** + Enable SPI TPM + +**/ +VOID +EnableSpiTpm ( + IN VOID + ) +{ + // Set TPM Decode + PciAndThenOr8 ( + PCI_SEGMENT_LIB_ADDRESS ( + 0, + FCH_LPC_BUS, + FCH_LPC_DEV, + FCH_LPC_FUNC, + FCH_LPC_REG7C + ), + 0xFF, + 0x85 + ); + + // Set RouteTpm2Spi + PciAndThenOr8 ( + PCI_SEGMENT_LIB_ADDRESS ( + 0, + FCH_LPC_BUS, + FCH_LPC_DEV, + FCH_LPC_FUNC, + FCH_LPC_REGA0 + ), + 0xFF, + 0x08 + ); + + // Set AGPIO76 As SPI_TPM_CS_L + MmioWrite8 ( + ACPI_MMIO_BASE + IOMUX_BASE + 0x4C, + ((MmioRead8 (ACPI_MMIO_BASE + IOMUX_BASE + 0x4C) & 0xFF) | 0x01) + ); +} + +/** + Entry point for FCH intialization PEIM + + @param FileHandle Pointer to the FFS file header. + @param PeiServices Pointer to the PEI services table. + + @retval EFI_STATUS EFI_SUCCESS + EFI_STATUS respective failure status. +**/ +EFI_STATUS +EFIAPI +FchInitEntry ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + DEBUG ((DEBUG_INFO, "Entered %a Platform FCH initialization.\n", __func__)); + + EnableLpcWideIoPort2 (); + EnableSpiTpm (); + return EFI_SUCCESS; +} diff --git a/Platform/AMD/TurinBoard/Universal/FchPlatformInitPei/FchPlatformInitPei.inf b/Platform/AMD/TurinBoard/Universal/FchPlatformInitPei/FchPlatformInitPei.inf new file mode 100644 index 0000000000..f10c9ed9c3 --- /dev/null +++ b/Platform/AMD/TurinBoard/Universal/FchPlatformInitPei/FchPlatformInitPei.inf @@ -0,0 +1,38 @@ +## @file +# INF file of AMD FCH initialization hook PEI library +# +# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved. +# +## + +[Defines] + INF_VERSION = 1.29 + BASE_NAME = FchPLatformInitPei + FILE_GUID = 520A04A3-1BAB-4E24-AF12-859F5D632B58 + MODULE_TYPE = PEIM + ENTRY_POINT = FchInitEntry + +[Sources] + FchPlatformInitPei.c + FchPlatformInit.h + +[Packages] + AgesaModulePkg/AgesaModuleFchPkg.dec + AmdPlatformPkg/AmdPlatformPkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + DebugLib + IoLib + PcdLib + PciLib + PeimEntryPoint + +[Pcd] + gEfiAmdAgesaModulePkgTokenSpaceGuid.PcdLpcEnable + gAmdPlatformPkgTokenSpaceGuid.PcdIpmiInterfaceType + gEfiMdePkgTokenSpaceGuid.PcdIpmiKcsIoBaseAddress + +[Depex] + TRUE + diff --git a/Platform/AMD/TurinBoard/VolcanoBoardPkg/Include/Dsc/Smbios.dsc b/Platform/AMD/TurinBoard/VolcanoBoardPkg/Include/Dsc/Smbios.dsc new file mode 100644 index 0000000000..d6822b7fc7 --- /dev/null +++ b/Platform/AMD/TurinBoard/VolcanoBoardPkg/Include/Dsc/Smbios.dsc @@ -0,0 +1,243 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All rights reserved. +#; +#;****************************************************************************** +# +## @file +# Smbios Platform description. +# +## + +[PcdsFixedAtBuild] + #**************************************************************************** + # COMMON SMBIOS + #**************************************************************************** + # + # IPMI Interface Type + # + # 0 - Unknown + # 1 - KCS + # 2 - SMIC + # 3 - BT + # 4 - SSIF + gAmdPlatformPkgTokenSpaceGuid.PcdIpmiInterfaceType|1 + + # SMBIOS Type 4 Processor Information + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSerialNumberSocket0|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSerialNumberSocket1|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosAssetTagSocket0|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosAssetTagSocket1|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosPartNumberSocket0|"To be filled by O.E.M." + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosPartNumberSocket1|"To be filled by O.E.M." + + # AMD SMBIOS Type 8 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8Number|14 + + # AMD SMBIOS Type 9 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics1.Provides33Volts|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType9SlotCharacteristics2.BifurcationSupported|1 + + # Port #0 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.IntDesiganatorStr|"J145" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[0].DesinatorStr.ExtDesiganatorStr|"USB3" + + # Port #1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.ExternalConnectorType|PortConnectorTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].Type8Data.PortType|PortTypeUsb + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.IntDesiganatorStr|"J3" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[1].DesinatorStr.ExtDesiganatorStr|"USB3" + + # Port #2 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.ExternalConnectorType|PortConnectorTypeRJ45 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].Type8Data.PortType|PortTypeNetworkPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].DesinatorStr.IntDesiganatorStr|"J15" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[7].DesinatorStr.ExtDesiganatorStr|"MGMT RJ45 Port" + + # Port #3 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalReferenceDesignator|0x02 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalConnectorType|PortConnectorTypeDB15Female + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.PortType|PortTypeVideoPort + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.IntDesiganatorStr|"J129" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.ExtDesiganatorStr|"VGA" + + # Port #4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.InternalConnectorType|PortConnectorTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalReferenceDesignator|0x0 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].Type8Data.PortType|PortTypeSerial16550ACompatible + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.IntDesiganatorStr|"J133 - Serial Port Header" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[4].DesinatorStr.ExtDesiganatorStr|{0} + + # Port #5 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalConnectorType|PortConnectorTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalReferenceDesignator|0x0 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.PortType|PortTypeOther + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.IntDesiganatorStr|"J5 - LPC Header" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.ExtDesiganatorStr|{0} + + # Port #6 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.IntDesiganatorStr|"SATA8 - SATA Port 8" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.ExtDesiganatorStr|{0} + + # Port #7 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.IntDesiganatorStr|"SATA9 - SATA Port 9" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.ExtDesiganatorStr|{0} + + # Port #8 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.IntDesiganatorStr|"SATA10 - SATA Port 10" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.ExtDesiganatorStr|{0} + + # Port #9 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.IntDesiganatorStr|"SATA11 - SATA Port 11" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.ExtDesiganatorStr|{0} + + # Port #10 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.IntDesiganatorStr|"SATA12 - SATA Port 12" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.ExtDesiganatorStr|{0} + + # Port #11 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.IntDesiganatorStr|"SATA13 - SATA Port 13" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.ExtDesiganatorStr|{0} + + # Port #12 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.IntDesiganatorStr|"SATA14 - SATA Port 14" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.ExtDesiganatorStr|{0} + + # Port #13 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalReferenceDesignator|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.InternalConnectorType|PortConnectorTypeSasSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalReferenceDesignator|0x00 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.ExternalConnectorType|PortConnectorTypeNone + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].Type8Data.PortType|PortTypeSata + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.IntDesiganatorStr|"SATA15 - SATA Port 15" + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType8.SmbiosPortConnectorRecords[5].DesinatorStr.ExtDesiganatorStr|{0} + + # AMD SMBIOS Type 41 record + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41Number|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].ReferenceDesignation|0x01 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceType|OnBoardDeviceExtendedTypeEthernet + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceEnabled|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceTypeInstance|1 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].VendorId|0x14E4 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].DeviceId|0x165F + gAmdPlatformPkgTokenSpaceGuid.PcdAmdSmbiosType41.SmbiosOnboardDevExtInfos[0].RefDesignationStr|"Onboard Ethernet" + +[PcdsDynamicDefault] + #**************************************************************************** + # BASIC SMBIOS + #**************************************************************************** + # + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0305 + # SMBIOS Type 0 BIOS Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosReleaseDate|"$(RELEASE_DATE)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosVersion|"$(FIRMWARE_VERSION_STR)" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.SystemBiosMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMajorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.EmbeddedControllerFirmwareMinorRelease|0xFF + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Size|32 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.ExtendedBiosSize.Unit|0x00 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PlugAndPlayIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.EDDSpecificationIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy525_12IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_720IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Floppy35_288IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrintScreenIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.Keyboard8042IsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.SerialIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.PrinterIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BiosCharacteristics.CgaMonoIsSupported|0 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[0]|0x01 + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0BiosInformation.BIOSCharacteristicsExtensionBytes[1]|0x0C + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringVendor|"AMD Corporation" + + # SMBIOS Type 1 System Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringFamily|$(AMD_PROCESSOR) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1SystemInformation.Uuid|{GUID("5879B2F2-E823-4C6D-830A-6F52935EA561")} + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringSerialNumber|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringVersion|"To be filled by O.E.M." + + # SMBIOS Type 2 Baseboard Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringProductName|$(PLATFORM_CRB) + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringVersion|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringAssetTag|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringLocationInChassis|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringSerialNumber|"To be filled by O.E.M." + + # SMBIOS Type 3 System Enclosure Information Strings + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringManufacturer|"AMD Corporation" + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringVersion|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringAssetTag|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSKUNumber|"To be filled by O.E.M." + gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosType3StringSerialNumber|"To be filled by O.E.M." + + # SMBIOS Type 11 OEM Strings + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStringsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType11OemStrings|{"To be filled by O.E.M."} + + # SMBIOS Type 12 System Configuration Options + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptionsCount|1 + gAmdPlatformPkgTokenSpaceGuid.PcdType12SystemCfgOptions|{"To be filled by O.E.M."} + +[Components.X64] + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + SystemInformation/SmbiosFeaturePkg/SmbiosBasicDxe/SmbiosBasicDxe.inf + AmdPlatformPkg/Universal/SmbiosCommonDxe/SmbiosCommonDxe.inf { + + PciSegmentLib|MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.inf + PciSegmentInfoLib|AgesaPkg/Addendum/PciSegments/PciExpressPciSegmentInfoLib/PciExpressPciSegmentInfoLib.inf + } diff --git a/Platform/AMD/TurinBoard/VolcanoBoardPkg/Project.dsc b/Platform/AMD/TurinBoard/VolcanoBoardPkg/Project.dsc new file mode 100644 index 0000000000..ab4db828d5 --- /dev/null +++ b/Platform/AMD/TurinBoard/VolcanoBoardPkg/Project.dsc @@ -0,0 +1,195 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All rights reserved. +#; +#;****************************************************************************** + +# ***************************************************************************** +# Defines passed into build +# RELEASE_DATE +# FIRMWARE_REVISION_NUM +# FIRMWARE_VERSION_STR +# PLATFORM_CRB +# AMD_PROCESSOR +# CBS_INCLUDE +# INTERNAL_IDS +# SIMNOW_SUPPORT +# EMULATION +# ***************************************************************************** + +[Defines] +!ifndef AMD_PROCESSOR + AMD_PROCESSOR = Turin +!endif + PROCESSOR_PATH = $(AMD_PROCESSOR)Board +!ifndef PLATFORM_CRB + PLATFORM_CRB = Volcano +!endif + PLATFORM_NAME = $(PLATFORM_CRB)BoardPkg + PLATFORM_GUID = C3851035-490E-485E-8941-DFFDBDB45F69 + PLATFORM_VERSION = 0.01 + DSC_SPECIFICATION = 1.30 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)_$(AMD_PROCESSOR) +!ifdef $(INTERNAL_IDS) + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_INTERNAL +!else + OUTPUT_DIRECTORY = $(OUTPUT_DIRECTORY)_EXTERNAL +!endif + SUPPORTED_ARCHITECTURES = IA32|X64 + BUILD_TARGETS = DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = $(PLATFORM_NAME)/Project.fdf + + DEFINE PEI_ARCH = IA32 + DEFINE DXE_ARCH = X64 + PREBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py prebuild" + POSTBUILD = "python PlatformTools/Server/support/prepostbuild_launcher.py postbuild" + + # + # Platform On/Off features are defined here + # + DEFINE SOURCE_DEBUG_ENABLE = FALSE + DEFINE DEBUG_DISPATCH_ENABLE = FALSE + DEFINE DISABLE_SMT = FALSE + + # AGESA Defines to skip Cf9Reset Driver + DEFINE AMD_RESET_DXE_DRIVER_SUPPORT_DISABLED = TRUE + + DEFINE PLATFORM_CRB_TABLE_ID = "VOLCANO " + + DEFINE SATA_OVERRIDE = TRUE + + !ifdef $(INTERNAL_IDS) + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = FALSE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = TRUE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE + !else + # AGESA debug output + DEFINE IDS_DEBUG_ENABLE = FALSE + # Non-runtime UEFI output + DEFINE LOGGING_ENABLE = FALSE + # SMM and Dxe runtime debug message control + DEFINE RUNTIME_LOGGING_ENABLE = FALSE + !endif + + # Predefined Fabric Resource + DEFINE PREDEFINED_FABRIC_RESOURCES = TRUE + # use emulated variable store instead of real spirom + # use this flag for early brigup when there is issue + # with accessing the spirom + DEFINE USE_EMULATED_VARIABLE_STORE = $(EMULATION) + + # Multisegment support + DEFINE PCIE_MULTI_SEGMENT = TRUE + + # EDK2 components are starting to use PLATFORMX64_ENABLE in their include + # DSC/FDF files + DEFINE PLATFORMX64_ENABLE = TRUE + + # MACRO used by AGESA FCH include DSC/FDF to exclude legacy CSM support + DEFINE AMD_CSM_SUPPORT_DISABLED = TRUE + + DEFINE ROM3_1TB_REMAP = FALSE + + !ifndef SOC_FAMILY_2 + DEFINE SOC_FAMILY_2 = $(SOC_FAMILY) + !endif + !ifndef SOC_SKU_2 + DEFINE SOC_SKU_2 = $(SOC_SKU) + !endif + !ifndef SOC2_2 + DEFINE SOC2_2 = $(SOC2) + !endif + !ifndef SOC_SKU_TITLE + DEFINE SOC_SKU_TITLE = Brh + !endif + + # Console settings + # + # Background info: + # As per Turin PPR vol7 17.4.10 UART Registers + # There are 3 physical UARTS available for SBIOS. + # UART0 supports flow controls. + # UART1 doest support flow controls. + # UART2 is disabled by AGESA/CPM to enable flow control for UART0. + # Hence only two UARTs (UART0 and UART1) are available for SBIOS. + # MMIO addresses for 4 UART as FEDCF000,FEDCE000,FEDCA000 and FEDC9000 + # + # Platform settings: + # AGESA/CPM enables UART0 and UART1 by setting BIT11 and BIT12 of FchRTDeviceEnableMap. + # If SBIOS wants to use MMIO space then above mentioned reserved MMIO can be used. + # If SBIOS wants UART in legacy mode(to use 0x3F8/0x2F8) then need to set below PCD for + # for respective UART. + # FchUart0LegacyEnable, FchUart1LegacyEnable and FchUart2LegacyEnable + # + # SERIAL_PORT Options: + # NONE + # FCH_MMIO UART0, MMIO + # FCH_IO UART0, 0x3F8 + # BMC_SOL UART1, MMIO + # BMC_SOL_IO UART1, 0x3F8 + # BMC_ESPI eSPI0, 0x3F8 + DEFINE SERIAL_PORT = "BMC_SOL_IO" + DEFINE ESPI_UART = FALSE # Define ESPI_UART to modify APCB tokens + + # + # Simnow Options + # + DEFINE SIMNOW_PORT80_DEBUG = $(EMULATION) + DEFINE USB_SUPPORT = TRUE + DEFINE SATA_SUPPORT = TRUE + DEFINE NVME_SUPPORT = TRUE + + # + # Check undefined variables + # +!ifndef RELEASE_DATE + RELEASE_DATE = 01/01/2023 +!endif +!ifndef FIRMWARE_VERSION_STR + FIRMWARE_VERSION_STR = NONE +!endif +!ifndef FIRMWARE_REVISION_NUM + FIRMWARE_REVISION_NUM = 0x00000000 +!endif + +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +# Add platform includes AGESA, CPM etc +!include $(PROCESSOR_PATH)/Include/Dsc/Platform.inc.dsc + +# Board specific SMBIOS defines +!include $(PLATFORM_NAME)/Include/Dsc/Smbios.dsc + +# Platform Common PCDs +!include $(PROCESSOR_PATH)/Include/Dsc/PlatformCommonPcd.dsc.inc + +# Board specific PCDs +[PcdsFixedAtBuild] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSocketDesignationSocket0|"A0" + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdSmbiosSocketDesignationSocket1|"A1" + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x204f4e41434C4F56 # "VOLCANO " + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|768 + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|2 + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|768 + gAmdPlatformPkgTokenSpaceGuid.PcdAmdEspiOffset|0x20000 + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicCount|16 + +[PcdsDynamicDefault] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdEarlyBmcLinkLaneNum|135 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdCfgPlatformPPT|500 + gEfiAmdAgesaPkgTokenSpaceGuid.PcdSataEnable2|0x30 + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0xFFFF + +####################################### +# Library Includes +####################################### +!include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc +!include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc +!include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc +# do not change the order of include +!include $(PROCESSOR_PATH)/Include/Dsc/ProjectCommon.inc.dsc diff --git a/Platform/AMD/TurinBoard/VolcanoBoardPkg/Project.fdf b/Platform/AMD/TurinBoard/VolcanoBoardPkg/Project.fdf new file mode 100644 index 0000000000..8e53006685 --- /dev/null +++ b/Platform/AMD/TurinBoard/VolcanoBoardPkg/Project.fdf @@ -0,0 +1,36 @@ +#;***************************************************************************** +#; Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All rights reserved. +#; +#;***************************************************************************** + + +############################################################################## +# +# Turin reference board - 2 SPI FLash devices accessible by x86 (selected by DIP-switch): +# 1) 32MB Flash with 10-pin header next to the VGA connector. +# 2) 64MB Flash with 10-pin header at 90-degrees from VGA connector, and also accessible by the BMC. +# +############################################################################## + +[Defines] + # Platform.inc.fdf can contain custom DEFINES, consumed by FlashmMapInclude.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/Platform.inc.fdf + !include $(PROCESSOR_PATH)/Include/Fdf/FlashMapInclude.fdf + + DEFINE EFS_ESPI_BYTE0 = 0xFF + DEFINE EFS_ESPI_BYTE1 = 0x0E +#----------------------------------------------------------- +# End of [Defines] section +#----------------------------------------------------------- + +!include $(PROCESSOR_PATH)/Include/Fdf/ProjectCommon.inc.fdf + +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ +!include MinPlatformPkg/Include/Fdf/RuleInclude.fdf