diff --git a/Platform/Bosc/XiangshanSeriesPkg/NanhuDev/NanhuDev.dsc b/Platform/Bosc/XiangshanSeriesPkg/NanhuDev/NanhuDev.dsc index 02cd011e7a..5af7fc7524 100644 --- a/Platform/Bosc/XiangshanSeriesPkg/NanhuDev/NanhuDev.dsc +++ b/Platform/Bosc/XiangshanSeriesPkg/NanhuDev/NanhuDev.dsc @@ -241,6 +241,7 @@ PlatformUpdateProgressLib|Platform/RISC-V/PlatformPkg/Library/PlatformUpdateProgressLibNull/PlatformUpdateProgressLibNull.inf # Pci dependencies PciSegmentLib|Silicon/Bosc/NanHuPkg/Library/PciSegmentLib/PciSegmentLib.inf + PciHostBridgeLib|Silicon/Bosc/NanHuPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf [LibraryClasses.common.UEFI_APPLICATION] PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf @@ -264,6 +265,24 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE [PcdsFixedAtBuild] + # + # XILINX PCI Root Complex + # + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x40000000 + gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|FALSE + gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation|0x0 + gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation|0x50000000 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciConfigBase|0x40000000 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciConfigSize|0x10000000 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciBusMin|0 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciBusMax|255 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciIoBase|0x00000 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciIoSize|0xf00000 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciMmio32Base|0x50000000 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciMmio32Size|0x10000000 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciMmio64Base|0x1000000000 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciMmio64Size|0x0000000000 + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeMemorySize|1 @@ -429,11 +448,13 @@ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf !endif - UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf + UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf { PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf } + MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf MdeModulePkg/Universal/Metronome/Metronome.inf MdeModulePkg/Universal/BdsDxe/BdsDxe.inf MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf { diff --git a/Platform/Bosc/XiangshanSeriesPkg/NanhuDev/NanhuDev.fdf b/Platform/Bosc/XiangshanSeriesPkg/NanhuDev/NanhuDev.fdf index 1236c313af..1956d9b9c8 100644 --- a/Platform/Bosc/XiangshanSeriesPkg/NanhuDev/NanhuDev.fdf +++ b/Platform/Bosc/XiangshanSeriesPkg/NanhuDev/NanhuDev.fdf @@ -69,8 +69,6 @@ INF OvmfPkg/Fdt/HighMemDxe/HighMemDxe.inf INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf -INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf -INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf INF MdeModulePkg/Universal/Metronome/Metronome.inf INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf @@ -127,6 +125,13 @@ INF ShellPkg/Application/Shell/Shell.inf !include NetworkPkg/Network.fdf.inc +# +# PCI Support +# +INF UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf +INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf +INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + # # Usb Support # diff --git a/Silicon/Bosc/NanHuPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Silicon/Bosc/NanHuPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c new file mode 100644 index 0000000000..56bc7dbe56 --- /dev/null +++ b/Silicon/Bosc/NanHuPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c @@ -0,0 +1,178 @@ +/** @file + PCI host bridge library instance for NanHuDev SOC. + + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
+ Copyright (c) 2024, Bosc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include + +#include "PciHostBridgeLib.h" + +#pragma pack(1) + +typedef struct { + PCI_DEVICE_PATH PciDevicePath; + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; + +#pragma pack () + +STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = { + { + PCI_DEVICE_PATH_NODE(0, 0), + END_DEVICE_PATH_DEF + }, +}; + +GLOBAL_REMOVE_IF_UNREFERENCED +CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = { + L"Mem", L"I/O", L"Bus" +}; + +STATIC PCI_ROOT_BRIDGE mRootBridge = { + 0, // Segment + 0, // Supports + 0, // Attributes + FALSE, // DmaAbove4G + FALSE, // NoExtendedConfigSpace + FALSE, // ResourceAssigned + 0, // AllocationAttributes + { + // Bus + FixedPcdGet32 (PcdPciBusMin), + FixedPcdGet32 (PcdPciBusMax) + }, { + // Io + FixedPcdGet64 (PcdPciIoBase), + FixedPcdGet64 (PcdPciIoBase) + FixedPcdGet64 (PcdPciIoSize) - 1 + }, { + // Mem + FixedPcdGet32 (PcdPciMmio32Base), + FixedPcdGet32 (PcdPciMmio32Base) + (FixedPcdGet32 (PcdPciMmio32Size) - 1) + //0x7FFFFFFF + }, { + // MemAbove4G + FixedPcdGet64 (PcdPciMmio64Base), + FixedPcdGet64 (PcdPciMmio64Base) + FixedPcdGet64 (PcdPciMmio64Size) - 1 + }, { + // PMem + MAX_UINT64, + 0 + }, { + // PMemAbove4G + MAX_UINT64, + 0 + }, + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath +}; + +/** + Return all the root bridge instances in an array. + + @param[out] Count Return the count of root bridge instances. + + @return All the root bridge instances in an array. + The array should be passed into PciHostBridgeFreeRootBridges() + when it's not used. + +**/ +PCI_ROOT_BRIDGE * +EFIAPI +PciHostBridgeGetRootBridges ( + OUT UINTN *Count + ) +{ + /* Enable the Bridge enable bit */ + UINT64 PciConfigBase = FixedPcdGet64 (PcdPciConfigBase); + UINT32 Rpsc = MmioRead32 (PciConfigBase + XILINX_PCIE_REG_RPSC); + MmioWrite32 (PciConfigBase + XILINX_PCIE_REG_RPSC, Rpsc | XILINX_PCIE_REG_RPSC_BEN); + DEBUG ((DEBUG_INFO, "%a: PciConfigBase:0x%x Rpsc:0x%x\n", __func__, PciConfigBase)); + DEBUG ((DEBUG_INFO, "%a: Rpsc:0x%x \n", __func__, Rpsc)); + + *Count = 1; + return &mRootBridge; +} + + +/** + Free the root bridge instances array returned from PciHostBridgeGetRootBridges(). + + @param[in] Bridges The root bridge instances array. + @param[in] Count The count of the array. + +**/ +VOID +EFIAPI +PciHostBridgeFreeRootBridges ( + IN PCI_ROOT_BRIDGE *Bridges, + IN UINTN Count + ) +{ + +} + + +/** + Inform the platform that the resource conflict happens. + + @param[in] HostBridgeHandle Handle of the Host Bridge. + @param[in] Configuration Pointer to PCI I/O and PCI memory resource + descriptors. The Configuration contains the resources + for all the root bridges. The resource for each root + bridge is terminated with END descriptor and an + additional END is appended indicating the end of the + entire resources. The resource descriptor field + values follow the description in + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL + SubmitResources(). + +**/ +VOID +EFIAPI +PciHostBridgeResourceConflict ( + IN EFI_HANDLE HostBridgeHandle, + IN VOID *Configuration + ) +{ + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor; + BOOLEAN IsPrefetchable; + + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration; + while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) { + for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) { + ASSERT (Descriptor->ResType < + ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr)); + DEBUG ((DEBUG_INFO, " %s: Length/Alignment = 0x%lx / 0x%lx\n", + mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType], + Descriptor->AddrLen, + Descriptor->AddrRangeMax + )); + if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) { + + IsPrefetchable = (Descriptor->SpecificFlag & + EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE) != 0; + + DEBUG ((DEBUG_INFO, " Granularity/SpecificFlag = %ld / %02x%s\n", + Descriptor->AddrSpaceGranularity, + Descriptor->SpecificFlag, + (IsPrefetchable) ? L" (Prefetchable)" : L"" + )); + } + } + // + // Skip the end descriptor for root bridge + // + ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR); + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) ( + (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1 + ); + } +} diff --git a/Silicon/Bosc/NanHuPkg/Library/PciHostBridgeLib/PciHostBridgeLib.h b/Silicon/Bosc/NanHuPkg/Library/PciHostBridgeLib/PciHostBridgeLib.h new file mode 100644 index 0000000000..b9bceffc34 --- /dev/null +++ b/Silicon/Bosc/NanHuPkg/Library/PciHostBridgeLib/PciHostBridgeLib.h @@ -0,0 +1,37 @@ +/** @file + Main Header file for the PciHostBridgeLib + + Copyright (c) 2024, Bosc. All rights reserved.
ved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef __PCIHOSTBRIDGELIB_H +#define __PCIHOSTBRIDGELIB_H + +/* Register definitions */ +#define XILINX_PCIE_REG_RPSC (0x00000148) + +/* Root Port Status/control Register definitions */ +#define XILINX_PCIE_REG_RPSC_BEN BIT(0) + +#define END_DEVICE_PATH_DEF { END_DEVICE_PATH_TYPE, \ + END_ENTIRE_DEVICE_PATH_SUBTYPE, \ + { END_DEVICE_PATH_LENGTH, 0 } \ + } + +#define PCI_DEVICE_PATH_NODE(Func, Dev) \ + { \ + { \ + HARDWARE_DEVICE_PATH, \ + HW_PCI_DP, \ + { \ + (UINT8) (sizeof (PCI_DEVICE_PATH)), \ + (UINT8) ((sizeof (PCI_DEVICE_PATH)) >> 8) \ + } \ + }, \ + (Func), \ + (Dev) \ + } + +#endif diff --git a/Silicon/Bosc/NanHuPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Silicon/Bosc/NanHuPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf new file mode 100644 index 0000000000..819662c0b0 --- /dev/null +++ b/Silicon/Bosc/NanHuPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf @@ -0,0 +1,49 @@ +#/** @file +# PCI Host Bridge Library instance for Bosc SOC. +# +# Copyright (c) 2024, Bosc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001b + BASE_NAME = PciHostBridgeLib + FILE_GUID = 7F418E45-0127-454E-9CBB-F5FCF237E383 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = PciHostBridgeLib|DXE_DRIVER + +# +# The following information is for reference only and not required by the build +# tools. +# +# VALID_ARCHITECTURES = RISCV64 +# + +[Sources] + PciHostBridgeLib.h + PciHostBridgeLib.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec + +[LibraryClasses] + DebugLib + +[Guids] + +[FixedPcd] + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciConfigBase + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciConfigSize + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciBusMin + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciBusMax + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciIoBase + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciIoSize + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciMmio32Base + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciMmio32Size + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciMmio64Base + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciMmio64Size